WO2012112666A2

WO2012112666A2 - Light emitting semiconductor device having multi-level substrate

Info

Publication number: WO2012112666A2
Application number: PCT/US2012/025214
Authority: WO
Inventors: Philip E. Watson; Yarn Chee Poon; Ravi Palaniswamy; Jesudoss AROKIARAJ; Alejandro Aldrin Agcaoili II NARAG; Kim Leong Tan; Andrew J. Ouderkirk; Douglas S. Parker; Justine A. Mooney
Original assignee: 3M Innovate Properties Company
Priority date: 2011-02-18
Filing date: 2012-02-15
Publication date: 2012-08-23
Also published as: WO2012112666A3; TW201242072A

Abstract

Provided is a light emitting semiconductor device that includes a substrate having a first area having a first height and a second area having a second height different from the first height, wherein the first area supports at least a first light emitting semiconductor (LES) and the second area supports at least a second light emitting semiconductor (LES).

Description

LIGHT EMITTING SEMICONDUCTOR DEVICE HAVING MULTI-LEVEL

SUBSTRATE

RELATED APPLICATIONS

The present application claims priority to U.S. Provisional Patent Application Serial No. 61/444,348, filed on February 18, 2011, and U.S. Provisional Patent Application Serial No. 61/577,733, filed on December 20, 2011, which is hereby incorporated by reference in its entirety.

BACKGROUND

Conventional light emitting semi-conductors (LESs), including light emitting diodes (LEDs), laser diodes, and LES devices (LESDs), and packages containing LESDs have several drawbacks. High power LESDs generate a substantial amount of heat that must be managed. Thermal management of the LESDs includes issues arising from heat dissipation and thermal stresses, which is currently a key factor in limiting the performances of light-emitting diodes.

In general, LESDs are commonly prone to damage caused by buildup of heat generated from within the devices, as well as heat from sunlight when they are used in outside lighting applications. Excessive heat buildup can cause deterioration of the materials used in the LES devices, such as encapsulants for the LESDs. When LESDs are attached to high thermal resistance substrates such as FR4 flexible-circuit laminates that often include other electrical components, the heat dissipation problems are greatly increased.

Additionally, conventional LESDs and packages tend to be thick, which limits their uses in low form factor applications. Consequently, there is a continuing need to improve the design of flexible LESDs and packages to improve their thermal dissipation properties, as well as to allow for their use in low form factors.

SUMMARY

At least one aspect of the present disclosure provides a cost-effective thermal management solution for current and future high power LESD constructions through a robust flexible LESD construction. The ability to dissipate large amounts of heat is needed for the operation of high power LESD arrays. According to at least one embodiment of the present disclosure, heat dissipation can be managed by integrating the LESDs into a system having a flexible dielectric layer with LESDs disposed on one major surface and a thermally conductive material disposed on, or adjacent to, a second major surface of the dielectric layer. To accomplish good heat management, the LESDs can be positioned at different distances from the thermally conductive layer, based, for example, on their heat dissipation requirements. This is accomplished by controlling the thickness of the insulation (dielectric) layer between each type of LESD and the thermally conductive layer.

In at least one embodiment of the present disclosure, to achieve the desired positioning of one or more LESDs in relation to the conductive material, controlled etching of areas of the dielectric layer to one or more desired thicknesses is performed.

Recessed areas including large areas or small cavities can be etched or can be formed by other suitable methods including microreplication. For purposes of the present disclosure, a recessed area may be in the form of a small cavity in which only one or a few LESDs can be placed, or a large depression in which a plurality of LESDs can be placed.

In some embodiments, creation of the recessed areas in which some of the LESDs are placed, may increase the amount of insulation (dielectric) material between adjacent LESDs when at least one LESD is located in a recess and one is not, or when LESDs are placed in recesses of different depths. Because of this added insulation, the LESDs may be placed closer in the X and Y direction than they could be if they sat on the same planar surface.

In some embodiments, etching of the dielectric layer provides the additional advantages of creating recessed areas with slanted side walls which can be coated with a reflecting material to provide enhanced light efficiency. Additionally, in some embodiments, because at least a portion of the LESDs sit below the surface of the dielectric layer, the flexible LESD of the present disclosure has a lower profile than standard LESDs, which makes it well-suited for low form factor applications. Further, in some embodiments, solder can be retained in a recessed area and such implementations avoid solder spreading when it is subjected to solder re flow process for die attachment.

At least one aspect of the present disclosure features an illumination system that includes an optical collection system, a first light emitting semiconductor device (LESD) having a first height, the first LESD facing the optical collection system, a second light emitting

semiconductor device (LESD) having a second height different from the first height, the second LESD facing the optical collection system, and a substrate. The substrate has a first area and a second area, wherein the first area supports at least the first LESD and the second area supports at least the second LESD, and the first area has a first area height different from a second area height of the second area. At least one aspect of the present disclosure features an illumination assembly that includes a first light emitting semiconductor device (LESD) having a first height, a second light emitting semiconductor device (LESD) having a second height different from the first height, and a dielectric layer having a first area and a second area. The first area supports at least the first LESD and the second area supports at least the second LESD. The first area has a first area height different from a second area height of the second area such that the first LESD and the second LESD have a generally planar emission surface.

At least one aspect of the present disclosure features a method including the steps of:

providing an optical collection system; providing a substrate having first and second major surfaces and having a first area having a first height; creating at least one recessed second area on the first major surface such that the second area has a second height that is less than the first height; and placing at least one light emitting semiconductor on each of the first and second areas facing the optical collection system.

At least one aspect of the present disclosure features an article including a flexible dielectric layer having first and second major surfaces, the first major surface having at least one first area having a first height and at least one second area having a second height different from the first height, wherein the first area supports at least a first light emitting semiconductor device (LESD) and the second area supports at least a second light emitting semiconductor device (LESD); and a first conductive layer on the first major surface of the dielectric layer.

At least one aspect of the present disclosure features a method of making a flexible light emitting device that includes the steps of: providing a flexible dielectric material having first and second major surfaces and having a first area having a first height; creating at least one recessed second area on the first major surface having a second height that is less than the first height; creating a conductive layer on the first major surface of the dielectric material; and placing at least one LESD on each of the first and second areas.

As used in this application:

"LES" means light emitting semiconductor(s), including light emitting diodes and laser diodes;

"LESD" means light emitting semiconductor devices, including light emitting diode device(s) and laser diode device(s). An LESD may be a bare LES die construction, a complete packaged LES construction, or an intermediate LES construction including more than the bare die, but less than all the components for a complete LES package, such that the terms LES and LESD may be used interchangeably in some situations and refer to one or all of the different LES constructions;

"flexible LES device" or "flexible LESD" typically refers to the flexible article containing the bare die light emitting semiconductor, packaged LES construction, or

intermediate LES construction;

"height" and "thickness" with respect to the dielectric layer typically refers to the vertical dimension of the dielectric layer in a certain area;

"depth" with respect to a recessed area in the dielectric layer typically refers to the vertical dimension of the recessed area, i.e., the absence of material, in the dielectric layer;

"cavity" means a recessed area in which only one or a few LESDs can be placed; and

"depression" means a large recessed area in which a plurality of LESDs can be placed.

The above summary of the present disclosure is not intended to describe each disclosed embodiment or every implementation of the present disclosure. The Figures and detailed description that follow below more particularly exemplify illustrative embodiments.

BRIEF DESCRIPTION OF DRAWINGS

The accompanying drawings are incorporated in and constitute a part of this specification and, together with the description, explain the advantages and principles of the invention. In the drawings,

Figure 1 A and IB provide illustrative ray tracing diagrams for illumination assemblies with different configurations;

Figure 2A illustrates an exemplary embodiment of a flexible LES device;

Figure 2B illustrates a comparative LESD device to Figure 2A;

Figure 3 illustrates a schematic cross-section view of an exemplary embodiment of an illumination system;

Figures 4A-4F illustrate schematic cross-section views of a number of exemplary configurations of an illumination assembly;

Figures 5A and 5B depict schematic cross-section views of exemplary embodiments of an LES device;

Figure 6A illustrates a schematic cross-section view of another exemplary embodiment of an LES device; Figure 6B illustrates a schematic perspective view of an exemplary embodiment of an LES device similar to the LES device illustrated in Figure 6A;

Figures 7A and 7B illustrate an embodiment of an illumination assembly with integrating rod and four LESDs having emission surface at different levels. Figure 7A is a side view and Figure 7B is a perspective view of the illumination assembly;

Figures 8A and 8B illustrate an embodiment illumination assembly with the same optical components as the ones in the illumination assembly illustrated in Figures 7 A and 7B, but the four LESDs having an essentially planar emission surface. Figure 8 A is a side view of and Figure 8B is a perspective view of the illumination assembly 800; and

Figures 9A-9G illustrate the steps of an exemplary etching process that may also be used to form recessed areas of the present disclosure.

DETAILED DESCRIPTION

In the following description, reference is made to the accompanying set of drawings that form a part of the description hereof and in which are shown by way of illustration several specific embodiments. It is to be understood that other embodiments are contemplated and may be made without departing from the scope or spirit of the present disclosure. The following detailed description, therefore, is not to be taken in a limiting sense.

Unless otherwise indicated, all numbers expressing feature sizes, amounts, and physical properties used in the specification and claims are to be understood as being modified in all instances by the term "about." Accordingly, unless indicated to the contrary, the numerical parameters set forth in the foregoing specification and attached claims are approximations that can vary depending upon the desired properties sought to be obtained by those skilled in the art utilizing the teachings disclosed herein. The use of numerical ranges by endpoints includes all numbers within that range (e.g. 1 to 5 includes 1, 1.5, 2, 2.75, 3, 3.80, 4, and 5) and any range within that range.

Unless otherwise indicated, the terms "coat," "coating," "coated," and the like are not limited to a particular type of application method such as spray coating, dip coating, flood coating, etc., and may refer to a material deposited by any method suitable for the material described, including deposition methods such vapor deposition methods, plating methods, coating methods, etc.

An illumination assembly often includes LESDs having different colors, where different color LESDs may have different heights. For example, the RGB (i.e., red, blue, and green) LESDs are usually combined to produce white light. The blue and greens LESDs are sometimes made of the same materials system and hence have similar dimensions, while the red LESD is often made of a different material system and has different dimension from those of blue or green LESDs.

It is often desirable to have a generally planar emission surface of multiple LESDs, as illustrated in Figures 1A and IB. Figure 1A and IB provide illustrative ray tracing diagrams for illumination assemblies with difference configurations. Figure 1 A illustrates an illumination assembly 100A, which includes two LESDs 110A and 120A and an optical collection system 150. The two LESDs 110A and 120A have different emission surfaces. As illustrated in the area 140 A, a portion of light rays emitted from the LESD 110A, which is further away from the optical collection system 150 than the LESD 120 A, is not collected by the optical collection system 150. Figure IB illustrates an illumination assembly 100B, which includes two LESDs HOB and 120B and an optical collection system 150. The two LESDs HOB and 120B have an essentially planar emission surface. A small portion of light rays emitted from the LESD HOB, as illustrated in area 140B, is not collected by the optical collection system 150. The proportion of light rays not collected from LESD 110B by optical collection systeml50 is less than the proportion of light rays not collected from the LESD 110A in Figure 1A. Methods and systems of this disclosure are directed to an illumination assembly having a multi-level substrate to support a plurality of LESDs having different heights, where the illumination assembly provides an essentially planar emission surface of the plurality of the LESDs. An illumination assembly often includes an optical collection system accepting lights generated by the LESDs. For such implementations, an illumination assembly with an essentially planar emission surface can provide higher optical power because more light is collected by the optical collection system than an illumination assembly with emission surfaces that are located at varying distances from the collection system.

In some embodiments of illumination assemblies with collection optics, if the substrate supports a plurality of LESDs with different heights, the substrate can be multi-level such that at least two of the plurality of LESDs have generally the same optical path length from the emission surface of the LESD to the emission surface of the collection optics. For example, for collection optics having a higher refractive index for shorter wavelength light, the longer wavelength LESDs may be positioned slightly further from the collection optics than the shorter wavelength LESDs. With such implementations, the chromatic aberration of an illumination system can be largely corrected. Furthermore, the substrate thickness and/or cavity surface area can be tailored to achieve better heat dissipation depending upon the heat generation of the LESDs. Advantages of embodiments of the present disclosure directed to LESDs include: the flexible LESDs provide excellent heat dissipation, a quality necessary for high power LESDs; the flexible LESDs can be wired as an array on a single flexible and insulating layer; the resulting flexible LESDs can be bent in simple or compound curves; and the use of a flexible layer with LESDs reduces the cost associated with conventional submounts.

An exemplary embodiment of a flexible LES device is illustrated in Figure 2A, which shows a dielectric layer 12 having a first major surface 13, a second major surface 14 opposing the first major surfacel3, and at least one recessed area 10. An LESD 26 that is located within recessed area 10. The floor and, optionally, the walls of recessed area 10 may be coated with conductive material 18, which may be made of the same material as conductive layer 19 or a different material from conductive layer 19, and may be deposited at the same time as conductive layer 19. Recessed area 10 may be any suitable shape, e.g., circular, oval, rectangular, serpentine, a channel, a grid (i.e., forming large or small islands of dielectric layer separated by a continuous pattern of overlapping channels), etc. In other embodiments, conductive material 18 may support additional layers such as a reflective coating. The reflective coating may be gold, silver, aluminum with enhanced reflectivity, an inherently reflective dielectric material, or a pigmented material. Conductive layer 19 is located on the first major surface 13 of dielectric layer 12 and conductive layer 20 is located on the second major surface 14 of dielectric layer 12 as shown in Figure 2A. The conductive layer 19 can partially or entirely cover the first major surface 13. The conductive material may be any suitable material, but is typically copper. In some embodiments, one or both of conductive layers 19 and 20 include an electrically conductive circuit. LESD 24 is located on a conductive feature 16, which can be part of the conductive layer 19 or include additional material such as a reflective coating, on the first major surface of dielectric layer 12. LESD 24 is insulated from LESD 26 and conductive layer 20 by the portion of dielectric layer 12 located beneath conductive feature 16, which in some cases may be an electrically isolated conductive feature.

The portion of the dielectric layer beneath each LESDs defines the distance between the LESD (and any intervening layers or materials) and the conductive layer on the second surface of the dielectric layer. This distance influences the dissipation of heat generated by the LESDs through the dielectric layer to the thermally conductive layer on the second surface of the dielectric layer. The dielectric layer can be a flexible dielectric layer or a rigid dielectric layer. A rigid dielectric layer can include one or more materials, for example, such as ceramic, FR4 PCB boards, or the like. A flexible dielectric layer can include one or more flexible non- conductive materials, for example, such as polymeric material, polymide, polyester,

polynapthanate, liquid crystal polymer, ferroelectric material (i.e., BaTi03 barium titanite), SrTi02 Strontium Titanate, or the like. The conductive layer can include one or more conductive materials, for example, such as copper, semiconductor (i.e., silicon, germanium, gallium nitride, gallium Arsenide), ceramic (i.e., silicon carbide), carbon (i.e., graphite, diamond like carbon), transparent conductive materials (i.e, indium tin oxide, antimony zinc oxide, etc.), or the like. In at least some embodiments of the present disclosure, a suitable maximum thickness for a flexible dielectric layer is about 10 to about 100 micrometers. A preferred thickness for a flexible dielectric layer under recessed areas is about 1 to about 10 micrometers. Typically cavities can be deeper than depressions because the small size of the thin dielectric layer at the bottom of the cavities results in fewer structural and mechanical issues than for a large area of thin dielectric layer.

If there are recessed areas having more than one depth, the depths may differ by any suitable amount, but typically will differ by about 10% to about 50%. In at least some embodiments of the present disclosure, LESD 26 generates more heat than LESD 24. For example, LESD 26 may be a blue or green LED and LESD 24 may be a red LED. By placing the hotter LESD in recessed area 10, the heat generated by LESD 26 has a shorter distance to travel through the dielectric layer to conductive layer 20, and therefore the heat generated by it can be more readily transferred to a heat sink. At the same time, by placing LESD 24, which generates less heat than LESD 26, at a greater distance from conductive layer 20, heat generated by LESD 26 and travelling in the X direction and Y direction along conductive layer 20 is less likely to reach LESD 24 and negatively impact its operation and functionality.

The amount of conductive material in the recessed area can also be controlled to further influence heat management. The recessed areas, especially the cavities, can be filled up to 100% with conductive material. In some embodiments this is preferred, although the recessed areas are more typically filled about from aboutl0% to about 95% full. For example, if a cavity is 50 micrometers deep, in some embodiments, conductive material 50 micrometers deep is preferred, but the depth of the conductive material may more typically be about 45 micrometers or less.

Typically, the more conductive material contained in the recessed area, the better the transfer of heat away from the LESD. Figure 2B illustrates a comparative LESD device to Figure 2A in which LESDs 24 and 26 are located in recessed areas 10 having the same depth. The floor and, optionally, the walls of recessed area 10 may be coated with conductive material 18. In Figure 2B, heat generated by LESD 26 could reach LESD 24 by first travelling in the Z direction down through the thin layer of insulation layer material between the bottom of the recessed area 10 in which LESD 26 is located to conductive layer 20; next travelling in the X direction along conductive layer 20; and finally travelling once again in the Z direction up through the thin layer of insulation layer material between conductive layer 20 and the bottom of the recessed area 10 in which LESD 24 is located. Such a heat transfer is mitigated in Figure 2B by the thick area of dielectric layer between the two recessed areas 10. However, having this thick area between recessed areas takes up surface area on the flexible LESD and will reduce the number of LESDs that can be placed in a given area.

As can be seen by comparing Figures 2A and 2B, by placing LESDs 24 and 26 at different heights on dielectric layer 12, the LESDs may be located much closer to each other in the X and Y directions than in Figure 2B while still maintaining a significant amount of insulating material (dielectric layer) between the LESDs. In at least some embodiments of the present disclosure, the ratio of (1) the difference between the first height and second height to (2) the pitch of the LESDs in the first and second areas may be any suitable ratio but is typically in a range from about 1 : 1 to about 1 : 10. Further, in some embodiments, the depths of one or more recessed areas can be adjusted such that LESD 24 and LESD 26 have a generally planar emission surface.

Figure 3 illustrates an exemplary embodiment of an illumination system 300. The illumination system 300 can include a substrate 310, a first light emitting semiconductor device (LESD) 320, a second light emitting semiconductor device (LESD) 330, and an optional optical collection system 390. The first LESD 320 has a first height and the second LESD 330 has a second height different from the first height. The first LESD 320 and the second LESD 330 can face to the optical collection system 390. The optical collection system 390 has a light entrance major surface 391 facing the LESDs and a light emission major surface 392. The substrate 310 has a first major surface 312 and a second major surface 314 opposing the first major surface 312. The first major surface 312 faces to the optical collection system 390. The substrate 310 can include a first area 370 supporting at least the first LESD 320 and a second area 380 supporting at least the second LESD 330. The first area 370 has a first area height Hi that can be indicated by the distance between the surface of the first area 370 and the second major surface 314 of the substrate 310. Similarly, the second area 380 has a second area height H? that can be indicated by the distance between the surface of the second area 380 and the second major surface 314 of the substrate 310. In some embodiments, the first area height Hi is different from the second area height H? such that the first LESD 320 and the second LESD 330 have a generally planar emission surface. In some implementations, the differences of the first and second area heights can be generally the same as the differences in the heights of the first LESD 320 and the second LESD 330. In some embodiments of the illumination system 300 including the optical collection system, the emission surface of first LESD 320 and the emission surface of second LESD 330 are at generally a same distance from the optical collection system 390. The optical collection system can include any collection optics, for example, such as lenses, integrating rods, parabolic reflectors, encapsulants, or the like. In some other embodiments, the first area height Hi is different from the second area height H_? such that the first LESD 320 and the second LESD 330 have a generally same optical path length from the light emission major surface 392 of the optical collection system 390.

In some embodiments, the substrate 310 can include a dielectric layer 340. In some other embodiments, the substrate 310 can include a conductive layer 350 at the first major surface 312. Optionally, the substrate 310 can include another conductive layer 360 at the second major surface 314 of the substrate 310. In a particular embodiment, the dielectric layer 340 is designed to have a first dielectric layer height DHi at the first area 370 and a second dielectric layer height DH at the second area 380, the first dielectric layer height DHi is different from the second dielectric layer height DH , as illustrated in Figure 3. In some implementations, the differences between the first and second dielectric layer heights can be generally the same as the differences in the heights between the first LESD 320 and the second LESD 330 in order to realize the generally planar emission suffice of the first and second LESDs.

Figures 4A-4F illustrate a number of exemplary configurations of an illumination assembly 400. The illumination assembly 400 can include a substrate 410, a first LESD 420, a second LESD 430. The height of the first LESD 420 can be different from the height of the second LESD 430. The substrate 410 includes a first major surface 412 and a second major surface 414 opposite the first major surface 412. The substrate 410 can include a first area 470 supporting at least the first LESD 420 and a second area 480 supporting at least the second

LESD 430. The first area height can be different from the second area height such that the first LESD 420 and the second LESD 430 have a generally planar emission surface. The substrate 410 can include a dielectric layer 440 and a conductive layer 450. Optionally, the substrate 410 can include a second conductive layer 460. In an exemplary embodiment illustrated in Figure 4A, the difference in the first area height and the second area height is obtained by different thickness of the dielectric layer 440 at the first area 470 and the second area 480.

In an exemplary embodiment of the illumination assembly 400, as illustrated in Figure 4B, the conductive layer 450 is designed to have a first conductive layer height CH; at the first area 470 and a second conductive layer height CH₂ at the second area 480, the first conductive layer height being different from the second conductive layer height. Conductive layer height may be understood as the height of the conductor beneath each LESD, or between the LESD and the dielectric layer. The differences between the first conductive layer height CH; and second conductive layer height CH₂ can be generally the same as the differences between the heights of the first LESD 420 and the second LESD 430.

Figure 4C illustrates an exemplary embodiment of the illumination assembly 400 with one recessed supporting area. The first area 470 of the substrate 410 is at the same level as the first major surface 412 of the substrate 410. The second area 480 of the substrate 410 is recessed. The dielectric layer 440 has a first dielectric layer height DHi at the first area 470 and a second dielectric layer height DH at the second area 480. The first dielectric layer height DHi is different from the second dielectric layer height DH such that the LESD 420 and the LESD 430 have an essentially planar emission surface. Figure 4D illustrates another exemplary embodiment of the illumination assembly 400, where the dielectric layer 440 is completely etched at the second area 480. The conductive layer 450 has a first conductive layer height CH; different from a second conductive layer height C¾ to compensate the differences in the heights of the first LESD 420 and the second LESD 430 and the differences in the dielectric layer thicknesses.

Figure 4E illustrates yet another exemplary embodiment of the illumination assembly 400, where the dielectric layer 440 is completely etched at both the first area 470 and the second area 480. The conductive layer 450 can have a first conductive layer height CH; different from a second conductive layer height CH] to compensate for the differences in the heights of the first LESD 420 and the second LESD 430. In some implementations, a first photolithograph process can be applied to create the generally same thickness for both areas. Next, the first area 470 can be masked and a second photolithograph process can be applied to create additional layer of conductive materials at the second area 480.

Figure 4F illustrates yet another exemplary embodiment of the illumination assembly 400, where a conductive material 455 having different thicknesses is disposed in the first area 470 and the second area 480. The conductive material 455 can be, for example, such as a conductive paste, solder, or the like. In some implementations, the conductive material 455 can have different thickness to support the proper heights of the first LESD 420 and the second LESD 430.

Figure 5 A illustrates an exemplary embodiment of an LES device 500 A in which LESDs

524 and 526 are placed in adjacent recessed areas 510 that are small cavities having different depths. The LESD device 500A includes a conductive layer 519, a dielectric layer 512, and a second conductive layer 520. In this embodiment, the recessed areas are cavities that hold individual LESDs. As with the embodiment illustrated in Figure 2 A, this allows placing the higher heat generating LESD 526 on a portion of the first major surface 513 of dielectric layer 512 having a second height DH2 that places LESD 526 in close proximity to the second conductive layer 520 while still insulating LESD 524 from the heat generated by LESD 526 by placing it on a portion of the first major surface 513 of dielectric layer 512 having a first height DH], that is greater than the second height. In at least some embodiments of the present disclosure, the second height DH₂ is between about 10% and about 90% less that than the first height DH;.

Figure 5B illustrates an exemplary embodiment of an LES device 500B in which LESD 524 is placed on a conductive feature of conductive layer 519 on a portion of the first major surface 513 of dielectric layer 512 that is at the maximum thickness of dielectric layer 512, while LESD 526 is located on a conductive feature in a recessed area 510 that is a depression in which multiple LESDs may be located. Such a depression may be as wide as the full width of the dielectric layer 512 and may also extend along the length of the dielectric layer 512 so that the recessed area is effectively a step change in the height of the dielectric layer. In other embodiments, there may be multiple depressions 510 that are interspersed with large non- recessed areas.

Figure 6A illustrates another exemplary embodiment of an LES device 600A in which there are recessed areas of different heights and different sizes. The LESD 600A can include a dielectric layer 612, a conductive layer 619 partially or entirely covering a first major surface 613, and optionally a conductive layer 620 partially or entirely covering a second major surface 614. In this embodiment, LESD 624 is placed on a conductive feature of the conductive layer 619 at a first height DH] that is at the maximum thickness of dielectric layer 612. LESD 626 is located on a conductive feature on a portion of the first major surface 613 of dielectric layer 612 at a third height DHs in a recessed area 6 IOC that is a small cavity, and LESD 628 is located on a conductive feature on a portion of the first major surface 613 of dielectric layer 612 at a second height DH₂ in a recessed area 610L that is a depression in which multiple LESDs may be located. The height of the portion of dielectric layer 612 under recessed area 610L Ζλ¾ is less than the maximum height of dielectric layer 612 but greater than the height of the portion of dielectric layer 612 under recessed area 6 IOC Ζλ¾. This intermediate height Ζλ¾ may be suitable, for example, for an LED that generates heat at a level between those of LESDs 624 and 626. In some embodiments of the present disclosure, the second height is between about 10% and about 90% less that than the first height and the third height is between about 10% and about 90%) less than the second height

Figure 6B illustrates a perspective view of an exemplary embodiment of an LES device

600B similar to the LES device 600A illustrated in Figure 6A. LESDs 624 are placed on conductive features of conductive layer 619 on the first major surface 613 of dielectric layer 612. LESDs 628 are placed on conductive features within recessed area 610L. LESDs 626 are placed on conductive features within recessed areas 6 IOC, which are cavities formed in the surface of recessed area 610L. Conductive layer 619 comprises a circuit that spans the first major surface of dielectric layer 612 including the surface of recessed area 610L. In this manner, many LESDs may be connected to a circuit of the flexible LESD. In some implementations, the heights of the recessed areas can be adjusted such that at least some of the LESDs included in the LESD device have a generally planar emission surface with respect to one another.

As shown in Figure 6B, in some embodiments, one or more of LESDs 624, 626, and 628 may be wire bonded to an electrically conductive circuit comprising conductive layer 19.

Conductive layer 620 is preferably thermally conductive and optionally electrically conductive. In some embodiments, conductive layer 620 comprises an electrically conductive circuit. In some embodiments, a passivation or bonding layer is located beneath LESDs 624, 626, and 628 to facilitate bonding one or more of LESDs 624, 626, and 628 to an underlying layer.

Figures 7A and 7B illustrate an embodiment of an illumination assembly 700 with integrating rod and four LESDs having emission surface at different levels. Figure 7A is a side view of the illumination assembly 700 and Figure 7B is a perspective view of the illumination assembly 700. The illumination assembly 700 includes LESD 710 (not shown in Figure 7A), LESD 715, LESD 720 (not shown in Figure 7A), LESD 725, and an integrating rod 730 functioning as the collection optics. The integrating rod 730 has an entrance surface 735 collecting lights from the LESDs and an exit surface 737 (not shown in Figure 7B) outputting light. The LESD 715 has the emission surface closest to the integrating rod among the four LESDs and the LESD 720 has the emission surface furthest away from the integrating rod among the four LESDs. In an exemplary implementation, the LESD 715 is a red LED with height of 225um; the LESDs 710 and 725 are green LED with height of 170um; the LESD 720 is a blue LED with height of 100 um; all four LESDs have 0.25 W output power; the integrating rod 730 is 5 mm long, with 2mm x 2mm entrance surface 735 and 2mm x 3mm exit surface 737; and the integrating rod 730 is placed at 0.1 mm from the top surface LESD 715 (i.e., the surface facing the integrating rod 730). The optical power entering into the integrating rod is 0.83353W and the optical power output from the integrating rod is 0.82955W.

In comparison, Figures 8A and 8B illustrate an embodiment illumination assembly with the same optical components as the ones in the illumination assembly illustrated in Figures 7A and 7B, but the four LESDs have emission surfaces on a common plane. Figure 8A is a side view of the illumination assembly 800 and Figure 8B is a perspective view of the illumination assembly 800. In an exemplary implementation with the same components as the example above, where the integrating rod 730 is placed at 0.1 mm from the emission surface of the four LESDs, the optical power entering into the integrating rod is 0.903W and the optical power output from the integrating rod is 0.89856W. As demonstrated in this example, an illumination assembly with LESDs with a generally planar emission surface (with respect to one another) can provide higher optical power than an illumination assembly with LESDs with emission surfaces at different heights (relative to the collecting optics or optics).

At least one embodiment of the present disclosure provides a flexible LESD array construction using a partially etched dielectric layer. A recessed area is etched into the dielectric layer to a desired depth. The recessed areas may have a conductive material deposited therein in any suitable manner, such as coating, vapor deposition, plating etc., but the conductive material is typically plated either using electro or electroless plating. LESDs are typically attached directly or indirectly to the conductive material using a known die bonding method such as eutectic, solder (including solder bumps for flip chip mounting), adhesive, fusion bonding, or the other bonding methods.

Suitable dielectric layers for the present disclosure include polyesters, polycarbonates, liquid crystal polymers, and polyimides. Polyimides are preferred. Suitable polyimides include those available under the trade names KAPTON, available from DuPont, Wilmington, Delaware; APICAL available from Kaneka Texas Corporation, Pasadena, Texas; SKC Kolon PI, available from SKC Kolon PI Inc., Anyang, South Korea; and UPILEX and UPISEL, available from Ube- Nitto Industries, Tokyo, Japan. Most preferred are polyimides available under the trade designations UPILEX S, UPILEX SN, and UPISEL VT, all available from Ube-Nitto Industries, Tokyo, Japan. These polyimides are made from monomers such as biphenyl tetracarboxylic dianhydride (BPDA) and phenyl diamine (PDA).

Recessed areas may be formed in the dielectric layers using any suitable method such as chemical etching, plasma etching, focused ion-beam etching, laser ablation, microreplication, embossing, and injection molding. Chemical etching may be preferred in some embodiments. Any suitable etchant may be used and may vary depending on the dielectric layer material.

Suitable etchants may include alkali metal salts, e.g. potassium hydroxide; alkali metal salts with one or both of solubilizers, e.g., amines, and alcohols, such as ethylene glycol. Suitable chemical etchants for some embodiments of the present disclosure include potassium hydroxide (KOH), ethanolamine, and ethylene glycol etchants, such as those described in more detail in U.S. Patent Publication No. 2007-0120089-A1, incorporated herein by reference. Other suitable chemical etchants for some embodiments of the present disclosure include KOH and glycine etchants, such as those described in more detail in co-pending U.S. Provisional Patent Application No. 61/409791 , incorporated herein by reference. Subsequent to etching, the dielectric layers may be treated with an alkaline KOH/ potassium permanganate (PPM) solution, e.g., a solution of about 0.7 to about 1.0 wt% KOH and about 3 wt% KMn0₄.

In at least one embodiment of the present disclosure, a UPISEL VT dielectric layer is a suitable starting material for forming a dielectric layer of the present disclosure, particularly if recessed areas are formed by chemical etching. UPISEL VT is constructed of a core layer comprising UPILEX S and thin outer layers comprising a thermoplastic polyimide (TPPI). The UPISEL VT may be etched using any suitable chemistry, such as KOH/ethanol amine/ethylene glycol described in more detail on U.S. Patent Publication. No. 2007-0120089-A1. With this etchant, the hydrophobic nature and higher modulus of the UPILEX S can result in etching by a dissolution mechanism that resulted in the side walls of the recessed areas being very smooth.

Because this etchant formulation etched quickly, the etching may be stopped before the recessed area reached the second TPPI layer. Next, a subsequent etching can be performed with a KOH/ potassium permanganate (PPM) solution, comprising about 0.7 to about 1.0 wt% KOH and about 3 wt% KMn0₄, which is not an effective etchant of the TPPI layer, to remove the remaining thin layer of UPILEX S core, thereby leaving the thin TPPI layer at the bottom of the etched recessed area.

Another suitable etchant chemistry for etching the UPISEL VT is the KOH /glycine chemistry described in more detail in co-pending U.S. Provisional Patent Application No. 61/409791. The KOH and glycine etchant is well-suited to etch the UPISEL VT because it provided a slow, controlled etching that enables controlling the thickness of the dielectric material at the bottom of the etched recessed area.

As previously mentioned as an alternative to chemical etching, recessed areas in the dielectric layer may be formed by plasma etching, focused ion-beam etching, laser ablation, embossing, microreplication, injection molding, and other suitable methods. With these methods of forming a recessed area, the side walls typically have a steeper angle, e.g., up to 90°, although the side walls can be formed at almost any desired angle if embossing, microreplication, or injection molding methods are used.

Recessed areas having different depths may be formed in the dielectric layer of the present disclosure by any suitable method, such as multiple pass etching or gray scale etching. To use the multiple pass process, for example, a dielectric layer is coated with a first photoresist material. The first photoresist is patterned and developed to exposed areas of the dielectric layer that are to be etched to form recessed areas having a first depth. After the recessed areas have been formed, the first photoresist is removed and the dielectric layer is coated with a second photoresist. The second photresist is then patterned and developed to exposed areas of the dielectric layer that are to be etched to form recessed areas having a second depth and to cover the recessed areas having a first depth so they are not further etched. If recessed areas having a third depth are desired, the process may be repeated.

Figures 9A-9G illustrate the steps of an exemplary etching process that may also be used to form recessed areas of the present disclosure. Figure 9 A shows a layer of photoresist material 910 deposited on each side of a dielectric layer 920 that is clad on one side with a conductive film 930. Figure 9B shows that the portions of the photoresist material 910 covering areas of the dielectric layer 920 that will not be etched are cross-linked areas 940, the portions of the photoresist material 910 covering areas of the dielectric layer that will be etched during a first (and second) etching step are uncross-linked areas 950, and the portions of the photoresist covering areas of the dielectric layer that will be etched during the second etching step are partially cross-linked areas 960. Figure 9C shows after the first development step, the photoresist material 910 in the uncross-linked areas 950 are removed and the photoresist material 910 in the partially cross-linked areas 960 are partially removed or not removed. Figure 9D shows the results of the first chemical etching step in which the areas of dielectric layer 920 not covered by photoresist materials are etched. Figure 9E shows after the second development step, the photoresist materials in the remaining portions of the partially cross-linked areas 960 are removed. Figure 9F shows the results of the second chemical etching step in which the areas of dielectric layer 920 not covered by photoresist are etched. This results in the dielectric layer 920 etched in the first chemical etching step in the areas 950 being further etched and the dielectric layer 920 exposed by removal photoresist materials in the partially cross-linked areas 960 being initially etched. Figure 9G shows the resulting dielectric layer 920 clad on one side with a conductive layer 930 after photoresist materials in the cross-linked areas has been removed.

The dielectric layers may be clad on one or both sides with a conductive layer. If the conductive layer(s) are to be formed into circuits, they may be pre -patterned, or may be patterned during the process of making the flexible LESDs. A multilayer flexible substrate (having multiple layers of dielectric and conductive material) may also be used as a substrate. The conductive layers may be any suitable material, but are typically copper.

If a conductive layer is to be added to one or both sides of the dielectric layer after it is formed to the desired thickness, this can be done by lamination of a metal foil to the dielectric, but is more typically done by some type of metal deposition process.

Conductive features and circuits can be formed as part of a metal deposition process. For example, a standard semi-additive deposition method of forming a circuit would include providing a vapor deposited tie layer, typically of CrOx, NiCr, or NiCrOx, vapor depositing thereon a metal seed layer that typically, but not necessarily, comprises the same metal as the subsequently plated metal layer, patterning a photomask on the seed layer using a traditional photolithography process, plating a conductive material (any suitable material, but typically copper), on the exposed portions of the seed layer using either electro or electroless plating, stripping the photomask, and removing the remaining, now-exposed portion of the seed and tie layers.

Subsequent passivation with gold, tin, silver, etc. of the conductive features onto which the LESDs will be bonded can be carried out to facilitate such bonding. The individual LESDs may be bonded onto the conductive features using any suitable bonding mechanism. Different types of bonding can be employed such as eutectic, flip chip, fusion and adhesive bonding. The LESDs preferably have a passivation layer (typically gold/tin but may be any suitable passivation material, e.g., metals such as Au and intermetallic alloys(s) such as AuSn, AuGe, AuSi) applied to their bottom surfaces to facilitate bonding the LESDs to the gold passivated conductive features. The temperature used for attaching LESDs to the conductive features is typically between about 250°C and 325°C, and most typically about 285°C for eutectic bonding (for Au/Sn). The LESDs may be adhered by other methods such as organic die attach, e.g., using silver epoxy, or soldering. Eutectic bonding is considered a direct bonding method while soldering is considered an indirect bonding method.

In at least one embodiment, the dielectric substrate and copper layers thereon provide a thin and compliant support for the LESDs. The LESDs can be packaged directly on the flexible layer, e.g., by applying an encapsulating material over individual LESDs and the recessed areas on or in which they are located, or by applying an encapsulant over an array of LESDs and the surrounding areas. The encapsulant is preferably a transparent (i.e., having a transmittance over 94%, preferably over 99%) molding compound. The encapsulant may optionally be suitable to act as a lens when cured. Silicones and epoxies are suitable encapsulating compounds. The encapsulant may further contain optical diffusing particles distributed therein. Suitable molding compounds may be purchased, e.g., from Shin-Etsu Chemical Co., Ltd., Tokyo, Japan and NuSil Silicone Technology, Santa Barbara, California. If desired, a wavelength converting material, such as a phosphor coating, may be deposited on top of the LESD prior to encapsulation. An underfill material may optionally be applied prior to encapsulating the LESD. The flexible LESDs may also be enclosed in a waterproof/weatherproof, transparent casing, which may be made from any suitable polymeric transparent material.

In at least one embodiment of the present disclosure one or more cavity structures similar to those in Figure 5 is formed in the dielectric substrate layer, an LESD is placed in the cavity, and the cavity is filled with an encapsulant that covers the LESD. In at least one embodiment of the present disclosure, the encapsulant is a transparent color conversion material, which can absorb light emitted from the LES of the LESD and re-emit the light at a different, typically higher, wavelength. For example, a color conversion material containing yellow phosphors may be used to encapsulate a blue LED, which allows for production of white light. In some embodiments of the present disclosure, the slopes of the cavity sidewalls can be tailored to create a uniform thickness of the color conversion layer surrounding the LESD to provide uniform light conversion, and preferably, superior thermal management. In at least one embodiment of the present disclosure, the slopes of the cavity sidewalls are about 5° to about 90°. An advantage of at least one embodiment of the present disclosure is that placing the LESD in a cavity enables precise placement of the encapsulant because it can be contained snugly within the cavity. An advantage of at least one embodiment of the present disclosure is that placing the LESD in the center of a cavity and filling the cavity with encapsulant creates uniform light conversion due to the uniform layer of encapsulant that can be created around the LESD. In an alternate embodiment of the present disclosure, instead of encapsulating the LESD with the color conversion material, a layer of the color conversion material is coated on the floor of the cavity prior to placing the LESD in the cavity. In this manner, the color conversion material can absorb at least some of the light emitted from the LES of the LESD and re-emit the light at a different, typically higher, wavelength. An example of a suitable color conversion material is a phosphor- filled encapsulant. Such an encapsulant may be made by mixing yellow phosphor, such as that available under the trade designation ISIPHOR SSA612100 from Merck, with a suitable silicone encapsulant having suitable adhesion properties. A weight ratio of 75% phosphor to silicone adhesive may be suitable in some embodiments. After the encapsulant is dispensed into the cavity, in some embodiments it may be cured by exposure to UV light at 80°C for an hour.

In at least one embodiment of the present disclosure a cavity structure similar to those illustrated in Figure 5 is formed in the dielectric substrate layer. An LESD, which is a complete packaged LES construction, is placed in the cavity. The body of the LESD resides in the cavity, while contact leads extend to bond pads on the first major surface of the dielectric layer. In another embodiment of the present disclosure a complete packaged LES construction resides in a cavity in the dielectric layer. In this embodiment, the LESD is surface mounted directly to the conductive material in the cavity. In this embodiment, the bond sites for the two LESD contacts need to be electrically isolated from each other. This may be done, for example, by creating a gap in the conductive material deposited in the cavity. Examples of the type of complete packaged LES constructions that may be suitable for use in embodiments of the present disclosure include Golden DRAGON LEDs, available from OSRAM Opto Semiconductors

GmbH, Munich, Germany; LUXION LEDs, available from Philips Lumileds Lighting Company, San Jose, California, USA; and XLAMP LEDs, available from Cree, Inc., Durham, North Carolina.

In at least some embodiments of the present disclosure, the dielectric layer and the copper layers on one or both of the first and second surface of the dielectric layer support and surround the LESDs, thereby providing a robust flexible LESD.

The flexible LESDs can be made in a batch process or a continuous process such as a roll-to-roll process that is often used in making flexible circuits. Arrays of LESDs can be placed in any desired pattern on the flexible substrate. The LESDs can then be divided as desired, e.g., singulated into individual LESDs, strips of LESDs, or arrays of LESDs, e.g., by stamping or by slitting the substrate. Accordingly, an entire reel of LESDs on a flexible substrate can be shipped without the need for the traditional tape and reel process in which individual LESDs are typically transported in individual pockets of a carrier tape. Before or after forming individual, strips, or arrays of LESDs, the flexible LESDs can be attached to an additional substrate, for example by attaching the conductive layer on the second major surface of the dielectric substrate to an additional substrate with a thermally conductive adhesive. The thermally conductive adhesive can further facilitate the transfer of heat away from the LESD. Alternatively, the conductive layer on the second major surface of the dielectric substrate may be treated with metals or other materials that will facilitate its adhesion to an additional substrate. The flexible LESDs can be attached to any desired substrate, depending on their intended use. The additional substrate may be thermally and/or electrically conductive or may be a semiconductor, ceramic, or polymeric substrate, which may or may not be thermally conductive. For example, the additional substrates can be flexible metal substrates, rigid metal substrates, heat sinks, dielectric substrates, circuit boards, etc.

If the LESDs are for use on a circuit board, the flexible LESDs, whether in singulated, strip, or array form can be directly attached to an end user's circuit board, thereby eliminating the need for conventional lead frame materials. If the LESDs are for use as a lighting strip, the flexible LESDs could be enclosed in a waterproof/weatherproof, transparent casing, as described above.

If the LESDs are in strip or array form, the LESDs may be electrically connected to one or more of the other LESDs in the strip or array. Additional elements such as Zener diodes and Schottky diodes can also be added to the first or second surface of the flexible LESD by, e.g. using direct wafer bonding or flip chip processes, prior to be division of the LESDs into the flexible LESDs. These elements may also be electrically connected to the LESDs.

In at least one embodiment of the present disclosure, the flexible LESDs are thinner than conventional single or multiple LESD packages because the LESD sits below the surface of the dielectric layer. This enables the flexible LESDs of the present disclosure to be used in applications with tight volume restrictions, such as cell phones and camera flashes. For example, the flexible LESDs of the present disclosure can provide a package profile of approximately 0.7 to 4 mm, and in some embodiments 0.7 to 2 mm whereas conventional LESD package profiles are typically greater than 4 mm and are approximately 4.8 mm to 6.00 mm. Moreover, the flexible devices of the present disclosure can be flexed or bent to easily fit into a non-linear or non-planar assembly if desired.

In at least one embodiment, the dielectric layer and copper layers thereon provide a thin and compliant support for the flexible LESD. In at least one embodiment, the total copper thickness is less than 200 micrometers, preferably less than 100 micrometers, and most preferably less than 50 micrometers. In at least one embodiment, the thickness of the dielectric layer is preferably 50 micrometers or less.

EXAMPLES

This invention is illustrated by the following examples, but the particular materials and amounts thereof recited in these examples, as well as other conditions and details should not be construed to unduly limit this invention.

Etching Method

The general procedure for preparing the etchants included first dissolving 37 wt% potassium hydroxide (KOH) in water by mixing, followed by the subsequent addition of 3.5 wt% ethylene glycol and 22 wt% ethanolamine. Samples of 50 μιη polyimide dielectric substrate with 3 μιη copper layer clad on one side, available under the trade designation UPISEL-N from Ube- Nitto Kasei Co., Ltd. Industries, Tokyo, Japan, was subjected to selective etching from the PI side using aqueous photoresist, available under the trade designation HM-4056 from Hitachi

Chemicals, Japan, as an etch mask. The etching was controlled by timing to create a thin region of polyimide having a bulk thickness, which took approximately 15 minutes.

Circuit-Forming Method

A 20 inch (50.8 cm) wide by 10 m long sample of 50 μιη polyimide with 3 μιη copper clad on one side, available under the trade designation UPISEL-N from Ube-Nitto Kasei Co., Ltd. Industries, Tokyo, Japan, was first slit into a 13.4 inch (34.04 cm) width. Following removal of the 18 μιη copper carrier layer from the copper (Cu) side, a region of the polyimide was thinned down to a bulk thickness in the sample by laminating dry film photoresist, available under the trade designation HM4056 from Hitachi Chemicals, Ltd. on both sides and creating a patterned etch mask on the polyimide side using a photolithography process. The sample was then subjected to a chemical etching process using the Etching Method described above for approximately 15 minutes to create a thinned down region in the polyimide substrate having a bulk thickness of about 5 μιη, a width at the thinned down PI level of about 500 μιη, and a width at the original PI level of about 700 μιη (with a transition wall angle of about 25° - 28°). After removing the photoresist from both sides, the exposed PI surface of the sample was first subjected to seeding of a chrome tie layer having a thickness of 2-20 nm by vacuum deposition, then to depositing copper to a thickness of about 100 nm on the tie layer by vacuum deposition to form a conductive coating. The conductive coating was then subjected to electroplating to build up the conductive copper coating to a final thickness of about 3 μιη. This provided a structure of a conductive coating in the etched thinned down region of the PI dielectric substrate. Photoresist was then applied on both sides of the copper clad (on one side) and copper coated (on the other side) dielectric substrate and patterned on both sides by a re-registration photolithography process. 45 μιη of copper was electrodeposited onto the exposed portions of the thin

electrodeposited copper on the etched PI side and exposed portions of the copper cladded side. Then after the photoresist was removed from the etched PI side, the exposed portions of the 3 μιη copper layer and the chrome tie layer were removed to create circuit patterns on the dielectric substrate. This resulted in conductive electrodes having a thickness of 45 μιη on the thinned down region of the polyimide substrate and also the thick polyimide region.

Example 1

Following is an example of packaging LESDs on a flexible substrate, specifically, mounting blue LEDs on a thinned down region of a flexible dielectric substrate with organic die attach.

Conductive circuits were formed on a thinned down region of a flexible dielectric substrate using the Circuit-Forming Method described above. The thinned down region had a bulk thickness of about 5 μιη and a conductive coating of electroplated copper of about 45 μιη. A Cree EZ 290 Gen II LED, available as part number CA460EZ290-S2100-2 from Cree, Inc., Durham, NC, U.S.A., was bonded to the conductive coating using a silver epoxy organic die attach available from Quantum Materials, San Diego, U.S.A. with thermal curing done at 150 °C for 1 hour. Each LED was wire bonded to the conductive circuit on the top surface of the dielectric substrate with gold bonding pads using a manual wire bonder, available under the trade designation 4524D from Kulicke and Soffa Industries, Inc., Fort Washington, PA, U.S.A., using 1 mil diameter gold wire. The assembly was tested using a power supply available as model number EX4210R (voltage rating 42 V, current rating 10 A) from Thurlby Thandar Instruments Limited (TTi), Huntingdon, Cambridgeshire, United Kingdom. The LEDs were bright blue when lit up and the assembly showed flexibility.

Example 2 Following is another example of packaging LESDs on a flexible substrate, specifically, mounting blue LEDs on a thinned down region of a flexible dielectric substrate with indirect die bonding.

Conductive circuits were formed on a thinned down region of a flexible dielectric substrate using the Circuit-Forming Method described above. The thinned down region had a bulk thickness of about 5 μιη and a conductive coating of electroplated copper of about 45 μιη. A Cree EZ 290 Gen II LED, available as part number CA460EZ290-S2100-2 from Cree, Inc., Durham, NC, U.S.A., was bonded to the conductive coating using solder in between the LED and the conductive coating. Each LED was wire bonded to the conductive circuit on the top surface of the dielectric substrate through gold bonding pads using a manual wire bonder, available under the trade designation 4524D from Kulicke and Soffa Industries, Inc., Fort Washington, PA, U.S.A., with 1 mil diameter gold wire. The assembly was tested using a power supply available as model number EX4210R (voltage rating 42 V, current rating 10 A) from Thurlby Thandar Instruments Limited (TTi), Huntingdon, Cambridgeshire, United Kingdom. The LEDs were bright blue when lit up and the assembly showed flexibility.

Exemplary Embodiments

1. An illumination system comprising:

an optical collection system,

a first light emitting semiconductor device (LESD) having a first height, the first LESD facing the optical collection system,

a second light emitting semiconductor device (LESD) having a second height different from the first height, the second LESD facing the optical collection system,

a substrate having a first area and a second area, the first area supporting at least the first LESD and the second area supporting at least the second LESD, and the first area having a first area height different from a second area height of the second area such that the emission surface of first LESD and the emission surface of second LESD are at generally a same distance from the optical collection system.

2. The illumination system of embodiment 1, wherein the optical collection system comprises a lens.

3. The illumination system of embodiment 1, wherein the optical collection system comprises an integrating rod. 4. The illumination system of embodiment 1, wherein the substrate comprises a conductor layer, the conductor layer having a first conductor layer height at the first area and a second conductor layer height at the second area, the first conductor layer height is different from the second conductor layer height.

5. The illumination system of embodiment 1, wherein the substrate comprises a dielectric layer, the dielectric layer designed to have a first dielectric layer height at the first area and a second dielectric layer height at the second area, the first dielectric layer height is different from the second dielectric layer height.

6. The illumination system of embodiment 5, wherein the dielectric layer comprises a polyimide core and a thermoplastic polyimide layer on one side of the core.

7. The illumination system of embodiment 1, wherein the light emitting semiconductor device is an intermediate light emitting semiconductor construction.

8. The illumination system of embodiment 1, wherein the light emitting semiconductor device is an encapsulated light emitting semiconductor construction.

9. The illumination system of embodiment 1 , wherein at least one of the first area and the second area is a recessed area.

10. The illumination system of embodiment 9, wherein the recessed area is a cavity.

11. The illumination system of embodiment 10, wherein the cavity is filled with a phosphor- filled encapsulant.

12. An illumination assembly comprising:

a first light emitting semiconductor device (LESD) having a first height,

a second light emitting semiconductor device (LESD) having a second height different from the first height,

a dielectric layer having a first area and a second area, the first area supporting at least the first LESD and the second area supporting at least the second LESD, and the first area having a first area height different from a second area height of the second area such that the first LESD and the second LESD have a generally planar emission surface.

13. The illumination assembly of embodiment 12, further comprising:

an optical collection system facing the first LESD and the second LESD.

14. The illumination assembly of embodiment 13, wherein the optical collection system comprises a lens.

15. The illumination assembly of embodiment 13, wherein the optical collection system comprises an integrating rod. 16. The illumination assembly of embodiment 12, further comprising:

a conductor layer on top of the dielectric layer, the conductor layer having a first conductor layer height at the first area and a second conductor layer height at the second area, the first conductor layer height is different from the second conductor layer height.

17. The illumination assembly of embodiment 12, wherein the light emitting semiconductor device is an intermediate light emitting semiconductor construction.

18. The illumination assembly of embodiment 12, wherein the light emitting semiconductor device is an encapsulated light emitting semiconductor construction.

19. The illumination assembly of embodiment 12, wherein the dielectric layer comprises a polyimide core and a thermoplastic polyimide layers on one side of the core.

20. The illumination assembly of embodiment 12, wherein at least one of the first area and the second area is a recessed area.

21. The illumination assembly of embodiment 20, wherein the recessed area is a cavity.

22. The illumination assembly of embodiment 21, wherein the cavity is filled with a phosphor- filled encapsulant.

23. A method comprising :

providing an optical collection system;

providing a substrate having first and second major surfaces and having a first area having a first height;

creating at least one recessed second area on the first major surface such that the second area has a second height that is less than the first height; and

placing at least one light emitting semiconductor on each of the first and second areas facing the optical collection system.

24. The method of embodiment 23, wherein the substrate comprises a dielectric layer.

25. The method of embodiment 24, wherein the substrate further comprises a conductive layer on top of the dielectric layer.

26. The method of embodiment 25, wherein the conductive layer comprises a circuit.

27. The method of embodiment 23, wherein the second area in the first major surface of the dielectric layer is created by a method selected from the group consisting of chemical etching, plasma etching, focused ion-beam etching, and laser ablation.

28. The method of embodiment 23, wherein the at least one recessed second area is chemically etched with an etchant solution comprising potassium hydroxide, ethanolamine , and ethylene glycol. 29. The method of embodiment 28, wherein the at least one recessed second area is further etched by an etchant solution comprising alkaline potassium permanganate.

30. The method of embodiment 23, wherein the at least one recessed second area is chemically etched with an etchant solution comprising potassium hydroxide and glycine.

31. The method of embodiment 23, wherein the at least one recessed second area is further etched by an etchant solution comprising alkaline potassium permanganate.

32. An article comprising:

A flexible dielectric layer having first and second major surfaces, the first major surface having at least one first area having a first height and at least one second area having a second height different from the first height, wherein the first area supports at least a first light emitting semiconductor device (LESD) and the second area supports at least a second light emitting semiconductor device (LESD); and a first conductive layer on the first major surface of the dielectric layer.

33. The article of embodiment 32, wherein the first height is greater than the second height. 34. The article of embodiment 33, wherein the first height is the maximum height of the dielectric layer.

35. The article of embodiment 33, wherein the second height is formed by removal of material from the first major surface.

36. The article of any of embodiments 32 to 34, wherein the second LESD generates more heat than the first LESD.

37. The article of embodiment 32, wherein the first height and the second height are both less than the maximum height of the flexible dielectric layer and the second height is less than the first height.

38. The article of embodiment 32, wherein the second area is a recessed area.

39. The article of embodiment 38, wherein the recessed area is a cavity.

40. The article of embodiment 32, wherein the first and second areas are both recessed areas that are cavities.

41. The article of embodiment 32, wherein the ratio of the difference between the first height and second height to the pitch of the LESDs in the first and second areas is about 1 : 1 to about 1 : 10.

42. The article of embodiment 32, wherein the first area is a recessed area that is a depression and the second area is a recessed area that is a cavity. 43. The article of embodiment 32, further comprising at least a third area having a third height that is less than the first and second heights, the third area supporting a third light emitting semiconductor device.

44. The article of embodiment 32, wherein the second light emitting semiconductor device produces more heat during operation than the first light emitting semiconductor device.

45. The article of embodiment 32, wherein the third light emitting semiconductor device produces more heat during operation than the first and second light emitting semiconductor devices.

46. The article of embodiment 32, wherein the second height is between about 10% and about 90% less that than the first height.

47. The article of embodiment 32, wherein the second height is between about 10% and about 90% less that than the first height and the third height is between about 10% and about 90% less than the second height.

48. The article of embodiment 32, wherein the second major surface of the dielectric layer has a conductive layer thereon.

49. The article of embodiment 48, wherein the conductive layer on the second major surface of the dielectric layer comprises a circuit.

50. The article of embodiment 32, wherein the flexible dielectric layer comprises a polyimide core and thermoplastic polyimide layers on one or both sides of the core.

51. The article of embodiment 32, wherein the light emitting semiconductor device is a bare die LES construction.

52. The article of embodiment 32, wherein the light emitting semiconductor device is an intermediate LES construction.

53. The article of embodiment 32, wherein the light emitting semiconductor device is a complete packaged LES construction.

54. The article of embodiment 32, wherein the cavity is filled with a phosphor-filled encapsulant.

55. A method comprising :

providing a flexible dielectric layer having first and second major surfaces and having a first area having a first height;

creating at least one recessed second area on the first major surface having a second height that is less than the first height;

creating a conductive layer on the first major surface of the dielectric layer, and placing at least one LES on each of the first and second areas.

56. The method of embodiment 55, further comprising creating at least one recessed third area on the first major surface having a third height that is less than the first and second heights.

57. The method of embodiment 55, wherein the conductive layer on the first major surface of the dielectric layer comprises a circuit.

58. The method of embodiment 55, further comprising creating a conductive layer on the second major surface of the dielectric layer.

59. The method of embodiment 58, wherein the conductive layer on the second major surface of the dielectric layer comprises a circuit.

60. The method of embodiment 55, wherein the second area in the first major surface of the dielectric layer is created by a method selected from the group consisting of chemical etching, plasma etching, focused ion-beam etching, and laser ablation.

61. The method of embodiment 55, wherein the at least one recessed second area is chemically etched with an etchant solution comprising potassium hydroxide (KOH) , ethanolamine (MEA), and ethylene glycol (MEG).

62. The method of embodiment 61, wherein the at least one recessed second area is further etched by an etchant solution comprising alkaline potassium permanganate.

63. The method of embodiment 55, wherein the at least one recessed second area is chemically etched with an etchant solution comprising KOH and glycine.

64. The method of embodiment 63, wherein the at least one recessed second area is further etched by an etchant solution comprising alkaline potassium permanganate.

65. An illumination system comprising:

an optical collection system has a light entrance major surface and a light emission surface opposing the light entrance major surface,

a first light emitting semiconductor device (LESD) having a first height, the first LESD facing the light entrance major surface of the optical collection system,

a second light emitting semiconductor device (LESD) having a second height different from the first height, the second LESD facing the light entrance major surface of the optical collection system, and

a substrate having a first area and a second area, the first area supporting at least the first

LESD and the second area supporting at least the second LESD, and the first area having a first area height different from a second area height of the second area. 66. The illumination system of embodiment 65, wherein the first area height is different from the second area height such that the emission surface of the first LESD and the emission surface of the second LESD are at generally a same distance from the light entrance major surface of the optical collection system.

67. The illumination system of embodiment 65, wherein the first area height is different from the second area height such that the emission surface of the first LESD and the emission surface of second LESD are at generally a same optical path length from the light emission major surface of the optical collection system.

Although specific embodiments have been illustrated and described herein for purposes of description of the preferred embodiment, it will be appreciated by those of ordinary skill in the art that a wide variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present disclosure. This application is intended to cover any adaptations or variations of the preferred embodiments discussed herein. Therefore, it is manifestly intended that this invention be limited only by the claims and the equivalents thereof.

Claims

What is claimed is:

1. An illumination system comprising:

a substrate having a first area and a second area, the first area supporting at least the first LESD and the second area supporting at least the second LESD, and the first area having a first area height different from a second area height of the second area.

2. The illumination system of claim 1, wherein the first area height is different from the second area height such that the emission surface of the first LESD and the emission surface of the second LESD are at generally a same distance from the light entrance major surface of the optical collection system.

3. The illumination system of claim 1, wherein the first area height is different from the second area height such that the emission surface of the first LESD and the emission surface of second LESD are at generally a same optical path length from the light emission major surface of the optical collection system.

4. The illumination system of claim 1 , wherein the optical collection system comprises a lens.

5. The illumination system of claim 1, wherein the optical collection system comprises an integrating rod.

6. The illumination system of claim 1, wherein the substrate comprises a conductive layer, the conductive layer having a first conductive layer height at the first area and a second conductive layer height at the second area, the first conductive layer height is different from the second conductive layer height.

7. The illumination system of claim 1 , wherein the substrate comprises a dielectric layer, the dielectric layer designed to have a first dielectric layer height at the first area and a second dielectric layer height at the second area, the first dielectric layer height is different from the second dielectric layer height.

8. The illumination system of claim 1, wherein the light emitting semiconductor device is an intermediate light emitting semiconductor construction.

9. The illumination system of claim 1, wherein the light emitting semiconductor device is an encapsulated light emitting semiconductor construction.

10. The illumination system of claim 1, wherein at least one of the first area and the second area is a recessed area.

11. The illumination system of claim 10, wherein the recessed area is a cavity.

12. The illumination system of claim 11, wherein the cavity is filled with a phosphor-filled encapsulant.

13. An illumination assembly comprising:

a first light emitting semiconductor device (LESD) having a first height,

a second light emitting semiconductor device (LESD) having a second height different from the first height, and

14. The illumination assembly of claim 13, further comprising:

an optical collection system facing the first LESD and the second LESD.

15. The illumination assembly of claim 14, wherein the optical collection system comprises a lens.

16. The illumination assembly of claim 14, wherein the optical collection system comprises an integrating rod.

17. The illumination assembly of claim 13, further comprising:

a conductive layer on top of the dielectric layer, the conductive layer having a first conductive layer height at the first area and a second conductive layer height at the second area, the first conductive layer height is different from the second conductive layer height.

18. The illumination assembly of claim 13, wherein the light emitting semiconductor device is an intermediate light emitting semiconductor construction.

19. The illumination assembly of claim 13, wherein the light emitting semiconductor device is an encapsulated light emitting semiconductor construction.

20. The illumination assembly of claim 13, wherein the dielectric layer comprises a polyimide core and a thermoplastic polyimide layers on one side of the core.

21. The illumination assembly of claim 13, wherein at least one of the first area and the second area is a recessed area.

22. The illumination assembly of claim 21, wherein the recessed area is a cavity.

23. The illumination assembly of claim 22, wherein the cavity is filled with a phosphor-filled encapsulant.

24. A method comprising:

providing an optical collection system;

providing a substrate having first and second major surfaces and having a first area having a first height; creating at least one recessed second area on the first major surface such that the second area has a second height that is less than the first height; and

25. The method of claim 24, wherein the substrate comprises a dielectric layer.

26. The method of claim 25, wherein the substrate further comprises a conductive layer on top of the dielectric layer.

27. The method of claim 26, wherein the conductive layer comprises a circuit.

28. An article comprising:

29. The article of claim 28, wherein the first height is greater than the second height.

30. The article of claim 28, wherein the second height is formed by removal of material from the first major surface.

31. The article of claim 28, wherein the second LESD generates more heat than the first LESD.

32. The article of claim 28, wherein the ratio of the difference between the first height and second height to the pitch of the LESDs in the first and second areas is about 1 : 1 to about 1 : 10.

33. The article of claim 28, wherein the first area is a recessed area that is a depression and the second area is a recessed area that is a cavity.

34. The article of claim 28, wherein the second major surface of the dielectric layer has a conductive layer thereon.

35. A method comprising:

creating a conductive layer on the first major surface of the dielectric layer; and placing at least one LES on each of the first and second areas.

36. The method of claim 35, wherein the conductive layer on the first major surface of the dielectric layer comprises a circuit.

37. The method of claim 35, further comprising creating a conductive layer on the second major surface of the dielectric layer.