WO2012101856A1 - 窒化物半導体素子の製造方法 - Google Patents
窒化物半導体素子の製造方法 Download PDFInfo
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- WO2012101856A1 WO2012101856A1 PCT/JP2011/069085 JP2011069085W WO2012101856A1 WO 2012101856 A1 WO2012101856 A1 WO 2012101856A1 JP 2011069085 W JP2011069085 W JP 2011069085W WO 2012101856 A1 WO2012101856 A1 WO 2012101856A1
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- layer
- semiconductor layer
- gallium nitride
- based semiconductor
- gas
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 252
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 35
- 238000000034 method Methods 0.000 title claims abstract description 31
- 150000004767 nitrides Chemical class 0.000 title claims description 45
- 239000007789 gas Substances 0.000 claims abstract description 50
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims abstract description 49
- 239000000758 substrate Substances 0.000 claims abstract description 46
- 239000012159 carrier gas Substances 0.000 claims abstract description 36
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 24
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims abstract description 18
- 229910001873 dinitrogen Inorganic materials 0.000 claims abstract description 16
- 229910052786 argon Inorganic materials 0.000 claims abstract description 9
- 239000001307 helium Substances 0.000 claims abstract description 9
- 229910052734 helium Inorganic materials 0.000 claims abstract description 9
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 claims abstract description 9
- 229910052754 neon Inorganic materials 0.000 claims abstract description 9
- GKAOGPIIYCISHV-UHFFFAOYSA-N neon atom Chemical compound [Ne] GKAOGPIIYCISHV-UHFFFAOYSA-N 0.000 claims abstract description 9
- 229910002601 GaN Inorganic materials 0.000 claims description 205
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 113
- 230000000903 blocking effect Effects 0.000 claims description 63
- 239000002019 doping agent Substances 0.000 claims description 58
- 239000001257 hydrogen Substances 0.000 claims description 20
- 229910052739 hydrogen Inorganic materials 0.000 claims description 20
- 239000011777 magnesium Substances 0.000 claims description 17
- 229910002704 AlGaN Inorganic materials 0.000 claims description 14
- 229910052738 indium Inorganic materials 0.000 claims description 10
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 10
- 229910052749 magnesium Inorganic materials 0.000 claims description 7
- 239000011701 zinc Substances 0.000 claims description 6
- 229910052725 zinc Inorganic materials 0.000 claims description 6
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 5
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 claims description 5
- 229910052733 gallium Inorganic materials 0.000 claims description 5
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 4
- 230000005669 field effect Effects 0.000 abstract description 13
- 230000007423 decrease Effects 0.000 abstract description 5
- 125000004435 hydrogen atom Chemical group [H]* 0.000 description 43
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 19
- 238000010438 heat treatment Methods 0.000 description 16
- 238000005259 measurement Methods 0.000 description 15
- 230000004888 barrier function Effects 0.000 description 14
- 125000005842 heteroatom Chemical group 0.000 description 12
- 239000012535 impurity Substances 0.000 description 12
- 239000011261 inert gas Substances 0.000 description 11
- 230000008569 process Effects 0.000 description 9
- 230000000052 comparative effect Effects 0.000 description 8
- 229910021529 ammonia Inorganic materials 0.000 description 7
- 238000000137 annealing Methods 0.000 description 7
- 230000004913 activation Effects 0.000 description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 6
- 239000001301 oxygen Substances 0.000 description 6
- 229910052760 oxygen Inorganic materials 0.000 description 6
- 239000012298 atmosphere Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 229910052757 nitrogen Inorganic materials 0.000 description 4
- 230000005533 two-dimensional electron gas Effects 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 239000000969 carrier Substances 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 3
- 239000012299 nitrogen atmosphere Substances 0.000 description 3
- KDLHZDBZIXYQEI-UHFFFAOYSA-N palladium Substances [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 3
- 239000002994 raw material Substances 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 230000009849 deactivation Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000010348 incorporation Methods 0.000 description 2
- QBJCZLXULXFYCK-UHFFFAOYSA-N magnesium;cyclopenta-1,3-diene Chemical compound [Mg+2].C1C=CC=[C-]1.C1C=CC=[C-]1 QBJCZLXULXFYCK-UHFFFAOYSA-N 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 229910000077 silane Inorganic materials 0.000 description 2
- XCZXGTMEAKBVPV-UHFFFAOYSA-N trimethylgallium Chemical compound C[Ga](C)C XCZXGTMEAKBVPV-UHFFFAOYSA-N 0.000 description 2
- 229910017083 AlN Inorganic materials 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- HQWPLXHWEZZGKY-UHFFFAOYSA-N diethylzinc Chemical compound CC[Zn]CC HQWPLXHWEZZGKY-UHFFFAOYSA-N 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
- 230000008707 rearrangement Effects 0.000 description 1
- 238000001004 secondary ion mass spectrometry Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- JBQYATWDVHIOAR-UHFFFAOYSA-N tellanylidenegermanium Chemical compound [Te]=[Ge] JBQYATWDVHIOAR-UHFFFAOYSA-N 0.000 description 1
- JLTRXTDYQLMHGR-UHFFFAOYSA-N trimethylaluminium Chemical compound C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 description 1
- IBEFSUTVZWZJEL-UHFFFAOYSA-N trimethylindium Chemical compound C[In](C)C IBEFSUTVZWZJEL-UHFFFAOYSA-N 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/2003—Nitride compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/737—Hetero-junction transistors
- H01L29/7371—Vertical transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7788—Vertical transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7789—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface the two-dimensional charge carrier gas being at least partially not parallel to a main surface of the semiconductor body
Definitions
- the present invention relates to a method for manufacturing a nitride semiconductor device.
- Patent Document 1 discloses a hetero electric field having a vertical transistor structure in which an n-type GaN drift layer, a p-type GaN barrier layer, and an n-type GaN cap layer are sequentially formed on a conductive substrate.
- An effect transistor (HFET: Heterojunctin Field Effect Transistor) is disclosed.
- HFET Heterojunctin Field Effect Transistor
- an opening from the n-type GaN cap layer to the n-type GaN drift layer through the p-type GaN barrier layer is formed, and an electron transit layer and an electron supply are formed on the side surface of the opening.
- the layers are sequentially stacked.
- an n-type GaN drift layer, a p-type GaN barrier layer, and an n-type GaN cap layer are sequentially formed on a conductive substrate by MOCVD or the like, and then the p-type GaN is formed from the n-type GaN cap layer.
- An opening reaching the n-type GaN drift layer via the barrier layer is formed, and an electron transit layer and an electron supply layer are sequentially laminated on the side surface of the opening.
- hydrogen atoms such as ammonia (NH 3 ) gas used for suppressing decomposition of the semiconductor crystal and hydrogen (H 2 ) gas used as carrier gas are used.
- the contained gas may be introduced into the growth furnace.
- ammonia gas or hydrogen gas remains in the growth furnace when the temperature is lowered after the p-type semiconductor layer is formed at a high temperature, ammonia gas or hydrogen gas
- the derived hydrogen atoms are taken into the p-type semiconductor layer, and the hydrogen atoms may be bonded (passivation) to the dopant (for example, Mg), resulting in an insufficient acceptor concentration of the p-type semiconductor layer (for example, Non-patent document 1 above).
- nitride semiconductor device such as the transistor described in Patent Document 1
- the activity of the dopant in the p-type semiconductor layer is improved, and the current block at the pn interface is functioned to cause drain leakage. Therefore, it is considered that activation annealing is performed after the semiconductor stack is formed.
- an n-type GaN cap layer is formed on the p-type GaN barrier layer. Since the annealing is performed in a state where the layers are stacked, the n-type GaN cap layer acts as a barrier against hydrogen atoms. Therefore, hydrogen atoms are prevented from being released from the p-type GaN barrier layer to the outside of the device, and it is difficult to sufficiently function the p-type GaN barrier layer for suppressing drain leakage.
- the interface between the n-type GaN drift layer and the p-type GaN barrier layer does not sufficiently function electrically, and drain leakage (current leakage) Will occur and the pinch-off characteristic will be degraded.
- the present invention has been made in view of such problems, and an object thereof is to provide a method for manufacturing a nitride semiconductor device capable of reducing drain leakage current.
- an inert gas for example, nitrogen gas
- an inert gas different from hydrogen gas in the step of forming the p-type semiconductor layer from the viewpoint of suppressing the entry of hydrogen atoms into the p-type semiconductor layer.
- an inert gas such as nitrogen gas
- compensation impurities such as oxygen are likely to be mixed into the p-type semiconductor layer.
- the dopant in the p-type semiconductor layer is compensated by the mixed compensation impurities, the acceptor concentration of the p-type semiconductor layer is lowered, and the occurrence of defective drain leakage is promoted.
- hydrogen gas when hydrogen gas is used as the carrier gas in the step of forming the p-type semiconductor layer, it is possible to sufficiently prevent the compensation impurities from being mixed into the p-type semiconductor layer.
- the drain leakage current can be reduced as compared with the case where an active gas is used.
- hydrogen gas can serve as a supply source of hydrogen atoms, by forming the p-type semiconductor layer at a high temperature, the dopant in the p-type semiconductor layer is bonded to the hydrogen atoms while reducing the hydrogen concentration of the p-type semiconductor layer. Can be suppressed.
- the hydrogen concentration of the p-type semiconductor layer is reduced while suppressing the introduction of compensation impurities into the p-type semiconductor layer.
- it can suppress that the dopant in a p-type semiconductor layer couple
- the method for manufacturing a nitride semiconductor device includes a step of epitaxially growing a first gallium nitride based semiconductor layer on a freestanding group III nitride substrate, and using hydrogen gas as a carrier gas.
- the second gallium nitride based semiconductor layer which is a p-type semiconductor layer, is epitaxially grown on the first gallium nitride based semiconductor layer at 1000 ° C. or higher, and selected from the group consisting of nitrogen gas, argon gas, helium gas and neon gas.
- the second gallium nitride based semiconductor layer which is a p-type semiconductor layer, is epitaxially grown at 1000 ° C. or higher using hydrogen gas as a carrier gas.
- hydrogen gas as a carrier gas.
- the dopant in the second gallium nitride semiconductor layer is reduced while reducing the amount of hydrogen atoms mixed in the second gallium nitride semiconductor layer while suppressing the introduction of compensation impurities into the second gallium nitride semiconductor layer. Bonding with a hydrogen atom can be suppressed.
- the third gallium nitride based semiconductor layer is epitaxially grown using at least one gas selected from the group consisting of nitrogen gas, argon gas, helium gas and neon gas as a carrier gas. Since these gases are unlikely to be a hydrogen atom supply source, hydrogen gas is taken into the second gallium nitride semiconductor layer in the step of epitaxially growing the third gallium nitride semiconductor layer by using these gases as a carrier gas. Can be suppressed. Furthermore, in one aspect of the present invention, the third gallium nitride based semiconductor layer is epitaxially grown on the second gallium nitride based semiconductor layer.
- the second gallium nitride semiconductor layer is suppressed from being exposed to the outside, it is possible to suppress the deactivation of the dopant due to the incorporation of hydrogen atoms into the second gallium nitride semiconductor layer.
- the interface between the first gallium nitride semiconductor layer and the second gallium nitride semiconductor layer is sufficient. It functions electrically. Therefore, the drain leakage current in the nitride semiconductor element can be reduced.
- the third gallium nitride based semiconductor layer is preferably an n-type semiconductor layer.
- the drain leakage current can be further reduced.
- the first gallium nitride based semiconductor layer may be an n-type semiconductor layer.
- a pn junction can be formed at the interface between the first gallium nitride semiconductor layer and the second gallium nitride semiconductor layer.
- the second gallium nitride based semiconductor layer may contain at least one element selected from the group consisting of magnesium and zinc as a dopant. In this case, the second gallium nitride based semiconductor layer can be formed efficiently. Further, although magnesium and zinc tend to be deactivated by bonding with hydrogen atoms, according to one aspect of the present invention, drain leakage current is reduced even when magnesium and zinc are used as dopants. be able to.
- the ratio of the hydrogen concentration to the acceptor concentration in the second gallium nitride based semiconductor layer is preferably less than 0.8. In this case, deactivation of the dopant in the second gallium nitride based semiconductor layer is sufficiently suppressed, so that the second gallium nitride based semiconductor layer functions more electrically, and the drain leakage current is further increased. Can be reduced.
- the thickness of the third gallium nitride based semiconductor layer is preferably 50 to 500 nm.
- the third gallium nitride based semiconductor layer can be made to function more satisfactorily while maintaining the flatness of the surface of the third gallium nitride based semiconductor layer.
- the combination of the materials of the first to third gallium nitride semiconductor layers is n + -type GaN / when described as the third gallium nitride semiconductor layer / second gallium nitride semiconductor layer / first gallium nitride semiconductor layer.
- p-type GaN / n-type GaN, n + -type GaN / p-type AlGaN / n-type GaN it is n + -type InGaN / p-type GaN / n-type GaN or n + -type InGaN / p-type AlGaN / n-GaN good. According to these combinations, a good pn junction is provided, and the drain leakage current can be further reduced.
- a method of manufacturing a nitride semiconductor device includes a first gallium nitride based semiconductor layer for a drift layer, a second gallium nitride based semiconductor layer for a current blocking layer, and a contact layer.
- the aspect larger than the band gap of a layer may be sufficient.
- the nitride semiconductor device is a bipolar transistor including a collector layer, a base layer, and an emitter layer.
- the collector layer is a first gallium nitride based semiconductor layer
- the base layer is a second gallium nitride based semiconductor layer containing indium
- the emitter layer is a third gallium nitride based semiconductor layer, Also good.
- a method for manufacturing a nitride semiconductor device capable of reducing drain leakage current can be provided.
- a method for manufacturing a power control transistor having a vertical structure can be provided.
- FIG. 1 is a cross-sectional view schematically showing a nitride semiconductor device manufactured by the manufacturing method according to the present embodiment.
- the hetero field effect transistor 1 has a vertical transistor structure, and includes a support substrate 10, a semiconductor region 20, a source electrode 30, a drain electrode 40, an insulating film 50, and a gate electrode 60. Yes.
- the support substrate 10 is a conductive self-standing group III nitride substrate, and is a gallium nitride based semiconductor substrate such as a GaN substrate.
- the support substrate 10 has a front surface (main surface) 10a and a back surface (main surface) 10b facing each other.
- the semiconductor region 20 is disposed on the surface 10 a of the support substrate 10.
- the semiconductor region 20 includes a drift layer 20a, a current blocking layer 20b, a contact layer 20c, a channel layer 20d, and a carrier supply layer 20e.
- the drift layer 20a, the current blocking layer 20b, and the contact layer 20c are sequentially stacked on the surface 10a of the support substrate 10 to form a stacked body (semiconductor stack) 25, and a contact layer is formed on the surface side of the stacked body 25.
- An opening 27 is formed from 20c to the drift layer 20a via the current blocking layer 20b.
- the opening 27 extends in a predetermined direction along the surface 10a of the support substrate 10, and FIG. 1 shows a cut surface in a direction orthogonal to the predetermined direction.
- the opening 27 has a side surface 27a and a bottom surface 27b.
- the side surface 27a is composed of side surfaces of the drift layer 20a, the current blocking layer 20b, and the contact layer 20c, and is inclined toward the bottom surface 27b side.
- the bottom surface 27b of the opening 27 is composed of the drift layer 20a and is connected to the side surface 27a.
- the drift layer 20 a is disposed on the surface 10 a so as to cover the entire surface 10 a of the support substrate 10. A recess that forms the bottom of the opening 27 is formed on the surface of the drift layer 20a.
- the drift layer 20a is a gallium nitride based semiconductor layer made of GaN, AlGaN, InGaN, InAlGaN, or the like, for example, an n-type semiconductor layer containing an n-type dopant (Si or the like).
- the donor layer has a donor concentration of, for example, 5 ⁇ 10 15 to 2 ⁇ 10 16 cm ⁇ 3 .
- the thickness of the drift layer 20a is, for example, 3 to 12 ⁇ m in a region where no recess is formed.
- the current blocking layer (barrier layer) 20b is disposed on a region of the drift layer 20a where no recess is formed, and is in contact with the drift layer 20a.
- the current blocking layer 20b is a gallium nitride based semiconductor layer made of GaN, AlGaN, InGaN, InAlGaN, or the like. It can be sufficiently suppressed.
- the current blocking layer 20b is a p-type semiconductor layer containing at least one element selected from the group consisting of magnesium (Mg) and zinc (Zn) as a p-type dopant.
- a pn junction 29a is formed between the current blocking layer 20b and the drift layer 20a.
- the acceptor concentration of the current blocking layer 20b is preferably 1 ⁇ 10 17 cm ⁇ 3 or more and more preferably 1 ⁇ 10 18 cm ⁇ 3 or more from the viewpoint of effectively functioning the pn junction 29a and maintaining the drain breakdown voltage.
- the acceptor concentration of the current blocking layer 20b is preferably 5 ⁇ 10 18 cm ⁇ 3 or less from the viewpoint of suppressing an increase in on-resistance due to dopant diffusion from the current blocking layer 20b to the channel layer 20d.
- the ratio of the hydrogen concentration to the acceptor concentration (hydrogen concentration / acceptor concentration) in the current blocking layer 20b is preferably less than 0.8 and 0.7 or less from the viewpoint of further suppressing the decrease in the activity of the dopant. More preferred.
- the hydrogen concentration can be adjusted by the type of atmospheric gas and the growth temperature, and can be measured by secondary ion mass spectrometry (SIMS) or the like.
- the thickness of the current blocking layer 20b is preferably 0.5 ⁇ m or more from the viewpoint that the pn junction 29a functions effectively and maintains the drain breakdown voltage.
- the thickness of the current blocking layer 20b is preferably 2 ⁇ m or less, and more preferably 1 ⁇ m or less from the viewpoint of increasing the on-resistance of the transistor in proportion to the thickness of the current blocking layer 20b.
- the contact layer 20c is disposed on the current blocking layer 20b and is in contact with the current blocking layer 20b.
- the contact layer 20c is a gallium nitride based semiconductor layer made of GaN, AlGaN, InGaN, InAlGaN, or the like.
- the contact layer 20c is made of InGaN having a small band gap, it is possible to promote the diffusion of hydrogen atoms in the current blocking layer 20b. .
- the contact layer 20c is an n-type semiconductor layer containing an n-type dopant (Si or the like), for example.
- a pn junction 29b is formed between the contact layer 20c and the current blocking layer 20b.
- the donor concentration of the contact layer 20c is preferably 1 ⁇ 10 18 cm ⁇ 3 or more from the viewpoint of reducing the series resistance between the source electrode 30 and the channel layer 20d.
- the donor concentration of the contact layer 20c is preferably 1 ⁇ 10 19 cm ⁇ 3 or less, more preferably 5 ⁇ 10 18 cm ⁇ 3 or less, from the viewpoint of suppressing the introduction of compensated defects due to excessive donors.
- the contact layer 20c is an n-type semiconductor layer, if a compensation impurity such as oxygen is mixed, it contributes to an increase in carriers, and a carrier gas containing such a compensation impurity is used for forming the contact layer 20c. it can.
- the thickness of the contact layer 20c is preferably 0.05 ⁇ m (50 nm) or more from the viewpoint that the contact layer 20c functions sufficiently electrically even when the dopant diffuses from the current blocking layer 20b to the contact layer 20c. 0.2 ⁇ m (200 nm) or more is more preferable. From the viewpoint of maintaining the flatness of the surface of the contact layer 20c, the thickness of the contact layer 20c is preferably 0.5 ⁇ m (500 nm) or less, and more preferably 0.3 ⁇ m (300 nm) or less.
- the combination of the materials of the drift layer 20a, the current blocking layer 20b, and the contact layer 20c is n + -type GaN / p-type GaN / n-type GaN, n, when described as the contact layer 20c / current blocking layer 20b / drift layer 20a, n It is preferable that they are + type GaN / p type AlGaN / n type GaN, n + type InGaN / p type GaN / n type GaN, or n + type InGaN / p type AlGaN / n type GaN. According to these combinations, a good pn junction is provided, and the drain leakage current can be further reduced.
- the channel layer 20d is disposed on the side surface 27a and the bottom surface 27b of the opening 27 along the shape of the opening 27, and each of the drift layer 20a, the current blocking layer 20b, and the contact layer 20c exposed to the opening 27 is provided. It touches the side.
- the channel layer 20d covers a region near the opening 27 in the main surface of the contact layer 20c.
- the channel layer 20d is a gallium nitride based semiconductor layer made of GaN, AlGaN, InGaN, InAlGaN, or the like, and is non-doped, for example.
- the thickness of the channel layer 20d is, for example, 50 to 200 nm.
- the carrier supply layer (barrier layer) 20e is disposed on the channel layer 20d along the shape of the opening 27, and is in contact with the channel layer 20d.
- the carrier supply layer 20e is a group III nitride semiconductor layer made of AlN, GaN, AlGaN, InGaN, InAlGaN, or the like, and is non-doped, for example.
- the thickness of the carrier supply layer 20e is, for example, 5 to 30 nm.
- the band gap of the carrier supply layer 20e is preferably larger than the band gap of the channel layer 20d from the viewpoint of the function of forming a well-type potential at the interface between the carrier supply layer 20e and the channel layer 20d and confining the two-dimensional electron gas. .
- the combination of the material of the channel layer 20d and the carrier supply layer 20e is preferably InGaN / AlGaN, GaN / AlGaN, or AlGaN / AlN when described as the channel layer 20d / carrier supply layer 20e. These combinations provide good carrier generation and good channel formation.
- the source electrode 30 is formed on a region of the main surface of the contact layer 20c that is not covered with the channel layer 20d, and the side surface of the source electrode 30 is in contact with the ends of the channel layer 20d and the carrier supply layer 20e.
- the source electrode 30 for example, Ti / Al can be used.
- the drain electrode 40 is disposed on the support substrate 10 or the stacked body 25. In the present embodiment, the drain electrode 40 is disposed so as to cover the entire back surface 10 b of the support substrate 10.
- the drain electrode 40 for example, Ti / Al can be used.
- the insulating film 50 is disposed on the carrier supply layer 20 e along the shape of the opening 27, and forms a recess along the shape of the opening 27.
- the insulating film 50 is a silicon oxide film, for example, and the thickness of the insulating film 50 is, for example, about 10 nm.
- the gate electrode 60 is disposed in a recess formed by the insulating film 50.
- the gate electrode 60 for example, Ni / Au, Pt / Au, Pd / Au, or Mo / Au can be used.
- the hetero field effect transistor 1 when the carrier is an electron, the carrier from the source electrode 30 propagates in the channel layer 20d as a two-dimensional carrier gas.
- the voltage of the gate electrode 60 of the hetero field effect transistor 1 exceeds the threshold value, the carriers reach the drift layer 20a after passing through the channel layer 20d immediately below the gate electrode 60, and the drain electrode via the back surface 10b of the support substrate 10 40 is reached.
- the hetero field effect transistor 1 has a vertical structure.
- FIGS. 2 to 4 are cross-sectional views schematically showing the steps of the method for manufacturing a nitride semiconductor device according to this embodiment.
- the manufacturing method of the hetero field effect transistor 1 includes, for example, a first semiconductor layer forming step, a second semiconductor layer forming step, a third semiconductor layer forming step, an opening forming step, a regrowth step, an insulating film forming step, and an electrode forming step.
- the method for manufacturing the hetero field effect transistor 1 may include a step of lowering the temperature of the sample to, for example, room temperature (25 ° C.) after the third semiconductor layer forming step, for example, from the third semiconductor layer forming step to the opening forming step.
- the sample may be taken out from the growth furnace used in the third semiconductor layer forming step and cooled down, and then stored in the chamber used in the opening forming step.
- the semiconductor layer can be epitaxially grown by, for example, the MOCVD method.
- the source gas include trimethylgallium (gallium source), ammonia (nitrogen source), trimethylaluminum (aluminum source), and trimethylindium (indium source).
- the n-type dopant gas include silane.
- the p-type dopant gas include biscyclopentadienyl magnesium and diethyl zinc.
- the support substrate 10 is placed in a growth furnace 80a as shown in FIG.
- the surface 10a of the support substrate 10 may be cleaned by performing a heat treatment on the substrate 10.
- the heat treatment temperature is 1000 to 1100 ° C., for example.
- the heat treatment time is, for example, 5 minutes. By this heat treatment, moisture, oxygen, and the like on the surface 10a of the support substrate 10 can be desorbed.
- a source gas is supplied together with a carrier gas into the growth furnace 80a, and a semiconductor layer (first gallium nitride semiconductor layer) 70a is formed on the surface 10a of the support substrate 10 as a gallium nitride semiconductor layer for the drift layer 20a. Is epitaxially grown in the normal direction of the surface 10a.
- hydrogen gas is used as the carrier gas.
- the source gas is supplied together with the carrier gas into the growth furnace 80a, and the semiconductor layer (second gallium nitride semiconductor layer) 70b is used as the semiconductor as the gallium nitride semiconductor layer for the current blocking layer 20b. Epitaxial growth is performed on the layer 70a in the normal direction of the surface 10a.
- hydrogen gas is used as a carrier gas. By using the palladium permeable membrane, high-purity hydrogen gas can be easily introduced into the growth furnace 80a.
- the growth temperature in the second semiconductor layer forming step is 1000 ° C. or higher from the viewpoint of suppressing the hydrogen concentration of the semiconductor layer 70b and suppressing bonding of the dopant in the semiconductor layer 70b with hydrogen atoms, and is 1040 ° C. or higher. Preferably, 1050 ° C. or higher is more preferable.
- the upper limit of the growth temperature is 1100 ° C., for example.
- the growth pressure is preferably 50 to 760 Torr, and more preferably 200 to 760 Torr.
- the supply molar ratio (V / III) is preferably 500 to 10,000, for example, (amount of ammonia supplied) / (amount of supply of organic gallium raw material).
- the source gas is supplied together with the carrier gas into the growth furnace 80a, and the semiconductor layer (third gallium nitride semiconductor layer) 70c is formed as the semiconductor layer as the gallium nitride semiconductor layer for the contact layer 20c. Epitaxial growth is performed in the normal direction of the surface 10a on 70b. Thereby, as shown in FIG. 2, the laminated body 90a is obtained.
- the carrier gas is switched from the hydrogen gas in the second semiconductor layer forming step, and at least one inert gas selected from the group consisting of nitrogen gas, argon gas, helium gas, and neon gas is used.
- the growth temperature in the third semiconductor layer forming step is preferably 1000 to 1100 ° C., more preferably 1050 to 1100 ° C.
- the second semiconductor layer forming step and the third semiconductor layer forming step are preferably performed continuously.
- the semiconductor layer 70b is preferably maintained at 1000 ° C. or higher in a series of processes of the second semiconductor layer forming step and the third semiconductor layer forming step.
- the dopant is dissociated from hydrogen atoms in the current blocking layer 20b. Can be maintained.
- the growth pressure is preferably 50 to 760 Torr, and more preferably 200 to 760 Torr.
- the supply molar ratio (V / III) is preferably 500 to 10,000, for example, (amount of ammonia supplied) / (amount of supply of organic gallium raw material).
- hydrogen gas is used in the second semiconductor layer forming step, and at least one inert gas selected from the group consisting of nitrogen gas, argon gas, helium gas, and neon gas in the third semiconductor layer forming step.
- an inert gas such as nitrogen gas
- compensation impurities such as oxygen are likely to be mixed into the current blocking layer 20b.
- the dopant in the current blocking layer 20b is compensated by the mixed compensation impurities, the acceptor concentration of the current blocking layer 20b is lowered, and the occurrence of a drain leak failure is promoted.
- the dopant in the current blocking layer 20b can be reduced while reducing the hydrogen concentration of the current blocking layer 20b by forming the current blocking layer 20b at a high temperature of 1000 ° C. or higher. Bonding with a hydrogen atom can be suppressed.
- the current blocking layer 20b by forming the current blocking layer 20b at a high temperature using hydrogen gas as a carrier gas, it is possible to reduce the hydrogen concentration of the current blocking layer 20b while preventing the compensation impurities from entering the current blocking layer 20b. However, it can suppress that the dopant in the electric current block layer 20b couple
- the raw material when hydrogen gas is used, the raw material can be diffused more efficiently than when inert gas such as nitrogen gas is used.
- inert gas such as nitrogen gas
- the opening forming step After the stacked body 90a is taken out from the growth furnace 80a, the stacked body 90a is placed in a chamber 80b of an etching apparatus as shown in FIG. Next, an opening 27 extending from the semiconductor layer 70c to the semiconductor layer 70a through the semiconductor layer 70b is formed on the surface side of the stacked body 90a including the semiconductor layer 70a, the semiconductor layer 70b, and the semiconductor layer 70c, and drifting is performed. A stacked body 90b having the layer 20a, the current blocking layer 20b, the contact layer 20c, and the opening 27 is obtained.
- the opening forming step for example, after a silicon oxide film is formed on the semiconductor layer 70c by a sputtering method, the silicon oxide film is patterned, and a mask layer having a pattern in which a region for forming the opening 27 is exposed (not shown). Z). Next, reactive ion etching or the like is performed through the mask layer, and the semiconductor layer 70c, the semiconductor layer 70b, and a part of the semiconductor layer 70a are sequentially removed to form the opening 27.
- the mask layer can be removed by wet etching.
- the regrowth process includes a channel layer forming process and a carrier supply layer forming process.
- the stack 90b is subjected to an atmosphere containing ammonia gas (for example, a flow rate of 16 slm) and hydrogen gas (for example, a flow rate of 4 slm).
- Heat treatment may be performed. Thereby, the rearrangement of atoms becomes possible on the surface of the stacked body 90b which is the base of the channel layer 20d.
- the heat treatment temperature is 1000 to 1100 ° C., for example.
- the furnace pressure is, for example, 50 to 760 Torr.
- the heat treatment time is, for example, 5 minutes.
- the channel layer forming step first, the stacked body 90b is taken out from the chamber 80b, and then the stacked body 90b is disposed again in the growth furnace 80a.
- the channel layer 20 d is formed along the shape of the opening 27 so as to contact the side surface 27 a and the bottom surface 27 b of the opening 27 and the main surface of the contact layer 20 c.
- hydrogen gas is used as the carrier gas.
- the growth temperature is, for example, 950 to 1050 ° C.
- the growth pressure is, for example, 50 to 760 Torr
- the supply molar ratio (V / III) is, for example, 500 to 10,000.
- the carrier supply layer 20e is formed on the channel layer 20d so as to cover the channel layer 20d along the shape of the opening 27.
- hydrogen gas is used as the carrier gas.
- the growth temperature is, for example, 1000 to 1150 ° C.
- the growth pressure is, for example, 50 to 200 Torr
- the supply molar ratio (V / III) is, for example, 500 to 10,000.
- the insulating film 50 is formed on the carrier supply layer 20e so as to cover the entire surface of the carrier supply layer 20e along the shape of the opening 27. Thereby, a recess along the shape of the opening 27 is formed by the insulating film 50.
- the source electrode 30 is formed on the outer edge portion.
- the drain electrode 40 is formed on the support substrate 10 or the stacked body 25. In the present embodiment, the drain electrode 40 is formed on the back surface 10 b opposite to the front surface 10 a of the support substrate 10. Further, the gate electrode 60 is formed on the side surface 27 a and the bottom surface 27 b of the opening 27 so as to fill the recess formed by the insulating film 50.
- the current blocking layer 20b which is a p-type semiconductor layer, is epitaxially grown at 1000 ° C. or higher using hydrogen gas as a carrier gas.
- the contact layer 20c is epitaxially grown using at least one inert gas selected from the group consisting of nitrogen gas, argon gas, helium gas and neon gas as a carrier gas. Yes. Since these gases are unlikely to supply hydrogen atoms, the use of these gases as carrier gases can suppress the incorporation of hydrogen atoms into the current blocking layer 20b in the third semiconductor layer forming step.
- the contact layer 20c is epitaxially grown on the current blocking layer 20b.
- the current blocking layer 20b formed while suppressing the bonding of the dopant with hydrogen atoms is suppressed from being exposed to the outside, so that the hydrogen atoms are taken into the current blocking layer 20b and the dopant is deactivated. This can be suppressed.
- the acceptor concentration of the current blocking layer 20b is suppressed from being insufficient, the pn junction 29a of the drift layer 20a and the current blocking layer 20b functions sufficiently electrically. Therefore, the drain leakage current in the hetero field effect transistor 1 can be reduced.
- the cap layer acts as a barrier against hydrogen atoms. . Therefore, hydrogen atoms are inhibited from being released from the p-type semiconductor layer to the outside of the device, and it is difficult to sufficiently function the current blocking layer 20b for suppressing drain leakage.
- the cap layer is an n-type semiconductor layer or a non-doped semiconductor layer, such a phenomenon is remarkably confirmed. This phenomenon is caused by hydrogen atoms diffusing while hopping between the most stable arrangement positions that change depending on the Fermi level in a heat-treated semiconductor (for example, GaN).
- the current blocking layer 20b is capped with the contact layer 20c in a state in which the dopant is suppressed from bonding with hydrogen atoms, the current blocking layer 20b is not required for heat treatment such as activation annealing. It can suppress that the dopant in it deactivates.
- two-dimensional electron gas is generated at the interface between the channel layer 20d / carrier supply layer 20e formed on the side surface 27a of the opening 27 due to piezo polarization accompanying lattice distortion.
- the gas carries a current from the contact layer 20c to the drift layer 20a.
- the two-dimensional electron gas at the interface of the channel layer 20d / carrier supply layer 20e is depleted due to insufficient increase in potential of the current blocking layer 20b. Will not.
- a drain leak failure occurs in the transistor operation, and the pinch-off characteristics are degraded.
- the acceptor concentration of the current blocking layer 20b is suppressed from being insufficient, the drain leakage current can be reduced, and the deterioration of the pinch-off characteristic can be suppressed.
- the dopant in the current blocking layer 20b when the dopant in the current blocking layer 20b is deactivated, it is conceivable to increase the dopant doping amount in the current blocking layer 20b from the viewpoint of increasing the acceptor concentration.
- the dopant easily diffuses from the current blocking layer 20b to the interface of the channel layer 20d / carrier supply layer 20e, the amount of two-dimensional electron gas at the interface decreases, and the on-resistance during the on-operation of the transistor Will increase.
- the dopant in the current blocking layer 20b since the dopant in the current blocking layer 20b is suppressed from being deactivated, the doping amount of the dopant can be kept as small as possible. Therefore, in this embodiment, the drain leakage current can be reduced while suppressing an increase in on-resistance during the on-operation of the transistor.
- the present invention is not limited to the above-described embodiment, and various modifications can be made.
- the nitride semiconductor device is not limited to the above transistor, and may be an npn bipolar transistor as shown in FIGS.
- the bipolar transistor 100 shown in FIG. 5 includes a support substrate 110, a buffer layer 120, a collector layer (first gallium nitride semiconductor layer) 130, a base layer (second gallium nitride semiconductor layer) 140, and an emitter layer (third gallium nitride).
- the support substrate 110 is a self-supporting group III nitride substrate such as a GaN substrate.
- the buffer layer 120 is disposed on the surface 110 a of the support substrate 110.
- the buffer layer 120 is a gallium nitride based semiconductor layer containing an n-type dopant such as Si, for example, an n-type GaN layer.
- the collector layer 130 is disposed on the main surface of the buffer layer 120.
- the collector layer 130 is a gallium nitride based semiconductor layer containing an n-type dopant such as Si, for example, an n-type GaN layer.
- the base layer 140 is disposed on the main surface of the collector layer 130.
- the base layer 140 is a gallium nitride based semiconductor layer containing indium, and is a p-type semiconductor layer containing a p-type dopant such as Mg and Zn.
- the base layer 140 is, for example, a p-type InGaN layer.
- the emitter layer 150 is disposed on the main surface of the base layer 140.
- the emitter layer 150 is a gallium nitride-based semiconductor layer containing n-type dopant such as Si, for example, n + -type GaN layer.
- the collector electrode 160 is disposed on the back surface 110 b of the support substrate 110.
- Base electrode 170 is disposed on the main surface of base layer 140 so as to be separated from emitter layer 150.
- the emitter electrode 180 is disposed on the main surface of the emitter layer 150.
- the manufacturing method of the bipolar transistor 100 includes a step of epitaxially growing the collector layer 130 on the support substrate 110 via the buffer layer 120 and a base layer 140 on the collector layer 130 at 1000 ° C. or higher using hydrogen gas as a carrier gas. And a step of epitaxially growing the emitter layer 150 on the base layer 140 using at least one inert gas selected from the group consisting of nitrogen gas, argon gas, helium gas and neon gas as a carrier gas. . According to the bipolar transistor 100 manufactured by such a manufacturing method, the drain leakage current can be reduced similarly to the hetero field effect transistor 1.
- the bipolar transistor 200 shown in FIG. 6 includes a buffer layer 220, a collector layer (first gallium nitride semiconductor layer) 230, a base layer (second gallium nitride semiconductor layer) 240, an emitter layer (on the main surface of a support substrate 210).
- a third gallium nitride based semiconductor layer) 250 and an emitter cap layer 260 are stacked in this order.
- the support substrate 210 is a self-supporting group III nitride substrate such as a GaN substrate.
- the buffer layer 220 is a gallium nitride based semiconductor layer made of GaN or the like.
- the thickness of the buffer layer 220 is, for example, 2.0 ⁇ m.
- the collector layer 230 is formed by laminating a sub-collector layer 230a, a collector layer 230b, and a collector layer 230c in this order on the main surface of the support substrate 210.
- the subcollector layer 230a is a gallium nitride based semiconductor layer made of GaN or the like and contains, for example, an n-type dopant (Si or the like).
- the donor concentration of the subcollector layer 230a is, for example, 2.0 ⁇ 10 18 cm ⁇ 3 .
- the thickness of the subcollector layer 230a is, for example, 500 nm.
- the collector layer 230b is a gallium nitride based semiconductor layer made of GaN or the like and contains, for example, an n-type dopant (Si or the like).
- the donor concentration of the collector layer 230b is, for example, 2.0 ⁇ 10 17 cm ⁇ 3 .
- the thickness of the collector layer 230b is, for example, 200 nm.
- Collector layer 230c is a composition gradient layer indium composition is tilted, for example, gallium nitride indium composition In 0.03 Ga 0.97 N base layer 240 side from the collector layer 230b side GaN is inclined semiconductor layer It is.
- the collector layer 230c contains, for example, an n-type dopant (Si or the like), and the donor concentration of the collector layer 230c is, for example, 2.0 ⁇ 10 18 cm ⁇ 3 .
- the thickness of the collector layer 230c is, for example, 30 nm.
- the base layer 240 is a composition gradient layer having a gradient indium composition.
- the indium composition is changed from In 0.03 Ga 0.97 N on the collector layer 230 side to In 0.06 Ga 0.94 N on the emitter layer 250 side.
- Base layer 240 is a p-type semiconductor layer containing a p-type dopant (Mg, Zn, etc.), the acceptor concentration in the base layer 240 is, for example, 2.5 ⁇ 10 18 cm -3.
- the thickness of the base layer 240 is, for example, 100 nm.
- the emitter layer 250 is a composition gradient layer indium composition is tilted, for example, the base layer 240 side of an In 0.06 Ga 0.94 gallium nitride GaN indium composition of the emitter cap layer 260 side from N are inclined semiconductor Is a layer.
- the emitter layer 250 contains, for example, an n-type dopant (Si or the like), and the donor concentration of the emitter layer 250 is, for example, 1.0 ⁇ 10 19 cm ⁇ 3 .
- the thickness of the emitter layer 250 is, for example, 30 nm.
- the emitter cap layer 260 is a gallium nitride based semiconductor layer made of GaN or the like and contains, for example, an n-type dopant (Si or the like).
- the donor concentration of the emitter cap layer 260 is, for example, 1.0 ⁇ 10 19 cm ⁇ 3 .
- the thickness of the emitter cap layer 260 is, for example, 70 nm.
- the manufacturing method of the bipolar transistor 200 includes a step of epitaxially growing the collector layer 230 on the support substrate 210 through the buffer layer 220 and a base layer 240 on the collector layer 230 at 1000 ° C. or higher using hydrogen gas as a carrier gas. And a step of epitaxially growing the emitter layer 250 on the base layer 240 using at least one inert gas selected from the group consisting of nitrogen gas, argon gas, helium gas and neon gas as a carrier gas. . According to the bipolar transistor 200 manufactured by such a manufacturing method, the drain leakage current can be reduced as in the hetero field effect transistor 1.
- an n-type GaN layer drift layer, thickness: 5 ⁇ m, Si doping amount: 1 ⁇ 10 16 cm ⁇ 3
- p-type GaN layer current blocking layer, thickness: 0.5 ⁇ m, Mg doping amount: 5
- n + -type GaN layer contact layer, thickness: 0.2 ⁇ m, Si doping amount: 1 ⁇ 10 18 cm ⁇ 3
- the growth conditions of each semiconductor layer are the same except for the dopant type, dopant doping amount, film formation time, etc., and after each semiconductor layer is formed continuously to form a stacked body, the stacked body is cooled to room temperature. I let you. No heat treatment (activation annealing) was performed after the stack was formed.
- Example 1 An n-type GaN layer and a p-type GaN layer are formed in this order on a gallium nitride substrate using purified hydrogen as a carrier gas, and then an n + -type GaN layer is formed on the p-type GaN layer using nitrogen gas as a carrier gas.
- a laminate was obtained in the same manner as in Comparative Example 1 except that the film was formed. The ratio of the hydrogen concentration to the acceptor concentration in the laminate was 0.7.
- Electrochemical CV (ECV) measurement was performed to measure the capacitance of each laminate of Comparative Example 1 and Example 1 while etching with a KOH solution from the n + -type GaN layer to the p-type GaN layer on the surface.
- the donor / acceptor concentration was measured.
- FIG. 7 shows the measurement results of ECV measurement.
- FIG. 7A shows the measurement result of Comparative Example 1
- FIG. 7B shows the measurement result of Example 1.
- the vertical axis represents “acceptor concentration (Na) ⁇ donor concentration (Nd)” (cm ⁇ 3 ), and the horizontal axis represents the measurement depth ( ⁇ m) from the surface of the laminate. In the vertical axis, for example, "2.0E + 18" represents the 2.0 ⁇ 10 18.
- the laminate produced in the same manner as in Comparative Example 1 was in a nitrogen atmosphere and in an atmosphere in which a certain amount of oxygen (flow rate ratio 1 to 20%) was added to nitrogen. After heat treatment at 700 ° C., ECV measurement was performed in the same manner as described above. As a result, it was confirmed that the acceptor concentration of the p-type GaN layer hardly changed compared with that before the heat treatment.
- Such a phenomenon is a state in which the p-type GaN layer is capped with the n + -type GaN layer, and thus heat treatment is performed, but hydrogen atoms in the p-type GaN layer are blocked by the n + -type GaN layer and stacked. This is presumably due to the fact that it was not released outside the body.
- the n + type GaN layer and the p type GaN layer were formed in this order on the gallium nitride substrate, and then the n + type GaN layer was not formed.
- ECV measurement was performed on the obtained laminate in the same manner as described above.
- the acceptor concentration was about 2.0 ⁇ 10 17 cm ⁇ 3 in a state where no heat treatment was applied, and was 1/10 or less of the Mg doping amount. .
- Such a phenomenon is presumed to be due to the fact that most of Mg in the p-type GaN layer is passivated by hydrogen atoms.
- the stacked body with the p-type GaN layer exposed on the surface is heat-treated at 700 ° C. in a nitrogen atmosphere and in an atmosphere in which a certain amount of oxygen is added to nitrogen (flow rate ratio: 1 to 20%). Then, ECV measurement was performed in the same manner as described above. As a result, the acceptor concentration was about 4.5 ⁇ 10 18 cm ⁇ 3 , which was equivalent to the Mg doping amount. Such a phenomenon is presumed to be due to the Mg in the p-type GaN layer being dissociated from the hydrogen atoms and released to the outside of the stacked body by the heat treatment.
- Example 1 In the measurement result of Example 1 (FIG. 7B), the donor profile of the n + -type GaN layer behaves in the same manner as in Comparative Example 1, but the acceptor concentration of the p-type GaN layer is 4.0 ⁇ 10 18. It was about cm ⁇ 3 , which was confirmed to be higher than the acceptor concentration of Comparative Example 1 of 1.5 ⁇ 10 18 cm ⁇ 3 .
- Such a phenomenon is caused in the stacked body of Example 1 in which the p-type GaN layer is capped with the n + -type GaN layer in a state where Mg is dissociated from the hydrogen atom while the hydrogen concentration is reduced, and in the subsequent steps. It is presumed that the activity of Mg in the p-type GaN layer is maintained high because hydrogen atoms are prevented from being taken into the p-type GaN layer when the temperature is lowered.
- SYMBOLS 1 Hetero field effect transistor (nitride semiconductor element) 10, 110, 210 ... Support substrate (III group nitride substrate), 20a ... Drift layer, 20b ... Current blocking layer, 20c ... Contact layer, 20d ... Channel layer, 20e ... carrier supply layer, 25 ... laminate, 27 ... opening, 27a ... side face, 30 ... source electrode, 40 ... drain electrode, 50 ... insulating film, 60 ... gate electrode, 70a ... semiconductor layer (first gallium nitride system) Semiconductor layer), 70b ... Semiconductor layer (second gallium nitride based semiconductor layer), 70c ...
- Semiconductor layer (third gallium nitride based semiconductor layer), 100, 200 ... Bipolar transistor (nitride semiconductor element), 130, 230 ... Collector Layer (first gallium nitride based semiconductor layer), 140, 240... Base layer (second gallium nitride based semiconductor layer), 150, 250. Jitter layer (third gallium nitride-based semiconductor layer).
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Abstract
Description
まず、2インチ角の導電性の窒化ガリウム基板(GaN基板)を成長炉内に設置した後、1030℃、100Torr、アンモニア及び水素雰囲気中で基板クリーニングを実施した。
キャリアガスとして純化水素を用いてn型GaN層及びp型GaN層を窒化ガリウム基板上にこの順に成膜した後、キャリアガスとして窒素ガスを用いてn+型GaN層をp型GaN層上に成膜したことを除き比較例1と同様にして積層体を得た。当該積層体におけるアクセプタ濃度に対する水素濃度の比は、0.7であった。
Claims (9)
- 第1窒化ガリウム系半導体層を自立III族窒化物基板上にエピタキシャル成長させる工程と、
水素ガスをキャリアガスとして用いて、p型半導体層である第2窒化ガリウム系半導体層を前記第1窒化ガリウム系半導体層上に1000℃以上でエピタキシャル成長させる工程と、
窒素ガス、アルゴンガス、ヘリウムガス及びネオンガスからなる群より選ばれる少なくとも一種のガスをキャリアガスとして用いて、第3窒化ガリウム系半導体層を前記第2窒化ガリウム系半導体層上にエピタキシャル成長させる工程と、を備える、窒化物半導体素子の製造方法。 - 前記第3窒化ガリウム系半導体層がn型半導体層である、請求項1に記載の窒化物半導体素子の製造方法。
- 前記第1窒化ガリウム系半導体層がn型半導体層である、請求項1又は2に記載の窒化物半導体素子の製造方法。
- 前記第2窒化ガリウム系半導体層が、マグネシウム及び亜鉛からなる群より選ばれる少なくとも一種の元素をドーパントとして含有する、請求項1~3のいずれか一項に記載の窒化物半導体素子の製造方法。
- 前記第2窒化ガリウム系半導体層におけるアクセプタ濃度に対する水素濃度の比が0.8未満である、請求項1~4のいずれか一項に記載の窒化物半導体素子の製造方法。
- 前記第3窒化ガリウム系半導体層の厚さが50~500nmである、請求項1~5のいずれか一項に記載の窒化物半導体素子の製造方法。
- 前記第1~第3窒化ガリウム系半導体層の材料の組み合わせが、前記第3窒化ガリウム系半導体層/前記第2窒化ガリウム系半導体層/前記第1窒化ガリウム系半導体層として記載したときに、n+型GaN/p型GaN/n型GaN、n+型GaN/p型AlGaN/n型GaN、n+型InGaN/p型GaN/n型GaN又はn+型InGaN/p型AlGaN/n型GaNである、請求項1~6のいずれか一項に記載の窒化物半導体素子の製造方法。
- ドリフト層のための前記第1窒化ガリウム系半導体層、電流ブロック層のための前記第2窒化ガリウム系半導体層、及び、コンタクト層のための前記第3窒化ガリウム系半導体層に、前記第3窒化ガリウム系半導体層から前記第2窒化ガリウム系半導体層を介して前記第1窒化ガリウム系半導体層に至る開口部を形成して、前記ドリフト層、前記電流ブロック層及び前記コンタクト層並びに前記開口部を有する積層体を得る工程と、
窒化ガリウム系半導体からなるチャネル層を前記開口部の側面上にエピタキシャル成長させる工程と、
III族窒化物半導体からなるキャリア供給層を前記チャネル層上にエピタキシャル成長させる工程と、
絶縁膜を前記キャリア供給層上に形成する工程と、
ゲート電極を前記絶縁膜上に形成し、ソース電極を前記積層体上に形成し、前記自立III族窒化物基板又は前記積層体上にドレイン電極を形成する工程と、を更に備え、
前記キャリア供給層のバンドギャップが前記チャネル層のバンドギャップよりも大きい、請求項1~7のいずれか一項に記載の窒化物半導体素子の製造方法。 - 当該窒化物半導体素子が、コレクタ層、ベース層及びエミッタ層を備えるバイポーラトランジスタであり、
前記コレクタ層が、前記第1窒化ガリウム系半導体層であり、
前記ベース層が、インジウムを含有する前記第2窒化ガリウム系半導体層であり、
前記エミッタ層が、前記第3窒化ガリウム系半導体層である、請求項1~6のいずれか一項に記載の窒化物半導体素子の製造方法。
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WO2014057748A1 (ja) * | 2012-10-12 | 2014-04-17 | 住友電気工業株式会社 | Iii族窒化物複合基板およびその製造方法、ならびにiii族窒化物半導体デバイスの製造方法 |
US9923063B2 (en) | 2013-02-18 | 2018-03-20 | Sumitomo Electric Industries, Ltd. | Group III nitride composite substrate and method for manufacturing the same, laminated group III nitride composite substrate, and group III nitride semiconductor device and method for manufacturing the same |
JP6216524B2 (ja) * | 2013-03-18 | 2017-10-18 | トランスフォーム・ジャパン株式会社 | 半導体装置の製造方法及び半導体装置 |
KR20150016667A (ko) * | 2013-08-05 | 2015-02-13 | 서울반도체 주식회사 | 질화물계 전계효과 트랜지스터 및 그 제조방법 |
JP2015032744A (ja) | 2013-08-05 | 2015-02-16 | 株式会社東芝 | 半導体装置および半導体装置の製造方法 |
KR101758082B1 (ko) * | 2013-12-30 | 2017-07-17 | 한국전자통신연구원 | 질화물 반도체 소자의 제조 방법 |
US9761709B2 (en) | 2014-08-28 | 2017-09-12 | Hrl Laboratories, Llc | III-nitride transistor with enhanced doping in base layer |
US9865725B2 (en) * | 2015-04-14 | 2018-01-09 | Hrl Laboratories, Llc | III-nitride transistor with trench gate |
JP2016225477A (ja) * | 2015-05-29 | 2016-12-28 | サンケン電気株式会社 | 半導体装置 |
JP6687831B2 (ja) * | 2015-10-30 | 2020-04-28 | 富士通株式会社 | 化合物半導体装置及びその製造方法 |
WO2018063489A1 (en) | 2016-09-30 | 2018-04-05 | Hrl Laboratories, Llc | Doped gate dielectric materials |
CN106409901B (zh) * | 2016-10-27 | 2019-10-11 | 苏州捷芯威半导体有限公司 | 一种半导体器件及其制备方法 |
JP6327378B1 (ja) * | 2017-04-03 | 2018-05-23 | 富士電機株式会社 | 半導体装置および半導体装置の製造方法 |
CN111354777A (zh) * | 2018-12-24 | 2020-06-30 | 东南大学 | 一种低导通电阻的异质结半导体器件 |
US20220336600A1 (en) * | 2021-04-20 | 2022-10-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Ohmic electrode for two-dimensional carrier gas (2dcg) semiconductor device |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10135575A (ja) * | 1996-09-06 | 1998-05-22 | Toshiba Corp | 窒化物系半導体素子及びその製造方法 |
JPH11150296A (ja) * | 1997-11-19 | 1999-06-02 | Toshiba Corp | 窒化物系半導体素子及びその製造方法 |
JP2000315818A (ja) * | 1999-04-30 | 2000-11-14 | Sanken Electric Co Ltd | 半導体装置の製造方法 |
JP2010062254A (ja) * | 2008-09-02 | 2010-03-18 | Hitachi Cable Ltd | 窒化物半導体素子 |
JP2010087328A (ja) * | 2008-10-01 | 2010-04-15 | Panasonic Corp | 発光装置およびその製造方法 |
JP2010098076A (ja) * | 2008-10-15 | 2010-04-30 | Sumitomo Electric Device Innovations Inc | 半導体装置の製造方法 |
JP2010206020A (ja) * | 2009-03-04 | 2010-09-16 | Panasonic Corp | 半導体装置 |
JP2011003882A (ja) * | 2009-05-20 | 2011-01-06 | Ngk Insulators Ltd | エピタキシャル基板の製造方法 |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4916671B2 (ja) | 2005-03-31 | 2012-04-18 | 住友電工デバイス・イノベーション株式会社 | 半導体装置 |
TW200711171A (en) * | 2005-04-05 | 2007-03-16 | Toshiba Kk | Gallium nitride based semiconductor device and method of manufacturing same |
-
2011
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Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10135575A (ja) * | 1996-09-06 | 1998-05-22 | Toshiba Corp | 窒化物系半導体素子及びその製造方法 |
JPH11150296A (ja) * | 1997-11-19 | 1999-06-02 | Toshiba Corp | 窒化物系半導体素子及びその製造方法 |
JP2000315818A (ja) * | 1999-04-30 | 2000-11-14 | Sanken Electric Co Ltd | 半導体装置の製造方法 |
JP2010062254A (ja) * | 2008-09-02 | 2010-03-18 | Hitachi Cable Ltd | 窒化物半導体素子 |
JP2010087328A (ja) * | 2008-10-01 | 2010-04-15 | Panasonic Corp | 発光装置およびその製造方法 |
JP2010098076A (ja) * | 2008-10-15 | 2010-04-30 | Sumitomo Electric Device Innovations Inc | 半導体装置の製造方法 |
JP2010206020A (ja) * | 2009-03-04 | 2010-09-16 | Panasonic Corp | 半導体装置 |
JP2011003882A (ja) * | 2009-05-20 | 2011-01-06 | Ngk Insulators Ltd | エピタキシャル基板の製造方法 |
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