WO2012097661A1 - 基站时钟装置、基站***和时钟同步方法 - Google Patents
基站时钟装置、基站***和时钟同步方法 Download PDFInfo
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- WO2012097661A1 WO2012097661A1 PCT/CN2011/084394 CN2011084394W WO2012097661A1 WO 2012097661 A1 WO2012097661 A1 WO 2012097661A1 CN 2011084394 W CN2011084394 W CN 2011084394W WO 2012097661 A1 WO2012097661 A1 WO 2012097661A1
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- clock signal
- signal
- clock
- locked loop
- synchronization
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- 238000000034 method Methods 0.000 title claims abstract description 25
- 230000001360 synchronised effect Effects 0.000 claims description 18
- 239000013078 crystal Substances 0.000 claims description 5
- 238000011084 recovery Methods 0.000 claims description 5
- 239000000284 extract Substances 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 15
- 230000009977 dual effect Effects 0.000 description 9
- 230000000694 effects Effects 0.000 description 4
- 230000006870 function Effects 0.000 description 4
- 238000010295 mobile communication Methods 0.000 description 3
- 230000002159 abnormal effect Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
- 238000009432 framing Methods 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/04—Speed or phase control by synchronisation signals
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W56/00—Synchronisation arrangements
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/22—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop
- H03L7/23—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop with pulse counters or frequency dividers
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
- H04J3/0688—Change of the master or reference, e.g. take-over or failure of the master
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W88/00—Devices specially adapted for wireless communication networks, e.g. terminals, base stations or access point devices
- H04W88/08—Access point devices
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W56/00—Synchronisation arrangements
- H04W56/001—Synchronization between nodes
- H04W56/0015—Synchronization between nodes one node acting as a reference for the others
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W56/00—Synchronisation arrangements
- H04W56/0035—Synchronisation arrangements detecting errors in frequency or phase
Definitions
- Embodiments of the present invention relate to the field of mobile communications, and more particularly, to a base station clock device, a base station system, and a clock synchronization method. Background technique
- a base station capable of supporting both GSM (Global System for Mobile Communications) and UMTS (Universal Mobile Telecommunications System) wireless systems is called a GU dual-mode base station.
- GSM Global System for Mobile Communications
- UMTS Universal Mobile Telecommunications System
- the BBU Base Band Unit
- the BBU includes the main control board of each system and the board of the Common Public Radio Interface (CRI).
- the board can be integrated with the main control board (such as the GSM system) or integrated with the service processing board (such as the UMTS system).
- the system clock of the multimode RF module must be synchronized with the clock of the master system of the two systems. Otherwise, the out-of-step will occur on the CPRI interface, and the RF processing part cannot work normally. problem.
- Embodiments of the present invention provide a base station clock device, a base station system, and a clock synchronization method, which are capable of synchronizing system clocks of different standards.
- an embodiment of the present invention provides a base station clock device, including: a first standard clock module based on a first standard, configured to generate a first frequency synchronization clock signal and a first phase synchronization signal according to a first external clock signal And a first system clock signal, wherein the first system clock signal includes the first frequency synchronization clock signal and the first phase synchronization signal; a second standard clock module based on a second system different from the first system, for The one-system clock module receives the first frequency synchronization clock signal and the first phase synchronization signal, and generates a second system clock signal, wherein the second system clock signal includes the first frequency synchronization clock signal and the first phase synchronization signal.
- an embodiment of the present invention provides a base station system, including the foregoing base station clock device and radio frequency module device.
- the radio frequency module device is configured to receive a first system clock signal and a second system clock signal from the base station clock device, and select one of the first system clock signal and the second system clock signal as a local clock frequency recovery Input.
- an embodiment of the present invention provides a method for synchronizing a clock in a base station clock device, where the base station clock device includes a first standard clock module based on a first system and a second system based on a second standard different from the first system.
- a two-standard clock module comprising: generating, by the first standard clock module, a first frequency synchronization clock signal, a first phase synchronization signal, and a first system clock signal according to the first external clock signal, wherein the first system clock signal The first frequency synchronization clock signal and the first phase synchronization signal are included; the first frequency synchronization clock signal and the first phase synchronization signal are received from the first standard clock module by the second standard clock module, and the second system clock signal is generated The second system clock signal includes the first frequency synchronization clock signal and the first phase synchronization signal.
- the clock module of the multiple systems in the embodiment of the present invention can generate a system clock signal including the same frequency synchronization clock signal and phase synchronization signal, so that the frequency and phase between the system clock signals generated by the clock modules of different standards are generated.
- a system clock signal including the same frequency synchronization clock signal and phase synchronization signal, so that the frequency and phase between the system clock signals generated by the clock modules of different standards are generated.
- Fig. 1 is a block diagram showing the structure of a dual mode GU macro base station.
- FIG. 2 is a schematic structural diagram showing a dual mode distributed GU base station.
- FIG. 3 is a schematic block diagram showing a base station clock device according to an embodiment of the present invention.
- FIG. 4 is a schematic block diagram showing an example of a base station clock device according to an embodiment of the present invention.
- FIG. 5 is a schematic block diagram showing an example of a base station clock device according to an embodiment of the present invention.
- FIG. 6 is a schematic block diagram showing a base station system according to an embodiment of the present invention.
- Fig. 7 is a schematic block diagram showing an example of a dual mode radio frequency module device according to an embodiment of the present invention.
- FIG. 8 is a flowchart of a clock synchronization method in a multimode base station system according to an embodiment of the present invention. detailed description
- the embodiments of the present invention can be applied to multi-mode scenarios composed of different standards, and are applicable to GSM, UMTS, CDMA (Code Division Multiple Access), WiMAX (Worldwide Interoperability for Microwave Access) a multimode base station formed by combining various standards such as LTE (Long Term Evolution), such as, but not limited to, a dual mode base station composed of two standards of GSM and UMTS, and a dual mode base station composed of two standards of UMTS and CDMA.
- LTE Long Term Evolution
- FIG. 1 is a schematic structural diagram showing a dual mode GU macro base station.
- 2 is a block diagram showing the structure of a dual mode distributed GU base station.
- the two multimode base stations shown in Figures 1 and 2 are equipped with common mode RF modules (multimode RF modules) to support multiple modes.
- the RF module and the BBU are connected through a CPRI link.
- the CPRI links of the various systems will converge together, so it is necessary to ensure strict frequency synchronization and phase synchronization of the two system clocks, that is, the CPRI operating clock needs to be strictly synchronized.
- the CPRI framing is performed based on the frame number of the frame timing (FN; Frame Number)
- FN Frame Number
- the frame timing (or frame number) of the CPRI must be strictly synchronized between the modes of the multimode base station. For this reason, it is required that the system clocks for wireless services in the various modes in the BBU can be synchronized.
- FIG. 3 is a schematic block diagram showing a base station clock device 1000 in accordance with an embodiment of the present invention.
- the base station clock device 1000 includes a first system clock module 1100 and a second system clock module 1200.
- the first mode clock module 1100 is based on the first system
- the second mode clock module 1200 is based on a second system different from the first system.
- the first standard clock module 1100 can receive the first external clock signal Sl from the outside.
- the first external clock signal S1 may be a GPS (Global Positioning System) clock, an E1 clock, an IP (Internet Protocol) clock, or a BITS (Building Integrated Timing Supply System) clock. Wait for an external clock source signal.
- the first standard clock module 1100 According to the first external clock signal S1, the first standard clock module 1100 generates a first frequency synchronization clock signal (system clock frequency) S2, a first phase synchronization signal (frame timing signal) S3, and a first system clock signal S4, wherein the first A system clock signal S4 includes the first frequency synchronization clock signal S2 and the first phase synchronization signal S3 described above.
- the second system clock module 1200 receives the first frequency synchronization clock signal S2 and the first phase synchronization signal S3 from the first system clock module 1100, and generates a second system clock signal S5, wherein the second system clock signal S5 includes the foregoing A frequency synchronization clock signal S2 and a first phase synchronization signal S3.
- the two system clock signals S4 and S5 output by the two standard clock modules 1100 and 1200 will contain the same frequency and phase, thereby achieving a strict synchronization effect.
- the system clock can be generated by a combination of soft and hard phase locked loops.
- 4 is a schematic block diagram showing a base station clock device 2000 in accordance with an embodiment of the present invention. It should be noted that the connection relationships shown in this specification and the drawings do not imply that the two blocks must be directly connected, and they may be indirectly connected through one or more intermediate blocks or intermediate circuits/devices/cables or the like. This connection relationship also does not mean that the two blocks must be wired or connected wirelessly. Similarly, the flow of signals between the two blocks shown in this specification and the drawings does not mean that the signals must be transferred directly from one block, or indirectly through one or more intermediate blocks. These connections and signal flows are all within the scope of embodiments of the present invention.
- the base station clock device 2000 includes a first standard clock module 2100 and a second standard clock module 2200.
- the first system clock module 2100 is based on the first system
- the second system clock module 2200 is based on a second system different from the first system.
- the first standard clock module 2100 can include a first soft phase locked loop 2110 and a first hard phase locked loop 2120.
- the first external clock signal S1 is first sent to the first soft phase locked loop 2110, and the first soft phase locked loop 2110 generates a first frequency synchronous clock signal according to the first external clock signal S1 by frequency division lock equalization processing.
- S2 (eg 10MHz or 13MHz clock signal).
- the first hard phase locked loop 2120 receives the first frequency synchronized clock signal S2 from the first soft phase locked loop 2110 and generates a first phase synchronization signal (frame timing signal) S3.
- the first hard phase locked loop 2120 also sends a smooth system clock signal S4 through the frequency division lock, and S4 includes both the first frequency synchronous clock signal S2 and the first phase synchronization signal S3.
- the second standard clock module 2200 includes a second hard phase locked loop 2220.
- the frequency synchronizing clock signal S2 sent by the first system can be sent to the second phase of the hard phase-locked loop 2220 via the backplane, and the first-standard hardware lock is
- the phase synchronization signal (i.e., frame timing signal) output by phase loop 2120 is sent to the hardware phase locked loop 2220 of the second system as a reference signal for frequency division phase locking of S2, thereby generating a smooth second system clock signal S5.
- the system clock signal S5 also includes both the first frequency synchronizing clock signal S2 and the first phase synchronizing signal S3.
- the final system clocks S4 and S5 sent by the two systems achieve a strict synchronization effect.
- the first system can also be locked by the second system, and the system can also work normally.
- the second standard clock module 2200 may further include a second soft phase locked loop 2210 for receiving the second external clock signal Sl.
- the second external clock signal Sl may be the same as or different from the first external clock signal S1.
- the second soft phase locked loop 2210 Similar to the operation of the first soft phase locked loop 2110, the second soft phase locked loop 2210 generates a second frequency synchronized clock signal S6 based on the second external clock signal S1'.
- the second hard phase locked loop 2220 is further configured to receive the second frequency synchronized clock signal S6 from the second soft phase locked loop 2210, and generate a second phase synchronization signal S7 and The three-system clock signal S8, wherein the third system clock signal S8 includes a second frequency synchronization clock signal S6 and a second phase synchronization signal S7.
- the first hard phase locked loop 2120 is further configured to receive the second frequency synchronized clock signal S6 from the second soft phase locked loop 2210 and from the second hard phase locked loop 2220.
- the second phase synchronization signal S7 and generates a fourth system clock signal S9, wherein the fourth system clock signal S9 also includes a second frequency synchronization clock signal S6 and a second phase synchronization signal S7.
- the third system clock signal S8 and the fourth system clock signal S9 also contain the same frequency and phase, achieving a strict synchronization effect.
- the entire base station has only the external clock source Sl of the second system, and the external clock source S1 of the first system does not function. In other words, the same time can only be the first system lock second system or the second system lock first system, and cannot be interlocked at the same time.
- backups can be provided for the base station clock, thereby improving system reliability.
- the base station clock it is the second system of the first system lock. If the clock signal of the first system is abnormal during operation.
- first soft phase-locked loop 2110 If the first soft phase-locked loop 2110 is abnormal, it can be switched to the second system lock first system, and the system can continue to work normally.
- the frame synchronization information of the system clock finally sent by different systems may contain common frame synchronization information and unique frame synchronization information (for example, the GSM system specificity) GFN frame timing).
- FIG. 5 is a schematic block diagram showing an example of a base station clock device 5000 in a GU dual mode base station according to an embodiment of the present invention.
- Figure 5 shows the implementation of the UMTS lock GSM system clock.
- the base station clock device 5000 includes a GSM clock module 5100 and a UMTS clock module 5200.
- the two clock modules can be composed of the master clock boards of the respective standards.
- the soft phase-locked loop 5110 of the GSM clock module 5100 is composed of a CPU (Central Processing Unit) 5112, a frequency division lock module 5114, and an OCXO (Oven Controlled Crystal Oscillator) 5116, and the system is sent out.
- the clock (ie, the first frequency synchronization clock signal) S2 is 13M (may also be 10M, different implementation hardware is different, and does not affect the principle of the embodiment of the present invention).
- the 13M clock signal S2 is sent to the hard phase-locked loop 5120 of the UMTS standard, in addition to the hard phase-locked loop 5120 of the UMTS standard, for example, to the hard phase-locked loop 5220 via the backplane.
- the soft phase-locked loop 5210 of the UMTS clock module 5200 is composed of a CPU 5212, a frequency division lockout module 5214, and an OCXO 5216, and outputs a 13M (or 10M) system clock (i.e., a second frequency synchronization clock signal) S6.
- a selection module 5215 can be provided between the soft phase locked loop 5210 of the UMTS clock module 5200 and the hard phase locked loop 5220.
- the selection module 5215 can select which one of the frequency synchronizing clock signals S2 and S6 is received for output to the hard phase locked loop 5220 as needed.
- the selection module 5215 can be removed, and the first frequency synchronization clock signal S2 is directly used.
- the hard phase locked loop 5120 of the GSM missing module 5100 is comprised of a VCXO 5122 and a frequency division lockout module 5124.
- the selection module 5215 selects the first frequency synchronization clock signal S2
- the VCXO 5222 generates a hard phase locked clock signal based on the first frequency synchronization clock signal S2 and outputs it to the hard phase locked loop 5220.
- the selection module 5215 selects the second frequency synchronization clock signal S6
- the VCXO 5222 generates a hard phase locked clock signal based on the second frequency synchronization clock signal S6 and outputs it to the hard phase locked loop 5220.
- the frame timing of the system clock output from the hard phase locked loop 5120 (i.e., the first phase synchronization signal S3 is also sent to the frequency division lockout module 5224 in the hard phase locked loop 5220 of the UMTS clock module 5200.
- the frequency division phase-locking module 5224 of the UMTS refers to the phase synchronization signal S3, strictly aligns its own frame timing with GSM, and generates a system clock signal S5 synchronized with the system clock signal S4 of the GSM.
- the system clock finally sent by GSM and UMTS is Synchronization is achieved both in frequency and in time (phase).
- Figure 5 shows the implementation of the UMTS lock GSM system clock. However, similar to Figure 4, Figure 5 can also implement the GSM lock UMTS system clock. In this case, a selection module 5115 can also be provided between the soft phase locked loop 5110 of the GSM clock module 5100 and the hard phase locked loop 5120. Thereby achieving clock backup and improving system stability.
- the frequency synchronization clock signal and the frame timing signal output by the UMTS system may also be referred to as a first frequency synchronization clock signal S2 and a first phase synchronization signal S3, respectively.
- FIG. 6 is a schematic block diagram showing an example of a base station system 6000 according to an embodiment of the present invention. It should be noted that FIG. 6 mainly shows some devices regarding the synchronous clock, but this does not mean that the base station system 6000 Does not include other functional modules. For example, base station system 6000 can also include functional modules and the like for traffic signal flows.
- the base station system 6000 includes a base station clock device 6100 and a radio frequency module device 6200.
- the base station clock pointer 6100 may be the base station clock device 1000, 2000 or 5000 described above, including a first mode clock module 6110 and a second mode clock module 6120.
- 6 shows an implementation of the first system of the second system lock, that is, according to the external clock source S1 of the first system clock module 6110, the first system clock is generated according to the similar operation mode of the base station clock device 1000, 2000 or 5000.
- the first system clock signal S4 and the second system clock signal S5 contain the same frequency synchronizing clock signal and phase synchronizing signal, and thus are strictly synchronized.
- the RF module unit 6200 is a multimode RF module that needs to be synchronized with the master system clock of at least two systems.
- a dual-mode base station is taken as an example for description. Therefore, the radio frequency module device 6200 receives the first system clock signal S4 and the second system clock signal S5, and selects one of the system clock signals S4 or S5 as needed to obtain a recovered clock signal. In this way, both the standard and multimode RF modules use a synchronized system clock to achieve clock synchronization within the base station system.
- Clock signals S4 and S5 may be incorporated via an interface board incorporated into base station clock device 6100 (e.g.
- the CPRI interface board is transmitted to the RF module unit 6200 independently of the interface board of the base station clock device 6100.
- the principle that the radio frequency module device 6200 selects may be: if the clock signals of the two links are all good, then any one of the paths is randomly selected, for example, if one is good or bad, if the two clock signals are bad, If they are not selected, the RF module device can be abnormally alarmed.
- base station system 6000 contains more standards is similar. Additionally, base station system 6000 can be a macro base station or a distributed base station similar in structure to that of Figure 1 or Figure 2.
- FIG. 7 is a schematic block diagram showing an example of a dual mode radio frequency module device 7000 according to an embodiment of the present invention.
- the radio frequency module device 7000 can have a first input interface unit 7100, a second input interface unit 7200, a clock signal selection unit 7300, a clock frequency recovery unit 7400, and a medium RF processing unit 7500.
- the first input interface unit 7100 and the second input interface unit 7200 may be CPRI interfaces that receive a first system clock signal S4 and a second system clock signal S5 from a base station clock device (not shown in FIG. 7) via a CPRI cable, respectively.
- the first input interface unit ⁇ 100 extracts the first frequency synchronizing clock signal S2a in the first system clock signal S4 and outputs it to the clock signal selecting unit 7300.
- the second input interface unit 7200 extracts the first frequency synchronizing clock signal S2b of the second system clock signal S5 and outputs it to the clock signal selecting unit 7300.
- the clock signal selecting unit 7300 selects one of the two frequency synchronizing clock signals S2a and S2b as a local frequency synchronizing clock signal and uses it as the input of the local clock frequency restoring unit 7400.
- the clock frequency recovery unit 7400 receives the local frequency synchronization clock signal and generates a recovered clock signal.
- the frame synchronization information of the system clock finally sent by different systems may contain common frame synchronization information and unique frame synchronization information (for example, frame timing signals).
- the first input interface unit 7100 is further configured to extract the first system frame timing signal SFNa from the first system clock signal S4 and output it to the medium RF processing unit 7500.
- the second input interface unit 7200 is further configured to extract the second system frame timing signal SFNb from the second system clock signal S5 and output it to the medium RF processing unit 7500.
- the medium RF processing unit 7500 performs radio frequency processing on the recovered clock signal, the frame timing signals SFNa and SFNb, thereby obtaining a radio frequency signal that can be transmitted through an antenna (not shown).
- FIG. 8 is a flow diagram of a clock synchronization method 800 in a multimode base station system in accordance with an embodiment of the present invention.
- the clock synchronization method 800 is applicable to the base station clock device 1000 shown in FIG.
- the method 800 of Fig. 8 is described below in conjunction with Fig. 3.
- the clock synchronization method 800 generates a first frequency synchronization clock signal S2, a first phase synchronization signal S3, and a first system clock signal S4 according to the first external clock signal S1 through the first standard clock module 1100, where the first System clock signal S4 includes a first frequency synchronization clock signal S2 And the first phase synchronization signal S3.
- the first frequency synchronization clock signal S2 and the first phase synchronization signal S3 are received from the first standard clock module 1100 by the second standard clock module 1200, and a second system clock signal S5 is generated, wherein the second system clock signal S5 A first frequency synchronization clock signal S2 and the first phase synchronization signal S3 are included.
- the clock synchronization method 800 is equally applicable to the base station clock device 2000 of Fig. 4 and the base station clock device 5000 of Fig. 5, including operations performed by various components therein. To avoid repetition, we will not repeat them.
- the two system clock signals S4 and S5 output by the clock modules 1100 and 1200 of the two modes will contain the same frequency and phase, thereby achieving a strict synchronization effect.
- RAM random access memory
- ROM read only memory
- EEPROM electrically programmable ROM
- EEPROM electrically erasable programmable ROM
- registers hard disk, removable disk, CD-ROM, or technical field Any other form of storage medium known.
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Description
基站时钟装置、 基站***和时钟同步方法
本申请要求于 2011 年 1 月 21 日提交中国专利局、 申请号为 201 110023915. 0、 发明名称为 "基站时钟装置、 基站***和时钟同步方法" 的中国专利申请的优先权, 其全部内容通过引用结合在本申请中。 技术领域
本发明实施例涉及移动通信领域, 更具体地, 涉及基站时钟装置、 基站 ***和时钟同步方法。 背景技术
随着移动通信技术的进步, 已经出现了多模基站, 即能同时支持多种无 线制式的基站。 比如能同时支持 GSM ( Global System for Mobile Communications; 全球移动通讯*** ) 和 UMTS ( Universal Mobile Telecommunications System; 通用移动通信***) 两种无线制式的基站称为 GU双模基站。
多模基站的一种解决方案就是以叠加不同制式的单板形成多模基站。 以 GU双模基站为例进行说明, BBU ( Base Band Unit; 基带单元 ) 内包括各制 式的主控板和出 CPRI接口( Common Public Radio Interface,公共通用无线接 口 ) 的单板, 出 CPRI接口的单板可以和主控板合一(如 GSM制式), 也可 以和业务处理单板合一 (如 UMTS制式)。
由于多模基站的射频模块支持多种制式, 多模射频模块的***时钟必须 与两个制式的主控***时钟同步, 否则就会在 CPRI接口上出现失步、 中射 频处理部分无法正常工作等问题。
因此, 在多模基站中存在对于不同制式的***时钟同步 (或者称为时钟 互锁) 的需要。
发明内容
本发明实施例提供一种基站时钟装置、 基站***和时钟同步方法, 能够 使得不同制式的***时钟同步。
一方面, 本发明实施例提供了一种基站时钟装置, 包括: 基于第一制式 的第一制式时钟模块, 用于根据第一外部时钟信号, 生成第一频率同步时钟 信号、 第一相位同步信号和第一***时钟信号, 其中该第一***时钟信号包 含上述第一频率同步时钟信号和第一相位同步信号; 基于与第一制式不同的 第二制式的第二制式时钟模块, 用于从第一制式时钟模块接收上述第一频率 同步时钟信号和第一相位同步信号, 并生成第二***时钟信号, 其中该第二 ***时钟信号包含上述第一频率同步时钟信号和第一相位同步信号。
另一方面, 本发明实施例提供了一种基站***, 包括上述基站时钟装置 和射频模块装置。 该射频模块装置用于从所述基站时钟装置接收第一***时 钟信号和第二***时钟信号, 并选择所述第一***时钟信号和所述第二*** 时钟信号之一作为本地时钟频率恢复的输入。
再一方面, 本发明实施例提供了一种基站时钟装置中同步时钟的方法, 所述基站时钟装置包括基于第一制式的第一制式时钟模块和基于与第一制式 不同的第二制式的第二制式时钟模块, 该方法包括: 通过第一制式时钟模块, 根据第一外部时钟信号, 生成第一频率同步时钟信号、 第一相位同步信号和 第一***时钟信号, 其中该第一***时钟信号包含上述第一频率同步时钟信 号和第一相位同步信号; 通过第二制式时钟模块, 从第一制式时钟模块接收 上述第一频率同步时钟信号和第一相位同步信号,并生成第二***时钟信号, 其中该第二***时钟信号包含上述第一频率同步时钟信号和第一相位同步信 号。
由此, 本发明实施例中多种制式的时钟模块可以生成包含相同的频率同 步时钟信号和相位同步信号的***时钟信号, 使得不同制式的时钟模块所生 成的***时钟信号之间的频率和相位能够互相同步, 从而实现了时钟同步。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案, 下面将对实 施例或现有技术描述中所需要使用的附图作简单地介绍, 显而易见地, 下面 描述中的附图仅仅是本发明的一些实施例, 对于本领域普通技术人员来讲, 在不付出创造性劳动的前提下, 还可以根据这些附图获得其他的附图。
图 1是示出双模 GU宏基站的结构示意图。
图 2是示出双模分布式 GU基站的结构示意图。
图 3是示出根据本发明实施例的基站时钟装置的示意框图。
图 4是示出根据本发明实施例的基站时钟装置的一个例子的示意框图。 图 5是示出根据本发明实施例的基站时钟装置的一个例子的示意框图。 图 6是示出根据本发明实施例的基站***的示意框图。
图 7是示出根据本发明实施例的双模射频模块装置的一个例子的示意框 图。
图 8是根据本发明实施例的多模基站***中的时钟同步方法的流程图。 具体实施方式
本发明实施例能够应用于各种不同制式组成的多模场景, 适用于 GSM、 UMTS、 CDMA ( Code Division Multiple Access; 码分多址)、 WiMAX ( Worldwide Interoperability for Microwave Access; 全球微波互联接入 )、 LTE (Long Term Evolution; 长期演进)等各种制式的组合形成的多模基站, 例如但 不限于 GSM与 UMTS两种制式组成的双模基站, UMTS与 CDMA两种制式 组成的双模基站, UMTS与 LTE两种制式组成的基站, GSM、 UMTS, LTE 组成的三模基站等。 下文中, 为了描述方便且不失一般性, 采用双模基站(例 如, 由 GSM与 UMTS两种制式组成的 GU双模基站 ) 为例进行说明。 但应 注意, 本发明实施例的多模基站的范围不限于特定的制式种类和数目。
此外, 本发明实施例不仅适用于多模宏基站, 也适用于分布式多模基站。 图 1是示出双模 GU宏基站的结构示意图。 图 2是示出双模分布式 GU基站 的结构示意图。
图 1和图 2所示的两种多模基站均配置共模的射频模块(多模射频模块), 以支持多种制式。射频模块和 BBU之间通过 CPRI链路相连接。在此情况下, 各制式的 CPRI链路会汇聚在一起, 因此必须保证两种制式***时钟严格的 频率同步和相位同步, 即 CPRI的工作时钟需要严格同步。 由于 CPRI组帧是 基于帧定时的帧号(FN; Frame Number )来进行的, 所以多模基站的制式之 间要求 CPRI的帧定时(或帧号) 必须保持严格同步。 为此, 要求在 BBU内 的各制式用于无线业务的***时钟能够同步。
图 3是示出根据本发明实施例的基站时钟装置 1000的示意框图。基站时 钟装置 1000包括第一制式时钟模块 1100和第二制式时钟模块 1200。 第一制 式时钟模块 1100基于第一制式, 而第二制式时钟模块 1200基于与第一制式 不同的第二制式。
第一制式时钟模块 1100可以从外部接收第一外部时钟信号 Sl。 该第一 外部时钟信号 S1可以是 GPS ( Global Positioning System; 全球定位*** )时 钟、 E1时钟、 IP( Internet Protocol;因特网协议)时钟、 BITS( Building Integrated Timing Supply System; 通信楼综合定时供给***) 时钟等外部时钟源信号。
根据第一外部时钟信号 S1 , 第一制式时钟模块 1100生成第一频率同步 时钟信号(***时钟频率) S2、 第一相位同步信号(帧定时信号) S3和第一 ***时钟信号 S4, 其中该第一***时钟信号 S4包含上述第一频率同步时钟 信号 S2和第一相位同步信号 S3。
第二制式时钟模块 1200从第一制式时钟模块 1100接收上述第一频率同 步时钟信号 S2和第一相位同步信号 S3 , 并生成第二***时钟信号 S5, 其中 该第二***时钟信号 S5包含上述第一频率同步时钟信号 S2和第一相位同步 信号 S3。
这样, 两种制式的时钟模块 1100和 1200所输出的两路***时钟信号 S4 和 S5将包含相同的频率和相位, 从而达到严格同步的效果。
根据本发明的一个实施例, 可通过软硬锁相环的组合来生成***时钟。 图 4是示出根据本发明实施例的基站时钟装置 2000的示意框图。 应注意, 本 说明书以及附图中所示的连接关系不意味着两个块必须直接相连, 它们也可 以通过一个或多个中间块或中间电路 /装置 /线缆等间接相连。该连接关系也不 意味着两个块之间必须是有线方式的连接, 也可以通过无线方式连接。 同样 地, 本说明书以及附图中所示的两个块之间的信号流也不意味着信号必须直 接从一个块传送的另一块, 也可以通过一个或多个中间块而间接传送。 这些 连接方式和信号流均落入本发明实施例的范围内。
与图 3的基站时钟装置 1000类似, 基站时钟装置 2000包括第一制式时 钟模块 2100和第二制式时钟模块 2200。 第一制式时钟模块 2100基于第一制 式, 而第二制式时钟模块 2200基于与第一制式不同的第二制式。
具体地, 第一制式时钟模块 2100可包括第一软锁相环 2110和第一硬锁 相环 2120。 如图 4所示, 第一外部时钟信号 S1先送入第一软锁相环 2110, 第一软锁相环 2110根据第一外部时钟信号 S1经分频锁相等处理生成第一频 率同步时钟信号 S2 (例如 10MHz或 13MHz时钟信号)。
第一硬锁相环 2120接收来自第一软锁相环 2110的第一频率同步时钟信 号 S2,并生成第一相位同步信号(帧定时信号) S3。此外,第一硬锁相环 2120 还经过分频锁相送出平稳的***时钟信号 S4, S4包含第一频率同步时钟信号 S2和第一相位同步信号 S3这两者。
第二制式时钟模块 2200 包括第二硬锁相环 2220。 为了达到两种制式的 多模基站***时钟同步的目的, 可以将第一制式送出的频率同步时钟信号 S2 经背板送给第二制式的硬锁相环 2220, 并且将第一制式的硬件锁相环 2120 输出的相位同步信号 (即帧定时信号 ) S3送给第二制式的硬件锁相环 2220, 作为对 S2进行分频锁相的参照信号, 从而生成平稳的第二***时钟信号 S5。
这样, 该***时钟信号 S5同样包含第一频率同步时钟信号 S2和第一相位同 步信号 S3这两者。从而两个制式送出的最终的***时钟 S4和 S5就达到严格 同步的效果。
上面描述了根据第一制式时钟模块 2100 的时钟信号锁定第二制式时钟 模块 2200的时钟信号的方式(图 4中的实线所示的时钟信号流)。 这种情况 下***可以正常工作。 由于第二制式的硬件锁相环 2220选择了第一制式的软 锁相环 2110输出, 所以整个基站只有第一制式的外部时钟源 S1起作用。
同理, 也可以通过第二制式锁定第一制式, ***同样可以正常工作。 在 此情况下, 如图 4中的虚线框所示, 第二制式时钟模块 2200还可以包括第二 软锁相环 2210, 用于接收第二外部时钟信号 Sl,。 第二外部时钟信号 Sl,可以 与第一外部时钟信号 S1相同, 也可以不同。
类似于第一软锁相环 2110的操作, 第二软锁相环 2210根据第二外部时 钟信号 S1 '生成第二频率同步时钟信号 S6。
类似于第一硬锁相环 2120的操作, 第二硬锁相环 2220还用于接收来自 第二软锁相环 2210的第二频率同步时钟信号 S6, 并生成第二相位同步信号 S7和第三***时钟信号 S8, 其中第三***时钟信号 S8包含第二频率同步时 钟信号 S6和第二相位同步信号 S7。
此时, 如图 4中的虚线信号流所示, 第一硬锁相环 2120还用于接收来自 第二软锁相环 2210的第二频率同步时钟信号 S6和来自第二硬锁相环 2220的 第二相位同步信号 S7, 并生成第四***时钟信号 S9, 其中第四***时钟信号 S9同样包含第二频率同步时钟信号 S6和第二相位同步信号 S7。 这样, 第三 ***时钟信号 S8和第四***时钟信号 S9也包含相同的频率和相位, 达到严 格同步的效果。应注意,此时整个基站只有第二制式的外部时钟源 Sl,起作用, 而第一制式的外部时钟源 S1不起作用。换句话说, 同一时刻只能是第一制式 锁第二制式或者第二制式锁第一制式, 不能同时互锁。
在此构造下, 可以为基站时钟提供备份, 从而提高***的可靠性。 例如,
一开始是第一制式锁第二制式, 在运行过程中如果第一制式的时钟信号异常
(如第一软锁相环 2110异常), 则可以倒换为第二制式锁第一制式, ***仍 然可以继续正常工作。
另外, 由于不同制式的帧同步信息除了公共的信息外, 还有各自特有的 信息, 因此不同制式最终送出的***时钟的帧同步信息可以含有公共帧同步 信息和特有帧同步信息 (例如 GSM制式特有的 GFN帧定时)。
下面以 GU双模基站***时钟同步方案为例描述***时钟同步的实现方 式。 图 5是示出根据本发明实施例的 GU双模基站中的基站时钟装置 5000的 一个例子的示意框图。如图 5所示的是 UMTS锁 GSM***时钟的实现方式。
具体地, 基站时钟装置 5000包括 GSM时钟模块 5100和 UMTS时钟模 块 5200。 两个时钟模块可以由各自制式的主控时钟板构成。 GSM 时钟模块 5100的软锁相环 5110由 CPU ( Central Processing Unit; 中央处理单元)5112、 分频锁相模块 5114和 OCXO ( Oven Controlled Crystal Oscillator; 恒温晶体压 控振荡器) 5116组成, 送出的***时钟(即, 第一频率同步时钟信号) S2为 13M (也可以是 10M,不同的实现硬件不一样,不影响本发明实施例的原理)。 13M时钟信号 S2除了送给本板的硬锁相环 5120, 也送给 UMTS制式的时钟 模块 5200的硬锁相环 5220, 例如经过背板送给硬锁相环 5220。
类似地, UMTS时钟模块 5200的软锁相环 5210由 CPU 5212、 分频锁相 模块 5214和 OCXO 5216组成, 输出 13M (或 10M的 )***时钟(即, 第二 频率同步时钟信号) S6。
在 UMTS时钟模块 5200的软锁相环 5210和硬锁相环 5220之间可设置 选择模块 5215。 选择模块 5215可以根据需要选择接收频率同步时钟信号 S2 和 S6 中的哪一路时钟以输出至硬锁相环 5220。 当然, 在不采用第二外部时 钟信号 Sl,的情况下, 可以去掉选择模块 5215 , 直接采用第一频率同步时钟 信号 S2。
UMTS 时钟模块 5200 的硬锁相环 5220 由 VCXO ( Voltage-controlled
Crystal Oscillator; 电压控制的晶体振荡器) 5222和分频锁相模块 5224两个 部分组成。 类似地, GSM失踪模块 5100的硬锁相环 5120由 VCXO 5122和 分频锁相模块 5124组成。
在选择模块 5215选择第一频率同步时钟信号 S2的情况下, VCXO 5222 根据第一频率同步时钟信号 S2生成硬锁相时钟信号,并将其输出至硬锁相环 5220。在选择模块 5215选择第二频率同步时钟信号 S6的情况下, VCXO 5222 根据第二频率同步时钟信号 S6生成硬锁相时钟信号,并将其输出至硬锁相环 5220„
如图 5所示, 从硬锁相环 5120输出的***时钟的帧定时(即, 第一相位 同步信号 S3还送给 UMTS时钟模块 5200的硬锁相环 5220中的分频锁相模 块 5224。 UMTS的分频锁相模块 5224参照相位同步信号 S3 , 将自己的帧定 时严格与 GSM的对齐, 生成与 GSM的***时钟信号 S4同步的***时钟信 号 S5。 这样 GSM和 UMTS最终送出的***时钟在频率和时间 (相位 )上都 达到了同步的效果。
图 5中主要显示了 UMTS锁 GSM***时钟的实现方式。 但是与图 4相 似, 图 5也可以实现 GSM锁 UMTS***时钟。 在此情况下, 也可在 GSM时 钟模块 5100的软锁相环 5110和硬锁相环 5120之间设置选择模块 5115。从而 实现时钟的备份, 提高***的稳定性。
应注意, 本发明说明书中所涉及的 "第一" 和 "第二" 等并不对本发明 实施例的范围构成限制, 因为它们是对称的, 因而可以互换。 例如, 在 GSM 锁 UMTS***时钟的实现方式中,也可以将 UMTS制式输出的频率同步时钟 信号和帧定时信号分别称为第一频率同步时钟信号 S2 和第一相位同步信号 S3。
上面所述的基站时钟装置 1000、 2000和 5000可应用于基站***中。 图 6是示出根据本发明实施例的基站*** 6000的一个例子的示意框图。应注意, 图 6中主要显示了关于同步时钟的部分装置, 但这并未意味着基站*** 6000
不包括其他功能模块。 例如, 基站*** 6000还可包括关于业务信号流的功能 模块等。
基站*** 6000包括基站时钟装置 6100和射频模块装置 6200。 基站时钟 指针 6100可以是上面所述的基站时钟装置 1000、 2000或 5000, 包括第一制 式时钟模块 6110和第二制式时钟模块 6120。 图 6示出了第二制式锁第一制 式的实现方式, 即根据第一制式时钟模块 6110的外部时钟源 S1 , 按照基站 时钟装置 1000、 2000或 5000的类似操作方式, 分别生成第一***时钟信号 S4和第二***时钟信号 S5。 此时, 第一***时钟信号 S4和第二***时钟信 号 S5包含相同的频率同步时钟信号和相位同步信号, 因而严格同步。
射频模块装置 6200是多模射频模块,需要与至少两种制式的主控***时 钟同步。 以双模基站为例进行说明。 因此, 射频模块装置 6200接收第一*** 时钟信号 S4和第二***时钟信号 S5 , 并根据需要选择其中一路***时钟信 号 S4或 S5 , 用以得到恢复时钟信号。 这样, 两种制式和多模射频模块均采 用同步的***时钟, 从而在基站***内实现了时钟同步。
时钟信号 S4和 S5可经由合并到基站时钟装置 6100中的接口板(例如
CPRI接口板)或独立于基站时钟装置 6100的接口板而传送到射频模块装置 6200„
射频模块装置 6200进行选择的原则可以是:如果两条链路的时钟信号都 好, 则任意选一路例如随机选一路; 如果一好一坏, 则选择好的; 如果两路 时钟信号都坏, 则都不选, 此时射频模块装置可异常告警。
基站*** 6000包含更多制式的情况与此类似。 另外, 基站*** 6000可 以是与图 1或图 2结构类似的宏基站或分布式基站。
图 7是示出根据本发明实施例的双模射频模块装置 7000的一个例子的示 意框图。 如图 7所示, 射频模块装置 7000可具有第一输入接口单元 7100、 第二输入接口单元 7200、 时钟信号选择单元 7300、 时钟频率恢复单元 7400 和中射频处理单元 7500。
第一输入接口单元 7100和第二输入接口单元 7200可以是 CPRI接口, 分别通过 CPRI线缆从基站时钟装置 (图 7中未示出 )接收第一***时钟信 号 S4和第二***时钟信号 S5。
第一输入接口单元 Ί 100提取第一***时钟信号 S4中的第一频率同步时 钟信号 S2a, 并将其输出至时钟信号选择单元 7300。 第二输入接口单元 7200 提取第二***时钟信号 S5中的第一频率同步时钟信号 S2b, 并将其输出至时 钟信号选择单元 7300。
时钟信号选择单元 7300选择两路频率同步时钟信号 S2a和 S2b之一,作 为本地频率同步时钟信号, 并将其作为本地的时钟频率恢复单元 7400 的输 入。 时钟频率恢复单元 7400接收本地频率同步时钟信号并生成恢复时钟信 号。
由于不同制式的帧同步信息除了公共的信息外, 还有各自特有的信息, 因此不同制式最终送出的***时钟的帧同步信息可以含有公共帧同步信息和 特有帧同步信息 (例如帧定时信号)。
在此情况下, 第一输入接口单元 7100还用于从第一***时钟信号 S4中 提取第一制式帧定时信号 SFNa, 并将其输出至中射频处理单元 7500。 第二 输入接口单元 7200还用于从第二***时钟信号 S5中提取第二制式帧定时信 号 SFNb, 并将其输出至中射频处理单元 7500。
中射频处理单元 7500对恢复时钟信号、 帧定时信号 SFNa和 SFNb进行 中射频处理, 从而得到能通过天线 (未示出)发射的射频信号。
图 8是根据本发明实施例的多模基站***中的时钟同步方法 800的流程 图。 该时钟同步方法 800可应用于图 3所示的基站时钟装置 1000。 下面结合 图 3描述图 8的方法 800。
在 S810 , 时钟同步方法 800通过第一制式时钟模块 1100, 根据第一外部 时钟信号 S 1 , 生成第一频率同步时钟信号 S2、 第一相位同步信号 S3和第一 ***时钟信号 S4, 其中第一***时钟信号 S4包含第一频率同步时钟信号 S2
和第一相位同步信号 S3。
在 S820, 通过第二制式时钟模块 1200, 从第一制式时钟模块 1100接收 第一频率同步时钟信号 S2和第一相位同步信号 S3 , 并生成第二***时钟信 号 S5 ,其中第二***时钟信号 S5包含第一频率同步时钟信号 S2和所述第一 相位同步信号 S3。
时钟同步方法 800同样可应用于图 4的基站时钟装置 2000和图 5的基站 时钟装置 5000, 包含由其中各个部件所执行的操作。 为避免重复, 不再贅述。
这样, 通过根据本发明实施例的时钟同步方法 800, 两种制式的时钟模 块 1100和 1200所输出的两路***时钟信号 S4和 S5将包含相同的频率和相 位, 从而达到严格同步的效果。
本领域普通技术人员可以意识到, 结合本文中所公开的实施例描述的各 示例的单元及算法步骤, 能够以电子硬件、 计算机软件或者二者的结合来实 现, 为了清楚地说明硬件和软件的可互换性, 在上述说明中已经按照功能一 般性地描述了各示例的组成及步骤。 这些功能究竟以硬件还是软件方式来执 行, 取决于技术方案的特定应用和设计约束条件。 专业技术人员可以对每个 特定的应用来使用不同方法来实现所描述的功能, 但是这种实现不应认为超 出本发明的范围。
结合本文中所公开的实施例描述的方法或算法的步骤可以用硬件、 处理 器执行的软件模块, 或者二者的结合来实施。 软件模块可以置于随机存储器 ( RAM )、内存、只读存储器( ROM )、电可编程 ROM、电可擦除可编程 ROM, 寄存器、 硬盘、 可移动磁盘、 CD-ROM、 或技术领域内所公知的任意其它形 式的存储介质中。
尽管已示出和描述了本发明的一些实施例, 但本领域技术人员应理解, 在不脱离本发明的原理和精神的情况下, 可对这些实施例进行各种修改, 这 样的修改应落入本发明的范围内。
Claims
1、 一种基站时钟装置, 其特征在于, 包括:
基于第一制式的第一制式时钟模块, 用于根据第一外部时钟信号, 生成 第一频率同步时钟信号、 第一相位同步信号和第一***时钟信号, 其中所述 第一***时钟信号包含所述第一频率同步时钟信号和所述第一相位同步信 号;
基于与所述第一制式不同的第二制式的第二制式时钟模块, 用于从所述 第一制式时钟模块接收所述第一频率同步时钟信号和第一相位同步信号, 并 生成第二***时钟信号, 其中所述第二***时钟信号包含所述第一频率同步 时钟信号和所述第一相位同步信号。
2、如权利要求 1所述的基站时钟装置,其中所述第一制式时钟模块包括: 第一软锁相环, 用于接收所述第一外部时钟信号, 并根据所述第一外部 时钟信号生成所述第一频率同步时钟信号;
第一硬锁相环, 用于接收来自所述第一软锁相环的所述第一频率同步时 钟信号, 并生成所述第一相位同步信号和所述第一***时钟信号,
其中, 所述第二制式时钟模块包括:
第二硬锁相环, 用于接收来自所述第一软锁相环的所述第一频率同步时 钟信号和来自所述第一硬锁相环的所述第一相位同步信号, 并生成所述第二 ***时钟信号。
3、 如权利要求 2所述的基站时钟装置, 其中所述第二制式时钟模块还包 括:
第二软锁相环, 用于接收第二外部时钟信号, 并根据所述第二外部时钟 信号生成第二频率同步时钟信号,
所述第二硬锁相环还用于接收来自所述第二软锁相环的所述第二频率同 步时钟信号, 并生成第二相位同步信号和第三***时钟信号, 其中所述第三 ***时钟信号包含所述第二频率同步时钟信号和第二相位同步信号。
4、 如权利要求 3所述的基站时钟装置, 其中所述第一硬锁相环还用于接 收来自所述第二软锁相环的所述第二频率同步时钟信号和来自所述第二硬锁 相环的所述第二相位同步信号, 并生成第四***时钟信号, 其中所述第四系 统时钟信号包含所述第二频率同步时钟信号和所述第二相位同步信号。
5、 如权利要求 4所述的基站时钟装置, 其中所述第一制式时钟模块还包 括:
选择模块, 用于从所述第一软锁相环接收所述第一频率同步时钟信号并 从所述第二软锁相环接收所述第二频率同步时钟信号, 以及用于选择所述第 一频率同步时钟信号和所述第二频率同步时钟信号之一以输出至所述第一硬 锁相环。
6、 如权利要求 3所述的基站时钟装置, 其中所述第二制式时钟模块还包 括:
选择模块, 用于从所述第一软锁相环接收所述第一频率同步时钟信号并 从所述第二软锁相环接收所述第二频率同步时钟信号, 以及用于选择所述第 一频率同步时钟信号和所述第二频率同步时钟信号之一以输出至所述第二硬 锁相环。
7、 如权利要求 2所述的基站时钟装置, 其中所述第二硬锁相环包括: 电压控制晶体振荡器, 用于接收所述第一频率同步时钟信号, 并生成硬 锁相时钟信号;
分频锁相模块, 用于从所述电压控制晶体振荡器接收所述硬锁相时钟信 号, 从所述第一硬锁相环接收所述第一相位同步信号, 并生成所述第二*** 时钟信号。
8、 一种基站***, 其特征在于, 包括:
如权利要求 1-7中任一个所述的基站时钟装置,
射频模块装置, 用于从所述基站时钟装置接收第一***时钟信号和第二 ***时钟信号 ,并选择所述第一***时钟信号和所述第二***时钟信号之一 , 用以得到恢复时钟信号。
9、 如权利要求 8所述的基站***, 其中所述射频模块装置包括: 第一输入接口单元, 用于接收所述第一***时钟信号, 并提取所述第一 ***时钟信号中的第一频率同步时钟信号;
第二输入接口单元, 用于接收所述第二***时钟信号, 并提取所述第二 ***时钟信号中的第一频率同步时钟信号;
时钟信号选择单元, 用于选择所述第一***时钟信号中的第一频率同步 时钟信号和所述第二***时钟信号中的第一频率同步时钟信号之一作为本地 频率同步时钟信号;
时钟频率恢复单元, 用于接收所述本地频率同步时钟信号, 并生成恢复 时钟信号。
10、 如权利要求 9所述的基站***, 其中, 所述第一***时钟信号还包 括第一制式帧定时信号,所述第二***时钟信号还包括第二制式帧定时信号, 所述第一输入接口单元还用于从所述第一***时钟信号中提取所述第一 制式帧定时信号;
所述第二输入接口单元还用于从所述第二***时钟信号中提取所述第二 制式帧定时信号;
所述射频模块装置还包括:
中射频处理单元, 用于接收所述恢复时钟信号, 接收所述第一制式帧定 时信号和第二制式帧定时信号, 并对所述恢复时钟信号、 所述第一制式帧定 时信号和第二制式帧定时信号进行中射频处理。
11、 如权利要求 8所述的基站***, 其中所述基站***为宏基站或分布 式基站。
12、 一种基站时钟装置中同步时钟的方法, 其特征在于, 所述基站时钟 装置包括基于第一制式的第一制式时钟模块和基于与所述第一制式不同的第 二制式的第二制式时钟模块, 所述方法包括: 通过所述第一制式时钟模块, 根据第一外部时钟信号, 生成第一频率同 步时钟信号、 第一相位同步信号和第一***时钟信号, 其中所述第一***时 钟信号包含所述第一频率同步时钟信号和所述第一相位同步信号;
通过所述第二制式时钟模块, 从所述第一制式时钟模块接收所述第一频 率同步时钟信号和第一相位同步信号, 并生成第二***时钟信号, 其中所述 第二***时钟信号包含所述第一频率同步时钟信号和所述第一相位同步信 号。
13、 如权利要求 12所述的方法, 其中所述第一制式时钟模块包括第一软 锁相环和第一硬锁相环, 所述第二制式时钟模块包括第二硬锁相环, 其中 所述生成第一频率同步时钟信号、 第一相位同步信号和第一***时钟信 号包括:
通过所述第一软锁相环, 接收所述第一外部时钟信号, 并根据所述第一 外部时钟信号生成所述第一频率同步时钟信号;
通过所述第一硬锁相环, 接收来自所述第一软锁相环的所述第一频率同 步时钟信号, 并生成所述第一相位同步信号和所述第一***时钟信号,
其中, 所述生成第二***时钟信号包括:
通过所述第二硬锁相环, 接收来自所述第一软锁相环的所述第一频率同 步时钟信号和来自所述第一硬锁相环的所述第一相位同步信号, 并生成所述 第二***时钟信号。
14、 如权利要求 13所述的方法, 其中所述第二制式时钟模块还包括第二 软锁相环, 所述方法还包括:
通过所述第二软锁相环, 接收第二外部时钟信号, 并根据所述第二外部 时钟信号生成第二频率同步时钟信号,
通过所述第二硬锁相环, 接收来自所述第二软锁相环的所述第二频率同 步时钟信号, 并生成第二相位同步信号和第三***时钟信号, 其中所述第三 ***时钟信号包含所述第二频率同步时钟信号和第二相位同步信号。
15、 如权利要求 14所述的方法, 其中所述方法还包括:
通过所述第一硬锁相环, 接收来自所述第二软锁相环的所述第二频率同 步时钟信号和来自所述第二硬锁相环的所述第二相位同步信号, 并生成第四 ***时钟信号, 其中所述第四***时钟信号包含所述第二频率同步时钟信号 和所述第二相位同步信号。
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EP2663141A1 (en) | 2013-11-13 |
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EP2663141A4 (en) | 2013-11-20 |
US9215676B2 (en) | 2015-12-15 |
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