WO2012090564A1 - データ要素列を処理する装置及び方法 - Google Patents
データ要素列を処理する装置及び方法 Download PDFInfo
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- WO2012090564A1 WO2012090564A1 PCT/JP2011/072891 JP2011072891W WO2012090564A1 WO 2012090564 A1 WO2012090564 A1 WO 2012090564A1 JP 2011072891 W JP2011072891 W JP 2011072891W WO 2012090564 A1 WO2012090564 A1 WO 2012090564A1
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- 238000000034 method Methods 0.000 title claims abstract description 44
- 230000004044 response Effects 0.000 claims description 8
- 238000013144 data compression Methods 0.000 description 51
- 101710147134 Putative transposase for insertion sequence element IS986/IS6110 Proteins 0.000 description 19
- 101710099762 Uncharacterized protein in sodM 3'region Proteins 0.000 description 19
- 238000007906 compression Methods 0.000 description 16
- 230000003252 repetitive effect Effects 0.000 description 16
- 230000006835 compression Effects 0.000 description 15
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 13
- 238000010586 diagram Methods 0.000 description 8
- 230000001360 synchronised effect Effects 0.000 description 4
- 102100026926 60S ribosomal protein L4 Human genes 0.000 description 2
- 101100527655 Arabidopsis thaliana RPL4D gene Proteins 0.000 description 2
- 101100469270 Candida albicans (strain SC5314 / ATCC MYA-2876) RPL10A gene Proteins 0.000 description 2
- 101100304908 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) RPL5 gene Proteins 0.000 description 2
- JJWKPURADFRFRB-UHFFFAOYSA-N carbonyl sulfide Chemical compound O=C=S JJWKPURADFRFRB-UHFFFAOYSA-N 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 101150060526 rpl1 gene Proteins 0.000 description 2
- 101150009248 rpl4 gene Proteins 0.000 description 2
- 101150079275 rplA gene Proteins 0.000 description 2
- 230000001174 ascending effect Effects 0.000 description 1
- 238000013075 data extraction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 239000000284 extract Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1064—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in cache or content addressable memories
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
- G11C15/04—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
- H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
- H03M7/3084—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction using adaptive string matching, e.g. the Lempel-Ziv method
- H03M7/3088—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction using adaptive string matching, e.g. the Lempel-Ziv method employing the use of a dictionary, e.g. LZ78
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/04—Protocols for data compression, e.g. ROHC
Definitions
- the present invention relates to an apparatus and method for processing a data element sequence.
- the present invention relates to an apparatus and method for processing a first partial data element sequence of a data element sequence based on the position of a second partial data element sequence.
- Deflate compression is a compression method based on ZLIB (RFC1950) and GZIP (RFC1952), which are data compression formats currently widely used in computers, and uses LZ77 encoding.
- LZ77 encoding data is compressed by searching for repeated portions of a character string in the data and replacing the character string with the position and length of the repeated portion. For example, when the character string “IBM is IBM” is LZ77-encoded, since the second “IBM” is a repetition, this portion is compressed. Specifically, it is replaced with a code such as “7, 3” indicating that “3 characters length is repeated from 7 characters before” and compressed. In this case, the longer the character length of the repeated portion, the higher the compression rate.
- the search for the repeated portion of the character string is performed on the data from the character string up to a maximum of 32 Kbytes.
- a comparison process is required. Therefore, if it is attempted to do this with software, processing takes time.
- the search time is usually shortened by a hash method.
- the hash method when there are many character strings having the same hash value, some of them may be discarded. That is, there is a problem that it is difficult to completely search all character strings in consideration of processing time and buffer capacity.
- the present applicant has proposed a method in which all character strings can be completely searched by hardware (see, for example, Patent Documents 1 to 3).
- the character string search can be performed very quickly.
- Patent Document 1 when a search character string (ABCA) is searched with respect to a search target character string (BABCABB%) Sequentially stored in an associative memory cell column, the comparison operation with the first character (A) is performed for all cells. Compared with the next character (B), the comparison operation with the next character (B) is performed only with the cell column of the address (2), (5) adjacent to the previously matched cell column, and the comparison operation with the next character (C) is the same.
- the search process is completed in a short time by performing only the cell sequence of addresses (3) and (6) and comparing the last character (A) with the cell sequence of address (4). I am doing so.
- the first switching means is provided between the power supply and the part opposite to the ground end across the match line switching element, and the associative memory switches according to the comparison result.
- the comparison result between the search character in the write buffer and the character data stored in each cell column of the CAM is sequentially held in the first latch and the second latch, and the signal generation circuit has a low input signal. If there is an AND between the output of the first latch and the output of the third latch of the previous stage, and if the input signal is high, an AND of the output of the first latch and the output of the second latch of the previous stage is passed through the third latch.
- the first and second priority encoders output the OR of the input signal, and the signal output from the OR circuit passes through the fourth latch and another OR circuit.
- An object of the present invention is to enable a process performed using a CAM to continue even if an error occurs in the data stored in the CAM if there is no error in the data stored in the CAM.
- the present invention is an apparatus for processing a first partial data element sequence of a data element sequence based on the position of a second partial data element sequence of the data element sequence,
- Each data element of a plurality of data elements constituting at least a part is stored at an address corresponding to the position of each data element in the data element sequence, and when a search data element is given, a match that matches the search data element If the data element is stored as one of a plurality of data elements, an associative memory that outputs an address at which the matching data element is stored, and the input data element is given to the associative memory as a search data element.
- a processing unit that processes the first partial data element sequence using the specific data element output from the second path if an error occurs in the matching data element.
- the second path may have a pipeline configuration that outputs data elements in synchronization with the output of addresses from the first path.
- the present invention also relates to an apparatus for compressing a data element sequence by replacing the first partial data element sequence of the data element sequence with information on the position and length of the second partial data element sequence of the data element sequence.
- the first pass gives a specific data element as a search data element to the associative memory in response to an input of the specific data element included in the first partial data element string Continuous output of column presence information from the first pass, with one condition that there is no error in the matching data element that matches the data element
- the data is replaced with information on the position and length of the second partial data element sequence determined according to the number and the column address information output from the first pass, and an error is found in the matching data element that matches the search data element
- a processing unit that performs a process of partially uncompressing the first partial data element sequence using the specific data element output from the second pass.
- the processing unit when the first pass gives a specific data element as a search data element to the associative memory, the processing unit has a predetermined number of continuous outputs of the column presence information from the first pass in addition to one condition. Processing that replaces with the information on the position and length of the second partial data element sequence determined according to the number of continuous outputs and the column address information output from the first pass, on the condition that the number has been exceeded Do what you do.
- the processing unit when the first pass gives a specific data element as a search data element to the associative memory, the processing unit, if the number of continuous outputs of the column presence information from the first pass does not exceed a predetermined number
- the specific data element output from the second pass may be used to perform processing for partially uncompressing the first partial data element sequence.
- the second path may have a pipeline configuration that outputs data elements in synchronization with the output of the column presence information and the column address information from the first path.
- the present invention provides an apparatus for compressing a data element sequence by replacing the first partial data element sequence of the data element sequence with information on the position and length of the second partial data element sequence of the data element sequence. And storing each data element of a plurality of data elements constituting at least a part of the data element string and a parity element corresponding to each data element at an address corresponding to the position of each data element in the data element string.
- An associative memory that outputs an address at which the matching data element is stored if a matching data element that matches the searching data element is stored as one of the plurality of data elements when the searching data element is given;
- a search data element is given to the associative memory, a matching data element sequence that matches the search data element sequence given so far is stored in the associative memory.
- column presence information indicating that the column of the matching data element is stored and column address information indicating the address where the column of the matching data element is stored are generated.
- the generation circuit and the search data element are given to the associative memory, if the matching data element matching the search data element is stored in the associative memory, the parity stored at the address where the matching data element is stored A determination circuit for determining whether or not an element value is generated from a search data element; and the input data element is given to the associative memory as a search data element, and column presence information and column address information generated by the generation circuit , A second path for outputting the input data element without giving it to the associative memory as a search data element, In response to an input of a specific data element included in the partial data element sequence, a value of the parity element is generated by the determination circuit when the first pass gives the specific data element to the associative memory as a search data element.
- the first partial data element sequence is determined as the number of continuous outputs.
- a process of replacing with the position and length information of the second partial data element sequence determined according to the column address information output from the first path is performed, and it is determined that the parity element value is not generated by the determination circuit. If at least one of the following conditions and the condition that the number of continuous outputs of column presence information from the first pass does not exceed a predetermined number is satisfied, the identification output from the second pass And a processing unit that performs processing for uncompressing a specific data element portion of the first partial data element sequence using the data elements.
- the present invention is a method for processing a first partial data element sequence of a data element sequence based on a position of a second partial data element sequence of the data element sequence, wherein at least part of the data element sequence Is stored in an address corresponding to the position of each data element in the data element sequence, and when a search data element is given, a matching data element that matches the search data element is stored.
- an associative memory that outputs the address where the matching data element is stored, and the input data element is given to the associative memory as a search data element and output from the associative memory And a second path for outputting the input data element without giving it to the associative memory as a search data element,
- a matching data element matching the search data element is displayed.
- the processing performed using the CAM can be continued even if an error occurs in the data stored in the CAM.
- the microcomputer 10 includes a plurality of repetitive data search devices 20a, 20b,... In the present embodiment, which are connected to the bus 18 via a data compression controller 22 that controls the operation of the repetitive data search device. It is connected.
- the repeated data search devices 20a, 20b,... Have the same configuration, and in this embodiment, P + 1 repeated data search devices are provided.
- the configuration of the P + 1 repetitive data search apparatuses will be collectively referred to as “repetitive data search apparatus 20”, and the individual repetitive data search apparatuses will be distinguished from each other by being referred to as “block 0” to “block P”. .
- the CAM cell 28 includes two NOT circuits 30 and 32 having their input terminals and output terminals connected to each other.
- the loop of the NOT circuits 30 and 32 constitutes a storage circuit (SRAM type) that stores 1-bit data.
- the output terminal of the NOT circuit 30 is connected to the source of the N-MOSFET 34
- the output terminal of the NOT circuit 32 is connected to the source of the N-MOSFET 36
- the gates of the N-MOSFETs 34 and 36 are connected to the word line WL. Yes.
- the drains of the N-MOSFETs 34 and 36 are connected to the bit lines BL and BL ′, respectively.
- the word line WL is set to the high level
- the bit line BL is set to the level corresponding to the data D to be written (when D is “1”, “ “0” is low level)
- the bit line BL ′ is inverted with respect to the level of the bit line BL (low level when the bit line BL is high level, high level when the bit line BL is low level) Level).
- the N-MOSFETs 34 and 36 are turned on, and the data supplied via the bit line BL or BL ′ is held in the loop of the NOT circuits 30 and 32.
- the output terminal of the NOT circuit 30 is connected to the gate of the N-MOSFET 38, and the output terminal of the NOT circuit 32 is connected to the gate of the N-MOSFET 40.
- the NOT circuit 32 outputs data (Q ′) obtained by inverting the data D
- the drains of the N-MOSFETs 38 and 40 are connected to the bit lines BL ′ and BL, respectively, and the sources are connected to the gate of the N-MOSFET 42.
- the drain of the N-MOSFET 42 is connected to the match line MATCH, and the source is grounded.
- M + 1 CAM cells 28 are connected to the same word line and match line, and a plurality of CAM cells 28 (hereinafter, referred to as the same word line and match line). These are called CAM cell strings) so that M + 1 bit data can be stored.
- CAM cell strings a plurality of CAM cells 28 (hereinafter, referred to as the same word line and match line).
- the N + 1 parity memory cells 24 have the same configuration. As shown in FIG. 4, the configuration of the parity memory cell 24 is almost the same as the configuration of the CAM cell 28 of FIG. However, the parity memory cell 24 does not have the N-MOSFETs 38, 40, and 42 included in the CAM cell 28, and the NOT circuit 30 so that the data held in the loop of the NOT circuits 30 and 32 is read as it is. Are connected to the read parity line RPL. In the CAM cell array 26, each parity memory cell 24 is also given an address.
- the repeated data search circuit 21 includes a timing controller 50.
- the timing controller 50 is connected to the data compression controller 22.
- the repeated data search circuit 21 compares the input search data with the data stored in each CAM cell column of the CAM cell array 26, and then A “search” mode is executed in which search data is repeatedly written into any CAM cell column of the CAM cell array 26.
- the system clock CLOCK is input from the data compression controller 22 to the timing controller 50, and a clock SR synchronized with the system clock CLOCK is generated and output.
- the clock SR is output to the write buffer 56 connected to the timing controller 50.
- a parity generator 54 is connected to the write buffer 56, and search data is sequentially input from the write buffer 56 to the parity generator 54.
- the parity generator 54 is connected to a write parity line pair WPL, WPL ′, calculates a parity bit based on the input search data, and is synchronized with the clock SR input from the timing controller 50.
- the level of the write parity line pair WPL, WPL ′ is changed according to the calculated parity bit (the bit line pair is driven). While the parity generator 54 drives the bit line pair according to the parity bit, the parity bit is written into a predetermined parity memory cell 24.
- the parity generator 54 is also connected to a search parity line SPL, and changes the level of the search parity line SPL according to the calculated parity bit.
- the address controller 52 is also connected to the timing controller 50, and the clock SR is also output to the address decoder 52.
- the address decoder 52 is connected to the data compression controller 22, and an address (write address WADR) of a CAM cell string to which search data is written is designated from the data compression controller 22.
- Word lines WL0 to WLN are connected to the address decoder 52, and more specifically within a period in which the write buffer 56 drives each bit line pair according to predetermined search data at a timing synchronized with the clock SR.
- the word line corresponding to the specified write address WADR is asserted (enabled), and the predetermined search data is The parity bit calculated from the predetermined search data is written to the parity memory cell 24 corresponding to the designated address while writing to the CAM cell column corresponding to the designated address.
- the timing controller 50 is also connected to N + 1 match line controllers 58 0 to 58 N respectively connected to the match lines MATCH0 to MATCHN, and the clock SR is supplied to each of the match line controllers 58 0 to 58 N. Is also output.
- the match line controllers 58 0 to 58 N charge (precharge) the match lines MATCH0 to MATCHN to a high level prior to the comparison between the data stored in each CAM cell column and the search data based on the input clock SR. .
- the match line precharge by the match line controllers 58 0 to 58 N is performed after each bit line pair corresponding to the next search data after the write buffer 56 finishes driving each bit line pair corresponding to the predetermined search data. It is performed within a period until the driving of the pair is started.
- the match lines MATCH0 to MATCHN are connected to the comparison result control circuit 60, respectively.
- the comparison result control circuit 60 includes latches 62 0 to 62 N , signal generation circuits 64 0 to 64 N , and latches 66 0 to 66 N.
- illustration of the match line controllers 58 0 to 58 N is omitted.
- FIG. 5 shows a specific configuration of only the signal generation circuit 64 1 connected to the match line MATCH1 among the signal generation circuits 64 0 to 64 N , but the other signal generation circuits have the same configuration. Only the circuit portion corresponding to the match line MATCH1 in the comparison result control circuit 60 will be described below.
- the output terminal of the AND circuit 68 1 is connected to the input terminal of the latch 66 1, the output terminal of the latch 66 1 is similar to the above, OR circuit 72 2 and the AND circuit (not shown) of the next-stage signal generating circuit 64 2 They are respectively connected to the 70 second input terminal.
- the output terminal of the latch 66 1 is also connected to the input of the first priority encoder 74. Furthermore, one is connected to the input terminal, the other AND circuits 70 0 to the input terminal (not shown), 70 2 ⁇ 70 N of the output terminal of the OR circuit 78 of the output terminal OR circuit 78 of the AND circuit 70 1 Is connected.
- FIG. 5 shows the comparison result control circuit 60 of the repeat data search circuit 21 of the block 0, one of the two input terminals of the OR circuits 72 0 of the signal generating circuit 64 0, the comparison result of the block P It is connected to the output terminal of the latch 66 N of the control circuit 60.
- the output terminal of latch 66 N comparison result control circuit 60 of the block 0 is connected to one of two input terminals of the OR circuits 72 0 of the comparison result control circuit 60 of the block 1 (Fig. 2 See also ).
- the output terminal of the first priority encoder 74 is connected to the input terminal of the second priority encoder 76.
- the first priority encoder 74 encodes the address corresponding to the signal input signal after "search" operation of each signal input from the 66 0 ⁇ 66 N of the comparison result control circuit 60 is at high level
- the coincidence address MADR0 is output to the second priority encoder 76, and the logical sum of the signals input from the latches 66 0 to 66 N is output to the second priority encoder 76 as the coincidence signal MSIG0.
- the address of the associative memory cell column having a high priority according to a predetermined standard is used as the match address MADR0. For example, the lowest address or the address closest to the current write address WADR is output. The latter address is output because the distance information used for compression can be small, resulting in a high compression rate.
- match address MADR and the match signal MSIG output from the first priority encoder 74 of the other repeated data search circuit 21 are also input to the input terminal of the second priority encoder 76.
- the output terminal of the second priority encoder 76 is connected to the data compression controller 22.
- the second priority encoder 76 has substantially the same configuration as that of the first priority encoder 74.
- MSIG0 to MSIGP are previously selected from those having a high level.
- the close address is output to the data compression controller 22 as the match address MADR, and a signal representing the logical sum of the match signals MSIG0 to MSIGP input from the plurality of first priority encoders 74 is output to the data compression controller 22 as the match signal MSIG.
- the comparison result control circuit 60 also includes EXOR circuits 82 0 to 82 N and NAND circuits 84 0 to 84 N. Only the circuit portion corresponding to the read parity line RPL1 will be described below.
- Read parity line RPL1 is connected to one of two input terminals of the EXOR circuit 82 1, the other two input terminals of the EXOR circuit 82 1 search parity line SPL is connected.
- the output terminal of the EXOR circuit 82 1 is connected to one of two input terminals of the NAND circuit 84 1, the other two input terminals of the NAND circuit 84 1 is connected to the output terminal of the latch 62 1 .
- the output terminal of the NAND circuit 84 1 is connected to one input terminal of the OR circuit 86 via an inverter, and the other input terminals of the OR circuit 86 are connected to the NAND circuits 84 0 , 84 2 to 84 N. The output end is connected via an inverter.
- the output terminal of the OR circuit 86 is connected to one input terminal of the OR circuit 88, and the output terminal of the OR circuit 86 of the other repeated data search circuit 21 is connected to the other input terminal of the OR circuit 88. ing.
- the parity error signal PE output from the OR circuit 88 is output to the data compression controller 22 (see also FIG. 2).
- the data compression controller 22 sequentially extracts unit data having a predetermined bit length from the original data as search data, as will be described later, and repeatedly performs a data search circuit together with a search instruction SEARCH and a write address WADR. 21 sequentially output.
- the repetitive data search circuit 21 When the search instruction SEARCH is input, the repetitive data search circuit 21 outputs the clock SR from the timing controller 50 to the write buffer 56, the address decoder 52 and the match line controllers 58 0 to 58 N , and the match line controller 58 outputs the CAM cell array 26.
- the match lines MATCH0 to MATCHN Prior to the comparison operation in, the match lines MATCH0 to MATCHN are precharged, and the write buffer 56 holds the input search data and drives the bit line pairs BL0, BL0 'to BLM, BLM' according to the search data To do.
- each CAM cell 28 of the CAM cell array 26 if the data Q output from the NOT circuit 30 is “1” (high level), the N-MOSFET 38 is on, and the data Q ′ output from the NOT circuit 32 is If “1”, the N-MOSFET 40 is on. Accordingly, when the data Q (Q ′) held in the loop of the NOT circuits 30 and 32 and the data D (D ′) supplied via the bit line pair BL and BL ′ coincide with each other, N -MOSFET 42 does not turn on, but if they do not match, current flows from the drain to the source of the N-MOSFET 38, 40 which is turned on, and the N-MOSFET 42 is turned on. Thereby, the level of the precharged match line MATCH is lowered to a low level (discharge).
- the above data comparison is performed simultaneously in each of the CAM cells 28.
- CAM cell string CAM cell string
- the character data stored in the CAM cell string is inputted in almost the first half of one cycle of the clock SR.
- each match line corresponds to the character data stored in the CAM cell column.
- the high level state is maintained only when the character data input to the write buffer 56 matches, and the low level is set when the character data does not match.
- the word line of the CAM cell column corresponding to the input write address WADR is asserted (enabled) by the address decoder 52, and the search data is written into the CAM cell column.
- the match line controller 58 precharges each match line. Is done again.
- the above operation is performed during one cycle of the clock SR, and is repeated in synchronization with the input of the search data from the data compression controller 22, the search instruction SEARCH, and the write address WADR.
- the repeated data search circuit 21 also performs a parity check of the character data stored in each CAM cell column, so the parity check operation will also be described.
- the EXOR circuit 82 compares the level of the search parity line SPL output from the parity generator 54 with the level of the read parity line RPL output from the parity memory cell 24, and if they match, outputs a low level signal. If there is a mismatch, a high level signal is output.
- the signal output from the latch 62 is set to high level to indicate data match, and the signal output from the EXOR circuit 82 is set to low level to indicate parity bit match, or is output from the latch 62.
- the NAND circuit 84 outputs a high level signal when the signal is set to a low level and indicates a data mismatch.
- the NAND circuit 84 Outputs a low level signal.
- the OR circuit 86 When at least one of the signals output from the NAND circuits 84 0 to 84 N is at a low level, the OR circuit 86 outputs a high level signal, and the OR circuit 88 compresses the parity error signal PE. Output to the controller 22.
- character data is an example of a data element
- a parity bit is an example of a parity element.
- the signal when ORFB is “1” is an example of column presence information indicating that a column of matching data elements that matches the column of search data elements is stored, and MADR is the search data element column. It is an example of column address information indicating an address where a column of matching data elements that match the column is stored, and includes a signal generation circuit 64, a latch 66, a first priority encoder 74, a second priority encoder 76, an OR circuit 78, OR
- the portion composed of the circuit 80 is an example of a generation circuit.
- a portion including the latch 62, the EXOR circuit 82, the NAND circuit 84, the OR circuit 86, and the OR circuit 88 is an example of a determination circuit.
- the original data is text data
- the character data string “ABABBC” is already stored in order in the CAM cell strings of addresses “0” to “5”
- latch 62 0-62 5 ML0 ⁇ ML5 are referred to as latches 66 0-66 5 PS0 ⁇ PS5.
- latches 66 0-66 5 PS0 ⁇ PS5. it is assumed that the result of the comparison operation is continuously “mismatched” in other repeated data search apparatuses.
- the levels held in the latches PS0 to PS5 are low (“0” in FIG. 6: latches PS6 to PSN not shown, and latches of other blocks). Therefore, the signals output from the AND circuits 70 0 to 70 5 are all at the low level, and are output from the feedback signal ORFB 0 output from the OR circuit 78 and the OR circuit 80.
- the feedback signal ORFB also goes low.
- the feedback signal ORFB does not become high level only when only one character is matched, that is, when there is a CAM cell string whose comparison result is “match” in one comparison operation.
- the feedback signal ORFB becomes the high level only when two or more characters are continuously matched, that is, when the data string composed of a plurality of search data continuously input is stored in the CAM cell array 26.
- the coincidence address MADR0 becomes the address “0” corresponding to PS0.
- the match address MADR output from the second priority encoder 76 depends on the value of the match address input from another repeated data search device, but the data does not match in the other repeated data search device. In this case, the value of the lower-order bit of the match address MADR is equal to the value of the match address MADR0.
- the value of the upper bit of the coincidence address MADR is the address of the coincident encoder block (the address given to each of the plurality of repetitive data retrieval devices). In this case, it is all 0 because it is the block of address 0. .
- the same match line as the previous time becomes high level, and the level of each match line is once set in the latches ML0 to ML5. after being held, they are respectively outputted to the signal generating circuit 64 0-64 5.
- the output is also output high level of the previous latch PS of latch ML1, ML3, ML4, which becomes high level latch because only the latch ML4, output from the AND circuit 70 1, 70 3, 70 4 only the signal outputted from the aND circuit 70 4 of that signal becomes a high level. Therefore, the feedback signal ORFB0 output from the OR circuit 78 is maintained at the high level, and the coincidence address MADR0 becomes the address “4” corresponding to PS4.
- character data “B” is input as the next search data.
- the latch although levels of the match lines, each of which is input to the signal generating circuit 64 0-64 5 after each has been temporarily held in the latch ML0 ⁇ ML5 is the same as the previous, outputs a high level signal ML1, ML3, for any of ML4 also, the signal output from the previous latch PS is at a low level, both the signal output from the aND circuits 70 0 to 70 5 becomes a low level, the feedback signal ORFB0 and the feedback signal ORFB Becomes low level.
- the feedback signal ORFB becomes low level
- the output signal of the OR circuits 72 0-72 5 of the signal generating circuits 64 0-64 5 are each a high level
- the level of the signal output from the latch ML1 ⁇ ML5 are It is held in the latches PS0 to PS5 as they are.
- the repeated data search circuit 21 can search for a match of one character in one clock, and enables a character string search that is overwhelmingly faster than other methods. Specifically, every time one character is input, the input character can be compared with all the characters in the CAM cell array 26, so that high-speed search is possible.
- FIG. 7 shows a case where a parity error has occurred in the repeated data search operation by the repeated data search circuit 21.
- character strings up to “IBMisIB” are sequentially stored in the CAM cell array 26.
- the CAM cell array 26 also stores parity bits (represented by “p”) corresponding to each character.
- the numbers written on the left side of the CAM cell array 26 indicate the addresses of the cell columns of the CAM, and correspond to the N value of the word line WLN (match line MATCHN, read parity line RPLN).
- the repeated data search circuit 21 sequentially compares the character string stored in the CAM cell array 26. That is, when the first character “I” is input to the write buffer 56, the character data at the address 0 matches this, so the match line MATCH0 is maintained in the high level state. When the second character “B” is input to the write buffer 56, the character data at the address 1 matches this, so the match line MATCH1 is maintained at the high level. Further, when the third character “M” is input to the write buffer 56, the character data at the address 2 matches this, so the match line MATCH2 is maintained at the high level.
- the match line MATCH3 is maintained in a high level state, but a parity error is detected (indicated by “x” in the figure). ).
- a parity error is detected (indicated by “x” in the figure). ).
- the cause for example, it is conceivable that what was originally a different character has become the same bit sequence as the character “i” due to bit flip or the like due to noise.
- the match with the letter “i” at this time becomes unreliable. That is, the reliability of the data in the CAM cell array 26 cannot be guaranteed. Accordingly, no further processing can be performed, and it is necessary to interrupt the processing of the data search circuit 21 at this point. In this case, usually, a method of starting all over from the beginning is adopted.
- the data supplier is notified that a parity error has occurred, and the data is sent again from the beginning.
- the error can be recovered by having the data flow again.
- a parity error occurs permanently rather than temporarily due to a bit damage or the like of the CAM cell array 26, the CAM cell array 26 is faulty and cannot be recovered.
- FIG. 8 is a diagram showing a configuration example (part) of the repeated data search device 20 and the data compression controller 22 in this case.
- the repetitive data search device 20 includes the repetitive data search circuit 21 described with reference to FIGS.
- the data compression controller 22 also holds a flip-flop 90 that holds the character data (character code) output from the repeated data search circuit 21 and a match address (MADR in FIG. 2) output from the repeated data search circuit 21.
- Flip-flop 92, a counter 94 that counts the number of times the character string match signal (ORFB in FIG. 2) is continuously output from the repeated data search circuit 21, and a parity error signal ( 2 and a flip-flop 96 that holds PE) in FIG.
- the data compression controller 22 selects either the character data held by the flip-flop 90 based on the count result of the counter 94, or the set of the coincidence address held by the flip-flop 92 and the count result of the counter 94.
- a selector 98 for outputting is also included.
- character data is input to the repeated data search circuit 21 in units of 1 byte.
- the character data input source is the data compression controller 22.
- the repeated data search circuit 21 sequentially writes the input character data to the CAM and compares it with all the character data written so far. If there is matching character data, “1” is set as the character string match signal. Is output. However, as this character string match signal, “1” is not output when only one character is matched, but “1” is output when two or more characters are matched continuously. While the character strings match, “1” is continuously output.
- “1” for one clock is output as the character string match signal, and when it falls to “0” in the next clock, this represents a two-character match.
- “1” is output for two clocks as a character string match signal and falls to “0” at the next clock, this indicates a match of three characters.
- “1” is output for K clocks and falls to “0” at the next clock, this indicates a match of K + 1 characters. Therefore, the data compression controller 22 can detect how many characters match by counting the character string match signal by the counter 94.
- the repeated data search circuit 21 outputs the address of the CAM that matches the character data as a match address, and the flip-flop 92 holds this. Further, the repeated data search circuit 21 outputs the input character data regardless of whether the character data matches or not, and the flip-flop 90 holds it. This character data is required as non-compressed data when there is no match between the character data.
- the selector 98 outputs the character data held in the flip-flop 90 when there is no match of the character data, and the match held in the flip-flop 92 when there is a match of the character data.
- the number of times counted by the address and counter 94 (the number of consecutive matches of character data) is output.
- the repeated data search circuit 21 when a parity error occurs in the repeated data search circuit 21, the repeated data search circuit 21 outputs “1” to the data compression controller 22 as a parity error signal.
- the data compression controller 22 recognizes that the character string match signal and the character code are not reliable. In this case, since the compression process cannot be continued, the compression target data is flowed again.
- FIG. 9 is a diagram showing a configuration example (part) of the repeated data search device 20 and the data compression controller 22 in the present embodiment.
- the repetitive data search device 20 includes flip-flops 100 1 , 100 2 , 100 3 , and 100 4 in addition to the configuration of FIG.
- the compressed data path is an example of a first path, and is a path for performing compression based on the search result of the repeated data search circuit 21.
- the uncompressed data path is an example of a second path, and is a path through which input character data flows as it is.
- the repeated data search device 20 has a redundant configuration by providing two paths.
- the flip-flops 100 1 , 100 2 , 100 3 , 100 provided outside the repeated data search circuit 21 are not the character data that has passed through the repeated data search circuit 21 as shown in FIG.
- the character data passed through 4 is held in the flip-flop 102.
- the signal generation circuit 104 When a parity error occurs in the repetitive data search circuit 21 and the repetitive data search circuit 21 outputs a parity error signal, the signal generation circuit 104 outputs a signal instructing to select data of the uncompressed data path. Output to selector 98. Thus, the selector 98 selects the character data held in the flip-flop 102 and outputs it to the processing portion of the data compression controller 22.
- the signal generation circuit 104 has two or less consecutively matched characters. If there is, a signal instructing to select data in the uncompressed data path is output to the selector 98. Thus, the selector 98 selects the character data held in the flip-flop 102 and outputs it to the processing portion of the data compression controller 22. If the number of consecutively matched characters is 3 or more, a signal instructing selection of data in the compressed data path is output to the selector 98.
- the selector 98 selects a set of character data held in the flip-flop 92 and the count result of the counter 94 and outputs the set to the processing portion of the data compression controller 22. It should be noted that when the number of consecutively matched characters is 2 or less, the data of the uncompressed data path is selected, and when the number of consecutively matched characters is 3 or more, the data of the compressed data path is selected. This is because the compression effect cannot be obtained even if the matching character string is compressed using the position and length in the case of 2 or less.
- the repeated data search circuit 21 since no parity error has occurred until the first “IBM”, the repeated data search circuit 21 operates normally, and the selector 97 assumes that the three characters “IBM” match ( 0,3) is output. Thereafter, since a parity error has occurred, the selector 98 outputs the character data “i” as it is as the fourth character. That is, the output data is (0, 3) and “i” in order. On the other hand, if no parity error has occurred in the repeated data search circuit 21, since four characters match up to “IBMi”, the selector 98 outputs (0, 4).
- the repetitive data search circuit 21 in the compressed data path of FIG. 9 is configured such that character data is input by one character (1 byte) every clock and the input character data is processed by a four-stage pipeline. It has become. That is, the character data is written to the CAM cell array 26 at the first clock, the character data match is held in the latch 62 at the second clock, and the character string match just before the character data is latched at the latch 66 at the third clock. The coincidence address is held in the flip-flop 92 at the fourth clock. Therefore, the coincidence address and the character string coincidence signal are output 4 clocks after the character data is inputted.
- the non-compressed data path also needs to have the same number of stages as the compressed data path as a four-stage pipeline configuration of flip-flops 100 1 , 100 2 , 100 3 , and 100 4 .
- the number of stages is merely an example. If the number of stages of the compressed data path is K, the number of stages of the non-compressed data path needs to be K.
- the data compression controller 22 determines whether or not the parity error signal PE has become high level (step 207). Processing when the parity error signal PE is at a high level and the determination is affirmed will be described later. If the parity error signal PE is at a low level and the determination is negative, the data compression controller 22 determines whether or not the character string match signal ORFB output from the data search device 20 has repeatedly been at a high level ( Step 208). At this time, the character string match signal ORFB is maintained at the low level in accordance with the reset of each latch 62 and each latch 66 in the previous step 200, so the determination is negative and the routine proceeds to step 210.
- the data compression controller 22 determines whether or not the current comparison operation is the first comparison operation with respect to predetermined original data (step 210). If the determination is affirmative, the compressed data is output in step 212. The process proceeds to step 214 without performing processing. As described above, the character string match signal ORFB does not become high unless two or more characters are matched continuously. Therefore, when the comparison result “mismatch” continues, the previously searched character is output as compressed data as will be described later. . Therefore, since there is no data to be output as compressed data at this time, step 212 is not executed.
- the data compression controller 22 assigns “1” to the match length MLEN (step 214), and proceeds to step 218. Then, the data of the previous search character C1 is set in the previous search character C2 and the data of the current character C0 is set in the previous search character C1 (step 218), and the current write address WADR (0 in the first comparison operation) is set. The data of the character C0 is written in the CAM cell string corresponding to (). This write process is actually performed by asserting (enabling) the word line of the CAM cell column corresponding to the write address WADR by the address decoder 52.
- the data compression controller 22 adds 1 to the write address WADR as the next write address WADR (therefore, the character data is written in ascending order of the address of the CAM cell column), and the remainder obtained by dividing by the size N + 1 of the CAM cell array 26 Is set (step 222).
- the CAM cell array 26 is used as a so-called ring buffer, and the CAM cell array 26 overflows. There is nothing.
- step 222 After performing the process of step 222, the process returns to step 204. If the determination in step 204 is negative, the processing from step 206 is executed again. In step 206, the data of the character C0 following the previous search character C1 is extracted from the original data as search data, and the search instruction SEARCH is written. The data is repeatedly output to the data search device 20 together with the address WADR. If the determination in step 208 is negative, the process proceeds to step 210. If this determination is negative, the compressed data output process in step 212 is performed.
- the data compression controller 22 determines whether or not the match length MLEN is 0 in this compressed data output process (step 229). If the previous parity error signal PE was at a high level, all data up to that point was output and the match length MLEN was 0 by the processing described later, so that the data is not output as compressed data. The process proceeds to step 214 in the flowchart of 10-1. If the determination in step 229 is negative, the data compression controller 22 determines whether or not the match length MLEN is 2 (step 230). Although the previous comparison result is “match”, if the previous comparison result is not “match”, the determination is affirmed, and the data of the search character C2 is output as the compressed data (step 236), and then the previous search character.
- step 238 The data of C1 is output (step 238), and then the process proceeds to step 214 in the flowchart of FIG. If the determination in step 230 is negative, the data compression controller 22 determines whether or not the match length MLEN is 1 (step 232). If the previous comparison result is not “match”, the determination is affirmed, the data of the previous search character C1 is output as the compressed data (step 238), and then the process proceeds to step 214 in the flowchart of FIG.
- step 208 determines whether the match length MLEN is counted up (step 216), and then the process proceeds to step 218. Therefore, the compressed data is not output while the character string match signal ORFB is at the high level.
- step 212 the compressed data output process is performed. At this time, if the comparison results of the previous time and the previous time are both “match”, the match length MLEN is counted up in step 216 described above to be 3 or more, so steps 229, 230, and 232 are performed. Both of these determinations are denied, and the routine proceeds to step 234.
- the data compression controller 22 obtains a compression code for repeatedly compressing the character string.
- a compressed code composed of a first code representing a pointer indicating the position of the same character string as the repeated character string and a second code representing the length of the repeated character string is used. Then, a value obtained by adding 1 to the difference between the match address MADR and the match length MLEN (MADR ⁇ MLEN + 1) is set as the first code, and the match length MLEN is set and output as the second code (step 234). Thereby, the length of the compressed data output from the data compression controller 22 becomes shorter than the original data.
- the data compression controller 22 separates the character data from the compressed code so that the compressed code and the character data can be distinguished when the compressed character string is restored. Also insert a code to represent. In this way, every time a repeated character string is found, step 234 is executed, and the found repeated character string is converted into a compressed code and output, thereby removing the redundancy of the original data and It will be compressed into compressed data.
- step 207 in the flowchart in FIG. 10-1 If the determination in step 207 in the flowchart in FIG. 10-1 is affirmed, the process proceeds to step 240 in the flowchart in FIG. 10-2. If this determination is denied, the compressed data output process in step 242 is performed. Is called. Since this compressed data output processing has already been described with reference to the flowchart of FIG. When the parity error signal PE becomes high level, the character string match signal ORFB is not reliable. At this time, the character C0 obtained via the uncompressed data path of the repeated data search device 20 is output (step 244). . Then, “0” is substituted into the match length MLEN (step 246), the process proceeds to step 218 in the flowchart of FIG. 10-1, and thereafter the above processing is continued.
- step 224 the data compression controller 22 performs the compressed data output process again (step 224).
- the compressed code is output in step 234. If the value of the match length MLEN is 2, search is performed as compressed data in steps 236 and 238 one after another. If the character C2 data and the previous search character C1 data have a match length MLEN value of 1, the data of the previous search character C1 is output as compressed data in step 238, and the process ends.
- a pointer indicating the position of the same character string as the repeated character string is used as the first code in the compressed code.
- the position of the same character string as the repeated character string is used.
- the distance between the position of the repeated character string may be used.
- a value obtained by subtracting the position of the same character string as the repeated character string from WADR may be used as the first code.
- a compressed data path for outputting the length, and when a parity error occurs in the CAM, character data from the uncompressed data path is used.
- the processing using the character data can be continued without interruption.
- a character string is compressed by replacing a part of a character string with information on the position and length of another part, but a part of the character string is replaced with another part. It may be assumed that processing is performed based on the position of In this case, the compressed data path is a path from the part where the character data of the CAM cell array 26 is input to the part where the address of the character data matching the character data is output, and the non-compressed data path is from the compressed data path.
- a path having a pipeline configuration that outputs character data in synchronization with the output of the address may be used.
- the parity bit is stored in the CAM cell array 26, but may be stored in another memory other than the CAM cell array 26. Further, although a parity error has been mentioned as an error occurring in data stored in the CAM cell array 26, the present invention can be similarly applied even when an error other than a parity error occurs.
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Abstract
Description
従って、これをソフトウェアで行おうとすると、処理に時間がかかってしまう。ソフトウェアでは、通常、ハッシュ法により、検索時間の短縮を図ることになる。しかしながら、ハッシュ法では、同じハッシュ値を持つ文字列が多い場合、その一部が捨てられてしまうことがある。つまり、全ての文字列を完全に検索することは、処理時間とバッファ容量を考慮すると難しいという問題があった。
また、処理部は、第1のパスが特定のデータ要素を検索データ要素として連想メモリに与えた場合に、第1のパスからの列存在情報の連続出力回数が所定数を超えなかったならば、第2のパスから出力された特定のデータ要素を用いて、第1の部分データ要素列を部分的に非圧縮とする処理を行う、ものであってよい。
また、第2のパスは、第1のパスから列存在情報と列アドレス情報とが出力されるのと同期してデータ要素を出力するようなパイプライン構成を有する、ものであってよい。
図1は、本実施の形態が適用されるマイクロコンピュータ10の構成(一部)を示す。マイクロコンピュータ10は、CPU12、ROM14、RAM16を備えており、これらはアドレスバス、データバス、コントロールバス等からなるバス18を介して互いに接続されている。
繰り返しデータ検索回路21は、図に「○」で示す多数の連想メモリセル(以下、連想メモリをCAMという)28がマトリクス状に配置されて構成されたCAMセルアレイ26を備えている。CAMセルアレイ26にはN+1本のワード線WL0~WLN、N+1本のマッチ線MATCH0~MATCHN、M+1組のビット線対BL0,BL0'~BLM,BLM'が各々マトリクス状に配置されており、各CAMセル28は、ワード線WL0~WLNの何れか、マッチ線MATCH0~MATCHNの何れか、及び、ビット線対BL0,BL0'~BLM,BLM'の何れかに各々接続されている。
尚、CAMセルアレイ26では、各パリティメモリセル24にもアドレスが付与されている。
EXOR回路82は、パリティ生成器54から出力された検索パリティ線SPLのレベルと、パリティメモリセル24から出力された読出しパリティ線RPLのレベルとを比較し、一致する場合にはローレベルの信号を出力し、不一致の場合にはハイレベルの信号を出力する。
一方、ラッチ62から出力された信号がハイレベルにされ、データの一致を示し、かつ、EXOR回路82から出力された信号がハイレベルにされ、パリティビットの不一致を示す場合、NAND回路84は、ローレベルの信号を出力する。
図7は、繰り返しデータ検索回路21による繰り返しデータ検索動作でパリティエラーが発生した場合について示したものである。
まず、CAMセルアレイ26に「IBMisIB」までの文字列が順次格納されたとする。また、CAMセルアレイ26には各文字に対応するパリティビット(「p」で表す)も格納されているとする。尚、図において、CAMセルアレイ26の左側に記載した数字は、CAMの各セル列のアドレスを示しており、ワード線WLN(マッチ線MATCHN、読出しパリティ線RPLN)のNの値に対応する。
この場合、通常は、最初から全てをやり直すという方法が採られる。つまり、パリティエラーが起きたことをデータ供給元に伝え、再度データを最初から流してもらう。
このとき、ノイズ等により一時的にパリティエラーが発生したのであれば、再度データを流してもらうことにより、エラーを回復することが可能である。しかしながら、CAMセルアレイ26のビットの破損等により、一時的ではなく、恒久的にパリティエラーが発生する場合は、CAMセルアレイ26の故障であって、回復は不能となる。
図8は、この場合の繰り返しデータ検索装置20及びデータ圧縮コントローラ22の構成例(一部)を示した図である。
図示するように、繰り返しデータ検索装置20は、図2~図6で述べた繰り返しデータ検索回路21を含む。また、データ圧縮コントローラ22は、繰り返しデータ検索回路21から出力された文字データ(文字コード)を保持するフリップフロップ90と、繰り返しデータ検索回路21から出力された一致アドレス(図2のMADR)を保持するフリップフロップ92と、繰り返しデータ検索回路21から文字列一致信号(図2のORFB)が連続して出力された回数をカウントするカウンタ94と、繰り返しデータ検索回路21から出力されたパリティエラー信号(図2のPE)を保持するフリップフロップ96とを含む。更に、データ圧縮コントローラ22は、カウンタ94のカウント結果に基づき、フリップフロップ90が保持する文字データ、及び、フリップフロップ92が保持する一致アドレスとカウンタ94のカウント結果のセットの何れかを選択して出力するセレクタ98も含む。
まず、繰り返しデータ検索回路21に1バイト単位で文字データが入力される。尚、図には明記していないが、この文字データの入力元はデータ圧縮コントローラ22である。 繰り返しデータ検索回路21は、入力された文字データをCAMに順次書き込むと共に、それまでに書き込まれた全ての文字データと比較し、一致する文字データが存在すれば、文字列一致信号として「1」を出力する。但し、この文字列一致信号として、単に1文字が一致しただけでは「1」は出力せず、2文字以上連続して一致した場合に「1」を出力する。そして、文字列が一致している間は「1」を出力し続ける。つまり、文字列一致信号として、1クロック分「1」が出力され、すぐ次のクロックで「0」に落ちた場合、これは2文字一致を表す。また、文字列一致信号として、2クロック分「1」が出力され、次のクロックで「0」に落ちた場合、これは3文字一致を表す。以下同様に、Kクロック分「1」が出力され、次のクロックで「0」に落ちた場合、これはK+1文字の一致を表す。従って、データ圧縮コントローラ22は、文字列一致信号をカウンタ94によりカウントすることで、何文字一致したかを検出することができる。
更に、繰り返しデータ検索回路21は、文字データの一致があってもなくても、入力された文字データを出力し、フリップフロップ90がこれを保持する。尚、この文字データは、文字データの一致がなかった場合に非圧縮のデータとして必要となるものである。
図9は、本実施の形態における繰り返しデータ検索装置20及びデータ圧縮コントローラ22の構成例(一部)を示した図である。
図示するように、繰り返しデータ検索装置20は、図8の構成に加え、フリップフロップ1001、1002、1003、1004を含む。また、データ圧縮コントローラ22は、図8のフリップフロップ90に代えて、フリップフロップ1004から出力された文字データを保持するフリップフロップ102を含み、加えて、カウンタ94のカウント結果及びフリップフロップ96からのパリティエラー信号に基づいてセレクタ98に出力する信号を生成する信号生成回路104を含む。本実施の形態では、処理部の一例として、データ圧縮コントローラ22を設けている。
繰り返しデータ検索回路21が一致アドレス及び文字列一致信号を出力し、フリップフロップ92が一致アドレスを保持し、カウンタ94が連続一致回数をカウントするところまでは、図8と同様である。
一方、繰り返しデータ検索回路21内でパリティエラーが発生していない場合は、「IBMi」まで4文字が一致したことになるので、セレクタ98は、(0,4)を出力する。
図10-1及び図10-2は、データ圧縮コントローラ22における処理を示したフローチャートである。尚、この処理は、データ圧縮コントローラ22にバス18を介して圧縮すべきデータ(元データ)が転送され、CPU12から元データの圧縮が指示されると実行される。
ステップ229で判定が否定された場合、データ圧縮コントローラ22は、一致長MLENが2か否か判定する(ステップ230)。前回の比較結果は「一致」であるが、前々回の比較結果が「一致」でない場合は判定が肯定され、圧縮データとして、前々回検索文字C2のデータを出力し(ステップ236)、次いで前回検索文字C1のデータを出力し(ステップ238)、その後に図10-1のフローチャートのステップ214へ移行する。
ステップ230で判定が否定された場合、データ圧縮コントローラ22は、一致長MLENが1か否かを判定する(ステップ232)。前回の比較結果が「一致」でない場合は判定が肯定され、圧縮データとして前回検索文字C1のデータを出力し(ステップ238)、その後に図10-1のフローチャートのステップ214へ移行する。
パリティエラー信号PEがハイレベルになった場合は、文字列一致信号ORFBが信頼できないので、この時点で、繰り返しデータ検索装置20の非圧縮データパス経由で得た文字C0を出力する(ステップ244)。そして、一致長MLENに「0」を代入して(ステップ246)、図10-1のフローチャートのステップ218へ移行し、その後は上記処理を継続する。
このように、本実施の形態では、繰り返しデータ検索装置20内に、入力された文字データをそのまま流す非圧縮データパスと、入力された文字データに連続して一致するCAM内の文字列の位置及び長さを出力する圧縮データパスとを設け、CAMにパリティエラーが発生すると、非圧縮データパスからの文字データを用いるようにした。これにより、CAM内の文字データにパリティエラーが発生しても、文字データを用いた処理を中断することなく継続できるようになる。
・ケース1:一時的な場合
これは、宇宙線、ノイズ等の影響で偶発的に一度だけ起きる場合である。この場合は、再度データを読み出せば、エラーは発生しない。
・ケース2:セルが故障した場合
通常、CAM等のメモリセルは、工場出荷時にテストされているので、最初から壊れて出荷されることは殆どない。従って、動作中に故障した場合がこれにあたる。
本実施の形態は、ケース1、ケース2の両方において有効である。
ケース1は、一時的なものなので、一時的に圧縮率が下がるだけである。ケース2は、故障したセルがヒットしたときは常に圧縮率が下がることになる。しかしながら、本実施の形態によれば、何れの場合も、データ自体が壊れるわけではないので、問題にはならない。
Claims (8)
- データ要素列の第1の部分データ要素列を、当該データ要素列の第2の部分データ要素列の位置に基づいて処理する装置であって、
前記データ要素列の少なくとも一部を構成する複数のデータ要素の各データ要素を、当該データ要素列における当該各データ要素の位置に応じたアドレスに記憶し、検索データ要素が与えられた場合に、当該検索データ要素に一致する一致データ要素を当該複数のデータ要素の1つとして記憶していれば、当該一致データ要素が記憶されているアドレスを出力する連想メモリと、
入力されたデータ要素を前記検索データ要素として前記連想メモリに与え、当該連想メモリから出力された前記アドレスを出力する第1のパスと、
入力されたデータ要素を前記検索データ要素として前記連想メモリに与えることなく出力する第2のパスと、
前記第1の部分データ要素列に含まれる特定のデータ要素の入力に応じて、前記第1のパスが当該特定のデータ要素を前記検索データ要素として前記連想メモリに与えた場合に、当該検索データ要素に一致する一致データ要素に誤りが発生していなければ、前記第1のパスから出力された前記アドレスに応じて決まる前記第2の部分データ要素列の位置を用いて当該第1の部分データ要素列を処理し、当該検索データ要素に一致する一致データ要素に誤りが発生していれば、前記第2のパスから出力された当該特定のデータ要素を用いて当該第1の部分データ要素列を処理する処理部と
を含む、装置。 - 前記第2のパスは、前記第1のパスから前記アドレスが出力されるのと同期して前記データ要素を出力するようなパイプライン構成を有する、請求項1の装置。
- データ要素列の第1の部分データ要素列を、当該データ要素列の第2の部分データ要素列の位置及び長さの情報で置換することにより、当該データ要素列を圧縮する装置であって、
前記データ要素列の少なくとも一部を構成する複数のデータ要素の各データ要素を、当該データ要素列における当該各データ要素の位置に応じたアドレスに記憶し、検索データ要素が与えられた場合に、当該検索データ要素に一致する一致データ要素を当該複数のデータ要素の1つとして記憶していれば、当該一致データ要素が記憶されているアドレスを出力する連想メモリと、
前記検索データ要素が前記連想メモリに与えられた場合に、それまでに与えられた検索データ要素の列に一致する一致データ要素の列が当該連想メモリに記憶されていれば、当該連想メモリから出力される前記アドレスに基づいて、当該一致データ要素の列が記憶されていることを示す列存在情報と、当該一致データ要素の列が記憶されているアドレスを示す列アドレス情報とを生成する生成回路と、
入力されたデータ要素を前記検索データ要素として前記連想メモリに与え、前記生成回路により生成された前記列存在情報と前記列アドレス情報とを出力する第1のパスと、
入力されたデータ要素を前記検索データ要素として前記連想メモリに与えることなく出力する第2のパスと、
前記第1の部分データ要素列に含まれる特定のデータ要素の入力に応じて、前記第1のパスが当該特定のデータ要素を前記検索データ要素として前記連想メモリに与えた場合に、当該検索データ要素に一致する一致データ要素に誤りが発生していないことを1つの条件として、当該第1の部分データ要素列を、前記第1のパスからの当該列存在情報の連続出力回数と前記第1のパスから出力された前記列アドレス情報とに応じて決まる前記第2の部分データ要素列の位置及び長さの情報で置換する処理を行い、当該検索データ要素に一致する一致データ要素に誤りが発生していれば、前記第2のパスから出力された当該特定のデータ要素を用いて、当該第1の部分データ要素列を部分的に非圧縮とする処理を行う処理部と
を含む、装置。 - 前記処理部は、前記第1のパスが前記特定のデータ要素を前記検索データ要素として前記連想メモリに与えた場合に、前記1つの条件に加え、前記第1のパスからの前記列存在情報の連続出力回数が所定数を超えたことを更に1つの条件として、当該連続出力回数と前記第1のパスから出力された前記列アドレス情報とに応じて決まる前記第2の部分データ要素列の位置及び長さの情報で置換する処理を行う、請求項3の装置。
- 前記処理部は、前記第1のパスが前記特定のデータ要素を前記検索データ要素として前記連想メモリに与えた場合に、前記第1のパスからの前記列存在情報の連続出力回数が所定数を超えなかったならば、前記第2のパスから出力された当該特定のデータ要素を用いて、当該第1の部分データ要素列を部分的に非圧縮とする処理を行う、請求項3又は請求項4の装置。
- 前記第2のパスは、前記第1のパスから前記列存在情報と前記列アドレス情報とが出力されるのと同期して前記データ要素を出力するようなパイプライン構成を有する、請求項3乃至請求項5の何れかの装置。
- データ要素列の第1の部分データ要素列を、当該データ要素列の第2の部分データ要素列の位置及び長さの情報で置換することにより、当該データ要素列を圧縮する装置であって、
前記データ要素列の少なくとも一部を構成する複数のデータ要素の各データ要素と当該各データ要素に対応するパリティ要素とを、当該データ要素列における当該各データ要素の位置に応じたアドレスに記憶し、検索データ要素が与えられた場合に、当該検索データ要素に一致する一致データ要素を当該複数のデータ要素の1つとして記憶していれば、当該一致データ要素が記憶されているアドレスを出力する連想メモリと、
前記検索データ要素が前記連想メモリに与えられた場合に、それまでに与えられた検索データ要素の列に一致する一致データ要素の列が当該連想メモリに記憶されていれば、当該連想メモリから出力される前記アドレスに基づいて、当該一致データ要素の列が記憶されていることを示す列存在情報と、当該一致データ要素の列が記憶されているアドレスを示す列アドレス情報とを生成する生成回路と、
前記検索データ要素が前記連想メモリに与えられた場合に、当該検索データ要素に一致する一致データ要素が前記連想メモリに記憶されていれば、当該一致データ要素が記憶されているアドレスに記憶された前記パリティ要素の値が、当該検索データ要素から生成されるかどうかを判定する判定回路と、
入力されたデータ要素を前記検索データ要素として前記連想メモリに与え、前記生成回路により生成された前記列存在情報と前記列アドレス情報とを出力する第1のパスと、
入力されたデータ要素を前記検索データ要素として前記連想メモリに与えることなく出力する第2のパスと、
前記第1の部分データ要素列に含まれる特定のデータ要素の入力に応じて、前記第1のパスが当該特定のデータ要素を前記検索データ要素として前記連想メモリに与えた場合に、前記判定回路により前記パリティ要素の値が生成されると判定されたという条件、及び、前記第1のパスからの前記列存在情報の連続出力回数が所定数を超えたという条件の両方が満たされれば、当該第1の部分データ要素列を、当該連続出力回数と前記第1のパスから出力された前記列アドレス情報とに応じて決まる前記第2の部分データ要素列の位置及び長さの情報で置換する処理を行い、前記判定回路により前記パリティ要素の値が生成されないと判定されたという条件、及び、前記第1のパスからの前記列存在情報の連続出力回数が前記所定数を超えなかったという条件の少なくともいずれか一方が満たされれば、前記第2のパスから出力された当該特定のデータ要素を用いて、当該第1の部分データ要素列の当該特定のデータ要素の部分を非圧縮とする処理を行う処理部と
を含む、装置。 - データ要素列の第1の部分データ要素列を、当該データ要素列の第2の部分データ要素列の位置に基づいて処理する方法であって、
前記データ要素列の少なくとも一部を構成する複数のデータ要素の各データ要素を、当該データ要素列における当該各データ要素の位置に応じたアドレスに記憶し、検索データ要素が与えられた場合に、当該検索データ要素に一致する一致データ要素を当該複数のデータ要素の1つとして記憶していれば、当該一致データ要素が記憶されているアドレスを出力する連想メモリと、
入力されたデータ要素を前記検索データ要素として前記連想メモリに与え、当該連想メモリから出力された前記アドレスを出力する第1のパスと、
入力されたデータ要素を前記検索データ要素として前記連想メモリに与えることなく出力する第2のパスと
を含み、
前記第1の部分データ要素列に含まれる特定のデータ要素の入力に応じて、前記第1のパスが当該特定のデータ要素を前記検索データ要素として前記連想メモリに与えた場合に、当該検索データ要素に一致する一致データ要素に誤りが発生しているかどうかを判定するステップと、
前記一致データ要素に誤りが発生していないと判定されれば、前記第1のパスから出力された前記アドレスを用いて前記第1の部分データ要素列を処理し、前記一致データ要素に誤りが発生していると判定されれば、前記第2のパスから出力された当該特定のデータ要素を用いて前記第1の部分データ要素列を処理するステップと
を含む、方法。
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