WO2012075627A1 - 电平转换电路 - Google Patents

电平转换电路 Download PDF

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Publication number
WO2012075627A1
WO2012075627A1 PCT/CN2010/079553 CN2010079553W WO2012075627A1 WO 2012075627 A1 WO2012075627 A1 WO 2012075627A1 CN 2010079553 W CN2010079553 W CN 2010079553W WO 2012075627 A1 WO2012075627 A1 WO 2012075627A1
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WO
WIPO (PCT)
Prior art keywords
transistor
signal
module
source
drain
Prior art date
Application number
PCT/CN2010/079553
Other languages
English (en)
French (fr)
Inventor
覃正才
刘启付
刘楠
吴大军
周承捷
陆宁
徐鼎
Original Assignee
上海贝岭股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 上海贝岭股份有限公司 filed Critical 上海贝岭股份有限公司
Priority to US13/991,714 priority Critical patent/US8723585B2/en
Priority to CN201080066288.2A priority patent/CN102893320B/zh
Priority to PCT/CN2010/079553 priority patent/WO2012075627A1/zh
Publication of WO2012075627A1 publication Critical patent/WO2012075627A1/zh

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/017509—Interface arrangements
    • H03K19/017518—Interface arrangements using a combination of bipolar and field effect transistors [BIFET]
    • H03K19/017527—Interface arrangements using a combination of bipolar and field effect transistors [BIFET] with at least one differential stage
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit

Definitions

  • the present invention relates to voltage level conversion, and more particularly to a level conversion circuit for a row driving circuit in an LCD display panel.
  • driving circuits for large-sized TFT-LCDs are basically developed using a high voltage (HV) CMOS (Compensated Metal Oxide Semiconductor) process.
  • the row driver circuit includes a plurality of output channel circuits, wherein each of the output channels is composed of a low voltage logic combination circuit, a level conversion circuit, and a high voltage output circuit.
  • a level shifting circuit in a conventional row driver chip output channel is shown in FIG. As shown, VIN is the input drive signal and V 0UT is the output drive signal. V CC is the low potential supply voltage, and V GG /VEE is the high potential voltage / ground. MP 1 -MP4 and MN 1 -MN4 form a level shifting circuit, and MP5 and MN5 constitute an output driving circuit.
  • the threshold voltage of the high-voltage device in the output channel circuit is large and the transconductance is small, so the on-resistance is large, which limits the reduction of the chip area and the improvement of the operating efficiency of the chip.
  • the BCD process that integrates Bipolar (bipolar) devices, CMOS devices, and DMOS (dual-diffused metal oxide semiconductor) devices has the advantages of high integration, low power consumption, and small chip area. Especially important, the process The LDMOS (transverse double-diffused metal oxide semiconductor) device used has a large transconductance and a small on-resistance.
  • the high-voltage device in the BCD process has a small gate-to-source breakdown voltage compared to a conventional HV CMOS high voltage device. Therefore, when the BCD process is applied, such as the level shift circuit of the conventional structure in the above FIG. 1, the device damage will be caused, and the chip function will not be realized normally. Therefore, a new level shifting circuit structure is needed to effectively prevent the high voltage device in the BCD process from being damaged due to excessive gate voltage, and stably realize high and low level switching in the channel.
  • the level shifting circuit of the present invention includes: a first level converting module; a first signal input terminal for providing a first input signal to the first level converting module; and converting from the first level a module providing an output first signal output; a second level conversion module; a second signal input for providing a second input signal to the second level conversion module; providing an output from the second level conversion module a second signal output terminal; a driving module connected to the first signal output terminal and the second signal output terminal; and a driving output signal terminal outputted by the driving module; wherein the first level converting module comprises: a first transistor having a gate connected to the first signal output terminal, a source connected to the low voltage ground reference voltage source, a second transistor having a gate connected to the drain, and a source coupled to the high voltage reference voltage source a third transistor having a gate connected to a gate of the second transistor, a source coupled to the high voltage reference voltage source, and a drain coupled to a drain of the first transistor The first a signal output terminal is connected; a fourth
  • the driving module includes a first driving transistor and a second driving transistor, wherein: a gate of the first driving transistor is connected to the first signal output end, and a source is connected to the high voltage reference voltage source Connecting, the drain is connected to the output end of the driving signal; the gate of the second driving transistor is connected to the second signal output end, the source is connected to the high voltage ground reference voltage source, and the drain is connected The drains of the first driving transistors are connected.
  • the first clamping module and the second clamping module are composed of one or more transistors connected in series.
  • the first current limiting module and the second current limiting module are composed of resistors.
  • the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are all LDMOS transistors.
  • the one or more transistors are LDMOS transistors.
  • the level conversion circuit of the invention can be adapted to the requirements of the BCD process, and prevents the high voltage device from being damaged due to the high gate voltage, thereby effectively realizing the conversion of the high and low levels in the channel.
  • FIG. 2 is a circuit block diagram of an output channel including a level shifting circuit of the present invention
  • Figure 4 is a circuit diagram of the first clamp module of Figure 3
  • Figure 5 is a circuit diagram of the second clamp module of Figure 3
  • Figure 6 is a circuit diagram of one embodiment of the level shifting circuit of the present invention
  • BEST MODE FOR CARRYING OUT THE INVENTION The composition and working principle of the level conversion circuit of the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.
  • 2 is a schematic diagram of a circuit block including an output channel of the level shifting circuit of the present invention.
  • an output channel circuit includes a low voltage circuit 200 and a high voltage circuit portion (i.e., the level shift circuit portion of the present invention) 100.
  • the low voltage input signal input from the low voltage circuit portion 100 is generated by the logic control module to drive the high voltage circuit.
  • the drive signal, and the high-level portion of the level shift circuit realizes the level conversion from low voltage to high voltage and the function of driving a high voltage load. Specifically, after the input signal Din passes through the register module 210, two signals Din_A, Din_B are generated. After the two signals pass through the low-voltage logic control module 220, the level conversion circuit portion 100 for the high voltage can be generated.
  • the input signal passes through the level conversion module 10 of the level conversion circuit (including the first level conversion module 110 and the second level conversion module 120, see FIG. 3 in detail)
  • the high voltage signals netP, netN are generated and driven.
  • Module 130 generates a high voltage signal Vout that is output to subsequent display components.
  • Din is a signal output from the shift register of the (N-1)th stage, which generates shift register output signals Din_A and Din of the Nth and (N+1)th stages.
  • the role of Din-A in the level shifting circuit of the present invention is to switch the level of the control circuit from low to high, so that the output Vout is set to a high level, and the role of Din-B in the circuit of the present invention is in the circuit.
  • the shift pulse is pulled low by a high level and then Vout is pulled low.
  • Peon and Pconb are generated by Din-A through combinational logic (see FIG. 7 for timing relationship), and the above functions of Din-A are realized by controlling the operation of the level-shifting circuit of the present invention by Peon and Pconb; by Din-B Neon and Nconb are generated by combinational logic, and Din-B functions by controlling the operation of the level shifting circuit of the present invention by Neon and Nconb.
  • the level shifting circuit 100 includes: a first level converting module 110; a first signal input terminal Peon for providing a first input signal to the first level converting module 110; converting from a first level
  • the module 120 provides an output first signal output terminal netP; a second level conversion module 120; a second signal input terminal Neon for providing a second input signal to the second level conversion module 120; and a second level conversion module 120 provides an output second signal output terminal netN; a drive module 120 connected to the first signal output terminal netP and the second signal output terminal netN; and a drive output signal terminal Vout outputted by the drive module 120.
  • the first level conversion module 110 includes a first transistor M1 having a gate connected to the first signal output terminal Peon, a source connected to the low voltage ground reference voltage source GND, and a second transistor M2 having a gate Connected to the drain, the source is connected to the high voltage reference voltage source VGG; the third transistor M3 has a gate connected to the gate of the second transistor M2, the source is connected to the high voltage reference voltage source VGG, and the drain is connected The drain of the first transistor M1 is connected to the first signal output terminal netP; the fourth transistor M4 has a gate connected to the second complementary signal input terminal Nconb for inputting the second complementary signal, the drain and the second transistor The drain of M6 is connected, wherein the second complementary signal is complementary to the second input signal (see FIG.
  • the first clamping module 111 has one end connected to the high voltage reference voltage source VGG and the other end connected to the first transistor.
  • the drain of M1 is connected;
  • the first current limiting module 112 has one end connected to the source of the fourth transistor M4 and the other end connected to the low-voltage ground reference voltage source GND.
  • the second level converting module 120 includes: a fifth transistor M5 having a gate connected to the second signal output terminal Neon, a source connected to the low voltage reference voltage source VCC, and a sixth transistor M6 having a gate Connected to the drain, the source is connected to the high voltage ground reference voltage source VEE; the seventh transistor M7 has a gate connected to the gate of the sixth transistor M6, and the source is connected to the high voltage ground reference voltage source VEE, and the drain a drain and a drain of the fifth transistor M5 And the second signal output terminal ne tN is connected; the eighth transistor M8 has a gate connected to the first complementary signal input terminal Pconb for inputting the first complementary signal, and a drain connected to the drain of the sixth transistor M6 The first complementary signal is complementary to the first input signal (see FIG.
  • the second clamping module 121 has one end connected to the high voltage ground reference voltage source VEE and the other end connected to the drain of the fifth transistor M5.
  • the second current limiting module 122 has one end connected to the source of the eighth transistor M8 and the other end connected to the low voltage reference voltage source VCC.
  • the first to eighth transistors M1-M8 are all LDMMOS transistors.
  • the high voltage reference voltage source VGG and the high voltage ground reference voltage source VEE are the 40V power supply/ground of the high voltage portion; the low voltage reference voltage source VCC and the low voltage ground reference voltage source GND are the 1.8V power supply/ground of the low voltage portion.
  • the driving module 130 includes a first driving transistor N1 and a second driving transistor N2, both of which are LDMOS transistors, wherein the gate of the first driving transistor N1 is connected to the first signal output terminal netP, the source and the high voltage The reference voltage source VGG is connected, the drain is connected to the driving signal output terminal Vout; the gate of the second driving transistor N2 is connected to the second signal output terminal netN, and the source is connected to the high voltage ground reference voltage source VEE, and the drain Connected to the drain of the first driving transistor N 1 .
  • the first clamping module 111 and the second clamping module 121 are composed of one or more transistors P1-PN, Q1-QN connected in series.
  • P1-PN, Q1-QN are LDMOS transistor devices in which the drain and source of each series connected transistor are sequentially connected, and the gate of each transistor is connected to its drain.
  • the number of transistors in the first clamp module 111 and the second clamp module 121 varies depending on the clamp voltage.
  • the transistors in the two clamp modules are preferably composed of LDMOS transistors, but the clamp function can also be realized by using a semiconductor device such as a triode or a diode.
  • the first current limiting module 112 and the second current limiting module 122 are composed of resistors. Of course, other current limiting devices or circuits may be used.
  • the two current limiting modules may utilize transistor devices to implement their current limiting functions. As shown in FIG.
  • the first clamping module 111 includes three transistors PI, P2, and P3 connected in series
  • the second clamping module 121 includes four transistors Q1, Q2, Q3, and Q4 connected in series.
  • the drain of the transistor PI is connected to the drain of the first transistor M1
  • the source of the transistor P3 is connected to the high voltage reference voltage source VGG
  • the source of Q1 is connected to the high voltage ground reference voltage source VEE
  • the drain of the Q5 Connected to the drain of the fifth transistor M5.
  • FIG. 6 depicts the signal timing diagrams for each input or output Din, Din-A, Din-B, Peon, Pconb, Neon, Nconb, netP, netN, and Vout.
  • the functions of Ml-M3, P1-P3, and M5-M7, Q1 ⁇ Q4 are to solve the limitation that the gates of the first driving transistor and the second driving transistor N1, N2 in the driving module 130 cannot withstand high voltage, that is, guarantee :
  • VGG - V netp ⁇ V T , V netN - VEE ⁇ V T (Equation 1) where is the maximum allowable gate-to-source voltage of the high-voltage device, V netP is the voltage at the first signal output terminal netP, and V netN is the second The voltage at the signal output, netN.
  • V netP point voltage V netP the signal amplitude of the gate of the first transistor M1 is GND-VCC, and when the first input signal voltage Pcon of the first signal input terminal Peon is VCC, the first transistor M1 is turned on. Generating a saturation current I M1 , three transistors P1 in the first clamping module 111, P2 and P3 are equivalent to three resistors connected in series. Therefore, the voltage at the first signal output terminal netP is:
  • V netP V GG - I m (R onl + R on2 + R on3 ) (Equation 2) where R 0N1 , R 0N2 R ON3 are the on-resistances of PI, P2 and P3, respectively.
  • R 0N1 , R 0N2 R ON3 are the on-resistances of PI, P2 and P3, respectively.
  • transistors M2 ⁇ M4 can avoid this from happening. Specifically, when the first transistor M1 is turned off, the input signal Nconb of the second complementary signal input terminal controls the fourth transistor M4 to be turned on, and the generated saturation current I M4 flows through the second transistor M2 to provide a gate for the third transistor M3.
  • the turn-on voltage at which time the third transistor M3 is in the line region, causes the voltage at netP to be very close to VGG, thus completely turning off the first drive transistor N1.
  • the introduction of M5, M6, M8 and Q1 ⁇ Q4 can also satisfy the requirements of equation (1).
  • the netP is stepped down from the high voltage high level VGG via the first clamping module 111, and the netN is lowered to the high voltage low level VEE.
  • a driving transistor N1 is turned on and the second driving transistor N2 is completely turned off, Vout is outputted as a high voltage VGG, and the channel charges the load; on the other hand, after the fourth transistor M4 and the fifth transistor M5 are simultaneously turned on, the netP becomes a high voltage
  • the level VGG, netN is boosted from the high voltage level VEE via the second clamping module 121, at which time the first driving transistor N1 is completely turned off and the second driving transistor N2 is turned on, and the Vout output is the high voltage ground level VEE, the channel pair The load is discharged.
  • the level conversion circuit of the present invention can be adapted to the requirements of the BCD process, preventing the high voltage device from being damaged due to the high gate voltage, and effectively realizing the conversion of the high and low levels in the channel.

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  • Logic Circuits (AREA)

Description

电平转换电路 技术领域 本发明涉及电压电平转换， 更具体地， 是一种用于 LCD显示屏中 行驱动电路的电平转换电路。 背景技术 目前， 用于大尺寸 TFT-LCD (薄膜晶体管液晶显示器） 的驱动电 路基本上都是采用高压 （HV ) 的 CMOS (补偿型金属氧化物半导体） 工艺进行开发。 行驱动电路包括多个输出通道电路， 其中每个输出通 道由低压逻辑组合电路、 电平转换电路和高压输出电路组成。 采用 HVCMOS工艺的优点是行驱动电路中输出通道的高压输出电路筒单， 电平转换易于实现。 图 1中显示了一种传统的行驱动芯片输出通道中的电平转换电路。 如图所示， VIN为输入驱动信号， V0UT为输出驱动信号。 VCC为低电位 电源电压， VGG/VEE为高电位电压 /地。 MP 1 -MP4以及 MN 1 -MN4组成 电平转换电路， MP5和 MN5组成输出驱动电路。 采用 HV MOS工艺时，输出通道电路中的高压器件的阈值电压大、 跨导小， 因此导通电阻较大， 这限制了芯片面积的降低以及芯片运行 效率的提高。 与此对照的是， 集成了 Bipolar (双极型） 器件、 CMOS 器件、 以及 DMOS (双扩散金属氧化物半导体）器件的 BCD工艺则具 有集成度高、 功耗低、 芯片面积小等优点。 尤其重要的是， 该工艺所 使用的 LDMOS (横向双扩散金属氧化物半导体）器件跨导大、 并且导 通电阻小。 与传统的 HV CMOS工艺的高压器件相比， BCD工艺中的高压器 件的栅源击穿电压小。 因此， 在应用 BCD工艺时， 如采用上述图 1中 的传统结构的电平转换电路， 将会造成器件损坏， 并进而导致芯片功 能不能正常实现。 因此， 需要一种新的电平转换电路结构， 以有效避免 BCD工艺中 的高压器件因栅极电压过高而导致器件损坏的现象发生， 同时稳定地 实现通道中的高低电平转换。 发明内容 本发明的目的， 在于提供一种基于 BCD工艺的电平转换电路， 以 适应于 BCD工艺中器件特定属性的要求。 为实现该目的， 本发明的电平转换电路包括： 第一电平转换模块； 用于为该第一电平转换模块提供第一输入信号的第一信号输入端； 从 该第一电平转换模块提供输出的第一信号输出端； 第二电平转换模块； 用于为该第二电平转换模块提供第二输入信号的第二信号输入端； 从 该第二电平转换模块提供输出的第二信号输出端； 与所述第一信号输 出端和第二信号输出端相连接的驱动模块； 以及由该驱动模块输出的 驱动输出信号端； 其中， 所述第一电平转换模块包括： 第一晶体管， 其栅极与所述第一信号输出端相连接， 源极与低压地参考电压源相连 接； 第二晶体管， 其栅极与漏极相连接， 源极与高压参考电压源相连 接； 第三晶体管， 其栅极与所述第二晶体管的栅极相连接， 源极与所 述高压参考电压源相连接， 漏极与所述第一晶体管的漏极以及所述第 一信号输出端相连接； 第四晶体管， 其栅极与用于输入第二互补信号 的第二互补信号输入端相连接， 漏极与所述第二晶体管的漏极相连接， 其中所述第二互补信号与所述第二输入信号互补； 第一箝位模块， 其 一端与高压参考电压源相连接， 另一端与所述第一晶体管的漏极相连 接； 第一限流模块， 其一端与所述第四晶体管的源极相连接， 另一端 与所述低压地参考电压源相连接； 所述第二电平转换模块包括： 第五 晶体管， 其栅极与所述第二信号输出端相连接， 源极与低压参考电压 源相连接； 第六晶体管， 其栅极与漏极相连接， 源极与高压地参考电 压源相连接； 第七晶体管， 其栅极与所述第六晶体管的栅极相连接， 源极与所述高压地参考电压源相连接， 漏极与所述第五晶体管的漏极 以及第二信号输出端相连接； 第八晶体管， 其栅极与用于输入第一互 补信号的第一互补信号输入端相连接， 漏极与所述第六晶体管的漏极 相连接， 其中所述第一互补信号与所述第一输入信号互补； 第二箝位 模块， 其一端与高压地参考电压源相连接， 另一端与所述第五晶体管 的漏极相连接； 第二限流模块， 其一端与所述第八晶体管的源极相连 接， 另一端与所述低压参考电压源相连接。 优选地， 所述驱动模块包括第一驱动晶体管以及第二驱动晶体管， 其中： 所述第一驱动晶体管的栅极与所述第一信号输出端相连接， 源 极与所述高压参考电压源相连接， 漏极与所述驱动信号输出端相连接； 所述第二驱动晶体管的栅极与所述第二信号输出端相连接， 源极与所 述高压地参考电压源相连接， 漏极与所述第一驱动晶体管的漏极相连 接。 优选地， 所述第一箝位模块和第二箝位模块由一个或多个晶体管 串接组成。 优选地， 所述第一限流模块和第二限流模块由电阻组成。 优选地， 所述第一晶体管、 第二晶体管、 第三晶体管、 第四晶体 管、 第五晶体管、 第六晶体管、 第七晶体管和第八晶体管均为 LDMOS 晶体管。 优选地， 所述一个或多个晶体管均为 LDMOS晶体管。 本发明的电平转换电路， 可适应于 BCD工艺的要求， 防止高压器 件因栅极电压过高而导致器件损坏， 有效地实现了通道中高低电平的 转换。 附图说明 图 1为现有的一种电平转换电路的电路图； 图 2为包括有本发明的电平转换电路的一个输出通道的电路模块 图； 图 3为本发明的电平转换电路的电路图； 图 4是图 3中第一箝位模块的电路图； 图 5是图 3中第二箝位模块的电路图； 图 6是本发明的电平转换电路一个实施方式的电路图； 图 7是本发明的电平转换电路中各相关信号的时序图。 具体实施方式 以下结合附图和具体实施方式， 对本发明的电平转换电路的组成 和工作原理进行详细说明。 如图 2所示， 是包括有本发明的电平转换电路的一个输出通道的 电路模块示意图。 如图所示， 一个输出通道电路中， 包含低压电路 200 和高压电路部分（即本发明的电平转换电路部分） 100, 低压电路部分 100 输入的低压输入信号通过逻辑控制模块产生驱动高压电路的驱动 信号， 而高压部分的电平转换电路实现从低压到高压的电平转换以及 驱动高压负载的功能。 具体地， 输入信号 Din经过寄存器模块 210后， 产生两个信号 Din— A、 Din— B, 该两个信号经过低压逻辑控制模块 220 后， 可产生用于高压的电平转换电路部分 100的第一输入信号 Peon和 第二输入信号 Neon, 以及与第一输入信号 Peon反相互补的第一互补 信号 Pconb、和与第二输入信号 Neon反相互补的第二互补信号 Nconb。 上述输入信号经过电平转换电路的电平转换模块 10(包括第一电平转 换模块 110, 以及第二电平转换模块 120, 具体参见图 3)后， 产生高 压信号 netP、 netN, 并通过驱动模块 130, 产生输出给后续显示器组件 的高压信号 Vout。 在上述各信号的关系方面， Din是第 （N-1 )级的移位寄存器输出 的信号， 它产生第 N级和第 （N+1 )级的移位寄存器输出信号 Din— A 和 Din— B。 Din— A在本发明电平转换电路中的作用是控制电路的电平 由低到高的转换，使输出 Vout置为高电平， Din— B在本发明电路中的作 用是在该电路的移位脉冲由高电平置为低电平后将 Vout拉低。 另外， 由 Din— A通过组合逻辑产生 Peon和 Pconb (时序关系参见图 7 ), 上述 Din— A的作用是通过 Peon和 Pconb来控制本发明电平转换电路的工作 而实现的； 由 Din— B通过组合逻辑产生 Neon和 Nconb, Din— B的作用 是通过 Neon和 Nconb来控制本发明电平转换电路的工作而实现的。这 将在下述对本发明电平转换电路的详细描述中， 进行更具体说明。 如图 3 所示， 是本发明的上述电平转换电路的具体的电路图。 如 图所示， 该电平转换电路 100包括： 第一电平转换模块 110; 用于为第 一电平转换模块 110提供第一输入信号的第一信号输入端 Peon; 从第 一电平转换模块 120提供输出的第一信号输出端 netP; 第二电平转换 模块 120;用于为第二电平转换模块 120提供第二输入信号的第二信号 输入端 Neon; 从第二电平转换模块 120提供输出的第二信号输出端 netN;与第一信号输出端 netP和第二信号输出端 netN相连接的驱动模 块 120; 以及由驱动模块 120输出的驱动输出信号端 Vout。 更具体地， 第一电平转换模块 110包括第一晶体管 Ml , 其栅极与 第一信号输出端 Peon相连接，源极与低压地参考电压源 GND相连接； 第二晶体管 M2, 其栅极与漏极相连接， 源极与高压参考电压源 VGG 相连接； 第三晶体管 M3 , 其栅极与第二晶体管 M2的栅极相连接， 源 极与高压参考电压源 VGG相连接， 漏极与第一晶体管 Ml的漏极以及 第一信号输出端 netP相连接； 第四晶体管 M4, 其栅极与用于输入第 二互补信号的第二互补信号输入端 Nconb相连接， 漏极与第二晶体管 M6的漏极相连接， 其中第二互补信号与第二输入信号反相互补（参见 图 7 ); 第一箝位模块 111 , 其一端与高压参考电压源 VGG相连接， 另 一端与第一晶体管 Ml的漏极相连接； 第一限流模块 112 , 其一端与第 四晶体管 M4的源极相连接，另一端与低压地参考电压源 GND相连接。 另一方面， 第二电平转换模块 120包括： 第五晶体管 M5 , 其栅极 与第二信号输出端 Neon相连接，源极与低压参考电压源 VCC相连接； 第六晶体管 M6,其栅极与漏极相连接， 源极与高压地参考电压源 VEE 相连接； 第七晶体管 M7, 其栅极与第六晶体管 M6的栅极相连接， 源 极与高压地参考电压源 VEE相连接， 漏极与第五晶体管 M5的漏极以 及第二信号输出端 netN相连接； 第八晶体管 M8 , 其栅极与用于输入 第一互补信号的第一互补信号输入端 Pconb相连接， 漏极与第六晶体 管 M6的漏极相连接，其中第一互补信号与第一输入信号反相互补（参 见图 7 );第二箝位模块 121 ,其一端与高压地参考电压源 VEE相连接， 另一端与第五晶体管 M5的漏极相连接； 第二限流模块 122, 其一端与 第八晶体管 M8的源极相连接，另一端与低压参考电压源 VCC相连接。 其中，上述第一晶体管至第八晶体管 M1-M8均为 LDM0S晶体管。 高压参考电压源 VGG和高压地参考电压源 VEE为高压部分的 40V电 源 /地； 低压参考电压源 VCC和低压地参考电压源 GND为低压部分的 1.8V电源 /地。 进一步地，驱动模块 130包括第一驱动晶体管 N1以及第二驱动晶 体管 N2, 两个晶体管均为 LDMOS晶体管， 其中第一驱动晶体管 N1 的栅极与第一信号输出端 netP相连接， 源极与高压参考电压源 VGG 相连接， 漏极与驱动信号输出端 Vout相连接； 第二驱动晶体管 N2的 栅极与第二信号输出端 netN相连接， 源极与高压地参考电压源 VEE 相连接， 漏极与第一驱动晶体管 N 1的漏极相连接。 如图 4、 5所示， 第一箝位模块 111和第二箝位模块 121由一个或 多个晶体管 P1-PN、 Q1-QN 串接组成。 P1-PN、 Q1-QN均为 LDMOS 晶体管器件， 其中各串接的晶体管漏极和源极顺次相连， 并且各晶体 管的栅极与其漏极相连。 第一箝位模块 111和第二箝位模块 121 内晶 体管的个数根据箝位电压的不同而变化。 另外， 两个箝位模块内的晶 体管优选地由 LDMOS管组成， 但也可以利用三极管或二极管等半导 体器件来实现箝位功能。 第一限流模块 112和第二限流模块 122 由电阻器组成， 当然也可 采用其它的限流器件或电路， 例如， 两个限流模块可利用晶体管器件 来实现其限流功能。 如图 6所示， 是更详细的呈现有本发明的电平转换电路的第一箝 位模块 111、 第二箝位模块 121、 第一限流模块 112以及第二限流模块 122的电路图。 该实施方式中， 第一箝位模块 111包括三个依次串接的 晶体管 PI、 P2、 P3 , 第二箝位模块 121 包括四个依次串接的晶体管 Ql、 Q2、 Q3、 Q4。 其中晶体管 PI的漏极与第一晶体管 Ml的漏极相 连接， 晶体管 P3的源极与高压参考电压源 VGG相连接， Q 1的源极与 高压地参考电压源 VEE相连接， Q5的漏极与第五晶体管 M5的漏极相 连接。 其它部分的电路结构与上述图 3中相同。 以下结合图 6、 图 7 , 对本发明的电平转换电路的工作原理进行详 细描述。其中图 7中描绘了各输入端或输出端 Din, Din— A, Din— B, Peon, Pconb, Neon, Nconb, netP, netN以及 Vout处的信号时序图。 图 6中， Ml-M3、 P1-P3以及 M5-M7 , Q1~Q4的作用是解决驱动 模块 130中第一驱动晶体管和第二驱动晶体管 Nl、 N2的栅极不能承 受高压的限制， 即保证：
VGG - Vnetp < VT， VnetN - VEE < VT (等式 1 ) 其中 是高压器件最大可以承受的栅源电压， VnetP是第一信号输出 端 netP处的电压， VnetN是第二信号输出端 netN处的电压。 以 netP点 电压 VnetP为例，第一晶体管 Ml的栅极接收的信号幅度为 GND-VCC, 当第一信号输入端 Peon的第一输入信号电压 Pcon=VCC时，第一晶体 管 Ml导通，产生饱和电流 IM1 ,第一箝位模块 111中的三个晶体管 Pl、 P2、 P3相当于三个电阻串联， 因此， 第一信号输出端 netP处电压为：
VnetP = VGG - Im (Ronl + Ron2 + Ron3 ) (等式 2 ) 其中， R0N1 , R0N2 RON3分别是 PI , P2和 P3的导通电阻。 通过 调整 Ml , PI , P2 , P3的宽长比， 可使 netP处电压以满足等式 1的要 求。 当第一信号输入端 Peon的第一输入信号电压 VPc。n=G )时，第一 晶体管 Ml关断， 第一信号输出端 netP被充电至较高电压从而关断第 一驱动晶体管 Nl。 但实际上， 此时尽管第一晶体管 Ml的栅源电压相 等， 但 Ml 中仍存在微弱的漏电流， 这部分漏电流在 P1~P3上的压降 很容易使第一驱动晶体管 N1处于亚阈值区从而不能完全关断，这大大 增加了输出级的瞬态响应时间。晶体管 M2~M4的引入可以避免这种情 况的发生。 具体地， 当第一晶体管 Ml 关断时， 第二互补信号输入端 的输入信号 Nconb控制第四晶体管 M4导通，产生的饱和电流 IM4流过 第二晶体管 M2 , 为第三晶体管 M3提供栅极导通电压， 此时第三晶体 管 M3处于线形区， 从而使 netP处电压非常接近 VGG, 因此完全关断 第一驱动晶体管 Nl。 同理， 对于 netN处， M5 , M6、 M8以及 Q1~Q4 的引入也能使其满足等式 (1)的要求。 时序方面， 结合图 7 , 第一晶体 管 Ml和第八晶体管 M8同时导通后， netP从高压高电平 VGG经第一 箝位模块 111降压， netN降低到高压低电平 VEE, 此时第一驱动晶体 管 N1导通而第二驱动晶体管 N2完全截止， Vout输出为高压 VGG, 通道对负载进行充电； 另一方面， 第四晶体管 M4 和第五晶体管 M5 同时导通后， netP变为高压高电平 VGG, netN从高压氏电平 VEE经 第二箝位模块 121升压，此时第一驱动晶体管 N1完全截止而第二驱动 晶体管 N2导通， Vout输出为高压地电平 VEE, 通道对负载进行放电。 综上所述， 本发明的电平转换电路， 可适应于 BCD工艺的要求， 防止高压器件因栅极电压过高而导致器件损坏， 有效地实现了通道中 高低电平的转换。

Claims

权利要求
1、 一种电平转换电路， 其特征在于， 该电平转换电路包括： 第一电平转换模块； 用于为该第一电平转换模块提供第一输入信号的第一信号输入 端； 从该第一电平转换模块提供输出的第一信号输出端； 第二电平转换模块； 用于为该第二电平转换模块提供第二输入信号的第二信号输入 端； 从该第二电平转换模块提供输出的第二信号输出端； 与所述第一信号输出端和第二信号输出端相连接的驱动模块； 以 及由该驱动模块输出的驱动输出信号端； 其中， 所述第一电平转换模块包括： 第一晶体管， 其栅极与所述第一信号输出端相连接， 源极与低压 地参考电压源相连接； 第二晶体管， 其栅极与漏极相连接， 源极与高压参考电压源相连 接； 第三晶体管， 其栅极与所述第二晶体管的栅极相连接， 源极与所 述高压参考电压源相连接， 漏极与所述第一晶体管的漏极以及所述第 一信号输出端相连接； 第四晶体管， 其栅极与用于输入第二互补信号的第二互补信号输 入端相连接， 漏极与所述第二晶体管的漏极相连接， 其中所述第二互 补信号与所述第二输入信号互补； 第一箝位模块， 其一端与高压参考电压源相连接， 另一端与所述 第一晶体管的漏极相连接； 第一限流模块， 其一端与所述第四晶体管的源极相连接， 另一端 与所述低压地参考电压源相连接； 所述第二电平转换模块包括： 第五晶体管， 其栅极与所述第二信号输出端相连接， 源极与低压 参考电压源相连接； 第六晶体管， 其栅极与漏极相连接， 源极与高压地参考电压源相 连接； 第七晶体管， 其栅极与所述第六晶体管的栅极相连接， 源极与所 述高压地参考电压源相连接， 漏极与所述第五晶体管的漏极以及第二 信号输出端相连接； 第八晶体管， 其栅极与用于输入第一互补信号的第一互补信号输 入端相连接， 漏极与所述第六晶体管的漏极相连接， 其中所述第一互 补信号与所述第一输入信号互补； 第二箝位模块， 其一端与高压地参考电压源相连接， 另一端与所 述第五晶体管的漏极相连接； 第二限流模块， 其一端与所述第八晶体管的源极相连接， 另一端 与所述低压参考电压源相连接。
2、 根据权利要求 1所述的电平转换电路， 其特征在于， 所述驱动 模块包括第一驱动晶体管以及第二驱动晶体管， 其中： 所述第一驱动晶体管的栅极与所述第一信号输出端相连接， 源极 与所述高压参考电压源相连接， 漏极与所述驱动信号输出端相连接； 所述第二驱动晶体管的栅极与所述第二信号输出端相连接， 源极 与所述高压地参考电压源相连接， 漏极与所述第一驱动晶体管的漏极 相连接。
3、 根据权利要求 1或 2所述的电平转换电路， 其特征在于， 所述 第一箝位模块和第二箝位模块由一个或多个晶体管串接组成。
4、 根据权利要求 1或 2所述的电平转换电路， 其特征在于， 所述 第一限流模块和第二限流模块由电阻组成。
5、 根据权利要求 1或 2所述的电平转换电路， 其特征在于， 所述 第一晶体管、 第二晶体管、 第三晶体管、 第四晶体管、 第五晶体管、 第六晶体管、 第七晶体管和第八晶体管均为 LDMOS晶体管。
6、 根据权利要求 3所述的电平转换电路， 其特征在于， 所述一个 或多个晶体管均为 LDMOS晶体管。
PCT/CN2010/079553 2010-12-08 2010-12-08 电平转换电路 WO2012075627A1 (zh)

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