WO2012072062A2 - Procédé de fabrication d'un module solaire et module solaire - Google Patents

Procédé de fabrication d'un module solaire et module solaire Download PDF

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Publication number
WO2012072062A2
WO2012072062A2 PCT/DE2011/001974 DE2011001974W WO2012072062A2 WO 2012072062 A2 WO2012072062 A2 WO 2012072062A2 DE 2011001974 W DE2011001974 W DE 2011001974W WO 2012072062 A2 WO2012072062 A2 WO 2012072062A2
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WO
WIPO (PCT)
Prior art keywords
contact layer
electrical contact
trenches
semiconductor layers
layer
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PCT/DE2011/001974
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German (de)
English (en)
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WO2012072062A3 (fr
Inventor
Eerke Bunte
Brigitte Zwaygardt
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Forschungszentrum Jülich GmbH
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Priority to EP11815752.8A priority Critical patent/EP2647061A2/fr
Publication of WO2012072062A2 publication Critical patent/WO2012072062A2/fr
Publication of WO2012072062A3 publication Critical patent/WO2012072062A3/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
    • H01L31/075—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PIN type
    • H01L31/076—Multiple junction or tandem solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/042—PV modules or arrays of single PV cells
    • H01L31/0445—PV modules or arrays of single PV cells including thin film solar cells, e.g. single thin film a-Si, CIS or CdTe solar cells
    • H01L31/046—PV modules composed of a plurality of thin film solar cells deposited on the same substrate
    • H01L31/0463—PV modules composed of a plurality of thin film solar cells deposited on the same substrate characterised by special patterning methods to connect the PV cells in a module, e.g. laser cutting of the conductive or active layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/042—PV modules or arrays of single PV cells
    • H01L31/0445—PV modules or arrays of single PV cells including thin film solar cells, e.g. single thin film a-Si, CIS or CdTe solar cells
    • H01L31/046—PV modules composed of a plurality of thin film solar cells deposited on the same substrate
    • H01L31/0465—PV modules composed of a plurality of thin film solar cells deposited on the same substrate comprising particular structures for the electrical interconnection of adjacent PV cells in the module
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/548—Amorphous silicon PV cells

Definitions

  • the invention relates to a method for producing a solar module and a solar module.
  • FIG. 1 A known method for the production and simultaneous series connection of strip-shaped photovoltaic elements of a solar module is shown roughly schematically in FIG. 1 and in cross-section.
  • a first electrical contact layer for. B. a transparent conductive layer 2, z. B. ZnO or Sn0 2 , applied to a transparent substrate 1 as a carrier material (see Figure lb).
  • a transparent substrate 1 As a carrier material (see Figure lb).
  • a substrate z. As glass or foil used.
  • a typical process temperature for applying a ZnO layer by sputtering is 300 ° C.
  • first trenches 5 arranged parallel to one another are produced over the length of the module (FIG. 1c, FIG. 3).
  • the term "over the length of the module” is used, meaning a structuring that extends in the depth of the leaf level of the figures, forming the lines characteristic of solar modules, the lines being visible on top of the finished solar module.
  • a typical process temperature for the deposition of silicon layers by PECVD method is 100-250 ° C.
  • the P2 lines are again formed by ablation.
  • the second trenches 6 are produced, in FIG. 1 always to the right of the first trenches.
  • a second electrical contact layer 4 is applied as a back contact on the semiconductor layers 3, z. B. a ZnO / Ag contact, see Fig. L f.
  • the second trenches 6 are filled.
  • a typical process temperature for applying a ZnO / Ag back contact by sputtering is the room temperature.
  • the P3 line is again produced with a laser, see Fig. Lg.
  • third trenches 7 are formed parallel and in the image always to the right of the first and second trenches.
  • the same number of trenches 5, 6 and 7 are formed. This completes the series connection of cell A with cell B and cell B with cell C and so on.
  • the material ZnO is etchable in acid or in caustic. The etching takes place before the arrangement of the semiconductor layers 3.
  • the surface of the ZnO 2 with a wet-chemical etching process, for.
  • roughened and craters are formed. The roughening of the ZnO layer is important to ensure better light coupling and light scattering of the trapped light back into the semiconductor layers.
  • a general method for producing a planar solar module provides, on the
  • first electrical contact layer To dispense with the formation of first, second and third trenches. Then, the first electrical contact layer, then the semiconductor layers and then the second electrical contact layer are successively arranged on the substrate over the entire area one after the other. Contacts to the first electrical contact layer and to the second electrical contact layer are finally formed.
  • the first electrical contact layer is also referred to as the first electrode, and the second electrical contact layer as the second electrode.
  • the solar modules according to the prior art have a low efficiency.
  • the described method for producing and simultaneous series connection of the strip-shaped elements also takes too long, or is too complex to meet efficiency and output as required by industry.
  • the object of the invention is to provide a rapid process for the production of solar modules with higher efficiency. Another object of the invention is to provide a corresponding solar module with high efficiency. The object is achieved by a method according to claim 1 and by the module according to the independent claim. Advantageous embodiments emerge from the respective back claims.
  • the method for producing the solar module provides the following steps: a first contact layer is arranged over the entire surface of a substrate, and the active semiconductor layers are arranged over the entire surface of the first electrical contact layer.
  • a first contact layer is arranged over the entire surface of a substrate, and the active semiconductor layers are arranged over the entire surface of the first electrical contact layer.
  • at least four layers are sequentially deposited without the deposition of layers being interrupted as such. All layers are preferably arranged over the entire surface in succession.
  • An elaborate mask technology for strip-like structuring is advantageously dispensed with.
  • glass plastic film or a metal with an insulating layer is considered as a substrate.
  • the material of the first electrical contact layer is etchable. Etchable in the sense of the invention means that the material of the first electrical contact layer should also be laterally etchable, that is to say laterally under the semiconductor layers. In addition, the material has good conductivity.
  • ZnO Al
  • ZnO B
  • ITO indium tin oxide
  • Ti0 2 and alloys such as Ti0 2 and alloys such.
  • B ZnMgO, in question.
  • Sn0 2 or metals can be used.
  • Possible coating methods for the first contact layer are the methods known in the art, such. Sputtering, vapor deposition and PECVD processes.
  • Possible semiconductor layer systems are amorphous, microcrystalline, polycrystalline silicon, silicon germanium, silicon carbon, Si0 2 , Si 3 N 4 , SiO x, SiON, CdTe and CIGS. It is also possible to arrange pin diodes made of a-Si or ⁇ -Si or tandem structures of a-Si / a-Si or also a-SiVc-Si and the respective alloys of silicon with germanium or carbon one above the other.
  • a second electrical contact layer is then arranged over the entire surface.
  • Possible coating methods for the second contact layer are sputtering, vapor deposition and PEC VD methods.
  • the second electrical contact layer advantageously consists of a metal layer or a combination of a transparent conductive layer with a metal layer. Also very thin dielectric layers can be used.
  • Materials are: SiO x) ZnO: Al, ZnO: B, indium tin oxide (ITO), SnO 2 , TiO 2 , ZnMgO, Ag, Al, Cr, Ni, and so on.
  • ITO indium tin oxide
  • the method is characterized in that after the arrangement of the semiconductor layers and before the arrangement of the second contact layer, a wet-chemical etching step is carried out.
  • the wet-chemical etching step causes exposed conductive material of the first electrical contact layer to be etched, so that no unwanted short-circuit occurs after the arrangement of the second electrical contact layer at these locations.
  • the material of the first electrical contact layer may protrude from the semiconductor layers even after the deposition of the semiconductor layers and cause a short circuit as soon as it comes into contact with the second electrical contact layer.
  • the material of the semiconductor layers itself may also flake off the first electrical contact layer, so that Openings down to the first electrical contact layer are present at which arise after the deposition of the second electrical contact layer unwanted short circuits.
  • the method according to the invention advantageously prevents both variants of these short circuits, in that the freely accessible material of the first contact layer is etched away before the arrangement of the second electrical contact layer.
  • this has the effect that the subsequently arranged material of the second electrical contact layer does not form a short circuit with the first electrical contact layer, since it no longer receives any contact with the first electrical contact layer at these points.
  • the tips of the first electrical contact protruding out of the semiconductor layers are also simultaneously etched (variant 1). This also prevents an unwanted short circuit after arranging the second electrical contact layer.
  • the layer sequence of substrate, first electrical contact layer and the semiconductor layers with or without trenches is introduced into an etching solution during the etching.
  • the module with or without strip-shaped elements can simply be immersed in a bath with the wet-chemical etching solution.
  • a person skilled in the art will select a suitable etching solution and etching time depending on the material of the first electrical contact.
  • As an etching solution z.
  • the layer sequence with the first electrical contact layer can, for. B. for up to 260 Se- künden be immersed in a 0.5% (weight percent) hydrochloric acid solution.
  • the acid strength is advantageously between pH 0.1 and pH 1.
  • the etching times are typically between 10 and 500 seconds.
  • the concentration of the acid is about 0.1-5 mol * ! ,
  • the chosen acid should advantageously not attack the absorber layer (eg silicon), ie etch or modify it and in particular not oxidize it.
  • hydrofluoric acid can be used as the etching medium.
  • Hydrofluoric acid advantageously removes any Si0 2 layer on the silicon of the semiconductor layers. A Si0 2 layer on silicon is formed rapidly, z. B. when the silicon of the semiconductor layers is stored in the air or etched with nitric acid or sulfuric acid as fiction, contemporary step.
  • a hydrofluoric acid etch may therefore follow an etch with sulfuric acid or nitric acid.
  • the method can be used with identical mechanism of action of the etching step in particular in the production and simultaneous series connection of strip-shaped elements to a solar module.
  • the first electrical contact and the semiconductor layers are advantageously arranged over the entire area one after the other.
  • the method is particularly fast or simplified compared to the prior art.
  • a plurality of first trenches arranged in parallel are produced by a first PI structure, preferably by laser ablation.
  • the trenches run the length of the module.
  • the surface of the first electrical contact layer is exposed in the first trenches.
  • the trenches extend through the semiconductor layers in the cross-section of the module.
  • the trenches can also be formed down to the surface of the substrate by the PI structuring, depending on which structuring method or laser wavelength is selected. This is done by removing the active semiconductor layers and the first electrical contact layer, preferably in one step by means of a laser. The trenches run through the semiconductor layers and through the first electrical contact layer in the cross section of the module. Then, before the P2 structuring and the arrangement of the second electrical contact layer, the wet-chemical etching according to the invention advantageously takes place.
  • the semiconductor layers are laterally undercut and cavities HR are created under the Semiconductor layers (variant 2).
  • This advantageously has the effect that the subsequently arranged material of the second electrical contact layer does not form a short circuit with the first electrical contact layer. det, since it no longer receives contact with the first electrical contact layer.
  • the first trenches extend in their lateral extent enlarged and grow below the semiconductor layers, which are not or only slightly etched by the etching step.
  • the protruding from the semiconductor layers tips of the first electrical contact are also also etched away (Variant 1), In the course of the etching also unwanted short circuits are prevented by lateral undercutting of the semiconductor layers.
  • the first trenches have been wide by the PI structuring, for example, about 50 to 100 ⁇ .
  • they are widened, for example, by a total of approximately 2 to 20 ⁇ m.
  • This measure advantageously creates space in the first trenches for the subsequent deposition of the second electrical contact layer and avoids contact.
  • the material of the second electrical contact layer may not be in contact with the material of the first electrical contact layer of the same strip-shaped element at the location of the first trenches, otherwise a short circuit would occur.
  • first trenches In the region of the first trenches, material of the first electrical contact layer under the semiconductor layers is removed by the lateral undercutting. As a result, the semiconductor layers are on average over. At the same time, the first trenches under the semiconductor layers are widened laterally.
  • first trenches below the semiconductor layers are broadened by the lateral undercutting and by removal of the first electrical contact layer, the lower the risk of an undesired short circuit due to contact of the second to the first electrical contact layer of the same strip-shaped element.
  • the first trenches below the semiconductor layers should not be made too wide by the etching, as this leads to more dead volume in the module.
  • the surface of the substrate in the first trenches is exposed.
  • Adjacent and laterally offset from the first trenches of the first PI structuring second trenches are formed by a second P2 structuring. All second trenches are formed in parallel in the same orientation to the first trenches, in section, for example, to the right of the first trenches.
  • the surface of the first electrical contact layer must be exposed, since here the series connection of adjacent elements takes place.
  • the second trenches are preferably formed closely adjacent and parallel to the first trenches. With closely adjacent preferably a few microns distance of the parallel first and second trenches to each other is included.
  • a second contact layer for.
  • silver aluminum or a combination of ZnO: Al and silver or aluminum deposited on the semiconductor layers and in the first and second trenches.
  • the electrical contact is advantageously used for the series connection of adjacent strip-shaped photovoltaic elements.
  • the contact of the second to the first electrical contact layer in the region of the first trenches formed by the P 1 structuring is advantageously prevented by the etching step, since only the surface of the substrate for the second electrical contact layer is accessible there.
  • the second electrical contact layer must not be electrically interrupted at the undercut trenches of the PI structure. In the second trenches, however, the desired contacts for series connection of the second electrical contact layer of a first strip-shaped element, for. B. an element A, to a first electrical contact layer of a thereto adjacent second strip-shaped element, for. B. an element B, and so forth formed.
  • a method In the production of the second contact layer, a method should be chosen which represents a directed deposition process.
  • Typical directed deposition processes are the so-called PVD (physical vapor deposition) processes.
  • the PVD methods include the arc discharge method (Are method), the low-voltage arc evaporator (classic Balzers method) and the cathode sputtering (magnetron sputtering).
  • non-directional processes such as the so-called CVD (chemical vapor deposition) method or deposits from the liquid phase, for example by galvanic means, however, are less likely, since it in the deposition in this way in the cavity for contact between the first and second contact layer can come.
  • CVD chemical vapor deposition
  • the back contact (second contact layer) of z. B 80 nm zinc oxide and then 200 nm silver (or aluminum) is primarily the magnetron sputtering used.
  • the metal layers are alternatively applied by means of thermal evaporation.
  • third trenches each are formed by a third P3 structuring corresponding to the number of first and second trenches.
  • the third trenches electrically separate the adjacent strip-shaped elements A, B, C and so on.
  • the third trenches are in turn all in the same direction, z. B. in section to the right of the first and the second trenches formed.
  • the first, second and / or third trenches for separating the strip-shaped elements are produced in particular by laser ablation.
  • the first trenches are created by ablation of the semiconductor layers.
  • a laser of wavelength 532 nm used for the laser process z. B. This laser ablates only the semiconductor layers. It is also conceivable that both the material of the semiconductor layers and that of the first electrical contact layer is ablated in the PI structuring. Then a laser with 350 or 1064 nm wavelength must be used.
  • the second trenches are created by ablation of the semiconductor layers.
  • a laser of wavelength 532 nm is usually used during P2 structuring.
  • the third trenches are typically generated by simultaneous ablation of the semiconductor layers and the second electrical contact layer.
  • a laser of wavelength 532 nm is also used.
  • the surface of the first electrical Contact layer exposed.
  • the material of the first electrical contact layer is ablated, then the surface of the substrate is exposed. The choice of the laser thus depends on the material of the layer to be removed.
  • the first trenches which were formed after the first PI structuring, can be closed particularly advantageously by a local arrangement of insulator material.
  • the architecture of the strip-shaped elements is advantageously preserved in this way.
  • the lateral undercutting produced by the etching step according to the invention is intended as protection against contact of the second with the first electrical contact layer.
  • the closure with the insulator also advantageously has the effect that the surface of the semiconductor layers is not laterally interrupted by the first trenches of the PI structuring. Such depressions in the semiconductor layers could, after the deposition of the second electrical contact layer, disadvantageously cause the second electrical contact layer to be interrupted at these points.
  • the PI structuring can advantageously be carried out perforated. This has the advantage that a "tearing off" of the second contact layer on the undercut Pl structuring line does not lead to electrical separation of the second electrical contact layer on the Pl structuring line, since the semiconductor layers form webs above the PI trench.
  • the module according to the invention is produced rapidly by the method according to the invention and has undercut semiconductor layers. It has a high efficiency of 10%, since short circuits according to the two possible variants are prevented by the etching according to the invention.
  • the module may have a plurality of adjacent strip-shaped elements in the case of a series behavior.
  • Each strip-shaped element has a layer sequence of substrate, a first electrical contact layer on the substrate, the active semiconductor layers on the first electrical contact layer and a second electrical contact layer arranged thereon. shear contact layer on.
  • the second electrical contact layer of a strip-shaped element, for. B. element A except for the first electrical contact layer of a thereto adjacent strip-shaped photovoltaic element, for. B. element B, arranged.
  • the module is characterized in that cavities formed under the semiconductor layers by lateral undercoring are present in the first contact layer, which prevent there contact of the first electrical contact layer to the second electrical contact layer and yet a charge carrier transport in the second electrical contact layer via the PI Digging away.
  • the semiconductor layers can survive about 1 to 10 ⁇ above the first electrical contact layer.
  • Figure 1 Production and series connection of strip-shaped photovoltaic elements according to the prior art.
  • Figure 2 Inventive method for the production and series connection of strip-shaped photovoltaic elements.
  • Figure 3 View of a solar module to explain the length and width of the module.
  • FIG. 4 shows a plan view of the first electrical contact layer with needle-shaped (b) and spherical formations (a).
  • Figure 5 Top view of the first electrical contact layer with contamination on the surface (a) and chipped points (b).
  • Figure 6 General view of short circuits of the variant 1 according to the prior
  • Figure 7 General view of shorts of the variant 2 according to the prior
  • FIG. 8 General illustration of the prevention of short circuits of variant 1.
  • FIG. 9 General illustration of the prevention of short circuits of variant 2.
  • a 10 ⁇ 10 cm 2 glass substrate 1 (Corning, Eagle XG) is coated by sputtering with aluminum-doped zinc oxide (ZnO: Al) 2, which serves as a front electrode for the solar cell, see Figures 2a and 2b with the exception of the edge over the entire surface with the first electrical contact layer 2 coated.
  • ZnO aluminum-doped zinc oxide
  • the first electrical contact layer 2 is deposited on Corning Eagle XG glass with the following sputtering conditions.
  • the excitation frequency is 13.56 MHz in a VISS 300 deposition system from Von Ardenne Anlagentechnik (VA AT).
  • a ceramic target with 1% (wt) alumina content (Al 2 O 3 ) in ZnO was chosen.
  • the substrate temperature is 300 ° C at a discharge power of 1, 5 kW.
  • the argon deposition pressure is 0.1 Pa.
  • the layer thickness of the layer 2 after the deposition is about 800 nm.
  • the layer sequence with the first electrical contact layer 2 is etched in dilute hydrochloric acid (0.5% wt) for 30-50 seconds.
  • This etching step serves for the roughening of the layer 2 known from the prior art and is not the etching step according to the invention.
  • the layer thickness is about 650 nm. The etching was carried out at 25 ° C.
  • the semiconductor layers 3, here a tandem solar cell, which is based on amorphous and microcrystalline silicon, are applied by means of PECVD
  • the first trenches are ablated by the Pl patterning from the substrate side with a laser of wavelength 532 nm.
  • eight first trenches 5 arranged in parallel are formed over the length of the module (FIG. 2d, FIG. 3).
  • the lateral distance of the first trenches 5 to each other is about 1 cm.
  • the solar module to be produced is subjected to the etching process according to the invention for 260 seconds in 0.5% hydrochloric acid.
  • the layer sequence is immersed in a hydrochloric acid bath for this purpose. This step leads to lateral undercutting of the semiconductor layers 3.
  • the first trenches 5 are widened laterally, ie laterally, below the semiconductor layers so that overhangs 8 of the semiconductor layers are formed over the first electrical contact layer 2.
  • the semiconductor layers 3 are not etched.
  • the step is shown in FIG. 2e.
  • the double arrow in the trench indicates the formation of the lateral undercut by removal of the material of the first electrical contact layer 2. This creates cavities HR below the semiconductor layers.
  • the second trenches 6 are ablated by the P2 structuring in the silicon of the semiconductor layers 3 with a laser with a wavelength of 532 nm, see FIG. 2f.
  • FIG. 2f see FIG. 2f.
  • the ZnO: Al / Ag back contact is applied as a second electrical contact layer 4 over the whole area by means of sputtering (FIG. 2g). Due to the preceding lateral undercutting in FIG. 2 e, advantageously there is no contact with the first contact layer 2 in the first trenches 5 and the back contact 4 is not electrically interrupted in the region of the first trenches 5.
  • the double arrow in the first trenches in FIG. 2 g indicates the distance of the material of the second electrical contact layer 4 from that of the first electrical contact layer 2.
  • the contacts to the series shading are formed in the second trenches 6.
  • the second electrical contact layer 4 of the cell A is connected in series with the first electrical contact layer 2 of the cell B (FIG. 4A-2B).
  • the layer 4 of the cell B is contacted with the layer 2 of the cell C. This procedure is repeated over the width B of the module (FIG. 3).
  • the third trenches 7 are ablated by the P3 structuring with a laser of wavelength 532 nm, so that third trenches 7 corresponding to the number of first and second trenches 5, 6 are formed. All three laser cuts are therefore carried out with a 532 nm laser. The outer edge of the module is then defined. For this purpose, a 1064 nm laser was used.
  • this cut can be replaced with a 532 nm laser cut in silicon after the application of the semiconductor layers together with the writing of the first trenches and before the etching step according to the invention.
  • the dimensions and distances of the trenches are as follows. Due to the laser ablation, the lateral dimensions of all first, second and third trenches 5, 6 and 7 are each 80 ⁇ m wide. The additional overhang of the semiconductor layers 3 at reference numeral 8 is about 10 ⁇ wide.
  • the cells A, B and C are indicated in section by the dotted vertical lines which extend over the entire height of the layer sequence.
  • the short vertical lines at positions PI, P2 and P3 indicate the sites of formation of trenches 5, 6 and 7.
  • the efficiency of the thus prepared module with a total area of 64 cm 2 is 9.7%, the filling factor is 66%, the short circuit current density is 10.4 mA / cm 2 (or the short circuit Ström is 83.5 mA / cm 2 ) and the open terminal voltage is 1 1.3 V, so on average 1.41 V per strip.
  • Figure 3 shows in plan view and schematically the module. Length L and width B are indicated. Each 8 vertical lines separate the 9 strip-shaped photovoltaic elements from each other.
  • a detail enlargement in the region of the cells A, ⁇ and C is shown. In the detail enlargement, the vertical line corresponds to the separation of the cell A from the cell B, and the vertical line to separate the cell B from the cell C corresponds to the schematic representation of the three trenches 5 to 7 in FIG.
  • Figures 4a and 4b show scanning tunneling microscopic images of the first electrical contact layer of ZnO in the plan view.
  • the formations 49 which are needle-shaped in FIG. 4 b and mushroom-shaped in FIG. 4 a, are clearly recognizable. These are also after the
  • FIG. 5a also shows a scanning tunneling microscopic image of the first electrical contact layer in the top view.
  • An impurity on the first electrical contact layer is indicated by the arrow.
  • Such impurities may be caused by particles such.
  • the semiconductor layers can chip off at these locations.
  • FIG. 5b likewise shows a scanning tunnel microscopic image of the first electrical contact layer in the plan view.
  • the arrow marks a point where the first electrical contact layer was not uniformly deposited.
  • an imperfect coating process in the application of the semiconductor layer system can lead to small holes, so-called "pinholes.”
  • pinholes an imperfect coating process in the application of the semiconductor layer system can lead to small holes, so-called "pinholes.”
  • an incomplete coverage of the surface of the first contact layer by the semiconductor layer system leads to the formation of a local short circuit after the arrangement of the second electrical contact - layer.
  • FIG. 6 shows the end product of a process for producing such a solar module according to the prior art.
  • the first electrical contact layer 62, the semiconductor layers 63 and the second electrical contact layer 64 are deposited on the substrate 61.
  • the reference numeral 69 two shorts of variant 1 are shown.
  • FIG. 7 shows the end product of a process for producing a solar module according to the prior art.
  • FIG. 8 shows the end product of a method according to the invention for producing a solar module, in which the formation of strip-shaped photovoltaic elements has been dispensed with.
  • the first electrical contact layer 82 and the semiconductor layers 83 are arranged on the substrate 81.
  • the etching step according to the invention in this case in 0.5% hydrochloric acid for 260 seconds.
  • the hydrochloric acid advantageously causes the exposed material of the first electrical contact layer to be etched away. Not only the material of the first electrical contact layer on the surface of the semiconductor layers 83 is then etched away at these locations. Rather, the material of the first electrical contact layer 82 which passes through the semiconductor layers is also etched away, so that a channel (not shown) is formed in the semiconductor layers down to the surface of the substrate 81. With continued etching of the first electrical contact layer 82, the cavities HR are formed by the lateral undercut. In this way, all potential short circuits of variant 1 are prevented.
  • the second electrical contact layer 84 on the semiconductor layers 83 not only the surface of the semiconductor layers 83 is correspondingly over the entire surface covered, but also filled the channel in the semiconductor layers 83 with the material of the second electrical contact layer 84 (Fig. 8).
  • the material of the second electrical contact layer 84 in this case occurs down to the surface of the substrate 81, but without forming contact with the material of the first electrical contact layer 82. At these locations, the short-circuit between the first electrical contact layer 82 and the second electrical contact layer 84 is prevented by the cavities HR.
  • FIG. 9 shows the end product of a method according to the invention for producing a solar module.
  • the first electrical contact layer 92 and the semiconductor layers 93 are arranged on the substrate 91.
  • the material of the first electrical contact layer 92 deposited as in the method of the first embodiment is not uniformly disposed on the substrate 91, or the material of FIG Semiconductor layers 93 are not uniformly disposed on the first electrical contact layer 92.
  • the material of the subsequently arranged second electrical contact layer 94 as shown in FIG. 7, can be led to the surface of the first electrical contact layer and form shorts of variant 2 there.
  • a channel as shown by way of example in FIG. 7 as far as the surface of the substrate, is then present.
  • the etching step according to the invention is carried out in 0.5% strength hydrochloric acid for 260 seconds.
  • the hydrochloric acid advantageously has the effect that the exposed material of the first electrical contact layer on the surface of the substrate 91 is etched away. With continued etching of the first electrical contact layer 92, the cavities HR are formed by the lateral undercut. In this way, all potential short circuits of variant 2 are prevented.
  • the second electrical contact layer 94 In the subsequent arrangement of the second electrical contact layer 94 on the semiconductor layers 93 not only the surface of the semiconductor layers 93 is correspondingly covered over the entire surface, but also the channel in the semiconductor layers 93 filled with the material of the second electrical contact layer 94 , The material of the second electrical contact layer 94 in this case occurs down to the surface of the substrate 91, but without forming contact with the material of the first electrical contact layer 92. At these points, the short circuit between the first electrical contact layer 92 and the second electrical contact layer 94 is prevented by the cavities HR.
  • sulfuric acid and nitric acid are relatively strong oxidizing agents.
  • the zinc oxide is optionally etched, but also the silicon surface can be oxidized to Si0 2 .
  • This layer may possibly impair the functioning of the solar module.
  • hydrofluoric acid eg 1% for 10 s
  • concentrations and the etching times are characterized by an approximately linear relationship. It is therefore conceivable to choose any other concentrations and to adapt the etching times to this.
  • a method for producing a layer sequence comprising the steps: a) a first electrical contact layer 2 is arranged on a substrate 1,
  • a second electrical contact layer 4 is arranged, characterized in that
  • step b) a wet-chemical etching step is carried out.
  • the above-described novel manufacturing method according to the exemplary embodiments also reduces the occurrence of local short circuits.
  • a situation prior to the application of the second contact layer, which leads to local short circuit in the device in conventional further processing is, by the erfmdungsnostien selective, isotropic, z. B. wet chemical etching prevented.
  • the first contact layer 2 is always removed at the locations which are not covered by the semiconductor layer system, while the semiconductor layer system is not attacked by the etching process. Due to the isotropy of the selected etching process, undercutting of the semiconductor layer system occurs.
  • the etching time is basically to be chosen so that a sufficient amount of material of the first contact layer 2 is removed. This occurs at the cost of a minor generation of dead (solar) cell surface from which no (photo) current can be collected. This dead area is comparatively negligible.
  • a directed method is to be selected.
  • the guidance of the laser in lines or meandering is freely selectable.

Abstract

L'invention concerne un procédé de fabrication d'un module solaire consistant a) à disposer une première couche de contact électrique (2) sur un substrat (1); b) à disposer des couches de semi-conducteurs actives (3) sur la première couche de contact électrique (2); c) à disposer une deuxième couche de contact électrique (4) sur les couches de semi-conducteurs actives (3). Le procédé est caractérisé en ce qu'une étape d'attaque chimique humide est réalisée entre l'étape b) et l'étape c).
PCT/DE2011/001974 2010-12-01 2011-11-11 Procédé de fabrication d'un module solaire et module solaire WO2012072062A2 (fr)

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DE102010052863.3 2010-12-01
DE201010052863 DE102010052863A1 (de) 2010-12-01 2010-12-01 Verfahren zur Herstellung eines Solarmoduls und ein Solarmodul

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EP0236938A3 (fr) * 1986-03-11 1989-11-15 Siemens Aktiengesellschaft Procédé pour éviter des court-circuits lors de la fabrication de cellules solaires à couches minces en silicium amorphe
US5055416A (en) * 1988-12-07 1991-10-08 Minnesota Mining And Manufacturing Company Electrolytic etch for preventing electrical shorts in solar cells on polymer surfaces
WO2000007249A1 (fr) * 1998-07-27 2000-02-10 Citizen Watch Co., Ltd. Cellule solaire, procede de production et masque de photolithographie permettant de fabriquer ladite cellule solaire
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DE102009031592A1 (de) * 2009-07-03 2011-01-13 Forschungszentrum Jülich GmbH Verfahren zur Herstellung und Serienverschaltung von streifenförmigen Elementen auf einem Substrat

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