WO2012065497A1 - Method and apparatus for data code block synchronization - Google Patents

Method and apparatus for data code block synchronization Download PDF

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Publication number
WO2012065497A1
WO2012065497A1 PCT/CN2011/081141 CN2011081141W WO2012065497A1 WO 2012065497 A1 WO2012065497 A1 WO 2012065497A1 CN 2011081141 W CN2011081141 W CN 2011081141W WO 2012065497 A1 WO2012065497 A1 WO 2012065497A1
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Prior art keywords
data
value
synchronization
control module
holdvect
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PCT/CN2011/081141
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French (fr)
Chinese (zh)
Inventor
郭从尧
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中兴通讯股份有限公司
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Publication of WO2012065497A1 publication Critical patent/WO2012065497A1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
    • H04L7/042—Detectors therefor, e.g. correlators, state machines

Definitions

  • the present invention relates to the field of 10 Gigabit Ethernet technologies, and in particular, to a method and apparatus for synchronizing data blocks. Background technique
  • 10Gigabit Ethernet (LOGbE) technology is an extension of existing Ethernet technologies such as Gigabit Ethernet.
  • the physical layer (PHY layer) of 10 Gigabit Ethernet uses different codecs, such as 10GBase-X, which uses the same 8B/10B code as Gigabit Ethernet; and 1 OGBase-R and 1 OGBase-W uses the 64B/66B code.
  • the 10 Gigabit Ethernet has two different physical layers: the physical layer of the local area network and the physical layer of the wide area network.
  • the 10 Gigabit Ethernet physical layer includes a Physical Coding Sublayer (PCS), a Physical Medium Connection Sublayer (PMA), and a Physical Media Association Sublayer (PMD).
  • PCS Physical Coding Sublayer
  • PMA Physical Medium Connection Sublayer
  • PMD Physical Media Association Sublayer
  • FIG. 1 shows the structure of the PCS layer transceiver circuit and the relationship between the PCS layer and PMA and MAC.
  • the PCS layer transceiver circuit consists of a PCS transmit circuit and a PCS receive circuit.
  • the PCS transmitting circuit is used to implement the encoding process, and should include a 64B/66B encoding unit, a scrambling unit, a gearbox, and a data width conversion unit;
  • the PCS receiving circuit is configured to implement a decoding process, including a data width conversion unit, a data block synchronization unit, De-scrambling unit and 64B/66B decoding unit.
  • the data width conversion unit of the PCS receiving direction is used to capture the 16-bit sent by the PMA.
  • the data block synchronization unit synchronizes the 66-bit data code block from the input 64-bit data, and gives a code block lock indication, so that the subsequent 64B/66B decoding unit can complete the decoding.
  • the data block synchronization unit is a key component of the receiving direction of the 10 Gigabit Ethernet PCS.
  • the technical problem to be solved by the present invention is to provide a method and apparatus for synchronizing data code blocks, realizing a synchronization process of data code blocks, and providing working signals for subsequent descrambling and decoding.
  • a method for synchronizing data blocks includes: detecting synchronization data from the input data, and detecting a synchronization header of the synchronization data obtained by the sample, in the detection process, if detecting If the number of invalid sync headers does not reach a threshold, the configuration code block synchronization indication signal is valid, and the decoding unit is notified to perform a decoding operation.
  • the step of synchronizing the data from the input data comprises:
  • the step of performing bit width conversion on the input data comprises:
  • step counter When the count value of the step counter is 0, save the input data (wdata) to the vector save register (holdvect), and do not output the data after the bit width conversion (dout), and set the data to be valid. The indication is invalid.
  • the method further comprises:
  • the output dout ⁇ wdata[2k- 1 :0] , holdvect[65-2k: 0] ⁇ ;
  • the method further comprises:
  • the data sample window is slidably adjusted, and the sliding adjusted data sample window is sampled.
  • the sync header of the sync data is detected.
  • the sliding adjustment is to slide the data sample window to the high position of the data after the bit width conversion.
  • the step of sliding the data sample window to the upper bit of the data after the bit width conversion comprises: setting an odd flag (odd), buffering the dout of two clock cycles to the input data save register (stage), detecting the value of the odd, the value of the odd is flipped between the first value and the second value, and if the odd takes the first value, sliding the position of the data sample window in the stage to a high position One bit, and flip the value of oddd.
  • the method further comprises:
  • the step of detecting the synchronization header of the synchronization data obtained by the sampling comprises: detecting whether the lower two bits of the synchronization data are the same, if not the same, the effective synchronization header; otherwise, the invalid synchronization header.
  • a device for synchronizing data blocks comprising: a data block synchronization unit and a sliding control module, wherein:
  • the sliding control module is set to: Synchronize data from the input data;
  • the data block synchronization unit is configured to: detect a synchronization header of the synchronization data obtained by the sliding control module, and configure a code block synchronization indication signal if the number of detected invalid synchronization headers does not reach a threshold during the detection process. To be effective, the decoding unit is notified to perform a decoding operation.
  • the sliding control module comprises a write control module and a read control module, wherein:
  • the write control module is set to: perform bit width conversion on the input data
  • the read control module is set to: Synchronize data from the data converted from the bit width through the data sample window.
  • the write control module performs bit width conversion on the input data, including:
  • step counter When the count value of the step counter is 0, save the input data (wdata) to the vector save register (holdvect), and do not output the data after the bit width conversion (dout), and set the data to be valid. The indication is invalid;
  • the data block synchronization unit is further configured to: in the detecting process, if the number of detected invalid synchronization heads reaches a threshold value, or the code block synchronization indication signal is invalid, the read control module is called to perform the data sampling window.
  • the slide adjustment detects the sync header of the sync data of the slide-adjusted data sample window.
  • the read control module is further configured to: perform sliding adjustment on the data sampling window, the sliding adjustment is to slide the data sampling window to a high bit of the data after the bit width conversion, and the high bit of the data after the bit width conversion
  • the steps for sliding include:
  • the read control module is further configured to: when the odd value takes the second value, call the write control module to discard the upper two bits of the holdvect for the dout, and slide the position of the data sample window in the stage to the lower position by one bit, and Turn the odd to flip;
  • the data block synchronization state machine and the sliding control module realize synchronous 66-bit data code blocks from the input 64-bit data, and give a code block lock indication.
  • FIG. 1 is a schematic diagram showing the position of a data block synchronization unit in a PCS in the prior art
  • FIG. 2 is a functional block diagram of a data block synchronization device according to an embodiment of the present invention.
  • FIG. 3 is a flowchart of functional steps performed by the data block synchronization state machine according to the embodiment;
  • FIG. 4 is a flowchart of functional steps performed by the write control module in the embodiment;
  • FIG. 5 is a schematic diagram of 64-bit data to 66-bit data conversion according to an embodiment of the present invention;
  • Figure 6 is a flow chart showing the functional steps performed by the read control module of the present embodiment.
  • the data block synchronization unit includes: a data block synchronization state machine and a slide control module, wherein the slide control module includes: a read control module and a write control module.
  • the input signal of the data block synchronization unit has a 64-bit data signal wdata sent by the data width conversion unit and a signal valid signal sent by the PMA module indicating that signal_ok, wdata and signal_ok are input to the write control module, wherein, wdata 64-bit data converted by the data width conversion unit by capturing 16-bit data.
  • the output signal of the data block synchronization unit has 66-bit synchronization data rdata, code block synchronization indication signal block_lock and data valid indication wen, wherein block-lock is valid after data block synchronization is implemented, and is used to inform the decoding unit.
  • the data block is locked and can be decoded. Since the read control module and the write control module operate at the same clock frequency, the input data wdata has a bit width of 64-bit, and the output data rdata has a bit width of 66-bit. Therefore, the output data rdata will be available every 33 clock cycles. One clock cycle data is invalid.
  • the wen is used to indicate whether the data of the current clock cycle is valid data, and is used to notify the validity of the subsequent descrambling unit and the decoding unit data.
  • the internal signal of the data block synchronization unit is sent by the write control module to the data block synchronization state machine to notify whether the current data of the data block synchronization state machine is 66-bit valid data for the current data.
  • the validity of the frame header is detected.
  • the internal signal further includes a sliding signal slip sent by the data block synchronization state machine to the read control module, a slide completion signal slip-done sent by the read control module to the data block synchronization state machine, and a bit sent by the read control module to the write control module.
  • the flag drop-flag and the write control module are sent to the 66-bit data dout of the read control module.
  • slip indicates block-lock is invalid or the block-lock is valid but the number of frame headers found to be illegal in a round of loop detection is greater than the threshold (such as 16), to achieve a 66-bit data sample window Sliding, such as sliding 1 bit to the high position; slip- done means that the read control module has completed the processing of sliding the data sample window to the upper position by 1 bit; drop_flag indicates that the read control module is to be The write control module discards two bits of data.
  • the function of the data block synchronization state machine is: When wen is valid and signal_ok is valid, it is detected whether the synchronization header of the 66-bit data code block rdata is a valid synchronization header, when the lower two bits of rdata, rdata[l] and rdata When [0] is not the same, it is a valid sync header; otherwise it is an invalid sync header. At the same time, a sync header counter and an invalid sync header counter are set, and the sync header counter is incremented by one for each sync header detected, and the null sync header counter is incremented by one if it is an invalid sync header.
  • the count value of the sync header counter is equal to 64, that is, when 64 data code blocks are detected, if the count value of the invalid sync head counter is less than 16, the block_lock is set, then the two counters are cleared, and the next round of detection is started. process.
  • the function of the slide control module is: When the block-lock is invalid or the count value of the invalid sync counter is equal to 16, the sliding adjustment of the data sample window is performed, and the input 64-bit wdata is rearranged into 66-bit rdata. The bit width is still 66-bit. In this way, the data block synchronization state machine can use the new rdata[l:0] to detect whether the synchronization header is valid. Each time the data block synchronization state machine calls the sliding control module, the 66-bit data sampling window is shifted to the upper position by one bit.
  • the write control module rearranges the input 64-bit wdata into a 66-bit dout output to the read control module, and gives a valid data indication.
  • the read control module buffers the dout data sent by the write control module for two clock cycles, and slides the output 66-bit rdata data to a high position each time the slip signal sent by the data block synchronization state machine is detected. And send the swept data to the descrambling and decoding unit. After the sliding adjustment is completed, the read control module sets the slip-done signal to notify the data block synchronization state machine that the sliding adjustment is over, and the synchronization header can be re-detected.
  • the data block synchronization state machine is the main functional component of the data block synchronization unit, and its function is to detect the validity of the synchronization header of rdata.
  • the block synchronization indication signal block_lock is valid, otherwise it is invalid.
  • the data sample window is started. The sliding adjustment mechanism until the synchronization condition is met.
  • the specific implementation of the data block synchronization state machine is shown in FIG. 3, and includes the following steps:
  • Step 301 When the data valid indication signal wen is valid and signal_ok is valid, enter an initialization state, clear the synchronization header counter sh_cnt and the invalid synchronization header counter invalid_sh_cnt, and set block_lock to be invalid;
  • Step 302 Enter a synchronization header detection state, check whether the synchronization header of the current 66-bit data rdata is valid; if it is a valid synchronization header, the synchronization header counter sh_cnt count value is incremented by one, and the process proceeds to step 303; if it is an invalid synchronization header , the synchronization header counter sh_cnt and the invalid synchronization header counter invalid_sh_cnt count value is increased by 1, to jump to step 304;
  • the determination condition of the validity of the synchronization header is: If rdata[l] is different from rdata[0], that is, the difference between the two is 1 and it is considered to be a valid synchronization header, and the synchronization header is effectively indicated by sh_ valid; Otherwise it is an invalid sync header and sh_active is cleared.
  • a detection process is set to detect 64 synchronization data.
  • Sync header set block-lock.
  • Step 302 If the sync header counter sh_cnt ⁇ 64, and invalid_sh_cnt ⁇ l6, then jump to step 302 to perform the next sync header detection of the current round.
  • Step 304 If invalid_sh_cnt is equal to 16, or the block_lock signal is invalid, then go to step 305 to perform sliding adjustment;
  • Step 305 Set the slip to set the slide control module to move the 66-bit data sampling window to the upper position by one bit.
  • Step 306 Sh—cnt and invalid—sh—cnt is cleared, go to step 302, proceed to the next Synchronous head loop detection of the wheel;
  • the function of the sliding control module is to slide the 66-bit data sampling window and discard the 2-bit data when the block-lock is invalid or when the number of invalid synchronization headers is equal to 16.
  • the input data wdata bit width is 64-bit
  • the output data rdata bit width is 66-bit
  • the output data rdata will have one clock every 33 clock cycles.
  • the cycle data is invalid
  • the write control module generates a valid data indication, and recombines the 64-bit input data wdata into a 66-bit dout, and sends it to the read control module, as shown in Figure 4, the specific implementation steps of the write control module.
  • Step 401 When the drop-flag sent by the read control module is detected, it indicates that the input wdata needs to be discarded by two bits, and is rearranged into 66-bit data output to the read control module, and the process proceeds to step 403; If drop-flag is detected, then go to step 402;
  • Step 402 setting a step counter count value (step), the value range is 0 to 32, adding 1 to step, and jumping to step 404, if step>32, then step is cleared, and the process proceeds to step 404;
  • the overflow value of the advance counter is 32.
  • Ste Step 1 has a 66-bit data dout output, and the output 66-bit data dout consists of the current 64-bit input data wdata and the data holdvect saved in the previous clock cycle. If step is 2, the output data dout will discard the upper two bits of holdvect.
  • Step 403 step increments 2, jumps to step 404, if step>31, then step is cleared, step 404 is performed;
  • Step 404 it is determined whether the current step value is 0, if it is 0, then jump to step 405; if the current step is not 0, then jump to step 406;
  • Step 405 Save the input 64-bit wdata to the holdvect (vector save register), and the data cycle does not output the data dout, and the valid data indication is invalid;
  • Holdvect has a bit width of 64 bits, which is used to hold the input wdata.
  • Figure 5 is a more intuitive representation of the above steps.
  • the left side of Figure 5 is holdvect, the right side is dout, and each line corresponds to a step.
  • the low order of dout is assigned by the holdvect saved in the previous clock cycle, and the remaining of dout
  • the upper bit is assigned by the lower bits of wdata of the current clock cycle.
  • step is increased by 2
  • the output dout will discard the upper two bits of holdvect, and the remaining bits are assigned by the current wdata.
  • Step 603 inverting the odd, step 604;
  • Step 608 inverting odd, and set drop_flag, informing the write control module to discard the upper two bits of holdvect, step 609;
  • step 612 the value of rdata is swiped from stage[66:l] to stage[65:0].
  • duet is deleted the upper two bits of holdvect, and the value of rdata is slid to the lower level of stage. Bit, thus achieving the function of rdata value sliding to a high bit, step 613;
  • Step 613 set slip- done, the adjustment is completed.
  • the data block synchronization state machine and the sliding control module realize that 66-bit data code blocks are synchronized from the input 64-bit data, and the code block locking indication is given, and the data code block synchronization is realized.

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Abstract

The invention discloses a method and an apparatus for data code block synchronization. The method includes: sampling synchronization data from input data, and performing detection for the synchronization head of the sampled synchronization data; during the detection process, if the number of the detected invalid synchronization heads does not come to the threshold value, configuring the code block synchronization indication signal to be valid, and informing a decoding unit to perform decoding operation. It is realized that a 66-bit data code block is synchronized from 64-bit input data by a data code block synchronization state machine and a sliding control module in the invention. And an instruction of code block locking is provided to achieve the function of data code block synchronization.

Description

一种数据码块同步的方法及装置  Method and device for synchronizing data code blocks
技术领域 Technical field
本发明涉及万兆以太网技术领域， 尤其涉及一种数据码块同步的方法及 装置。 背景技术  The present invention relates to the field of 10 Gigabit Ethernet technologies, and in particular, to a method and apparatus for synchronizing data blocks. Background technique
万兆以太网 （ lOGigabit Ethernet, lOGbE )技术是千兆以太网 （Gigabit Ethernet )等已有以太网技术的延伸。 针对不同的使用环境， 万兆以太网的物 理层（PHY层）使用不同的编解码方式， 如 10GBase-X釆用的是与千兆以太 网相同的 8B/10B码； 而 1 OGBase-R和 1 OGBase-W釆用的是 64B/66B码。  10Gigabit Ethernet (LOGbE) technology is an extension of existing Ethernet technologies such as Gigabit Ethernet. For different environments, the physical layer (PHY layer) of 10 Gigabit Ethernet uses different codecs, such as 10GBase-X, which uses the same 8B/10B code as Gigabit Ethernet; and 1 OGBase-R and 1 OGBase-W uses the 64B/66B code.
万兆以太网有两种不同的物理层： 局域网物理层和广域网物理层。 万兆 以太网物理层包括物理编码子层 （PCS ) 、 物理媒质连接子层（PMA )和物 理媒质关联子层（PMD ) 。  10 Gigabit Ethernet has two different physical layers: the physical layer of the local area network and the physical layer of the wide area network. The 10 Gigabit Ethernet physical layer includes a Physical Coding Sublayer (PCS), a Physical Medium Connection Sublayer (PMA), and a Physical Media Association Sublayer (PMD).
图 1为现有 PCS层收发电路的组成结构示意图以及 PCS层和 PMA、MAC 的关系。如图 1所示， PCS层收发电路由 PCS发送电路和 PCS接收电路组成。 PCS发送电路用于实现编码过程， 应该包括 64B/66B编码单元、 扰码单元、 变速箱和数据宽度转换单元； PCS接收电路用于实现解码过程， 包括数据宽 度转换单元、 数据码块同步单元、 解扰单元和 64B/66B解码单元。  Figure 1 shows the structure of the PCS layer transceiver circuit and the relationship between the PCS layer and PMA and MAC. As shown in Figure 1, the PCS layer transceiver circuit consists of a PCS transmit circuit and a PCS receive circuit. The PCS transmitting circuit is used to implement the encoding process, and should include a 64B/66B encoding unit, a scrambling unit, a gearbox, and a data width conversion unit; the PCS receiving circuit is configured to implement a decoding process, including a data width conversion unit, a data block synchronization unit, De-scrambling unit and 64B/66B decoding unit.
其中， PCS接收方向的数据宽度转换单元用来捕获 PMA送来的 16-bit The data width conversion unit of the PCS receiving direction is used to capture the 16-bit sent by the PMA.
XSBI接口数据， 并转换为 64-bit数据。 数据码块同步单元从输入的 64-bit数 据中， 同步出 66-bit的数据码块， 并给出码块锁定指示， 便于后续的 64B/66B 解码单元完成解码。 从图 1可见， 数据码块同步单元是万兆以太网 PCS的接 收方向的关键组成部分。 XSBI interface data, and converted to 64-bit data. The data block synchronization unit synchronizes the 66-bit data code block from the input 64-bit data, and gives a code block lock indication, so that the subsequent 64B/66B decoding unit can complete the decoding. As can be seen from Figure 1, the data block synchronization unit is a key component of the receiving direction of the 10 Gigabit Ethernet PCS.
目前， IEEE 802.3ae标准中只对数据码块同步进行功能性描述， 并没有 提供具体的实现方案。 发明内容 本发明要解决的技术问题是提供一种数据码块同步的方法和装置， 实现 数据码块的同步过程， 为后续的解扰和解码提供工作信号。 At present, only the functional description of data block synchronization is performed in the IEEE 802.3ae standard, and no specific implementation scheme is provided. Summary of the invention The technical problem to be solved by the present invention is to provide a method and apparatus for synchronizing data code blocks, realizing a synchronization process of data code blocks, and providing working signals for subsequent descrambling and decoding.
为解决上述技术问题， 本发明的一种数据码块同步的方法， 包括： 从输入数据中釆样同步数据，对釆样得到的同步数据的同步头进行检测， 在检测过程中， 若检测到的无效同步头的数量未达到阔值， 则配置码块同步 指示信号为有效， 通知解码单元进行解码操作。  In order to solve the above technical problem, a method for synchronizing data blocks according to the present invention includes: detecting synchronization data from the input data, and detecting a synchronization header of the synchronization data obtained by the sample, in the detection process, if detecting If the number of invalid sync headers does not reach a threshold, the configuration code block synchronization indication signal is valid, and the decoding unit is notified to perform a decoding operation.
优选地， 从输入数据中釆样同步数据的步骤包括：  Preferably, the step of synchronizing the data from the input data comprises:
对输入数据进行位宽转换， 通过数据釆样窗口从位宽转换后的数据中釆 样同步数据。  Perform bit width conversion on the input data, and synchronize the data in the data converted from the bit width through the data sample window.
优选地， 对输入数据进行位宽转换的步骤包括：  Preferably, the step of performing bit width conversion on the input data comprises:
设置步进计数器， 在该步进计数器的计数值为 0时， 将输入数据 (wdata) 保存到向量保存寄存器 (holdvect)中， 且不输出位宽转换后的数据 (dout), 并设 置数据有效指示为无效。  Set the step counter. When the count value of the step counter is 0, save the input data (wdata) to the vector save register (holdvect), and do not output the data after the bit width conversion (dout), and set the data to be valid. The indication is invalid.
优选地， 该方法还包括：  Preferably, the method further comprises:
在步进计数器的计数值大于 0 且未达到溢出值时， 输出 dout= { wdata[2k- 1 :0] ,holdvect[65-2k: 0] } ； holdvect 中 保存的数据为 ： holdvect[63-2k:0]=wdata[63:2k]; holdvect[63:64-2k]=0, 其中， k为步进计数器 的当前计数值， 并设置数据有效指示为有效。  When the count value of the step counter is greater than 0 and the overflow value is not reached, the output dout= { wdata[2k- 1 :0] , holdvect[65-2k: 0] } ; The data saved in holdvect is: holdvect[63- 2k:0]=wdata[63:2k]; holdvect[63:64-2k]=0, where k is the current count value of the step counter, and the data valid indication is set to be valid.
优选地， 该方法还包括：  Preferably, the method further comprises:
在 步 进 计 数 器 的 计 数 值 达 到 溢 出 值 时 ， 输 出 dout={wdata[63:0],holdvect[l :0]]} , 并设置数据有效指示为有效。  When the count value of the step counter reaches the overflow value, output dout={wdata[63:0], holdvect[l :0]]}, and set the data valid indication to be valid.
优选地， 检测过程中， 若检测到的无效同步头的数量达到阔值， 或码块 同步指示信号为无效， 则对数据釆样窗口进行滑动调整， 对滑动调整后的数 据釆样窗口釆样的同步数据的同步头进行检测。  Preferably, during the detecting process, if the number of detected invalid sync heads reaches a threshold value, or the code block synchronization indication signal is invalid, the data sample window is slidably adjusted, and the sliding adjusted data sample window is sampled. The sync header of the sync data is detected.
优选地， 滑动调整为将数据釆样窗口向位宽转换后的数据的高位滑动。 优选地， 将数据釆样窗口向位宽转换后的数据的高位滑动的步骤包括： 设置奇偶标志 (odd),将两个时钟周期的 dout緩存到输入数据保存寄存器 (stage)中 ,检测 odd的取值， 该 odd的取值在第一值与第二值之间翻转， 若该 odd取第一值， 则将数据釆样窗口在 stage中的位置向高位滑动一位， 并翻转 oddd的取值。 Preferably, the sliding adjustment is to slide the data sample window to the high position of the data after the bit width conversion. Preferably, the step of sliding the data sample window to the upper bit of the data after the bit width conversion comprises: setting an odd flag (odd), buffering the dout of two clock cycles to the input data save register (stage), detecting the value of the odd, the value of the odd is flipped between the first value and the second value, and if the odd takes the first value, sliding the position of the data sample window in the stage to a high position One bit, and flip the value of oddd.
优选地， 该方法还包括：  Preferably, the method further comprises:
若 odd取第二值，则对 dout丟弃 holdvect的高两位， dout={wdata[2k+3:0] , holdvect[61-2k:0]} , 其中， k为步进计数器的当前计数值， 并将数据釆样窗口 在 stage中的位置向低位滑动一位， 并翻转 oddd的取值。  If odd takes the second value, discard the upper two bits of holdvect for dout, dout={wdata[2k+3:0] , holdvect[61-2k:0]} , where k is the current count of the step counter Value, and slide the position of the data sample window in the stage to the lower position, and flip the value of oddd.
优选地， 对釆样得到的同步数据的同步头进行检测的步骤包括： 检测同步数据的低两位是否相同， 若不相同， 则为有效同步头； 否则， 为无效同步头。  Preferably, the step of detecting the synchronization header of the synchronization data obtained by the sampling comprises: detecting whether the lower two bits of the synchronization data are the same, if not the same, the effective synchronization header; otherwise, the invalid synchronization header.
一种数据码块同步的装置， 包括： 数据码块同步单元和滑动控制模块， 其中：  A device for synchronizing data blocks, comprising: a data block synchronization unit and a sliding control module, wherein:
滑动控制模块设置为： 从输入数据中釆样同步数据；  The sliding control module is set to: Synchronize data from the input data;
数据码块同步单元设置为： 对滑动控制模块釆样得到的同步数据的同步 头进行检测， 在检测过程中， 若检测到的无效同步头的数量未达到阔值， 则 配置码块同步指示信号为有效， 通知解码单元进行解码操作。  The data block synchronization unit is configured to: detect a synchronization header of the synchronization data obtained by the sliding control module, and configure a code block synchronization indication signal if the number of detected invalid synchronization headers does not reach a threshold during the detection process. To be effective, the decoding unit is notified to perform a decoding operation.
优选地， 滑动控制模块包括写控制模块和读控制模块， 其中：  Preferably, the sliding control module comprises a write control module and a read control module, wherein:
写控制模块设置为： 对输入数据进行位宽转换；  The write control module is set to: perform bit width conversion on the input data;
读控制模块设置为： 通过数据釆样窗口从位宽转换后的数据中釆样同步 数据。  The read control module is set to: Synchronize data from the data converted from the bit width through the data sample window.
优选地， 写控制模块对输入数据进行位宽转换包括：  Preferably, the write control module performs bit width conversion on the input data, including:
设置步进计数器， 在该步进计数器的计数值为 0时， 将输入数据 (wdata) 保存到向量保存寄存器 (holdvect)中， 且不输出位宽转换后的数据 (dout), 并设 置数据有效指示为无效；  Set the step counter. When the count value of the step counter is 0, save the input data (wdata) to the vector save register (holdvect), and do not output the data after the bit width conversion (dout), and set the data to be valid. The indication is invalid;
在 步进计数器 的计数值 大于 0 且未达到 溢 出 值时 ， dout= { wdata[2k- 1 :0] ,holdvect[65-2k: 0] } ； holdvect 中 保存的数据为 ： holdvect[63-2k:0]=wdata[63:2k]; holdvect[63:64-2k]=0, 其中， k为步进计数器 的当前计数值， 并设置数据有效指示为有效； When the count value of the step counter is greater than 0 and the overflow value is not reached, dout= { wdata[2k- 1 :0] , holdvect[65-2k: 0] } ; The data saved in holdvect is: holdvect[63-2k :0]=wdata[63:2k]; holdvect[63:64-2k]=0, where k is the step counter Current count value, and set the data valid indication to be valid;
在步进计数器的计数值达到溢出值时， dout={wdata[63:0],holdvect[l :0]]} , 并设置数据有效指示为有效。  When the count value of the step counter reaches the overflow value, dout={wdata[63:0], holdvect[l :0]]}, and set the data valid indication to be valid.
优选地， 数据码块同步单元还设置为： 在检测过程中， 若检测到的无效 同步头的数量达到阔值， 或码块同步指示信号为无效， 则调用读控制模块对 数据釆样窗口进行滑动调整， 对滑动调整后的数据釆样窗口釆样的同步数据 的同步头进行检测。  Preferably, the data block synchronization unit is further configured to: in the detecting process, if the number of detected invalid synchronization heads reaches a threshold value, or the code block synchronization indication signal is invalid, the read control module is called to perform the data sampling window. The slide adjustment detects the sync header of the sync data of the slide-adjusted data sample window.
优选地， 读控制模块还设置为： 对对数据釆样窗口进行滑动调整， 该滑 动调整为将数据釆样窗口向位宽转换后的数据的高位滑动， 该向位宽转换后 的数据的高位滑动的步骤包括：  Preferably, the read control module is further configured to: perform sliding adjustment on the data sampling window, the sliding adjustment is to slide the data sampling window to a high bit of the data after the bit width conversion, and the high bit of the data after the bit width conversion The steps for sliding include:
设置奇偶标志 (odd),将两个时钟周期的 dout緩存到输入数据保存寄存器 (stage)中，检测 odd的取值， 该 odd的取值在第一值与第二值之间翻转， 若该 odd取第一值，则将数据釆样窗口在 stage中的位置向高位滑动一位，并将 odd 进行翻转。  Set the odd-odd flag (odd), cache the dout of two clock cycles into the input data save register (stage), detect the value of the odd, the value of the odd is flipped between the first value and the second value, if When odd takes the first value, it slides the position of the data sample window in the stage to the upper position and flips the odd.
优选地， 读控制模块还设置为： 在 odd取第二值时， 调用写控制模块对 dout丟弃 holdvect的高两位，并将数据釆样窗口在 stage中的位置向低位滑动 一位， 并将 odd进行翻转；  Preferably, the read control module is further configured to: when the odd value takes the second value, call the write control module to discard the upper two bits of the holdvect for the dout, and slide the position of the data sample window in the stage to the lower position by one bit, and Turn the odd to flip;
写控制模块还设置为： 在读控制模块调用时， 取 dout={wdata[2k+3:0] , holdvect[61-2k:0]} , 其中， k为步进计数器的当前计数值。  The write control module is also set to: When the read control module is called, take dout={wdata[2k+3:0], holdvect[61-2k:0]}, where k is the current count value of the step counter.
综上所述， 本发明实施例通过数据码块同步状态机和滑动控制模块， 实 现从输入的 64-bit数据中， 同步出 66-bit的数据码块， 并给出码块锁定指示， 实现数据码块同步的功能。 附图概述  In summary, the data block synchronization state machine and the sliding control module realize synchronous 66-bit data code blocks from the input 64-bit data, and give a code block lock indication. The function of data block synchronization. BRIEF abstract
图 1为现有技术中数据码块同步单元在 PCS中的位置示意图；  1 is a schematic diagram showing the position of a data block synchronization unit in a PCS in the prior art;
图 2为本实施方式数据码块同步装置的功能框图；  2 is a functional block diagram of a data block synchronization device according to an embodiment of the present invention;
图 3为本实施方式数据码块同步状态机所执行功能步骤的流程图； 图 4为本实施方式中写控制模块所执行功能步骤的流程图； 图 5为本实施方式 64-bit数据到 66-bit数据转换示意图； 3 is a flowchart of functional steps performed by the data block synchronization state machine according to the embodiment; FIG. 4 is a flowchart of functional steps performed by the write control module in the embodiment; FIG. 5 is a schematic diagram of 64-bit data to 66-bit data conversion according to an embodiment of the present invention; FIG.
图 6为本实施方式的读控制模块所执行功能步骤的流程图。  Figure 6 is a flow chart showing the functional steps performed by the read control module of the present embodiment.
本发明的较佳实施方式 Preferred embodiment of the invention
下面结合附图对本发明的实施方式进行详细说明。  Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
如图 2所示， 数据码块同步单元包括： 数据码块同步状态机和滑动控制 模块， 其中， 滑动控制模块包括： 读控制模块和写控制模块。 数据码块同步单元的输入信号有数据宽度转换单元送来的 64-bit数据信 号 wdata和 PMA模块送来的信号有效指示 signal— ok, wdata和 signal— ok均输 入到写控制模块， 其中， wdata为数据宽度转换单元通过捕获 16-bit的数据转 换而成的 64-bit数据。  As shown in FIG. 2, the data block synchronization unit includes: a data block synchronization state machine and a slide control module, wherein the slide control module includes: a read control module and a write control module. The input signal of the data block synchronization unit has a 64-bit data signal wdata sent by the data width conversion unit and a signal valid signal sent by the PMA module indicating that signal_ok, wdata and signal_ok are input to the write control module, wherein, wdata 64-bit data converted by the data width conversion unit by capturing 16-bit data.
数据码块同步单元的输出信号有 66-bit的同步数据 rdata、 码块同步指示 信号 block— lock和数据有效指示 wen, 其中， block— lock在实现数据码块同步 后有效， 用来告知解码单元数据码块已经锁定， 可以进行解码操作。 由于读 控制模块和写控制模块工作的时钟频率相同， 输入的数据 wdata 的位宽为 64-bit, 而输出数据 rdata的位宽为 66-bit, 因此， 每 33个时钟周期输出数据 rdata将有一个时钟周期数据无效。 wen用来指示当前时钟周期的数据是否为 有效数据， 用来通知后续的解扰单元和解码单元数据的有效性。 wen 同时作 为数据码块同步单元的内部信号，由写控制模块发送给数据码块同步状态机， 用来通知数据码块同步状态机当前数据是否为 66-bit的有效数据， 以进行当 前数据的帧头的有效性检测。  The output signal of the data block synchronization unit has 66-bit synchronization data rdata, code block synchronization indication signal block_lock and data valid indication wen, wherein block-lock is valid after data block synchronization is implemented, and is used to inform the decoding unit. The data block is locked and can be decoded. Since the read control module and the write control module operate at the same clock frequency, the input data wdata has a bit width of 64-bit, and the output data rdata has a bit width of 66-bit. Therefore, the output data rdata will be available every 33 clock cycles. One clock cycle data is invalid. The wen is used to indicate whether the data of the current clock cycle is valid data, and is used to notify the validity of the subsequent descrambling unit and the decoding unit data. The internal signal of the data block synchronization unit is sent by the write control module to the data block synchronization state machine to notify whether the current data of the data block synchronization state machine is 66-bit valid data for the current data. The validity of the frame header is detected.
内部信号还包含数据码块同步状态机送给读控制模块的滑动信号 slip、读 控制模块送给数据码块同步状态机的滑动完毕信号 slip— done、 读控制模块送 给写控制模块的 bit丟弃标志 drop— flag和写控制模块送给读控制模块的 66-bit 数据 dout。 其中， slip表示 block— lock无效或者在 block— lock已有效但是在一 轮的循环检测当中发现不合法的帧头数目大于阔值（如 16 )时，要实现 66-bit 的数据釆样窗口的滑动， 如向高位滑动 1位； slip— done表示读控制模块已经 完成了对数据釆样窗口向高位滑动 1位的处理； drop— flag表示读控制模块要 求写控制模块丟掉两比特的数据。 The internal signal further includes a sliding signal slip sent by the data block synchronization state machine to the read control module, a slide completion signal slip-done sent by the read control module to the data block synchronization state machine, and a bit sent by the read control module to the write control module. The flag drop-flag and the write control module are sent to the 66-bit data dout of the read control module. Where slip indicates block-lock is invalid or the block-lock is valid but the number of frame headers found to be illegal in a round of loop detection is greater than the threshold (such as 16), to achieve a 66-bit data sample window Sliding, such as sliding 1 bit to the high position; slip- done means that the read control module has completed the processing of sliding the data sample window to the upper position by 1 bit; drop_flag indicates that the read control module is to be The write control module discards two bits of data.
数据码块同步状态机的功能是： 当 wen有效且 signal— ok有效时， 检测 66-bit数据码块 rdata的同步头是否为有效同步头， 当 rdata的低两位， rdata[l] 和 rdata[0]不相同时， 为有效同步头； 否则为无效同步头。 同时设置一个同步 头计数器和一个无效同步头计数器，每检测一个同步头则同步头计数器加一， 若为无效同步头， 则无效同步头计数器加一。  The function of the data block synchronization state machine is: When wen is valid and signal_ok is valid, it is detected whether the synchronization header of the 66-bit data code block rdata is a valid synchronization header, when the lower two bits of rdata, rdata[l] and rdata When [0] is not the same, it is a valid sync header; otherwise it is an invalid sync header. At the same time, a sync header counter and an invalid sync header counter are set, and the sync header counter is incremented by one for each sync header detected, and the null sync header counter is incremented by one if it is an invalid sync header.
当检测到的无效同步头数目等于 16时， 或者 block— lock无效时， 要进行 数据釆样窗口的滑动调整，将 66-bit的釆样数据向高位调整一位，在 slip— done 有效， 即滑动调整结束时， 清零两个计数器， 开始下一轮检测过程。  When the number of invalid sync headers detected is equal to 16, or block-lock is invalid, the sliding adjustment of the data sample window is performed, and the 66-bit sample data is adjusted to the upper position by one bit, which is valid in slip-done, that is, At the end of the slide adjustment, both counters are cleared and the next round of detection is started.
当同步头计数器的计数值等于 64, 即检测了 64个数据码块时， 若无效 同步头计数器的计数值小于 16, 则 block— lock置位， 然后清零两个计数器， 开始下一轮检测过程。  When the count value of the sync header counter is equal to 64, that is, when 64 data code blocks are detected, if the count value of the invalid sync head counter is less than 16, the block_lock is set, then the two counters are cleared, and the next round of detection is started. process.
当同步头计数器的计数值小于 64时， 且无效同步头计数器数值小于 16 时， 继续本轮的下一次检测过程。  When the count value of the sync header counter is less than 64, and the value of the invalid sync counter counter is less than 16, the next detection process of this round is continued.
滑动控制模块的功能是： 当 block— lock无效或者无效同步头计数器的计 数值等于 16时， 进行数据釆样窗口的滑动调整， 将输入的 64-bit的 wdata重 新整理成 66-bit的 rdata,位宽仍然保持 66-bit。这样数据码块同步状态机就可 以利用新的 rdata[l :0]来检测同步头是否有效。 数据码块同步状态机每次调用 滑动控制模块， 都实现 66-bit的数据釆样窗口向高位滑动 1位。  The function of the slide control module is: When the block-lock is invalid or the count value of the invalid sync counter is equal to 16, the sliding adjustment of the data sample window is performed, and the input 64-bit wdata is rearranged into 66-bit rdata. The bit width is still 66-bit. In this way, the data block synchronization state machine can use the new rdata[l:0] to detect whether the synchronization header is valid. Each time the data block synchronization state machine calls the sliding control module, the 66-bit data sampling window is shifted to the upper position by one bit.
其中， 写控制模块将输入的 64-bit的 wdata重新整理成 66-bit的 dout输 出给读控制模块， 并给出数据有效指示 wen。 读控制模块緩存两个时钟周期 的写控制模块送来的 dout数据，并每当检测到数据码块同步状态机送来的 slip 信号时， 将输出的 66-bit的 rdata数据向高位滑动一位， 并将滑动后的数据送 到解扰和解码单元。在滑动调整结束之后，读控制模块将 slip— done信号置位， 通知数据码块同步状态机滑动调整结束， 可以重新检测同步头。  The write control module rearranges the input 64-bit wdata into a 66-bit dout output to the read control module, and gives a valid data indication. The read control module buffers the dout data sent by the write control module for two clock cycles, and slides the output 66-bit rdata data to a high position each time the slip signal sent by the data block synchronization state machine is detected. And send the swept data to the descrambling and decoding unit. After the sliding adjustment is completed, the read control module sets the slip-done signal to notify the data block synchronization state machine that the sliding adjustment is over, and the synchronization header can be re-detected.
数据码块同步状态机是数据码块同步单元的主要功能部件， 其功能是检 测 rdata 的同步头的有效性， 当满足同步条件时， 置码块同步指示信号 block— lock为有效，否则当无效同步头的数量超过阔值时，启动数据釆样窗口 的滑动调整机制， 直至满足同步条件为止。 数据码块同步状态机的具体实现 方式如图 3所示， 包括以下步骤： The data block synchronization state machine is the main functional component of the data block synchronization unit, and its function is to detect the validity of the synchronization header of rdata. When the synchronization condition is satisfied, the block synchronization indication signal block_lock is valid, otherwise it is invalid. When the number of sync headers exceeds the threshold, the data sample window is started. The sliding adjustment mechanism until the synchronization condition is met. The specific implementation of the data block synchronization state machine is shown in FIG. 3, and includes the following steps:
步骤 301： 当数据有效指示信号 wen有效且 signal— ok有效时， 进入初始 化状态， 将同步头计数器 sh—cnt和无效同步头计数器 invalid— sh—cnt清零， 并 且将 block— lock置为无效；  Step 301: When the data valid indication signal wen is valid and signal_ok is valid, enter an initialization state, clear the synchronization header counter sh_cnt and the invalid synchronization header counter invalid_sh_cnt, and set block_lock to be invalid;
步骤 302: 进入同步头检测状态， 检测当前 66-bit数据 rdata的同步头是 否有效；若为有效同步头， 同步头计数器 sh—cnt计数值加 1 ,跳转到步骤 303; 若为无效同步头， 同步头计数器 sh—cnt和无效同步头计数器 invalid— sh—cnt的 计数值均加 1 , 跳转到步骤 304;  Step 302: Enter a synchronization header detection state, check whether the synchronization header of the current 66-bit data rdata is valid; if it is a valid synchronization header, the synchronization header counter sh_cnt count value is incremented by one, and the process proceeds to step 303; if it is an invalid synchronization header , the synchronization header counter sh_cnt and the invalid synchronization header counter invalid_sh_cnt count value is increased by 1, to jump to step 304;
同步头有效性的判定条件是： 若 rdata[l]与 rdata[0]不同， 即两者取异或 运算结果为 1 , 则认为是有效同步头， 对同步头有效指示 sh— valid置位； 否则 为无效同步头， sh— valid清零。  The determination condition of the validity of the synchronization header is: If rdata[l] is different from rdata[0], that is, the difference between the two is 1 and it is considered to be a valid synchronization header, and the synchronization header is effectively indicated by sh_ valid; Otherwise it is an invalid sync header and sh_active is cleared.
步骤 303： 若同步头计数器 sh— cnt=64 , 且无效同步头计数器 invalid— sh—cnt<l 6, 此时满足 block— lock的产生条件， 置位 block— lock, 跳转 到步骤 302;  Step 303: If the synchronization header counter sh_cnt=64, and the invalid synchronization header counter invalid_sh_cnt<l6, at this time the block_lock generation condition is satisfied, the block_lock is set, and the process proceeds to step 302;
本实施方式中一个检测过程设置为检测 64个同步数据，在同步头计数器 sh_cnt=64, 且无效同步头计数器 invalid— sh—cnt=0时， 表示在一轮同步头检测 中， 不存在无效的同步头， 置位 block— lock。 在 sh— cnt=64, 0 < invalid— sh—cnt < 16时， 表明在 block— lock已经锁定的情况下， 检测到同步头无效， 但无效 同步头的数目不至于引起 block— lock进入未锁定状态， 此时跳转到步骤 302, 进行下一轮的同步头检测。  In the embodiment, a detection process is set to detect 64 synchronization data. When the synchronization header counter sh_cnt=64, and the invalid synchronization header counter invalid_sh_cnt=0, it means that there is no invalid in one round of synchronization header detection. Sync header, set block-lock. When sh_cnt=64, 0 < invalid_ sh—cnt < 16, it indicates that the sync header is invalid when the block-lock is locked, but the number of invalid sync headers does not cause block-lock to enter unlocked. State, then jump to step 302 to perform the next round of sync header detection.
若同步头计数器 sh— cnt<64 , 且 invalid— sh—cnt<l 6 , 则跳转到步骤 302 , 进行本轮的下一次同步头检测。 步骤 304: 若 invalid— sh—cnt等于 16, 或 block— lock信号无效， 则跳转到 步骤 305 , 进行滑动调整；  If the sync header counter sh_cnt<64, and invalid_sh_cnt<l6, then jump to step 302 to perform the next sync header detection of the current round. Step 304: If invalid_sh_cnt is equal to 16, or the block_lock signal is invalid, then go to step 305 to perform sliding adjustment;
步骤 305: 将 slip置位， 调用滑动控制模块将 66-bit数据釆样窗口向高位 移动一位， 当调整完毕之后， 即检测到 slip— done有效时， 跳转到步骤 306; 步骤 306: 将 sh—cnt和 invalid— sh—cnt清零， 跳转到步骤 302, 进行下一 轮的同步头循环检测； Step 305: Set the slip to set the slide control module to move the 66-bit data sampling window to the upper position by one bit. When the adjustment is completed, that is, when the slip-do is detected to be valid, the process proceeds to step 306; Step 306: Sh—cnt and invalid—sh—cnt is cleared, go to step 302, proceed to the next Synchronous head loop detection of the wheel;
滑动控制模块的作用是当 block— lock无效或者当无效同步头数目等于 16 时， 将 66-bit的数据釆样窗口进行滑动， 丟弃 2bit的数据。  The function of the sliding control module is to slide the 66-bit data sampling window and discard the 2-bit data when the block-lock is invalid or when the number of invalid synchronization headers is equal to 16.
由于读控制模块和写控制模块工作的时钟频率相同， 输入的数据 wdata 位宽为 64-bit, 而输出的数据 rdata位宽为 66-bit, 因此每 33个时钟周期输出 数据 rdata将有一个时钟周期数据无效， 写控制模块产生数据有效指示 wen, 并将 64-bit的输入数据 wdata重新组合为 66-bit的 dout, 送到读控制模块，如 图 4所示， 写控制模块的具体实施步骤包括：  Since the read control module and the write control module operate at the same clock frequency, the input data wdata bit width is 64-bit, and the output data rdata bit width is 66-bit, so the output data rdata will have one clock every 33 clock cycles. The cycle data is invalid, the write control module generates a valid data indication, and recombines the 64-bit input data wdata into a 66-bit dout, and sends it to the read control module, as shown in Figure 4, the specific implementation steps of the write control module. Includes:
步骤 401 , 当检测到读控制模块送来的 drop— flag时， 表明需要将输入的 wdata丟弃两个 bit, 重新整理为 66-bit数据输出给读控制模块， 跳转到步骤 403; 若没有检测到 drop— flag, 则跳转到步骤 402;  Step 401: When the drop-flag sent by the read control module is detected, it indicates that the input wdata needs to be discarded by two bits, and is rearranged into 66-bit data output to the read control module, and the process proceeds to step 403; If drop-flag is detected, then go to step 402;
步骤 402, 设置步进计数器计数值（step ) , 取值范围为 0到 32, 对 step 增加 1 , 并跳转到步骤 404, 若 step>32, 则 step清零， 跳转到步骤 404; 步进计数器的溢出值为 32。  Step 402, setting a step counter count value (step), the value range is 0 to 32, adding 1 to step, and jumping to step 404, if step>32, then step is cleared, and the process proceeds to step 404; The overflow value of the advance counter is 32.
ste 每步进 1 , 就有一拍 66-bit的数据 dout输出， 输出的 66-bit数据 dout 由当前的 64-bit输入数据 wdata和上一个时钟周期保存的数据 holdvect构成。 若 step步进 2 , 则输出的数据 dout将丟弃掉 holdvect的高两个 bit。  Ste Step 1 has a 66-bit data dout output, and the output 66-bit data dout consists of the current 64-bit input data wdata and the data holdvect saved in the previous clock cycle. If step is 2, the output data dout will discard the upper two bits of holdvect.
步骤 403 , step增加 2, 跳转到步骤 404, 若 step>31 , 则 step清零， 执行 步骤 404;  Step 403, step increments 2, jumps to step 404, if step>31, then step is cleared, step 404 is performed;
步骤 404, 判断当前的 step值是否为 0, 若为 0, 则跳转到步骤 405; 若 当前 step不为 0 , 则跳转到步骤 406；  Step 404, it is determined whether the current step value is 0, if it is 0, then jump to step 405; if the current step is not 0, then jump to step 406;
步骤 405 , 将输入的 64-bit的 wdata保存到 holdvect (向量保存寄存器 ) 中， 且该时钟周期， 不输出数据 dout, 数据有效指示 wen无效；  Step 405: Save the input 64-bit wdata to the holdvect (vector save register), and the data cycle does not output the data dout, and the valid data indication is invalid;
Holdvect的位宽为 64bit, 其作用是保存输入的 wdata。  Holdvect has a bit width of 64 bits, which is used to hold the input wdata.
步骤 406, 判断 step是否等于 32, 若 step=32, 则跳转到步骤 407; 否则 跳转到步骤 408;  Step 406, determining whether step is equal to 32, if step=32, then jumping to step 407; otherwise, jumping to step 408;
步骤 407 ,输出的 66-bit数据 dout由当前的 wdata[63:0]和上一拍 holdvect 中保存的 wdata[63:62]构成， 即： Dout={wdata[63:0],holdvect[l :0]]} , 且数据 有效指示 wen置位； Step 407, the output 66-bit data dout is composed of the current wdata[63:0] and the wdata[63:62] saved in the previous beat holdvect, namely: Dout={wdata[63:0], holdvect[l :0]]} , and the data Valid indication wen set;
步骤 408, 输出数据 dout为： Dout={wdata[2k-l :0],holdvect[65-2k:0]]} ; holdvect为： holdvect[63-2k:0]=wdata[63:2k]; holdvect[63:64-2k]=0, 且数据有 效指示 wen置位， k为 step当前值。  In step 408, the output data dout is: Dout={wdata[2k-l:0], holdvect[65-2k:0]]}; holdvect is: holdvect[63-2k:0]=wdata[63:2k]; Holdvect[63:64-2k]=0, and the data valid indicates that wen is set, and k is the current value of step.
图 5为上述步骤更直观的表述， 图 5左侧为 holdvect, 右侧为 dout, 每一 行对应一个 step,每一个 step中， dout的低位由上一个时钟周期保存的 holdvect 赋值， dout的剩余的高位则由当前时钟周期的 wdata的低位赋值。 同时， 将 wdata剩余的高位保存到 holdvect中， 以便下一个时钟周期使用。从图中可以 看出， 若 step增加 2, 则输出的 dout将会丟弃掉 holdvect的高两位， 剩余 bit 由当前 wdata赋值。  Figure 5 is a more intuitive representation of the above steps. The left side of Figure 5 is holdvect, the right side is dout, and each line corresponds to a step. In each step, the low order of dout is assigned by the holdvect saved in the previous clock cycle, and the remaining of dout The upper bit is assigned by the lower bits of wdata of the current clock cycle. At the same time, save the remaining high bits of wdata to holdvect for use in the next clock cycle. As can be seen from the figure, if step is increased by 2, the output dout will discard the upper two bits of holdvect, and the remaining bits are assigned by the current wdata.
读控制模块的功能是将输入的 dout数据緩存两个时钟周期， 保存到 132 比特的 stage (输入数据保存寄存器） 中， 即 stage[131 :66]=stage[65:0] , stage[65:0]=dout, 并在数据码块同步状态机每次调用滑动控制模块时， 将丟 弃标志（drop— flag )置为有效， 实现釆样窗口的移位， 并在滑动调整完毕后， 置位 slip— done, 通知数据码块同步状态机调整完毕， 具体实现步骤如图 6所 示， 包括：  The function of the read control module is to buffer the input dout data for two clock cycles and save it to the 132-bit stage (input data save register), ie stage[131 :66]=stage[65:0] , stage[65: 0]=dout, and each time the data block synchronization state machine calls the sliding control module, the drop flag is set to be valid, the shift of the sample window is realized, and after the sliding adjustment is completed, Bit slip-done, the data block synchronization state machine is adjusted, and the specific implementation steps are as shown in FIG. 6, including:
步骤 601 , 设置 odd (奇偶标志） ， 每次调用滑动控制模块时， odd均翻 转一次， 当 odd 标志为 0 时， rdata=stage[66:l] ; 当 odd 标志为 1 时， rdata=stage[65:0];  Step 601, setting odd (parity flag), each time the sliding control module is called, odd is flipped once, when the odd flag is 0, rdata=stage[66:l]; when the odd flag is 1, rdata=stage[ 65:0];
步骤 602 , 当数据有效， 数据码块同步状态机有滑动请求时， 检测 odd 的值， 若为 odd=l , 跳转到步骤 603; 否则跳转到步骤 608;  Step 602, when the data is valid, the data block synchronization state machine has a sliding request, the value of odd is detected, if odd = l, the process proceeds to step 603; otherwise, the process proceeds to step 608;
步骤 603 , 将 odd取反， 执行步骤 604;  Step 603, inverting the odd, step 604;
步骤 604, 无 drop— flag标志， 写控制模块的步进计数器 step=step+l , 执 行步骤 605;  Step 604, there is no drop-flag flag, the step counter of the write control module step=step+l, step 605 is performed;
步骤 605 , dout由上个节拍保存的 holdvect和该节拍的 wdata组合而成， 即： dout={wdata[2k-l :0] , holdvect[65-2k:0]} , k为 step当前值，执行步骤 606; 步骤 606 , 緩存两个周期的 dout , 即 stage[65:0]=stage[131 :66] , stage[131 :66]=dout, 执行步骤 607; 步骤 607 , rdata的取值由 stage[65:0]滑动一位到 stage[66: 1] ,从而实现 rdata 向高位滑动一位的功能， 执行步骤 613。 Step 605, dout is composed of the holdvect saved by the last beat and the wdata of the beat, that is: dout={wdata[2k-l:0] , holdvect[65-2k:0]}, k is the current value of step, Step 606; Step 606, buffering two periods of dout, that is, stage[65:0]=stage[131:66], stage[131:66]=dout, performing step 607; In step 607, the value of rdata is slid from the stage[65:0] to the stage[66:1], so that the function of rdata sliding to the upper position is performed, and step 613 is performed.
步骤 608, 将 odd取反， 并置位 drop— flag, 通知写控制模块丟弃 holdvect 的高两位， 执行步骤 609;  Step 608, inverting odd, and set drop_flag, informing the write control module to discard the upper two bits of holdvect, step 609;
步骤 609,检测到 drop— flag标志，写控制模块的步进计数器 step=step+2, 执行步骤 610;  Step 609, detecting the drop_flag flag, writing the step counter of the control module step=step+2, performing step 610;
步骤 610, 丟弃 holdvect的高两位， 缺少的两位由 wdata补齐， 组合出 66-bit的 dout, 即： dout={wdata[2k+3:0] , holdvect[61-2k:0]} , k为 step未力口 2 时的值， 执行步骤 611 ;  In step 610, the upper two bits of the holdvect are discarded, and the missing two bits are complemented by wdata, and the 66-bit dout is combined, namely: dout={wdata[2k+3:0], holdvect[61-2k:0] }, k is the value when the step is not 2, and step 611 is performed;
步骤 611 , 緩存两个周期的 dout , 即 stage[65:0]=stage[131 :66] , stage[131 :66]=dout, 执行步骤 612;  Step 611, buffering two periods of dout, that is, stage[65:0]=stage[131:66], stage[131:66]=dout, performing step 612;
步骤 612, rdata的取值由 stage[66:l]滑动一位到 stage[65:0] , 在该步骤由 于 dout删除了 holdvect的高两位，而 rdata取值又向 stage的低位滑动了一位， 这样就实现了 rdata取值向高位滑动一位的功能， 执行步骤 613;  In step 612, the value of rdata is swiped from stage[66:l] to stage[65:0]. In this step, duet is deleted the upper two bits of holdvect, and the value of rdata is slid to the lower level of stage. Bit, thus achieving the function of rdata value sliding to a high bit, step 613;
步骤 613 , 置位 slip— done, 调整完毕。  Step 613, set slip- done, the adjustment is completed.
以上所述， 仅为本发明的较佳实施例而已， 并非用于限定本发明的保护 范围， 凡在本发明的精神和原则之内所作的任何修改、 等同替换和改进等， 均应包含在本发明的保护范围之内。 The above description is only for the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included. Within the scope of protection of the present invention.
工业实用性 Industrial applicability
本发明实施例通过数据码块同步状态机和滑动控制模块， 实现从输入的 64-bit数据中， 同步出 66-bit的数据码块， 并给出码块锁定指示， 实现数据码 块同步的功能。  In the embodiment of the invention, the data block synchronization state machine and the sliding control module realize that 66-bit data code blocks are synchronized from the input 64-bit data, and the code block locking indication is given, and the data code block synchronization is realized. Features.

Claims

权 利 要 求 书 Claim
1、 一种数据码块同步的方法， 包括： 1. A method for synchronizing data blocks, comprising:
从输入数据中釆样同步数据，对釆样得到的同步数据的同步头进行检测， 在检测过程中， 若检测到的无效同步头的数量未达到阔值， 则配置码块同步 指示信号为有效， 通知解码单元进行解码操作。  Synchronizing data from the input data is detected, and the synchronization header of the synchronization data obtained by the sample is detected. In the detection process, if the number of detected invalid synchronization headers does not reach a threshold, the configuration code block synchronization indication signal is valid. , the decoding unit is notified to perform a decoding operation.
2、 如权利要求 1所述的方法，其中， 所述从输入数据中釆样同步数据的 步骤包括： 2. The method of claim 1, wherein the step of synchronizing data from the input data comprises:
对所述输入数据进行位宽转换， 通过数据釆样窗口从位宽转换后的数据 中釆样所述同步数据。  The input data is subjected to bit width conversion, and the synchronous data is sampled from the bit width converted data through the data sampling window.
3、 如权利要求 2所述的方法，其中， 所述对所述输入数据进行位宽转换 的步骤包括： 3. The method of claim 2, wherein the step of performing bit width conversion on the input data comprises:
设置步进计数器， 在该步进计数器的计数值为 0 时， 将所述输入数据 (wdata)保存到向量保存寄存器 (holdvect)中， 且不输出所述位宽转换后的数据 (dout), 并设置数据有效指示为无效。  Setting a step counter, when the count value of the step counter is 0, saving the input data (wdata) into a vector save register (holdvect), and not outputting the bit-width converted data (dout), And set the data valid indication to be invalid.
4、 如权利要求 3所述的方法， 其中， 该方法还包括： 4. The method of claim 3, wherein the method further comprises:
在所述步进计数器的计数值大于 0 且未达到溢出值时， 输出所述 dout={wdata[2k-l :0],holdvect[65-2k:0]}； 所述 holdvect 中保存的数据为： holdvect[63-2k:0]=wdata[63 :2k]； holdvect[63:64-2k]=0, 其中， k为所述步进计 数器的当前计数值， 并设置所述数据有效指示为有效。  When the count value of the step counter is greater than 0 and the overflow value is not reached, the dout={wdata[2k-l:0], holdvect[65-2k:0]} is output; the data saved in the holdvect It is: holdvect[63-2k:0]=wdata[63 :2k]; holdvect[63:64-2k]=0, where k is the current count value of the step counter, and the data valid indication is set To be effective.
5、 如权利要求 3所述的方法， 其中， 该方法还包括： 5. The method of claim 3, wherein the method further comprises:
在所述步进计数器的计数值达到溢出值时， 输出 所述 dout={wdata[63:0],holdvect[l :0]]} , 并设置所述数据有效指示为有效。  When the count value of the step counter reaches the overflow value, the dout={wdata[63:0], holdvect[l:0]]} is output, and the valid indication of the data is set to be valid.
6、 如权利要求 4所述的方法， 其中， 所述检测过程中， 若检测到的无效 同步头的数量达到阔值， 或所述码块同步指示信号为无效， 则对所述数据釆 样窗口进行滑动调整， 对滑动调整后的数据釆样窗口釆样的同步数据的同步 头进行检测。 The method according to claim 4, wherein, in the detecting process, if the number of detected invalid sync headers reaches a threshold value, or the code block synchronization indication signal is invalid, then the data is sampled The window is slidably adjusted to detect the sync header of the sync data of the slide-adjusted data sample window.
7、 如权利要求 6所述的方法，其中， 所述滑动调整为将所述数据釆样窗 口向所述位宽转换后的数据的高位滑动。 7. The method of claim 6, wherein the sliding adjustment is to slide the data sample window to a high level of the data after the bit width conversion.
8、 如权利要求 7所述的方法，其中， 所述将所述数据釆样窗口向所述位 宽转换后的数据的高位滑动的步骤包括： 8. The method of claim 7, wherein the step of sliding the data sample window to a high level of the bit-converted data comprises:
设置奇偶标志 (odd),将两个时钟周期的 dout緩存到输入数据保存寄存器 Set the parity flag (odd) to buffer the dout of two clock cycles to the input data save register
(stage)中， 检测所述 odd的取值， 该 odd的取值在第一值与第二值之间翻转， 若该 odd取第一值，则将所述数据釆样窗口在所述 stage中的位置向高位滑动 一位， 并翻转所述 oddd的取值。 (stage), detecting the value of the odd, the value of the odd is flipped between the first value and the second value, if the odd takes the first value, the data sampling window is at the stage The position in the middle slides one bit to the high position and flips the value of the oddd.
9、 如权利要求 8所述的方法， 其中， 该方法还包括： 9. The method of claim 8, wherein the method further comprises:
若所述 odd取第二值， 则对所述 dout丟弃 holdvect 的高两位， 所述 dout={wdata[2k+3:0] , holdvect[61-2k:0]} , 其中， k为所述步进计数器的当前 计数值， 并将所述数据釆样窗口在所述 stage中的位置向低位滑动一位， 并翻 转所述 oddd的取值。  If the odd takes the second value, discard the upper two bits of the holdvect for the dout, the dout={wdata[2k+3:0], holdvect[61-2k:0]}, where k is The current counter value of the step counter, and sliding the position of the data sampling window in the stage to a lower position, and flipping the value of the oddd.
10、 如权利要求 1所述的方法， 其中， 所述对釆样得到的同步数据的同 步头进行检测的步骤包括： 10. The method according to claim 1, wherein the step of detecting the synchronization header of the synchronization data obtained by the sample comprises:
检测所述同步数据的低两位是否相同， 若不相同， 则为有效同步头； 否 则， 为无效同步头。  Detect whether the lower two bits of the synchronization data are the same, if not, the valid synchronization header; otherwise, the invalid synchronization header.
11、 一种数据码块同步的装置， 包括： 数据码块同步单元和滑动控制模 块， 其中： 11. A device for synchronizing data blocks, comprising: a data block synchronization unit and a sliding control module, wherein:
所述滑动控制模块设置为： 从输入数据中釆样同步数据；  The sliding control module is configured to: synchronize data from the input data;
所述数据码块同步单元设置为： 对所述滑动控制模块釆样得到的同步数 据的同步头进行检测， 在检测过程中， 若检测到的无效同步头的数量未达到 阔值， 则配置码块同步指示信号为有效， 通知解码单元进行解码操作。  The data block synchronization unit is configured to: detect a synchronization header of the synchronization data obtained by the sliding control module, and if the number of detected invalid synchronization headers does not reach a threshold during the detection process, the configuration code The block synchronization indication signal is valid, and the decoding unit is notified to perform a decoding operation.
12、 如权利要求 11所述的装置，其中， 所述滑动控制模块包括写控制模 块和读控制模块， 其中： 12. The apparatus of claim 11, wherein the slip control module comprises a write control module and a read control module, wherein:
所述写控制模块设置为： 对所述输入数据进行位宽转换； 所述读控制模块设置为： 通过数据釆样窗口从位宽转换后的数据中釆样 所述同步数据。 The write control module is configured to: perform bit width conversion on the input data; The read control module is configured to: sample the synchronous data from the data converted by the bit width through the data sampling window.
13、 如权利要求 12所述的装置，其中， 所述写控制模块对所述输入数据 进行位宽转换包括： 13. The apparatus of claim 12, wherein the bit control conversion of the input data by the write control module comprises:
设置步进计数器， 在该步进计数器的计数值为 0 时， 将所述输入数据 Setting a step counter, when the count value of the step counter is 0, the input data is
(wdata)保存到向量保存寄存器 (holdvect)中， 且不输出所述位宽转换后的数据 (dout), 并设置数据有效指示为无效； (wdata) is saved in the vector save register (holdvect), and the bit-converted data (dout) is not output, and the data valid indication is set to be invalid;
在所述步进计数器的计数值大于 0 且未达到溢出值时， 所述 dout={wdata[2k-l :0],holdvect[65-2k:0]}； 所述 holdvect 中保存的数据为： holdvect[63-2k:0]=wdata[63 :2k]； holdvect[63:64-2k]=0, 其中， k为所述步进计 数器的当前计数值， 并设置所述数据有效指示为有效；  When the count value of the step counter is greater than 0 and the overflow value is not reached, the dout={wdata[2k-l:0], holdvect[65-2k:0]}; the data saved in the holdvect is Holdvect[63-2k:0]=wdata[63 :2k]; holdvect[63:64-2k]=0, where k is the current count value of the step counter, and the valid indication of the data is set to Effective
在 所 述 步 进计 数 器 的 计 数值 达到 溢 出 值 时 ， 所 述 dout={wdata[63:0],holdvect[l :0]]} , 并设置所述数据有效指示为有效。  When the count value of the step counter reaches the overflow value, the dout={wdata[63:0], holdvect[l:0]]}, and the valid indication of the data is set to be valid.
14、 如权利要求 13所述的装置， 其中， 14. The apparatus according to claim 13, wherein
所述数据码块同步单元还设置为： 在所述检测过程中， 若检测到的无效 同步头的数量达到阔值， 或所述码块同步指示信号为无效， 则调用所述读控 制模块对所述数据釆样窗口进行滑动调整， 对滑动调整后的数据釆样窗口釆 样的同步数据的同步头进行检测。  The data block synchronization unit is further configured to: in the detecting process, if the number of detected invalid synchronization headers reaches a threshold, or the code block synchronization indication signal is invalid, the read control module is invoked The data sampling window performs sliding adjustment to detect a synchronization header of the synchronized data of the sliding adjusted data sample window.
15、 如权利要求 14所述的装置， 其中， 15. The apparatus according to claim 14, wherein
所述读控制模块还设置为： 对对所述数据釆样窗口进行滑动调整， 该滑 动调整为将所述数据釆样窗口向所述位宽转换后的数据的高位滑动， 该向所 述位宽转换后的数据的高位滑动的步骤包括：  The read control module is further configured to: perform sliding adjustment on the data sampling window, the sliding adjustment is to slide the data sampling window to a high position of the data converted by the bit width, where the bit is The steps of the high-order sliding of the wide converted data include:
设置奇偶标志 (odd),将两个时钟周期的 dout緩存到输入数据保存寄存器 (stage)中， 检测所述 odd的取值， 该 odd的取值在第一值与第二值之间翻转， 若该 odd取第一值，则将所述数据釆样窗口在所述 stage中的位置向高位滑动 一位， 并将所述 odd进行翻转。  Setting an odd-odd flag (odd), buffering the dout of two clock cycles into an input data save register (stage), detecting the value of the odd, the value of the odd is flipped between the first value and the second value, If the odd takes the first value, the position of the data sample window in the stage is slid one bit to the upper position, and the odd is flipped.
16、 如权利要求 15所述的装置， 其中， 所述读控制模块还设置为： 在所述 odd取第二值时， 调用所述写控制模 块对所述 dout丟弃 holdvect的高两位， 并将所述数据釆样窗口在所述 stage 中的位置向低位滑动一位， 并将所述 odd进行翻转； 16. The apparatus according to claim 15, wherein The read control module is further configured to: when the odd value takes the second value, invoking the write control module to discard the upper two bits of the holdvect for the dout, and the data sampling window is in the stage The position slides one bit to the lower position and flips the odd;
所述写控制模块还设置为： 在所述读控制模块调用时， 取所述 dout={wdata[2k+3:0] , holdvect[61-2k:0]} , 其中， k为所述步进计数器的当前 计数值。  The write control module is further configured to: when the read control module invokes, take the dout={wdata[2k+3:0], holdvect[61-2k:0]}, where k is the step Enter the current count value of the counter.
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