WO2012057608A1 - A method for producing metal-oxide-semiconductor (mos) capacitor - Google Patents

A method for producing metal-oxide-semiconductor (mos) capacitor Download PDF

Info

Publication number
WO2012057608A1
WO2012057608A1 PCT/MY2011/000178 MY2011000178W WO2012057608A1 WO 2012057608 A1 WO2012057608 A1 WO 2012057608A1 MY 2011000178 W MY2011000178 W MY 2011000178W WO 2012057608 A1 WO2012057608 A1 WO 2012057608A1
Authority
WO
WIPO (PCT)
Prior art keywords
oxide
semiconductor
producing
metal
capacitor
Prior art date
Application number
PCT/MY2011/000178
Other languages
French (fr)
Inventor
Kuan Yew Cheong
Zainovia Lockman
Zainuriah Hassan
Hock Jin Quah
Way Foong Lim
Original Assignee
Universiti Sains Malaysia
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Universiti Sains Malaysia filed Critical Universiti Sains Malaysia
Publication of WO2012057608A1 publication Critical patent/WO2012057608A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/92—Capacitors having potential barriers
    • H01L29/94—Metal-insulator-semiconductors, e.g. MOS
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/02—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by thermal decomposition
    • C23C18/12—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by thermal decomposition characterised by the deposition of inorganic material other than metallic material
    • C23C18/1204—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by thermal decomposition characterised by the deposition of inorganic material other than metallic material inorganic material, e.g. non-oxide and non-metallic such as sulfides, nitrides based compounds
    • C23C18/1208—Oxides, e.g. ceramics
    • C23C18/1216—Metal oxides
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/02—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by thermal decomposition
    • C23C18/12—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by thermal decomposition characterised by the deposition of inorganic material other than metallic material
    • C23C18/1229—Composition of the substrate
    • C23C18/1245—Inorganic substrates other than metallic
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/02—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by thermal decomposition
    • C23C18/12—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by thermal decomposition characterised by the deposition of inorganic material other than metallic material
    • C23C18/125—Process of deposition of the inorganic material
    • C23C18/1279—Process of deposition of the inorganic material performed under reactive atmosphere, e.g. oxidising or reducing atmospheres
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/02—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by thermal decomposition
    • C23C18/12—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by thermal decomposition characterised by the deposition of inorganic material other than metallic material
    • C23C18/125—Process of deposition of the inorganic material
    • C23C18/1283—Control of temperature, e.g. gradual temperature increase, modulation of temperature
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02192—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing at least one rare earth metal element, e.g. oxides of lanthanides, scandium or yttrium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour

Definitions

  • the present invention relates to a method for producing metal-oxide- semiconductor device using a gate oxide with high dielectric constant (k) which is being integrated in the semiconductor.
  • Gallium nitride possesses excellent properties such as wide bandgap (3.4 eV), large critical electric field (3 MV/cm), high electron mobility, and good thermal conductivity and stability, which are suitable for high power and high temperature applications in metal-oxide-semiconductor (MOS) based devices.
  • MOS metal-oxide-semiconductor
  • insulating layer sandwiched between metal and semiconductor or typically termed as gate oxide with thickness more than 50 nm is required to sustain a high transverse electric field.
  • Thick native oxide of GaN Ga 2 0 3
  • k dielectric constant
  • Si0 2 possessed low-k value of 3.9 proportional to GaN (k 9) has caused an electric field imposed in Si0 2 to be approximately 2.3 times higher than in GaN.
  • the excellent properties of GaN cannot be fully exploited due to the operation of the device at an electric field lower than the GaN breakdown field aiming to prevent the breakdown of the Si0 2 . Therefore, there is a need for a high-k gate oxide on GaN to assist in operating the MOS based device at the breakdown field of GaN.
  • high-k gate oxide electric field imposed in the gate oxide is being suppressed by a factor of (3.9/k) in contrast to Si0 2 on similar substrate. In this way, gate oxide reliability issues in regard to Si0 2 on GaN may be counteracted.
  • the present invention relates to a gate oxide, cerium oxide, with high dielectric constant (k) that is being integrated in a semiconductor and a method for producing metal-oxide-semiconductor device using the gate oxide with high dielectric constant (k).
  • the present invention relates to a method for producing the oxide-semiconductor. The oxide-semiconductor is then subjected to an etching, evaporating and photolithography process to produce metal-oxide-semiconductor capacitor.
  • the method for producing the oxide-semiconductor includes the steps of:
  • step (iii) performing a post deposition annealing of the wet film obtained from step (iii) under a flow of oxygen gas or under a flow of nitrous oxide gas at a temperature range of 400°C to 1000°C;
  • step (iii) cooling of the annealed film obtained from step (iii) to room temperature.
  • the method for producing a metal-oxide-semiconductor capacitor includes the steps of:
  • step (iii) performing a post deposition annealing on the wet film obtained from step (iii) under a flow of oxygen gas or under a flow of nitrous oxide gas at a temperature range of 400°C to 1000°C;
  • step (iv) cooling of the annealed film obtained from step (iii) to room temperature to produce oxide-semiconductor; v) etching the film obtained from step (iv);
  • cerium containing precursor mentioned in both the methods above is prepare using the steps of:
  • step (iv) allowing the precursor obtained from step (iv) to cool down to room temperature.
  • the oxide is cerium oxide.
  • the semiconductor is Silicon (Si)-doped Gallium Nitride (GaN) epitaxial layer grown on sapphire substrate.
  • the semiconductor has a doping concentration of 1.0 x 10 18 cm “3 to 9.0 x 10 18 cm “3 .
  • the Si-doped GaN is separated from sapphire substrate by a thin layer.
  • the thin layer is A1N buffer layer.
  • the oxide- semiconductor has a thickness in a range of 52-70nm.
  • the wet film obtained from the spin coating is Ce0 2 film.
  • the post deposition annealing of the wet film under a flow of oxygen gas is at a flow rate of 100-200ml/min.
  • the nitrous oxide gas flow rate is 100-200ml/min.
  • the post deposition annealing is performed at a heating rate of 5°C/min.
  • the cooling of the annealed film is performed at a cooling rate of 5°C/min.
  • the spin coating of the cerium containing precursor onto the semiconductor is done at a spinning rate of 3000-5000rpm and spinning time of 30-45 seconds.
  • the oxide- semiconductor produced by post deposition annealing under the flow of oxygen gas provides electric breakdown field of 5.3 MV/cm.
  • the oxide-semiconductor produced by post deposition annealing under the flow of nitrous oxide gas provides electric breakdown field of 6.3 MV/cm.
  • the etching of the film in step (v) is done using a buffer solution of Hydrogen
  • HF Fluoride
  • H 2 0 water
  • a layer of aluminum is evaporated on the film obtained from step (v) using thermal evaporation.
  • the metal- oxide-semiconductor capacitor obtained from step (vi) is patterned by photolithography process.
  • Figure 1 shows the comparison of current density-breakdown field (J-E) characteristics among high thick oxides deposited on Gallium nitride (GaN) substrate and the post deposition annealed cerium oxide (Ce0 2 ) on GaN substrate at 1000°C under oxygen gas flow.
  • J-E current density-breakdown field
  • Figure 2 shows current density-breakdown field (J-E) characteristics of the post deposition annealed cerium oxide (Ce0 2 ) on Gallium nitride (GaN) substrate at temperature 400°C -1000°C under oxygen gas flow;
  • Figure 3 shows the structure of the oxide-semiconductor;
  • Figure 4 shows the Dj t vs Ec-E curve of the post deposition annealed cerium oxide (Ce0 2 ) on Gallium nitride (GaN) substrate at temperature 400°C -1000°C under oxygen gas flow
  • Figure 5 shows the X-ray diffractographs of Metal-Organic-Decomposed cerium oxide (Ce0 2 ) films annealed on Gallium nitride (GaN) substrate in N 2 0 and 0 2 ambient at 1000°C in comparison to bare GaN sample;
  • Figure 6 shows a typical FESEM (Field Emission Scanning Microscopy) image of bare Gallium nitride (GaN) with two dimensional Atomic Force Microscope (AFM) inset;
  • FESEM Field Emission Scanning Microscopy
  • Figure 6 (b) shows a typical FESEM (Field Emission Scanning Microscopy) image of post deposition annealed cerium oxide (Ce0 2 ) on Gallium nitride (GaN) substrate at 1000°C under N 2 0 ambient with two dimensional Atomic Force Microscope (AFM) inset;
  • FESEM Field Emission Scanning Microscopy
  • Figure 6 (c) shows a typical FESEM (Field Emission Scanning Microscopy) image of post deposition annealed cerium oxide (Ce0 2 ) on Gallium nitride (GaN) substrate at 1000°C under 0 2 ambient with two dimensional Atomic Force Microscope (AFM) inset;
  • Figure 7 shows leakage current-electric breakdown field (J-E) characteristics of post deposition annealed cerium oxide (Ce0 2 ) on Gallium nitride (GaN) substrate at 1000°C under N 2 0 and 0 2 ambient;
  • Figure 8 shows a comparison of interface-trap density of post deposition annealed cerium oxide (Ce0 2 ) on Gallium nitride (GaN) substrate at 1000°C under N 2 0 and 0 2 ambient.
  • Inset of the figure 8 shows a comparison of high frequency capacitance-voltage (C-V) results of post deposition annealed Ce0 2 on GaN substrate at 1000°C under
  • the present invention relates to a method for producing metal-oxide- semiconductor using a gate oxide with high dielectric constant (k) which is being integrated in a semiconductor.
  • the semiconductor used in the present invention is Si- doped (n-type) Gallium nitride GaN epitaxial layer grown on sapphire substrate.
  • the present invention firstly relates to a method for producing the oxide-semiconductor. The oxide-semiconductor is then subjected to an etching, evaporating and photolithography process to produce metal-oxide-semiconductor capacitor.
  • Metal-organic-decomposition (MOD) technique is used to derive cerium oxide (Ce0 2 ) precursor.
  • the MOD technique includes the steps of: i) dissolving 1 mole of cerium (III) acetylacetonate hydrate in 30 moles of methanol and 42 moles of acetic acid to form a mixture;
  • the amount of cerium (III) acetylacetonate hydrate, methanol and acetic acid used in the present invention is 1.0936g, 3ml and 6ml respectively to form a precursor with 0.0025 moles.
  • the cerium oxide precursor obtained from the MOD technique is transformed into a wet film, i.e. Ce0 2 film, by spin-coating the precursor on a semiconductor, i.e. Si-doped (n-type) GaN epitaxial layer grown on sapphire substrate at a spinning rate of 3000-5000 rpm and a spinning time of 30-45 seconds at room temperature, 300K.
  • the semiconductor has a doping concentration of 1.0 x 10 18 cm "3 to 9.0 x 10 18 cm "3 .
  • the Si-doped GaN is separated from sapphire substrate by a thin layer.
  • the thin layer is AIN buffer layer.
  • the AIN buffer layer reduces lattice mismatch between the GaN and the sapphire.
  • the wet film, i.e. Ce0 2 film, obtained from spin-coating is inserted into a horizontal tube furnace and post-deposition annealing (PDA) is performed at different temperatures, ranging from 400°C to 1000°C in oxygen gas flow at 100- 200ml/min. Dwelling time of 15 minutes is employed for each specific temperature. Heating rate of the PDA is 5°C/min. Thereafter, the annealed film is allowed to gradually cool down at a rate of 5°C/min to room temperature in oxygen gas flow of 100- 200ml/min.
  • PDA post-deposition annealing
  • each film with oxide thickness of (52-70nm) is estimated by an ellipsometer (L 116S) using a laser light source of 632.8 nm at five different locations on the film.
  • Metal-oxide-semiconductor (MOS) capacitors are then fabricated by selectively etching the annealed Ce0 2 film by using a buffer solution of Hydrogen fluoride (HF) and water (H 2 0) having a ratio of 1 : 1 respectively.
  • a layer of aluminum is then evaporated on the Ce0 2 film by using a thermal evaporator.
  • An area of capacitor is patterned by photolithography process. The area of the capacitor is depended on the industrial commercial needs.
  • Figure 4 shows interface trap density, D it , of the Ce0 2 film annealed at different temperatures, which was extracted by using Terman method. From the Figure 4, it is clear that the Ce0 2 film annealed at 1000°C has the lowest D it , followed by Ce0 2 film annealed at 800°C and 600°C. The highest D lt is obtained by the Ce0 2 film annealed at 400°C.
  • the wet film i.e. Ce0 2 film
  • the wet film obtained from spin-coating of the precursor on Si-doped (n-type) GaN epitaxial layer grown on sapphire substrate is inserted into a horizontal tube furnace at room temperature and post-deposition annealing (PDA) is carried out by ramping up the temperature from 400°C to 1000 °C in nitrous oxide (N 2 0) gas flow of 100-200ml/min. Dwelling time of 15 minutes is employed for each specific temperature. Heating rate of the PDA is 5°C/min. Thereafter, the annealed film is allowed to gradually cool down at a rate of 5°C/min to room temperature in N 2 0 gas flow of 100-200ml/min.
  • PDA post-deposition annealing
  • Figure 5 shows diffractographs of the annealed Ce0 2 film and annealed GaN (control sample) at 1000 °C in N 2 0 and 0 2 gas flow.
  • Broadness of GaN (004) diffraction peak (ICCD file no. 00-050-0792) of the annealed Ce0 2 film in N 2 0 gas flow is larger than the annealed Ce0 2 film in 0 2 gas flow but similar to the broadness of GaN, control sample.
  • Reason attributed to increment in broadness of the GaN (004) diffraction peak is decomposition of GaN wafer. This indicates that PDA in N 2 0 gas flow enables suppression of GaN decomposition.
  • 0 2 , N 2 , NO, and O are dissociated from N 2 0 gas, wherein the N 2 gas contributes to increase of nitrogen ambient partial pressure. The increment of nitrogen partial pressure may minimize decomposition of GaN surface.
  • Ce0 2 film annealed in 0 2 ambient has a higher intensity of Ce0 2 (400) diffraction peak.
  • XRD characterization manage to detect P-Ga 2 0 3 (200), (013), and (202) diffraction peaks (ICCD file no. 01-074-1776), indicating that oxidization of liquid Ga dissociated from solid GaN. It is noted from the Figure 5, the Ce0 2 film annealed in N 2 0 ambient acquired higher intensity of P-Ga 2 0 3 peaks than the Ce0 2 film annealed in 0 2 ambient.
  • Figure 6 (a), (b) and (c) show field-emission scanning electron microscopy (FESEM) images of bare GaN and the Ce0 2 film annealed in N 2 0 ambient and 0 2 ambient respectively.
  • Surface of bare GaN is very smooth as shown in Figure 6(a).
  • PDA field-emission scanning electron microscopy
  • rough annealed film surface is obtained due to decomposition of the GaN as shown in Figure 6(b)-6(c). It is perceived that surface of the Ce0 2 film annealed under N 2 0 ambient is covered with a more uniform size and number of protrusion compared to Ce0 2 film annealed under 0 2 ambient.
  • the Ce0 2 film annealed under N 2 0 ambient has a denser film when compared with the Ce0 2 film annealed under 0 2 ambient, which is supported by calculating film density of respective sample using Lorentz-Lorenz law.
  • Ellipsometer has been used to obtain average refractive index (n) value of the Ce0 2 film annealed under N 2 0 ambient and the Ce0 2 film annealed under 0 2 ambient.
  • the index (n) value is 2.37 and 2.23 for Ce0 2 film annealed under N 2 0 ambient and the Ce0 2 film annealed under 0 2 ambient respectively.
  • Typical leakage current density-electric field (J-E) plot for both Ce0 2 films annealed in N 2 0 and 0 2 ambient are shown in Figure 7.
  • PDA performed in N 2 0 ambient has played a vital role in enhancing the EB of the annealed Ce0 2 film to approximately 6.3 MV/cm if compared with Ce0 2 film annealed in 0 2 ambient, i.e. - 5.3 MV/cm.
  • larger leakage current density has been demonstrated by the Ce0 2 film annealed under N 2 0 ambient at low electric field.

Landscapes

  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Organic Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Inorganic Chemistry (AREA)
  • Thermal Sciences (AREA)
  • General Chemical & Material Sciences (AREA)
  • Computer Hardware Design (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

The present invention relates to a gate oxide, cerium oxide, with high dielectric constant (k) that is being integrated in a semiconductor and a method for producing metal-oxide-semiconductor device using the gate oxide with high dielectric constant (k). The gate oxide is being deposited on the semiconductor via post deposition annealing under 02 and N20 ambient. The semiconductor used in the present invention is Si-doped (n-type) Gallium nitride GaN epitaxial layer grown on sapphire substrate. The present invention firstly relates to a method for producing the oxide-semiconductor. The oxide- semiconductor is then subjected to an etching, evaporating and photolithography process to produce metal-oxide-semiconductor capacitor.

Description

A METHOD FOR PRODUCING METAL-OXIDE-SEMICONDUCTOR (MOS)
CAPACITOR
FIELD OF INVENTION
The present invention relates to a method for producing metal-oxide- semiconductor device using a gate oxide with high dielectric constant (k) which is being integrated in the semiconductor.
BACKGROUND OF THE INVENTION
Gallium nitride (GaN) possesses excellent properties such as wide bandgap (3.4 eV), large critical electric field (3 MV/cm), high electron mobility, and good thermal conductivity and stability, which are suitable for high power and high temperature applications in metal-oxide-semiconductor (MOS) based devices. In order to exploit the excellent properties of GaN, selection of a gate oxide acting as semiconductor passivation layer is essential to operate the MOS based devices near the breakdown field of GaN.
In order to fabricate a functional high power MOS based device, insulating layer sandwiched between metal and semiconductor or typically termed as gate oxide, with thickness more than 50 nm is required to sustain a high transverse electric field. Thick native oxide of GaN (Ga203) in the range of 130 to 220 nm has been successfully grown on GaN through thermal oxidization. However, it is not a preferable choice due to its slow growth rate as well as relatively high leakage current. Additionally, a relatively low dielectric constant (k) gate oxide, Si02 in comparison to Ga203, has been employed as a thick gate-oxide in GaN-based MOS devices. However, Si02 possessed low-k value of 3.9 proportional to GaN (k = 9) has caused an electric field imposed in Si02 to be approximately 2.3 times higher than in GaN. Thus, the excellent properties of GaN cannot be fully exploited due to the operation of the device at an electric field lower than the GaN breakdown field aiming to prevent the breakdown of the Si02. Therefore, there is a need for a high-k gate oxide on GaN to assist in operating the MOS based device at the breakdown field of GaN. By employing high-k gate oxide, electric field imposed in the gate oxide is being suppressed by a factor of (3.9/k) in contrast to Si02 on similar substrate. In this way, gate oxide reliability issues in regard to Si02 on GaN may be counteracted.
SUMMARY OF THE INVENTION
The present invention relates to a gate oxide, cerium oxide, with high dielectric constant (k) that is being integrated in a semiconductor and a method for producing metal-oxide-semiconductor device using the gate oxide with high dielectric constant (k). Firstly, the present invention relates to a method for producing the oxide-semiconductor. The oxide-semiconductor is then subjected to an etching, evaporating and photolithography process to produce metal-oxide-semiconductor capacitor.
The method for producing the oxide-semiconductor includes the steps of:
i) preparing a cerium containing precursor using metal organic decomposition method;
ii) spin coating the cerium containing precursor onto a semiconductor to obtain a wet film;
iii) performing a post deposition annealing of the wet film obtained from step (iii) under a flow of oxygen gas or under a flow of nitrous oxide gas at a temperature range of 400°C to 1000°C; and
iv) cooling of the annealed film obtained from step (iii) to room temperature.
The method for producing a metal-oxide-semiconductor capacitor includes the steps of:
i) preparing a cerium containing precursor using metal organic decomposition method;
ii) spin coating the cerium containing precursor onto a semiconductor to obtain a wet film;
iii) performing a post deposition annealing on the wet film obtained from step (iii) under a flow of oxygen gas or under a flow of nitrous oxide gas at a temperature range of 400°C to 1000°C; and
iv) cooling of the annealed film obtained from step (iii) to room temperature to produce oxide-semiconductor; v) etching the film obtained from step (iv);
vi) evaporating a layer of aluminum on the film obtained from step (v); and vii) patterning of metal-oxide-semiconductor capacitor obtained from step (vi). The cerium containing precursor mentioned in both the methods above is prepare using the steps of:
i) dissolving 1 mole of cerium (III) acetylacetonate hydrate in 30 moles of methanol and 42 moles of acetic acid;
ii) heating the mixture from step (i) up to 30-35C
iii) stirring the mixture on a hot plate when the temperatures reaches
30-35C
iv) heating the mixture up to 60-70C; and
v) allowing the precursor obtained from step (iv) to cool down to room temperature.
The oxide is cerium oxide. The semiconductor is Silicon (Si)-doped Gallium Nitride (GaN) epitaxial layer grown on sapphire substrate. The semiconductor has a doping concentration of 1.0 x 1018 cm"3 to 9.0 x 1018cm"3. The Si-doped GaN is separated from sapphire substrate by a thin layer. The thin layer is A1N buffer layer. The oxide- semiconductor has a thickness in a range of 52-70nm. The wet film obtained from the spin coating is Ce02 film.
The post deposition annealing of the wet film under a flow of oxygen gas is at a flow rate of 100-200ml/min. As for the post deposition annealing under a flow of nitrous oxide gas, the nitrous oxide gas flow rate is 100-200ml/min. The post deposition annealing is performed at a heating rate of 5°C/min. The cooling of the annealed film is performed at a cooling rate of 5°C/min.
The spin coating of the cerium containing precursor onto the semiconductor is done at a spinning rate of 3000-5000rpm and spinning time of 30-45 seconds. The oxide- semiconductor produced by post deposition annealing under the flow of oxygen gas provides electric breakdown field of 5.3 MV/cm. The oxide-semiconductor produced by post deposition annealing under the flow of nitrous oxide gas provides electric breakdown field of 6.3 MV/cm. The etching of the film in step (v) is done using a buffer solution of Hydrogen
Fluoride (HF) and water (H20) with a ratio of 1:1. After etching, a layer of aluminum is evaporated on the film obtained from step (v) using thermal evaporation. The metal- oxide-semiconductor capacitor obtained from step (vi) is patterned by photolithography process.
BRIEF DESCRIPTION OF THE DRAWINGS
The present invention will become more fully understood from the detailed description given herein below and accompanying drawings which are given by way of illustration only, and thus are not limitative of the present invention, wherein:
Figure 1 shows the comparison of current density-breakdown field (J-E) characteristics among high thick oxides deposited on Gallium nitride (GaN) substrate and the post deposition annealed cerium oxide (Ce02) on GaN substrate at 1000°C under oxygen gas flow. The notation of the numbers in the figure 1 are referred to following references:
[I] Y. Zhou, C. Ahyi, T. I. Smith, M. Bozack, C. Tin, J. Williams, M. Park, A. Cheng, J. Park, D. Kim, D. Wang, E. A. Preble, A. Hanser, and K. Evans, Solid-state Electron., 52, 756 (2008); [7] L. M. Lin, Y. Luo, P. T. Lai, and K. M. Lau, Thin Solid Films, 515, 2111 (2006).
[II] M. K. Lee, C. L. Ho, and J. Y. Zeng, Electrochem. Solid-State Lett., 11, D9 (2008);
[13] C. Liu, E. F. Chor, L. S. Tan, and Y. Dong, Appl. Phys. Lett., 88, 222113-1-3 (2006);
[14] L. W. Tu, W. C. Kuo, K. H. Lee, P. H. Tsao, C. M. Lai, A. K. Chu, and J. K.
Sheu, Appl. Phys. Lett., 77, 3788 (2000); [15] J. Kim, B. Gila, R. Mehandni, J. W. Johnson, J. H. Shin, K. P. Lee, B. Luo, A. Onstine, C. R. Abernathy, S. J. Pearton, and F. Ren, J. Electrochem. Soc, 149, G482 (2002).
Figure 2 shows current density-breakdown field (J-E) characteristics of the post deposition annealed cerium oxide (Ce02) on Gallium nitride (GaN) substrate at temperature 400°C -1000°C under oxygen gas flow; Figure 3 shows the structure of the oxide-semiconductor;
Figure 4 shows the Djt vs Ec-E curve of the post deposition annealed cerium oxide (Ce02) on Gallium nitride (GaN) substrate at temperature 400°C -1000°C under oxygen gas flow; Figure 5 shows the X-ray diffractographs of Metal-Organic-Decomposed cerium oxide (Ce02) films annealed on Gallium nitride (GaN) substrate in N20 and 02 ambient at 1000°C in comparison to bare GaN sample;
Figure 6 (a) shows a typical FESEM (Field Emission Scanning Microscopy) image of bare Gallium nitride (GaN) with two dimensional Atomic Force Microscope (AFM) inset;
Figure 6 (b) shows a typical FESEM (Field Emission Scanning Microscopy) image of post deposition annealed cerium oxide (Ce02) on Gallium nitride (GaN) substrate at 1000°C under N20 ambient with two dimensional Atomic Force Microscope (AFM) inset;
Figure 6 (c) shows a typical FESEM (Field Emission Scanning Microscopy) image of post deposition annealed cerium oxide (Ce02) on Gallium nitride (GaN) substrate at 1000°C under 02 ambient with two dimensional Atomic Force Microscope (AFM) inset; Figure 7 shows leakage current-electric breakdown field (J-E) characteristics of post deposition annealed cerium oxide (Ce02) on Gallium nitride (GaN) substrate at 1000°C under N20 and 02 ambient; and Figure 8 shows a comparison of interface-trap density of post deposition annealed cerium oxide (Ce02) on Gallium nitride (GaN) substrate at 1000°C under N20 and 02 ambient. Inset of the figure 8 shows a comparison of high frequency capacitance-voltage (C-V) results of post deposition annealed Ce02 on GaN substrate at 1000°C under N20 and 02 ambient.
DETAILED DESCRIPTION OF THE INVENTION
The present invention relates to a method for producing metal-oxide- semiconductor using a gate oxide with high dielectric constant (k) which is being integrated in a semiconductor. The semiconductor used in the present invention is Si- doped (n-type) Gallium nitride GaN epitaxial layer grown on sapphire substrate. The present invention firstly relates to a method for producing the oxide-semiconductor. The oxide-semiconductor is then subjected to an etching, evaporating and photolithography process to produce metal-oxide-semiconductor capacitor. It should be understood, however, that the disclosed preferred embodiments are merely exemplary of the invention, which may be embodied in various forms. Therefore, the details disclosed herein are not to be interpreted as limiting, but merely as the basis for the claims and for teaching one skilled in the art of the invention.
In the present invention, cerium oxide (Ce02) is used as the gate oxide with high dielectric constant (k), (k = 20-30). Metal-organic-decomposition (MOD) technique is used to derive cerium oxide (Ce02) precursor. The MOD technique includes the steps of: i) dissolving 1 mole of cerium (III) acetylacetonate hydrate in 30 moles of methanol and 42 moles of acetic acid to form a mixture;
ii) heating the mixture up to 30°C-35°C on a hot plate;
iii) stirring the mixture on a hot plate when the temperature reaches 30°C-35°C and it is further increased to 60°C-70°C; iv) maintaining this temperature of 60°C-70°C for 15 minutes;
v) allowing the precursor to cool down to room temperature.
The amount of cerium (III) acetylacetonate hydrate, methanol and acetic acid used in the present invention is 1.0936g, 3ml and 6ml respectively to form a precursor with 0.0025 moles. The cerium oxide precursor obtained from the MOD technique is transformed into a wet film, i.e. Ce02 film, by spin-coating the precursor on a semiconductor, i.e. Si-doped (n-type) GaN epitaxial layer grown on sapphire substrate at a spinning rate of 3000-5000 rpm and a spinning time of 30-45 seconds at room temperature, 300K. The semiconductor has a doping concentration of 1.0 x 1018 cm"3 to 9.0 x 1018cm"3. The Si-doped GaN is separated from sapphire substrate by a thin layer. The thin layer is AIN buffer layer. The AIN buffer layer reduces lattice mismatch between the GaN and the sapphire. In one embodiment, the wet film, i.e. Ce02 film, obtained from spin-coating is inserted into a horizontal tube furnace and post-deposition annealing (PDA) is performed at different temperatures, ranging from 400°C to 1000°C in oxygen gas flow at 100- 200ml/min. Dwelling time of 15 minutes is employed for each specific temperature. Heating rate of the PDA is 5°C/min. Thereafter, the annealed film is allowed to gradually cool down at a rate of 5°C/min to room temperature in oxygen gas flow of 100- 200ml/min.
After that, each film with oxide thickness of (52-70nm) is estimated by an ellipsometer (L 116S) using a laser light source of 632.8 nm at five different locations on the film. Metal-oxide-semiconductor (MOS) capacitors are then fabricated by selectively etching the annealed Ce02 film by using a buffer solution of Hydrogen fluoride (HF) and water (H20) having a ratio of 1 : 1 respectively. A layer of aluminum is then evaporated on the Ce02 film by using a thermal evaporator. An area of capacitor is patterned by photolithography process. The area of the capacitor is depended on the industrial commercial needs. However, in the present invention, an array of 2.5 x 10" 3 cm 2 capacitor is patterned by the photolithography process. A better MOS characteristic has been presented by the annealed Ce02 film under oxygen gas flow, which is being reported in the present invention in comparison to other high-k thick oxides. The highest dielectric breakdown field of ~ 5.3 MV/cm has been attained by the Ce02 film annealed at 1000 °C if compared with other thick oxide deposited on GaN substrate as shown in Figure 1. It is deduced that the Ce02 film annealed at 1000°C demonstrate a better current density (J)- breakdown field (E) characteristics than the other oxides. Acquisition of better MOS characteristics of the annealed Ce02 film under oxygen gas flow is due to emergence of a-Ce203 phase, which is embedded in Ce02 layer. During PDA, phase transformation of Ce02 to a-Ce203 has led to the formation of oxygen vacancies due to release of oxygen. Transformation of Ce02 to a-Ce203 is being expressed by following equation:
4Ce02 -> 2 a-Ce203 + 02 The released oxygen will either diffuse outward or inward through the oxygen vacancies. During the inward diffusion of oxygen, formation of P-Ga203 interfacial layer between Ce02 and GaN may take place due to the increase of excess oxygen available in inner region of the oxide. Furthermore, utilization of oxygen ambient in the present invention has further increased amount of oxygen diffused into inner region of the oxide. Thus, thickness of P-Ga203 interfacial layer increased as post-deposition annealing temperature increased from 400 °C to 1000 °C, thus reducing the leakage of current as shown in Figure 2. The lowest leakage current density of ~10-10A/cm2 and the highest electric breakdown field of 5.3 MV/cm have been perceived by Ce02 film annealed at 1000°C. Besides, the presence of interfacial layer would significantly reduce effect of dielectric polarization in MOS structure. As a result, the interfacial layer is less susceptible to breakage and leakage due to the reduction of molecular bonds distortion and soft optical phonon scattering. Thus, higher oxide breakdown field and higher channel carrier mobility with lower leakage current could be obtained when the wet film, i.e. Ce02 film, is subjected to highest PDA temperature of 1000 °C. Figure 3 shows the oxide-semiconductor structure of the present invention. Figure 4 shows interface trap density, Dit, of the Ce02 film annealed at different temperatures, which was extracted by using Terman method. From the Figure 4, it is clear that the Ce02 film annealed at 1000°C has the lowest Dit, followed by Ce02 film annealed at 800°C and 600°C. The highest Dlt is obtained by the Ce02 film annealed at 400°C. The acquisition of Dit value of ~ 8.2 x 1010 cm"2 eV"1 at Ec-E = 0.31 eV for Ce02 film annealed at 1000°C (in the present invention) is comparable to density of plasma enhanced chemical vapor deposited Si02, i.e.~l x 1011 cm^eV"1, molecular-beam epitaxially grown MgO, i.e. ~ 4 x 1011 cm VV"1 and thermally oxidized P-Ga203, i.e. ~ 1.5 x 1011 cm VV"1 on GaN substrate at similar energy level. Therefore, improvement of the MOS characteristics of the annealed Ce02 film under oxygen gas flow is due to utilization of oxygen ambient during the PDA. Total interface-trap density of the investigated energy range, Dtotai is calculated from the area under Dit vs (Ec-E) curve of the Figure 4. The lowest Dtotal of ~ 1.4 x 1011 cm"2 has been demonstrated by Ce02 film annealed at 1000°C, which is comparable to reported Dtotai of low pressure chemical vapor deposited (LPCVD) Si02 of ~ 2 x 10u cm"2.
In another embodiment, the wet film, i.e. Ce02 film, obtained from spin-coating of the precursor on Si-doped (n-type) GaN epitaxial layer grown on sapphire substrate is inserted into a horizontal tube furnace at room temperature and post-deposition annealing (PDA) is carried out by ramping up the temperature from 400°C to 1000 °C in nitrous oxide (N20) gas flow of 100-200ml/min. Dwelling time of 15 minutes is employed for each specific temperature. Heating rate of the PDA is 5°C/min. Thereafter, the annealed film is allowed to gradually cool down at a rate of 5°C/min to room temperature in N20 gas flow of 100-200ml/min. Figure 5 shows diffractographs of the annealed Ce02 film and annealed GaN (control sample) at 1000 °C in N20 and 02 gas flow. Broadness of GaN (004) diffraction peak (ICCD file no. 00-050-0792) of the annealed Ce02 film in N20 gas flow is larger than the annealed Ce02 film in 02 gas flow but similar to the broadness of GaN, control sample. Reason attributed to increment in broadness of the GaN (004) diffraction peak is decomposition of GaN wafer. This indicates that PDA in N20 gas flow enables suppression of GaN decomposition. At temperature of 1000°C, 02, N2, NO, and O are dissociated from N20 gas, wherein the N2 gas contributes to increase of nitrogen ambient partial pressure. The increment of nitrogen partial pressure may minimize decomposition of GaN surface.
Additionally, utilization of high PDA temperature at 1000°C has caused transformation of Ce02 to a-Ce203, which contributes to the generation of 02 vacancies in the Ce02 film. This has been proven by detection of a-Ce203 (002) and (011) diffraction peaks (ICCD file no. 01-078-0484). It is observed from Figure 5 that a sharper and higher intensity of Ce02 (111), (200), (220), (311), and (222) diffraction peaks (ICDD file no. 00-034-0394) have been attained for the Ce02 film annealed in N20 ambient if compared with the Ce02 film annealed in 02 ambient. This is due to compensation of 02 vacancies in Ce02 by the 02 that has been dissociated from the N20 gas. However, Ce02 film annealed in 02 ambient has a higher intensity of Ce02 (400) diffraction peak. Besides that, XRD characterization manage to detect P-Ga203 (200), (013), and (202) diffraction peaks (ICCD file no. 01-074-1776), indicating that oxidization of liquid Ga dissociated from solid GaN. It is noted from the Figure 5, the Ce02 film annealed in N20 ambient acquired higher intensity of P-Ga203 peaks than the Ce02 film annealed in 02 ambient. This denotes that more P-Ga203 interfacial layer with higher crystallinity is formed in the Ce02 film annealed in N20 ambient. Even though formation of P-Ga203 interfacial layer may reduce effective k value to become lower than pure Ce02 but it assists in reducing the leakage current of and enhancing EB, which will be clarified in the following succeeding paragraph.
Figure 6 (a), (b) and (c) show field-emission scanning electron microscopy (FESEM) images of bare GaN and the Ce02 film annealed in N20 ambient and 02 ambient respectively. Surface of bare GaN is very smooth as shown in Figure 6(a). After PDA at temperature of 1000 °C, rough annealed film surface is obtained due to decomposition of the GaN as shown in Figure 6(b)-6(c). It is perceived that surface of the Ce02 film annealed under N20 ambient is covered with a more uniform size and number of protrusion compared to Ce02 film annealed under 02 ambient. This observation is supported by two-dimensional surface topography as shown in inset of figure 6 (b) and figure 6 (c) and root-mean-square (RMS) roughness acquired from Atomic Force Microscope (AFM) characterization with scanning area of 10 um2. The Ce02 film annealed under 02 ambient has higher RMS roughness, i.e. 30.24 nm, than the Ce02 film annealed under N20 ambient, i.e. 16.16 nm. This signifies that decomposition of GaN is being minimized by using N20 gas. In addition, the Ce02 film annealed under N20 ambient has a denser film when compared with the Ce02 film annealed under 02 ambient, which is supported by calculating film density of respective sample using Lorentz-Lorenz law. Ellipsometer has been used to obtain average refractive index (n) value of the Ce02 film annealed under N20 ambient and the Ce02 film annealed under 02 ambient. The index (n) value is 2.37 and 2.23 for Ce02 film annealed under N20 ambient and the Ce02 film annealed under 02 ambient respectively.
Typical leakage current density-electric field (J-E) plot for both Ce02 films annealed in N20 and 02 ambient are shown in Figure 7. PDA performed in N20 ambient has played a vital role in enhancing the EB of the annealed Ce02 film to approximately 6.3 MV/cm if compared with Ce02 film annealed in 02 ambient, i.e. - 5.3 MV/cm. However, larger leakage current density has been demonstrated by the Ce02 film annealed under N20 ambient at low electric field. This may be attributed to the existence of higher semiconductor-oxide interface-trap density, Du, which is verified from the extraction of Djt from high-frequency capacitance- voltage (C-V) curves as shown in inset of Figure 8 using Terman method. Figure 8 shows Dit-(EC-E) plots of the Ce02 film annealed under N20 ambient and the Ce02 film annealed under 02 ambient, indicating occurrence of leakage current for applied electric field lower than 3.6 MV/cm dominated by Dit. Effective oxide charge (Qeff) is extracted indicating accumulation of negative Qeff (~ 9 x 1010 cm"2) and positive Qeff, i.e. ~ 1.7 x 1012 cm"2 in the Ce02 film annealed under 02 ambient and the Ce02 film annealed under N20 ambient, respectively. The presence of positive Qeff in the bulk oxide is possibly attributed to accumulation of N2 in bulk oxide or lower density of oxygen vacancy. When electric field increased beyond 3.6 MV/cm, Qeff dominates leakage current in bulk oxide. The acquisition of positive Qeff in the Ce02 film annealed under N20 ambient allows electrons injected from the GaN substrate to be captured by positive trap centers and form neutral traps. Whereas, presence of negative Qeff in the Ce02 film under 02 ambient may act as a scattering centre for electrons injected from the GaN substrate and thus, the Ce02 is more susceptible to breakage and leakage. As a result, more electrons are required to break network of bulk oxide consisting of positive Qeff, and thus increasing the EB of the Ce02 film annealed under N20 ambient.

Claims

1. A method for producing an oxide-semiconductor, the method includes the steps of:
i) preparing a cerium containing precursor using metal organic decomposition method;
ii) spin coating the cerium containing precursor onto a semiconductor to obtain a wet film;
iii) performing a post deposition annealing of the wet film obtained from step (ii) under a flow of oxygen gas or under a flow of nitrous oxide gas at a temperature range of 400°C to 1000°C; and
iv) cooling of the annealed film obtained from step (iii) to room temperature.
2. The method for producing an oxide-semiconductor as claimed in claim 1 wherein the oxide is cerium oxide.
3. The method for producing an oxide-semiconductor as claimed in claim 1 wherein the semiconductor is Silicon (Si)-doped Gallium Nitride (GaN) epitaxial layer grown on sapphire substrate.
4. The method for producing an oxide-semiconductor as claimed in claim 1 wherein the semiconductor has a doping concentration of 1.0 x 1018 cm"3 to 9.0 x 10I8cm 3.
5. The method for producing an oxide-semiconductor as claimed in claim 3 wherein the Si-doped GaN is separated from sapphire substrate by a thin layer.
6. The method for producing an oxide-semiconductor as claimed in claim 5 wherein the thin layer is A1N buffer layer.
7. The method for producing an oxide-semiconductor as claimed in claim 1 wherein the oxide-semiconductor has a thickness in a range of 52-70nm.
8. The method for producing an oxide-semiconductor as claimed in claim 1 wherein flow rate of the oxygen gas is at 100-200ml/min.
9. The method for producing an oxide-semiconductor as claimed in claim 1 wherein flow rate of the nitrous oxide gas is 100-200ml/min.
10. The method for producing an oxide-semiconductor as claimed in claim 1 wherein the post deposition annealing in step (iii) is performed at a heating rate of 5°C/min.
11. The method for producing an oxide-semiconductor as claimed in claim 1 wherein the cooling of the annealed film in step (iv) is performed at a cooling rate of 5°C/min.
12. The method for producing an oxide-semiconductor as claimed in claim 1 wherein the cerium containing precursor is prepared using the steps of:
i) dissolving 1 mole of cerium (III) acetylacetonate hydrate in 30 moles of methanol and 42 moles of acetic acid;
ii) heating mixture obtained from step (i) up to 30°C-35°C;
iii) stirring the mixture on a hot plate when the temperature reaches 30°C- 35°C; iv) heating the mixture up to 60°C-70°C; and
v) allowing the precursor obtained from step (iii) to cool down to room temperature.
13. The method for producing an oxide-semiconductor as claimed in claim 1 wherein the spin coating of the cerium containing precursor onto the semiconductor is done at a spinning rate of 3000-5000rpm and spinning time of 30-45 seconds.
14. The method for producing an oxide-semiconductor a claimed in claim 1 wherein the oxide-semiconductor produced by post deposition annealing under the flow of oxygen gas provides electric breakdown field of 5.3 MV/cm.
15. The method for producing an oxide-semiconductor a claimed in claim 1 wherein the oxide-semiconductor produced by post deposition annealing under the flow of nitrous oxide gas provides electric breakdown field of 6.3 MV/cm.
16. An oxide-semiconductor produced according to claims 1 to 15.
17. A method for producing a metal-oxide-semiconductor capacitor, the method includes the steps of:
i) preparing a cerium containing precursor using metal organic decomposition method;
ii) spin coating the cerium containing precursor onto a semiconductor to obtain a wet film;
iii) performing a post deposition annealing of the wet film obtained from step (ii) under a flow of oxygen gas or under a flow of nitrous oxide gas at a temperature range of 400°C to 1000°C;
iv) cooling of the annealed film obtained from step (iii) to room temperature to produce oxide-semiconductor;
v) etching the film obtained from step (iv);
vi) evaporating a layer of aluminum on the film obtained from step (v); and
vii) patterning of metal-oxide-semiconductor capacitor obtained from step (vi).
18. The method for producing a metal-oxide-semiconductor capacitor as claimed in claim 17 wherein the oxide is cerium oxide.
19. The method for producing a metal-oxide-semiconductor capacitor as claimed in claim 17 wherein the semiconductor is Silicon (Si)-doped Gallium Nitride (GaN) epitaxial layer grown on sapphire substrate.
20. The method for producing a metal-oxide-semiconductor capacitor as claimed in claim 17 wherein the semiconductor has a doping concentration of 1.0 x 1018 cm'3 to 9.0 x 1018cm"3.
21. The method for producing a metal-oxide-semiconductor capacitor as claimed in claim 19 wherein the Si-doped GaN is separated from sapphire substrate by a thin layer.
22. The method for producing a metal-oxide-semiconductor capacitor as claimed in claim 21 wherein the thin layer is A1N buffer layer.
23. The method for producing a metal-oxide-semiconductor capacitor as claimed in claim 17 wherein the oxide-semiconductor has a thickness in a range of 52-70nm.
24. The method for producing a metal-oxide-semiconductor capacitor as claimed in claim 17 wherein flow rate of the oxygen gas is 100-200ml/min.
25. The method for producing a metal-oxide-semiconductor capacitor as claimed in claim 17 wherein flow rate of the nitrous oxide gas is 100-200ml/min.
26. The method for producing a metal-oxide-semiconductor capacitor as claimed in claim 17 wherein the post deposition annealing in step (iii) is performed at a heating rate of 5°C/min.
27. The method for producing a metal-oxide-semiconductor capacitor as claimed in claim 17 wherein the cooling of the annealed film in step (iv) is performed at a cooling rate of 5°C/min.
28. The method for producing a metal-oxide-semiconductor capacitor as claimed in claim 17 wherein the cerium containing precursor is prepared using the steps of: i) dissolving 1 mole of cerium (III) acetylacetonate hydrate in 30 moles of methanol and 42 moles of acetic acid;
ii) heating mixture obtained from step (i) up to 30°C-35°C;
iii) stirring the mixture on a hot plate when the temperature reaches 30°C- 35°C;
iv) heating the mixture up to 60°C- 70°C;
v) allowing the precursor obtained from step (iii) to cool down to room temperature.
29. The method for producing a metal-oxide-semiconductor capacitor as claimed in claim 17 wherein the spin coating of the cerium containing precursor onto the semiconductor is done at a spinning rate of 3000-5000rpm and spinning time of 30-45 seconds.
30. The method for producing a metal-oxide-semiconductor capacitor as claimed in claim 17 wherein the oxide-semiconductor produced by post deposition annealing under the flow of oxygen gas provides and electric breakdown field of 5.3 MV/cm.
31. The method for producing a metal-oxide-semiconductor capacitor as claimed in claim 17 wherein the oxide-semiconductor produced by post deposition annealing under the flow of nitrous oxide gas provides electric breakdown field of 6.3 MV/cm.
32. The method for producing a metal-oxide-semiconductor capacitor as claimed in claim 17 wherein the etching of the film in step (v) is done using buffer solution of Hydrogen Fluoride (HF) and water (H20).
33. The method for producing a metal-oxide-semiconductor capacitor as claimed in claim 17 wherein a layer of aluminum is evaporated on the film obtained from step (v) using thermal evaporation.
34. The method for producing metal-oxide-semiconductor capacitor as claimed in claim 17 wherein the metal-oxide-semiconductor capacitor obtained from step (vi) is patterned by photolithography process.
35. A metal-oxide-semiconductor produced according to claims 17 to 34.
PCT/MY2011/000178 2010-10-29 2011-07-22 A method for producing metal-oxide-semiconductor (mos) capacitor WO2012057608A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
MYPI2010005133 2010-10-29
MYPI2010005133 2010-10-29

Publications (1)

Publication Number Publication Date
WO2012057608A1 true WO2012057608A1 (en) 2012-05-03

Family

ID=45994139

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/MY2011/000178 WO2012057608A1 (en) 2010-10-29 2011-07-22 A method for producing metal-oxide-semiconductor (mos) capacitor

Country Status (1)

Country Link
WO (1) WO2012057608A1 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030152813A1 (en) * 1992-10-23 2003-08-14 Symetrix Corporation Lanthanide series layered superlattice materials for integrated circuit appalications
US20050217568A1 (en) * 2004-03-30 2005-10-06 American Superconductor Corporation Deposition of buffer layers on textured metal surfaces

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030152813A1 (en) * 1992-10-23 2003-08-14 Symetrix Corporation Lanthanide series layered superlattice materials for integrated circuit appalications
US20050217568A1 (en) * 2004-03-30 2005-10-06 American Superconductor Corporation Deposition of buffer layers on textured metal surfaces

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
QUAH, H. J. ET AL.: "MOS Characteristics of Metallorganic-Decomposed CeO2 Spin- Coated on GaN", ELECTROCHEMICAL AND SOLID-STATE LETTERS, vol. 13, no. 4, 21 January 2010 (2010-01-21), pages H116 - H118 *

Similar Documents

Publication Publication Date Title
Kim et al. Thermally oxidized GaN film for use as gate insulators
CN100514558C (en) Method of producing p-GaN low-resistance Ohm contact
US20090291523A1 (en) Method of Manufacturing High Quality ZnO Monocrystal Film on Silicon(111) Substrate
CN103022295B (en) Aluminum nitride film growing on silicon substrate and preparation method and application thereof
TW201411839A (en) System and method for gas-phase sulfur passivation of a semiconductor surface
TW201251085A (en) Semiconductor laminate, semiconductor device, method for producing semiconductor laminate, and method for manufacturing semiconductor device
CN109411328B (en) Preparation method of gallium oxide film with crystallization temperature reduced by doping iron
CN107731974B (en) GaN-based light emitting diode epitaxial wafer and growth method thereof
Quah et al. Effect of postdeposition annealing in oxygen ambient on gallium-nitride-based MOS capacitors with cerium oxide gate
CN102386246A (en) P-type conductive zinc oxide film material and preparation method thereof
Alquier et al. Recent progresses in GaN power rectifier
Zhang et al. Improvement of electroluminescent performance of n-ZnO/AlN/p-GaN light-emitting diodes by optimizing the AlN barrier layer
Ting et al. Electrical and structural characteristics of tin-doped GaN thin films and its hetero-junction diode made all by RF reactive sputtering
Chen et al. UV electroluminescence and structure of n-ZnO/p-GaN heterojunction LEDs grown by atomic layer deposition
Kim et al. Fabrication and properties of A1N film on GaN substrate by using remote plasma atomic layer deposition method
JP5997258B2 (en) Stacked substrate of silicon single crystal and group III nitride single crystal having off-angle, and method for manufacturing the same
Lin et al. Influence of oxidation and annealing temperatures on quality of Ga2O3 film grown on GaN
CN101368288B (en) P type ZnO thin film production method
CN101826550B (en) ABO3/TiO2MgO/III-V nitride semiconductor heterostructure and preparation method
Thao et al. Electrical and structural characteristics of Ge-doped GaN thin films and its hetero-junction diode made all by RF reactive sputtering
TWI413185B (en) A method for forming an interfacial passivation layer in the ge semiconductor
Nakano et al. Electrical properties of thermally oxidized p-GaN metal–oxide–semiconductor diodes
CN103972332A (en) P-type gallium nitride material hole activating method
Zhang et al. Epitaxial growth and luminescence properties of ZnO-based heterojunction light-emitting diode on Si (1 1 1) substrate by pulsed-laser deposition
Lu et al. Impact of composite last quantum barrier on the performance of AlGaN-based deep ultraviolet light-emitting diode

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 11836693

Country of ref document: EP

Kind code of ref document: A1

DPE1 Request for preliminary examination filed after expiration of 19th month from priority date (pct application filed from 20040101)
NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 11836693

Country of ref document: EP

Kind code of ref document: A1