WO2012057194A1 - Method of manufacturing organic thin film transistor, and organic thin film transistor manufactured by said method - Google Patents

Method of manufacturing organic thin film transistor, and organic thin film transistor manufactured by said method Download PDF

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WO2012057194A1
WO2012057194A1 PCT/JP2011/074657 JP2011074657W WO2012057194A1 WO 2012057194 A1 WO2012057194 A1 WO 2012057194A1 JP 2011074657 W JP2011074657 W JP 2011074657W WO 2012057194 A1 WO2012057194 A1 WO 2012057194A1
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conductive layer
layer
forming
conductive
gate insulating
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PCT/JP2011/074657
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French (fr)
Japanese (ja)
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智紀 松室
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住友化学株式会社
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/621—Providing a shape to conductive layers, e.g. patterning or selective deposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/80—Constructional details
    • H10K10/82—Electrodes
    • H10K10/84—Ohmic electrodes, e.g. source or drain electrodes

Definitions

  • the present invention relates to an organic thin film transistor, and more particularly to an organic thin film transistor having a bottom gate / bottom contact structure.
  • organic semiconductors oxide semiconductors, microcrystalline silicon semiconductors, low-temperature polysilicon semiconductors that can be applied with solutions, and the like are being actively studied as materials for next-generation thin film active devices.
  • an organic semiconductor has a high mechanical strength against bending and the like, and can be formed into a layer by a coating method at a low temperature, which is superior to other semiconductor materials in manufacturing an element using a flexible substrate.
  • FIG. 17 is a cross-sectional view showing a layer structure of an organic thin film transistor having a bottom gate / bottom contact structure using an organic semiconductor.
  • a substrate 1, a gate electrode 2 formed on the substrate 1, a gate insulating layer 3 formed on the gate electrode 2, and a channel portion on the gate insulating layer 3 are formed.
  • a source electrode 7 and a drain electrode 7, an organic semiconductor layer 8 formed on the source electrode 7 and the drain electrode 7, and an overcoat 10 covering the entire element are provided.
  • the source / drain electrodes and the channel forming portion of the organic semiconductor layer are arranged on the same plane, which is also called a coplanar type.
  • FIG. 18 is a cross-sectional view showing a layer structure of an organic thin film transistor having a bottom gate / top contact structure using an organic semiconductor.
  • the organic thin film transistor includes a substrate 1, a gate electrode 2 formed on the substrate 1, a gate insulating layer 3 formed on the gate electrode 2, an organic semiconductor layer 8 formed on the gate insulating layer 3, A source electrode 7 and a drain electrode 7 formed on the organic semiconductor layer 8 with a channel portion interposed therebetween, and an overcoat 10 covering the entire element are provided.
  • the source / drain electrodes and the channel forming portion of the organic semiconductor layer are arranged in different planes, and is also called a staggered type.
  • a top gate / bottom contact type structure in which the arrangement of layers is upside down from the structure of FIG. 18 is also used.
  • the staggered device carriers flow from the source electrode through the bulk of the organic semiconductor, then through the interface between the gate insulating layer where the channel formation portion exists and the organic semiconductor, and then flow through the bulk of the organic semiconductor to the drain. To the electrode. Therefore, when the short channel is used, a high resistance value of the organic semiconductor bulk becomes a factor for remarkably reducing the transistor characteristics.
  • the coplanar structure has an advantage that the resistance of the organic semiconductor bulk becomes 0, and the coplanar structure is widely used for fine elements.
  • the contact area between the source / drain electrodes and the channel formation part of the organic semiconductor is small compared to the staggered structure, and the contact resistance between them is a critical factor that determines the characteristics.
  • a metal material layer having excellent adhesion to an organic insulating material is formed on the surface of the gate insulating layer, and a metal material layer that forms ohmic contact with the organic semiconductor is formed on the lateral portion thereof.
  • Patent Document 1 an element formed by forming a source / drain electrode
  • the metal material layer is formed by a lift-off method, and there is a problem that the photolithography process and the total number of masks increase.
  • metal vapor has high energy and may damage the organic insulating material that comes into contact. Therefore, when an organic insulating material is used as the gate insulating layer, if the source electrode and the drain electrode are directly subjected to physical vapor deposition (PVD) on the insulating layer, defects are generated on the surface of the gate insulating layer, resulting in transistor characteristics. There is a problem that decreases.
  • PVD physical vapor deposition
  • Patent Document 2 An element in which an inorganic barrier layer is formed on an organic insulating film and source / drain electrodes are formed on the inorganic barrier layer in order to reduce process damage to the surface of the gate insulating layer when the source / drain electrode is formed (Patent Document 2)
  • Patent Document 3 A device (Patent Document 3) is known in which an inorganic insulating layer is stacked on an organic insulating film, and source / drain electrodes are formed on the inorganic insulating layer.
  • an inorganic layer inferior in bending stress is formed on the entire surface of the element, and these elements are inferior in flexibility and durability.
  • JP 2006-147613 A International Publication No. 2007/099689 Japanese Unexamined Patent Publication No. 2006-013480
  • An object of the present invention is to easily manufacture a large-area element, does not damage the surface of the gate insulating layer when forming the source electrode and the drain electrode, and does not impair the flexibility of the organic insulating material.
  • An object of the present invention is to provide a method for manufacturing an organic thin film transistor having a bottom contact structure.
  • Another object of the present invention is to provide an organic thin film transistor having a bottom gate / bottom contact structure manufactured by such a manufacturing method.
  • the present invention is a method of manufacturing an organic thin film transistor having a bottom gate / bottom contact structure, Forming a gate electrode and a gate insulating layer covering the gate electrode and including an organic insulating material; Forming a first conductive layer made of a conductive material on the gate insulating layer using one of the group consisting of a coating method, an electroless plating method, or an atomic layer deposition method; Forming a second conductive layer by further forming a conductive layer made of a conductive material on the first conductive layer and then patterning the conductive layer into a predetermined shape; Removing a portion of the first conductive layer not covered with the second conductive layer to form a source electrode and a drain electrode composed of the first conductive layer and the second conductive layer; Forming an organic semiconductor layer so as to cover the source electrode, the drain electrode, and the gate insulating layer in a region sandwiched between the source electrode and the drain electrode; A method is provided.
  • the process of forming a 1st conductive layer is a precursor of the electroconductive material containing the at least 1 sort (s) of material chosen from the group which consists of silver oxide, copper oxide, zinc oxide, silver salt, silver, and copper.
  • s the at least 1 sort of material chosen from the group which consists of silver oxide, copper oxide, zinc oxide, silver salt, silver, and copper.
  • an ink in which nanoparticles of the body and / or the conductive material are dissolved or dispersed is formed on the gate insulating layer by a coating method and baked to obtain a conductive layer made of the conductive material.
  • the step of forming the first conductive layer includes forming a sol-gel solution made from tungsten alkoxide on the gate insulating layer by a coating method, and forming the gelled tungsten alkoxide.
  • a conductive layer made of tungsten oxide is obtained by baking treatment.
  • the solvent of the tungsten alkoxide sol-gel solution is propylene glycol monomethyl ether acetate (PGMEA) or 2,3,4,5,6-pentafluorotoluene.
  • PGMEA propylene glycol monomethyl ether acetate
  • 2,3,4,5,6-pentafluorotoluene 2,3,4,5,6-pentafluorotoluene
  • the first conductive layer is removed by a wet etching method using the second conductive layer as a mask, and the etching solution used at that time is an alkaline solution, and the first conductive layer and the second conductive layer are removed.
  • the etching selectivity of the conductive layer is 10: 1 or more.
  • the source electrode and the drain electrode of the organic thin film transistor having the bottom gate / bottom contact structure include a third conductive layer.
  • the third conductive layer is formed by exposing the patterned second conductive layer and the first conductive layer. After the conductive material layer is formed on the portion, the conductive material layer is patterned so that the second conductive layer is completely covered.
  • the present invention is an organic thin film transistor having a bottom gate / bottom contact structure manufactured by any one of the above methods.
  • the method for producing an organic thin film transistor of the present invention includes forming a gate electrode 2 and a gate insulating layer 3 containing an organic insulating material on the substrate 1 so as to cover the gate electrode; Forming a first conductive layer 4 made of a conductive material on the gate insulating layer 3 using one method selected from the group consisting of a coating method, an electroless plating method or an atomic layer deposition method; Forming a second conductive layer 5 by further forming a conductive layer made of a conductive material on the first conductive layer 4 and then patterning the conductive layer into a predetermined shape; Removing a portion of the first conductive layer 4 not covered with the second conductive layer 5 to form a source electrode and a drain electrode composed of the first conductive layer 4 and the second conductive layer 5; Forming the organic semiconductor layer 8 so as to cover the source electrode, the drain electrode, and the gate insulating layer in a region sandwiched between the source electrode and the drain electrode; It is the method which has.
  • the method includes
  • FIG. 1 is a sectional view showing the structure of an organic thin film transistor according to the first embodiment of the present invention.
  • This organic thin film transistor has a gate electrode 2 and a gate insulating layer 3 covering the gate electrode 2 on a substrate 1, and comprises a first conductive layer 4 and a second conductive layer 5 on the gate insulating layer 3.
  • a source electrode and a drain electrode 7 are provided, an organic semiconductor layer 8 is provided between the source and drain electrodes, and a protective layer 10 covering the organic semiconductor layer 8 is provided.
  • materials used for the substrate 1 include polyimide (PI), polyethylene terephthalate (PET), polycarbonate (PC), polyethylene naphthalate (PEN), and aromatic polyether. Examples thereof include resins such as sulfone (PES) and liquid crystal polymer (LCP), metal foils such as stainless steel, and thinned glass that can be bent by etching.
  • examples of the material used for the substrate 1 include glass and metal.
  • the gate electrode 2 As a material of the gate electrode 2, a highly conductive metal and its alloy are preferably used. More preferred are alloys, oxides and nitrides of refractory metals having high resistance to electro-stress migration.
  • the gate electrode may have a laminated structure or a surface modification treatment as necessary.
  • the refractory metal refers to a metal having a melting point of 1000 ° C. or higher.
  • the gate electrode 2 is formed on the substrate 1 by a commonly used method such as a photolithography method or a printing method.
  • a protective layer may be provided between the substrate 1 and the gate electrode 2 as necessary in order to prevent alteration of the gate electrode due to the material contained in the substrate 1.
  • a resin having no fluorine atom such as PMMA (polymethyl methacrylate), polystyrene, polyethylene, polyimide, polyvinyl alcohol, polyester, polyvinyl chloride, polyvinyl phenol, cyanoethyl pullulan, Examples thereof include fluorine resins such as “Cytop” (registered trademark) manufactured by Asahi Glass Co., Ltd. and “TEFLON” (registered trademark) manufactured by Dupont.
  • fluorine resins such as “Cytop” (registered trademark) manufactured by Asahi Glass Co., Ltd. and “TEFLON” (registered trademark) manufactured by Dupont.
  • the copolymer preferably includes a repeating unit having no polarization such as a repeating unit derived from styrene, and the composition preferably includes a polymer compound having no polarization such as polystyrene.
  • the gate insulating layer 3 is laminated on the gate electrode 2 by, for example, a method of applying and drying a solution containing an organic insulating material and a solvent.
  • a solution coating method include spin coating, dip coating, blade coating, capillary coating, slit coating, spray coating, and printing.
  • the organic insulating material is preferably crosslinked and cured by light or heat, and when the patterning is performed, it is more preferable that the organic insulating material has photosensitivity.
  • the organic insulating material a material having no polarization is preferable, and a material having a dielectric constant of 1.5 (F / m) or more is preferable.
  • the organic insulating material may be dried to form a film to ensure a high withstand voltage.
  • the organic insulating material is inactive and insoluble with respect to the solvent used in the production of the organic thin film transistor.
  • source / drain electrodes both are collectively referred to as source / drain electrodes.
  • the source / drain electrode 7 is formed through the following steps. That is, Forming a first conductive layer 4 made of a conductive material on the gate insulating layer 3 by using one method selected from the group consisting of a coating method, an electroless plating method or an atomic layer deposition method; Forming a second conductive layer 5 by further forming a conductive layer made of a conductive material on the first conductive layer 4 and then patterning the conductive layer into a predetermined shape; and the second conductive layer 5 Removing a portion of the first conductive layer 4 not covered with the step of forming a source electrode and a drain electrode comprising the first conductive layer 4 and the second conductive layer 5.
  • the step of forming the first conductive layer 4 includes the step of depositing an ink in which the precursor of the conductive material and / or nanoparticles of the conductive material are dissolved or dispersed on the gate insulating layer 3.
  • a conductive layer made of a conductive material selected from the group consisting of silver oxide, copper oxide, zinc oxide, silver salt, silver and copper is obtained by forming a film by a coating method and baking.
  • the step of forming the first conductive layer 4 includes forming a gelled tungsten alkoxide by forming a sol-gel solution made from tungsten alkoxide on the gate insulating layer 3 by a coating method.
  • the side is baked to obtain a conductive layer made of tungsten oxide.
  • This method is a so-called sol-gel method.
  • the solvent of the tungsten alkoxide sol-gel solution is propylene glycol monomethyl ether acetate (PGMEA) or 2,3,4,5,6-pentafluorotoluene.
  • the removal of the first conductive layer 4 is performed by a wet etching method using the second conductive layer 5 as a mask, and the etching solution used at that time is an alkaline solution,
  • the etching selectivity between the conductive layer 4 and the second conductive layer 5 is 10: 1 or more.
  • the source / drain electrode 7 has a laminated structure composed of the first conductive layer 4 and the second conductive layer 5.
  • each layer can have a different function.
  • a function of the first conductive layer 4 a function as an adhesion layer having an effect of improving the adhesion between the gate insulating layer 3 and the source / drain electrodes 7, and metal atoms of the second conductive layer 5 diffuse into the gate insulating layer 3.
  • the first conductive layer 4 made of a conductive material is formed on the organic insulating layer (that is, laminated as a continuous layer), it is selected from the group consisting of a coating method, an electroless plating method, or an atomic layer deposition method. It is preferable to use one method, and it is more preferable to use a coating method. By using these methods, process damage to the organic insulating material contained in the gate insulating layer 3 is reduced.
  • the material In order to form the first conductive layer 4 by the coating method, the material needs to be ink. Furthermore, in order to obtain the effect of the present invention, it is preferable to use an inorganic conductive layer in which unnecessary portions can be easily removed from the ink state in a subsequent process.
  • Tungsten oxide, silver oxide, copper oxide, silver salt, silver and copper can be converted from an ink state to an inorganic conductive layer by firing at a relatively low temperature, and can be applied to a resin substrate such as a flexible substrate.
  • tungsten oxide can be easily formed into a sol-gel solution at a temperature of about 150 to 200 ° C. by the sol-gel method.
  • Silver oxide can be reduced by immersing it in an ethanol solution and subjecting it to ultrasonic treatment.
  • reaction occurs, and further, it is known that it is reduced to silver by performing a heat treatment at less than 200 ° C. using a highly reducing alcohol (for example, triethylene glycol) as a solvent. Yes. Further, the best material is tungsten oxide, and the etching selectivity can be obtained relatively easily with respect to the metal material used in the second conductive layer 5.
  • a highly reducing alcohol for example, triethylene glycol
  • process damage means that operations and processes for producing an organic thin film transistor damage its constituent members.
  • a metal or the like is directly deposited on the gate insulating layer by physical vapor deposition (PVD)
  • PVD physical vapor deposition
  • the organic insulating material contained in the gate insulating layer is damaged by the energy of the metal vapor.
  • damage is significant.
  • the first conductive layer 4 is preferably formed by applying a solution containing a conductive material and a solvent on the gate insulating layer 3 and drying it as shown in FIG.
  • the first conductive layer 4 includes, for example, polymetalloxane that can be formed from metal alkoxide by a sol-gel method.
  • metal alkoxide include titanium, aluminum, tungsten, niobium, zirconium, vanadium, and tantalum.
  • a preferred metal alkoxide is tungsten alkoxide.
  • the tungsten oxide layer can be easily etched with an alkaline solution that is an orthogonal solvent (orthogonal solvent) with respect to the gate insulating layer 3 and the second conductive layer 5, and the first conductive layer 4 that has become unnecessary is the surface of the gate insulating layer 3. Can be easily removed.
  • tungsten alkoxide examples include tungsten (V) methoxide, tungsten (V) ethoxide, tungsten (V) isopropoxide, tungsten (V) butoxide, and the like.
  • the valence of tungsten in tungsten oxide obtained from these tungsten alkoxides is pentavalent.
  • Tungsten oxide obtained from tungsten alkoxide has the advantage that the etching time can be shortened because it dissolves very well in an alkaline solution. Furthermore, if the etching time is too short, the solubility can be changed by changing the valence of tungsten in tungsten oxide by applying ozone UV or O 2 plasma, etc., so it is easy to increase the etching time.
  • the WO 3 layer can be easily obtained by the coating method without using a reactive sputtering method or the like.
  • the firing temperature can be as low as 150 ° C., it can be applied to a flexible substrate or the like.
  • the tungsten valence in the tungsten oxide of the first conductive layer 4 obtained in this manner is hexavalent tungsten oxide in the vicinity of the end of the second conductive layer 5 where the influence of UV / O 3 due to ozone UV treatment is strong.
  • the first conductive layer 4 of tungsten oxide finally obtained is a combination of pentavalent and hexavalent.
  • the solvent of the sol-gel solution used dissolves or disperses the metal alkoxide used and exhibits volatility at room temperature.
  • an orthogonal solvent orthogonal solvent
  • examples of such a solvent include propylene glycol monomethyl ether acetate (hereinafter sometimes referred to as “PGMEA”) and aromatic compounds having a fluorine atom.
  • PGMEA propylene glycol monomethyl ether acetate
  • aromatic compounds having a fluorine atom when the gate insulating layer 3 has a fluororesin, it is necessary to uniformly form a smooth film on the surface having a surface free energy of 30 mN / m or less.
  • An aromatic compound for example, 2,3,4,5,6-pentafluorotoluene (also known as perfluorotoluene)).
  • the sol-gel solution may contain a metal alkoxide stabilizer in order to improve the uniformity and surface smoothness of the formed layer.
  • Metal alkoxide stabilizers include, for example, ⁇ -hydroxyketone compounds, ⁇ -hydroxyketone derivatives, ethanolamine compounds, ⁇ -diketone compounds, ⁇ -diketone compound derivatives, ⁇ -hydroxycarboxylic acid compounds, and ⁇ -diketone compounds. It is preferably at least one compound selected from the group.
  • the material included in the first conductive layer 4 include metals, metal compounds, alloys containing metals, semiconductors, semiconductor compounds, and alloys containing semiconductors.
  • the metal compound includes silver salts such as the above metal oxides, oxide semiconductors, and silver chloride.
  • Examples of the metal include Ti, Ta, Cu, Mo, W, Au, and Ag.
  • Examples of the metal compound include TiN, TaN, TiO 2 , WO 3 , MoO 3 , AgCl, Ag 2 O, and CuO.
  • Examples of the metal-containing alloy include MoW, TiW, and MoCr.
  • Examples of the semiconductor include Si, Ge, and Ga.
  • Examples of the semiconductor compound include SiC, GaN, and GaAs.
  • Examples of the alloy containing a semiconductor include WSi, MoSi, TiSi and the like.
  • oxide semiconductor examples include indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc composite oxide (IGZO), zinc oxide (ZnO), zinc tin oxide (ZTO), CdSnO, GaSnO, TiSnO, CuAlO, SrCuO, LaCuOS, etc. are mentioned.
  • Ti, Mo, Cr, Ta, W, Ni, Pd, Cu, Ag, Au, Pt, Ir, Co, Fe, V, Zr, a compound of these metals, an alloy containing any of these metals, Si, B, Ge, a compound of these semiconductors, and an alloy containing any of these semiconductors are preferable, silver oxide, copper oxide, zinc oxide, silver salt, silver, and copper are more preferable, and silver oxide is more preferable.
  • the first conductive layer 4 contains an oxide or nitride of a metal selected from the group consisting of Ti, Al, W, Nb, Zr, V, and Ta.
  • the material contained in the first conductive layer 4 is more preferably refractory metal fine particles, oxides and nitrides, and even more preferably metal fine particles, oxides and nitrides having a melting point of 1000 ° C. or higher.
  • the metal fine particles refer to metals having a particle diameter of 1 nm to 1000 nm. Nanoparticles having an average particle diameter of 3 to 100 nm are preferable, and nanoparticles having a particle diameter of 3 to 30 nm are more preferable.
  • the solution containing the conductive material and the solvent for forming the first conductive layer 4 is, for example, ITO, IZO, IGZO, tungsten oxide (W x O y ), titanium oxide other than the metal alkoxide shown above.
  • the solution is an electroless plating solution containing metal ions of these conductive materials.
  • the first conductive layer 4 uses a dispersion liquid or a sol-gel liquid containing a conductive material and a solvent, and spin coating, dip coating, blade coating, capillary coating, slit coating, spray coating, printing, etc. It is preferable to form a film by this coating method.
  • the first conductive layer 4 is formed by using an electroless plating solution containing metal ions of the conductive material, spin coating method, dip coating method, blade coating method, capillary coating method, slit coating method, spray coating method, By applying a plating catalyst or a plating catalyst precursor on the entire surface of the gate insulating layer by a printing method, and immersing the plating catalyst or the plating catalyst precursor in the electroless plating solution together with the gate insulating layer or the like to deposit metal or the like. It may be formed.
  • the method for laminating the first conductive layer 4 may be a method other than those described above, and is not particularly limited as long as it does not damage the gate insulating film.
  • the layers may be grown by an atomic layer deposition (ALD) method or the like.
  • ALD atomic layer deposition
  • materials included in the first conductive layer 4 include Ti, Mo, Cr, Ta, W, Ni, Pd, Cu, Au, Pt, Ir, Co, Fe, V, Zr, and these And alloys containing any of these metals, oxides of these metals, or nitrides of these metals.
  • the Fermi level of the first conductive layer 4 is equal to or deeper than the energy of the highest occupied orbit (HOMO) of the organic semiconductor layer 7.
  • the layer thickness of the first conductive layer 4 is preferably 3 to 500 nm, and more preferably 3 to 50 nm.
  • the second conductive layer 5 is preferably formed by forming a conductive material on the first conductive layer 4 and then patterning it as shown in FIG.
  • the second conductive layer 5 can be formed by sputtering from an Ag alloy, for example. Even when the sputtering method is used, since the first conductive layer 4 before patterning functions as a barrier layer, process damage to the organic insulating material is reduced.
  • the Ag alloy include an Ag—Pd—Cu alloy (APC).
  • a metal having high conductivity, an alloy thereof, an oxide thereof, or a nitride thereof can be used in addition to the Ag alloy.
  • Ag, Al, Au, Cd, Co, Cr, Cu, Fe, Mg, Mo, Ni, Pb, Pd, Pt, Sn, Ta, Ti, V, W, Zn, Zr, or any of these metals Alloys containing are preferred.
  • These metals are very common metals and have high conductivity, and it is possible to obtain a sputtering target relatively easily. Furthermore, even when these metal alloys, oxides, and nitrides are formed, these materials can be easily obtained by reactive sputtering.
  • the material has low electrocost migration resistance at low cost. Examples of the material include Cu.
  • the material included in the second conductive layer 5 is specifically illustrated along with a non-limiting combination with the material included in the first conductive layer 4.
  • the conductivity of the second conductive layer 5 is preferably higher than the conductivity of the first conductive layer 4. Since the conductivity of the second conductive layer 5 is higher than the conductivity of the first electrode layer 4, it is possible to give the second conductive layer a function as a wiring layer such as a bus line that is indispensable for the element configuration. It is because it becomes.
  • the second conductive layer 5 may be laminated by a physical vapor deposition (PVD) method, a chemical vapor deposition (CVD) method, or an electroless plating method in addition to the sputtering method.
  • PVD physical vapor deposition
  • CVD chemical vapor deposition
  • electroless plating method in addition to the sputtering method.
  • the patterning of the second conductive layer 5 is performed using a photolithography method.
  • a mask 9 is formed on the second conductive layer 5, and the portion of the second conductive layer 5 not covered with the mask is removed by etching.
  • a dispersion liquid or a sol-gel liquid containing a conductive material such as a metal nanoparticle dispersion solution and a solvent is applied to a necessary region on the first conductive layer 4 by a printing method.
  • the patterned second conductive layer 5 may be formed by direct application.
  • a plating catalyst or a plating catalyst precursor is directly printed on a necessary region on the first conductive layer 4 to perform patterning, and the plating catalyst or the plating catalyst precursor together with the first conductive layer and the like.
  • the patterned second conductive layer 5 may be formed by immersing the body in an electroless plating solution containing metal ions of the conductive material and depositing metal or the like.
  • the second conductive layer 5 is formed at a desired position suitable for the bottom gate / bottom contact structure.
  • the layer thickness of the second conductive layer is preferably 10 to 1000 nm, more preferably 50 to 500 nm.
  • the first conductive layer 4 is wet-etched with an alkaline etchant having a high etching selectivity with respect to the second conductive layer 5, and the first conductive layer 4 is shown in FIG.
  • the source / drain electrode 7 is formed by patterning as shown.
  • the second conductive layer 5 has a thickness of 50 nm. Only etched. In this case, more preferably, an etching solution in which the second conductive layer 5 is insoluble is used.
  • a dilute aqueous solution of potassium hydroxide (KOH) or a dilute aqueous solution of tetramethylammonium hydroxide (TMAH) may be used, and the concentration of the solution may be adjusted in any way for adjusting the etching rate. Although it can be changed, it is preferably 0.1 wt% or more.
  • KOH potassium hydroxide
  • TMAH tetramethylammonium hydroxide
  • a commercially available alkaline etching solution may be used, and specific examples include “Melstrip” (trade name) series manufactured by Meltex Co., Ltd. and the like.
  • a more preferred alkaline etching solution is a dilute aqueous solution of tetramethylammonium hydroxide aqueous solution (TMAH) free from metal ions.
  • the second conductive layer 5 is made of Al, Cd, Co, Cr, Fe, Mg, Mo, Ni, Pb, Pd, Pt, Sn, Ta, Ti, V, W other than those described above.
  • Zn, Zr, and the like may be used, but are not preferable from the viewpoint of process such as etching and the charge injection property to the semiconductor layer.
  • gold, silver, copper, or silver, copper, and a palladium alloy are preferable. These metals are fired by firing the organic semiconductor layer 8 that has been applied and formed. Compared with the case where no etching is performed, a higher hole injection property to the organic semiconductor layer 8 can be obtained.
  • an alkaline resist stripping solution or the like may be used, and the first conductive layer 4 may be stripped simultaneously with the resist stripping.
  • the first conductive layer 4 before patterning has a function as a protective layer that protects the gate insulating layer 3 from process damage when the second conductive layer 5 is formed.
  • the first conductive layer 4 has a function of improving the adhesion between the gate insulating layer 3 and the second conductive layer 5. Further, the first conductive layer 4 has a function as a barrier layer, a function as a charge injection layer to the organic semiconductor layer 8, and the like.
  • the function of the first conductive layer 4 as a protective layer refers to a function of protecting the constituent members from physical and chemical external factors generated during the manufacturing process of the organic thin film transistor. For example, in the case of an organic insulating layer, the contact angle and the surface roughness change when the surface is damaged, but these changes can be suppressed by providing a protective layer.
  • the function of improving the adhesion between the gate insulating layer of the first conductive layer 4 and the second conductive layer is a grid board defined in “JIS G0202” as a quantitative evaluation by a scratch test method and a method for confirming more easily. It can be confirmed by an eye test.
  • the function of the first conductive layer 4 as a barrier layer refers to a function of preventing diffusion of metal molecules into a peripheral film, a function of imparting electromigration and stress migration resistance.
  • the function can be confirmed by conducting a composition analysis in the layer thickness direction by XPS, AES, TOF-SIMS, or the like, and confirming that metal atoms are not diffused in the organic insulating film.
  • electromigration and stress migration it can be determined that no problem has occurred if there is no significant change in the resistance value of the electrode and the organic thin film transistor is in a desired movement.
  • electromigration is caused by the movement of metal atoms in a metal wiring subjected to a large current stress, resulting in void formation or accumulation of atoms, causing failures such as an increase in wiring resistance, disconnection, and short between wirings.
  • stress migration refers to the stress that the metal wiring film receives from the protective layer (passivation film) or interlayer insulating film, causing atomic movement in the wiring due to high-temperature treatment or temperature cycle, resulting in fluctuations in resistance value or disconnection. Refers to the phenomenon.
  • the function as a charge injection layer into the organic semiconductor layer 8 refers to a function of injecting holes or electrons into the organic semiconductor layer 8. This function can be confirmed by evaluating electrical characteristics of the organic thin film transistor.
  • the organic semiconductor layer 8 made of an organic semiconductor material can be laminated on the gate insulating layer 3 between the source electrode and the drain electrode by, for example, a spin coating method.
  • a coating method such as a spin coating method, a dip coating method, a blade coating method, a capillary coating method, a slit coating method, a spray coating method, or a printing method is preferable.
  • the organic semiconductor material is not particularly limited as long as it is a material that can be dissolved in a solvent and form the organic semiconductor layer 8 by a coating method.
  • the organic semiconductor material include 6,13-bis (triisopropylsilylethynyl) pentacene (6,13-bis (triisopropylsilylethynyl) pentacene (Tips-Pentacene)), 13,6-N-sulfinylacetamidopentacene (13,6- N-sulfinyl acetamidopentacene (NSFAAP)), 6,13-dihydro-6,13-methanopentacene-15-one (6,13-Dihydro-6,13-methanopentacene-15-one (DMP)), pentacene-N-sulfinyl-n -Pentacene-N-sulfinyl-n-butylcarbamate adduct, Pentacene
  • the protective layer 10 can be laminated by applying a solution containing an organic insulating material and a solvent on the organic semiconductor layer 8 by a spin coating method or the like. At this time, if necessary, the protective layer 10 may be subjected to patterning such as contact hole formation.
  • the organic insulating material contained in the protective layer 10 has photosensitivity.
  • the organic insulating material a material having no polarization is preferable, and a material having a dielectric constant of 1.5 (F / m) or more and 4.0 (F / m) or less is desirable.
  • Organic insulating materials include PMMA (polymethyl methacrylate), polystyrene, polyethylene, polyimide-free resin, such as “Cytop” (trade name) manufactured by Asahi Glass Co., “TEFLON” (registered by DuPont) (registered) Trademark) and the like.
  • PMMA polymethyl methacrylate
  • polystyrene polystyrene
  • polyethylene polyethylene
  • polyimide-free resin such as “Cytop” (trade name) manufactured by Asahi Glass Co., “TEFLON” (registered by DuPont) (registered) Trademark) and the like.
  • TEFLON registered by DuPont
  • the copolymer preferably includes a repeating unit having no polarization such as a repeating unit derived from styrene, and the composition preferably includes
  • the organic thin film transistor manufacturing method of the present invention is such that the source electrode and the drain electrode of the organic thin film transistor having the bottom gate / bottom contact structure include the third conductive layer 6, and the formation of the third conductive layer 6 is as follows.
  • the patterned second conductive layer 5 and a layer of a conductive material are formed on the exposed portion of the first conductive layer 4 so that the second conductive layer 5 is completely covered with the layer. This is done by patterning. This aspect will be described in detail below.
  • FIG. 8 is a sectional view showing the structure of an organic thin film transistor according to the second embodiment of the present invention.
  • This organic thin film transistor has a gate electrode 2 and a gate insulating layer 3 covering the gate electrode 2 on a substrate 1, and a first conductive layer 4, a second conductive layer 5, and a second conductive layer are formed on the gate insulating layer 3.
  • a source electrode and a drain electrode made of three conductive layers 6 are provided, an organic semiconductor layer 8 is provided between the source / drain electrodes 7, and a protective layer 10 covering the organic semiconductor layer 8 is provided.
  • the materials included in the substrate 1, the gate electrode 2, and the gate insulating layer 3 and the formation method of the organic thin film transistor are the same as those in the first embodiment.
  • the source / drain electrode 7 includes a first conductive layer 4, a second conductive layer 5, and a third conductive layer 6.
  • a coating method, an electroless plating method or an atomic layer deposition method is preferably used, and a coating method is more preferably used.
  • the first conductive layer 4 is preferably coated with a solution containing a conductive material and a solvent on the gate insulating layer 3 and dried to form a continuous layer as shown in FIG. Form.
  • the material contained in the first conductive layer 4, the method of laminating the first conductive layer 4, and the function of the first conductive layer 4 are the same as those in the first embodiment.
  • the second conductive layer 5 is preferably laminated as a continuous layer on the first conductive layer 4 as shown in FIG. Thereafter, the second conductive layer 5 is patterned using a mask 9 as shown in FIG. 11, and formed at a desired position as shown in FIG.
  • the material contained in the second conductive layer 5 and the method of forming and patterning the second conductive layer 5 are the same as those in the first embodiment.
  • the third conductive layer 6 is preferably formed by laminating as a continuous layer on the first conductive layer 4 and the second conductive layer 5 and then patterning as shown in FIG.
  • the third conductive layer 6 can be laminated by sputtering from TaN, for example. Thereafter, a mask is formed on the stacked continuous layers by a printing method or the like, and the patterning is performed by removing the portion of the third conductive layer 6 (TaN film) not covered with the mask by wet etching. As an etching solution for TaN, for example, “667501” (trade name) manufactured by Sigma-Aldrich is used. By the patterning, a third conductive layer 6 is formed on the second conductive layer 5 as shown in FIG.
  • the third conductive layer 6 is formed so as to cover the upper surface and the side surface of the second conductive layer 5 and the end portion is in contact with the upper surface of the first conductive layer.
  • a metal, a metal compound, a metal-containing alloy, a semiconductor, a semiconductor compound, a semiconductor-containing alloy, an oxide semiconductor, or the like can be used as the material contained in the third conductive layer 6, in addition to TaN.
  • metals, metal compounds, metal-containing alloys, semiconductors, semiconductor compounds, semiconductor-containing alloys, and oxide semiconductors include metals that may be included in the first conductive layer 4, metal compounds, and metals.
  • the same material as an alloy, a semiconductor, a compound of a semiconductor, an alloy including a semiconductor, and an oxide semiconductor is included.
  • An oxide semiconductor typified by is preferable.
  • an oxide semiconductor material or a material having a high work function such as Pd, Au, Pt, or Ir is more preferable from the viewpoint of charge injection.
  • the conductivity of the second conductive layer 5 is preferably higher than that of the third conductive layer 6. Since the conductivity of the second conductive layer 5 is higher than the conductivity of the third electrode layer 6, it is possible to give the second conductive layer a function as a wiring layer such as a bus line that is indispensable for the element configuration. It is because it becomes.
  • the third conductive layer 6 may be laminated by a physical vapor deposition (PVD) method, a chemical vapor deposition (CVD) method, or an electroless plating method.
  • the third conductive layer 6 may be grown and stacked by an atomic layer deposition (ALD) method or the like.
  • materials contained in the conductive layer 6 include Ti, Mo, Cr, Ta, W, Ni, Pd, Cu, Au, Pt, Ir, Co, Fe, V, Zr, and these metals.
  • the third conductive layer 6 may be patterned by directly printing an etching protective layer by patterning by photolithography or printing.
  • a dispersion solution or a sol-gel solution containing a conductive material such as a metal fine particle dispersion solution and a solvent is directly applied on the second conductive layer 5 by a printing method
  • the third conductive layer 6 may be formed.
  • a plating catalyst or a plating catalyst precursor is printed directly on the second conductive layer 5 by using an electroless plating method, and the plating catalyst or the plating catalyst precursor is made of the conductive material together with the second conductive layer or the like.
  • the third conductive layer 6 may be formed by depositing a metal or the like by dipping in an electroless plating solution containing metal ions.
  • the layer thickness of the third conductive layer is preferably 10 to 500 nm, and more preferably 10 to 100 nm.
  • the first conductive layer 4 is wet-etched with an alkaline etchant having a high etching selectivity with respect to the third conductive layer 6, and the first conductive layer 4 is shown in FIG.
  • the source / drain electrode 7 is formed by patterning as shown.
  • the third conductive layer 6 has a thickness of 50 nm. Only etched. In this case, more preferably, an etching solution in which the third conductive layer 6 is insoluble is used.
  • a dilute aqueous solution of potassium hydroxide (KOH) or a dilute aqueous solution of tetramethylammonium hydroxide (TMAH) may be used, and the concentration of the solution may be set in any way for adjusting the etching rate. Although it can be changed, it is preferably 0.1 wt% or more. Moreover, you may use a commercially available alkaline etching liquid and the Melstrip series by Meltex, etc. are mentioned.
  • a more preferred alkaline etching solution is a dilute aqueous solution of tetramethylammonium hydroxide aqueous solution (TMAH) free from metal ions.
  • the third conductive layer 6 and the first conductive layer 4 may be simultaneously peeled and patterned with a TaN etchant that is an alkaline etchant.
  • the third conductive layer 6 covers the upper surface and side surfaces of the second conductive layer 5 and has a function as a barrier layer.
  • the third conductive layer 6 covers the upper surface and the side surface of the second conductive layer 5 and functions as a charge injection layer to the organic semiconductor layer 8.
  • the third conductive layer 6 in order for the third conductive layer 6 to reliably cover the side surface of the second conductive layer 5, the third conductive layer 6 preferably protrudes 10 nm or more per side with respect to the second conductive layer 5, More preferably, it protrudes about 1000 nm. Therefore, the first conductive layer 4 inevitably has a structure that protrudes from the second conductive layer 5 in the same amount as the third conductive layer 6.
  • the organic semiconductor layer 8 made of an organic semiconductor material can be laminated on the gate insulating layer between the source electrode and the drain electrode as shown in FIG.
  • the material contained in the organic semiconductor layer 8 and the method for forming the organic semiconductor layer 8 are the same as those in the first embodiment.
  • the protective layer 10 can be laminated by applying a solution containing an organic insulating material and a solvent on the organic semiconductor layer 7 as shown in FIG.
  • the material contained in the protective layer 10 and the method for forming the protective layer 10 are the same as those in the first embodiment.
  • the organic thin film transistor of the present invention can be used for active matrix display devices and circuits.
  • the printing methods mentioned in the text are the slit coating method, the capillary coating method, the blade coating method, the spray coating method, the plateless printing method represented by the ink jet method, the flexographic printing, the gravure printing, and the offset printing. Plate printing methods represented by screen printing, microcontact printing, and nanoimprinting.
  • Synthesis example 1 (Synthesis of polymer compound 1) Styrene (made by Wako Pure Chemical Industries) 2.06 g, 2,3,4,5,6-pentafluorostyrene (made by Aldrich) 2.43 g, 2- [O- [1′-methylpropylideneamino] carboxyamino] ethyl -Methacrylate (made by Showa Denko, trade name “Karenz MOI-BM”) 1.00 g, 2,2′-azobis (2-methylpropionitrile) 0.06 g, 2-heptanone (made by Wako Pure Chemical Industries) 14.06 g Is put in a 50 ml pressure vessel (Ace), bubbled with nitrogen, sealed, and polymerized in an oil bath at 60 ° C. for 48 hours to give a viscous 2-heptanone solution in which the polymer compound 1 is dissolved.
  • the high molecular compound 1 has the following repeating unit. Here, the number in parentheses indicates the mole fraction of the repeating
  • Synthesis example 2 (Synthesis of polymer compound 2) 4-aminostyrene (manufactured by Aldrich) 3.50 g, 2,3,4,5,6-pentafluorostyrene (manufactured by Aldrich) 13.32 g, 2,2′-azobis (2-methylpropionitrile) 0.08 g 25-36 g of 2-heptanone (manufactured by Wako Pure Chemical Industries, Ltd.) was placed in a 125 ml pressure vessel (manufactured by Ace), bubbled with nitrogen, sealed, and polymerized in an oil bath at 60 ° C. for 48 hours to obtain a polymer A viscous 2-heptanone solution in which 2 was dissolved was obtained.
  • the high molecular compound 2 has the following repeating unit. Here, the number in parentheses indicates the mole fraction of the repeating unit.
  • Synthesis example 3 (Synthesis of polymer compound 3) In toluene (80 mL) containing 6.40 g of 9,9-di-n-octylfluorene-2,7-di (ethylene boronate) and 4.00 g of 5,5′-dibromo-2,2′-bithiophene Under nitrogen, 0.18 g of tetrakis (triphenylphosphine) palladium, 1.0 g of methyltrioctylammonium chloride (manufactured by Aldrich, trade name “Aliquat 336” (registered trademark)), and 24 mL of 2M aqueous sodium carbonate solution were added. It was.
  • the mixture was stirred vigorously and heated to reflux for 24 hours.
  • the viscous reaction mixture was poured into 500 mL of acetone to precipitate a fibrous yellow polymer.
  • the polymer was collected by filtration, washed with acetone and dried in a vacuum oven at 60 ° C. overnight.
  • the resulting polymer is referred to as polymer compound 3.
  • the high molecular compound 3 has the following repeating unit. n indicates the number of repeating units.
  • Example 1 Manufacture of organic thin-film transistors
  • Examples of the organic thin film transistor of the present invention will be described with reference to FIGS.
  • Layer 8 was formed to produce an organic thin film transistor.
  • the transistor characteristic was measured in the vacuum prober, the characteristic was compared, and the effect of this invention was confirmed.
  • the pressure of the vacuum prober at this time was about 5 ⁇ 10 ⁇ 3 Pa.
  • a Mo (molybdenum) layer was formed on the cleaned substrate 1 by sputtering, and the gate electrode 2 was formed by photolithography.
  • the photoresist is “TFR-H PL” manufactured by Tokyo Ohka Kogyo Co., Ltd.
  • the developer is “NPD-18” manufactured by Nagase ChemteX
  • the resist stripper is “106” manufactured by Tokyo Ohka Kogyo Co., Ltd.
  • As the Mo etching solution “S-80520” manufactured by Kanto Chemical Co., Inc. was used. Photolithography was performed by the following steps.
  • a film of photoresist “TFR-H PL” was formed on the Mo layer and irradiated with 365 nm UV light through a photomask.
  • the photoresist was developed using a developer “NPD-18”.
  • the Mo exposed portion of the Mo layer is removed using Mo etching solution “S-80520”, and the remaining photoresist is removed using resist stripping solution “106”. After peeling, the gate electrode 2 was patterned.
  • the substrate on which the gate electrode 2 is formed is wet-cleaned, and then the substrate is cleaned for 300 seconds with a UV ozone cleaner, and then a solution containing the polymer compound 1, polymer compound 2 and 2-heptanone is gated.
  • An organic layer was formed on the electrode 2 by spin coating. Since this organic layer is thermally crosslinkable, it was immediately fired to obtain the gate insulating layer 3.
  • the baking treatment at this time was carried out at 220 ° C. for 25 minutes as the final baking treatment.
  • the layer thickness of the gate insulating layer 3 was about 470 nm.
  • a sol-gel solution of pentavalent tungsten oxide (W 2 O 5 ) was applied onto the gate insulating layer 3 by a spin coating method. After coating, the film was dried in the air for about 5 minutes, and then baked at 150 ° C. for 30 minutes to obtain the first conductive layer 4 shown in FIG. In order to determine the layer thickness of the first conductive layer 4, the layer thickness of the layer formed by applying in advance under the same conditions was 30 nm.
  • the sol-gel solution of W 2 O 5 used for forming the first conductive layer 4 uses tungsten (V) ethoxide as tungsten alkoxide and is a ⁇ -diketone compound as a stabilizer. Acetylacetone was used. 2,3,4,5,6-pentafluorotoluene was used as the solvent for the sol-gel solution of the substrate produced this time.
  • copper (Cu) was formed with a layer thickness of 100 nm on the first conductive layer 4 by a sputtering method to obtain a second conductive layer 5 shown in FIG.
  • the second conductive layer 5 was processed by the photolithography method into the shape of the second conductive layer 5 shown in FIG.
  • the photoresist is “TFR-H PL” manufactured by Tokyo Ohka Kogyo Co., Ltd.
  • the developer is “NPD-18” manufactured by Nagase ChemteX
  • the resist stripper is “106” manufactured by Tokyo Ohka Kogyo Co., Ltd.
  • As a Cu etching solution a mixed acid “Cu-03” manufactured by Kanto Chemical Co., Inc. was used.
  • Photolithography was performed by the following steps.
  • a film of photoresist “TFR-H PL” was formed on the Cu layer, and irradiated with 365 nm UV light through a photomask.
  • the photoresist was developed using a developer “NPD-18”.
  • NPD-18 developer
  • the developed photoresist as a mask, the portion of the second conductive layer 5 where Cu is exposed is removed using a Cu etching solution “Cu-03”, and the remaining portion is removed using a resist stripping solution “106”.
  • the photoresist was peeled off and the second conductive layer 5 was patterned.
  • TMAH aqueous solution concentration 2.386%
  • the exposed portion was etched to obtain an element structure shown in FIG.
  • the etching time at this time was 90 seconds.
  • the final baking is performed in a nitrogen atmosphere with an oxygen concentration of less than 0.1 ppm. This was carried out at 200 ° C. for 10 minutes in a glove box having a moisture concentration of less than 1.0 ppm.
  • the surface of the gate insulating layer 3 can be protected from process damage when the second conductive layer 5 is produced. Further, by providing the first conductive layer 4, adhesion between the gate insulating layer 3 and the second conductive layer 5 is improved.
  • the first conductive layer also functions as a protective layer against diffusion of the second conductive layer 5 into the gate insulating layer 3.
  • the polymer compound 3 is dissolved in a xylene solution at a concentration of 0.5 wt%, and is applied onto the substrate by a spin coating method in a glove box under a nitrogen atmosphere.
  • the calcination process for 1 minute was implemented.
  • the thickness of the organic semiconductor layer was about 16 nm. In this way, an organic thin film transistor having the structure shown in FIG. 7 was obtained.
  • the surface treatment to the source electrode and the drain electrode was not performed.
  • the gate insulating layer surface roughness Ra of the gate insulating layer was measured using a scanning probe microscope (product name “SPI3800N”, manufactured by SII (Nanotechnology)).
  • the surface contact angle of the gate insulating layer was measured using an automatic contact angle measuring device (trade name “OCA20”, manufactured by Eihiro Seiki Co., Ltd.).
  • Mobility ⁇ , maximum current Ion, threshold voltage Vth, hysteresis, Swing Factor (subthreshold swing), and On / Off ratio were determined from the transmission (Vg ⁇ Id) characteristics. Further, the weak inversion region formation start voltage at which the drain current Id having the transmission (Vg ⁇ Id) characteristic rises is defined as the drain current rise voltage Von, and is shown in Table 2 separately from the threshold voltage Vth.
  • Comparative Example 1 As a comparative example, a substrate (glass) 1, a gate electrode (Mo) 2 on the substrate 1, a gate insulating layer (organic insulating layer) 3 on the gate electrode 2, and a second of the present invention on the gate insulating layer 3 An organic thin film transistor is manufactured by forming a single-layer source electrode and drain electrode of a single metal single layer of the same material as the conductive layer 5, and forming an organic semiconductor layer between the source electrode and the drain electrode. did.
  • the first conductive layer 4 was not formed, but the second conductive layer 5 was formed on the gate insulating layer 3 by a sputtering method and patterned by photolithography to form a source electrode and a drain electrode.
  • the organic thin-film transistor was manufactured similarly to 1, and the transistor characteristic was measured. Table 2 shows the obtained transistor characteristics.
  • the organic thin film transistor of Example 1 has greatly reduced process damage to the gate insulating layer when the Cu layer is formed by the sputtering method. The value is equivalent to that of the gate insulating layer not passing through the process in Example 1.
  • the physical damage to the gate insulating layer was affected by the surface roughness and the surface contact angle of the gate insulating layer 3. It appears remarkably.
  • the organic thin film transistor of Example 1 Compared with the organic thin film transistor of Comparative Example 1, the organic thin film transistor of Example 1 had a drain current rising voltage Von close to 0 [V], almost no hysteresis, and the maximum current Ion improved by about two orders of magnitude.
  • the organic thin-film transistor with a high characteristic was obtained by the method of this invention.
  • the protective layer 10 shown in FIGS. 1 and 8 is more preferably formed last.
  • the first conductive layer (W 2 O 5 layer) 4 has a function as a charge injection layer by using a material having a better charge injection property.
  • the organic thin film transistor of the present invention can be used for active matrix display devices and circuits.

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Abstract

Disclosed is a method of manufacturing organic thin film transistors which makes possible easy manufacture of large surface-area elements and which does not damage the gate insulating layer when forming the source electrode and the drain electrode nor compromises flexibility of organic insulating materials. The method involves: a step for forming a gate electrode and a gate insulating layer which covers said gate electrode and contains an organic insulating material; a step for using a coating method, an electroless plating method or an atomic layer deposition method to form a first conductive layer comprising a conductive material on said gate insulting layer; a step for forming a second conductive layer with patterning on said first conductive layer; a step for removing the portion of the first conductive layer not covered by said second conductive layer, and forming a source electrode and a drain electrode comprising a first conductive layer and a second conductive layer; and a step for forming an organic semiconductor layer so as to cover the source electrode, the drain electrode, and the gate insulating layer of the region between said source electrode and said drain electrode.

Description

有機薄膜トランジスタの製造方法及び該方法で製造された有機薄膜トランジスタMethod for producing organic thin film transistor and organic thin film transistor produced by the method
　本発明は、有機薄膜トランジスタに関し、特にボトムゲート・ボトムコンタクト構造の有機薄膜トランジスタに関する。 The present invention relates to an organic thin film transistor, and more particularly to an organic thin film transistor having a bottom gate / bottom contact structure.
　現在、次世代薄膜能動素子の材料として、有機半導体、酸化物半導体、マイクロクリスタルシリコン半導体、溶液塗布可能な低温ポリシリコン半導体等が盛んに研究されている。その中で、有機半導体は曲げ等に対する機械強度が強く、低温で塗布法にて層形成することができ、フレキシブル基板を用いた素子の製造において、他の半導体材料に比べ優れている。 Currently, organic semiconductors, oxide semiconductors, microcrystalline silicon semiconductors, low-temperature polysilicon semiconductors that can be applied with solutions, and the like are being actively studied as materials for next-generation thin film active devices. Among them, an organic semiconductor has a high mechanical strength against bending and the like, and can be formed into a layer by a coating method at a low temperature, which is superior to other semiconductor materials in manufacturing an element using a flexible substrate.
　図１７は、有機半導体を使用したボトムゲート・ボトムコンタクト構造の有機薄膜トランジスタの層構成を示す断面図である。この有機薄膜トランジスタには、基板１と、基板１上に形成されたゲート電極２と、ゲート電極２上に形成されたゲート絶縁層３と、ゲート絶縁層３上にチャネル部を挟んで形成されたソース電極７及びドレイン電極７と、ソース電極７及びドレイン電極７上に形成された有機半導体層８と、素子全体を被覆するオーバーコート１０とが、備えられている。この構造は、ソース・ドレイン電極と有機半導体層のチャンネル形成部とが同一平面的に配置されており、コプラナー型とも呼ばれる。 FIG. 17 is a cross-sectional view showing a layer structure of an organic thin film transistor having a bottom gate / bottom contact structure using an organic semiconductor. In this organic thin film transistor, a substrate 1, a gate electrode 2 formed on the substrate 1, a gate insulating layer 3 formed on the gate electrode 2, and a channel portion on the gate insulating layer 3 are formed. A source electrode 7 and a drain electrode 7, an organic semiconductor layer 8 formed on the source electrode 7 and the drain electrode 7, and an overcoat 10 covering the entire element are provided. In this structure, the source / drain electrodes and the channel forming portion of the organic semiconductor layer are arranged on the same plane, which is also called a coplanar type.
　図１８は、有機半導体を使用したボトムゲート・トップコンタクト構造の有機薄膜トランジスタの層構成を示す断面図である。この有機薄膜トランジスタには、基板１と、基板１上に形成されたゲート電極２と、ゲート電極２上に形成されたゲート絶縁層３と、ゲート絶縁層３上に形成された有機半導体層８と、有機半導体層８上にチャネル部を挟んで形成されたソース電極７及びドレイン電極７と、素子全体を被覆するオーバーコート１０とが、備えられている。この構造は、ソース・ドレイン電極と有機半導体層のチャンネル形成部とが異平面的に配置されており、スタガ型とも呼ばれる。この他、有機半導体を使用したスタガ型の構造としては、図１８の構造とは層の配置が上下逆になった、トップゲート・ボトムコンタクト型の構造も使われている。 FIG. 18 is a cross-sectional view showing a layer structure of an organic thin film transistor having a bottom gate / top contact structure using an organic semiconductor. The organic thin film transistor includes a substrate 1, a gate electrode 2 formed on the substrate 1, a gate insulating layer 3 formed on the gate electrode 2, an organic semiconductor layer 8 formed on the gate insulating layer 3, A source electrode 7 and a drain electrode 7 formed on the organic semiconductor layer 8 with a channel portion interposed therebetween, and an overcoat 10 covering the entire element are provided. In this structure, the source / drain electrodes and the channel forming portion of the organic semiconductor layer are arranged in different planes, and is also called a staggered type. In addition, as a stagger type structure using an organic semiconductor, a top gate / bottom contact type structure in which the arrangement of layers is upside down from the structure of FIG. 18 is also used.
　スタガ型の素子では、キャリアはソース電極から有機半導体のバルク内を流れ、次いで、チャネル形成部が存在するゲート絶縁層と有機半導体との界面を流れ、次いで、有機半導体のバルク内を流れてドレイン電極に至る。そのため、短チャネルにすると高い有機半導体バルクの抵抗値が、トランジスタ特性を顕著に低下させる因子となる。一方、コプラナー型の構造には、有機半導体バルクの抵抗が０になる利点があり、微細な素子には、コプラナー型の構造が広く用いられている。 In the staggered device, carriers flow from the source electrode through the bulk of the organic semiconductor, then through the interface between the gate insulating layer where the channel formation portion exists and the organic semiconductor, and then flow through the bulk of the organic semiconductor to the drain. To the electrode. Therefore, when the short channel is used, a high resistance value of the organic semiconductor bulk becomes a factor for remarkably reducing the transistor characteristics. On the other hand, the coplanar structure has an advantage that the resistance of the organic semiconductor bulk becomes 0, and the coplanar structure is widely used for fine elements.
　コプラナー型の構造では、スタガ型と比較して、ソース・ドレイン電極と有機半導体のチャネル形成部との接触面積が小さく、両者間のコンタクト抵抗が特性を決めるクリティカルな因子となる。コンタクト抵抗の問題を解決する手法として、ゲート絶縁層の表面に、有機絶縁材料に対する密着性に優れた金属材料の層を形成し、その横部に有機半導体とオーミック接触を形成する金属材料の層を形成してソース・ドレイン電極とした素子が知られている（特許文献１）。しかしながら、該金属材料の層はリフトオフ法で形成されており、フォトリソグラフィ工程及びマスク総数が増加してしまうという課題がある。 In the coplanar structure, the contact area between the source / drain electrodes and the channel formation part of the organic semiconductor is small compared to the staggered structure, and the contact resistance between them is a critical factor that determines the characteristics. As a method for solving the problem of contact resistance, a metal material layer having excellent adhesion to an organic insulating material is formed on the surface of the gate insulating layer, and a metal material layer that forms ohmic contact with the organic semiconductor is formed on the lateral portion thereof. There is known an element formed by forming a source / drain electrode (Patent Document 1). However, the metal material layer is formed by a lift-off method, and there is a problem that the photolithography process and the total number of masks increase.
　また、金属蒸気は高エネルギーを有し、接触した有機絶縁材料を損傷することがある。それゆえ、ゲート絶縁層として有機絶縁材料を用いた場合に、絶縁層上に直接ソース電極及びドレイン電極を物理気相成長（ＰＶＤ）させると、ゲート絶縁層の表面に欠陥が発生し、トランジスタ特性が低下するという課題がある。 Also, metal vapor has high energy and may damage the organic insulating material that comes into contact. Therefore, when an organic insulating material is used as the gate insulating layer, if the source electrode and the drain electrode are directly subjected to physical vapor deposition (PVD) on the insulating layer, defects are generated on the surface of the gate insulating layer, resulting in transistor characteristics. There is a problem that decreases.
　ソース・ドレイン電極形成時のゲート絶縁層表面に対するプロセスダメージを緩和するため、有機絶縁膜上に無機バリア層を形成し、該無機バリア層上にソース・ドレイン電極を形成した素子（特許文献２）、有機絶縁膜上に無機絶縁層を積層し、該無機絶縁層上にソース・ドレイン電極を形成した素子（特許文献３）が知られている。しかしながら、曲げ応力に劣る無機層が素子の全面に形成されており、これらの素子は柔軟性及び耐久性に劣る。 An element in which an inorganic barrier layer is formed on an organic insulating film and source / drain electrodes are formed on the inorganic barrier layer in order to reduce process damage to the surface of the gate insulating layer when the source / drain electrode is formed (Patent Document 2) A device (Patent Document 3) is known in which an inorganic insulating layer is stacked on an organic insulating film, and source / drain electrodes are formed on the inorganic insulating layer. However, an inorganic layer inferior in bending stress is formed on the entire surface of the element, and these elements are inferior in flexibility and durability.
特開2006-147613号公報JP 2006-147613 A 国際公開第2007/099689号International Publication No. 2007/099689 特開2006-013480号公報Japanese Unexamined Patent Publication No. 2006-013480
　本発明の目的は、大面積の素子の製造が容易であり、ソース電極及びドレイン電極を形成する際にゲート絶縁層表面を損傷せず、有機絶縁材料が有する柔軟性を損なわない、ボトムゲート・ボトムコンタクト構造の有機薄膜トランジスタの製造方法を提供することにある。また、本発明の目的は、かかる製造方法で製造されるボトムゲート・ボトムコンタクト構造の有機薄膜トランジスタを提供することにある。 It is an object of the present invention to easily manufacture a large-area element, does not damage the surface of the gate insulating layer when forming the source electrode and the drain electrode, and does not impair the flexibility of the organic insulating material. An object of the present invention is to provide a method for manufacturing an organic thin film transistor having a bottom contact structure. Another object of the present invention is to provide an organic thin film transistor having a bottom gate / bottom contact structure manufactured by such a manufacturing method.
　即ち、本発明は、ボトムゲート・ボトムコンタクト構造の有機薄膜トランジスタを製造する方法であって、
　ゲート電極、及び該ゲート電極を被覆し、有機絶縁材料を含むゲート絶縁層を形成する工程；
　該ゲート絶縁層上に塗布法、無電解めっき法又は原子層堆積法からなる群の内の一つを用いて導電性材料からなる第１導電層を成膜する工程；
　該第１導電層上に更に導電性材料からなる導電層を成膜後、該導電層を所定の形状にパターニングすることにより第２導電層を形成する工程；
　該第２導電層で被覆されていない第１導電層の部分を除去して、第１導電層及び第２導電層からなるソース電極及びドレイン電極を形成する工程；
　ソース電極、ドレイン電極、及び該ソース電極と該ドレイン電極に挟まれた領域のゲート絶縁層が被覆されるように、有機半導体層を形成する工程；
を有する方法を提供する。 That is, the present invention is a method of manufacturing an organic thin film transistor having a bottom gate / bottom contact structure,
Forming a gate electrode and a gate insulating layer covering the gate electrode and including an organic insulating material;
Forming a first conductive layer made of a conductive material on the gate insulating layer using one of the group consisting of a coating method, an electroless plating method, or an atomic layer deposition method;
Forming a second conductive layer by further forming a conductive layer made of a conductive material on the first conductive layer and then patterning the conductive layer into a predetermined shape;
Removing a portion of the first conductive layer not covered with the second conductive layer to form a source electrode and a drain electrode composed of the first conductive layer and the second conductive layer;
Forming an organic semiconductor layer so as to cover the source electrode, the drain electrode, and the gate insulating layer in a region sandwiched between the source electrode and the drain electrode;
A method is provided.
　ある一形態においては、第１導電層を成膜する工程は、酸化銀、酸化銅、酸化亜鉛、銀塩、銀及び銅からなる群から選ばれる少なくとも１種の材料を含む導電性材料の前駆体及び／又は前記導電性材料のナノ粒子を溶解もしくは分散させたインクを前記ゲート絶縁層上に塗布法で成膜し焼成することにより、前記導電性材料からなる導電層を得る工程である。 In one certain form, the process of forming a 1st conductive layer is a precursor of the electroconductive material containing the at least 1 sort (s) of material chosen from the group which consists of silver oxide, copper oxide, zinc oxide, silver salt, silver, and copper. In this step, an ink in which nanoparticles of the body and / or the conductive material are dissolved or dispersed is formed on the gate insulating layer by a coating method and baked to obtain a conductive layer made of the conductive material.
　ある一形態においては、前記第１導電層を成膜する工程は、タングステンアルコキサイドから作られたゾルゲル液を塗布法で該ゲート絶縁層上に成膜し、ゲル化したタングステンアルコキサイドを焼成処理して酸化タングステンからなる導電層を得る工程である。 In one embodiment, the step of forming the first conductive layer includes forming a sol-gel solution made from tungsten alkoxide on the gate insulating layer by a coating method, and forming the gelled tungsten alkoxide. In this step, a conductive layer made of tungsten oxide is obtained by baking treatment.
　ある一形態においては、タングステンアルコキサイドのゾルゲル液の溶媒は、プロピレングリコールモノメチルエーテルアセテート（PGMEA）もしくは、２，３，４，５，６－ペンタフルオロトルエンである。 In one embodiment, the solvent of the tungsten alkoxide sol-gel solution is propylene glycol monomethyl ether acetate (PGMEA) or 2,3,4,5,6-pentafluorotoluene.
　ある一形態においては、第１導電層の除去は、前記第２導電層をマスクとして用いて湿式エッチング法により行い、そのときに用いられるエッチング液はアルカリ溶液であり、第１導電層と第２導電層のエッチング選択比が１０：１以上である。 In one embodiment, the first conductive layer is removed by a wet etching method using the second conductive layer as a mask, and the etching solution used at that time is an alkaline solution, and the first conductive layer and the second conductive layer are removed. The etching selectivity of the conductive layer is 10: 1 or more.
　ボトムゲート・ボトムコンタクト構造の有機薄膜トランジスタのソース電極及びドレイン電極は第３導電層を備えており、第３導電層の形成は、パターニングされた第２導電層と、第１導電層の露出している部分の上に導電性材料の層を成膜した後、該導電性材料の層を第２導電層が完全に被覆されるようにパターニングすることにより行われる。 The source electrode and the drain electrode of the organic thin film transistor having the bottom gate / bottom contact structure include a third conductive layer. The third conductive layer is formed by exposing the patterned second conductive layer and the first conductive layer. After the conductive material layer is formed on the portion, the conductive material layer is patterned so that the second conductive layer is completely covered.
　また、本発明は、上記いずれかの方法により製造されるボトムゲート・ボトムコンタクト構造の有機薄膜トランジスタである。 Further, the present invention is an organic thin film transistor having a bottom gate / bottom contact structure manufactured by any one of the above methods.
本発明の第１の実施形態である有機薄膜トランジスタの構造を示す断面図である。It is sectional drawing which shows the structure of the organic thin-film transistor which is the 1st Embodiment of this invention. 図１の有機薄膜トランジスタの製造過程で形成される積層体の構造を示す断面図である。It is sectional drawing which shows the structure of the laminated body formed in the manufacture process of the organic thin-film transistor of FIG. 図１の有機薄膜トランジスタの製造過程で形成される積層体の構造を示す断面図である。It is sectional drawing which shows the structure of the laminated body formed in the manufacture process of the organic thin-film transistor of FIG. 図１の有機薄膜トランジスタの製造過程で形成される積層体の構造を示す断面図である。It is sectional drawing which shows the structure of the laminated body formed in the manufacture process of the organic thin-film transistor of FIG. 図１の有機薄膜トランジスタの製造過程で形成される積層体の構造を示す断面図である。It is sectional drawing which shows the structure of the laminated body formed in the manufacture process of the organic thin-film transistor of FIG. 図１の有機薄膜トランジスタの製造過程で形成される積層体の構造を示す断面図である。It is sectional drawing which shows the structure of the laminated body formed in the manufacture process of the organic thin-film transistor of FIG. 図１の有機薄膜トランジスタの製造過程で形成される積層体の構造を示す断面図である。It is sectional drawing which shows the structure of the laminated body formed in the manufacture process of the organic thin-film transistor of FIG. 本発明の第２の実施形態である有機薄膜トランジスタの構造を示す断面図である。It is sectional drawing which shows the structure of the organic thin-film transistor which is the 2nd Embodiment of this invention. 図８の有機薄膜トランジスタの製造過程で形成される積層体の構造を示す断面図である。It is sectional drawing which shows the structure of the laminated body formed in the manufacture process of the organic thin-film transistor of FIG. 図８の有機薄膜トランジスタの製造過程で形成される積層体の構造を示す断面図である。It is sectional drawing which shows the structure of the laminated body formed in the manufacture process of the organic thin-film transistor of FIG. 図８の有機薄膜トランジスタの製造過程で形成される積層体の構造を示す断面図である。It is sectional drawing which shows the structure of the laminated body formed in the manufacture process of the organic thin-film transistor of FIG. 図８の有機薄膜トランジスタの製造過程で形成される積層体の構造を示す断面図である。It is sectional drawing which shows the structure of the laminated body formed in the manufacture process of the organic thin-film transistor of FIG. 図８の有機薄膜トランジスタの製造過程で形成される積層体の構造を示す断面図である。It is sectional drawing which shows the structure of the laminated body formed in the manufacture process of the organic thin-film transistor of FIG. 図８の有機薄膜トランジスタの製造過程で形成される積層体の構造を示す断面図である。It is sectional drawing which shows the structure of the laminated body formed in the manufacture process of the organic thin-film transistor of FIG. 図８の有機薄膜トランジスタの製造過程で形成される積層体の構造を示す断面図である。It is sectional drawing which shows the structure of the laminated body formed in the manufacture process of the organic thin-film transistor of FIG. 図８の有機薄膜トランジスタの製造過程で形成される積層体の構造を示す断面図である。It is sectional drawing which shows the structure of the laminated body formed in the manufacture process of the organic thin-film transistor of FIG. ボトムゲート・ボトムコンタクト構造の有機薄膜トランジスタの層構成を示す断面図である。It is sectional drawing which shows the layer structure of the organic thin-film transistor of a bottom gate and a bottom contact structure. ボトムゲート・トップコンタクト構造の有機薄膜トランジスタの層構成を示す断面図である。It is sectional drawing which shows the layer structure of the organic thin-film transistor of a bottom gate top contact structure.
　本発明の有機薄膜トランジスタの製造方法は、基板１上に、ゲート電極２、及び該ゲート電極を被覆し、有機絶縁材料を含むゲート絶縁層３を形成する工程；
　該ゲート絶縁層３上に塗布法、無電解めっき法又は原子層堆積法からなる群から選択される一つの方法を用いて導電性材料からなる第１導電層４を成膜する工程；
　該第１導電層４上に更に導電性材料からなる導電層を成膜後、該導電層を所定の形状にパターニングすることにより第２導電層５を形成する工程；
　該第２導電層５で被覆されていない第１導電層４の部分を除去して、第１導電層４及び第２導電層５からなるソース電極及びドレイン電極を形成する工程；
　ソース電極、ドレイン電極、及び該ソース電極と該ドレイン電極に挟まれた領域のゲート絶縁層が被覆されるように、有機半導体層８を形成する工程；
を有する方法である。該方法は、以下に述べるような実施形態を包含する。 The method for producing an organic thin film transistor of the present invention includes forming a gate electrode 2 and a gate insulating layer 3 containing an organic insulating material on the substrate 1 so as to cover the gate electrode;
Forming a first conductive layer 4 made of a conductive material on the gate insulating layer 3 using one method selected from the group consisting of a coating method, an electroless plating method or an atomic layer deposition method;
Forming a second conductive layer 5 by further forming a conductive layer made of a conductive material on the first conductive layer 4 and then patterning the conductive layer into a predetermined shape;
Removing a portion of the first conductive layer 4 not covered with the second conductive layer 5 to form a source electrode and a drain electrode composed of the first conductive layer 4 and the second conductive layer 5;
Forming the organic semiconductor layer 8 so as to cover the source electrode, the drain electrode, and the gate insulating layer in a region sandwiched between the source electrode and the drain electrode;
It is the method which has. The method includes embodiments as described below.
　第１の実施形態
　本発明の第１の実施形態を、図１から図７を用いて説明する。 First Embodiment A first embodiment of the present invention will be described with reference to FIGS.
　図１は本発明の第１の実施形態である有機薄膜トランジスタの構造を示す断面図である。この有機薄膜トランジスタは、基板上１に、ゲート電極２及び該ゲート電極２を被覆するゲート絶縁層３を有し、該ゲート絶縁層３上に、第１導電層４及び第２導電層５からなるソース電極及びドレイン電極７を有し、該ソース・ドレイン電極の間に有機半導体層８を有し、該有機半導体層８を被覆する保護層１０を有する。 FIG. 1 is a sectional view showing the structure of an organic thin film transistor according to the first embodiment of the present invention. This organic thin film transistor has a gate electrode 2 and a gate insulating layer 3 covering the gate electrode 2 on a substrate 1, and comprises a first conductive layer 4 and a second conductive layer 5 on the gate insulating layer 3. A source electrode and a drain electrode 7 are provided, an organic semiconductor layer 8 is provided between the source and drain electrodes, and a protective layer 10 covering the organic semiconductor layer 8 is provided.
　有機薄膜トランジスタが折り曲げることが可能なフレキシブル素子である場合、基板１に用いられる材料としては、ポリイミド（ＰＩ）、ポリエチレンテレフタレート（ＰＥＴ）、ポリカーボネート（ＰＣ）、ポリエチレンナフタレート（ＰＥＮ）、芳香族ポリエーテルスルホン（ＰＥＳ）、液晶ポリマー（ＬＣＰ）等の樹脂、ステンレススチール等の金属箔、エッチングにより曲げる事が可能な薄さにしたガラス等が挙げられる。有機薄膜トランジスタが折り曲げることができない素子である場合、基板１に用いられる材料としては、ガラス、金属等が挙げられる。 When the organic thin film transistor is a flexible element that can be bent, materials used for the substrate 1 include polyimide (PI), polyethylene terephthalate (PET), polycarbonate (PC), polyethylene naphthalate (PEN), and aromatic polyether. Examples thereof include resins such as sulfone (PES) and liquid crystal polymer (LCP), metal foils such as stainless steel, and thinned glass that can be bent by etching. When the organic thin film transistor is an element that cannot be bent, examples of the material used for the substrate 1 include glass and metal.
　ゲート電極２の材料としては、導電性の高い金属及びその合金が好ましく用いられる。
より好ましくは、耐エレクトロ・ストレスマイグレーション性の高い高融点金属の合金、酸化物、窒化物である。また、金属表面の仕事関数を調整するため、必要に応じて、ゲート電極を積層構造にしたり、表面改質の処理を実施してもよい。本発明において、高融点金属とは、融点が１０００℃以上の金属を指す。 As a material of the gate electrode 2, a highly conductive metal and its alloy are preferably used.
More preferred are alloys, oxides and nitrides of refractory metals having high resistance to electro-stress migration. In addition, in order to adjust the work function of the metal surface, the gate electrode may have a laminated structure or a surface modification treatment as necessary. In the present invention, the refractory metal refers to a metal having a melting point of 1000 ° C. or higher.
　ゲート電極２は、例えばフォトリソグラフィ法、印刷法等のような、通常使用される方法によって基板１上に形成される。 The gate electrode 2 is formed on the substrate 1 by a commonly used method such as a photolithography method or a printing method.
　基板１とゲート電極２の間には、基板１に含まれる材料によるゲート電極の変質を防止するため、必要に応じて該基板１とゲート電極２との間に保護層を設けてもよい。 Between the substrate 1 and the gate electrode 2, a protective layer may be provided between the substrate 1 and the gate electrode 2 as necessary in order to prevent alteration of the gate electrode due to the material contained in the substrate 1.
　ゲート絶縁層３に含まれる有機絶縁材料としては、ＰＭＭＡ(ポリメチルメタクリレート)、ポリスチレン、ポリエチレン、ポリイミド、ポリビニルアルコール、ポリエステル、ポリ塩化ビニル、ポリビニルフェノール、シアノエチルプルラン等のフッ素原子を有さない樹脂、旭硝子社製「Ｃｙｔｏｐ」（登録商標）、Ｄｕｐｏｎｔ社製の「ＴＥＦＬＯＮ」（登録商標）等のフッ素系樹脂等が挙げられる。また、これらの樹脂に含まれる繰り返し単位を有する共重合体や該樹脂又は該共重合体を含む組成物を用いてもよい。該共重合体はスチレンから誘導される繰り返し単位等の分極を有さない繰り返し単位を含むことが好ましく、該組成物は、ポリスチレン等の分極を有さない高分子化合物を含むことが好ましい。 As the organic insulating material contained in the gate insulating layer 3, a resin having no fluorine atom, such as PMMA (polymethyl methacrylate), polystyrene, polyethylene, polyimide, polyvinyl alcohol, polyester, polyvinyl chloride, polyvinyl phenol, cyanoethyl pullulan, Examples thereof include fluorine resins such as “Cytop” (registered trademark) manufactured by Asahi Glass Co., Ltd. and “TEFLON” (registered trademark) manufactured by Dupont. Moreover, you may use the copolymer which has a repeating unit contained in these resin, the composition containing this resin or this copolymer. The copolymer preferably includes a repeating unit having no polarization such as a repeating unit derived from styrene, and the composition preferably includes a polymer compound having no polarization such as polystyrene.
　ゲート絶縁層３は、例えば有機絶縁材料と溶媒とを含む溶液を塗布し乾燥させる方法等によってゲート電極２上に積層される。溶液の塗布方法としては、スピンコート法、ディップコート法、ブレードコート法、キャピラリーコート法、スリットコート法、スプレーコート法、印刷法等が挙げられる。 The gate insulating layer 3 is laminated on the gate electrode 2 by, for example, a method of applying and drying a solution containing an organic insulating material and a solvent. Examples of the solution coating method include spin coating, dip coating, blade coating, capillary coating, slit coating, spray coating, and printing.
　ゲート絶縁層３の積層時には、必要に応じて、ゲート絶縁層３にコンタクトホールを形成する等のパターニングを施してもよい。有機絶縁材料は光もしくは熱により架橋し硬化することが好ましく、上記パターニングを行う場合は、有機絶縁材料が感光性を有していることがより好ましい。有機絶縁材料としては、分極を有さない材料が好ましく、誘電率が１．５（Ｆ／ｍ）以上の材料が好ましい。また、架橋により硬化する以外にも、有機絶縁材料を乾燥してフィルムを形成し、高い絶縁耐圧を確保してもよい。 When the gate insulating layer 3 is laminated, patterning such as forming a contact hole in the gate insulating layer 3 may be performed as necessary. The organic insulating material is preferably crosslinked and cured by light or heat, and when the patterning is performed, it is more preferable that the organic insulating material has photosensitivity. As the organic insulating material, a material having no polarization is preferable, and a material having a dielectric constant of 1.5 (F / m) or more is preferable. In addition to curing by crosslinking, the organic insulating material may be dried to form a film to ensure a high withstand voltage.
　有機薄膜トランジスタの特性の観点からは、有機絶縁材料が、有機薄膜トランジスタの製造に用いられる溶媒に対して不活性であり、かつ、不溶であることが好ましい。 From the viewpoint of the characteristics of the organic thin film transistor, it is preferable that the organic insulating material is inactive and insoluble with respect to the solvent used in the production of the organic thin film transistor.
　次に、ソース電極及びドレイン電極について説明する。本明細書では両者を総称してソース・ドレイン電極という。 Next, the source electrode and the drain electrode will be described. In this specification, both are collectively referred to as source / drain electrodes.
　ソース・ドレイン電極７は、以下の工程を経て形成される。即ち、
　前記ゲート絶縁層３上に塗布法、無電解めっき法又は原子層堆積法からなる群から選択される一つの方法を用いて導電性材料からなる第１導電層４を成膜する工程；
　該第１導電層４上に更に導電性材料からなる導電層を成膜後、該導電層を所定の形状にパターニングすることにより第２導電層５を形成する工程；及び
　該第２導電層５で被覆されていない第１導電層４の部分を除去して、第１導電層４及び第２導電層５からなるソース電極及びドレイン電極を形成する工程。 The source / drain electrode 7 is formed through the following steps. That is,
Forming a first conductive layer 4 made of a conductive material on the gate insulating layer 3 by using one method selected from the group consisting of a coating method, an electroless plating method or an atomic layer deposition method;
Forming a second conductive layer 5 by further forming a conductive layer made of a conductive material on the first conductive layer 4 and then patterning the conductive layer into a predetermined shape; and the second conductive layer 5 Removing a portion of the first conductive layer 4 not covered with the step of forming a source electrode and a drain electrode comprising the first conductive layer 4 and the second conductive layer 5.
　一つの好ましい態様において、前記第１導電層４を成膜する工程は、前記導電性材料の前駆体及び／又は前記導電性材料のナノ粒子を溶解もしくは分散させたインクを前記ゲート絶縁層３上に塗布法で成膜し焼成することにより、酸化銀、酸化銅、酸化亜鉛、銀塩、銀及び銅からなる群から選ばれる導電性材料からなる導電層を得る工程である。 In one preferred embodiment, the step of forming the first conductive layer 4 includes the step of depositing an ink in which the precursor of the conductive material and / or nanoparticles of the conductive material are dissolved or dispersed on the gate insulating layer 3. In this step, a conductive layer made of a conductive material selected from the group consisting of silver oxide, copper oxide, zinc oxide, silver salt, silver and copper is obtained by forming a film by a coating method and baking.
　一つの好ましい態様において、前記第１導電層４を成膜する工程は、タングステンアルコキサイドから作られたゾルゲル液を塗布法で該ゲート絶縁層３上に成膜し、ゲル化したタングステンアルコキサイドを焼成処理して酸化タングステンからなる導電層を得る工程である。この方法は、いわゆるゾル－ゲル法である。 In one preferred embodiment, the step of forming the first conductive layer 4 includes forming a gelled tungsten alkoxide by forming a sol-gel solution made from tungsten alkoxide on the gate insulating layer 3 by a coating method. In this step, the side is baked to obtain a conductive layer made of tungsten oxide. This method is a so-called sol-gel method.
　一つの好ましい態様において、前記タングステンアルコキサイドのゾルゲル液の溶媒は、プロピレングリコールモノメチルエーテルアセテート（PGMEA）もしくは、２，３，４，５，６－ペンタフルオロトルエンである。 In one preferred embodiment, the solvent of the tungsten alkoxide sol-gel solution is propylene glycol monomethyl ether acetate (PGMEA) or 2,3,4,5,6-pentafluorotoluene.
　更に、一つの好ましい態様において、前記第１導電層４の除去は、前記第２導電層５をマスクとして用いて湿式エッチング法により行い、そのときに用いられるエッチング液はアルカリ溶液であり、第１導電層４と第２導電層５のエッチング選択比が１０：１以上である。 Further, in one preferred embodiment, the removal of the first conductive layer 4 is performed by a wet etching method using the second conductive layer 5 as a mask, and the etching solution used at that time is an alkaline solution, The etching selectivity between the conductive layer 4 and the second conductive layer 5 is 10: 1 or more.
　以下にソース・ドレイン電極についてより具体的に説明する。ソース・ドレイン電極７は第１導電層４及び第２導電層５からなる積層構造をとる。ソース・ドレイン電極７を積層構造とすることでそれぞれの層に違った機能を持たせることが可能となる。例えば、第１導電層４の機能として、ゲート絶縁層３とソース・ドレイン電極７の密着性を上げる効果を持つ密着層としての機能や第２導電層５の金属原子がゲート絶縁層３へ拡散するのを防ぐバリア層としての機能を持たせたり、第１導電層４もしくは第２導電層５のどちらかに有機半導体層への電荷注入層の機能を持たせたりする事ができる様になる。 The source / drain electrodes will be described in more detail below. The source / drain electrode 7 has a laminated structure composed of the first conductive layer 4 and the second conductive layer 5. By making the source / drain electrodes 7 have a laminated structure, each layer can have a different function. For example, as a function of the first conductive layer 4, a function as an adhesion layer having an effect of improving the adhesion between the gate insulating layer 3 and the source / drain electrodes 7, and metal atoms of the second conductive layer 5 diffuse into the gate insulating layer 3. It is possible to provide a function as a barrier layer that prevents the occurrence of a failure, or to provide a function of a charge injection layer to the organic semiconductor layer in either the first conductive layer 4 or the second conductive layer 5. .
　有機絶縁層上に導電性材料からなる第１導電層４を成膜する（即ち、連続層として積層する）際には、塗布法、無電解めっき法又は原子層堆積法からなる群から選択される一つの方法を用いることが好ましく、塗布法を用いることがより好ましい。これらの方法を用いることにより、ゲート絶縁層３に含まれる有機絶縁材料に対するプロセスダメージが少なくなる。 When the first conductive layer 4 made of a conductive material is formed on the organic insulating layer (that is, laminated as a continuous layer), it is selected from the group consisting of a coating method, an electroless plating method, or an atomic layer deposition method. It is preferable to use one method, and it is more preferable to use a coating method. By using these methods, process damage to the organic insulating material contained in the gate insulating layer 3 is reduced.
　塗布法で第１導電層４を成膜するには、材料がインクで有る必要が有る。更に、本発明の効果を出すには、インク状態から後工程で不要箇所の除去が容易な無機の導電層になるのが良い。酸化タングステン、酸化銀、酸化銅、銀塩、銀及び銅は、比較的低温焼成でインク状態から無機の導電層にする事ができ、フレキシブル基板等の樹脂基板への適用も可能となる。この中でも、酸化タングステンはゾルゲル液にしてゾルゲル法で１５０～２００℃程度で容易に膜を得る事が可能であり、酸化銀は成膜後、エタノール液に浸漬し超音波処理を行う事で還元反応が起きる事が知られており、更には、還元反応の強いアルコール（例えば、トリエチレングリコールなど）を溶媒として用い２００℃未満の熱処理を行う事で還元されて銀になる事が知られている。更に最良の材料は、酸化タングステンであり第２導電層５で用いられる金属材料に対して比較的容易にエッチング選択比を取る事が可能である。 In order to form the first conductive layer 4 by the coating method, the material needs to be ink. Furthermore, in order to obtain the effect of the present invention, it is preferable to use an inorganic conductive layer in which unnecessary portions can be easily removed from the ink state in a subsequent process. Tungsten oxide, silver oxide, copper oxide, silver salt, silver and copper can be converted from an ink state to an inorganic conductive layer by firing at a relatively low temperature, and can be applied to a resin substrate such as a flexible substrate. Among these, tungsten oxide can be easily formed into a sol-gel solution at a temperature of about 150 to 200 ° C. by the sol-gel method. Silver oxide can be reduced by immersing it in an ethanol solution and subjecting it to ultrasonic treatment. It is known that the reaction occurs, and further, it is known that it is reduced to silver by performing a heat treatment at less than 200 ° C. using a highly reducing alcohol (for example, triethylene glycol) as a solvent. Yes. Further, the best material is tungsten oxide, and the etching selectivity can be obtained relatively easily with respect to the metal material used in the second conductive layer 5.
　本明細書でいうプロセスダメージとは、有機薄膜トランジスタを製造するための操作や処理がその構成部材を損傷することをいう。例えば、ゲート絶縁層上に直接金属等を物理気相成長（ＰＶＤ）させると、ゲート絶縁層に含まれている有機絶縁材料は金属蒸気のエネルギーによって損傷される。特に、ＰＶＤ法に含まれるスパッタリング法を用いた場合、損傷が顕著である。 As used herein, process damage means that operations and processes for producing an organic thin film transistor damage its constituent members. For example, when a metal or the like is directly deposited on the gate insulating layer by physical vapor deposition (PVD), the organic insulating material contained in the gate insulating layer is damaged by the energy of the metal vapor. In particular, when the sputtering method included in the PVD method is used, damage is significant.
　中でも、第１導電層４は、好ましくは、図２に示す様に、導電性材料と溶媒とを含む溶液を該ゲート絶縁層３上に塗布し乾燥させて成膜される。 Above all, the first conductive layer 4 is preferably formed by applying a solution containing a conductive material and a solvent on the gate insulating layer 3 and drying it as shown in FIG.
　第１導電層４は、例えば、金属アルコキサイドからゾルゲル法により形成することができるポリメタロキサンを含む。金属アルコキサイドの金属としては、チタン、アルミニウム、タングステン、ニオブ、ジルコニウム、バナジウム、タンタル等が挙げられる。 The first conductive layer 4 includes, for example, polymetalloxane that can be formed from metal alkoxide by a sol-gel method. Examples of the metal alkoxide include titanium, aluminum, tungsten, niobium, zirconium, vanadium, and tantalum.
　好ましい金属アルコキサイドは、タングステンアルコキサイドである。タングステン酸化物の層はゲート絶縁層３や第２導電層５に対して直交溶媒（オルトゴナル溶媒）であるアルカリ溶液でエッチングしやすく、不用になった第１導電層４は、ゲート絶縁層３表面から容易に除去することができる。 A preferred metal alkoxide is tungsten alkoxide. The tungsten oxide layer can be easily etched with an alkaline solution that is an orthogonal solvent (orthogonal solvent) with respect to the gate insulating layer 3 and the second conductive layer 5, and the first conductive layer 4 that has become unnecessary is the surface of the gate insulating layer 3. Can be easily removed.
　タングステンアルコキサイドとしては、タングステン（Ｖ）メトキサイド、タングステン（Ｖ）エトキサイド、タングステン（Ｖ）イソプロポキサイド、タングステン（Ｖ）ブトキサイド等が挙げられる。また、これらのタングステンアルコキサイドから得られる酸化タングステンにおけるタングステンの価数は５価である。タングステンアルコキサイドから得られる酸化タングステンは、アルカリ溶液に非常に良く溶ける為、エッチング時間を短くできるという利点もある。更に、エッチング時間が短かすぎる場合は、オゾンＵＶもしくはＯ２プラズマ等を当てることで酸化タングステンにおけるタングステンの価数を変えて溶解性を変化させることができるため、エッチング時間を長くすることも容易である。更には、塗布法に簡単なオゾンＵＶ処理のみで価数を上げて６価にできるため、反応性スパッタリング法などを用いずとも塗布法でＷＯ３の層を簡単に得ることができる。また、焼成温度も１５０℃と低温で処理出来るためフレキシブル基板等への適用も可能である。この様にして得られる第１導電層４の酸化タングステンにおけるタングステンの価数は、オゾンＵＶ処理によるＵＶ／Ｏ３の影響が強い第２導電層５の端部付近は６価の酸化タングステンであるＷＯ３が多く、ＵＶ／Ｏ３の影響が殆ど無い電極下は５価の成分が多い。従って、最終的に得られる酸化タングステンの第１導電層４は、５価と６価の組合せとなる。 Examples of tungsten alkoxide include tungsten (V) methoxide, tungsten (V) ethoxide, tungsten (V) isopropoxide, tungsten (V) butoxide, and the like. In addition, the valence of tungsten in tungsten oxide obtained from these tungsten alkoxides is pentavalent. Tungsten oxide obtained from tungsten alkoxide has the advantage that the etching time can be shortened because it dissolves very well in an alkaline solution. Furthermore, if the etching time is too short, the solubility can be changed by changing the valence of tungsten in tungsten oxide by applying ozone UV or O 2 plasma, etc., so it is easy to increase the etching time. It is. Furthermore, since the valence can be increased to 6 with only a simple ozone UV treatment for the coating method, the WO 3 layer can be easily obtained by the coating method without using a reactive sputtering method or the like. In addition, since the firing temperature can be as low as 150 ° C., it can be applied to a flexible substrate or the like. The tungsten valence in the tungsten oxide of the first conductive layer 4 obtained in this manner is hexavalent tungsten oxide in the vicinity of the end of the second conductive layer 5 where the influence of UV / O 3 due to ozone UV treatment is strong. There are many pentavalent components under the electrode where there is much WO 3 and there is almost no influence of UV / O 3 . Therefore, the first conductive layer 4 of tungsten oxide finally obtained is a combination of pentavalent and hexavalent.
　第１導電層４をゾルゲル法により形成する場合、用いられるゾルゲル液の溶媒は、使用する金属アルコキサイドを溶解又は分散し、室温で揮発性を示すものである。更には、下層であるゲート絶縁層３を溶かしたり膨潤させるなどのダメージを与えない直交溶媒（オルトゴナル溶媒）が好ましい。かかる溶媒には、例えば、プロピレングリコールモノメチルエーテルアセテート（以後、「ＰＧＭＥＡ」ということがある。）、フッ素原子を有する芳香族化合物が含まれる。また、ゲート絶縁層３がフッ素樹脂を有する場合、表面自由エネルギーが３０ｍＮ／ｍ以下の表面に均一に平滑膜を塗布形成する必要が有る為、最良の溶媒は、低表面張力でありフッ素原子を有する芳香族化合物（例えば、２，３，４，５，６－ペンタフルオロトルエン（別名：パーフルオロトルエン））である。 When the first conductive layer 4 is formed by the sol-gel method, the solvent of the sol-gel solution used dissolves or disperses the metal alkoxide used and exhibits volatility at room temperature. Further, an orthogonal solvent (orthogonal solvent) that does not cause damage such as dissolving or swelling the lower gate insulating layer 3 is preferable. Examples of such a solvent include propylene glycol monomethyl ether acetate (hereinafter sometimes referred to as “PGMEA”) and aromatic compounds having a fluorine atom. In addition, when the gate insulating layer 3 has a fluororesin, it is necessary to uniformly form a smooth film on the surface having a surface free energy of 30 mN / m or less. An aromatic compound (for example, 2,3,4,5,6-pentafluorotoluene (also known as perfluorotoluene)).
　また、ゾルゲル液には、形成される層の均一性及び表面平滑性を向上させるために金属アルコキシドの安定化剤を含有させてもよい。金属アルコキシドの安定化剤は、例えば、α－ヒドロキシケトン化合物、α－ヒドロキシケトン誘導体、エタノールアミン化合物、α－ジケトン化合物、α－ジケトン化合物誘導体、α－ヒドロキシカルボン酸化合物、β－ジケトン化合物からなる群より選ばれる少なくとも一種の化合物であることが好ましい。 The sol-gel solution may contain a metal alkoxide stabilizer in order to improve the uniformity and surface smoothness of the formed layer. Metal alkoxide stabilizers include, for example, α-hydroxyketone compounds, α-hydroxyketone derivatives, ethanolamine compounds, α-diketone compounds, α-diketone compound derivatives, α-hydroxycarboxylic acid compounds, and β-diketone compounds. It is preferably at least one compound selected from the group.
　その他、第１導電層４に含まれる材料としては、金属、金属の化合物、金属を含む合金、半導体、半導体の化合物、半導体を含む合金が挙げられる。金属の化合物には、上記金属酸化物、酸化物半導体、塩化銀等の銀塩が含まれる。 Other examples of the material included in the first conductive layer 4 include metals, metal compounds, alloys containing metals, semiconductors, semiconductor compounds, and alloys containing semiconductors. The metal compound includes silver salts such as the above metal oxides, oxide semiconductors, and silver chloride.
　金属としては、Ｔｉ、Ｔａ、Ｃｕ、Ｍｏ、Ｗ、Ａｕ、Ａｇ等が挙げられる。金属の化合物としては、ＴｉＮ、ＴａＮ、ＴｉＯ２、ＷＯ３、ＭｏＯ３、ＡｇＣｌ、Ａｇ２Ｏ、ＣｕＯ等が挙げられる。金属を含む合金としては、ＭｏＷ、ＴｉＷ、ＭｏＣｒ等が挙げられる。半導体としては、Ｓｉ、Ｇｅ、Ｇａ等が挙げられる。半導体の化合物としては、ＳｉＣ、ＧａＮ、ＧａＡｓ等が挙げられる。半導体を含む合金としては、ＷＳｉ、ＭｏＳｉ、ＴｉＳｉ等が挙げられる。酸化物半導体としては、インジウムスズ酸化物（ＩＴＯ）、インジウム亜鉛酸化物（ＩＺＯ）、インジウムガリウム亜鉛複合酸化物（ＩＧＺＯ）、酸化亜鉛（ＺｎＯ）、亜鉛スズ酸化物（ＺＴＯ）、ＣｄＳｎＯ、ＧａＳｎＯ、ＴｉＳｎＯ、ＣｕＡｌＯ、ＳｒＣｕＯ、ＬａＣｕＯＳ等が挙げられる。 Examples of the metal include Ti, Ta, Cu, Mo, W, Au, and Ag. Examples of the metal compound include TiN, TaN, TiO 2 , WO 3 , MoO 3 , AgCl, Ag 2 O, and CuO. Examples of the metal-containing alloy include MoW, TiW, and MoCr. Examples of the semiconductor include Si, Ge, and Ga. Examples of the semiconductor compound include SiC, GaN, and GaAs. Examples of the alloy containing a semiconductor include WSi, MoSi, TiSi and the like. Examples of the oxide semiconductor include indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc composite oxide (IGZO), zinc oxide (ZnO), zinc tin oxide (ZTO), CdSnO, GaSnO, TiSnO, CuAlO, SrCuO, LaCuOS, etc. are mentioned.
　中でも、Ｔｉ、Ｍｏ、Ｃｒ、Ｔａ、Ｗ、Ｎｉ、Ｐｄ、Ｃｕ、Ａｇ、Ａｕ、Ｐｔ、Ｉｒ、Ｃｏ、Ｆｅ、Ｖ、Ｚｒ、これらの金属の化合物、これらの金属のいずれかを含む合金、Ｓｉ、Ｂ、Ｇｅ、これらの半導体の化合物、これらの半導体のいずれかを含む合金が好ましく、酸化銀、酸化銅、酸化亜鉛、銀塩、銀、銅がより好ましく、酸化銀がさらに好ましい。 Among them, Ti, Mo, Cr, Ta, W, Ni, Pd, Cu, Ag, Au, Pt, Ir, Co, Fe, V, Zr, a compound of these metals, an alloy containing any of these metals, Si, B, Ge, a compound of these semiconductors, and an alloy containing any of these semiconductors are preferable, silver oxide, copper oxide, zinc oxide, silver salt, silver, and copper are more preferable, and silver oxide is more preferable.
　例えば、第１導電層４は、Ｔｉ、Ａｌ、Ｗ、Ｎｂ、Ｚｒ、Ｖ及びＴａから成る群から選択される金属の酸化物又は窒化物を含有する。 For example, the first conductive layer 4 contains an oxide or nitride of a metal selected from the group consisting of Ti, Al, W, Nb, Zr, V, and Ta.
　第１導電層４に含まれる材料としては、高融点金属の微粒子、酸化物、窒化物がより好ましく、融点が１０００℃以上である金属の微粒子、酸化物、窒化物がさらに好ましい。 The material contained in the first conductive layer 4 is more preferably refractory metal fine particles, oxides and nitrides, and even more preferably metal fine particles, oxides and nitrides having a melting point of 1000 ° C. or higher.
　ここで、金属の微粒子とは、粒径が１ｎｍ～１０００ｎｍの金属をいう。好ましくは、平均粒径が３～１００ｎｍのナノ粒子、更に好ましくは、３～３０ｎｍのナノ粒子である。 Here, the metal fine particles refer to metals having a particle diameter of 1 nm to 1000 nm. Nanoparticles having an average particle diameter of 3 to 100 nm are preferable, and nanoparticles having a particle diameter of 3 to 30 nm are more preferable.
　第１導電層４を形成するための導電性材料と溶媒とを含む溶液は、先に示した金属アルコキサイド以外では、例えば、ＩＴＯ、ＩＺＯ、ＩＧＺＯ、タングステン酸化物（ＷｘＯｙ）、チタン酸化物（ＴｉｘＯｙ）、チタンニオブ酸化物（ＴｉｘＮｂｙＯｚ）、酸化銀、酸化銅、酸化亜鉛、銀、銅のナノ粒子分散溶液又は銀塩である（式中、添え字のｘ、ｙ及びｚは０よりも大きい数である。）。又は、上記溶液は、これらの導電性材料の金属イオンを含有する無電解めっき液である。 The solution containing the conductive material and the solvent for forming the first conductive layer 4 is, for example, ITO, IZO, IGZO, tungsten oxide (W x O y ), titanium oxide other than the metal alkoxide shown above. Product (Ti x O y ), titanium niobium oxide (Ti x Nb y O z ), silver oxide, copper oxide, zinc oxide, silver, copper nanoparticle dispersion solution or silver salt (wherein the subscript x , Y and z are numbers greater than 0). Alternatively, the solution is an electroless plating solution containing metal ions of these conductive materials.
　第１導電層４は、導電性材料と溶媒とを含む分散液又はゾルゲル液を用い、スピンコート法、ディップコート法、ブレードコート法、キャピラリーコート法、スリットコート法、スプレーコート法、印刷法等の塗布手法により成膜することが好ましい。 The first conductive layer 4 uses a dispersion liquid or a sol-gel liquid containing a conductive material and a solvent, and spin coating, dip coating, blade coating, capillary coating, slit coating, spray coating, printing, etc. It is preferable to form a film by this coating method.
　又は、第１導電層４は、上記導電性材料の金属イオンを含有する無電解めっき液を用い、スピンコート法、ディップコート法、ブレードコート法、キャピラリーコート法、スリットコート法、スプレーコート法、印刷法でめっき触媒又はめっき触媒前駆体をゲート絶縁層上全面に塗布し、ゲート絶縁層等と共に該めっき触媒又はめっき触媒前駆体を上記無電解めっき液に浸漬して金属等を堆積させることにより形成してもよい。 Alternatively, the first conductive layer 4 is formed by using an electroless plating solution containing metal ions of the conductive material, spin coating method, dip coating method, blade coating method, capillary coating method, slit coating method, spray coating method, By applying a plating catalyst or a plating catalyst precursor on the entire surface of the gate insulating layer by a printing method, and immersing the plating catalyst or the plating catalyst precursor in the electroless plating solution together with the gate insulating layer or the like to deposit metal or the like. It may be formed.
　第１導電層４の積層方法は上記以外の方法であってもよく、ゲート絶縁膜へダメージを与えない方法ならば特に制限はない。また、原子層堆積（ＡＬＤ）法等により成長させて積層してもよい。ＡＬＤ法で積層する場合、第１導電層４に含まれる材料としては、Ｔｉ、Ｍｏ、Ｃｒ、Ｔａ、Ｗ、Ｎｉ、Ｐｄ、Ｃｕ、Ａｕ、Ｐｔ、Ｉｒ、Ｃｏ、Ｆｅ、Ｖ、Ｚｒ、これらの金属のいずれかを含む合金、これらの金属の酸化物又はこれらの金属の窒化物等が挙げられる。また、ＡＬＤ法に使用する金属化合物前駆体としては、窒化チタン（ＴｉＮ）の前駆体であるビス（ジエチルアミド）ビス（ジメチルアミド）チタニウム（ＩＶ）（Bis(diethylamido)bis(dimethylamido)titanium（ＩＶ））、窒化タンタル（ＴａＮ）の前駆体であるトリス（エミルメチルアミド）（ｔｅｒｔ－ブチルアミド）チタニウム（Tris(ethylmethylamido)(tert-butylimido)tantalum）等が挙げられる。 The method for laminating the first conductive layer 4 may be a method other than those described above, and is not particularly limited as long as it does not damage the gate insulating film. Alternatively, the layers may be grown by an atomic layer deposition (ALD) method or the like. When laminating by the ALD method, materials included in the first conductive layer 4 include Ti, Mo, Cr, Ta, W, Ni, Pd, Cu, Au, Pt, Ir, Co, Fe, V, Zr, and these And alloys containing any of these metals, oxides of these metals, or nitrides of these metals. In addition, as a metal compound precursor used in the ALD method, titanium nitride (TiN) precursor bis (diethylamido) bis (dimethylamido) titanium (IV) (Bis (diethylamido) bis (dimethylamido) titanium (IV)) And tris (ethylmethylamido) (tert-butylimido) tantalum) which are precursors of tantalum nitride (TaN).
　さらに、第１導電層４のフェルミレベルは、有機半導体層７の最高被占有軌道（ＨＯＭＯ）のエネルギーと同等かそれよりも深いことが好ましい。 Furthermore, it is preferable that the Fermi level of the first conductive layer 4 is equal to or deeper than the energy of the highest occupied orbit (HOMO) of the organic semiconductor layer 7.
　第１導電層４の層厚は、３～５００ｎｍが好ましく、３～５０ｎｍがより好ましい。 The layer thickness of the first conductive layer 4 is preferably 3 to 500 nm, and more preferably 3 to 50 nm.
　第２導電層５は、好ましくは、図３に示す様に、導電性材料を第１導電層４上に成膜し、その後パターニングして形成する。 The second conductive layer 5 is preferably formed by forming a conductive material on the first conductive layer 4 and then patterning it as shown in FIG.
　第２導電層５は、例えば、Ａｇ合金からスパッタリング法により成膜することができる。スパッタリング法を使用しても、パターニング前の第１導電層４がバリア層として機能するため、有機絶縁材料に対するプロセスダメージが小さくなる。Ａｇ合金としては、例えば、Ａｇ－Ｐｄ－Ｃｕ合金（ＡＰＣ）等が挙げられる。 The second conductive layer 5 can be formed by sputtering from an Ag alloy, for example. Even when the sputtering method is used, since the first conductive layer 4 before patterning functions as a barrier layer, process damage to the organic insulating material is reduced. Examples of the Ag alloy include an Ag—Pd—Cu alloy (APC).
　第２導電層５に含まれる材料は、Ａｇ合金以外にも、導電性が高い金属、その合金、その酸化物、その窒化物を用いることができる。中でも、Ａｇ、Ａｌ、Ａｕ、Ｃｄ、Ｃｏ、Ｃｒ、Ｃｕ、Ｆｅ、Ｍｇ、Ｍｏ、Ｎｉ、Ｐｂ、Ｐｄ、Ｐｔ、Ｓｎ、Ｔａ、Ｔｉ、Ｖ、Ｗ、Ｚｎ、Ｚｒ又はこれらの金属のいずれかを含む合金が好ましい。これらの金属は非常に一般的な金属であり、導電性が高く比較的容易にスパッタリングターゲットを入手する事が可能である。さらに、これらの金属の合金、酸化物、窒化物を成膜する場合にも、反応性スパッタにより容易にこれらの物を得る事が可能である。有機薄膜トランジスタの第１の実施形態においては、該材料が低コストで高いエレクトロ・ストレスマイグレーション耐性を有することが好ましい。該材料としては、Ｃｕ等が挙げられる。 As the material contained in the second conductive layer 5, a metal having high conductivity, an alloy thereof, an oxide thereof, or a nitride thereof can be used in addition to the Ag alloy. Among them, Ag, Al, Au, Cd, Co, Cr, Cu, Fe, Mg, Mo, Ni, Pb, Pd, Pt, Sn, Ta, Ti, V, W, Zn, Zr, or any of these metals Alloys containing are preferred. These metals are very common metals and have high conductivity, and it is possible to obtain a sputtering target relatively easily. Furthermore, even when these metal alloys, oxides, and nitrides are formed, these materials can be easily obtained by reactive sputtering. In the first embodiment of the organic thin film transistor, it is preferable that the material has low electrocost migration resistance at low cost. Examples of the material include Cu.
　第２導電層５に含まれる材料を、第１導電層４に含まれる材料との非限定的な組み合わせと共に、具体的に例示する。第２導電層５の導電性は第１導電層４の導電性よりも高くなることが好ましい。第２導電層５の導電性が第１電極層４の導電性よりも高くなることにより、第２導電層に、素子構成上不可欠なバスライン等、配線層としての機能を持たせることが可能となるためである。 The material included in the second conductive layer 5 is specifically illustrated along with a non-limiting combination with the material included in the first conductive layer 4. The conductivity of the second conductive layer 5 is preferably higher than the conductivity of the first conductive layer 4. Since the conductivity of the second conductive layer 5 is higher than the conductivity of the first electrode layer 4, it is possible to give the second conductive layer a function as a wiring layer such as a bus line that is indispensable for the element configuration. It is because it becomes.
［表１］
Figure JPOXMLDOC01-appb-I000001
[Table 1]
Figure JPOXMLDOC01-appb-I000001
　第２導電層５は、スパッタリング法以外に、物理気相成長（ＰＶＤ）法、化学気相成長（ＣＶＤ）法、無電解めっき法により積層してもよい。 The second conductive layer 5 may be laminated by a physical vapor deposition (PVD) method, a chemical vapor deposition (CVD) method, or an electroless plating method in addition to the sputtering method.
　微細なパターンを形成する観点からは、第２導電層５のパターニングは、フォトリソグラフィ法を用いて行う。その場合、図４に示す様に、第２導電層５の上にマスク９を形成し、マスクに被覆されていない第２導電層５の部分はエッチングして除去する。 From the viewpoint of forming a fine pattern, the patterning of the second conductive layer 5 is performed using a photolithography method. In that case, as shown in FIG. 4, a mask 9 is formed on the second conductive layer 5, and the portion of the second conductive layer 5 not covered with the mask is removed by etching.
　また、パターニングを簡便に行うためには、例えば、金属ナノ粒子分散溶液のような導電性材料と溶媒とを含む分散液又はゾルゲル液を、印刷法により第１導電層４上の必要な領域に直接塗布して、パターン化された第２導電層５を形成してもよい。又は、無電解めっき法を用いて、第１導電層４上の必要な領域に直接めっき触媒又はめっき触媒前駆体を印刷してパターニングを行い、第１導電層等と共に該めっき触媒又はめっき触媒前駆体を上記導電性材料の金属イオンを含有する無電解めっき液に浸漬して金属等を堆積し、パターン化された第２導電層５を形成してもよい。 In order to perform patterning easily, for example, a dispersion liquid or a sol-gel liquid containing a conductive material such as a metal nanoparticle dispersion solution and a solvent is applied to a necessary region on the first conductive layer 4 by a printing method. The patterned second conductive layer 5 may be formed by direct application. Alternatively, by using an electroless plating method, a plating catalyst or a plating catalyst precursor is directly printed on a necessary region on the first conductive layer 4 to perform patterning, and the plating catalyst or the plating catalyst precursor together with the first conductive layer and the like. The patterned second conductive layer 5 may be formed by immersing the body in an electroless plating solution containing metal ions of the conductive material and depositing metal or the like.
　これらのパターニングにより、図５に示す様に、ボトムゲート・ボトムコンタクト構造に適した所望の位置に第２導電層５を形成する。 By these patterning, as shown in FIG. 5, the second conductive layer 5 is formed at a desired position suitable for the bottom gate / bottom contact structure.
　第２導電層の層厚は、１０～１０００ｎｍであることが好ましく、５０ｎｍ～５００ｎｍがより好ましい。 The layer thickness of the second conductive layer is preferably 10 to 1000 nm, more preferably 50 to 500 nm.
　次に、パターニングされた第２導電層５をマスクとして、第２導電層５に対するエッチング選択比が高いアルカリエッチング液により第１導電層４の湿式エッチングを行い、第１導電層４を図６に示す様にパターニングして、ソース・ドレイン電極７を形成する。例えば、エッチング液のエッチング選択比が、第１導電層４：第２導電層５＝１０：１の場合、第１導電層４が５００ｎｍエッチングされる場合には、第２導電層５は、５０ｎｍしかエッチングされない。この場合、より好ましくは、第２導電層５が不溶であるエッチング液を用いる。 Next, using the patterned second conductive layer 5 as a mask, the first conductive layer 4 is wet-etched with an alkaline etchant having a high etching selectivity with respect to the second conductive layer 5, and the first conductive layer 4 is shown in FIG. The source / drain electrode 7 is formed by patterning as shown. For example, when the etching selectivity of the etching solution is the first conductive layer 4: second conductive layer 5 = 10: 1, when the first conductive layer 4 is etched by 500 nm, the second conductive layer 5 has a thickness of 50 nm. Only etched. In this case, more preferably, an etching solution in which the second conductive layer 5 is insoluble is used.
　アルカリエッチング液としては、水酸化カリウム（ＫＯＨ）の希釈水溶液、水酸化テトラメチルアンモニウム水溶液（ＴＭＡＨ）の希釈水溶液を用いてもよく、該溶液の濃度は、エッチングレートの調整のため如何ようにも変更が可能であるが０．１ｗｔ％以上であることが好ましい。また、市販のアルカリエッチング液を使用してもよく、具体例としては、メルテックス株式会社製「メルストリップ」（商品名）シリーズ等が挙げられる。より好ましいアルカリエッチング液は、金属イオンが無い水酸化テトラメチルアンモニウム水溶液（ＴＭＡＨ）の希釈水溶液である。 As the alkaline etching solution, a dilute aqueous solution of potassium hydroxide (KOH) or a dilute aqueous solution of tetramethylammonium hydroxide (TMAH) may be used, and the concentration of the solution may be adjusted in any way for adjusting the etching rate. Although it can be changed, it is preferably 0.1 wt% or more. A commercially available alkaline etching solution may be used, and specific examples include “Melstrip” (trade name) series manufactured by Meltex Co., Ltd. and the like. A more preferred alkaline etching solution is a dilute aqueous solution of tetramethylammonium hydroxide aqueous solution (TMAH) free from metal ions.
　所望のエッチング選択比を得る材料の組合せとしては、第１導電層４に酸化タングステンを用いた場合、第２導電層５には、金、銀、銅、又は銀と銅とパラジウム合金を用いる事がより好ましい。第１導電層４の酸化タングステンはＴＭＡＨに可溶であるが、金、銀、銅、又は銀と銅とパラジウム合金は不溶である。従って、非常に高い選択比を取る事が出来る。また、エッチング選択比を取るだけならば第２導電層５は前記以外のＡｌ、Ｃｄ、Ｃｏ、Ｃｒ、Ｆｅ、Ｍｇ、Ｍｏ、Ｎｉ、Ｐｂ、Ｐｄ、Ｐｔ、Ｓｎ、Ｔａ、Ｔｉ、Ｖ、Ｗ、Ｚｎ、Ｚｒ等でも良いがエッチングなどのプロセス的な側面や半導体層に対する電荷注入性の観点から好ましく無い。特に有機半導体への電荷注入性という側面では、金、銀、銅、又は銀と銅とパラジウム合金が好ましく、これらの金属は、塗布形成された有機半導体層８に焼成処理を行うことで、焼成を行わない場合と比べて有機半導体層８に対する高いホール注入性を得ることが出来る。 As a combination of materials for obtaining a desired etching selection ratio, when tungsten oxide is used for the first conductive layer 4, gold, silver, copper, or silver, copper and palladium alloy is used for the second conductive layer 5. Is more preferable. Tungsten oxide of the first conductive layer 4 is soluble in TMAH, but gold, silver, copper, or silver, copper, and a palladium alloy are insoluble. Therefore, a very high selection ratio can be obtained. Further, if only the etching selectivity is taken, the second conductive layer 5 is made of Al, Cd, Co, Cr, Fe, Mg, Mo, Ni, Pb, Pd, Pt, Sn, Ta, Ti, V, W other than those described above. Zn, Zr, and the like may be used, but are not preferable from the viewpoint of process such as etching and the charge injection property to the semiconductor layer. In particular, from the aspect of charge injection into an organic semiconductor, gold, silver, copper, or silver, copper, and a palladium alloy are preferable. These metals are fired by firing the organic semiconductor layer 8 that has been applied and formed. Compared with the case where no etching is performed, a higher hole injection property to the organic semiconductor layer 8 can be obtained.
　他のパターニング法として、アルカリ性のレジスト剥離液等を用い、レジスト剥離と同時に第１導電層４を剥離してもよい。 As another patterning method, an alkaline resist stripping solution or the like may be used, and the first conductive layer 4 may be stripped simultaneously with the resist stripping.
　パターニング前の第１導電層４は、第２導電層５を形成する際のプロセスダメージからゲート絶縁層３を保護する保護層としての機能を有している。また、第１導電層４は、ゲート絶縁層３と第２導電層５との密着性を高める機能を有している。更に、第１導電層４は、バリア層としての機能、有機半導体層８への電荷注入層としての機能等をも有している。 The first conductive layer 4 before patterning has a function as a protective layer that protects the gate insulating layer 3 from process damage when the second conductive layer 5 is formed. The first conductive layer 4 has a function of improving the adhesion between the gate insulating layer 3 and the second conductive layer 5. Further, the first conductive layer 4 has a function as a barrier layer, a function as a charge injection layer to the organic semiconductor layer 8, and the like.
　第１導電層４の保護層としての機能とは、有機薄膜トランジスタの製造プロセス中で発生する物理的及び化学的な外的因子から、構成部材を保護する機能をいう。例えば、有機絶縁層の場合、表面にダメージを受けると接触角や表面ラフネスが変化するが、保護層を設ける事によりこれらの変化を抑制する事が出来る。 The function of the first conductive layer 4 as a protective layer refers to a function of protecting the constituent members from physical and chemical external factors generated during the manufacturing process of the organic thin film transistor. For example, in the case of an organic insulating layer, the contact angle and the surface roughness change when the surface is damaged, but these changes can be suppressed by providing a protective layer.
　第１導電層４のゲート絶縁層と第２導電層との密着性を高める機能は、スクラッチ試験法による定量的な評価や、より簡単に確認する手法として「JIS　G0202」に定められている碁盤目試験により確認することができる。 The function of improving the adhesion between the gate insulating layer of the first conductive layer 4 and the second conductive layer is a grid board defined in “JIS G0202” as a quantitative evaluation by a scratch test method and a method for confirming more easily. It can be confirmed by an eye test.
　第１導電層４のバリア層としての機能とは、金属分子の周辺膜中への拡散防止層としての機能、エレクトロマイグレーション、ストレスマイグレーション耐性を付与する機能をいう。該機能は、ＸＰＳ、ＡＥＳ、ＴＯＦ－ＳＩＭＳ等により層厚方向に対する組成分析を実施し、有機絶縁膜中に金属原子が拡散してないかで確認できる。また、エレクトロマイグレーション及び、ストレスマイグレーションについては、電極の抵抗値に大きな変化が無く、有機薄膜トランジスタが所望の動きをしていれば問題が発生してないと判断できる。 The function of the first conductive layer 4 as a barrier layer refers to a function of preventing diffusion of metal molecules into a peripheral film, a function of imparting electromigration and stress migration resistance. The function can be confirmed by conducting a composition analysis in the layer thickness direction by XPS, AES, TOF-SIMS, or the like, and confirming that metal atoms are not diffused in the organic insulating film. In addition, regarding electromigration and stress migration, it can be determined that no problem has occurred if there is no significant change in the resistance value of the electrode and the organic thin film transistor is in a desired movement.
　ここで、エレクトロマイグレーションとは、大電流ストレスを受けた金属配線中の金属原子の移動が原因でボイド形成又は原子の蓄積が生じ、配線の抵抗値増加、断線及び配線間ショート等の故障を引き起こす現象をいう。また、ストレスマイグレーションとは、金属配線膜が保護層（パッシベーション膜）又は層間絶縁膜から受ける応力に起因して、高温処理又は温度サイクルによって配線内の原子移動が起こり、抵抗値が変動したり断線する現象をいう。 Here, electromigration is caused by the movement of metal atoms in a metal wiring subjected to a large current stress, resulting in void formation or accumulation of atoms, causing failures such as an increase in wiring resistance, disconnection, and short between wirings. A phenomenon. In addition, stress migration refers to the stress that the metal wiring film receives from the protective layer (passivation film) or interlayer insulating film, causing atomic movement in the wiring due to high-temperature treatment or temperature cycle, resulting in fluctuations in resistance value or disconnection. Refers to the phenomenon.
　有機半導体層８への電荷注入層としての機能とは、ホール又は電子を有機半導体層８へ注入する機能をいう。該機能は、有機薄膜トランジスタの電気特性評価により確認することができる。 The function as a charge injection layer into the organic semiconductor layer 8 refers to a function of injecting holes or electrons into the organic semiconductor layer 8. This function can be confirmed by evaluating electrical characteristics of the organic thin film transistor.
　有機半導体材料からなる有機半導体層８は、図７に示す様に、ソース電極とドレイン電極との間のゲート絶縁層３上に、例えば、スピンコート法により積層することができる。有機半導体層８の積層方法としては、スピンコート法、ディップコート法、ブレードコート法、キャピラリーコート法、スリットコート法、スプレーコート法、印刷法等の塗布手法が好ましい。 As shown in FIG. 7, the organic semiconductor layer 8 made of an organic semiconductor material can be laminated on the gate insulating layer 3 between the source electrode and the drain electrode by, for example, a spin coating method. As a method for laminating the organic semiconductor layer 8, a coating method such as a spin coating method, a dip coating method, a blade coating method, a capillary coating method, a slit coating method, a spray coating method, or a printing method is preferable.
　また、有機半導体材料としては、溶媒に溶解し、有機半導体層８を塗布法で形成できる材料であれば特に制限は無い。該有機半導体材料としては、６，１３－ビス（トリイソプロピルシリルエチニル）ペンタセン（6,13-bis(triisopropylsilylethynyl) pentacene(Tips-Pentacene))、１３，６－Ｎ－スルフィニルアセトアミドペンタセン（13,6-N-sulfinyl
acetamidopentacene(NSFAAP)）、６，１３－ジヒドロ－６，１３－メタノペンタセン－１５－オン（6,13-Dihydro-6,13-methanopentacene-15-one(DMP)）、ペンタセン－Ｎ－スルフィニル－ｎ－ブチルカルバマート付加物（Pentacene-N -sulfinyl-n -butylcarbamate adduct）、ペンタセン－Ｎ－スルフィニル－ｔｅｒｔ－ブチルカルバマート（Pentacene-
N -sulfinyl-tert -butylcarbamate）等のペンタセン前駆体、[１]ベンゾチエノ[３，２－ｂ]ベンゾチオフェン（[1]Benzothieno[3,2-b]benzothiophene (BTBT)）、ポルフィリ
ン、可溶性基としてアルキル基等を有するオリゴチオフェン等の低分子化合物、ポリ(3－ヘキシルチオフェン)(P3HT)等のポリチオフェン、フルオレンコポリマー(例えば、フルオレンジイル基とチオフェンジイル基とを有する共重合体)等の高分子化合物等が挙げられる。 The organic semiconductor material is not particularly limited as long as it is a material that can be dissolved in a solvent and form the organic semiconductor layer 8 by a coating method. Examples of the organic semiconductor material include 6,13-bis (triisopropylsilylethynyl) pentacene (6,13-bis (triisopropylsilylethynyl) pentacene (Tips-Pentacene)), 13,6-N-sulfinylacetamidopentacene (13,6- N-sulfinyl
acetamidopentacene (NSFAAP)), 6,13-dihydro-6,13-methanopentacene-15-one (6,13-Dihydro-6,13-methanopentacene-15-one (DMP)), pentacene-N-sulfinyl-n -Pentacene-N-sulfinyl-n-butylcarbamate adduct, Pentacene-N-sulfinyl-tert-butylcarbamate (Pentacene-
Pentacene precursors such as N-sulfinyl-tert-butylcarbamate), [1] benzothieno [3,2-b] benzothiophene ([1] Benzothieno [3,2-b] benzothiophene (BTBT)), porphyrin, soluble group Low molecular weight compounds such as oligothiophene having an alkyl group, etc., polythiophene such as poly (3-hexylthiophene) (P3HT), fluorene copolymers (for example, copolymers having a fluorenediyl group and a thiophene diyl group), etc. Examples thereof include molecular compounds.
　保護層１０は、図１に示す様に、有機半導体層８上に有機絶縁材料と溶媒とを含む溶液をスピンコート法等により塗布して積層することができる。この時、必要に応じて、保護層１０にコンタクトホール形成等のパターニングを施してもよい。パターン形成を行う場合は、保護層１０に含まれる有機絶縁材料が感光性を有していることが好ましい。有機絶縁材料としては、分極を有さない材料が好ましく、誘電率が１．５（Ｆ／ｍ）以上４．０（Ｆ／ｍ）以下の材料が望ましい。また、架橋で硬化させてもよく、有機絶縁材料を乾燥してフィルムを形成し、高い絶縁耐圧を確保してもよい。 As shown in FIG. 1, the protective layer 10 can be laminated by applying a solution containing an organic insulating material and a solvent on the organic semiconductor layer 8 by a spin coating method or the like. At this time, if necessary, the protective layer 10 may be subjected to patterning such as contact hole formation. When performing pattern formation, it is preferable that the organic insulating material contained in the protective layer 10 has photosensitivity. As the organic insulating material, a material having no polarization is preferable, and a material having a dielectric constant of 1.5 (F / m) or more and 4.0 (F / m) or less is desirable. Moreover, you may make it harden | cure by bridge | crosslinking, an organic insulating material may be dried and a film may be formed, and a high withstand voltage may be ensured.
　有機絶縁材料としては、ＰＭＭＡ(ポリメチルメタクリレート)、ポリスチレン、ポリエチレン、ポリイミド等のフッ素原子を有さない樹脂、例えば、旭硝子社製「Ｃｙｔｏｐ」（商品名）、Ｄｕｐｏｎｔ社製の「ＴＥＦＬＯＮ」（登録商標）等のフッ素系樹脂等が挙げられる。また、これらの樹脂に含まれる繰り返し単位を有する共重合体や該樹脂又は該共重合体を含む組成物を用いてもよい。該共重合体はスチレンから誘導される繰り返し単位等の分極を有さない繰り返し単位を含むことが好ましく、該組成物は、ポリスチレン等の分極を有さない高分子化合物を含むことが好ましい。 Organic insulating materials include PMMA (polymethyl methacrylate), polystyrene, polyethylene, polyimide-free resin, such as “Cytop” (trade name) manufactured by Asahi Glass Co., “TEFLON” (registered by DuPont) (registered) Trademark) and the like. Moreover, you may use the copolymer which has a repeating unit contained in these resin, the composition containing this resin or this copolymer. The copolymer preferably includes a repeating unit having no polarization such as a repeating unit derived from styrene, and the composition preferably includes a polymer compound having no polarization such as polystyrene.
　一つの態様において、本発明の有機薄膜トランジスタの製造方法は、前記ボトムゲート・ボトムコンタクト構造の有機薄膜トランジスタのソース電極及びドレイン電極は第３導電層６を備えており、第３導電層６の形成は、パターンニングした第２導電層５と、第１導電層４の露出している部分の上に導電性材料の層を成膜し、該層を第２導電層５が完全に被覆されるようにパターニングすることにより行われる。この態様について、以下に詳述する。 In one embodiment, the organic thin film transistor manufacturing method of the present invention is such that the source electrode and the drain electrode of the organic thin film transistor having the bottom gate / bottom contact structure include the third conductive layer 6, and the formation of the third conductive layer 6 is as follows. The patterned second conductive layer 5 and a layer of a conductive material are formed on the exposed portion of the first conductive layer 4 so that the second conductive layer 5 is completely covered with the layer. This is done by patterning. This aspect will be described in detail below.
　第２の実施形態
　次に、本発明の第２の実施形態を、図８から図１６を用いて説明する。 Second Embodiment Next, a second embodiment of the present invention will be described with reference to FIGS.
　図８は本発明の第２の実施形態である有機薄膜トランジスタの構造を示す断面図である。この有機薄膜トランジスタは、基板上１に、ゲート電極２及び該ゲート電極２を被覆するゲート絶縁層３を有し、該ゲート絶縁層３上に、第１導電層４、第２導電層５及び第３導電層６からなるソース電極及びドレイン電極を有し、該ソース・ドレイン電極７の間に有機半導体層８を有し、該有機半導体層８を被覆する保護層１０を有する。 FIG. 8 is a sectional view showing the structure of an organic thin film transistor according to the second embodiment of the present invention. This organic thin film transistor has a gate electrode 2 and a gate insulating layer 3 covering the gate electrode 2 on a substrate 1, and a first conductive layer 4, a second conductive layer 5, and a second conductive layer are formed on the gate insulating layer 3. A source electrode and a drain electrode made of three conductive layers 6 are provided, an organic semiconductor layer 8 is provided between the source / drain electrodes 7, and a protective layer 10 covering the organic semiconductor layer 8 is provided.
　この有機薄膜トランジスタの基板１、ゲート電極２、ゲート絶縁層３に含まれる材料及び形成方法は、上記第１の実施形態と同様である。 The materials included in the substrate 1, the gate electrode 2, and the gate insulating layer 3 and the formation method of the organic thin film transistor are the same as those in the first embodiment.
　次に、ソース・ドレイン電極について説明する。ソース・ドレイン電極７は第１導電層４、第２導電層５及び第３導電層６からなる。有機絶縁層上に第１導電層を積層する際には、塗布法、無電解めっき法又は原子層堆積法を用いることが好ましく、塗布法を用いることがより好ましい。これらの方法を用いることにより、ゲート絶縁層３に含まれる有機絶縁材料に対するプロセスダメージが少なくなる。 Next, the source / drain electrodes will be described. The source / drain electrode 7 includes a first conductive layer 4, a second conductive layer 5, and a third conductive layer 6. When laminating the first conductive layer on the organic insulating layer, a coating method, an electroless plating method or an atomic layer deposition method is preferably used, and a coating method is more preferably used. By using these methods, process damage to the organic insulating material contained in the gate insulating layer 3 is reduced.
　中でも、第１導電層４は、好ましくは、図９に示す様に、導電性材料と溶媒とを含む溶液を該ゲート絶縁層３上に塗布し乾燥させて連続層を積層し、その後パターニングして形成する。第１導電層４に含まれる材料、第１導電層４を積層する方法及び第１導電層４の機能は、上記第１の実施形態と同様である。 Among them, the first conductive layer 4 is preferably coated with a solution containing a conductive material and a solvent on the gate insulating layer 3 and dried to form a continuous layer as shown in FIG. Form. The material contained in the first conductive layer 4, the method of laminating the first conductive layer 4, and the function of the first conductive layer 4 are the same as those in the first embodiment.
　第２導電層５は、好ましくは、図１０に示す様に、第１導電層４上に連続層として積層する。その後、第２導電層５は、図１１に示す様に、マスク９を用いてパターニングされて、図１２に示す様に、所望の位置に形成される。第２導電層５に含まれる材料及び第２導電層５の形成及びパターニングの方法は、上記第１の実施形態と同様である。 The second conductive layer 5 is preferably laminated as a continuous layer on the first conductive layer 4 as shown in FIG. Thereafter, the second conductive layer 5 is patterned using a mask 9 as shown in FIG. 11, and formed at a desired position as shown in FIG. The material contained in the second conductive layer 5 and the method of forming and patterning the second conductive layer 5 are the same as those in the first embodiment.
　第３導電層６は、好ましくは、図１３に示す様に、第１導電層４及び第２導電層５上に連続層として積層し、その後パターニングして形成する。 The third conductive layer 6 is preferably formed by laminating as a continuous layer on the first conductive layer 4 and the second conductive layer 5 and then patterning as shown in FIG.
　第３導電層６は、例えばＴａＮからスパッタリング法により積層することができる。その後、印刷法等により、積層された連続層上にマスクを形成し、マスクに被覆されていない第３導電層６（ＴａＮ膜）の部分を湿式エッチングにより除去してパターニングが行われる。ＴａＮ用エッチング液としては、例えば、シグマ・アルドリッチ社製の「667501」（商品名）等が用いられる。該パターニングにより、図１４に示す様に、第２導電層５の上に第３導電層６を形成する。 The third conductive layer 6 can be laminated by sputtering from TaN, for example. Thereafter, a mask is formed on the stacked continuous layers by a printing method or the like, and the patterning is performed by removing the portion of the third conductive layer 6 (TaN film) not covered with the mask by wet etching. As an etching solution for TaN, for example, “667501” (trade name) manufactured by Sigma-Aldrich is used. By the patterning, a third conductive layer 6 is formed on the second conductive layer 5 as shown in FIG.
　例えば、第３導電層６は、第２導電層５の上面及び側面を被覆し、端部が第１導電層の上面と接するように形成される。 For example, the third conductive layer 6 is formed so as to cover the upper surface and the side surface of the second conductive layer 5 and the end portion is in contact with the upper surface of the first conductive layer.
　第３導電層６に含まれる材料は、ＴａＮ以外にも、金属、金属の化合物、金属を含む合金、半導体、半導体の化合物、半導体を含む合金、酸化物半導体等を用いることができる。金属、金属の化合物、金属を含む合金、半導体、半導体の化合物、半導体を含む合金、酸化物半導体の具体例としては、第１導電層４に含まれていてもよい金属、金属の化合物、金属を含む合金、半導体、半導体の化合物、半導体を含む合金、酸化物半導体と同じ材料が挙げられる。これらの中でも、Ｔｉ、Ｍｏ、Ｃｒ、Ｔａ、Ｗ、Ｎｉ、Ｐｄ、Ｃｕ、Ａｕ、Ｐｔ、Ｉｒ、Ｃｏ、Ｆｅ、Ｖ、Ｚｒ、これらの金属の化合物、これらの金属の酸化物又は窒化物、これらの金属のいずれかを含む合金、Ｓｉ、Ｂ、Ｇｅ、これらの半導体の化合物、これらの半導体を含む合金、ＺｎＯ、ＺＴＯ（ＺｎＳｎＯ）、ＣｄＳｎＯ、ＧａＳｎＯ、ＴｌＳｎＯ、ＩｎＧａＺｎＯ、ＣｕＡｌＯ、ＳｒＣｕＯ、ＬａＣｕＯＳ等に代表される酸化物半導体が好ましい。 As the material contained in the third conductive layer 6, in addition to TaN, a metal, a metal compound, a metal-containing alloy, a semiconductor, a semiconductor compound, a semiconductor-containing alloy, an oxide semiconductor, or the like can be used. Specific examples of metals, metal compounds, metal-containing alloys, semiconductors, semiconductor compounds, semiconductor-containing alloys, and oxide semiconductors include metals that may be included in the first conductive layer 4, metal compounds, and metals. The same material as an alloy, a semiconductor, a compound of a semiconductor, an alloy including a semiconductor, and an oxide semiconductor is included. Among these, Ti, Mo, Cr, Ta, W, Ni, Pd, Cu, Au, Pt, Ir, Co, Fe, V, Zr, compounds of these metals, oxides or nitrides of these metals, Alloys containing any of these metals, Si, B, Ge, compounds of these semiconductors, alloys containing these semiconductors, ZnO, ZTO (ZnSnO), CdSnO, GaSnO, TlSnO, InGaZnO, CuAlO, SrCuO, LaCuOS, etc. An oxide semiconductor typified by is preferable.
　これらの金属や半導体を用いれば、第２導電層５に用いる銀や銀とパラジウムと銅の合金よりも高いマイグレーション性能を得る事ができるため、バリア層としての機能をもつことができる。更に好ましくは、酸化物半導体材料やＰｄ、Ａｕ、Ｐｔ、Ｉｒなどの仕事関数が高い材料が電荷注入性の面からもより好ましい。 If these metals and semiconductors are used, a migration performance higher than that of silver or silver / palladium / copper alloy used in the second conductive layer 5 can be obtained, and thus a function as a barrier layer can be obtained. More preferably, an oxide semiconductor material or a material having a high work function such as Pd, Au, Pt, or Ir is more preferable from the viewpoint of charge injection.
　第２導電層５の導電性は第３導電層６の導電性よりも高くなることが好ましい。第２導電層５の導電性が第３電極層６の導電性よりも高くなることにより、第２導電層に、素子構成上不可欠なバスライン等、配線層としての機能を持たせることが可能となるためである。 The conductivity of the second conductive layer 5 is preferably higher than that of the third conductive layer 6. Since the conductivity of the second conductive layer 5 is higher than the conductivity of the third electrode layer 6, it is possible to give the second conductive layer a function as a wiring layer such as a bus line that is indispensable for the element configuration. It is because it becomes.
　スパッタリング法以外にも、物理気相成長（ＰＶＤ）法、化学気相成長（ＣＶＤ）法又は無電解めっき法により第３導電層６を積層してよい。第３導電層６は、原子層堆積（ＡＬＤ）法等により成長させて積層してもよい。ＡＬＤ法で積層する場合、導電層６に含まれる材料としては、Ｔｉ、Ｍｏ、Ｃｒ、Ｔａ、Ｗ、Ｎｉ、Ｐｄ、Ｃｕ、Ａｕ、Ｐｔ、Ｉｒ、Ｃｏ、Ｆｅ、Ｖ、Ｚｒ、これらの金属のいずれかを含む合金、これらの金属の酸化物又はこれらの金属の窒化物等が挙げられる。 Besides the sputtering method, the third conductive layer 6 may be laminated by a physical vapor deposition (PVD) method, a chemical vapor deposition (CVD) method, or an electroless plating method. The third conductive layer 6 may be grown and stacked by an atomic layer deposition (ALD) method or the like. In the case of laminating by the ALD method, materials contained in the conductive layer 6 include Ti, Mo, Cr, Ta, W, Ni, Pd, Cu, Au, Pt, Ir, Co, Fe, V, Zr, and these metals. An alloy containing any of the above, oxides of these metals, nitrides of these metals, and the like.
　その後、該第３導電層６をフォトリソグラフィによるパターニングや印刷法でエッチング保護層を直接印刷することによりパターニングしてもよい。 Thereafter, the third conductive layer 6 may be patterned by directly printing an etching protective layer by patterning by photolithography or printing.
　また、パターニングを簡便に行うためには、例えば、金属微粒子分散溶液のような導電性材料と溶媒とを含む分散溶液又はゾルゲル液を、印刷法により第２導電層５上に直接塗布して、第３導電層６を形成してもよい。又は、無電解めっき法を用いて、第２導電層５上に直接めっき触媒又はめっき触媒前駆体を印刷して、第２導電層等と共に該めっき触媒又はめっき触媒前駆体を上記導電性材料の金属イオンを含有する無電解めっき液に浸漬して金属等を堆積し、第３導電層６を形成してもよい。 In order to easily perform patterning, for example, a dispersion solution or a sol-gel solution containing a conductive material such as a metal fine particle dispersion solution and a solvent is directly applied on the second conductive layer 5 by a printing method, The third conductive layer 6 may be formed. Alternatively, a plating catalyst or a plating catalyst precursor is printed directly on the second conductive layer 5 by using an electroless plating method, and the plating catalyst or the plating catalyst precursor is made of the conductive material together with the second conductive layer or the like. The third conductive layer 6 may be formed by depositing a metal or the like by dipping in an electroless plating solution containing metal ions.
　第３導電層の層厚は、１０～５００ｎｍであることが好ましく、１０～１００ｎｍであることがより好ましい。 The layer thickness of the third conductive layer is preferably 10 to 500 nm, and more preferably 10 to 100 nm.
　次に、パターニングされた第３導電層６をマスクとして、第３導電層６に対するエッチング選択比が高いアルカリエッチング液により第１導電層４の湿式エッチングを行い、第１導電層４を図１５に示す様にパターニングして、ソース・ドレイン電極７を形成する。例えば、エッチング液のエッチング選択比が、第１導電層４：第３導電層６＝１０：１の場合、第１導電層４が５００ｎｍエッチングされる場合には、第３導電層６は、５０ｎｍしかエッチングされない。この場合、より好ましくは、第３導電層６が不溶であるエッチング液を用いる。 Next, using the patterned third conductive layer 6 as a mask, the first conductive layer 4 is wet-etched with an alkaline etchant having a high etching selectivity with respect to the third conductive layer 6, and the first conductive layer 4 is shown in FIG. The source / drain electrode 7 is formed by patterning as shown. For example, when the etching selectivity of the etching solution is the first conductive layer 4: the third conductive layer 6 = 10: 1, when the first conductive layer 4 is etched by 500 nm, the third conductive layer 6 has a thickness of 50 nm. Only etched. In this case, more preferably, an etching solution in which the third conductive layer 6 is insoluble is used.
　アルカリエッチング液としては、水酸化カリウム（ＫＯＨ）の希釈水溶液、水酸化テトラメチルアンモニウム水溶液（ＴＭＡＨ）の希釈水溶液を用いてもよく、該溶液の濃度は、エッチングレートの調整のため如何様にも変更が可能であるが０．１ｗｔ％以上であることが好ましい。また、市販のアルカリエッチング液を使用してもよく、メルテックス株式会社製メルストリップシリーズ等が挙げられる。より好ましいアルカリエッチング液は、金属イオンが無い水酸化テトラメチルアンモニウム水溶液（ＴＭＡＨ）の希釈水溶液である。 As the alkaline etching solution, a dilute aqueous solution of potassium hydroxide (KOH) or a dilute aqueous solution of tetramethylammonium hydroxide (TMAH) may be used, and the concentration of the solution may be set in any way for adjusting the etching rate. Although it can be changed, it is preferably 0.1 wt% or more. Moreover, you may use a commercially available alkaline etching liquid and the Melstrip series by Meltex, etc. are mentioned. A more preferred alkaline etching solution is a dilute aqueous solution of tetramethylammonium hydroxide aqueous solution (TMAH) free from metal ions.
　他のパターニング法として、アルカリ系エッチング液であるＴａＮ用エッチング液にて第３導電層６及び第１導電層４を同時に剥離してパターニングしてもよい。 As another patterning method, the third conductive layer 6 and the first conductive layer 4 may be simultaneously peeled and patterned with a TaN etchant that is an alkaline etchant.
　第３導電層６は第２導電層５の上面及び側面を覆い、バリア層としての機能を有している。
また、第３導電層６は第２導電層５の上面及び側面を覆い、有機半導体層８への電荷注入層としての機能を有している。 The third conductive layer 6 covers the upper surface and side surfaces of the second conductive layer 5 and has a function as a barrier layer.
The third conductive layer 6 covers the upper surface and the side surface of the second conductive layer 5 and functions as a charge injection layer to the organic semiconductor layer 8.
　またこの時、第３導電層６が第２導電層５の側面を確実に被覆する為、第３導電層６は第２導電層５に対して１辺あたり１０ｎｍ以上はみ出していることが好ましく、１０００ｎｍ程度はみ出していることがより好ましい。このため、必然的に第１導電層４も第３導電層６と同等量、第２導電層５からはみ出す構造となる。 At this time, in order for the third conductive layer 6 to reliably cover the side surface of the second conductive layer 5, the third conductive layer 6 preferably protrudes 10 nm or more per side with respect to the second conductive layer 5, More preferably, it protrudes about 1000 nm. Therefore, the first conductive layer 4 inevitably has a structure that protrudes from the second conductive layer 5 in the same amount as the third conductive layer 6.
　有機半導体材料からなる有機半導体層８は、図１６に示す様に、ソース電極とドレイン電極との間のゲート絶縁層上に積層することができる。有機半導体層８に含まれる材料及び有機半導体層８の形成方法は、上記第１の実施形態と同様である。 The organic semiconductor layer 8 made of an organic semiconductor material can be laminated on the gate insulating layer between the source electrode and the drain electrode as shown in FIG. The material contained in the organic semiconductor layer 8 and the method for forming the organic semiconductor layer 8 are the same as those in the first embodiment.
　保護層１０は、図８に示す通り、有機半導体層７上に有機絶縁材料と溶媒とを含む溶液を塗布して積層することができる。保護層１０に含まれる材料及び保護層１０の形成方法は、上記第１の実施形態と同様である。 The protective layer 10 can be laminated by applying a solution containing an organic insulating material and a solvent on the organic semiconductor layer 7 as shown in FIG. The material contained in the protective layer 10 and the method for forming the protective layer 10 are the same as those in the first embodiment.
　本発明の有機薄膜トランジスタは、アクティブマトリックス表示装置、回路に用いることができる。尚、文中で挙げた印刷法とは、パターン塗布可能なスリットコート法、キャピラリーコート法、ブレードコート法、スプレーコート法、インクジェット法に代表される無版印刷法とフレキソ印刷、グラビア印刷、オフセット印刷、スクリーン印刷、マイクロコンタクト印刷、ナノインプリントに代表される有版印刷法である。 The organic thin film transistor of the present invention can be used for active matrix display devices and circuits. In addition, the printing methods mentioned in the text are the slit coating method, the capillary coating method, the blade coating method, the spray coating method, the plateless printing method represented by the ink jet method, the flexographic printing, the gravure printing, and the offset printing. Plate printing methods represented by screen printing, microcontact printing, and nanoimprinting.
　合成例１
（高分子化合物１の合成）
　スチレン（和光純薬製）２．０６ｇ、２，３，４，５，６－ペンタフルオロスチレン（アルドリッチ製）２．４３ｇ、２－〔Ｏ－［１’－メチルプロピリデンアミノ］カルボキシアミノ〕エチル－メタクリレート（昭和電工製、商品名「カレンズＭＯＩ－ＢＭ」）１．００ｇ、２，２’－アゾビス（２－メチルプロピオニトリル）０．０６ｇ、２－ヘプタノン（和光純薬製）１４．０６ｇを、５０ｍｌ耐圧容器（エース製）に入れ、窒素をバブリングした後、密栓し、６０℃のオイルバス中で４８時間重合させて、高分子化合物１が溶解している粘稠な２－ヘプタノン溶液を得た。高分子化合物１は下記繰り返し単位を有している。ここで、（　）の添え数字は繰り返し単位のモル分率を示している。 Synthesis example 1
(Synthesis of polymer compound 1)
Styrene (made by Wako Pure Chemical Industries) 2.06 g, 2,3,4,5,6-pentafluorostyrene (made by Aldrich) 2.43 g, 2- [O- [1′-methylpropylideneamino] carboxyamino] ethyl -Methacrylate (made by Showa Denko, trade name “Karenz MOI-BM”) 1.00 g, 2,2′-azobis (2-methylpropionitrile) 0.06 g, 2-heptanone (made by Wako Pure Chemical Industries) 14.06 g Is put in a 50 ml pressure vessel (Ace), bubbled with nitrogen, sealed, and polymerized in an oil bath at 60 ° C. for 48 hours to give a viscous 2-heptanone solution in which the polymer compound 1 is dissolved. Got. The high molecular compound 1 has the following repeating unit. Here, the number in parentheses indicates the mole fraction of the repeating unit.
Figure JPOXMLDOC01-appb-C000002
 　　高分子化合物１
Figure JPOXMLDOC01-appb-C000002
 Polymer compound 1
　得られた高分子化合物１の標準ポリスチレンから求めた重量平均分子量は、３２８００であった（島津製ＧＰＣ、「Ｔｓｋｇｅｌ　ｓｕｐｅｒ　ＨＭ－Ｈ」１本＋「Ｔｓｋｇｅｌ　ｓｕｐｅｒ　Ｈ２０００」１本、移動相＝ＴＨＦ）。 The weight average molecular weight calculated | required from the standard polystyrene of the obtained high molecular compound 1 was 32800 (Shimadzu GPC, one "Tskel super HM-H" + one "Tskel super H2000", mobile phase = THF) .
　合成例２
（高分子化合物２の合成）
　４－アミノスチレン（アルドリッチ製）３．５０ｇ、２，３，４，５，６－ペンタフルオロスチレン（アルドリッチ製）１３．３２ｇ、２，２’－アゾビス（２－メチルプロピオニトリル）０．０８ｇ、２－ヘプタノン（和光純薬製）２５．３６ｇを、１２５ｍｌ耐圧容器（エース製）に入れ、窒素をバブリングした後、密栓し、６０℃のオイルバス中で４８時間重合させて、高分子化合物２が溶解している粘稠な２－ヘプタノン溶液を得た。
高分子化合物２は下記繰り返し単位を有している。ここで、（　）の添え数字は繰り返し単位のモル分率を示している。 Synthesis example 2
(Synthesis of polymer compound 2)
4-aminostyrene (manufactured by Aldrich) 3.50 g, 2,3,4,5,6-pentafluorostyrene (manufactured by Aldrich) 13.32 g, 2,2′-azobis (2-methylpropionitrile) 0.08 g 25-36 g of 2-heptanone (manufactured by Wako Pure Chemical Industries, Ltd.) was placed in a 125 ml pressure vessel (manufactured by Ace), bubbled with nitrogen, sealed, and polymerized in an oil bath at 60 ° C. for 48 hours to obtain a polymer A viscous 2-heptanone solution in which 2 was dissolved was obtained.
The high molecular compound 2 has the following repeating unit. Here, the number in parentheses indicates the mole fraction of the repeating unit.
Figure JPOXMLDOC01-appb-C000003
 高分子化合物２
Figure JPOXMLDOC01-appb-C000003
 Polymer compound 2
　得られた高分子化合物２の標準ポリスチレンから求めた重量平均分子量は、１３２０００であった（島津製ＧＰＣ、「Ｔｓｋｇｅｌ　ｓｕｐｅｒ　ＨＭ－Ｈ」１本＋「Ｔｓｋｇｅｌ　ｓｕｐｅｒ　Ｈ２０００」１本、移動相＝ＴＨＦ）。 The weight average molecular weight calculated | required from the standard polystyrene of the obtained high molecular compound 2 was 132000 (Shimadzu GPC, "Tskel super HM-H" one + "Tskel super H2000" one, mobile phase = THF) .
　合成例３
（高分子化合物３の合成）
　９，９－ジ－ｎ－オクチルフルオレン－２，７－ジ（エチレンボロネート）６．４０ｇ、及び５，５’－ジブロモ－２，２’－バイチオフェン４．００ｇを含むトルエン（８０ｍＬ）中に、窒素下において、テトラキス（トリフェニルホスフィン）パラジウム０．１８ｇ、メチルトリオクチルアンモニウムクロライド（Ａｌｄｒｉｃｈ製、商品名「Ａｌｉｑｕａｔ　３３６」（登録商標））１．０ｇ、及び２Ｍの炭酸ナトリウム水溶液２４ｍＬを加えた。この混合物を激しく攪拌し、加熱して２４時間還流した。粘稠な反応混合物をアセトン５００ｍＬに注ぎ、繊維状の黄色のポリマーを沈澱させた。このポリマーを濾過によって集め、アセトンで洗浄し、真空オーブンにおいて６０℃で一晩乾燥させた。得られたポリマーを高分子化合物３とよぶ。高分子化合物３は、下記繰り返し単位を有している。ｎは繰り返し単位の数を示している。高分子化合物３の標準ポリスチレンから求めた重量平均分子量は、６１０００であった（島津製ＧＰＣ、「Ｔｓｋｇｅｌ　ｓｕｐｅｒ　ＨＭ－Ｈ」１本＋「Ｔｓｋｇｅｌ　ｓｕｐｅｒ　Ｈ２０００」１本、移動相＝ＴＨＦ）。 Synthesis example 3
(Synthesis of polymer compound 3)
In toluene (80 mL) containing 6.40 g of 9,9-di-n-octylfluorene-2,7-di (ethylene boronate) and 4.00 g of 5,5′-dibromo-2,2′-bithiophene Under nitrogen, 0.18 g of tetrakis (triphenylphosphine) palladium, 1.0 g of methyltrioctylammonium chloride (manufactured by Aldrich, trade name “Aliquat 336” (registered trademark)), and 24 mL of 2M aqueous sodium carbonate solution were added. It was. The mixture was stirred vigorously and heated to reflux for 24 hours. The viscous reaction mixture was poured into 500 mL of acetone to precipitate a fibrous yellow polymer. The polymer was collected by filtration, washed with acetone and dried in a vacuum oven at 60 ° C. overnight. The resulting polymer is referred to as polymer compound 3. The high molecular compound 3 has the following repeating unit. n indicates the number of repeating units. The weight average molecular weight obtained from the standard polystyrene of the polymer compound 3 was 61000 (GPC manufactured by Shimadzu, one “Tskel super HM-H” + one “Tskel super H2000”, mobile phase = THF).
Figure JPOXMLDOC01-appb-C000004
 　　　　　高分子化合物３
Figure JPOXMLDOC01-appb-C000004
 Polymer compound 3
　実施例１
（有機薄膜トランジスタの製造）
　本発明の有機薄膜トランジスタの実施例を、図１から図７を用いて説明する。 Example 1
(Manufacture of organic thin-film transistors)
Examples of the organic thin film transistor of the present invention will be described with reference to FIGS.
　本実施例では、基板（ガラス）１、該基板１上にゲート電極（Ｍｏ）２、該ゲート電極２上にゲート絶縁膜（有機絶縁膜）３、該ゲート絶縁膜３上に第１導電層４及び第２導電層５からなるソース電極７と、第１導電層４及び第２導電層５からなるドレイン電極７とを形成し、該ソース電極７と該ドレイン電極７との間に有機半導体層８を形成して有機薄膜トランジスタを製造した。 In this embodiment, a substrate (glass) 1, a gate electrode (Mo) 2 on the substrate 1, a gate insulating film (organic insulating film) 3 on the gate electrode 2, and a first conductive layer on the gate insulating film 3 4 and the second conductive layer 5 and the drain electrode 7 formed of the first conductive layer 4 and the second conductive layer 5 are formed, and an organic semiconductor is formed between the source electrode 7 and the drain electrode 7. Layer 8 was formed to produce an organic thin film transistor.
　製造した有機薄膜トランジスタについては、真空プローバー内でトランジスタ特性を測定し特性を比較して本発明の効果を確認した。この時の真空プローバーの圧力は、約５×１０－３Ｐａとした。 About the manufactured organic thin-film transistor, the transistor characteristic was measured in the vacuum prober, the characteristic was compared, and the effect of this invention was confirmed. The pressure of the vacuum prober at this time was about 5 × 10 −3 Pa.
　次に、本発明の素子作製プロセスについて説明する。
　最初に、洗浄済の基板１上にスパッタリング法でＭｏ（モリブデン）層を形成し、フォトリソグラフィにより、ゲート電極２を形成した。フォトリソグラフィにおいて、フォトレジストは、東京応化工業社製「ＴＦＲ－Ｈ　ＰＬ」を、現像液は、ナガセケムテックス社製「ＮＰＤ－１８」を、レジスト剥離液は、東京応化工業社製「１０６」を、Ｍｏエッチング液は、関東化学社製の「Ｓ－８０５２０」を使用した。フォトリソグラフィは、以下の工程により行った。Ｍｏ層上にフォトレジスト「ＴＦＲ－Ｈ　ＰＬ」の膜を形成し、フォトマスクを介して３６５ｎｍ　ＵＶ光を照射した。次いで、現像液「ＮＰＤ－１８」を用いてフォトレジストの現像を行った。次いで、現像したフォトレジストをマスクとして、Ｍｏ層のＭｏが露出している部分を、Ｍｏエッチング液「Ｓ－８０５２０」を用いて除去し、レジスト剥離液「１０６」を用いて残りのフォトレジストを剥離して、ゲート電極２のパターニングを行った。 Next, the element manufacturing process of the present invention will be described.
First, a Mo (molybdenum) layer was formed on the cleaned substrate 1 by sputtering, and the gate electrode 2 was formed by photolithography. In photolithography, the photoresist is “TFR-H PL” manufactured by Tokyo Ohka Kogyo Co., Ltd., the developer is “NPD-18” manufactured by Nagase ChemteX, and the resist stripper is “106” manufactured by Tokyo Ohka Kogyo Co., Ltd. As the Mo etching solution, “S-80520” manufactured by Kanto Chemical Co., Inc. was used. Photolithography was performed by the following steps. A film of photoresist “TFR-H PL” was formed on the Mo layer and irradiated with 365 nm UV light through a photomask. Next, the photoresist was developed using a developer “NPD-18”. Next, using the developed photoresist as a mask, the Mo exposed portion of the Mo layer is removed using Mo etching solution “S-80520”, and the remaining photoresist is removed using resist stripping solution “106”. After peeling, the gate electrode 2 was patterned.
　次に、ゲート電極２を形成した基板をウエット洗浄し、その後、ＵＶオゾン洗浄機にて３００秒基板を洗浄し、その後、高分子化合物１、高分子化合物２及び２－ヘプタノンを含む溶液をゲート電極２上にスピンコート法により塗布して有機層を形成した。この有機層は熱架橋性であるため、直ぐに、焼成処理を行い、ゲート絶縁層３を得た。この時の焼成処理は、最終焼成処理として２２０℃で２５分焼成した。ゲート絶縁層３の層厚は、約４７０ｎｍであった。 Next, the substrate on which the gate electrode 2 is formed is wet-cleaned, and then the substrate is cleaned for 300 seconds with a UV ozone cleaner, and then a solution containing the polymer compound 1, polymer compound 2 and 2-heptanone is gated. An organic layer was formed on the electrode 2 by spin coating. Since this organic layer is thermally crosslinkable, it was immediately fired to obtain the gate insulating layer 3. The baking treatment at this time was carried out at 220 ° C. for 25 minutes as the final baking treatment. The layer thickness of the gate insulating layer 3 was about 470 nm.
　次に、該ゲート絶縁層３上に、５価の酸化タングステン（Ｗ２Ｏ５）のゾルゲル液をスピンコート法により塗布した。塗布後、５分程度大気中で乾燥させた後、１５０℃で３０分の焼成処理を行い図２に示す第１導電層４を得た。第１導電層４の層厚を求めるため、予め同条件で塗布して形成した層の層厚は３０ｎｍであった。 Next, a sol-gel solution of pentavalent tungsten oxide (W 2 O 5 ) was applied onto the gate insulating layer 3 by a spin coating method. After coating, the film was dried in the air for about 5 minutes, and then baked at 150 ° C. for 30 minutes to obtain the first conductive layer 4 shown in FIG. In order to determine the layer thickness of the first conductive layer 4, the layer thickness of the layer formed by applying in advance under the same conditions was 30 nm.
　第１導電層４の形成に使用したＷ２Ｏ５のゾルゲル液は、タングステンアルコキサイドとしてタングステン（Ｖ）エトキサイド（tungsten(V)ethoxide）を使用し、安定化剤としてβ－ジケトン化合物であるアセチルアセトンを使用した。今回作製した基板のゾル－ゲル溶液の溶媒は、２，３，４，５，６－ペンタフルオロトルエンを使用した。 The sol-gel solution of W 2 O 5 used for forming the first conductive layer 4 uses tungsten (V) ethoxide as tungsten alkoxide and is a β-diketone compound as a stabilizer. Acetylacetone was used. 2,3,4,5,6-pentafluorotoluene was used as the solvent for the sol-gel solution of the substrate produced this time.
　次に、スパッタリング法により第１導電層４上に銅（Ｃｕ）を１００ｎｍの層厚で形成し、図３に示す第２導電層５を得た。この後、該第２導電層５をフォトリソグラフィ法により図４の形態を経て、図５に示す第２導電層５の形状へ加工した。フォトリソグラフィにおいて、フォトレジストは、東京応化工業社製「ＴＦＲ－Ｈ　ＰＬ」を、現像液は、ナガセケムテックス社製「ＮＰＤ－１８」を、レジスト剥離液は、東京応化工業社製「１０６」を、Ｃｕエッチング液は、関東化学社製の混酸「Ｃｕ－０３」を使用した。フォトリソグラフィは、以下の工程により行った。Ｃｕ層上にフォトレジスト「ＴＦＲ－Ｈ　ＰＬ」の膜を形成し、フォトマスクを介して３６５ｎｍ　ＵＶ光を照射した。次いで、現像液「ＮＰＤ－１８」を用いてフォトレジストの現像を行った。次いで、現像したフォトレジストをマスクとして、第２導電層５のＣｕが露出している部分を、Ｃｕエッチング液「Ｃｕ－０３」を用いて除去し、レジスト剥離液「１０６」を用いて残りのフォトレジストを剥離して、第２導電層５のパターニングを行った。 Next, copper (Cu) was formed with a layer thickness of 100 nm on the first conductive layer 4 by a sputtering method to obtain a second conductive layer 5 shown in FIG. Thereafter, the second conductive layer 5 was processed by the photolithography method into the shape of the second conductive layer 5 shown in FIG. In photolithography, the photoresist is “TFR-H PL” manufactured by Tokyo Ohka Kogyo Co., Ltd., the developer is “NPD-18” manufactured by Nagase ChemteX, and the resist stripper is “106” manufactured by Tokyo Ohka Kogyo Co., Ltd. As a Cu etching solution, a mixed acid “Cu-03” manufactured by Kanto Chemical Co., Inc. was used. Photolithography was performed by the following steps. A film of photoresist “TFR-H PL” was formed on the Cu layer, and irradiated with 365 nm UV light through a photomask. Next, the photoresist was developed using a developer “NPD-18”. Next, using the developed photoresist as a mask, the portion of the second conductive layer 5 where Cu is exposed is removed using a Cu etching solution “Cu-03”, and the remaining portion is removed using a resist stripping solution “106”. The photoresist was peeled off and the second conductive layer 5 was patterned.
　次いで、パターニングされた第２導電層５をマスクとして、水酸化テトラメチルアンモニウム水溶液（ＴＭＡＨ水溶液：濃度２．３８％）で、第１導電層４の第２導電層５に覆われていない部分（露出している部分）をエッチングし、図６に示す素子構造を得た。この時のエッチング時間は、９０秒とした。最後に、ゲート絶縁膜３と第１電極層４、第２電極層５の密着性を向上させると共に、プロセス中に付着した水分を除去するため、最終焼成を窒素雰囲気で酸素濃度０．１ｐｐｍ未満、水分濃度１．０ｐｐｍ未満のグローブボックス中で２００℃１０分実施した。 Next, using the patterned second conductive layer 5 as a mask, a portion of the first conductive layer 4 not covered with the second conductive layer 5 with a tetramethylammonium hydroxide aqueous solution (TMAH aqueous solution: concentration 2.38%) ( The exposed portion was etched to obtain an element structure shown in FIG. The etching time at this time was 90 seconds. Finally, in order to improve the adhesion between the gate insulating film 3 and the first electrode layer 4 and the second electrode layer 5 and to remove water adhering during the process, the final baking is performed in a nitrogen atmosphere with an oxygen concentration of less than 0.1 ppm. This was carried out at 200 ° C. for 10 minutes in a glove box having a moisture concentration of less than 1.0 ppm.
　該第１導電層４を設ける事により、該第２導電層５を作製する際のプロセスダメージから該ゲート絶縁層３表面を保護する事ができる。また、該第１導電層４を設ける事により、ゲート絶縁層３と第２導電層５の密着性が向上する。第１導電層は第２導電層５のゲート絶縁層３への拡散に対する保護層としても機能する。 By providing the first conductive layer 4, the surface of the gate insulating layer 3 can be protected from process damage when the second conductive layer 5 is produced. Further, by providing the first conductive layer 4, adhesion between the gate insulating layer 3 and the second conductive layer 5 is improved. The first conductive layer also functions as a protective layer against diffusion of the second conductive layer 5 into the gate insulating layer 3.
　次に、有機半導体層８として、キシレン溶液に０．５ｗｔ％の濃度で高分子化合物３を溶かし、窒素雰囲気下のグローブボックス内でスピンコート法により基板上へ塗布し、塗布後直ぐに２００℃１０分の焼成処理を実施した。この時の有機半導体層の層厚は約１６ｎｍであった。この様にして、図７に示す構造を有する有機薄膜トランジスタを得た。また、この時はソース電極、及び、ドレイン電極への表面処理は行わなかった。 Next, as the organic semiconductor layer 8, the polymer compound 3 is dissolved in a xylene solution at a concentration of 0.5 wt%, and is applied onto the substrate by a spin coating method in a glove box under a nitrogen atmosphere. The calcination process for 1 minute was implemented. At this time, the thickness of the organic semiconductor layer was about 16 nm. In this way, an organic thin film transistor having the structure shown in FIG. 7 was obtained. At this time, the surface treatment to the source electrode and the drain electrode was not performed.
　この後、真空プローバーでトランジスタ特性として、２０～－４０Ｖの伝達（Ｖｇ－Ｉｄ）特性と０～－４０Ｖの出力（Ｖｄ－Ｉｄ）特性を測定した。この時の真空プローバーの真空度は、約５×１０－３Ｐａであった。トランジスタ特性を表２に示す。 Thereafter, a transistor characteristic of 20 to -40V (Vg-Id) and an output of 0 to -40V (Vd-Id) were measured with a vacuum prober. The vacuum degree of the vacuum prober at this time was about 5 × 10 −3 Pa. Table 2 shows the transistor characteristics.
　ゲート絶縁層のゲート絶縁層表面ラフネスＲａは走査型プローブ顕微鏡（エスアイアイ（ＳＩＩ）・ナノテクノロジー社製、商品名「ＳＰＩ３８００Ｎ」）を用いて測定した。
ゲート絶縁層表面接触角は自動接触角測定装置（英弘精機社製、商品名「OCA20」）を用いて測定した。移動度μ、最大電流Ｉｏｎ、スレッショルド電圧Ｖｔｈ、ヒステリシス、Ｓｗｉｎｇ　Ｆａｃｔｏｒ（サブスレッショルドスイング）、Ｏｎ／Ｏｆｆ比は、伝達（Ｖｇ－Ｉｄ）特性から求めた。また、伝達（Ｖｇ－Ｉｄ）特性のドレイン電流Ｉｄが立ち上がる弱反転領域形成開始電圧をドレイン電流立ち上り電圧Ｖｏｎと定義し、スレッショルド電圧Ｖｔｈとは別に表２に示す。 The gate insulating layer surface roughness Ra of the gate insulating layer was measured using a scanning probe microscope (product name “SPI3800N”, manufactured by SII (Nanotechnology)).
The surface contact angle of the gate insulating layer was measured using an automatic contact angle measuring device (trade name “OCA20”, manufactured by Eihiro Seiki Co., Ltd.). Mobility μ, maximum current Ion, threshold voltage Vth, hysteresis, Swing Factor (subthreshold swing), and On / Off ratio were determined from the transmission (Vg−Id) characteristics. Further, the weak inversion region formation start voltage at which the drain current Id having the transmission (Vg−Id) characteristic rises is defined as the drain current rise voltage Von, and is shown in Table 2 separately from the threshold voltage Vth.
　比較例１
　比較例として、基板（ガラス）１、該基板１上にゲート電極（Ｍｏ）２、該ゲート電極２上にゲート絶縁層（有機絶縁層）３、該ゲート絶縁層３上に本発明の第２導電層５と同材料の単一金属１層による単層のソース電極、及び、ドレイン電極を形成し、該ソース電極と該ドレイン電極との間に有機半導体層を形成して、有機薄膜トランジスタを製造した。 Comparative Example 1
As a comparative example, a substrate (glass) 1, a gate electrode (Mo) 2 on the substrate 1, a gate insulating layer (organic insulating layer) 3 on the gate electrode 2, and a second of the present invention on the gate insulating layer 3 An organic thin film transistor is manufactured by forming a single-layer source electrode and drain electrode of a single metal single layer of the same material as the conductive layer 5, and forming an organic semiconductor layer between the source electrode and the drain electrode. did.
　即ち、第１導電層４を形成せず、ゲート絶縁層３上に第２導電層５をスパッタリング法で成膜し、フォトリソグラフィによりパターニングしてソース電極及びドレイン電極を形成した以外は、実施例１と同様に有機薄膜トランジスタを製造し、トランジスタ特性を測定した。得られたトランジスタ特性を表２に示す。 That is, the first conductive layer 4 was not formed, but the second conductive layer 5 was formed on the gate insulating layer 3 by a sputtering method and patterned by photolithography to form a source electrode and a drain electrode. The organic thin-film transistor was manufactured similarly to 1, and the transistor characteristic was measured. Table 2 shows the obtained transistor characteristics.
　参考例１
　実施例１と同様の方法で、基板１上にゲート電極２を形成し、該ゲート電極上にゲート絶縁層３を形成した。該ゲート絶縁層のゲート絶縁層表面ラフネスＲａ及びゲート絶縁層表面接触角を測定した。結果を表２のプロセス未通過ゲート絶縁層の欄に示す。 Reference example 1
In the same manner as in Example 1, the gate electrode 2 was formed on the substrate 1, and the gate insulating layer 3 was formed on the gate electrode. The gate insulating layer surface roughness Ra and the gate insulating layer surface contact angle of the gate insulating layer were measured. The results are shown in the column of unprocessed gate insulating layer in Table 2.
［表２］
Figure JPOXMLDOC01-appb-I000005
[Table 2]
Figure JPOXMLDOC01-appb-I000005
　比較例１の有機薄膜トランジスタに対し、実施例１の有機薄膜トランジスタは、全てのトランジスタ特性が改善していることがわかる。また、ゲート絶縁層３の表面ラフネスと表面接触角については、実施例１の有機薄膜トランジスタは、スパッタリング法によりＣｕ層を形成する際のゲート絶縁層へのプロセスダメージが大幅に緩和されており、参考例１のプロセス未通過のゲート絶縁層と同等の値を示している。比較例１の有機薄膜トランジスタは、有機絶縁層上に、直接高出力のスパッタ法でＣｕ層を形成したため、ゲート絶縁層への物理的ダメージによる影響がゲート絶縁層３の表面ラフネスと表面接触角に顕著に表れている。 It can be seen that all the transistor characteristics of the organic thin film transistor of Example 1 are improved compared to the organic thin film transistor of Comparative Example 1. Further, regarding the surface roughness and the surface contact angle of the gate insulating layer 3, the organic thin film transistor of Example 1 has greatly reduced process damage to the gate insulating layer when the Cu layer is formed by the sputtering method. The value is equivalent to that of the gate insulating layer not passing through the process in Example 1. In the organic thin film transistor of Comparative Example 1, since the Cu layer was directly formed on the organic insulating layer by a high-power sputtering method, the physical damage to the gate insulating layer was affected by the surface roughness and the surface contact angle of the gate insulating layer 3. It appears remarkably.
　比較例１の有機薄膜トランジスタと比較して、実施例１の有機薄膜トランジスタは、ドレイン電流立ち上がり電圧Ｖｏｎが０［Ｖ］に近く、ヒステリシスが殆ど無く、最大電流Ｉｏｎは約２桁改善した。 Compared with the organic thin film transistor of Comparative Example 1, the organic thin film transistor of Example 1 had a drain current rising voltage Von close to 0 [V], almost no hysteresis, and the maximum current Ion improved by about two orders of magnitude.
　以上、本発明の方法により、特性が高い有機薄膜トランジスタを得られた。また、本発明の有機薄膜トランジスタは、図１及び図８に示す保護層１０を最後に形成するのがより好ましい。更に、第１導電層（Ｗ２Ｏ５層）４の部分に電荷注入性がより良好な材料を用いる事により、電荷注入層としての機能を備える事がより好ましい。本発明の有機薄膜トランジスタは、アクティブマトリックス表示装置、回路に用いることができる。 As mentioned above, the organic thin-film transistor with a high characteristic was obtained by the method of this invention. In the organic thin film transistor of the present invention, the protective layer 10 shown in FIGS. 1 and 8 is more preferably formed last. Furthermore, it is more preferable that the first conductive layer (W 2 O 5 layer) 4 has a function as a charge injection layer by using a material having a better charge injection property. The organic thin film transistor of the present invention can be used for active matrix display devices and circuits.
　また、本発明が実施例により限定されるものではないことは言うまでもない。 Needless to say, the present invention is not limited to the examples.
　１…基板、
　２…ゲート電極、
　３…ゲート絶縁層、
　４…第１導電層、
　５…第２導電層、
　６…第３導電層、
　７…ソース・ドレイン電極、
　８…有機半導体層、
　９…マスク、
　１０…保護層。 1 ... substrate,
2 ... Gate electrode,
3 ... gate insulating layer,
4 ... 1st conductive layer,
5 ... 2nd conductive layer,
6 ... 3rd conductive layer,
7 ... source / drain electrodes,
8 ... Organic semiconductor layer,
9 ... Mask,
10: Protective layer.

Claims (7)

  1. 　ボトムゲート・ボトムコンタクト構造の有機薄膜トランジスタを製造する方法であって、
    　ゲート電極、及び該ゲート電極を被覆し、有機絶縁材料を含むゲート絶縁層を形成する工程；
    　該ゲート絶縁層上に塗布法、無電解めっき法又は原子層堆積法からなる群から選択される一つの方法を用いて導電性材料からなる第１導電層を成膜する工程；
    　該第１導電層上に更に導電性材料からなる導電層を成膜後、該導電層を所定の形状にパターニングすることにより第２導電層を形成する工程；
    　該第２導電層で被覆されていない第１導電層の部分を除去して、第１導電層及び第２導電層からなるソース電極及びドレイン電極を形成する工程；
    　ソース電極、ドレイン電極、及び該ソース電極と該ドレイン電極に挟まれた領域のゲート絶縁層が被覆されるように、有機半導体層を形成する工程；
    を有する方法。     A method of manufacturing an organic thin film transistor having a bottom gate / bottom contact structure,
    Forming a gate electrode and a gate insulating layer covering the gate electrode and including an organic insulating material;
    Forming a first conductive layer made of a conductive material on the gate insulating layer using one method selected from the group consisting of a coating method, an electroless plating method or an atomic layer deposition method;
    Forming a second conductive layer by further forming a conductive layer made of a conductive material on the first conductive layer and then patterning the conductive layer into a predetermined shape;
    Removing a portion of the first conductive layer not covered with the second conductive layer to form a source electrode and a drain electrode composed of the first conductive layer and the second conductive layer;
    Forming an organic semiconductor layer so as to cover the source electrode, the drain electrode, and the gate insulating layer in a region sandwiched between the source electrode and the drain electrode;
    Having a method.
  2. 　前記第１導電層を成膜する工程は、酸化銀、酸化銅、酸化亜鉛、銀塩、銀及び銅からなる群から選ばれる少なくとも１種の材料を含む導電性材料の前駆体及び／又は前記導電性材料のナノ粒子を溶解もしくは分散させたインクを前記ゲート絶縁層上に塗布法で成膜し焼成することにより、前記導電性材料からなる導電層を得る工程である請求項１に記載の方法。 The step of forming the first conductive layer includes a precursor of a conductive material containing at least one material selected from the group consisting of silver oxide, copper oxide, zinc oxide, silver salt, silver and copper and / or 2. The step of obtaining a conductive layer made of the conductive material by forming an ink in which nanoparticles of the conductive material are dissolved or dispersed on the gate insulating layer by a coating method and baking the ink. Method.
  3. 　前記第１導電層を成膜する工程は、タングステンアルコキサイドから作られたゾルゲル液を塗布法で該ゲート絶縁層上に成膜し、ゲル化したタングステンアルコキサイドを焼成処理して酸化タングステンからなる導電層を得る工程である請求項１に記載の方法。 In the step of forming the first conductive layer, a sol-gel solution made from tungsten alkoxide is formed on the gate insulating layer by a coating method, and the gelled tungsten alkoxide is baked to form tungsten oxide. The method according to claim 1, which is a step of obtaining a conductive layer comprising:
  4. 　前記タングステンアルコキサイドのゾルゲル液の溶媒は、プロピレングリコールモノメチルエーテルアセテート（PGMEA）もしくは、２，３，４，５，６－ペンタフルオロトルエンである請求項３に記載の方法。 The method according to claim 3, wherein a solvent of the tungsten alkoxide sol-gel solution is propylene glycol monomethyl ether acetate (PGMEA) or 2,3,4,5,6-pentafluorotoluene.
  5. 　前記第１導電層の除去は、前記第２導電層をマスクとして用いて湿式エッチング法により行い、そのときに用いられるエッチング液はアルカリ溶液であり、第１導電層と第２導電層のエッチング選択比が１０：１以上である請求項１～４のいずれか一項に記載の方法。 The removal of the first conductive layer is performed by a wet etching method using the second conductive layer as a mask, and the etching solution used at that time is an alkaline solution, and the etching selection of the first conductive layer and the second conductive layer is selected. The method according to any one of claims 1 to 4, wherein the ratio is 10: 1 or more.
  6. 　前記ボトムゲート・ボトムコンタクト構造の有機薄膜トランジスタのソース電極及びドレイン電極は第３導電層を備えており、
    　前記第３導電層の形成は、パターンニングされた第２導電層と、第１導電層の露出している部分の上に導電性材料の層を成膜した後、該導電性材料の層を第２導電層が完全に被覆されるようにパターニングすることにより行われる請求項１～５のいずれか一項に記載の方法。     The source electrode and the drain electrode of the organic thin film transistor having the bottom gate / bottom contact structure include a third conductive layer,
    The third conductive layer is formed by forming a conductive material layer on the exposed second conductive layer and the exposed portion of the first conductive layer, and then forming the conductive material layer. The method according to any one of claims 1 to 5, wherein the method is performed by patterning so that the second conductive layer is completely covered.
  7. 　請求項１～６のいずれか一項に記載の方法により製造されるボトムゲート・ボトムコンタクト構造の有機薄膜トランジスタ。 An organic thin film transistor having a bottom gate / bottom contact structure manufactured by the method according to any one of claims 1 to 6.
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