WO2012053133A1 - Chopper amplifier, active filter, and reference frequency generating circuit - Google Patents

Chopper amplifier, active filter, and reference frequency generating circuit Download PDF

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Publication number
WO2012053133A1
WO2012053133A1 PCT/JP2011/003475 JP2011003475W WO2012053133A1 WO 2012053133 A1 WO2012053133 A1 WO 2012053133A1 JP 2011003475 W JP2011003475 W JP 2011003475W WO 2012053133 A1 WO2012053133 A1 WO 2012053133A1
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voltage
signal
node
oscillation
signal level
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PCT/JP2011/003475
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French (fr)
Japanese (ja)
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徳永　祐介
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パナソニック株式会社
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/38—DC amplifiers with modulator at input and demodulator at output; Modulators or demodulators specially adapted for use in such amplifiers
    • H03F3/387—DC amplifiers with modulator at input and demodulator at output; Modulators or demodulators specially adapted for use in such amplifiers with semiconductor devices only
    • H03F3/393—DC amplifiers with modulator at input and demodulator at output; Modulators or demodulators specially adapted for use in such amplifiers with semiconductor devices only with field-effect devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H03F3/45183—Long tailed pairs
    • H03F3/45192—Folded cascode stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/02—Multiple-port networks
    • H03H11/04—Frequency selective two-port networks
    • H03H11/12—Frequency selective two-port networks using amplifiers with feedback
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45424—Indexing scheme relating to differential amplifiers the CMCL comprising a comparator circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45614—Indexing scheme relating to differential amplifiers the IC comprising two cross coupled switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45616—Indexing scheme relating to differential amplifiers the IC comprising more than one switch, which are not cross coupled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45724—Indexing scheme relating to differential amplifiers the LC comprising two cross coupled switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45726—Indexing scheme relating to differential amplifiers the LC comprising more than one switch, which are not cross coupled

Definitions

  • the present invention relates to a differential amplifier that generates an output voltage corresponding to a difference between two input voltages, and more particularly to an amplifier to which a chopper technique is applied.
  • a differential amplifier that generates an output voltage corresponding to a difference between two input voltages.
  • Such differential amplifiers are used in various technical fields.
  • an active filter including a differential amplifier is used to perform feedback control so that the amplitudes of two oscillation signals generated by the oscillation circuit are constant.
  • Patent Document 1 describes that flicker noise of the differential amplifier can be reduced by incorporating a chopper mechanism in the differential amplifier provided in the active filter.
  • the settling time of the output voltage of the differential amplifier becomes longer than the chopper period, so that the settling error of the output voltage of the differential amplifier becomes an offset voltage. May be included in the output voltage.
  • the offset voltage fluctuates due to temperature changes and power supply voltage fluctuations. As a result, the output voltage of the differential amplifier fluctuates.
  • Patent Documents 2 and 3 describe techniques for reducing such an offset voltage. More specifically, in Patent Document 2, a half circuit of a differential amplifier is provided as a correction replica circuit, and the back gate voltage of a pair of MOS transistors constituting a load current mirror of the differential amplifier is calculated using the correction replica circuit. It is described that the offset voltage is removed from the output voltage of the differential amplifier by correcting. Patent Document 3 discloses a chopper mechanism by reducing the impedance of a path switching node by inserting a cascode transistor between an output node (a node for outputting an output voltage) of a differential amplifier and a chopper mechanism. The response speed of the differential amplifier is increased, and as a result, the offset voltage of the differential amplifier (that is, the settling error of the output voltage) is reduced.
  • an object of the present invention is to provide a chopper amplifier capable of reducing the offset voltage and suppressing the increase in noise of the output voltage without being influenced by the response speed of the chopper mechanism.
  • the chopper amplifier is a chopper amplifier that generates an output voltage corresponding to a difference between the first and second input voltages while alternately switching the first and second operation modes, In the first operation mode, the first input voltage is supplied to the first input node and the second input voltage is supplied to the second input node. In the second operation mode, the first input voltage is supplied to the first input node.
  • An input switching unit for supplying the first input voltage to the second input node and supplying the second input voltage to the first input node; and a first between the first intermediate node and the reference node.
  • the connection switching unit connected to the second intermediate node supplies the first intermediate voltage generated at the first intermediate node to the third intermediate node and the second intermediate node. Is supplied to an output node for outputting the output voltage.
  • the first intermediate voltage is supplied to the output node and the second intermediate voltage is output.
  • An output switching unit that supplies a voltage to the third intermediate node; and a voltage control unit that controls the control voltage so that a voltage applied to the third intermediate node approaches a voltage applied to the output node; Is provided.
  • the fluctuation range of the output voltage can be reduced by controlling the control voltage so that the voltage applied to the third intermediate node approaches the voltage applied to the output node. Accordingly, the settling error of the output voltage that occurs when the settling time of the output voltage is shorter than the chopper cycle (the switching cycle of the first and second operation modes) can be reduced. Therefore, the offset voltage included in the output voltage can be reduced without being influenced by the response speed of the chopper mechanism. Thereby, it is possible to suppress the output voltage from fluctuating due to a temperature change or a power supply voltage fluctuation.
  • the voltage control unit is generated in the voltage control unit by controlling the control voltage corresponding to the power source of the main differential amplification unit (differential amplification unit constituted by the voltage-current conversion unit and the first and second transconductance elements). Since the generated noise can be reduced by the power supply voltage fluctuation rejection ratio (PSRR) of the main differential amplifier, an increase in output voltage noise can be suppressed.
  • PSRR power supply voltage fluctuation rejection ratio
  • the figure which shows the structural example of a chopper amplifier The figure for demonstrating the chopper operation
  • FIG. 1 shows a configuration example of the chopper amplifier 1.
  • the chopper amplifier 1 generates an output voltage Vout corresponding to the difference between the input voltages Vin1 and Vin2 while alternately switching the first and second operation modes.
  • the chopper amplifier 1 includes an input switching unit 101, a voltage / current conversion unit 102, a load transistor 1031 (mutual conductance element), a load transistor 1032 (mutual conductance element), a connection switching unit 104, an output switching unit 105, And a voltage control unit 106.
  • the input switching unit 101 supplies the input voltage Vin1 to the input node Nin1 and supplies the input voltage Vin2 to the input node Nin2.
  • the input switching unit 101 supplies the input voltage Vin1 to the input node Nin2 and supplies the input voltage Vin2 to the input node Nin1.
  • the input switching unit 101 may include switches SW1 to SW4.
  • the switch SW1 is connected between the voltage node NN1 to which the input voltage Vin1 is applied and the input node Nin1.
  • Switch SW2 is connected between voltage node NN1 and input node Nin2.
  • the switch SW3 is connected between the voltage node NN2 to which the input voltage Vin2 is applied and the input node Nin1.
  • Switch SW4 is connected between voltage node NN2 and input node Nin2.
  • the switches SW1 and SW4 are turned on / off in response to the control clock CKc.
  • the switches SW2 and SW3 are turned on / off in response to a control clock CKd (for example, an inverted clock of the control clock CKc).
  • CKd for example, an inverted clock of the control clock CKc.
  • the voltage-current converter 102 has a first current path between the intermediate node N1 and the ground node (a reference node to which the ground voltage GND is applied) and a second current path between the intermediate node N2 and the ground node.
  • a current corresponding to a voltage (either one of the input voltages Vin1 and Vin2) applied to the input node Nin1 is generated in the first current path, and a voltage applied to the input node Nin2 (input voltage Vin1, Vin1) is generated.
  • a current corresponding to the other one of Vin2 is generated in the second current path.
  • the voltage-current converter 102 may include a current source CS, input transistors Tin1, Tin2, and current mirrors CM1, CM2.
  • Current source CS is connected between a power supply node (a reference node to which power supply voltage VDD is applied) and intermediate node N102.
  • the input transistor Tin1 is provided in a current path between the intermediate node N102 and the input end of the current mirror CM1, and generates an input current corresponding to the voltage applied to the input node Nin1.
  • the current mirror CM1 generates a current corresponding to the input current generated by the input transistor Tin1 in the first current path (current path between the intermediate node N1 and the ground node).
  • the input transistor Tin2 is provided in a current path between the intermediate node N102 and the input end of the current mirror CM2, and generates an input current corresponding to the voltage applied to the input node Nin2.
  • the current mirror CM2 generates a current corresponding to the input current generated by the input transistor Tin2 in the second current path (current path between the intermediate node N2 and the ground node).
  • the load transistor 1031 is provided in a third current path between the control node Ncnt (a node to which the control voltage Vcnt is applied) and the intermediate node N1, and supplies a current corresponding to the common voltage Vnc generated at the common node Nc. 3 current paths.
  • the load transistor 1032 is provided in the fourth current path between the control node Ncnt and the intermediate node N2, and generates a current corresponding to the common voltage Vnc generated at the common node Nc in the fourth current path.
  • the load transistors 1031 and 1032 are pMOS transistors.
  • connection switching unit 104 connects the common node Nc to the intermediate node N1 in the first operation mode. Further, the connection switching unit 104 connects the common node Nc to the intermediate node N2 in the second operation mode.
  • the connection switching unit 104 may include switches SW5 and SW6.
  • the switch SW5 is connected between the common node Nc and the intermediate node N1, and switches on / off in response to the control clock CKc.
  • the switch SW6 is connected between the common node Nc and the intermediate node N2, and switches on / off in response to the control clock CKd.
  • the switch SW5 changes from the off state to the on state and the switch SW6 changes from the on state to the off state.
  • the load transistor 1031 enters a diode connection state. That is, the load transistors 1031 and 1032 constitute a load current mirror having the intermediate nodes N1 and N2 as input terminals and output terminals, respectively.
  • the switch SW5 changes from the on state to the off state and the switch SW6 changes from the off state to the on state.
  • the load transistor 1032 is in a diode connection state.
  • the load transistors 1031 and 1032 form a load current mirror having the intermediate nodes N1 and N2 as output terminals and input terminals, respectively. In this way, the input end and the output end of the current mirror constituted by the load transistors 1031 and 1032 are periodically switched.
  • the output switching unit 105 supplies the intermediate voltage V1 generated at the intermediate node N1 to the intermediate node N105 and outputs the intermediate voltage V2 generated at the intermediate node N2 to the output node Nout (output voltage Vout). To the node).
  • the output switching unit 105 supplies the intermediate voltage V1 to the output node Nout and supplies the intermediate voltage V2 to the intermediate node N105.
  • the output switching unit 105 may include switches SW7 to SW10.
  • the switch SW7 is connected between the intermediate node N1 and the output node Nout.
  • Switch SW8 is connected between intermediate node N1 and intermediate node N105.
  • the switch SW9 is connected between the intermediate node N2 and the output node Nout.
  • Switch SW10 is connected between intermediate node N2 and intermediate node N105.
  • the switches SW7 and SW10 are turned on / off in response to a control clock CKd (for example, an inverted clock of the control clock CKc).
  • the switches SW8 and SW9 are turned on / off in response to the control clock CKc.
  • the voltage control unit 106 controls the voltage applied to the intermediate node N105 (any one of the intermediate voltages V1 and V2) to approach the voltage applied to the output node Nout (the other one of the intermediate voltages V1 and V2).
  • the control voltage Vcnt applied to the node Ncnt is controlled.
  • the voltage control unit 106 may include a differential amplifier AMP, a control transistor TC, a capacitor CC, and a resistor RR.
  • the differential amplifier AMP generates an output voltage corresponding to the difference (difference between the intermediate voltages V1 and V2) between the voltage applied to the intermediate node N105 and the voltage applied to the output node Nout.
  • Control transistor TC is provided in a current path between a power supply node (a node to which power supply voltage VDD is applied) and control node Ncnt.
  • the capacitor CC smoothes the output voltage of the differential amplifier AMP.
  • Resistor RR limits the amplification gain of the main differential amplifier so that the amplification gain of the main differential amplifier configured by voltage-current converter 102 and load transistors 1031 and 1032 does not exceed a predetermined upper limit value.
  • the voltage control unit 106 may not include the capacitor CC and the resistor RR.
  • the input switching unit 101 transfers the input voltages Vin1 and Vin2 to the input node.
  • the connection switching unit 104 disconnects the common node Nc from the intermediate node N2 and connects the common node Nc to the intermediate node N1.
  • the load transistors 1031 and 1032 form a load current mirror having the intermediate nodes N1 and N2 as input terminals and output terminals, respectively.
  • the voltage value of the intermediate voltage V1 gradually increases from the convergence value (voltage value Vrd) of the output voltage Vout toward the convergence value (voltage value Vdio) of the common voltage Vnc, and the voltage value of the intermediate voltage V2 is The value gradually decreases from the value Vdio toward the voltage value Vrd. Further, the output switching unit 105 disconnects the output node Nout from the intermediate node N1 and connects the output node Nout to the intermediate node N2. As a result, the output node Nout is charged / discharged by the intermediate voltage V2.
  • the input switching unit 101 causes the input voltages Vin1 and Vin2 to be input.
  • the connection switching unit 104 disconnects the common node Nc from the intermediate node N1 and connects the common node Nc to the intermediate node N2.
  • the load transistors 1031 and 1032 constitute a load current mirror having the intermediate nodes N1 and N2 as output terminals and input terminals, respectively.
  • the voltage value of the intermediate voltage V2 gradually increases from the convergence value (voltage value Vrd) of the output voltage Vout toward the convergence value (voltage value Vdio) of the common voltage Vnc, and the voltage value of the intermediate voltage V1 is The value gradually decreases from the value Vdio toward the voltage value Vrd. Further, the output switching unit 105 disconnects the output node Nout from the intermediate node N2 and connects the output node Nout to the intermediate node N1. As a result, the output node Nout is charged / discharged by the intermediate voltage V1.
  • flicker noise in a portion of the chopper amplifier 1 excluding the input switching unit 101 is an integral multiple of the chopper frequency (frequency of the control clocks CKc and CKb). It can be distributed in the vicinity of harmonics having a frequency.
  • the voltage values of the intermediate voltages V1 and V2 are the convergence value of the common voltage Vnc (voltage value Vdio) and the convergence value of the output voltage Vout (voltage value Vrd). Fluctuate in a complementary manner.
  • the settling time Ts of the output voltage Vout becomes longer than the chopper period (for example, the period from time t1 to t2), the voltage value of the output voltage Vout cannot reach the convergence value (voltage value Vrd) during the chopper period. (The chopper amplifier 1 is not balanced). Therefore, a settling error occurs in the output voltage Vout, and the settling error is included in the output voltage Vout as an offset voltage.
  • the settling error (offset voltage) of the output voltage Vout that occurs when the settling time Ts of the output voltage Vout is shorter than the chopper period increases as the fluctuation range (Vdio ⁇ Vrd) of the output voltage Vout increases.
  • the convergence value (voltage value Vdio) of the common voltage Vnc varies according to the voltage value of the control voltage Vcnt.
  • the convergence value (voltage value Vrd) of the output voltage Vout varies according to the voltage difference between the input voltages Vin1 and Vin2 and the load connected to the output node Nout.
  • control of the control voltage Vcnt in the chopper amplifier 1 will be described with reference to FIG.
  • the mutual conductance values of the load transistors 1031 and 1032 are assumed to be equal to each other.
  • the voltage control unit 106 decreases the voltage value of the control voltage Vcnt according to the difference (V1 ⁇ V2) between the intermediate voltages V1 and V2 during the period from time t1 to time t2, and from time t2 to time t3. In the period, the voltage value of the control voltage Vcnt is decreased according to the difference (V2 ⁇ V1) between the intermediate voltages V1 and V2.
  • the convergence value of the common voltage Vnc decreases from the voltage value Vdio1 to the voltage value Vdio2, and the convergence value of the common voltage Vnc approaches the convergence value of the output voltage Vout.
  • the fluctuation range of the output voltage Vout decreases from the fluctuation range (Vdio1-Vrd) to the fluctuation range (Vdio2-Vrd).
  • the fluctuation range of the output voltage Vout can be reduced by bringing the convergence value of the common voltage Vnc closer to the convergence value of the output voltage Vout. Therefore, the settling error of the output voltage Vout that occurs when the settling time Ts of the output voltage Vout becomes longer than the chopper period can be reduced. Therefore, the offset voltage included in the output voltage Vout can be reduced without being influenced by the response speed of the chopper mechanism. Thereby, as shown in FIG. 4, it is possible to suppress the output voltage Vout from fluctuating due to a temperature change or a power supply voltage fluctuation.
  • FIG. 4 it is possible to suppress the output voltage Vout from fluctuating due to a temperature change or a power supply voltage fluctuation.
  • the dotted line corresponds to the temperature characteristics when the control voltage Vcnt is not controlled (when the control voltage Vcnt is a constant voltage), and the solid line indicates the case where the control voltage Vcnt is controlled by the voltage control unit 106. Corresponds to temperature characteristics.
  • the control voltage corresponding to the power source of the main differential amplifier (the differential amplifier configured by the voltage / current converter 102 and the load transistors 1031 and 1032)
  • noise generated in the voltage controller 106 is reduced. Since it can be reduced by the power supply voltage fluctuation rejection ratio (PSRR) of the main differential amplifier, an increase in noise of the output voltage Vout can be suppressed.
  • PSRR power supply voltage fluctuation rejection ratio
  • the chopper amplifier 1 may be switched from the first operation mode to the second operation mode through the transient mode, and from the second operation mode to the first operation mode through the transient mode.
  • the input switching unit 101 does not supply the input voltages Vin1 and Vin2 to any of the input nodes Nin1 and Nin2, and the connection switching unit 104 connects the common node Nc to any of the intermediate nodes N1 and N2.
  • the output switching unit 105 does not supply the intermediate voltages V1 and V2 to either the intermediate node N105 or the output node Nout.
  • the control clocks CKc and CKd may be non-overlapping clocks whose effective output periods (here, high-level output periods) do not overlap each other.
  • FIG. 5 shows a configuration example of an active filter including the chopper amplifier 1 shown in FIG.
  • the active filter 2 includes a resistor R1 and a capacitor C1 in addition to the chopper amplifier 1.
  • One end of the resistor R1 is connected to the input node N21, and the other end of the resistor R1 is connected to the intermediate node N20.
  • Signal voltages VS21 and VS22 are applied to input nodes N21 and N22, respectively.
  • One end of the capacitor C1 is connected to the intermediate node N20, and the other end of the capacitor C1 is connected to the output node Nout of the chopper amplifier 1.
  • the chopper amplifier 1 receives the intermediate voltage Vn generated at the intermediate node N20 as one of the input voltages Vin1 and Vin2, and receives the signal voltage VS22 applied to the input node N22 as the other of the input voltages Vin1 and Vin2.
  • the function of extracting the intermediate voltage Vn proportional to the amplitude of the signal voltage VS21 (signal extraction function) and the function of outputting the output voltage Vout corresponding to the difference between the intermediate voltage and the signal voltage VS22 (difference) An active filter having an output function can be realized.
  • FIG. 6 shows a first modification of the active filter.
  • the active filter 2a includes a capacitor C2 in addition to the configuration of the active filter 2 shown in FIG.
  • One end of the capacitor C2 is connected to the output node Nout of the chopper amplifier 1, and the other end of the capacitor C2 is connected to a ground node (a reference node to which the ground voltage GND is applied).
  • the other end of the capacitor C1 is connected not to the output node Nout of the chopper amplifier 1 but to the ground node.
  • Other configurations are the same as those in FIG. Even in such a configuration, an active filter having a signal extraction function and a differential output function can be realized.
  • FIG. 7 shows a second modification of the active filter.
  • the active filter 2b includes a resistor R2 in addition to the configuration of the active filter 2 shown in FIG.
  • One end of the resistor R2 is connected to the input node N23, and the other end of the resistor R2 is connected to the intermediate node N20.
  • a signal voltage VS23 is applied to the input node N23.
  • FIG. 8 shows a third modification of the active filter.
  • the active filter 2c includes a resistor R2 in addition to the configuration of the active filter 2a shown in FIG.
  • One end of the resistor R2 is connected to the input node N23, and the other end of the resistor R2 is connected to the intermediate node N20.
  • a signal voltage VS23 is applied to the input node N23. Even in such a configuration, an active filter having a signal extraction function and a differential output function can be realized.
  • FIG. 9 shows a configuration example of a reference frequency generation circuit including the active filter 2 shown in FIG.
  • the reference frequency generation circuit 100 generates reference clocks CKa and CKb, and includes an oscillation circuit 11, an oscillation control circuit 12, a reference voltage generation circuit 13, and a reference control circuit 14.
  • Each of the reference clocks CKa and CKb has a frequency corresponding to the time constant of the oscillation circuit 11, and the respective signal levels fluctuate complementarily.
  • the oscillation circuit 11 increases or decreases the signal levels of the oscillation signals OSCa and OSCb in a complementary manner in response to the transition of the signal levels of the reference clocks CKa and CKb.
  • the oscillation circuit 11 includes capacitors Ca and Cb for generating oscillation signals OSCa and OSCb, constant current sources CS111a and CS111b for supplying constant current, and a switch SW1a for switching the connection state of the capacitors Ca and Cb. , SW2a, SW1b, SW2b (connection switching unit).
  • the oscillation control circuit 12 When the oscillation control circuit 12 detects that the signal level of the oscillation signal OSCa (or the signal level of the oscillation signal OSCb) is higher than the comparison voltage VR, the oscillation control circuit 12 transitions the signal levels of the reference clocks CKa and CKb.
  • the oscillation control circuit 12 includes a comparator CMPa that compares the comparison voltage VR and the signal level of the oscillation signal OSCa, a comparator CMPb that compares the comparison voltage VR and the signal level of the oscillation signal OSCb, and comparators CMPa and CMPb.
  • RS latch circuit 112 which receives output signals OUTa and OUTb and outputs reference clocks CKa and CKb.
  • the reference voltage generation circuit 13 generates a constant voltage having a predetermined voltage difference as the reference voltage Vref with respect to the ground voltage GND.
  • the reference voltage generation circuit 13 includes a band gap reference circuit (BGR) 113 and a constant voltage circuit (pMOS transistor T113, resistors R112, R113, differential amplifier circuit A113).
  • the reference control circuit 14 determines the difference between the signal level of the intermediate signal proportional to the amplitude of each of the oscillation signals OSCa and OSCb (here, the cumulative average voltage of each time constant waveform of the oscillation signals OSCa and OSCb) and the reference voltage Vref.
  • the comparison voltage VR is increased or decreased so as to decrease.
  • the reference control circuit 14 includes switches 114 a and 114 b (switch circuit) and the active filter 2.
  • the switch 114a When the signal level of the reference clock CKb is high, the switch 114a is turned on to pass the oscillation signal OSCa. On the other hand, since the signal level of the reference clock CKa is low, the switch 114b is turned off and cuts off the oscillation signal OSCb. On the other hand, when the signal level of the reference clock CKb is low, the switch 114a is turned off to cut off the oscillation signal OSCa. On the other hand, since the signal level of the reference clock CKa is high, the switch 114a is turned on to pass the oscillation signal OSCb.
  • the respective time constant waveform components of the reference clocks CKa and CKb (the time constant of the oscillation circuit 11). (The waveform component that increases in step) is supplied to the active filter 2.
  • the active filter 2 has a function (signal extraction function) for extracting an intermediate signal proportional to the amplitude of the oscillation signal from the oscillation signals OSCa and OSCb that have passed through the switches 114a and 114b, and the signal level of the intermediate signal and the reference voltage Vref.
  • the active filter 2 receives the oscillation signal Sx (one of the oscillation signals OSCa and OSCb) that has passed through the switches 114a and 114b as the signal voltage VS21 and the reference voltage Vref as the signal voltage VS22.
  • the output voltage Vout is supplied as the comparison voltage VR.
  • the frequency fluctuations of the reference clocks CKa and CKb due to the fluctuation of the delay time can be suppressed.
  • the frequency of the reference clocks CKa and CKb can be increased while suppressing an increase in power consumption (particularly, power consumption of the comparators CMPa and CMPb).
  • a noise component lower than the loop band of the feedback control is attenuated, low frequency noise in the reference frequency generation circuit (for example, low frequency noise of the comparison voltage VR, output noise of the comparators CMPa and CMPb, etc.) ) Can be reduced.
  • the resonance characteristic (Q value) of the reference frequency generating circuit 100 can be improved, and the frequency variation of the reference clocks CKa and CKb can be reduced.
  • the reference voltage generation circuit 13 since the reference voltage generation circuit 13 generates the reference voltage Vref with reference to the ground voltage GND, the reference voltage Vref does not change even if the power supply voltage VDD changes. Therefore, unnecessary fluctuations in the comparison voltage VR are suppressed, and as a result, frequency fluctuations in the reference clocks CKa and CKb caused by fluctuations in the power supply voltage VDD can be suppressed.
  • the chopper operation of the chopper amplifier 1 included in the active filter 2 can disperse flicker noise superimposed on the comparison voltage VR (output voltage Vout) in the vicinity of harmonics having a frequency that is an integral multiple of the chopper frequency. Since the flicker noise dispersed in the harmonics can be attenuated by the active filter 2, the resonance characteristic (Q value) of the reference frequency generation circuit can be further improved.
  • the control voltage in the chopper amplifier 1 it is possible to suppress the occurrence of a settling error in the comparison voltage VR (output voltage Vout). Therefore, as shown in FIG. 10, the reference clock CKa due to a temperature change or a power supply voltage change. , CKb frequency fluctuation can be suppressed.
  • the dotted line corresponds to the temperature characteristic when the control voltage Vcnt is not controlled (when the control voltage Vcnt is a constant voltage), and the solid line corresponds to the temperature characteristic when the control voltage Vcnt is controlled.
  • the chopper amplifier 1 included in the active filter 2 may receive the reference clocks CKa and CKb divided by a frequency dividing circuit (not shown) as control clocks CKc and CKd.
  • the load capacity for example, the signal path of the signal path
  • the chopper amplifier 1 can be improved as compared with the case where the reference clocks CKa and CKb are directly supplied to the chopper amplifier 1 as control clocks CKc and CKd without using a frequency divider.
  • the charge / discharge time of (parasitic capacitance) can be increased. Thereby, since the driving capability of the chopper amplifier 1 can be lowered, the power consumption of the chopper amplifier 1 can be reduced.
  • the chopper amplifier 1 may receive the reference clocks CKa and CKb as they are as the control clocks CKc and CKd without going through the frequency dividing circuit, or the internal signals of the reference frequency generation circuit 100 (for example, the oscillation signals OSCa and OSCb). May be received as control clocks CKc and CKd.
  • reference control circuit 14 may include an active filter 2a shown in FIG. 6 instead of the active filter 2 shown in FIG. 6
  • FIG. 11 shows a first modification of the reference frequency generation circuit.
  • the reference frequency generation circuit 200 includes an oscillation circuit 21, an oscillation control circuit 12, a reference voltage generation circuit 23, and a reference control circuit 24.
  • the oscillation circuit 21 includes resistors R211a and R211b instead of the constant current sources CS111a and CS111b shown in FIG.
  • resistors R211a and R211b instead of the constant current sources CS111a and CS111b shown in FIG.
  • 1 / f noise noise component inversely proportional to the frequency generated in the constant current source
  • the frequency stability of the reference clocks CKa and CKb can be improved compared to the generation circuit 100.
  • the resistors R211a and R211b have less aging degradation than the constant current sources CS111a and CS111b, the reference clocks CKa and CKb can be accurately generated over a long period of time.
  • the reference voltage generation circuit 23 includes resistors R212 and R213. Resistors R212 and R213 generate reference voltage Vref by dividing resistance between power supply voltage VDD and ground voltage GND.
  • the reference control circuit 24 includes resistors 211a and 211b instead of the switches 114a and 114b shown in FIG.
  • One end of each of the resistors 211a and 211b is connected to the active filter 2, and an oscillation signal OSCa is supplied to the other end of the resistor 211a, and an oscillation signal OSCb is supplied to the other end of the resistor 211b.
  • the active filter 2 receives the oscillation signal Sx (a signal generated by resistance-dividing the oscillation signals OSCa and OSCb by the resistors 211a and 211b) as the signal voltage VS21 and the reference voltage Vref as the signal voltage VS22.
  • the output voltage Vout of the active filter 2 is supplied as the comparison voltage VR.
  • the reference control circuit 24 may include an active filter 2a shown in FIG. 6 instead of the active filter 2 shown in FIG.
  • the reference frequency generation circuit 200 may include the reference control circuit 14 shown in FIG. 9 instead of the reference control circuit 24 shown in FIG. 11, or the active filter 2b shown in FIGS. , 2c may be provided as a reference control circuit.
  • the active filters 2b and 2c receive the oscillation signals OSCa and OSCb as the signal voltages VS21 and VS23, respectively, receive the reference voltage Vref as the signal voltage VS22, and supply the output voltage Vout of the active filters 2b and 2c as the comparison voltage VR. May be.
  • the reference frequency generation circuit 200 may include the reference voltage generation circuit 13 shown in FIG. 9 instead of the reference voltage generation circuit 23 shown in FIG.
  • FIG. 12 shows a second modification of the reference frequency generation circuit.
  • the reference frequency generation circuit 300 includes an oscillation circuit 31, an oscillation control circuit 32, a reference voltage generation circuit 13, and a reference control circuit (active filter 2).
  • the reference clock CK has a frequency corresponding to the time constant of the oscillation circuit 31.
  • the oscillation circuit 31 increases or decreases the signal level of the oscillation signal OSCa in response to the transition of the signal level of the reference clock CK.
  • the oscillation circuit 31 includes a capacitor Ca, a constant current source CS111a, and switches SW1a and SW2a.
  • the oscillation control circuit 32 detects that the signal level of the oscillation signal OSCa is higher than the comparison voltage VR, the oscillation control circuit 32 changes the reference clock CK from the low level to the high level, and sets the reference clock CK to the high level after a predetermined time has elapsed. Transition from low to low.
  • the oscillation control circuit 32 includes a comparator CMPa and a delay circuit 311.
  • the reference control circuit compares the reference voltage Vref so that the difference between the signal level of the intermediate signal proportional to the amplitude of the oscillation signal OSCa (here, the cumulative average voltage of the oscillation signal OSCa) and the reference voltage Vref is small. Increase or decrease VR.
  • the reference control unit is composed of an active filter 2, and the active filter 2 receives the oscillation signal OSCa as the signal voltage VS21 and the reference voltage Vref as the signal voltage VS22.
  • the output voltage Vout of the active filter 2 is , And supplied as a comparison voltage VR.
  • the reference frequency generation circuit 300 may include the active filter 2a illustrated in FIG. 6 instead of the active filter 2 illustrated in FIG.
  • the polarities of the chopper amplifier 1, the active filters 2, 2a, 2b, and 2c, and the reference frequency generation circuits 100, 200, and 300 may be reversed.
  • the load transistors 1031, 1032, the input transistors Tin1, Tin2, and the control transistor TC are configured by nMOS transistors
  • the current mirrors CM1, CM2 are configured by pMOS transistors
  • the power supply node The reference node to which the power supply voltage VDD is applied and the ground node (node to which the ground voltage GND is applied) may be interchanged.
  • the above-described chopper amplifier can reduce the offset voltage included in the output voltage without being affected by the response speed of the chopper mechanism and can suppress an increase in noise in the output voltage. Useful as.

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Abstract

In first operation mode, an input switching unit (101) supplies input voltages (Vin1, Vin2) to input nodes (Nin1, Nin2), respectively, a connection switching unit (104) connects a common node (Nc) to an intermediate node (N1), and an output switching unit (105) supplies intermediate voltages (V1, V2) to an intermediate node (N105) and an output node (Nout), respectively. In second operation mode, the input switching unit (101) supplies the input voltages (Vin1, Vin2) to the input nodes (Nin2, Nin1), respectively, and the connection switching unit (104) connects the common node (Nc) to the intermediate node (N1), and the output switching unit (105) supplies the intermediate voltages (V1, V2) to the output node (Nout) and the intermediate node (N105), respectively. A voltage control unit (106) controls a control voltage (Vcnt) such that the voltage applied to the intermediate node (N105) is close to the voltage applied to the output node (Nout).

Description

チョッパ増幅器、アクティブフィルタ、基準周波数生成回路Chopper amplifier, active filter, reference frequency generation circuit
　この発明は、２つの入力電圧の差分に応じた出力電圧を生成する差動増幅器に関し、さらに詳しくは、チョッパ技術を適用した増幅器に関する。 The present invention relates to a differential amplifier that generates an output voltage corresponding to a difference between two input voltages, and more particularly to an amplifier to which a chopper technique is applied.
　従来より、２つの入力電圧の差分に応じた出力電圧を生成する差動増幅器が知られている。このような差動増幅器は、様々な技術分野で利用されている。例えば、特許文献１に記載された基準周波数生成回路では、発振回路によって生成された２つの発振信号の振幅が一定になるようにフィードバック制御を施すために、差動増幅器を備えたアクティブフィルタが利用されている。また、特許文献１には、アクティブフィルタに備えられた差動増幅器にチョッパ機構を組み込むことにより、差動増幅器のフリッカノイズを低減できることが記載されている。 Conventionally, a differential amplifier that generates an output voltage corresponding to a difference between two input voltages is known. Such differential amplifiers are used in various technical fields. For example, in the reference frequency generation circuit described in Patent Document 1, an active filter including a differential amplifier is used to perform feedback control so that the amplitudes of two oscillation signals generated by the oscillation circuit are constant. Has been. Patent Document 1 describes that flicker noise of the differential amplifier can be reduced by incorporating a chopper mechanism in the differential amplifier provided in the active filter.
　このように、差動増幅器にチョッパ機構を組み込んだ場合、差動増幅器の出力電圧のセトリング時間がチョッパ周期よりも長くなることによって、差動増幅器の出力電圧のセトリング誤差がオフセット電圧として差動増幅器の出力電圧に含まれる場合がある。この場合、温度変化や電源電圧の変動によってこのオフセット電圧が変動し、その結果、差動増幅器の出力電圧が変動してしまうことになる。 Thus, when the chopper mechanism is incorporated in the differential amplifier, the settling time of the output voltage of the differential amplifier becomes longer than the chopper period, so that the settling error of the output voltage of the differential amplifier becomes an offset voltage. May be included in the output voltage. In this case, the offset voltage fluctuates due to temperature changes and power supply voltage fluctuations. As a result, the output voltage of the differential amplifier fluctuates.
　そこで、特許文献２，３には、このようなオフセット電圧を低減する技術が記載されている。詳しく説明すると、特許文献２には、差動増幅器の半回路を補正用レプリカ回路として設け、補正用レプリカ回路を用いて差動増幅器の負荷カレントミラーを構成する一対のＭＯＳトランジスタのバックゲート電圧を補正することによって、差動増幅器の出力電圧からオフセット電圧を除去することが記載されている。また、特許文献３には、差動増幅器の出力ノード（出力電圧を出力するためのノード）とチョッパ機構との間にカスコードトランジスタを挿入することで経路切替ノードを低インピーダンス化することによってチョッパ機構の応答速度を高速化し、結果的に差動増幅器のオフセット電圧（すなわち、出力電圧のセトリング誤差）を低減することが記載されている。 Therefore, Patent Documents 2 and 3 describe techniques for reducing such an offset voltage. More specifically, in Patent Document 2, a half circuit of a differential amplifier is provided as a correction replica circuit, and the back gate voltage of a pair of MOS transistors constituting a load current mirror of the differential amplifier is calculated using the correction replica circuit. It is described that the offset voltage is removed from the output voltage of the differential amplifier by correcting. Patent Document 3 discloses a chopper mechanism by reducing the impedance of a path switching node by inserting a cascode transistor between an output node (a node for outputting an output voltage) of a differential amplifier and a chopper mechanism. The response speed of the differential amplifier is increased, and as a result, the offset voltage of the differential amplifier (that is, the settling error of the output voltage) is reduced.
国際公開第２０１０／０１６１６７号パンフレットInternational Publication No. 2010/016167 Pamphlet 米国特許第４，４２３，３８５号明細書U.S. Pat. No. 4,423,385 米国特許第７，３８５，４４３号明細書US Pat. No. 7,385,443
　しかしながら、特許文献２に記載された技術では、負荷カレントミラーを構成する一対のＭＯＳトランジスタのバックゲートにそれぞれ接続される一対の容量に対して補正用レプリカ回路のノイズが別々に蓄積されるので、これらのＭＯＳトランジスタの閾値電圧がそれぞれ独立して変動することになる。これらのＭＯＳトランジスタの閾値電圧のばらつきが差動増幅器の出力電圧にノイズとなって現れてしまう。 However, in the technique described in Patent Document 2, since the noise of the correction replica circuit is accumulated separately for the pair of capacitors connected to the back gates of the pair of MOS transistors constituting the load current mirror, The threshold voltages of these MOS transistors vary independently. Variations in the threshold voltages of these MOS transistors appear as noise in the output voltage of the differential amplifier.
　また、特許文献３に記載された技術では、チョッパ機構の応答速度によって出力電圧のセトリング速度が制限される。そのため、チョッパ周波数が高くなるほど（チョッパ周期が短くなるほど）、出力電圧のセトリング誤差が増大し、結果的に差動増幅器のオフセット電圧も増大することになる。 In the technique described in Patent Document 3, the settling speed of the output voltage is limited by the response speed of the chopper mechanism. Therefore, the higher the chopper frequency (the shorter the chopper period), the larger the settling error of the output voltage, resulting in an increase in the offset voltage of the differential amplifier.
　そこで、この発明は、チョッパ機構の応答速度に左右されずにオフセット電圧を低減できるとともに出力電圧のノイズ増加を抑制可能なチョッパ増幅器を提供することを目的とする。 Therefore, an object of the present invention is to provide a chopper amplifier capable of reducing the offset voltage and suppressing the increase in noise of the output voltage without being influenced by the response speed of the chopper mechanism.
　この発明の１つの局面に従うと、チョッパ増幅器は、第１および第２の動作モードを交互に切り替えながら第１および第２の入力電圧の差分に応じた出力電圧を生成するチョッパ増幅器であって、上記第１の動作モードでは、上記第１の入力電圧を第１の入力ノードに供給するとともに上記第２の入力電圧を第２の入力ノードに供給し、上記第２の動作モードでは、上記第１の入力電圧を上記第２の入力ノードに供給するとともに上記第２の入力電圧を上記第１の入力ノードに供給する入力切替部と、第１の中間ノードと基準ノードとの間の第１の電流経路および第２の中間ノードと上記基準ノードとの間の第２の電流経路に設けられ、上記第１の入力ノードに印加された電圧に応じた電流を上記第１の電流経路に発生させるとともに上記第２の入力ノードに印加された電圧に応じた電流を上記第２の電流経路に発生させる電圧電流変換部と、制御電圧が印加される制御ノードと上記第１の中間ノードとの間の第３の電流経路および上記制御ノードと上記第２の中間ノードとの間の第４の電流経路にそれぞれ設けられ、共通ノードに発生する共通電圧に応じた電流を上記第３および第４の電流経路にそれぞれ発生させる第１および第２の相互コンダクタンス素子と、上記第１の動作モードでは、上記共通ノードを上記第１の中間ノードに接続し、上記第２の動作モードでは、上記共通ノードを上記第２の中間ノードに接続する接続切替部と、上記第１の動作モードでは、上記第１の中間ノードに発生する第１の中間電圧を第３の中間ノードに供給するとともに上記第２の中間ノードに発生する第２の中間電圧を上記出力電圧を出力するための出力ノードに供給し、上記第２の動作モードでは、上記第１の中間電圧を上記出力ノードに供給するとともに上記第２の中間電圧を上記第３の中間ノードに供給する出力切替部と、上記第３の中間ノードに印加された電圧が上記出力ノードに印加された電圧に近づくように上記制御電圧を制御する電圧制御部とを備える。 According to one aspect of the present invention, the chopper amplifier is a chopper amplifier that generates an output voltage corresponding to a difference between the first and second input voltages while alternately switching the first and second operation modes, In the first operation mode, the first input voltage is supplied to the first input node and the second input voltage is supplied to the second input node. In the second operation mode, the first input voltage is supplied to the first input node. An input switching unit for supplying the first input voltage to the second input node and supplying the second input voltage to the first input node; and a first between the first intermediate node and the reference node. Current path and a second current path between the second intermediate node and the reference node, and a current corresponding to the voltage applied to the first input node is generated in the first current path. And let A voltage-current converter for generating a current corresponding to the voltage applied to the two input nodes in the second current path, and a third between the control node to which the control voltage is applied and the first intermediate node. Current path and a fourth current path between the control node and the second intermediate node, respectively, and current corresponding to a common voltage generated at the common node is supplied to the third and fourth current paths. In the first operation mode, the common node is connected to the first intermediate node, and in the second operation mode, the common node is connected to the first and second transconductance elements respectively generated. In the first operation mode, the connection switching unit connected to the second intermediate node supplies the first intermediate voltage generated at the first intermediate node to the third intermediate node and the second intermediate node. Is supplied to an output node for outputting the output voltage. In the second operation mode, the first intermediate voltage is supplied to the output node and the second intermediate voltage is output. An output switching unit that supplies a voltage to the third intermediate node; and a voltage control unit that controls the control voltage so that a voltage applied to the third intermediate node approaches a voltage applied to the output node; Is provided.
　上記チョッパ増幅器では、第３の中間ノードに印加された電圧が出力ノードに印加された電圧に近づくように制御電圧を制御することによって、出力電圧の変動幅を減少させることができる。したがって、出力電圧のセトリング時間がチョッパ周期（第１および第２の動作モードの切替周期）よりも短い場合に生じる出力電圧のセトリング誤差を小さくすることができる。そのため、チョッパ機構の応答速度に左右されずに出力電圧に含まれるオフセット電圧を低減できる。これにより、温度変化や電源電圧の変動によって出力電圧が変動することを抑制できる。 In the chopper amplifier, the fluctuation range of the output voltage can be reduced by controlling the control voltage so that the voltage applied to the third intermediate node approaches the voltage applied to the output node. Accordingly, the settling error of the output voltage that occurs when the settling time of the output voltage is shorter than the chopper cycle (the switching cycle of the first and second operation modes) can be reduced. Therefore, the offset voltage included in the output voltage can be reduced without being influenced by the response speed of the chopper mechanism. Thereby, it is possible to suppress the output voltage from fluctuating due to a temperature change or a power supply voltage fluctuation.
　さらに、主差動増幅部（電圧電流変換部と第１および第２の相互コンダクタンス素子とによって構成される差動増幅部）の電源に相当する制御電圧を制御することにより、電圧制御部において発生したノイズを主差動増幅部の電源電圧変動除去比（ＰＳＲＲ）によって低減できるので、出力電圧のノイズ増加を抑制できる。 Further, it is generated in the voltage control unit by controlling the control voltage corresponding to the power source of the main differential amplification unit (differential amplification unit constituted by the voltage-current conversion unit and the first and second transconductance elements). Since the generated noise can be reduced by the power supply voltage fluctuation rejection ratio (PSRR) of the main differential amplifier, an increase in output voltage noise can be suppressed.
チョッパ増幅器の構成例を示す図。The figure which shows the structural example of a chopper amplifier. チョッパ増幅器によるチョッパ動作について説明するための図。The figure for demonstrating the chopper operation | movement by a chopper amplifier. チョッパ増幅器における制御電圧の制御について説明するための図。The figure for demonstrating control of the control voltage in a chopper amplifier. 温度変化に伴うオフセット電圧の変動について説明するためのグラフ。The graph for demonstrating the fluctuation | variation of the offset voltage accompanying a temperature change. チョッパ増幅器を備えるアクティブフィルタの構成例を示す図。The figure which shows the structural example of an active filter provided with a chopper amplifier. アクティブフィルタの変形例１を示す図。The figure which shows the modification 1 of an active filter. アクティブフィルタの変形例２を示す図。The figure which shows the modification 2 of an active filter. アクティブフィルタの変形例３を示す図。The figure which shows the modification 3 of an active filter. アクティブフィルタを備える基準周波数生成回路の構成例を示す図。The figure which shows the structural example of a reference frequency generation circuit provided with an active filter. 温度変化に伴う周波数変動について説明するためのグラフ。The graph for demonstrating the frequency fluctuation accompanying a temperature change. 基準周波数生成回路の変形例１を示す図。The figure which shows the modification 1 of a reference frequency generation circuit. 基準周波数生成回路の変形例２を示す図。The figure which shows the modification 2 of a reference frequency generation circuit.
　以下、実施の形態を図面を参照して詳しく説明する。なお、図中同一または相当部分には同一の符号を付しその説明は繰り返さない。 Hereinafter, embodiments will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.
　（チョッパ増幅器）
　図１は、チョッパ増幅器１の構成例を示す。チョッパ増幅器１は、第１および第２の動作モードを交互に切り替えながら入力電圧Ｖｉｎ１，Ｖｉｎ２の差分に応じた出力電圧Ｖｏｕｔを生成する。チョッパ増幅器１は、入力切替部１０１と、電圧電流変換部１０２と、負荷トランジスタ１０３１（相互コンダクタンス素子）と、負荷トランジスタ１０３２（相互コンダクタンス素子）と、接続切替部１０４と、出力切替部１０５と、電圧制御部１０６とを備える。 (Chopper amplifier)
FIG. 1 shows a configuration example of the chopper amplifier 1. The chopper amplifier 1 generates an output voltage Vout corresponding to the difference between the input voltages Vin1 and Vin2 while alternately switching the first and second operation modes. The chopper amplifier 1 includes an input switching unit 101, a voltage / current conversion unit 102, a load transistor 1031 (mutual conductance element), a load transistor 1032 (mutual conductance element), a connection switching unit 104, an output switching unit 105, And a voltage control unit 106.
　　〔入力切替部〕
　入力切替部１０１は、第１の動作モードでは、入力電圧Ｖｉｎ１を入力ノードＮｉｎ１に供給するとともに入力電圧Ｖｉｎ２を入力ノードＮｉｎ２に供給する。また、入力切替部１０１は、第２の動作モードでは、入力電圧Ｖｉｎ１を入力ノードＮｉｎ２に供給するとともに入力電圧Ｖｉｎ２を入力ノードＮｉｎ１に供給する。例えば、入力切替部１０１は、スイッチＳＷ１～ＳＷ４を含んでいても良い。スイッチＳＷ１は、入力電圧Ｖｉｎ１が印加される電圧ノードＮＮ１と入力ノードＮｉｎ１との間に接続される。スイッチＳＷ２は、電圧ノードＮＮ１と入力ノードＮｉｎ２との間に接続される。スイッチＳＷ３は、入力電圧Ｖｉｎ２が印加される電圧ノードＮＮ２と入力ノードＮｉｎ１との間に接続される。スイッチＳＷ４は、電圧ノードＮＮ２と入力ノードＮｉｎ２との間に接続される。スイッチＳＷ１，ＳＷ４は、制御クロックＣＫｃに応答してオン／オフを切り替える。スイッチＳＷ２，ＳＷ３は、制御クロックＣＫｄ（例えば、制御クロックＣＫｃの反転クロック）に応答してオン／オフを切り替える。制御クロックＣＫｃの論理レベルがローレベルからハイレベルへ遷移すると、スイッチＳＷ１，ＳＷ４がオフ状態からオン状態になるとともにスイッチＳＷ２，ＳＷ３がオン状態からオフ状態になる。一方、制御クロックＣＫｃの論理レベルがハイレベルからローレベルになると、スイッチＳＷ１，ＳＷ４がオン状態からオフ状態になるとともにスイッチＳＷ２，ＳＷ３がオフ状態からオン状態になる。このようにして、入力電圧Ｖｉｎ１，Ｖｉｎ２と入力ノードＮｉｎ１，Ｎｉｎ２の対応関係が周期的に切り替えられる。 [Input switching section]
In the first operation mode, the input switching unit 101 supplies the input voltage Vin1 to the input node Nin1 and supplies the input voltage Vin2 to the input node Nin2. In the second operation mode, the input switching unit 101 supplies the input voltage Vin1 to the input node Nin2 and supplies the input voltage Vin2 to the input node Nin1. For example, the input switching unit 101 may include switches SW1 to SW4. The switch SW1 is connected between the voltage node NN1 to which the input voltage Vin1 is applied and the input node Nin1. Switch SW2 is connected between voltage node NN1 and input node Nin2. The switch SW3 is connected between the voltage node NN2 to which the input voltage Vin2 is applied and the input node Nin1. Switch SW4 is connected between voltage node NN2 and input node Nin2. The switches SW1 and SW4 are turned on / off in response to the control clock CKc. The switches SW2 and SW3 are turned on / off in response to a control clock CKd (for example, an inverted clock of the control clock CKc). When the logic level of the control clock CKc transitions from the low level to the high level, the switches SW1 and SW4 change from the off state to the on state, and the switches SW2 and SW3 change from the on state to the off state. On the other hand, when the logic level of the control clock CKc changes from the high level to the low level, the switches SW1 and SW4 change from the on state to the off state and the switches SW2 and SW3 change from the off state to the on state. In this manner, the correspondence relationship between the input voltages Vin1 and Vin2 and the input nodes Nin1 and Nin2 is periodically switched.
　　〔電圧電流変換部〕
　電圧電流変換部１０２は、中間ノードＮ１と接地ノード（接地電圧ＧＮＤが印加される基準ノード）との間の第１の電流経路および中間ノードＮ２と接地ノードとの間の第２の電流経路に設けられ、入力ノードＮｉｎ１に印加された電圧（入力電圧Ｖｉｎ１，Ｖｉｎ２のいずれか一方）に応じた電流を第１の電流経路に発生させるとともに、入力ノードＮｉｎ２に印加された電圧（入力電圧Ｖｉｎ１，Ｖｉｎ２のいずれか他方）に応じた電流を第２の電流経路に発生させる。例えば、電圧電流変換部１０２は、電流源ＣＳと、入力トランジスタＴｉｎ１，Ｔｉｎ２と、カレントミラーＣＭ１，ＣＭ２とを含んでいても良い。電流源ＣＳは、電源ノード（電源電圧ＶＤＤが印加される基準ノード）と中間ノードＮ１０２との間に接続される。入力トランジスタＴｉｎ１は、中間ノードＮ１０２とカレントミラーＣＭ１の入力端との間の電流経路に設けられ、入力ノードＮｉｎ１に印加された電圧に応じた入力電流を生成する。カレントミラーＣＭ１は、入力トランジスタＴｉｎ１によって生成された入力電流に対応する電流を第１の電流経路（中間ノードＮ１と接地ノードとの間の電流経路）に発生させる。入力トランジスタＴｉｎ２は、中間ノードＮ１０２とカレントミラーＣＭ２の入力端との間の電流経路に設けられ、入力ノードＮｉｎ２に印加された電圧に応じた入力電流を生成する。カレントミラーＣＭ２は、入力トランジスタＴｉｎ２によって生成された入力電流に対応する電流を第２の電流経路（中間ノードＮ２と接地ノードとの間の電流経路）に発生させる。 [Voltage-current converter]
The voltage-current converter 102 has a first current path between the intermediate node N1 and the ground node (a reference node to which the ground voltage GND is applied) and a second current path between the intermediate node N2 and the ground node. A current corresponding to a voltage (either one of the input voltages Vin1 and Vin2) applied to the input node Nin1 is generated in the first current path, and a voltage applied to the input node Nin2 (input voltage Vin1, Vin1) is generated. A current corresponding to the other one of Vin2 is generated in the second current path. For example, the voltage-current converter 102 may include a current source CS, input transistors Tin1, Tin2, and current mirrors CM1, CM2. Current source CS is connected between a power supply node (a reference node to which power supply voltage VDD is applied) and intermediate node N102. The input transistor Tin1 is provided in a current path between the intermediate node N102 and the input end of the current mirror CM1, and generates an input current corresponding to the voltage applied to the input node Nin1. The current mirror CM1 generates a current corresponding to the input current generated by the input transistor Tin1 in the first current path (current path between the intermediate node N1 and the ground node). The input transistor Tin2 is provided in a current path between the intermediate node N102 and the input end of the current mirror CM2, and generates an input current corresponding to the voltage applied to the input node Nin2. The current mirror CM2 generates a current corresponding to the input current generated by the input transistor Tin2 in the second current path (current path between the intermediate node N2 and the ground node).
　　〔負荷トランジスタ（相互コンダクタンス素子）〕
　負荷トランジスタ１０３１は、制御ノードＮｃｎｔ（制御電圧Ｖｃｎｔが印加されるノード）と中間ノードＮ１との間の第３の電流経路に設けられ、共通ノードＮｃに発生した共通電圧Ｖｎｃに応じた電流を第３の電流経路に発生させる。負荷トランジスタ１０３２は、制御ノードＮｃｎｔと中間ノードＮ２との間の第４の電流経路に設けられ、共通ノードＮｃに発生した共通電圧Ｖｎｃに応じた電流を第４の電流経路に発生させる。なお、ここでは、負荷トランジスタ１０３１，１０３２は、ｐＭＯＳトランジスタによって構成されている。 [Load transistor (mutual conductance element)]
The load transistor 1031 is provided in a third current path between the control node Ncnt (a node to which the control voltage Vcnt is applied) and the intermediate node N1, and supplies a current corresponding to the common voltage Vnc generated at the common node Nc. 3 current paths. The load transistor 1032 is provided in the fourth current path between the control node Ncnt and the intermediate node N2, and generates a current corresponding to the common voltage Vnc generated at the common node Nc in the fourth current path. Here, the load transistors 1031 and 1032 are pMOS transistors.
　　〔接続切替部〕
　接続切替部１０４は、第１の動作モードでは、共通ノードＮｃを中間ノードＮ１に接続する。また、接続切替部１０４は、第２の動作モードでは、共通ノードＮｃを中間ノードＮ２に接続する。例えば、接続切替部１０４は、スイッチＳＷ５，ＳＷ６を含んでいても良い。スイッチＳＷ５は、共通ノードＮｃと中間ノードＮ１との間に接続され、制御クロックＣＫｃに応答してオン／オフを切り替える。スイッチＳＷ６は、共通ノードＮｃと中間ノードＮ２との間に接続され、制御クロックＣＫｄに応答してオン／オフを切り替える。制御クロックＣＫｃの論理レベルがローレベルからハイレベルへ遷移すると、スイッチＳＷ５がオフ状態からオン状態になるとともにスイッチＳＷ６がオン状態からオフ状態になる。これにより、負荷トランジスタ１０３１は、ダイオード接続状態となる。すなわち、負荷トランジスタ１０３１，１０３２は、中間ノードＮ１，Ｎ２をそれぞれ入力端および出力端とする負荷カレントミラーを構成することになる。一方、制御クロックＣＫｃの論理レベルがハイレベルからローレベルへ遷移すると、スイッチＳＷ５がオン状態からオフ状態になるとともにスイッチＳＷ６がオフ状態からオン状態になる。これにより、負荷トランジスタ１０３２は、ダイオード接続状態となる。すなわち、負荷トランジスタ１０３１，１０３２は、中間ノードＮ１，Ｎ２をそれぞれ出力端および入力端とする負荷カレントミラーを構成することになる。このように、負荷トランジスタ１０３１，１０３２によって構成されるカレントミラーの入力端および出力端が周期的に切り替えられる。 (Connection switching part)
The connection switching unit 104 connects the common node Nc to the intermediate node N1 in the first operation mode. Further, the connection switching unit 104 connects the common node Nc to the intermediate node N2 in the second operation mode. For example, the connection switching unit 104 may include switches SW5 and SW6. The switch SW5 is connected between the common node Nc and the intermediate node N1, and switches on / off in response to the control clock CKc. The switch SW6 is connected between the common node Nc and the intermediate node N2, and switches on / off in response to the control clock CKd. When the logic level of the control clock CKc transitions from the low level to the high level, the switch SW5 changes from the off state to the on state and the switch SW6 changes from the on state to the off state. As a result, the load transistor 1031 enters a diode connection state. That is, the load transistors 1031 and 1032 constitute a load current mirror having the intermediate nodes N1 and N2 as input terminals and output terminals, respectively. On the other hand, when the logic level of the control clock CKc transitions from the high level to the low level, the switch SW5 changes from the on state to the off state and the switch SW6 changes from the off state to the on state. As a result, the load transistor 1032 is in a diode connection state. That is, the load transistors 1031 and 1032 form a load current mirror having the intermediate nodes N1 and N2 as output terminals and input terminals, respectively. In this way, the input end and the output end of the current mirror constituted by the load transistors 1031 and 1032 are periodically switched.
　　〔出力切替部〕
　出力切替部１０５は、第１の動作モードでは、中間ノードＮ１に発生する中間電圧Ｖ１を中間ノードＮ１０５に供給するとともに中間ノードＮ２に発生する中間電圧Ｖ２を出力ノードＮｏｕｔ（出力電圧Ｖｏｕｔを出力するためのノード）に供給する。また、出力切替部１０５は、第２の動作モードでは、中間電圧Ｖ１を出力ノードＮｏｕｔに供給するとともに中間電圧Ｖ２を中間ノードＮ１０５に供給する。例えば、出力切替部１０５は、スイッチＳＷ７～ＳＷ１０を含んでいても良い。スイッチＳＷ７は、中間ノードＮ１と出力ノードＮｏｕｔとの間に接続される。スイッチＳＷ８は、中間ノードＮ１と中間ノードＮ１０５との間に接続される。スイッチＳＷ９は、中間ノードＮ２と出力ノードＮｏｕｔとの間に接続される。スイッチＳＷ１０は、中間ノードＮ２と中間ノードＮ１０５との間に接続される。スイッチＳＷ７，ＳＷ１０は、制御クロックＣＫｄ（例えば、制御クロックＣＫｃの反転クロック）に応答してオン／オフを切り替える。スイッチＳＷ８，ＳＷ９は、制御クロックＣＫｃに応答してオン／オフを切り替える。制御クロックＣＫｃの論理レベルがローレベルからハイレベルへ遷移すると、スイッチＳＷ７，ＳＷ１０がオン状態からオフ状態になるとともにスイッチＳＷ８，ＳＷ９がオフ状態からオン状態になる。一方、制御クロックＣＫｃの論理レベルがハイレベルからローレベルへ遷移すると、スイッチＳＷ７，ＳＷ１０がオフ状態からオン状態になるとともにスイッチＳＷ８，ＳＷ９がオン状態からオフ状態になる。このようにして、中間ノードＮ１，Ｎ２と出力ノードＮｏｕｔおよび中間ノードＮ１０５との対応関係が周期的に切り替えられることにより、中間電圧Ｖ１，Ｖ２が出力電圧Ｖｏｕｔとして交互に出力される。 (Output switching part)
In the first operation mode, the output switching unit 105 supplies the intermediate voltage V1 generated at the intermediate node N1 to the intermediate node N105 and outputs the intermediate voltage V2 generated at the intermediate node N2 to the output node Nout (output voltage Vout). To the node). In the second operation mode, the output switching unit 105 supplies the intermediate voltage V1 to the output node Nout and supplies the intermediate voltage V2 to the intermediate node N105. For example, the output switching unit 105 may include switches SW7 to SW10. The switch SW7 is connected between the intermediate node N1 and the output node Nout. Switch SW8 is connected between intermediate node N1 and intermediate node N105. The switch SW9 is connected between the intermediate node N2 and the output node Nout. Switch SW10 is connected between intermediate node N2 and intermediate node N105. The switches SW7 and SW10 are turned on / off in response to a control clock CKd (for example, an inverted clock of the control clock CKc). The switches SW8 and SW9 are turned on / off in response to the control clock CKc. When the logic level of the control clock CKc transitions from the low level to the high level, the switches SW7 and SW10 change from the on state to the off state and the switches SW8 and SW9 change from the off state to the on state. On the other hand, when the logic level of the control clock CKc transitions from the high level to the low level, the switches SW7 and SW10 change from the off state to the on state and the switches SW8 and SW9 change from the on state to the off state. In this way, the correspondence between the intermediate nodes N1, N2, the output node Nout, and the intermediate node N105 is periodically switched, so that the intermediate voltages V1, V2 are alternately output as the output voltage Vout.
　　〔電圧制御部〕
　電圧制御部１０６は、中間ノードＮ１０５に印加された電圧（中間電圧Ｖ１，Ｖ２のいずれか一方）が出力ノードＮｏｕｔに印加された電圧（中間電圧Ｖ１，Ｖ２のいずれか他方）に近づくように制御ノードＮｃｎｔに印加される制御電圧Ｖｃｎｔを制御する。例えば、電圧制御部１０６は、差動増幅器ＡＭＰと、制御トランジスタＴＣと、容量ＣＣと、抵抗ＲＲとを含んでいても良い。差動増幅器ＡＭＰは、中間ノードＮ１０５に印加された電圧と出力ノードＮｏｕｔに印加された電圧との差分（中間電圧Ｖ１，Ｖ２の差分）に応じた出力電圧を生成する。制御トランジスタＴＣは、電源ノード（電源電圧ＶＤＤが印加されるノード）と制御ノードＮｃｎｔとの間の電流経路に設けられる。容量ＣＣは、差動増幅器ＡＭＰの出力電圧を平滑化する。抵抗ＲＲは、電圧電流変換部１０２および負荷トランジスタ１０３１，１０３２によって構成される主差動増幅部の増幅利得が予め定められた上限値を超えないように主差動増幅部の増幅利得を制限するために設けられる。なお、電圧制御部１０６は、容量ＣＣおよび抵抗ＲＲを含んでいなくても良い。 (Voltage control unit)
The voltage control unit 106 controls the voltage applied to the intermediate node N105 (any one of the intermediate voltages V1 and V2) to approach the voltage applied to the output node Nout (the other one of the intermediate voltages V1 and V2). The control voltage Vcnt applied to the node Ncnt is controlled. For example, the voltage control unit 106 may include a differential amplifier AMP, a control transistor TC, a capacitor CC, and a resistor RR. The differential amplifier AMP generates an output voltage corresponding to the difference (difference between the intermediate voltages V1 and V2) between the voltage applied to the intermediate node N105 and the voltage applied to the output node Nout. Control transistor TC is provided in a current path between a power supply node (a node to which power supply voltage VDD is applied) and control node Ncnt. The capacitor CC smoothes the output voltage of the differential amplifier AMP. Resistor RR limits the amplification gain of the main differential amplifier so that the amplification gain of the main differential amplifier configured by voltage-current converter 102 and load transistors 1031 and 1032 does not exceed a predetermined upper limit value. Provided for. Note that the voltage control unit 106 may not include the capacitor CC and the resistor RR.
　　〔動作〕
　次に、図２を参照して、チョッパ増幅器１によるチョッパ動作について説明する。ここでは、説明の簡略化のために、負荷トランジスタ１０３１，１０３２の相互コンダクタンス値は互いに等しいものとしている。 [Operation]
Next, a chopper operation by the chopper amplifier 1 will be described with reference to FIG. Here, for simplification of explanation, the mutual conductance values of the load transistors 1031 and 1032 are assumed to be equal to each other.
　　《第１の動作モード》
　時刻ｔ１において、制御クロックＣＫｃの論理レベルがローレベルからハイレベルへ遷移するとともに制御クロックＣＫｄの論理レベルがハイレベルからローレベルへ遷移すると、入力切替部１０１は、入力電圧Ｖｉｎ１，Ｖｉｎ２を入力ノードＮｉｎ１，Ｎｉｎ２にそれぞれ供給し、接続切替部１０４は、共通ノードＮｃを中間ノードＮ２から切り離すとともに共通ノードＮｃを中間ノードＮ１に接続する。これにより、負荷トランジスタ１０３１，１０３２は、中間ノードＮ１，Ｎ２をそれぞれ入力端および出力端とする負荷カレントミラーを構成することになる。したがって、中間電圧Ｖ１の電圧値は、出力電圧Ｖｏｕｔの収束値（電圧値Ｖｒｄ）から共通電圧Ｖｎｃの収束値（電圧値Ｖｄｉｏ）に向けて徐々に増加し、中間電圧Ｖ２の電圧値は、電圧値Ｖｄｉｏから電圧値Ｖｒｄに向けて徐々に減少する。また、出力切替部１０５は、出力ノードＮｏｕｔを中間ノードＮ１から切り離すとともに出力ノードＮｏｕｔを中間ノードＮ２に接続する。これにより、出力ノードＮｏｕｔは、中間電圧Ｖ２によって充放電されることになる。 << First operation mode >>
At time t1, when the logic level of the control clock CKc transits from the low level to the high level and the logic level of the control clock CKd transits from the high level to the low level, the input switching unit 101 transfers the input voltages Vin1 and Vin2 to the input node. The connection switching unit 104 disconnects the common node Nc from the intermediate node N2 and connects the common node Nc to the intermediate node N1. As a result, the load transistors 1031 and 1032 form a load current mirror having the intermediate nodes N1 and N2 as input terminals and output terminals, respectively. Therefore, the voltage value of the intermediate voltage V1 gradually increases from the convergence value (voltage value Vrd) of the output voltage Vout toward the convergence value (voltage value Vdio) of the common voltage Vnc, and the voltage value of the intermediate voltage V2 is The value gradually decreases from the value Vdio toward the voltage value Vrd. Further, the output switching unit 105 disconnects the output node Nout from the intermediate node N1 and connects the output node Nout to the intermediate node N2. As a result, the output node Nout is charged / discharged by the intermediate voltage V2.
　　《第２の動作モード》
　次に、時刻ｔ２において、制御クロックＣＫｃの論理レベルがハイレベルからローレベルへ遷移するとともに制御クロックＣＫｄの論理レベルがローレベルからハイレベルへ遷移すると、入力切替部１０１は、入力電圧Ｖｉｎ１，Ｖｉｎ２を入力ノードＮｉｎ２，Ｎｉｎ１にそれぞれ供給し、接続切替部１０４は、共通ノードＮｃを中間ノードＮ１から切り離すとともに共通ノードＮｃを中間ノードＮ２に接続する。これにより、負荷トランジスタ１０３１，１０３２は、中間ノードＮ１，Ｎ２をそれぞれ出力端および入力端とする負荷カレントミラーを構成することになる。したがって、中間電圧Ｖ２の電圧値は、出力電圧Ｖｏｕｔの収束値（電圧値Ｖｒｄ）から共通電圧Ｖｎｃの収束値（電圧値Ｖｄｉｏ）に向けて徐々に増加し、中間電圧Ｖ１の電圧値は、電圧値Ｖｄｉｏから電圧値Ｖｒｄに向けて徐々に減少する。また、出力切替部１０５は、出力ノードＮｏｕｔを中間ノードＮ２から切り離すとともに出力ノードＮｏｕｔを中間ノードＮ１に接続する。これにより、出力ノードＮｏｕｔは、中間電圧Ｖ１によって充放電されることになる。 << Second operation mode >>
Next, at time t2, when the logic level of the control clock CKc transitions from the high level to the low level and the logic level of the control clock CKd transitions from the low level to the high level, the input switching unit 101 causes the input voltages Vin1 and Vin2 to be input. Are respectively supplied to the input nodes Nin2 and Nin1, and the connection switching unit 104 disconnects the common node Nc from the intermediate node N1 and connects the common node Nc to the intermediate node N2. Thereby, the load transistors 1031 and 1032 constitute a load current mirror having the intermediate nodes N1 and N2 as output terminals and input terminals, respectively. Therefore, the voltage value of the intermediate voltage V2 gradually increases from the convergence value (voltage value Vrd) of the output voltage Vout toward the convergence value (voltage value Vdio) of the common voltage Vnc, and the voltage value of the intermediate voltage V1 is The value gradually decreases from the value Vdio toward the voltage value Vrd. Further, the output switching unit 105 disconnects the output node Nout from the intermediate node N2 and connects the output node Nout to the intermediate node N1. As a result, the output node Nout is charged / discharged by the intermediate voltage V1.
　このように、第１および第２の動作モードを交互に切り替えることにより、チョッパ増幅器１のうち入力切替部１０１を除く部分のフリッカノイズをチョッパ周波数（制御クロックＣＫｃ，ＣＫｂの周波数）の整数倍の周波数を有する高調波の近傍に分散できる。 In this way, by alternately switching between the first and second operation modes, flicker noise in a portion of the chopper amplifier 1 excluding the input switching unit 101 is an integral multiple of the chopper frequency (frequency of the control clocks CKc and CKb). It can be distributed in the vicinity of harmonics having a frequency.
　また、第１および第２の動作モードが交互に切り替わることによって、中間電圧Ｖ１，Ｖ２の電圧値は、共通電圧Ｖｎｃの収束値（電圧値Ｖｄｉｏ）と出力電圧Ｖｏｕｔの収束値（電圧値Ｖｒｄ）との間を相補的に変動することになる。ここで、出力電圧Ｖｏｕｔのセトリング時間Ｔｓがチョッパ周期（例えば、時刻ｔ１～ｔ２の期間）よりも長くなると、チョッパ周期中において出力電圧Ｖｏｕｔの電圧値が収束値（電圧値Ｖｒｄ）に到達できなくなる（チョッパ増幅器１が平衡状態にならなくなる）。そのため、出力電圧Ｖｏｕｔにセトリング誤差が生じ、セトリング誤差がオフセット電圧として出力電圧Ｖｏｕｔに含まれることになる。なお、出力電圧Ｖｏｕｔの変動幅（Ｖｄｉｏ－Ｖｒｄ）が大きくなるほど、出力電圧Ｖｏｕｔのセトリング時間Ｔｓがチョッパ周期よりも短い場合に生じる出力電圧Ｖｏｕｔのセトリング誤差（オフセット電圧）も大きくなる。また、共通電圧Ｖｎｃの収束値（電圧値Ｖｄｉｏ）は、制御電圧Ｖｃｎｔの電圧値に応じて変動する。出力電圧Ｖｏｕｔの収束値（電圧値Ｖｒｄ）は、入力電圧Ｖｉｎ１，Ｖｉｎ２の電圧差および出力ノードＮｏｕｔに接続された負荷に応じて変動する。 Further, by alternately switching the first and second operation modes, the voltage values of the intermediate voltages V1 and V2 are the convergence value of the common voltage Vnc (voltage value Vdio) and the convergence value of the output voltage Vout (voltage value Vrd). Fluctuate in a complementary manner. Here, if the settling time Ts of the output voltage Vout becomes longer than the chopper period (for example, the period from time t1 to t2), the voltage value of the output voltage Vout cannot reach the convergence value (voltage value Vrd) during the chopper period. (The chopper amplifier 1 is not balanced). Therefore, a settling error occurs in the output voltage Vout, and the settling error is included in the output voltage Vout as an offset voltage. Note that the settling error (offset voltage) of the output voltage Vout that occurs when the settling time Ts of the output voltage Vout is shorter than the chopper period increases as the fluctuation range (Vdio−Vrd) of the output voltage Vout increases. Further, the convergence value (voltage value Vdio) of the common voltage Vnc varies according to the voltage value of the control voltage Vcnt. The convergence value (voltage value Vrd) of the output voltage Vout varies according to the voltage difference between the input voltages Vin1 and Vin2 and the load connected to the output node Nout.
　　〔基準電圧の制御〕
　次に、図３を参照して、チョッパ増幅器１における制御電圧Ｖｃｎｔの制御について説明する。ここでは、説明の簡略化のために、負荷トランジスタ１０３１，１０３２の相互コンダクタンス値は互いに等しいものとしている。 [Control of reference voltage]
Next, control of the control voltage Vcnt in the chopper amplifier 1 will be described with reference to FIG. Here, for simplification of explanation, the mutual conductance values of the load transistors 1031 and 1032 are assumed to be equal to each other.
　共通電圧Ｖｎｃの収束値が出力電圧Ｖｏｕｔの収束値よりも高い場合、時刻ｔ１～ｔ２の期間では、中間電圧Ｖ１が中間電圧Ｖ２よりも高くなり、時刻ｔ２～ｔ３の期間では、中間電圧Ｖ２が中間電圧Ｖ１よりも高くなる。この場合、電圧制御部１０６は、時刻ｔ１～ｔ２の期間では、中間電圧Ｖ１，Ｖ２の差分（Ｖ１－Ｖ２）に応じて制御電圧Ｖｃｎｔの電圧値を減少させることになり、時刻ｔ２～ｔ３の期間では、中間電圧Ｖ１，Ｖ２の差分（Ｖ２－Ｖ１）に応じて制御電圧Ｖｃｎｔの電圧値を減少させることになる。制御電圧Ｖｃｎｔの電圧値が減少することにより、共通電圧Ｖｎｃの収束値は、電圧値Ｖｄｉｏ１から電圧値Ｖｄｉｏ２に減少し、共通電圧Ｖｎｃの収束値が出力電圧Ｖｏｕｔの収束値に近づくことになる。これにより、出力電圧Ｖｏｕｔの変動幅は、変動幅（Ｖｄｉｏ１－Ｖｒｄ）から変動幅（Ｖｄｉｏ２－Ｖｒｄ）に減少する。 When the convergence value of the common voltage Vnc is higher than the convergence value of the output voltage Vout, the intermediate voltage V1 is higher than the intermediate voltage V2 in the period from time t1 to t2, and the intermediate voltage V2 is increased in the period from time t2 to t3. It becomes higher than the intermediate voltage V1. In this case, the voltage control unit 106 decreases the voltage value of the control voltage Vcnt according to the difference (V1−V2) between the intermediate voltages V1 and V2 during the period from time t1 to time t2, and from time t2 to time t3. In the period, the voltage value of the control voltage Vcnt is decreased according to the difference (V2−V1) between the intermediate voltages V1 and V2. As the voltage value of the control voltage Vcnt decreases, the convergence value of the common voltage Vnc decreases from the voltage value Vdio1 to the voltage value Vdio2, and the convergence value of the common voltage Vnc approaches the convergence value of the output voltage Vout. As a result, the fluctuation range of the output voltage Vout decreases from the fluctuation range (Vdio1-Vrd) to the fluctuation range (Vdio2-Vrd).
　以上のように、共通電圧Ｖｎｃの収束値を出力電圧Ｖｏｕｔの収束値に近づけることにより、出力電圧Ｖｏｕｔの変動幅を減少させることができる。したがって、出力電圧Ｖｏｕｔのセトリング時間Ｔｓがチョッパ周期よりも長くなった場合に生じる出力電圧Ｖｏｕｔのセトリング誤差を小さくすることができる。そのため、チョッパ機構の応答速度に左右されずに出力電圧Ｖｏｕｔに含まれるオフセット電圧を低減できる。これにより、図４のように、温度変化や電源電圧の変動によって出力電圧Ｖｏｕｔが変動することを抑制できる。なお、図４では、点線は、制御電圧Ｖｃｎｔを制御しない場合（制御電圧Ｖｃｎｔが定電圧である場合）の温度特性に対応し、実線は、電圧制御部１０６によって制御電圧Ｖｃｎｔを制御する場合の温度特性に対応する。 As described above, the fluctuation range of the output voltage Vout can be reduced by bringing the convergence value of the common voltage Vnc closer to the convergence value of the output voltage Vout. Therefore, the settling error of the output voltage Vout that occurs when the settling time Ts of the output voltage Vout becomes longer than the chopper period can be reduced. Therefore, the offset voltage included in the output voltage Vout can be reduced without being influenced by the response speed of the chopper mechanism. Thereby, as shown in FIG. 4, it is possible to suppress the output voltage Vout from fluctuating due to a temperature change or a power supply voltage fluctuation. In FIG. 4, the dotted line corresponds to the temperature characteristics when the control voltage Vcnt is not controlled (when the control voltage Vcnt is a constant voltage), and the solid line indicates the case where the control voltage Vcnt is controlled by the voltage control unit 106. Corresponds to temperature characteristics.
　さらに、主差動増幅部（電圧電流変換部１０２および負荷トランジスタ１０３１，１０３２によって構成される差動増幅部）の電源に相当する制御電圧を制御することにより、電圧制御部１０６において発生したノイズを主差動増幅部の電源電圧変動除去比（ＰＳＲＲ）によって低減できるので、出力電圧Ｖｏｕｔのノイズ増加を抑制できる。 Further, by controlling the control voltage corresponding to the power source of the main differential amplifier (the differential amplifier configured by the voltage / current converter 102 and the load transistors 1031 and 1032), noise generated in the voltage controller 106 is reduced. Since it can be reduced by the power supply voltage fluctuation rejection ratio (PSRR) of the main differential amplifier, an increase in noise of the output voltage Vout can be suppressed.
　また、特許文献２に記載された技術では、補正用レプリカ回路が差動増幅器の半回路に相当するので、補正用レプリカ回路を含む差動増幅器の消費電流は、補正用レプリカ回路を含まない場合の差動増幅器の消費電流の１．５倍になってしまう。一方、図１に示したチョッパ増幅器１では、差動増幅器ＡＭＰの周波数帯域を主差動増幅部の周波数帯域よりも低くすることができるので、消費電力の増大を抑制できる。なお、差動増幅器ＡＭＰの周波数帯域は、主差動増幅部の周波数帯域よりも低くなくても良い。 In the technique described in Patent Document 2, since the correction replica circuit corresponds to a half circuit of the differential amplifier, the consumption current of the differential amplifier including the correction replica circuit does not include the correction replica circuit. The current consumption of the differential amplifier becomes 1.5 times. On the other hand, in the chopper amplifier 1 shown in FIG. 1, since the frequency band of the differential amplifier AMP can be made lower than the frequency band of the main differential amplifier, an increase in power consumption can be suppressed. Note that the frequency band of the differential amplifier AMP may not be lower than the frequency band of the main differential amplifier.
　また、特許文献３に記載された技術では、カスコード接続構造が設けられているので、電源電圧を低減することが困難である。一方、図１に示したチョッパ増幅器では、カスコード接続構造を設けなくても良いので、電源電圧を低減できる。 Moreover, in the technique described in Patent Document 3, since the cascode connection structure is provided, it is difficult to reduce the power supply voltage. On the other hand, the chopper amplifier shown in FIG. 1 does not have to have a cascode connection structure, so that the power supply voltage can be reduced.
　なお、チョッパ増幅器１は、第１の動作モードから過渡モードを経て第２の動作モードに切り替わり、第２の動作モードから過渡モードを経て第１の動作モードに切り替わるものであっても良い。過渡モードでは、入力切替部１０１は、入力電圧Ｖｉｎ１，Ｖｉｎ２を入力ノードＮｉｎ１，Ｎｉｎ２のいずれにも供給せず、接続切替部１０４は、共通ノードＮｃを中間ノードＮ１，Ｎ２のいずれにも接続せず、出力切替部１０５は、中間電圧Ｖ１，Ｖ２を中間ノードＮ１０５および出力ノードＮｏｕｔのいずれにも供給しない。例えば、このような動作を実現するために、制御クロックＣＫｃ，ＣＫｄは、それぞれの有効出力期間（ここでは、ハイレベル出力期間）が互いに重複しないノンオーバーラップクロックであっても良い。 In addition, the chopper amplifier 1 may be switched from the first operation mode to the second operation mode through the transient mode, and from the second operation mode to the first operation mode through the transient mode. In the transient mode, the input switching unit 101 does not supply the input voltages Vin1 and Vin2 to any of the input nodes Nin1 and Nin2, and the connection switching unit 104 connects the common node Nc to any of the intermediate nodes N1 and N2. The output switching unit 105 does not supply the intermediate voltages V1 and V2 to either the intermediate node N105 or the output node Nout. For example, in order to realize such an operation, the control clocks CKc and CKd may be non-overlapping clocks whose effective output periods (here, high-level output periods) do not overlap each other.
　（アクティブフィルタ）
　図５は、図１に示したチョッパ増幅器１を備えるアクティブフィルタの構成例を示す。アクティブフィルタ２は、チョッパ増幅器１の他に、抵抗Ｒ１と、容量Ｃ１とを備える。抵抗Ｒ１の一端は、入力ノードＮ２１に接続され、抵抗Ｒ１の他端は、中間ノードＮ２０に接続される。入力ノードＮ２１，Ｎ２２には、それぞれ、信号電圧ＶＳ２１，ＶＳ２２が印加される。容量Ｃ１の一端は、中間ノードＮ２０に接続され、容量Ｃ１の他端は、チョッパ増幅器１の出力ノードＮｏｕｔに接続される。チョッパ増幅器１は、中間ノードＮ２０に発生する中間電圧Ｖｎを入力電圧Ｖｉｎ１，Ｖｉｎ２の一方として受けるとともに入力ノードＮ２２に印加された信号電圧ＶＳ２２を入力電圧Ｖｉｎ１，Ｖｉｎ２の他方として受ける。このように構成することにより、信号電圧ＶＳ２１の振幅に比例する中間電圧Ｖｎを抽出する機能（信号抽出機能）と中間電圧と信号電圧ＶＳ２２との差分に応じた出力電圧Ｖｏｕｔを出力する機能（差分出力機能）とを有するアクティブフィルタを実現できる。 (Active filter)
FIG. 5 shows a configuration example of an active filter including the chopper amplifier 1 shown in FIG. The active filter 2 includes a resistor R1 and a capacitor C1 in addition to the chopper amplifier 1. One end of the resistor R1 is connected to the input node N21, and the other end of the resistor R1 is connected to the intermediate node N20. Signal voltages VS21 and VS22 are applied to input nodes N21 and N22, respectively. One end of the capacitor C1 is connected to the intermediate node N20, and the other end of the capacitor C1 is connected to the output node Nout of the chopper amplifier 1. The chopper amplifier 1 receives the intermediate voltage Vn generated at the intermediate node N20 as one of the input voltages Vin1 and Vin2, and receives the signal voltage VS22 applied to the input node N22 as the other of the input voltages Vin1 and Vin2. With this configuration, the function of extracting the intermediate voltage Vn proportional to the amplitude of the signal voltage VS21 (signal extraction function) and the function of outputting the output voltage Vout corresponding to the difference between the intermediate voltage and the signal voltage VS22 (difference) An active filter having an output function can be realized.
　（アクティブフィルタの変形例１）
　図６は、アクティブフィルタの変形例１を示す。アクティブフィルタ２ａは、図５に示したアクティブフィルタ２の構成に加えて、容量Ｃ２を備える。容量Ｃ２の一端は、チョッパ増幅器１の出力ノードＮｏｕｔに接続され、容量Ｃ２の他端は、接地ノード（接地電圧ＧＮＤが印加される基準ノード）に接続される。ここでは、容量Ｃ１の他端は、チョッパ増幅器１の出力ノードＮｏｕｔではなく接地ノードに接続される。その他の構成は、図５と同様である。このように構成した場合も、信号抽出機能と差分出力機能とを有するアクティブフィルタを実現できる。 (Modification 1 of the active filter)
FIG. 6 shows a first modification of the active filter. The active filter 2a includes a capacitor C2 in addition to the configuration of the active filter 2 shown in FIG. One end of the capacitor C2 is connected to the output node Nout of the chopper amplifier 1, and the other end of the capacitor C2 is connected to a ground node (a reference node to which the ground voltage GND is applied). Here, the other end of the capacitor C1 is connected not to the output node Nout of the chopper amplifier 1 but to the ground node. Other configurations are the same as those in FIG. Even in such a configuration, an active filter having a signal extraction function and a differential output function can be realized.
　（アクティブフィルタの変形例２）
　図７は、アクティブフィルタの変形例２を示す。アクティブフィルタ２ｂは、図５に示したアクティブフィルタ２の構成に加えて、抵抗Ｒ２を備える。抵抗Ｒ２の一端は、入力ノードＮ２３に接続され、抵抗Ｒ２の他端は、中間ノードＮ２０に接続される。入力ノードＮ２３には、信号電圧ＶＳ２３が印加される。このように構成することにより、信号電圧ＶＳ２１，ＶＳ２３の合成電圧の振幅に比例する中間電圧Ｖｎを抽出する機能（信号抽出機能）と中間電圧と信号電圧ＶＳ２２との差分に応じた出力電圧Ｖｏｕｔを出力する機能（差分出力機能）とを有するアクティブフィルタを実現できる。 (Modification 2 of the active filter)
FIG. 7 shows a second modification of the active filter. The active filter 2b includes a resistor R2 in addition to the configuration of the active filter 2 shown in FIG. One end of the resistor R2 is connected to the input node N23, and the other end of the resistor R2 is connected to the intermediate node N20. A signal voltage VS23 is applied to the input node N23. With this configuration, the function of extracting the intermediate voltage Vn proportional to the amplitude of the combined voltage of the signal voltages VS21 and VS23 (signal extraction function) and the output voltage Vout corresponding to the difference between the intermediate voltage and the signal voltage VS22 are obtained. An active filter having an output function (difference output function) can be realized.
　（アクティブフィルタの変形例３）
　図８は、アクティブフィルタの変形例３を示す。アクティブフィルタ２ｃは、図６に示したアクティブフィルタ２ａの構成に加えて、抵抗Ｒ２を備える。抵抗Ｒ２の一端は、入力ノードＮ２３に接続され、抵抗Ｒ２の他端は、中間ノードＮ２０に接続される。入力ノードＮ２３には、信号電圧ＶＳ２３が印加される。このように構成した場合も、信号抽出機能と差分出力機能とを有するアクティブフィルタを実現できる。 (Modification 3 of the active filter)
FIG. 8 shows a third modification of the active filter. The active filter 2c includes a resistor R2 in addition to the configuration of the active filter 2a shown in FIG. One end of the resistor R2 is connected to the input node N23, and the other end of the resistor R2 is connected to the intermediate node N20. A signal voltage VS23 is applied to the input node N23. Even in such a configuration, an active filter having a signal extraction function and a differential output function can be realized.
　（基準周波数生成回路）
　図９は、図５に示したアクティブフィルタ２を備える基準周波数生成回路の構成例を示す。基準周波数生成回路１００は、基準クロックＣＫａ，ＣＫｂを生成するものであり、発振回路１１と、発振制御回路１２と、基準電圧生成回路１３と、レファレンス制御回路１４とを備える。基準クロックＣＫａ，ＣＫｂは、それぞれ、発振回路１１の時定数に対応する周波数を有し、それぞれの信号レベルは、互いに相補的に変動する。 (Reference frequency generation circuit)
FIG. 9 shows a configuration example of a reference frequency generation circuit including the active filter 2 shown in FIG. The reference frequency generation circuit 100 generates reference clocks CKa and CKb, and includes an oscillation circuit 11, an oscillation control circuit 12, a reference voltage generation circuit 13, and a reference control circuit 14. Each of the reference clocks CKa and CKb has a frequency corresponding to the time constant of the oscillation circuit 11, and the respective signal levels fluctuate complementarily.
　　〔発振回路および発振制御回路〕
　発振回路１１は、基準クロックＣＫａ，ＣＫｂの信号レベルの遷移に応答して、発振信号ＯＳＣａ，ＯＳＣｂの信号レベルを相補的に増減させる。発振回路１１は、発振信号ＯＳＣａ，ＯＳＣｂをそれぞれ生成するための容量Ｃａ，Ｃｂと、定電流を供給するための定電流源ＣＳ１１１ａ，ＣＳ１１１ｂと、容量Ｃａ，Ｃｂの接続状態を切り換えるためのスイッチＳＷ１ａ，ＳＷ２ａ，ＳＷ１ｂ，ＳＷ２ｂ（接続切換部）とを含む。発振制御回路１２は、発振信号ＯＳＣａの信号レベル（または、発振信号ＯＳＣｂの信号レベル）が比較電圧ＶＲよりも高くなったことを検出すると基準クロックＣＫａ，ＣＫｂの信号レベルを遷移させる。発振制御回路１２は、比較電圧ＶＲと発振信号ＯＳＣａの信号レベルとを比較する比較器ＣＭＰａと、比較電圧ＶＲと発振信号ＯＳＣｂの信号レベルとを比較する比較器ＣＭＰｂと、比較器ＣＭＰａ，ＣＭＰｂの出力信号ＯＵＴａ，ＯＵＴｂを受けて基準クロックＣＫａ，ＣＫｂを出力するＲＳラッチ回路１１２とを含む。 [Oscillation circuit and oscillation control circuit]
The oscillation circuit 11 increases or decreases the signal levels of the oscillation signals OSCa and OSCb in a complementary manner in response to the transition of the signal levels of the reference clocks CKa and CKb. The oscillation circuit 11 includes capacitors Ca and Cb for generating oscillation signals OSCa and OSCb, constant current sources CS111a and CS111b for supplying constant current, and a switch SW1a for switching the connection state of the capacitors Ca and Cb. , SW2a, SW1b, SW2b (connection switching unit). When the oscillation control circuit 12 detects that the signal level of the oscillation signal OSCa (or the signal level of the oscillation signal OSCb) is higher than the comparison voltage VR, the oscillation control circuit 12 transitions the signal levels of the reference clocks CKa and CKb. The oscillation control circuit 12 includes a comparator CMPa that compares the comparison voltage VR and the signal level of the oscillation signal OSCa, a comparator CMPb that compares the comparison voltage VR and the signal level of the oscillation signal OSCb, and comparators CMPa and CMPb. RS latch circuit 112 which receives output signals OUTa and OUTb and outputs reference clocks CKa and CKb.
　　〔基準電圧生成回路〕
　基準電圧生成回路１３は、接地電圧ＧＮＤに対して所定の電圧差を有する定電圧を基準電圧Ｖｒｅｆとして生成する。基準電圧生成回路１３は、バンドギャップレファレンス回路（ＢＧＲ）１１３と、定電圧回路（ｐＭＯＳトランジスタＴ１１３，抵抗Ｒ１１２，Ｒ１１３，差動増幅回路Ａ１１３）とを含む。 [Reference voltage generator]
The reference voltage generation circuit 13 generates a constant voltage having a predetermined voltage difference as the reference voltage Vref with respect to the ground voltage GND. The reference voltage generation circuit 13 includes a band gap reference circuit (BGR) 113 and a constant voltage circuit (pMOS transistor T113, resistors R112, R113, differential amplifier circuit A113).
　　〔レファレンス制御回路〕
　レファレンス制御回路１４は、発振信号ＯＳＣａ，ＯＳＣｂのそれぞれの振幅に比例する中間信号の信号レベル（ここでは、発振信号ＯＳＣａ，ＯＳＣｂの各時定数波形の累積平均電圧）と基準電圧Ｖｒｅｆとの差が小さくなるように、比較電圧ＶＲを増減させる。レファレンス制御回路１４は、スイッチ１１４ａ，１１４ｂ（スイッチ回路）と、アクティブフィルタ２とを含む。 [Reference control circuit]
The reference control circuit 14 determines the difference between the signal level of the intermediate signal proportional to the amplitude of each of the oscillation signals OSCa and OSCb (here, the cumulative average voltage of each time constant waveform of the oscillation signals OSCa and OSCb) and the reference voltage Vref. The comparison voltage VR is increased or decreased so as to decrease. The reference control circuit 14 includes switches 114 a and 114 b (switch circuit) and the active filter 2.
　基準クロックＣＫｂの信号レベルがハイレベルである場合、スイッチ１１４ａは、オン状態になり、発振信号ＯＳＣａを通過させる。一方、基準クロックＣＫａの信号レベルはローレベルであるので、スイッチ１１４ｂは、オフ状態になり、発振信号ＯＳＣｂを遮断する。また、基準クロックＣＫｂの信号レベルがローレベルである場合、スイッチ１１４ａは、オフ状態になり、発振信号ＯＳＣａを遮断する。一方、基準クロックＣＫａの信号レベルはハイレベルであるので、スイッチ１１４ａは、オン状態になり、発振信号ＯＳＣｂを通過させる。このように、基準クロックＣＫａ，ＣＫｂの信号レベルの遷移に応答して発振信号ＯＳＣａ，ＯＳＣｂを交互に通過させることにより、基準クロックＣＫａ，ＣＫｂのそれぞれの時定数波形成分（発振回路１１の時定数で増加する波形成分）がアクティブフィルタ２に供給される。 When the signal level of the reference clock CKb is high, the switch 114a is turned on to pass the oscillation signal OSCa. On the other hand, since the signal level of the reference clock CKa is low, the switch 114b is turned off and cuts off the oscillation signal OSCb. On the other hand, when the signal level of the reference clock CKb is low, the switch 114a is turned off to cut off the oscillation signal OSCa. On the other hand, since the signal level of the reference clock CKa is high, the switch 114a is turned on to pass the oscillation signal OSCb. As described above, by alternately passing the oscillation signals OSCa and OSCb in response to the transition of the signal levels of the reference clocks CKa and CKb, the respective time constant waveform components of the reference clocks CKa and CKb (the time constant of the oscillation circuit 11). (The waveform component that increases in step) is supplied to the active filter 2.
　アクティブフィルタ２は、スイッチ１１４ａ，１１４ｂを通過した発振信号ＯＳＣａ，ＯＳＣｂからその発振信号の振幅に比例する中間信号を抽出する機能（信号抽出機能）と、中間信号の信号レベルと基準電圧Ｖｒｅｆとの差に対応する比較電圧ＶＲを出力する機能（差分出力機能）とを有する。ここでは、アクティブフィルタ２は、スイッチ１１４ａ，１１４ｂを通過した発振信号Ｓｘ（発振信号ＯＳＣａ，ＯＳＣｂのいずれか一方）を信号電圧ＶＳ２１として受けるとともに基準電圧Ｖｒｅｆを信号電圧ＶＳ２２として受け、アクティブフィルタ２の出力電圧Ｖｏｕｔは、比較電圧ＶＲとして供給される。 The active filter 2 has a function (signal extraction function) for extracting an intermediate signal proportional to the amplitude of the oscillation signal from the oscillation signals OSCa and OSCb that have passed through the switches 114a and 114b, and the signal level of the intermediate signal and the reference voltage Vref. A function of outputting a comparison voltage VR corresponding to the difference (difference output function). Here, the active filter 2 receives the oscillation signal Sx (one of the oscillation signals OSCa and OSCb) that has passed through the switches 114a and 114b as the signal voltage VS21 and the reference voltage Vref as the signal voltage VS22. The output voltage Vout is supplied as the comparison voltage VR.
　以上のように、発振信号ＯＳＣａ，ＯＳＣｂのそれぞれの振幅が一定になるようにフィードバック制御を施すことにより、遅延時間の変動に起因する基準クロックＣＫａ，ＣＫｂの周波数変動を抑制できる。これにより、消費電力（特に、比較器ＣＭＰａ，ＣＭＰｂの消費電力）の増大を抑制しつつ基準クロックＣＫａ，ＣＫｂの周波数を高速化できる。さらに、フィードバック制御のループ帯域よりも低域のノイズ成分が減衰されるので、基準周波数生成回路内の低周波ノイズ（例えば、比較電圧ＶＲの低周波ノイズや、比較器ＣＭＰａ，ＣＭＰｂの出力ノイズなど）を低減できる。これにより、基準周波数生成回路１００の共振特性（Ｑ値）を向上させることができ、基準クロックＣＫａ，ＣＫｂの周波数ばらつきを低減できる。 As described above, by performing feedback control so that the amplitudes of the oscillation signals OSCa and OSCb are constant, the frequency fluctuations of the reference clocks CKa and CKb due to the fluctuation of the delay time can be suppressed. Thereby, the frequency of the reference clocks CKa and CKb can be increased while suppressing an increase in power consumption (particularly, power consumption of the comparators CMPa and CMPb). Further, since a noise component lower than the loop band of the feedback control is attenuated, low frequency noise in the reference frequency generation circuit (for example, low frequency noise of the comparison voltage VR, output noise of the comparators CMPa and CMPb, etc.) ) Can be reduced. Thereby, the resonance characteristic (Q value) of the reference frequency generating circuit 100 can be improved, and the frequency variation of the reference clocks CKa and CKb can be reduced.
　また、基準電圧生成回路１３は、接地電圧ＧＮＤを基準として基準電圧Ｖｒｅｆを生成するので、電源電圧ＶＤＤが変動しても基準電圧Ｖｒｅｆは変動しない。そのため、比較電圧ＶＲの不要な変動が抑制され、その結果、電源電圧ＶＤＤの変動に起因する基準クロックＣＫａ，ＣＫｂの周波数変動を抑制できる。 Further, since the reference voltage generation circuit 13 generates the reference voltage Vref with reference to the ground voltage GND, the reference voltage Vref does not change even if the power supply voltage VDD changes. Therefore, unnecessary fluctuations in the comparison voltage VR are suppressed, and as a result, frequency fluctuations in the reference clocks CKa and CKb caused by fluctuations in the power supply voltage VDD can be suppressed.
　また、アクティブフィルタ２に含まれるチョッパ増幅器１のチョッパ動作により、比較電圧ＶＲ（出力電圧Ｖｏｕｔ）に重畳されたフリッカノイズをチョッパ周波数の整数倍の周波数を有する高調波の近傍に分散でき、これらの高調波に分散されたフリッカノイズをアクティブフィルタ２によって減衰させることができるので、基準周波数生成回路の共振特性（Ｑ値）をさらに向上させることができる。 Further, the chopper operation of the chopper amplifier 1 included in the active filter 2 can disperse flicker noise superimposed on the comparison voltage VR (output voltage Vout) in the vicinity of harmonics having a frequency that is an integral multiple of the chopper frequency. Since the flicker noise dispersed in the harmonics can be attenuated by the active filter 2, the resonance characteristic (Q value) of the reference frequency generation circuit can be further improved.
　また、チョッパ増幅器１において制御電圧を制御することによって比較電圧ＶＲ（出力電圧Ｖｏｕｔ）にセトリング誤差が発生することを抑制できるので、図１０のように、温度変化や電源電圧の変動による基準クロックＣＫａ，ＣＫｂの周波数変動を抑制できる。図１０では、点線は、制御電圧Ｖｃｎｔを制御しない場合（制御電圧Ｖｃｎｔが定電圧である場合）の温度特性に対応し、実線は、制御電圧Ｖｃｎｔを制御する場合の温度特性に対応する。 Further, by controlling the control voltage in the chopper amplifier 1, it is possible to suppress the occurrence of a settling error in the comparison voltage VR (output voltage Vout). Therefore, as shown in FIG. 10, the reference clock CKa due to a temperature change or a power supply voltage change. , CKb frequency fluctuation can be suppressed. In FIG. 10, the dotted line corresponds to the temperature characteristic when the control voltage Vcnt is not controlled (when the control voltage Vcnt is a constant voltage), and the solid line corresponds to the temperature characteristic when the control voltage Vcnt is controlled.
　なお、アクティブフィルタ２に含まれるチョッパ増幅器１は、分周回路（図示せず）によって分周された基準クロックＣＫａ，ＣＫｂを制御クロックＣＫｃ，ＣＫｄとして受けても良い。このように構成することにより、分周回路を介さずに基準クロックＣＫａ，ＣＫｂをそのまま制御クロックＣＫｃ，ＣＫｄとしてチョッパ増幅器１に供給する場合よりも、チョッパ増幅器１による負荷容量（例えば、信号経路の寄生容量）の充放電時間を長くすることができる。これにより、チョッパ増幅器１の駆動能力を低くすることができるので、チョッパ増幅器１の消費電力を低減できる。なお、チョッパ増幅器１は、分周回路を介さずに基準クロックＣＫａ，ＣＫｂをそのまま制御クロックＣＫｃ，ＣＫｄとして受けても良いし、基準周波数生成回路１００の内部信号（例えば、発振信号ＯＳＣａ，ＯＳＣｂ）を制御クロックＣＫｃ，ＣＫｄとして受けても良い。 Note that the chopper amplifier 1 included in the active filter 2 may receive the reference clocks CKa and CKb divided by a frequency dividing circuit (not shown) as control clocks CKc and CKd. By configuring in this way, the load capacity (for example, the signal path of the signal path) by the chopper amplifier 1 can be improved as compared with the case where the reference clocks CKa and CKb are directly supplied to the chopper amplifier 1 as control clocks CKc and CKd without using a frequency divider. The charge / discharge time of (parasitic capacitance) can be increased. Thereby, since the driving capability of the chopper amplifier 1 can be lowered, the power consumption of the chopper amplifier 1 can be reduced. The chopper amplifier 1 may receive the reference clocks CKa and CKb as they are as the control clocks CKc and CKd without going through the frequency dividing circuit, or the internal signals of the reference frequency generation circuit 100 (for example, the oscillation signals OSCa and OSCb). May be received as control clocks CKc and CKd.
　また、レファレンス制御回路１４は、図９に示したアクティブフィルタ２に代えて、図６に示したアクティブフィルタ２ａを含んでいても良い。 Further, the reference control circuit 14 may include an active filter 2a shown in FIG. 6 instead of the active filter 2 shown in FIG.
　（基準周波数生成回路の変形例１）
　図１１は、基準周波数生成回路の変形例１を示す。基準周波数生成回路２００は、発振回路２１と、発振制御回路１２と、基準電圧生成回路２３と、レファレンス制御回路２４とを備える。 (Modification 1 of the reference frequency generation circuit)
FIG. 11 shows a first modification of the reference frequency generation circuit. The reference frequency generation circuit 200 includes an oscillation circuit 21, an oscillation control circuit 12, a reference voltage generation circuit 23, and a reference control circuit 24.
　発振回路２１は、図１に示した定電流源ＣＳ１１１ａ，ＣＳ１１１ｂに代えて、抵抗Ｒ２１１ａ，Ｒ２１１ｂを含む。このように、定電流源ＣＳ１１１ａ，ＣＳ１１１ｂを抵抗Ｒ２１１ａ，Ｒ２１１ｂに置き換えることにより、定電流源に発生する１／ｆノイズ（周波数に反比例するノイズ成分）を除去できるので、図９に示した基準周波数生成回路１００よりも基準クロックＣＫａ，ＣＫｂの周波数の安定性を向上させることができる。さらに、抵抗Ｒ２１１ａ，Ｒ２１１ｂは、定電流源ＣＳ１１１ａ，ＣＳ１１１ｂよりも経年劣化が少ないので、長期間に渡って基準クロックＣＫａ，ＣＫｂを精度良く生成できる。 The oscillation circuit 21 includes resistors R211a and R211b instead of the constant current sources CS111a and CS111b shown in FIG. In this way, by replacing the constant current sources CS111a and CS111b with the resistors R211a and R211b, 1 / f noise (noise component inversely proportional to the frequency) generated in the constant current source can be removed, so that the reference frequency shown in FIG. The frequency stability of the reference clocks CKa and CKb can be improved compared to the generation circuit 100. Furthermore, since the resistors R211a and R211b have less aging degradation than the constant current sources CS111a and CS111b, the reference clocks CKa and CKb can be accurately generated over a long period of time.
　基準電圧生成回路２３は、抵抗Ｒ２１２，Ｒ２１３を含む。抵抗Ｒ２１２，Ｒ２１３は、電源電圧ＶＤＤおよび接地電圧ＧＮＤの電圧間を抵抗分割することによって、基準電圧Ｖｒｅｆを生成する。 The reference voltage generation circuit 23 includes resistors R212 and R213. Resistors R212 and R213 generate reference voltage Vref by dividing resistance between power supply voltage VDD and ground voltage GND.
　レファレンス制御回路２４は、図９に示したスイッチ１１４ａ，１１４ｂに代えて、抵抗２１１ａ，２１１ｂを含む。抵抗２１１ａ，２１１ｂのそれぞれの一端は、アクティブフィルタ２に接続され、抵抗２１１ａの他端には発振信号ＯＳＣａが供給され、抵抗２１１ｂの他端には発振信号ＯＳＣｂが供給される。ここでは、アクティブフィルタ２は、発振信号Ｓｘ（抵抗２１１ａ，２１１ｂによって発振信号ＯＳＣａ，ＯＳＣｂを抵抗分割することによって生成された信号）を信号電圧ＶＳ２１として受けるとともに基準電圧Ｖｒｅｆを信号電圧ＶＳ２２として受け、アクティブフィルタ２の出力電圧Ｖｏｕｔは、比較電圧ＶＲとして供給される。 The reference control circuit 24 includes resistors 211a and 211b instead of the switches 114a and 114b shown in FIG. One end of each of the resistors 211a and 211b is connected to the active filter 2, and an oscillation signal OSCa is supplied to the other end of the resistor 211a, and an oscillation signal OSCb is supplied to the other end of the resistor 211b. Here, the active filter 2 receives the oscillation signal Sx (a signal generated by resistance-dividing the oscillation signals OSCa and OSCb by the resistors 211a and 211b) as the signal voltage VS21 and the reference voltage Vref as the signal voltage VS22. The output voltage Vout of the active filter 2 is supplied as the comparison voltage VR.
　なお、レファレンス制御回路２４は、図１１に示したアクティブフィルタ２に代えて、図６に示したアクティブフィルタ２ａを含んでいても良い。また、基準周波数生成回路２００は、図１１に示したレファレンス制御回路２４に代えて、図９に示したレファレンス制御回路１４を備えていても良いし、図７，図８に示したアクティブフィルタ２ｂ，２ｃをレファレンス制御回路として備えていても良い。この場合、アクティブフィルタ２ｂ，２ｃは、発振信号ＯＳＣａ，ＯＳＣｂを信号電圧ＶＳ２１，ＶＳ２３としてそれぞれ受けるとともに基準電圧Ｖｒｅｆを信号電圧ＶＳ２２として受け、アクティブフィルタ２ｂ，２ｃの出力電圧Ｖｏｕｔが比較電圧ＶＲとして供給されても良い。さらに、基準周波数生成回路２００は、図１１に示した基準電圧生成回路２３に代えて、図９に示した基準電圧生成回路１３を備えていても良い。 The reference control circuit 24 may include an active filter 2a shown in FIG. 6 instead of the active filter 2 shown in FIG. Further, the reference frequency generation circuit 200 may include the reference control circuit 14 shown in FIG. 9 instead of the reference control circuit 24 shown in FIG. 11, or the active filter 2b shown in FIGS. , 2c may be provided as a reference control circuit. In this case, the active filters 2b and 2c receive the oscillation signals OSCa and OSCb as the signal voltages VS21 and VS23, respectively, receive the reference voltage Vref as the signal voltage VS22, and supply the output voltage Vout of the active filters 2b and 2c as the comparison voltage VR. May be. Furthermore, the reference frequency generation circuit 200 may include the reference voltage generation circuit 13 shown in FIG. 9 instead of the reference voltage generation circuit 23 shown in FIG.
　（基準周波数生成回路の変形例２）
　図１２は、基準周波数生成回路の変形例２を示す。基準周波数生成回路３００は、発振回路３１と、発振制御回路３２と、基準電圧生成回路１３と、レファレンス制御回路（アクティブフィルタ２）とを備える。基準クロックＣＫは、発振回路３１の時定数に対応する周波数を有する。 (Modification 2 of the reference frequency generation circuit)
FIG. 12 shows a second modification of the reference frequency generation circuit. The reference frequency generation circuit 300 includes an oscillation circuit 31, an oscillation control circuit 32, a reference voltage generation circuit 13, and a reference control circuit (active filter 2). The reference clock CK has a frequency corresponding to the time constant of the oscillation circuit 31.
　発振回路３１は、基準クロックＣＫの信号レベルの遷移に応答して、発振信号ＯＳＣａの信号レベルを増減させる。発振回路３１は、容量Ｃａと、定電流源ＣＳ１１１ａと、スイッチＳＷ１ａ，ＳＷ２ａとを含む。発振制御回路３２は、発振信号ＯＳＣａの信号レベルが比較電圧ＶＲよりも高くなったことを検出すると、基準クロックＣＫをローレベルからハイレベルに遷移させ、所定時間の経過後に基準クロックＣＫをハイレベルからローレベルに遷移させる。発振制御回路３２は、比較器ＣＭＰａと、遅延回路３１１とを含む。 The oscillation circuit 31 increases or decreases the signal level of the oscillation signal OSCa in response to the transition of the signal level of the reference clock CK. The oscillation circuit 31 includes a capacitor Ca, a constant current source CS111a, and switches SW1a and SW2a. When the oscillation control circuit 32 detects that the signal level of the oscillation signal OSCa is higher than the comparison voltage VR, the oscillation control circuit 32 changes the reference clock CK from the low level to the high level, and sets the reference clock CK to the high level after a predetermined time has elapsed. Transition from low to low. The oscillation control circuit 32 includes a comparator CMPa and a delay circuit 311.
　レファレンス制御回路（アクティブフィルタ２）は、発振信号ＯＳＣａの振幅に比例する中間信号の信号レベル（ここでは、発振信号ＯＳＣａの累積平均電圧）と基準電圧Ｖｒｅｆとの差が小さくなるように、比較電圧ＶＲを増減させる。ここでは、レファレンス制御部は、アクティブフィルタ２によって構成されており、アクティブフィルタ２は、発振信号ＯＳＣａを信号電圧ＶＳ２１として受けるとともに基準電圧Ｖｒｅｆを信号電圧ＶＳ２２として受け、アクティブフィルタ２の出力電圧Ｖｏｕｔは、比較電圧ＶＲとして供給される。 The reference control circuit (active filter 2) compares the reference voltage Vref so that the difference between the signal level of the intermediate signal proportional to the amplitude of the oscillation signal OSCa (here, the cumulative average voltage of the oscillation signal OSCa) and the reference voltage Vref is small. Increase or decrease VR. Here, the reference control unit is composed of an active filter 2, and the active filter 2 receives the oscillation signal OSCa as the signal voltage VS21 and the reference voltage Vref as the signal voltage VS22. The output voltage Vout of the active filter 2 is , And supplied as a comparison voltage VR.
　なお、基準周波数生成回路３００は、図１２に示したアクティブフィルタ２に代えて、図６に示したアクティブフィルタ２ａを備えていても良い。 The reference frequency generation circuit 300 may include the active filter 2a illustrated in FIG. 6 instead of the active filter 2 illustrated in FIG.
　（その他の実施形態）
　以上の実施形態において、チョッパ増幅器１，アクティブフィルタ２，２ａ，２ｂ，２ｃ，および基準周波数生成回路１００，２００，３００の極性を反転させても良い。例えば、図１に示したチョッパ増幅器１において、負荷トランジスタ１０３１，１０３２，入力トランジスタＴｉｎ１，Ｔｉｎ２，および制御トランジスタＴＣをｎＭＯＳトランジスタによって構成し、カレントミラーＣＭ１，ＣＭ２をｐＭＯＳトランジスタによって構成し、電源ノード（電源電圧ＶＤＤが印加される基準ノード）および接地ノード（接地電圧ＧＮＤが印加されるノード）を互いに入れ替えても良い。 (Other embodiments)
In the above embodiment, the polarities of the chopper amplifier 1, the active filters 2, 2a, 2b, and 2c, and the reference frequency generation circuits 100, 200, and 300 may be reversed. For example, in the chopper amplifier 1 shown in FIG. 1, the load transistors 1031, 1032, the input transistors Tin1, Tin2, and the control transistor TC are configured by nMOS transistors, the current mirrors CM1, CM2 are configured by pMOS transistors, and the power supply node ( The reference node to which the power supply voltage VDD is applied and the ground node (node to which the ground voltage GND is applied) may be interchanged.
　以上説明したように、上述のチョッパ増幅器は、チョッパ機構の応答速度に左右されずに出力電圧に含まれるオフセット電圧を低減できるとともに出力電圧のノイズ増加を抑制できるので、アクティブフィルタに含まれる増幅器などとして有用である。 As described above, the above-described chopper amplifier can reduce the offset voltage included in the output voltage without being affected by the response speed of the chopper mechanism and can suppress an increase in noise in the output voltage. Useful as.
１　　チョッパ増幅器
１０１　　入力切替部
１０２　　電圧電流変換部
１０３１，１０３２　　負荷トランジスタ（相互コンダクタンス素子）
１０４　　接続切替部
１０５　　出力切替部
１０６　　電圧制御部
２，２ａ，２ｂ，２ｃ　　アクティブフィルタ
Ｒ１，Ｒ２　　抵抗
１００，２００，３００　　基準周波数生成回路
１１，２１，３１　　発振回路
１２，３２　　発振制御回路
１３，２３　　基準電圧生成回路
１４，２４　　レファレンス制御回路 DESCRIPTION OF SYMBOLS 1 Chopper amplifier 101 Input switching part 102 Voltage current conversion part 1031 and 1032 Load transistor (transconductance element)
104 connection switching unit 105 output switching unit 106 voltage control unit 2, 2a, 2b, 2c active filter R1, R2 resistor 100, 200, 300 reference frequency generation circuit 11, 21, 31 oscillation circuit 12, 32 oscillation control circuit 13, 23 Reference voltage generation circuit 14, 24 Reference control circuit

Claims (10)

  1. 　第１および第２の動作モードを交互に切り替えながら第１および第２の入力電圧の差分に応じた出力電圧を生成するチョッパ増幅器であって、
    　前記第１の動作モードでは、前記第１の入力電圧を第１の入力ノードに供給するとともに前記第２の入力電圧を第２の入力ノードに供給し、前記第２の動作モードでは、前記第１の入力電圧を前記第２の入力ノードに供給するとともに前記第２の入力電圧を前記第１の入力ノードに供給する入力切替部と、
    　第１の中間ノードと基準ノードとの間の第１の電流経路および第２の中間ノードと前記基準ノードとの間の第２の電流経路に設けられ、前記第１の入力ノードに印加された電圧に応じた電流を前記第１の電流経路に発生させるとともに前記第２の入力ノードに印加された電圧に応じた電流を前記第２の電流経路に発生させる電圧電流変換部と、
    　制御電圧が印加される制御ノードと前記第１の中間ノードとの間の第３の電流経路および前記制御ノードと前記第２の中間ノードとの間の第４の電流経路にそれぞれ設けられ、共通ノードに発生する共通電圧に応じた電流を前記第３および第４の電流経路にそれぞれ発生させる第１および第２の相互コンダクタンス素子と、
    　前記第１の動作モードでは、前記共通ノードを前記第１の中間ノードに接続し、前記第２の動作モードでは、前記共通ノードを前記第２の中間ノードに接続する接続切替部と、
    　前記第１の動作モードでは、前記第１の中間ノードに発生する第１の中間電圧を第３の中間ノードに供給するとともに前記第２の中間ノードに発生する第２の中間電圧を前記出力電圧を出力するための出力ノードに供給し、前記第２の動作モードでは、前記第１の中間電圧を前記出力ノードに供給するとともに前記第２の中間電圧を前記第３の中間ノードに供給する出力切替部と、
    　前記第３の中間ノードに印加された電圧が前記出力ノードに印加された電圧に近づくように前記制御電圧を制御する電圧制御部とを備える
    ことを特徴とするチョッパ増幅器。     A chopper amplifier that generates an output voltage according to a difference between the first and second input voltages while alternately switching between the first and second operation modes,
    In the first operation mode, the first input voltage is supplied to the first input node and the second input voltage is supplied to the second input node. In the second operation mode, the first input voltage is supplied to the first input node. An input switching unit that supplies one input voltage to the second input node and supplies the second input voltage to the first input node;
    Provided in a first current path between a first intermediate node and a reference node and a second current path between a second intermediate node and the reference node and applied to the first input node; A voltage-current converter that generates a current corresponding to a voltage in the first current path and generates a current corresponding to a voltage applied to the second input node in the second current path;
    Provided in a third current path between the control node to which the control voltage is applied and the first intermediate node and a fourth current path between the control node and the second intermediate node, respectively. First and second transconductance elements for generating currents corresponding to a common voltage generated at a node in the third and fourth current paths, respectively;
    A connection switching unit that connects the common node to the first intermediate node in the first operation mode, and connects the common node to the second intermediate node in the second operation mode;
    In the first operation mode, the first intermediate voltage generated at the first intermediate node is supplied to the third intermediate node, and the second intermediate voltage generated at the second intermediate node is supplied to the output voltage. To the output node for outputting the output, and in the second operation mode, the first intermediate voltage is supplied to the output node and the second intermediate voltage is supplied to the third intermediate node. A switching unit;
    And a voltage control unit that controls the control voltage so that a voltage applied to the third intermediate node approaches a voltage applied to the output node.
  2. 　請求項１に記載のチョッパ増幅器を備える
    ことを特徴とするアクティブフィルタ。     An active filter comprising the chopper amplifier according to claim 1.
  3. 　請求項２において、
    　第１の抵抗と、
    　第１の容量とをさらに備え、
    　前記第１の抵抗の一端には、第１の信号電圧が印加され、
    　前記第１の抵抗の他端は、中間ノードに接続され、
    　前記第１の容量の一端は、前記中間ノードに接続され、
    　前記第１の容量の他端は、前記チョッパ増幅器の出力ノードに接続され、
    　前記チョッパ増幅器は、前記中間ノードに発生する中間電圧を前記第１および第２の入力電圧の一方として受け、第２の信号電圧を前記第１および第２の入力電圧の他方として受ける
    ことを特徴とするアクティブフィルタ。     In claim 2,
    A first resistor;
    A first capacity;
    A first signal voltage is applied to one end of the first resistor,
    The other end of the first resistor is connected to an intermediate node;
    One end of the first capacitor is connected to the intermediate node;
    The other end of the first capacitor is connected to an output node of the chopper amplifier,
    The chopper amplifier receives an intermediate voltage generated at the intermediate node as one of the first and second input voltages, and receives a second signal voltage as the other of the first and second input voltages. The active filter.
  4. 　請求項２において、
    　第１の抵抗と、
    　第１の容量と、
    　第２の容量とをさらに備え、
    　前記第１の抵抗の一端には、第１の信号電圧が印加され、
    　前記第１の抵抗の他端は、中間ノードに接続され、
    　前記第１の容量の一端は、前記中間ノードに接続され、
    　前記第１の容量の他端は、前記基準ノードに接続され、
    　前記第２の容量の一端は、前記チョッパ増幅器の出力ノードに接続され、
    　前記第２の容量の他端は、前記基準ノードに接続され、
    　前記第１の容量の他端は、前記チョッパ増幅器の出力ノードに接続され、
    　前記チョッパ増幅器は、前記中間ノードに発生する中間電圧を前記第１および第２の入力電圧の一方として受け、第２の信号電圧を前記第１および第２の入力電圧の他方として受ける
    ことを特徴とするアクティブフィルタ。     In claim 2,
    A first resistor;
    A first capacity;
    A second capacity,
    A first signal voltage is applied to one end of the first resistor,
    The other end of the first resistor is connected to an intermediate node;
    One end of the first capacitor is connected to the intermediate node;
    The other end of the first capacitor is connected to the reference node,
    One end of the second capacitor is connected to the output node of the chopper amplifier,
    The other end of the second capacitor is connected to the reference node,
    The other end of the first capacitor is connected to an output node of the chopper amplifier,
    The chopper amplifier receives an intermediate voltage generated at the intermediate node as one of the first and second input voltages, and receives a second signal voltage as the other of the first and second input voltages. The active filter.
  5. 　請求項３または４において、
    　第２の抵抗をさらに備え、
    　前記第２の抵抗の一端には、第３の信号電圧が印加され、
    　前記第２の抵抗の他端は、前記中間ノードに接続される
    ことを特徴とするアクティブフィルタ。     In claim 3 or 4,
    A second resistor;
    A third signal voltage is applied to one end of the second resistor,
    The other end of the second resistor is connected to the intermediate node.
  6. 　基準クロックを生成する回路であって、
    　前記基準クロックの信号レベルの遷移に応答して、第１の発振信号の信号レベルを増加させるとともに第２の発振信号の信号レベルを減少させる動作と、前記第２の発振信号の信号レベルを増加させるとともに前記第１の発振信号の信号レベルを減少させる動作とを交互に行う発振回路と、
    　前記第１の発振信号の信号レベルが比較電圧に到達したことを検出すると前記基準クロックの信号レベルを第１の論理レベルに遷移させ、前記第２の発振信号の信号レベルが前記比較電圧に到達したことを検出すると前記基準クロックの信号レベルを第２の論理レベルに遷移させる発振制御回路と、
    　前記第１および第２の発振信号のそれぞれの振幅に比例する中間信号の信号レベルと基準電圧との差が小さくなるように、前記比較電圧を増減させるレファレンス制御回路とを備え、
    　前記レファレンス制御回路は、請求項２に記載のアクティブフィルタを含む
    ことを特徴とする基準周波数生成回路。     A circuit for generating a reference clock,
    In response to the transition of the signal level of the reference clock, an operation of increasing the signal level of the first oscillation signal and decreasing the signal level of the second oscillation signal, and increasing the signal level of the second oscillation signal And an oscillation circuit that alternately performs an operation for reducing the signal level of the first oscillation signal; and
    When it is detected that the signal level of the first oscillation signal has reached the comparison voltage, the signal level of the reference clock is shifted to the first logic level, and the signal level of the second oscillation signal reaches the comparison voltage. An oscillation control circuit that transitions the signal level of the reference clock to a second logic level when detecting that
    A reference control circuit that increases or decreases the comparison voltage so that a difference between a signal level of an intermediate signal proportional to the amplitude of each of the first and second oscillation signals and a reference voltage is small;
    The reference frequency generation circuit according to claim 2, wherein the reference control circuit includes the active filter according to claim 2.
  7. 　基準クロックを生成する回路であって、
    　前記基準クロックの信号レベルの遷移に応答して、第１の発振信号の信号レベルを増加させるとともに第２の発振信号の信号レベルを減少させる動作と、前記第２の発振信号の信号レベルを増加させるとともに前記第１の発振信号の信号レベルを減少させる動作とを交互に行う発振回路と、
    　前記第１の発振信号の信号レベルが比較電圧に到達したことを検出すると前記基準クロックの信号レベルを第１の論理レベルに遷移させ、前記第２の発振信号の信号レベルが前記比較電圧に到達したことを検出すると前記基準クロックの信号レベルを第２の論理レベルに遷移させる発振制御回路と、
    　前記第１および第２の発振信号のそれぞれの振幅に比例する中間信号の信号レベルと基準電圧との差が小さくなるように、前記比較電圧を増減させるレファレンス制御回路とを備え、
    　前記レファレンス制御回路は、
    　　前記第１および第２の発振信号をそれぞれ通過させる第１および第２の入力抵抗と、
    　　請求項３または４に記載のアクティブフィルタとを含み、
    　前記アクティブフィルタは、前記第１および第２の入力抵抗をそれぞれ通過した第１および第２の発振信号を合成して得られる合成信号を前記第１の信号電圧として受けるとともに前記基準電圧を前記第２の信号電圧として受け、
    　前記アクティブフィルタの出力電圧は、前記比較電圧として供給される
    ことを特徴とする基準周波数生成回路。     A circuit for generating a reference clock,
    In response to the transition of the signal level of the reference clock, an operation of increasing the signal level of the first oscillation signal and decreasing the signal level of the second oscillation signal, and increasing the signal level of the second oscillation signal And an oscillation circuit that alternately performs an operation for reducing the signal level of the first oscillation signal; and
    When it is detected that the signal level of the first oscillation signal has reached the comparison voltage, the signal level of the reference clock is shifted to the first logic level, and the signal level of the second oscillation signal reaches the comparison voltage. An oscillation control circuit that transitions the signal level of the reference clock to a second logic level when detecting that
    A reference control circuit that increases or decreases the comparison voltage so that a difference between a signal level of an intermediate signal proportional to the amplitude of each of the first and second oscillation signals and a reference voltage is small;
    The reference control circuit includes:
    First and second input resistors for passing the first and second oscillation signals, respectively;
    An active filter according to claim 3 or 4,
    The active filter receives, as the first signal voltage, a combined signal obtained by combining the first and second oscillation signals that have passed through the first and second input resistors, respectively, and receives the reference voltage as the first voltage. 2 as a signal voltage,
    A reference frequency generation circuit, wherein an output voltage of the active filter is supplied as the comparison voltage.
  8. 　基準クロックを生成する回路であって、
    　前記基準クロックの信号レベルの遷移に応答して、第１の発振信号の信号レベルを増加させるとともに第２の発振信号の信号レベルを減少させる動作と、前記第２の発振信号の信号レベルを増加させるとともに前記第１の発振信号の信号レベルを減少させる動作とを交互に行う発振回路と、
    　前記第１の発振信号の信号レベルが比較電圧に到達したことを検出すると前記基準クロックの信号レベルを第１の論理レベルに遷移させ、前記第２の発振信号の信号レベルが前記比較電圧に到達したことを検出すると前記基準クロックの信号レベルを第２の論理レベルに遷移させる発振制御回路と、
    　前記第１および第２の発振信号のそれぞれの振幅に比例する中間信号の信号レベルと基準電圧との差が小さくなるように、前記比較電圧を増減させるレファレンス制御回路とを備え、
    　前記レファレンス制御回路は、請求項５に記載のアクティブフィルタによって構成され、
    　前記アクティブフィルタは、前記第１および第２の発振信号を前記第１および第３の信号電圧としてそれぞれ受けるとともに前記基準電圧を前記第２の信号電圧として受け、
    　前記アクティブフィルタの出力電圧は、前記比較電圧として供給される
    ことを特徴とする基準周波数生成回路。     A circuit for generating a reference clock,
    In response to the transition of the signal level of the reference clock, an operation of increasing the signal level of the first oscillation signal and decreasing the signal level of the second oscillation signal, and increasing the signal level of the second oscillation signal And an oscillation circuit that alternately performs an operation for reducing the signal level of the first oscillation signal; and
    When it is detected that the signal level of the first oscillation signal has reached the comparison voltage, the signal level of the reference clock is shifted to the first logic level, and the signal level of the second oscillation signal reaches the comparison voltage. An oscillation control circuit that transitions the signal level of the reference clock to a second logic level when detecting that
    A reference control circuit that increases or decreases the comparison voltage so that a difference between a signal level of an intermediate signal proportional to the amplitude of each of the first and second oscillation signals and a reference voltage is small;
    The reference control circuit includes an active filter according to claim 5,
    The active filter receives the first and second oscillation signals as the first and third signal voltages, respectively, and receives the reference voltage as the second signal voltage,
    A reference frequency generation circuit, wherein an output voltage of the active filter is supplied as the comparison voltage.
  9. 　基準クロックを生成する回路であって、
    　前記基準クロックの信号レベルの遷移に応答して、第１の発振信号の信号レベルを増加させるとともに第２の発振信号の信号レベルを減少させる動作と、前記第２の発振信号の信号レベルを増加させるとともに前記第１の発振信号の信号レベルを減少させる動作とを交互に行う発振回路と、
    　前記第１の発振信号の信号レベルが比較電圧に到達したことを検出すると前記基準クロックの信号レベルを第１の論理レベルに遷移させ、前記第２の発振信号の信号レベルが前記比較電圧に到達したことを検出すると前記基準クロックの信号レベルを第２の論理レベルに遷移させる発振制御回路と、
    　前記第１および第２の発振信号のそれぞれの振幅に比例する中間信号の信号レベルと基準電圧との差が小さくなるように、前記比較電圧を増減させるレファレンス制御回路とを備え、
    　前記レファレンス制御回路は、
    　　前記基準クロックの信号レベルの遷移に応答して前記第１および第２の発振信号を交互に通過させるスイッチ回路と、
    　　請求項３または４に記載のアクティブフィルタとを含み、
    　前記アクティブフィルタは、前記スイッチ回路を通過した発振信号を前記第１の信号電圧として受けるとともに前記基準電圧を前記第２の信号電圧として受け、
    　前記アクティブフィルタの出力電圧は、前記比較電圧として供給される
    ことを特徴とする基準周波数生成回路。     A circuit for generating a reference clock,
    In response to the transition of the signal level of the reference clock, an operation of increasing the signal level of the first oscillation signal and decreasing the signal level of the second oscillation signal, and increasing the signal level of the second oscillation signal And an oscillation circuit that alternately performs an operation for reducing the signal level of the first oscillation signal; and
    When it is detected that the signal level of the first oscillation signal has reached the comparison voltage, the signal level of the reference clock is shifted to the first logic level, and the signal level of the second oscillation signal reaches the comparison voltage. An oscillation control circuit that transitions the signal level of the reference clock to a second logic level when detecting that
    A reference control circuit that increases or decreases the comparison voltage so that a difference between a signal level of an intermediate signal proportional to the amplitude of each of the first and second oscillation signals and a reference voltage is small;
    The reference control circuit includes:
    A switch circuit for alternately passing the first and second oscillation signals in response to the transition of the signal level of the reference clock;
    An active filter according to claim 3 or 4,
    The active filter receives the oscillation signal that has passed through the switch circuit as the first signal voltage and the reference voltage as the second signal voltage,
    A reference frequency generation circuit, wherein an output voltage of the active filter is supplied as the comparison voltage.
  10. 　基準クロックを生成する回路であって、
    　前記基準クロックの信号レベルの遷移に応答して、発振信号の信号レベルを増加させる動作と、前記発振信号の信号レベルを減少させる動作とを交互に行う発振回路と、
    　前記発振信号の信号レベルが比較電圧に到達したことを検出すると前記基準クロックの信号レベルを第１の論理レベルに遷移させ、所定時間の経過後に前記基準クロックの信号レベルを第２の論理レベルに遷移させる発振制御回路と、
    　前記発振信号の振幅に比例する中間信号の信号レベルと基準電圧との差が小さくなるように、前記比較電圧を増減させるレファレンス制御回路とを備え、
    　前記レファレンス制御回路は、請求項３または４に記載のアクティブフィルタによって構成され、
    　前記アクティブフィルタは、前記発振信号を前記第１の信号電圧として受けるとともに前記基準電圧を前記第２の信号電圧として受け、
    　前記アクティブフィルタの出力電圧は、前記比較電圧として供給される
    ことを特徴とする基準周波数生成回路。     A circuit for generating a reference clock,
    An oscillation circuit that alternately performs an operation of increasing the signal level of the oscillation signal and an operation of decreasing the signal level of the oscillation signal in response to the transition of the signal level of the reference clock;
    When it is detected that the signal level of the oscillation signal has reached the comparison voltage, the signal level of the reference clock is shifted to the first logic level, and the signal level of the reference clock is changed to the second logic level after a predetermined time has elapsed. An oscillation control circuit for transition;
    A reference control circuit for increasing or decreasing the comparison voltage so that the difference between the signal level of the intermediate signal proportional to the amplitude of the oscillation signal and the reference voltage is small;
    The reference control circuit includes an active filter according to claim 3 or 4,
    The active filter receives the oscillation signal as the first signal voltage and the reference voltage as the second signal voltage,
    A reference frequency generation circuit, wherein an output voltage of the active filter is supplied as the comparison voltage.
PCT/JP2011/003475 2010-10-19 2011-06-17 Chopper amplifier, active filter, and reference frequency generating circuit WO2012053133A1 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2015037532A1 (en) * 2013-09-13 2017-03-02 アルプス電気株式会社 Amplifier circuit
US11323083B2 (en) 2018-04-27 2022-05-03 Panasonic Intellectual Property Management Co., Ltd. Amplifier circuit
WO2022254995A1 (en) * 2021-05-31 2022-12-08 ローム株式会社 Amplification circuit, switching power supply circuit, and switching power supply device

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JP2003218698A (en) * 2002-01-25 2003-07-31 Sony Corp Parallel type ad converter
JP2007074670A (en) * 2005-09-09 2007-03-22 Nec Electronics Corp Differential amplifier circuit and semiconductor device
JP2008067050A (en) * 2006-09-07 2008-03-21 Handotai Rikougaku Kenkyu Center:Kk Feedback amplifier circuit
WO2009035665A1 (en) * 2007-09-14 2009-03-19 Analog Devices, Inc. Improved low power, low noise amplifier system

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JP2002530916A (en) * 1998-11-12 2002-09-17 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ Circuit having means for reducing DC offset and noise generated by an amplifier
JP2003218698A (en) * 2002-01-25 2003-07-31 Sony Corp Parallel type ad converter
JP2007074670A (en) * 2005-09-09 2007-03-22 Nec Electronics Corp Differential amplifier circuit and semiconductor device
JP2008067050A (en) * 2006-09-07 2008-03-21 Handotai Rikougaku Kenkyu Center:Kk Feedback amplifier circuit
WO2009035665A1 (en) * 2007-09-14 2009-03-19 Analog Devices, Inc. Improved low power, low noise amplifier system

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* Cited by examiner, † Cited by third party
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JPWO2015037532A1 (en) * 2013-09-13 2017-03-02 アルプス電気株式会社 Amplifier circuit
US11323083B2 (en) 2018-04-27 2022-05-03 Panasonic Intellectual Property Management Co., Ltd. Amplifier circuit
WO2022254995A1 (en) * 2021-05-31 2022-12-08 ローム株式会社 Amplification circuit, switching power supply circuit, and switching power supply device

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