WO2012023401A1 - Semiconductor switch circuit - Google Patents

Semiconductor switch circuit Download PDF

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Publication number
WO2012023401A1
WO2012023401A1 PCT/JP2011/067244 JP2011067244W WO2012023401A1 WO 2012023401 A1 WO2012023401 A1 WO 2012023401A1 JP 2011067244 W JP2011067244 W JP 2011067244W WO 2012023401 A1 WO2012023401 A1 WO 2012023401A1
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Prior art keywords
terminal
transistors
transistor
terminals
common
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PCT/JP2011/067244
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French (fr)
Japanese (ja)
Inventor
敦義 日村
修功 奥田
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株式会社村田製作所
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Publication of WO2012023401A1 publication Critical patent/WO2012023401A1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/693—Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/16—Modifications for eliminating interference voltages or currents
    • H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
    • H03K17/162—Modifications for eliminating interference voltages or currents in field-effect transistor switches without feedback from the output circuit to the control circuit

Definitions

  • the present invention relates to a semiconductor switch circuit, and more particularly to a semiconductor switch circuit using a plurality of transistors.
  • Patent Document 1 discloses a conventional semiconductor switch circuit that has few components and switches a signal flow between two terminals and two or more common terminals.
  • FIG. 4 is a circuit diagram showing a configuration example of a conventional semiconductor switch circuit.
  • the semiconductor switch circuit 100 shown in FIG. 4 includes two common terminals A101 and A102, two terminals P101 and P102, two control terminals V101 and V102, and the common terminals A101 and A102 and the terminals P101 and P102.
  • the transistors F105 and F106 are shunt FETs.
  • the transistor F101 has a drain electrode connected to the terminal P101, a source electrode connected to the common terminal A101, and a gate electrode connected to the inverter circuit L102 via the resistor R.
  • the inverter circuit L102 is connected to the control terminal V102.
  • the transistor F102 has a drain electrode connected to the terminal P101, a source electrode connected to the common terminal A102, and a gate electrode connected to the control terminal V102 via the resistor R.
  • the transistor F103 has a drain electrode connected to the terminal P102, a source electrode connected to the common terminal A101, and a gate electrode connected to the control terminal V102 via the resistor R.
  • the transistor F104 has a drain electrode connected to the terminal P102, a source electrode connected to the common terminal A102, and a gate electrode connected to the inverter circuit L102 via the resistor R.
  • the transistor F105 has a drain electrode connected to the terminal P101, a source electrode connected to the ground terminal via the capacitor C and the inductor L, and a gate electrode connected to the inverter circuit L101 via the resistor R.
  • the inverter circuit L101 is connected to the control terminal V101.
  • the transistor F106 has a drain electrode connected to the terminal P102, a source electrode connected to the ground terminal via the capacitor C and the inductor L, and a gate electrode connected to the control terminal V101 via the resistor R.
  • Table 1 shows the relationship between the supply of the control voltage and the circuit operation.
  • the semiconductor switch circuit 100 supplies a control voltage having a high level (H) or low level (L) potential to the control terminals V101 and V102, so that the common terminals A101 and A102, P101 and P102 can be controlled to be conductive.
  • the transistor F101 is turned on (the transistor F101 is turned on).
  • the transistor F102, F103 and the transistor (shunt FET) F105 are in the OFF state (the drain-source of the transistor F105 has a high resistance and a desired amount of current flows). Therefore, the common terminal A101 is electrically connected to the terminal P101.
  • the transistor F104 is turned on, but the transistor (shunt FET) F106 is turned on, so that an unnecessary high-frequency signal can be fed to the ground terminal without flowing to the terminal P102.
  • the transistor F102 When a high-level control voltage is supplied to the control terminal V101 and the control terminal V102, the transistor F102 is turned on and the transistors F101, F104, and F105 are turned off, so that the common terminal A102 and the terminal P101 are turned on. And conduct. At this time, the transistor F103 is turned on, but since the transistor F106 is turned on, an unnecessary high-frequency signal can be fed to the ground terminal without flowing to the terminal P102.
  • the semiconductor switch circuit 100 since one of the transistor F105 and the transistor F106 is controlled to be turned on, an unnecessary high-frequency signal is allowed to flow to the ground terminal without flowing to one of the terminal P101 and the terminal P102. In addition, the isolation characteristic between the terminals P101 and P102 can be improved.
  • a depletion type field effect transistor in which a drain current flows even when the gate voltage is a negative voltage (0 V or less) is used for the transistors F101 to F104 and the transistors F105 and F106.
  • a depletion type field effect transistor cannot be used for the inverter circuits L101 and L102. That is, when a control voltage having a high level or low level potential is supplied to the control terminals V101 and V102, the gates of the transistors constituting the inverter circuits L101 and L102 are connected to the gates in order to operate the inverter circuits L101 and L102 normally. It is necessary to use an enhancement type field effect transistor in which the drain current does not flow unless the voltage is a positive voltage (greater than 0 V).
  • An object of the present invention is to provide a semiconductor switch circuit that can be used.
  • a semiconductor switch circuit includes first to m-th (m is a natural number of 2 or more) common terminals and first to n-th (n is a natural number of 2 or more) terminals. Are connected between the first to m-th common terminals and the first to n-th terminals, and can be controlled so that one common terminal and one terminal are conductive. and n ⁇ (n ⁇ 1) second transistors connected in parallel to at least one terminal, wherein the first transistor and the second transistor are the same depletion type or the same enhancement. When a common terminal and one terminal are conductive, at least one second transistor is turned on among the second transistors connected in parallel to the other terminal. Control It is characterized by that.
  • the m ⁇ n first transistors and the m ⁇ (n ⁇ 1) second transistors are the same depletion type or the same enhancement type field effect transistor, and one common terminal,
  • the isolation characteristics between the terminals are improved by controlling so that at least one second transistor of the second transistors connected in parallel to the other terminals is turned on.
  • it is composed of only the field effect transistor of the same type without using a logic circuit composed of a field effect transistor of a different type (enhancement type or depletion type) from the first transistor (depletion type or enhancement type). Therefore, the manufacturing cost can be reduced.
  • no logic circuit since no logic circuit is used, resistance against ESD (electrostatic discharge) is improved, and the area occupied by the logic circuit is not required, and the semiconductor switch circuit can be downsized.
  • the second transistor is connected to a ground terminal via a resonance circuit.
  • the second transistor since the second transistor is connected to the ground terminal via the resonance circuit, it is possible to resonate a signal having a desired frequency and flow the signal to the ground terminal to attenuate the signal having the desired frequency.
  • the semiconductor switch circuit according to a third aspect of the present invention further comprises n ⁇ (m ⁇ 1) third transistors connected in parallel to at least one common terminal in the first or second aspect, wherein the third transistor Is a field effect transistor of the same type as the first transistor and the second transistor, and when one common terminal and one terminal are conductive, among the third transistors connected in parallel to the other common terminal, Control is performed so that at least one third transistor is turned on.
  • the third transistor is a field effect transistor of the same type as the first transistor and the second transistor, and is connected in parallel to another common terminal when one common terminal and one terminal are conductive.
  • the isolation characteristics between the terminals and between the common terminals can be improved, and further, the first transistor and the second transistor can be improved.
  • the semiconductor switch circuit according to a fourth aspect of the present invention is the semiconductor switch circuit according to the third aspect, wherein the third transistor is connected to a ground terminal via a resonance circuit.
  • the third transistor is connected to the ground terminal via the resonance circuit, it is possible to resonate a signal having a desired frequency and flow it to the ground terminal to attenuate the signal having the desired frequency.
  • a semiconductor switch circuit includes first to m-th (m is a natural number of 2 or more) common terminals and first to n-th (n is a natural number of 2 or more) terminals. Are connected between the first to m-th common terminals and the first to n-th terminals, and can be controlled so that one common terminal and one terminal are conductive.
  • the m ⁇ n first transistors and the n ⁇ (m ⁇ 1) second transistors are the same depletion type or the same enhancement type field effect transistor, and have one common terminal and one terminal. Is connected, the second transistor connected in parallel to another common terminal is controlled so that at least one second transistor is turned on, thereby improving the isolation characteristics between the common terminals.
  • the first transistor (depletion type or enhancement type) and a different type (enhancement type or depletion type) field effect transistor can be used without using a logic circuit. Therefore, the manufacturing cost can be reduced.
  • resistance against ESD electrostatic discharge
  • the area occupied by the logic circuit is not required, and the semiconductor switch circuit can be downsized.
  • the second transistor is connected to a ground terminal via a resonance circuit.
  • the second transistor since the second transistor is connected to the ground terminal via the resonance circuit, it is possible to resonate a signal having a desired frequency and flow the signal to the ground terminal to attenuate the signal having the desired frequency.
  • the semiconductor switch circuit according to a seventh aspect of the present invention is the semiconductor switch circuit according to any one of the first to sixth aspects, wherein the first to third transistors are depletion type field effect transistors.
  • the first to third transistors are depletion type field effect transistors, and the depletion type field effect transistor and the enhancement type field effect transistor are formed by configuring the semiconductor switch circuit only with the depletion type field effect transistor.
  • the pinch-off voltage does not vary uncorrelated as in the case of using a transistor, and the yield can be increased.
  • the m ⁇ n first transistors and the m ⁇ (n ⁇ 1) second transistors are field effect transistors of the same depletion type or the same enhancement type, and one common terminal and one terminal Can be improved by turning on at least one second transistor of the second transistors connected in parallel to the other terminals, so that the isolation characteristics between the terminals can be improved.
  • the logic circuit is composed of only the same type of field effect transistor. The manufacturing cost can be reduced.
  • no logic circuit since no logic circuit is used, resistance against ESD (electrostatic discharge) is improved, and the area occupied by the logic circuit is not required, and the semiconductor switch circuit can be downsized.
  • the m ⁇ n first transistors and the n ⁇ (m ⁇ 1) second transistors are the same depletion type or the same enhancement type field effect transistor,
  • the isolating circuit between the common terminals is controlled by controlling so that at least one of the second transistors connected in parallel to the other common terminal is turned on.
  • the field effect of the same type without using a logic circuit composed of a field effect transistor of a different type (enhancement type or depletion type) from the first transistor (depletion type or enhancement type). Since only the transistor is used, the manufacturing cost can be reduced.
  • ESD electrostatic discharge
  • FIG. 1 is a circuit diagram illustrating a configuration example of a semiconductor switch circuit according to a first embodiment of the present invention. It is a circuit diagram which shows the structural example of the semiconductor switch circuit which concerns on Embodiment 2 of this invention. It is a circuit diagram which shows the structural example of the semiconductor switch circuit which concerns on Embodiment 3 of this invention. It is a circuit diagram which shows the structural example of the conventional semiconductor switch circuit.
  • FIG. 1 is a circuit diagram showing a configuration example of the semiconductor switch circuit according to the first embodiment of the present invention.
  • 1 includes two common terminals A1 and A2, two terminals P1 and P2, four control terminals V1, V2, V3, and V4, common terminals A1 and A2, and terminals P1 and P2.
  • the semiconductor switch circuit 1 is not limited to the configuration of a DPDT type semiconductor switch circuit having two common terminals and two terminals.
  • the number of common terminals is m (m is a natural number of 2 or more) and the number of terminals is n. It may be a configuration of mPnT type semiconductor switch circuits (n is a natural number of 2 or more).
  • the semiconductor switch circuit 1 configured with m common terminals and n terminals, the number of transistors connected between the common terminals A1 to Am and the terminals P1 to Pn is mxn and each of the n terminals P1.
  • the number of transistors connected in parallel to .about.Pn is m.times. (N-1).
  • the transistor F11 has a drain electrode connected to the terminal P1, a source electrode connected to the common terminal A1, and a gate electrode connected to the control terminal V1 via a resistor R.
  • the transistor F12 has a drain electrode connected to the terminal P1, a source electrode connected to the common terminal A2, and a gate electrode connected to the control terminal V2 via the resistor R.
  • the transistor F13 has a drain electrode connected to the terminal P2, a source electrode connected to the common terminal A1, and a gate electrode connected to the control terminal V3 via the resistor R.
  • the transistor F14 has a drain electrode connected to the terminal P2, a source electrode connected to the common terminal A2, and a gate electrode connected to the control terminal V4 via the resistor R.
  • the transistor (shunt FET) F21 has a drain electrode connected to the terminal P1, a source electrode connected to the ground terminal via the capacitor C and the inductor L, and a gate electrode connected to the control terminal V3 via the resistor R.
  • the transistor (shunt FET) F22 has a drain electrode connected to the terminal P1, a source electrode connected to the ground terminal via the capacitor C and the inductor L, and a gate electrode connected to the control terminal V4 via the resistor R.
  • the transistor (shunt FET) F23 has a drain electrode connected to the terminal P2, a source electrode connected to the ground terminal via the capacitor C and the inductor L, and a gate electrode connected to the control terminal V1 via the resistor R.
  • the transistor (shunt FET) F24 has a drain electrode connected to the terminal P2, a source electrode connected to the ground terminal via the capacitor C and the inductor L, and a gate electrode connected to the control terminal V2 via the resistor R. Since the transistors F21 to F24 are connected to the ground terminal via a resonance circuit including a capacitor C and an inductor L connected in series, a signal having a desired frequency is resonated and passed to the ground terminal. A signal having a desired frequency can be attenuated.
  • the transistors F21 to F24 connected in parallel to the terminals P1 and P2 are field effect transistors of the same type as the transistors F11 to F14 connected between the common terminals A1 and A2 and the terminals P1 and P2.
  • the transistors F11 to F14 and the transistors F21 to F24 are depletion type field effect transistors, and the depletion type field effect transistor is configured by configuring the semiconductor switch circuit 1 only with the depletion type field effect transistor.
  • the enhancement type field effect transistor the pinch-off voltage does not vary uncorrelated and the yield can be increased.
  • transistors F11 to F14 and the transistors F21 to F24 are not limited to depletion type or enhancement type field effect transistors, and other types of field effect transistors may be used as long as they are field effect transistors capable of performing the same operation. There may be.
  • the semiconductor switch circuit 1 supplies a control voltage having a high level (H) or low level (L) potential to the control terminals V1 to V4, so that the common terminals A1 and A2 and the terminals It can be controlled so that P1 and P2 are conducted.
  • H high level
  • L low level
  • the semiconductor switch circuit 1 when one common terminal (for example, A1) and one terminal (for example, P1) are conducted, of the two transistors F23 and F24 connected in parallel to the other terminal (for example, P2), Control is performed so that at least one transistor (for example, F23) is turned on. Therefore, the transistor F23 can flow an unnecessary high-frequency signal to the ground terminal without flowing to the terminal P2. In particular, since a high frequency signal flowing between the common terminal A1 and the terminal P1 can be prevented from flowing into the terminal P2, the isolation characteristic between the terminals P1 and P2 can be improved.
  • the transistors F21 to F24 are field effect transistors of the same type as the transistors F11 to F14, and one common terminal A1 (A2) When one terminal P1 (P2) conducts, at least one of the two transistors F23 and F24 (F21, F22) connected in parallel to the other terminal P2 (P1) is turned on.
  • the isolation characteristic between the terminals P1 and P2 can be improved, and a logic circuit composed of a field effect transistor of a different type (enhancement type or depletion type) from the transistors F11 to F14 is used. And is made up of only the same type of field effect transistors. It can be reduced.
  • the semiconductor switch circuit 1 according to Embodiment 1 of the present invention includes a plurality of common terminals with respect to a plurality of terminals, it can be incorporated into a device that requires a plurality of common terminals.
  • the resistors R connected to the gate electrodes of the transistors F11 to F14 and the transistors F21 to F24 may all have the same resistance value or different resistance values.
  • the resistance value of the resistor R may be a value that allows the semiconductor switch circuit 1 to perform a desired operation.
  • the capacitance value of the capacitor C connected to the source electrode of each of the transistors F21 to F24 and the inductance of the inductor L may be the same value or different values.
  • the capacitance value of the capacitor C and the inductance of the inductor L may be values that allow the semiconductor switch circuit 1 to perform a desired operation.
  • two transistors F21 and F22 and transistors F23 and F24 are connected in parallel to the terminals P1 and P2, respectively. If it is not necessary to improve the isolation characteristics in both directions, a configuration in which two transistors F21 and F22 or transistors F23 and F24 are connected in parallel only to either the terminal P1 or the terminal P2 may be employed.
  • FIG. 2 is a circuit diagram showing a configuration example of the semiconductor switch circuit according to the second embodiment of the present invention.
  • the semiconductor switch circuit 2 according to the second embodiment of the present invention includes transistors (second transistors) F21 to F24 connected in parallel to the common terminals A1 and A2.
  • the semiconductor switch circuit 2 shown in FIG. 2 includes two common terminals A1, A2, two terminals P1, P2, four control terminals V1, V2, V3, V4, common terminals A1, A2, and terminals P1, P2.
  • the semiconductor switch circuit 2 is not limited to the configuration of the DPDT type semiconductor switch circuit having two common terminals and two terminals.
  • the number of common terminals is m (m is a natural number of 2 or more), and the number of terminals is n. It may be a configuration of mPnT type semiconductor switch circuits (n is a natural number of 2 or more).
  • the semiconductor switch circuit 2 configured with m common terminals and n terminals, the number of transistors connected between the common terminals A1 to Am and the terminals P1 to Pn is mxn common terminals.
  • the number of transistors connected in parallel to A1 to Am is n ⁇ (m ⁇ 1).
  • the transistor F11 has a drain electrode connected to the terminal P1, a source electrode connected to the common terminal A1, and a gate electrode connected to the control terminal V1 via a resistor R.
  • the transistor F12 has a drain electrode connected to the terminal P1, a source electrode connected to the common terminal A2, and a gate electrode connected to the control terminal V2 via the resistor R.
  • the transistor F13 has a drain electrode connected to the terminal P2, a source electrode connected to the common terminal A1, and a gate electrode connected to the control terminal V3 via the resistor R.
  • the transistor F14 has a drain electrode connected to the terminal P2, a source electrode connected to the common terminal A2, and a gate electrode connected to the control terminal V4 via the resistor R.
  • the transistor (shunt FET) F21 has a drain electrode connected to the common terminal A1, a source electrode connected to the ground terminal via the capacitor C and the inductor L, and a gate electrode connected to the control terminal V4 via the resistor R.
  • the transistor (shunt FET) F22 has a drain electrode connected to the common terminal A1, a source electrode connected to the ground terminal via the capacitor C and the inductor L, and a gate electrode connected to the control terminal V2 via the resistor R.
  • the transistor (shunt FET) F23 has a drain electrode connected to the common terminal A2, a source electrode connected to the ground terminal via the capacitor C and the inductor L, and a gate electrode connected to the control terminal V1 via the resistor R. .
  • the transistor (shunt FET) F24 has a drain electrode connected to the common terminal A2, a source electrode connected to the ground terminal via the capacitor C and the inductor L, and a gate electrode connected to the control terminal V3 via the resistor R. . Since the transistors F21 to F24 are connected to the ground terminal via a resonance circuit including a capacitor C and an inductor L connected in series, a signal having a desired frequency is resonated and passed to the ground terminal. A signal having a desired frequency can be attenuated.
  • field effect transistors of the same type as the transistors F11 to F14 connected between the common terminals A1 and A2 and the terminals P1 and P2 are used.
  • the transistors F11 to F14 and the transistors F21 to F24 are depletion type field effect transistors, and the depletion type field effect transistors are formed by configuring the semiconductor switch circuit 2 only with the depletion type field effect transistors.
  • the enhancement type field effect transistor the pinch-off voltage does not vary uncorrelated and the yield can be increased.
  • transistors F11 to F14 and the transistors F21 to F24 are not limited to depletion type or enhancement type field effect transistors, and other types of field effect transistors may be used as long as they are field effect transistors capable of performing the same operation. There may be.
  • the semiconductor switch circuit 2 supplies a control voltage having a high level (H) or low level (L) potential to the control terminals V1 to V4, thereby causing the common terminals A1, A2 and The terminals P1 and P2 can be controlled to conduct.
  • H high level
  • L low level
  • the semiconductor switch circuit 2 when one common terminal (for example, A1) and one terminal (for example, P1) are conducted, of the two transistors F23 and F24 connected in parallel to the other common terminal (for example, A2).
  • the at least one transistor (for example, F23) is controlled to be turned on. Therefore, the transistor F23 can flow an unnecessary high-frequency signal to the ground terminal without flowing to the common terminal A2.
  • the isolation characteristics between the common terminals A1 and A2 can be improved.
  • the transistors F21 to F24 are the same depletion type or enhancement type field effect transistors as the transistors F11 to F14, and one common terminal A1 ( When A2) and one terminal P1 (P2) are conducted, at least one of the two transistors F23 and F24 (F21, F22) connected in parallel to the other common terminal A2 (A1) is turned on.
  • the isolation characteristic between the common terminals A1 and A2 can be improved, and further, it is configured by a field effect transistor of a different type (enhancement type or depletion type) from the transistors F11 to F14.
  • the semiconductor switch circuit 2 according to the second embodiment of the present invention includes a plurality of common terminals with respect to a plurality of terminals, it can be incorporated into a device that requires a plurality of common terminals.
  • the resistors R connected to the gate electrodes of the transistors F11 to F14 and the transistors F21 to F24 may all have the same resistance value or different resistance values.
  • the resistance value of the resistor R may be a value that allows the semiconductor switch circuit 2 to perform a desired operation.
  • the capacitance value of the capacitor C connected to the source electrode of each of the transistors F21 to F24 and the inductance of the inductor L may be the same value or different values.
  • the capacitance value of the capacitor C and the inductance of the inductor L may be values that allow the semiconductor switch circuit 2 to perform a desired operation.
  • two transistors F21 and F22 and transistors F23 and F24 are connected in parallel to the common terminals A1 and A2, respectively. If it is not necessary to improve the isolation characteristics in both directions, two transistors F21 and F22 or transistors F23 and F24 may be connected in parallel only to either the common terminal A1 or the common terminal A2.
  • FIG. 3 is a circuit diagram showing a configuration example of the semiconductor switch circuit according to the third embodiment of the present invention.
  • the semiconductor switch circuit 3 according to the third embodiment of the present invention combines the configurations of the first and second embodiments, and includes transistors (second transistors) F21 to F24 connected in parallel to the terminals P1 and P2, and a common terminal A1, Transistors (third transistors) F31 to F34 connected in parallel to A2.
  • the semiconductor switch circuit 3 shown in FIG. 3 includes two common terminals A1, A2, two terminals P1, P2, four control terminals V1, V2, V3, V4, common terminals A1, A2, and terminals P1, P2.
  • the semiconductor switch circuit 3 is not limited to the configuration of a DPDT type semiconductor switch circuit having two common terminals and two terminals, and there are m common terminals (m is a natural number of 2 or more) and n terminals. It may be a configuration of mPnT type semiconductor switch circuits (n is a natural number of 2 or more).
  • n ⁇ (m ⁇ 1) transistors and m common terminals are connected between the common terminals A1 to Am and the terminals P1 to Pn.
  • n ⁇ (m ⁇ 1) transistors connected in parallel to A1 to Am
  • m ⁇ (n ⁇ 1) transistors connected in parallel to the n terminals P1 to Pn.
  • connections of the transistors F11 to F14 are the same as the connections of the transistors F11 to F14 of the semiconductor switch circuit 1 according to the first embodiment shown in FIG. 1, detailed description thereof is omitted. Further, since the connections of the transistors F21 to F24 are the same as the connections of the transistors F21 to F24 of the semiconductor switch circuit 1 according to the first embodiment shown in FIG. 1, detailed description thereof is omitted. Furthermore, since the connections of the transistors (shunt FETs) F31 to F34 are the same as the connections of the transistors F21 to F24 of the semiconductor switch circuit 2 according to the second embodiment shown in FIG.
  • the semiconductor switch circuit 3 supplies a control voltage having a high level (H) or low level (L) potential to the control terminals V1 to V4, so that the common terminals A1, A2 and The terminals P1 and P2 can be controlled to conduct.
  • H high level
  • L low level
  • the semiconductor switch circuit 3 when one common terminal (for example, A1) and one terminal (for example, P1) conduct, among the two transistors F23 and F24 connected in parallel to the other terminal (for example, P2), Control is performed so that at least one transistor (for example, F23) is turned on, and at least one of the two transistors F33 and F34 connected in parallel to the other common terminal (for example, A2) is turned on. Has been. Therefore, the transistor F23 and the transistor F33 can flow an unnecessary high-frequency signal to the ground terminal without flowing to the common terminal A2 and the terminal P2, and the isolation between the common terminals A1 and A2 and between the terminals P1 and P2. Characteristics can be improved.
  • the transistors F21 to F24 and F31 to F34 are field effect transistors of the same type as the transistors F11 to F14, and one common terminal A1 ( When A2) and one terminal P1 (P2) are conducted, at least one of the two transistors F33 and F34 (F31, F32) connected in parallel to the other common terminal A2 (A1) is turned on.
  • the semiconductor switch circuit 3 according to the third embodiment of the present invention includes a plurality of common terminals with respect to a plurality of terminals, it can be incorporated into a device that requires a plurality of common terminals.
  • the resistors R connected to the gate electrodes of the transistors F11 to F14, the transistors F21 to F24, and the transistors F31 to F34 may all have the same resistance value or different resistance values.
  • the resistance value of the resistor R may be a value that allows the semiconductor switch circuit 3 to perform a desired operation.
  • the capacitance value of the capacitor C connected to the source electrode of each of the transistors F21 to F24 and the transistors F31 to F34 and the inductance of the inductor L may all be the same value or may be different values.
  • the capacitance value of the capacitor C and the inductance of the inductor L may be values that allow the semiconductor switch circuit 3 to perform a desired operation.
  • two transistors F31 and F32, transistors F33 and F34, transistors F21 and F22, transistors F23 and F2 are connected to the common terminals A1 and A2 and terminals P1 and P2, respectively.
  • F24 is connected in parallel, if it is not necessary to improve the isolation characteristics in both directions between the common terminals A1 and A2, the two transistors F31 and F32 are provided only in either the common terminal A1 or the common terminal A2.
  • the transistors F33 and F34 may be connected in parallel, and if it is not necessary to improve the isolation characteristics in both directions between the terminals P1 and P2, the two transistors F21 are provided only at either the terminal P1 or the terminal P2.
  • F22 or transistors F23 and F24 connected in parallel It may be.

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Abstract

In the present invention, a semiconductor switch circuit is provided, which, while improving the isolation characteristics between terminals and/or between common terminals, enables manufacturing costs to be reduced due to not requiring additional manufacturing processes. This semiconductor switch circuit (1) is equipped with common terminals (A1, A2), terminals (P1, P2), four transistors (first transistor) F11 to F14, and transistors (second transistor) F21 to F24 connected in parallel to the terminals (P1, P2). The transistors F21 to F24 are the same depression-type or the same enhancement-type field effect transistors as the transistors F11 to F14 , and when conduction occurs between one of the common terminals (A1) (or A2) and one of the terminals (P1) (or P2), at least one of the transistors (F23, F24) (or F21, F22) that are connected in parallel to the other terminal (P2) (or P1) is controlled in such a manner as to switch on.

Description

半導体スイッチ回路Semiconductor switch circuit
　本発明は、半導体スイッチ回路に関し、特に複数のトランジスタを用いた半導体スイッチ回路に関する。 The present invention relates to a semiconductor switch circuit, and more particularly to a semiconductor switch circuit using a plurality of transistors.
　近年、携帯電話機や無線ＬＡＮの普及に伴い、トランジスタを用いて高周波信号の流れを切り換える半導体スイッチ回路が開発されている。特許文献１には、構成部品が少なく、２つの端子と２つ以上の共通端子との間の信号の流れを切り換える、従来の半導体スイッチ回路が開示されている。図４は、従来の半導体スイッチ回路の構成例を示す回路図である。 In recent years, with the widespread use of mobile phones and wireless LANs, semiconductor switch circuits that switch the flow of high-frequency signals using transistors have been developed. Patent Document 1 discloses a conventional semiconductor switch circuit that has few components and switches a signal flow between two terminals and two or more common terminals. FIG. 4 is a circuit diagram showing a configuration example of a conventional semiconductor switch circuit.
　図４に示す半導体スイッチ回路１００は、二つの共通端子Ａ１０１、Ａ１０２と、二つの端子Ｐ１０１、Ｐ１０２と、二つの制御端子Ｖ１０１、Ｖ１０２と、共通端子Ａ１０１、Ａ１０２と端子Ｐ１０１、Ｐ１０２との間に接続された四つのトランジスタ（第１トランジスタ）Ｆ１０１～Ｆ１０４と、端子Ｐ１０１、Ｐ１０２にそれぞれ接続されたトランジスタ（第２トランジスタ）Ｆ１０５、Ｆ１０６と、トランジスタＦ１０５、及びトランジスタＦ１０１、Ｆ１０４のゲート電極に接続されたインバータ回路Ｌ１０１、Ｌ１０２とを備える。なお、トランジスタＦ１０５、Ｆ１０６は、シャントＦＥＴである。 The semiconductor switch circuit 100 shown in FIG. 4 includes two common terminals A101 and A102, two terminals P101 and P102, two control terminals V101 and V102, and the common terminals A101 and A102 and the terminals P101 and P102. Four transistors (first transistors) F101 to F104 connected, transistors (second transistors) F105 and F106 connected to terminals P101 and P102, respectively, and gate electrodes of the transistors F105 and F101 and F104. Inverter circuits L101 and L102. The transistors F105 and F106 are shunt FETs.
　トランジスタＦ１０１は、ドレイン電極が端子Ｐ１０１に、ソース電極が共通端子Ａ１０１に、ゲート電極が抵抗Ｒを介してインバータ回路Ｌ１０２に、それぞれ接続されている。なお、インバータ回路Ｌ１０２は、制御端子Ｖ１０２に接続されている。トランジスタＦ１０２は、ドレイン電極が端子Ｐ１０１に、ソース電極が共通端子Ａ１０２に、ゲート電極が抵抗Ｒを介して制御端子Ｖ１０２に、それぞれ接続されている。トランジスタＦ１０３は、ドレイン電極が端子Ｐ１０２に、ソース電極が共通端子Ａ１０１に、ゲート電極が抵抗Ｒを介して制御端子Ｖ１０２に、それぞれ接続されている。トランジスタＦ１０４は、ドレイン電極が端子Ｐ１０２に、ソース電極が共通端子Ａ１０２に、ゲート電極が抵抗Ｒを介してインバータ回路Ｌ１０２に、それぞれ接続されている。 The transistor F101 has a drain electrode connected to the terminal P101, a source electrode connected to the common terminal A101, and a gate electrode connected to the inverter circuit L102 via the resistor R. The inverter circuit L102 is connected to the control terminal V102. The transistor F102 has a drain electrode connected to the terminal P101, a source electrode connected to the common terminal A102, and a gate electrode connected to the control terminal V102 via the resistor R. The transistor F103 has a drain electrode connected to the terminal P102, a source electrode connected to the common terminal A101, and a gate electrode connected to the control terminal V102 via the resistor R. The transistor F104 has a drain electrode connected to the terminal P102, a source electrode connected to the common terminal A102, and a gate electrode connected to the inverter circuit L102 via the resistor R.
　トランジスタＦ１０５は、ドレイン電極が端子Ｐ１０１に、ソース電極が容量ＣとインダクタＬとを介して接地端子に、ゲート電極が抵抗Ｒを介してインバータ回路Ｌ１０１に、それぞれ接続されている。なお、インバータ回路Ｌ１０１は、制御端子Ｖ１０１に接続されている。トランジスタＦ１０６は、ドレイン電極が端子Ｐ１０２に、ソース電極が容量ＣとインダクタＬとを介して接地端子に、ゲート電極が抵抗Ｒを介して制御端子Ｖ１０１に、それぞれ接続されている。 The transistor F105 has a drain electrode connected to the terminal P101, a source electrode connected to the ground terminal via the capacitor C and the inductor L, and a gate electrode connected to the inverter circuit L101 via the resistor R. The inverter circuit L101 is connected to the control terminal V101. The transistor F106 has a drain electrode connected to the terminal P102, a source electrode connected to the ground terminal via the capacitor C and the inductor L, and a gate electrode connected to the control terminal V101 via the resistor R.
　次に、従来の半導体スイッチ回路１００の動作について説明する。（表１）は、制御電圧の供給と回路動作との関係を示している。半導体スイッチ回路１００は、（表１）に示すように制御端子Ｖ１０１、Ｖ１０２にハイレベル（Ｈ）又はローレベル（Ｌ）の電位の制御電圧を供給することで、共通端子Ａ１０１、Ａ１０２と、端子Ｐ１０１、Ｐ１０２とが導通するように制御することができる。 Next, the operation of the conventional semiconductor switch circuit 100 will be described. Table 1 shows the relationship between the supply of the control voltage and the circuit operation. As shown in Table 1, the semiconductor switch circuit 100 supplies a control voltage having a high level (H) or low level (L) potential to the control terminals V101 and V102, so that the common terminals A101 and A102, P101 and P102 can be controlled to be conductive.
Figure JPOXMLDOC01-appb-T000001
Figure JPOXMLDOC01-appb-T000001
　（表１）に示すように、制御端子Ｖ１０１にハイレベルの電位の制御電圧が、制御端子Ｖ１０２にローレベルの電位の制御電圧が、それぞれ供給された場合、トランジスタＦ１０１がオン状態（トランジスタＦ１０１のドレイン－ソース間が低抵抗になり所望量の電流が流れる状態）、トランジスタＦ１０２、Ｆ１０３及びトランジスタ（シャントＦＥＴ）Ｆ１０５がオフ状態（トランジスタＦ１０５のドレイン－ソース間が高抵抗になり所望量の電流が流れない状態）となるので、共通端子Ａ１０１と、端子Ｐ１０１とが導通する。このとき、トランジスタＦ１０４がオン状態となるが、トランジスタ（シャントＦＥＴ）Ｆ１０６がオン状態となるので、不要な高周波信号を端子Ｐ１０２に流すことなく接地端子に流すことができる。制御端子Ｖ１０１及び制御端子Ｖ１０２にハイレベルの電位の制御電圧が、それぞれ供給された場合、トランジスタＦ１０２がオン状態、トランジスタＦ１０１、Ｆ１０４及びトランジスタＦ１０５がオフ状態となるので、共通端子Ａ１０２と、端子Ｐ１０１とが導通する。このとき、トランジスタＦ１０３がオン状態となるが、トランジスタＦ１０６がオン状態となるので、不要な高周波信号を端子Ｐ１０２に流すことなく接地端子に流すことができる。 As shown in Table 1, when a control voltage having a high level potential is supplied to the control terminal V101 and a control voltage having a low level potential is supplied to the control terminal V102, the transistor F101 is turned on (the transistor F101 is turned on). The transistor F102, F103 and the transistor (shunt FET) F105 are in the OFF state (the drain-source of the transistor F105 has a high resistance and a desired amount of current flows). Therefore, the common terminal A101 is electrically connected to the terminal P101. At this time, the transistor F104 is turned on, but the transistor (shunt FET) F106 is turned on, so that an unnecessary high-frequency signal can be fed to the ground terminal without flowing to the terminal P102. When a high-level control voltage is supplied to the control terminal V101 and the control terminal V102, the transistor F102 is turned on and the transistors F101, F104, and F105 are turned off, so that the common terminal A102 and the terminal P101 are turned on. And conduct. At this time, the transistor F103 is turned on, but since the transistor F106 is turned on, an unnecessary high-frequency signal can be fed to the ground terminal without flowing to the terminal P102.
　制御端子Ｖ１０１にローレベルの電位の制御電圧が、制御端子Ｖ１０２にハイレベルの電位の制御電圧が、それぞれ供給された場合、トランジスタＦ１０３がオン状態、トランジスタＦ１０１、Ｆ１０４及びトランジスタＦ１０６がオフ状態となるので、共通端子Ａ１０１と、端子Ｐ１０２とが導通する。このとき、トランジスタＦ１０２がオン状態となるが、トランジスタＦ１０５がオン状態となるので、不要な高周波信号を端子Ｐ１０１に流すことなく接地端子に流すことができる。制御端子Ｖ１０１及び制御端子Ｖ１０２にローレベルの電位の制御電圧が、それぞれ供給された場合、トランジスタＦ１０４がオン状態、トランジスタＦ１０２、Ｆ１０３及びトランジスタＦ１０６がオフ状態となるので、共通端子Ａ１０２と、端子Ｐ１０２とが導通する。このとき、トランジスタＦ１０１がオン状態となるが、トランジスタＦ１０５がオン状態となるので、不要な高周波信号を端子Ｐ１０１に流すことなく接地端子に流すことができる。 When a control voltage having a low level potential is supplied to the control terminal V101 and a control voltage having a high level potential is supplied to the control terminal V102, the transistor F103 is turned on, and the transistors F101, F104, and the transistor F106 are turned off. Therefore, the common terminal A101 and the terminal P102 are conducted. At this time, the transistor F102 is turned on, but since the transistor F105 is turned on, an unnecessary high-frequency signal can be fed to the ground terminal without flowing to the terminal P101. When a low-level control voltage is supplied to the control terminal V101 and the control terminal V102, the transistor F104 is turned on and the transistors F102, F103, and the transistor F106 are turned off, so that the common terminal A102 and the terminal P102 are turned on. And conduct. At this time, the transistor F101 is turned on, but since the transistor F105 is turned on, an unnecessary high-frequency signal can be supplied to the ground terminal without flowing to the terminal P101.
　半導体スイッチ回路１００では、トランジスタＦ１０５及びトランジスタＦ１０６のうち必ず一方がオン状態となるように制御されているので、不要な高周波信号を端子Ｐ１０１及び端子Ｐ１０２の一方に流すことなく接地端子に流すことができ、端子Ｐ１０１、Ｐ１０２の間のアイソレーション特性を向上させることができる。 In the semiconductor switch circuit 100, since one of the transistor F105 and the transistor F106 is controlled to be turned on, an unnecessary high-frequency signal is allowed to flow to the ground terminal without flowing to one of the terminal P101 and the terminal P102. In addition, the isolation characteristic between the terminals P101 and P102 can be improved.
特開平９－８６２７号公報Japanese Patent Laid-Open No. 9-8627
　図４に示す半導体スイッチ回路１００では、トランジスタＦ１０１～Ｆ１０４及びトランジスタＦ１０５、Ｆ１０６にゲート電圧が負電圧（０Ｖ以下）でもドレイン電流が流れるディプレッション型の電界効果トランジスタを用いているが、ロジック回路であるインバータ回路Ｌ１０１、Ｌ１０２にはディプレッション型の電界効果トランジスタを用いることができない。つまり、制御端子Ｖ１０１、Ｖ１０２にハイレベル又はローレベルの電位の制御電圧が供給された場合、インバータ回路Ｌ１０１、Ｌ１０２を正常に動作させるためには、インバータ回路Ｌ１０１、Ｌ１０２を構成するトランジスタに、ゲート電圧が正電圧（０Ｖより大きい）でないとドレイン電流が流れないエンハンスメント型の電界効果トランジスタを用いる必要がある。 In the semiconductor switch circuit 100 shown in FIG. 4, a depletion type field effect transistor in which a drain current flows even when the gate voltage is a negative voltage (0 V or less) is used for the transistors F101 to F104 and the transistors F105 and F106. A depletion type field effect transistor cannot be used for the inverter circuits L101 and L102. That is, when a control voltage having a high level or low level potential is supplied to the control terminals V101 and V102, the gates of the transistors constituting the inverter circuits L101 and L102 are connected to the gates in order to operate the inverter circuits L101 and L102 normally. It is necessary to use an enhancement type field effect transistor in which the drain current does not flow unless the voltage is a positive voltage (greater than 0 V).
　しかし、半導体スイッチ回路１００のように、一の回路をディプレッション型の電界効果トランジスタとエンハンスメント型の電界効果トランジスタとで構成する場合、ピンチオフ電圧が無相関にばらつくという問題があった。また、異なる型の電界効果トランジスタで構成されるロジック回路を用いるため、製造コストを低減することができないという問題があった。 However, when one circuit is composed of a depletion type field effect transistor and an enhancement type field effect transistor as in the semiconductor switch circuit 100, there is a problem that the pinch-off voltage varies uncorrelated. In addition, since a logic circuit composed of different types of field effect transistors is used, there is a problem in that the manufacturing cost cannot be reduced.
　本発明は、斯かる事情に鑑みてなされたものであり、端子の間及び／又は共通端子の間のアイソレーション特性を向上させつつ、製造プロセスの追加が不要で、製造コストを低減することができる半導体スイッチ回路を提供することを目的とする。 The present invention has been made in view of such circumstances, and it is possible to improve the isolation characteristics between the terminals and / or between the common terminals without adding a manufacturing process and reducing the manufacturing cost. An object of the present invention is to provide a semiconductor switch circuit that can be used.
　上記目的を達成するために第１発明に係る半導体スイッチ回路は、第１乃至第ｍ（ｍは２以上の自然数）の共通端子と、第１乃至第ｎ（ｎは２以上の自然数）の端子と、第１乃至第ｍの前記共通端子と第１乃至第ｎの前記端子との間に接続され、一の共通端子と、一の端子とが導通するように制御することが可能なｍ×ｎ個の第１トランジスタと、少なくとも一の端子に並列接続されたｍ×（ｎ－１）個の第２トランジスタとを備え、前記第１トランジスタ及び前記第２トランジスタは、同じディプレッション型又は同じエンハンスメント型の電界効果トランジスタであり、一の共通端子と、一の端子とが導通する場合、他の端子に並列接続された第２トランジスタのうち、少なくとも一の第２トランジスタがオン状態となるように制御することを特徴とする。 To achieve the above object, a semiconductor switch circuit according to a first aspect of the present invention includes first to m-th (m is a natural number of 2 or more) common terminals and first to n-th (n is a natural number of 2 or more) terminals. Are connected between the first to m-th common terminals and the first to n-th terminals, and can be controlled so that one common terminal and one terminal are conductive. and n × (n−1) second transistors connected in parallel to at least one terminal, wherein the first transistor and the second transistor are the same depletion type or the same enhancement. When a common terminal and one terminal are conductive, at least one second transistor is turned on among the second transistors connected in parallel to the other terminal. Control It is characterized by that.
　第１発明では、ｍ×ｎ個の第１トランジスタ及びｍ×（ｎ－１）個の第２トランジスタは、同じディプレッション型又は同じエンハンスメント型の電界効果トランジスタであり、一の共通端子と、一の端子とが導通する場合、他の端子に並列接続された第２トランジスタのうち、少なくとも一の第２トランジスタがオン状態となるように制御することで、端子の間のアイソレーション特性を向上させることができ、さらに第１トランジスタ（ディプレッション型又はエンハンスメント型）と異なる型（エンハンスメント型又はディプレッション型）の電界効果トランジスタで構成されるロジック回路を用いることなく、同じ型の電界効果トランジスタのみで構成されるので、製造コストを低減することができる。また、ロジック回路を用いることがないため、ＥＳＤ（静電気放電）に対する耐性が向上するとともに、ロジック回路の占有面積が不要となり半導体スイッチ回路を小型化することができる。 In the first invention, the m × n first transistors and the m × (n−1) second transistors are the same depletion type or the same enhancement type field effect transistor, and one common terminal, When the terminals are conductive, the isolation characteristics between the terminals are improved by controlling so that at least one second transistor of the second transistors connected in parallel to the other terminals is turned on. Furthermore, it is composed of only the field effect transistor of the same type without using a logic circuit composed of a field effect transistor of a different type (enhancement type or depletion type) from the first transistor (depletion type or enhancement type). Therefore, the manufacturing cost can be reduced. In addition, since no logic circuit is used, resistance against ESD (electrostatic discharge) is improved, and the area occupied by the logic circuit is not required, and the semiconductor switch circuit can be downsized.
　また、第２発明に係る半導体スイッチ回路は、第１発明において、前記第２トランジスタは、共振回路を介して接地端子に接続されている。 Further, in the semiconductor switch circuit according to a second invention, in the first invention, the second transistor is connected to a ground terminal via a resonance circuit.
　第２発明では、第２トランジスタが、共振回路を介して接地端子に接続されているので、所望の周波数の信号を共振させて接地端子に流し、所望の周波数の信号を減衰させることができる。 In the second invention, since the second transistor is connected to the ground terminal via the resonance circuit, it is possible to resonate a signal having a desired frequency and flow the signal to the ground terminal to attenuate the signal having the desired frequency.
　また、第３発明に係る半導体スイッチ回路は、第１又は第２発明において、少なくとも一の共通端子に並列接続されたｎ×（ｍ－１）個の第３トランジスタをさらに備え、前記第３トランジスタは、前記第１トランジスタ及び前記第２トランジスタと同じ型の電界効果トランジスタであり、一の共通端子と一の端子とが導通する場合、他の共通端子に並列接続された第３トランジスタのうち、少なくとも一の第３トランジスタがオン状態となるように制御することを特徴とする。 The semiconductor switch circuit according to a third aspect of the present invention further comprises n × (m−1) third transistors connected in parallel to at least one common terminal in the first or second aspect, wherein the third transistor Is a field effect transistor of the same type as the first transistor and the second transistor, and when one common terminal and one terminal are conductive, among the third transistors connected in parallel to the other common terminal, Control is performed so that at least one third transistor is turned on.
　第３発明では、第３トランジスタは、第１トランジスタ及び第２トランジスタと同じ型の電界効果トランジスタであり、一の共通端子と一の端子とが導通する場合、他の共通端子に並列接続された第３トランジスタのうち、少なくとも一の第３トランジスタがオン状態となるように制御することで、端子の間及び共通端子の間のアイソレーション特性を向上させることができ、さらに第１トランジスタ及び第２トランジスタ（ディプレッション型又はエンハンスメント型）と異なる型（エンハンスメント型又はディプレッション型）の電界効果トランジスタで構成されるロジック回路を用いることなく、同じ型の電界効果トランジスタのみで構成されるので、製造コストを低減することができる。 In the third invention, the third transistor is a field effect transistor of the same type as the first transistor and the second transistor, and is connected in parallel to another common terminal when one common terminal and one terminal are conductive. By controlling so that at least one third transistor of the third transistors is turned on, the isolation characteristics between the terminals and between the common terminals can be improved, and further, the first transistor and the second transistor can be improved. Reduces manufacturing costs by using only the same type of field effect transistors without using a logic circuit consisting of field effect transistors of different types (enhancement type or depletion type) than transistors (depletion type or enhancement type) can do.
　また、第４発明に係る半導体スイッチ回路は、第３発明において、前記第３トランジスタは、共振回路を介して接地端子に接続されている。 The semiconductor switch circuit according to a fourth aspect of the present invention is the semiconductor switch circuit according to the third aspect, wherein the third transistor is connected to a ground terminal via a resonance circuit.
　第４発明では、第３トランジスタが、共振回路を介して接地端子に接続されているので、所望の周波数の信号を共振させて接地端子に流し、所望の周波数の信号を減衰させることができる。 In the fourth invention, since the third transistor is connected to the ground terminal via the resonance circuit, it is possible to resonate a signal having a desired frequency and flow it to the ground terminal to attenuate the signal having the desired frequency.
　上記目的を達成するために第５発明に係る半導体スイッチ回路は、第１乃至第ｍ（ｍは２以上の自然数）の共通端子と、第１乃至第ｎ（ｎは２以上の自然数）の端子と、第１乃至第ｍの前記共通端子と第１乃至第ｎの前記端子との間に接続され、一の共通端子と一の端子とが導通するように制御することが可能なｍ×ｎ個の第１トランジスタと、少なくとも一の共通端子に並列接続されたｎ×（ｍ－１）個の第２トランジスタとを備え、前記第１トランジスタ及び前記第２トランジスタは、同じディプレッション型又は同じエンハンスメント型の電界効果トランジスタであり、一の共通端子と一の端子とが導通する場合、他の共通端子に並列接続された第２トランジスタのうち、少なくとも一の第２トランジスタがオン状態となるように制御することを特徴とする。 In order to achieve the above object, a semiconductor switch circuit according to a fifth aspect of the present invention includes first to m-th (m is a natural number of 2 or more) common terminals and first to n-th (n is a natural number of 2 or more) terminals. Are connected between the first to m-th common terminals and the first to n-th terminals, and can be controlled so that one common terminal and one terminal are conductive. First transistors and n × (m−1) second transistors connected in parallel to at least one common terminal, wherein the first transistor and the second transistor have the same depletion type or the same enhancement Type of field effect transistor, and when one common terminal and one terminal are conductive, at least one second transistor of the second transistors connected in parallel to the other common terminal is turned on. control It is characterized by doing.
　第５発明では、ｍ×ｎ個の第１トランジスタ及びｎ×（ｍ－１）個の第２トランジスタは、同じディプレッション型又は同じエンハンスメント型の電界効果トランジスタであり、一の共通端子と一の端子とが導通する場合、他の共通端子に並列接続された第２トランジスタのうち、少なくとも一の第２トランジスタがオン状態となるように制御することで、共通端子の間のアイソレーション特性を向上させることができ、さらに第１トランジスタ（ディプレッション型又はエンハンスメント型）と異なる型（エンハンスメント型又はディプレッション型）の電界効果トランジスタで構成されるロジック回路を用いることなく、同じ型の電界効果トランジスタのみで構成されるので、製造コストを低減することができる。また、ロジック回路を用いることがないため、ＥＳＤ（静電気放電）に対する耐性が向上するとともに、ロジック回路の占有面積が不要となり半導体スイッチ回路を小型化することができる。 In the fifth invention, the m × n first transistors and the n × (m−1) second transistors are the same depletion type or the same enhancement type field effect transistor, and have one common terminal and one terminal. Is connected, the second transistor connected in parallel to another common terminal is controlled so that at least one second transistor is turned on, thereby improving the isolation characteristics between the common terminals. In addition, the first transistor (depletion type or enhancement type) and a different type (enhancement type or depletion type) field effect transistor can be used without using a logic circuit. Therefore, the manufacturing cost can be reduced. In addition, since no logic circuit is used, resistance against ESD (electrostatic discharge) is improved, and the area occupied by the logic circuit is not required, and the semiconductor switch circuit can be downsized.
　また、第６発明に係る半導体スイッチ回路は、第５発明において、前記第２トランジスタは、共振回路を介して接地端子に接続されている。 Further, in the semiconductor switch circuit according to a sixth aspect of the present invention based on the fifth aspect, the second transistor is connected to a ground terminal via a resonance circuit.
　第６発明では、第２トランジスタが、共振回路を介して接地端子に接続されているので、所望の周波数の信号を共振させて接地端子に流し、所望の周波数の信号を減衰させることができる。 In the sixth aspect of the invention, since the second transistor is connected to the ground terminal via the resonance circuit, it is possible to resonate a signal having a desired frequency and flow the signal to the ground terminal to attenuate the signal having the desired frequency.
　また、第７発明に係る半導体スイッチ回路は、第１乃至第６発明のいずれか一つにおいて、前記第１乃至第３トランジスタは、ディプレッション型の電界効果トランジスタである。 The semiconductor switch circuit according to a seventh aspect of the present invention is the semiconductor switch circuit according to any one of the first to sixth aspects, wherein the first to third transistors are depletion type field effect transistors.
　第７発明では、第１乃至第３トランジスタはディプレッション型の電界効果トランジスタであり、半導体スイッチ回路をディプレッション型の電界効果トランジスタのみで構成することで、ディプレッション型の電界効果トランジスタとエンハンスメント型の電界効果トランジスタとで構成する場合のようにピンチオフ電圧が無相関にばらつくことがなく、歩留まりを高めることが可能になる。 In the seventh invention, the first to third transistors are depletion type field effect transistors, and the depletion type field effect transistor and the enhancement type field effect transistor are formed by configuring the semiconductor switch circuit only with the depletion type field effect transistor. The pinch-off voltage does not vary uncorrelated as in the case of using a transistor, and the yield can be increased.
　本発明では、ｍ×ｎ個の第１トランジスタ及びｍ×（ｎ－１）個の第２トランジスタは、同じディプレッション型又は同じエンハンスメント型の電界効果トランジスタであり、一の共通端子と、一の端子とが導通する場合、他の端子に並列接続された第２トランジスタのうち、少なくとも一の第２トランジスタがオン状態となるように制御することで、端子の間のアイソレーション特性を向上させることができ、さらに第１トランジスタ（ディプレッション型又はエンハンスメント型）と異なる型（エンハンスメント型又はディプレッション型）の電界効果トランジスタで構成されるロジック回路を用いることなく、同じ型の電界効果トランジスタのみで構成されるので、製造コストを低減することができる。また、ロジック回路を用いることがないため、ＥＳＤ（静電気放電）に対する耐性が向上するとともに、ロジック回路の占有面積が不要となり半導体スイッチ回路を小型化することができる。 In the present invention, the m × n first transistors and the m × (n−1) second transistors are field effect transistors of the same depletion type or the same enhancement type, and one common terminal and one terminal Can be improved by turning on at least one second transistor of the second transistors connected in parallel to the other terminals, so that the isolation characteristics between the terminals can be improved. In addition, since the first transistor (depletion type or enhancement type) and a different type (enhancement type or depletion type) field effect transistor are not used, the logic circuit is composed of only the same type of field effect transistor. The manufacturing cost can be reduced. In addition, since no logic circuit is used, resistance against ESD (electrostatic discharge) is improved, and the area occupied by the logic circuit is not required, and the semiconductor switch circuit can be downsized.
　さらに、本発明の別の構成では、ｍ×ｎ個の第１トランジスタ及びｎ×（ｍ－１）個の第２トランジスタは、同じディプレッション型又は同じエンハンスメント型の電界効果トランジスタであり、一の共通端子と一の端子とが導通する場合、他の共通端子に並列接続された第２トランジスタのうち、少なくとも一の第２トランジスタがオン状態となるように制御することで、共通端子の間のアイソレーション特性を向上させることができ、さらに第１トランジスタ（ディプレッション型又はエンハンスメント型）と異なる型（エンハンスメント型又はディプレッション型）の電界効果トランジスタで構成されるロジック回路を用いることなく、同じ型の電界効果トランジスタのみで構成されるので、製造コストを低減することができる。また、ロジック回路を用いることがないため、ＥＳＤ（静電気放電）に対する耐性が向上するとともに、ロジック回路の占有面積が不要となり半導体スイッチ回路を小型化することができる。 Further, in another configuration of the present invention, the m × n first transistors and the n × (m−1) second transistors are the same depletion type or the same enhancement type field effect transistor, When the terminal and the one terminal are conductive, the isolating circuit between the common terminals is controlled by controlling so that at least one of the second transistors connected in parallel to the other common terminal is turned on. The field effect of the same type without using a logic circuit composed of a field effect transistor of a different type (enhancement type or depletion type) from the first transistor (depletion type or enhancement type). Since only the transistor is used, the manufacturing cost can be reduced. In addition, since no logic circuit is used, resistance against ESD (electrostatic discharge) is improved, and the area occupied by the logic circuit is not required, and the semiconductor switch circuit can be downsized.
本発明の実施の形態１に係る半導体スイッチ回路の構成例を示す回路図である。1 is a circuit diagram illustrating a configuration example of a semiconductor switch circuit according to a first embodiment of the present invention. 本発明の実施の形態２に係る半導体スイッチ回路の構成例を示す回路図である。It is a circuit diagram which shows the structural example of the semiconductor switch circuit which concerns on Embodiment 2 of this invention. 本発明の実施の形態３に係る半導体スイッチ回路の構成例を示す回路図である。It is a circuit diagram which shows the structural example of the semiconductor switch circuit which concerns on Embodiment 3 of this invention. 従来の半導体スイッチ回路の構成例を示す回路図である。It is a circuit diagram which shows the structural example of the conventional semiconductor switch circuit.
　以下、本発明の実施の形態について、図面を参照しながら詳細に説明する。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
　（実施の形態１）
　図１は、本発明の実施の形態１に係る半導体スイッチ回路の構成例を示す回路図である。図１に示す半導体スイッチ回路１は、二つの共通端子Ａ１、Ａ２と、二つの端子Ｐ１、Ｐ２と、四つの制御端子Ｖ１、Ｖ２、Ｖ３、Ｖ４と、共通端子Ａ１、Ａ２と端子Ｐ１、Ｐ２との間に接続された四つのトランジスタ（第１トランジスタ）Ｆ１１～Ｆ１４と、端子Ｐ１に並列接続されたトランジスタ（第２トランジスタ）Ｆ２１、Ｆ２２と、端子Ｐ２に並列接続されたトランジスタ（第２トランジスタ）Ｆ２３、Ｆ２４とを備える。なお、半導体スイッチ回路１は、共通端子が二つ、端子が二つのＤＰＤＴ型半導体スイッチ回路の構成に限定されるものではなく、共通端子がｍ（ｍは２以上の自然数）個、端子がｎ（ｎは２以上の自然数）個のｍＰｎＴ型半導体スイッチ回路の構成であっても良い。共通端子がｍ個、端子がｎ個の構成の半導体スイッチ回路１の場合、共通端子Ａ１～Ａｍと端子Ｐ１～Ｐｎとの間に接続されるトランジスタはｍ×ｎ個、ｎ個の各端子Ｐ１～Ｐｎに並列接続されるトランジスタはｍ×（ｎ－１）個となる。 (Embodiment 1)
FIG. 1 is a circuit diagram showing a configuration example of the semiconductor switch circuit according to the first embodiment of the present invention. 1 includes two common terminals A1 and A2, two terminals P1 and P2, four control terminals V1, V2, V3, and V4, common terminals A1 and A2, and terminals P1 and P2. Transistors (first transistors) F11 to F14 connected to each other, transistors (second transistors) F21 and F22 connected in parallel to the terminal P1, and transistors (second transistors) connected in parallel to the terminal P2 ) F23 and F24. The semiconductor switch circuit 1 is not limited to the configuration of a DPDT type semiconductor switch circuit having two common terminals and two terminals. The number of common terminals is m (m is a natural number of 2 or more) and the number of terminals is n. It may be a configuration of mPnT type semiconductor switch circuits (n is a natural number of 2 or more). In the case of the semiconductor switch circuit 1 configured with m common terminals and n terminals, the number of transistors connected between the common terminals A1 to Am and the terminals P1 to Pn is mxn and each of the n terminals P1. The number of transistors connected in parallel to .about.Pn is m.times. (N-1).
　トランジスタＦ１１は、ドレイン電極が端子Ｐ１に、ソース電極が共通端子Ａ１に、ゲート電極が抵抗Ｒを介して制御端子Ｖ１に、それぞれ接続されている。トランジスタＦ１２は、ドレイン電極が端子Ｐ１に、ソース電極が共通端子Ａ２に、ゲート電極が抵抗Ｒを介して制御端子Ｖ２に、それぞれ接続されている。トランジスタＦ１３は、ドレイン電極が端子Ｐ２に、ソース電極が共通端子Ａ１に、ゲート電極が抵抗Ｒを介して制御端子Ｖ３に、それぞれ接続されている。トランジスタＦ１４は、ドレイン電極が端子Ｐ２に、ソース電極が共通端子Ａ２に、ゲート電極が抵抗Ｒを介して制御端子Ｖ４に、それぞれ接続されている。 The transistor F11 has a drain electrode connected to the terminal P1, a source electrode connected to the common terminal A1, and a gate electrode connected to the control terminal V1 via a resistor R. The transistor F12 has a drain electrode connected to the terminal P1, a source electrode connected to the common terminal A2, and a gate electrode connected to the control terminal V2 via the resistor R. The transistor F13 has a drain electrode connected to the terminal P2, a source electrode connected to the common terminal A1, and a gate electrode connected to the control terminal V3 via the resistor R. The transistor F14 has a drain electrode connected to the terminal P2, a source electrode connected to the common terminal A2, and a gate electrode connected to the control terminal V4 via the resistor R.
　トランジスタ（シャントＦＥＴ）Ｆ２１は、ドレイン電極が端子Ｐ１に、ソース電極が容量ＣとインダクタＬとを介して接地端子に、ゲート電極が抵抗Ｒを介して制御端子Ｖ３に、それぞれ接続されている。トランジスタ（シャントＦＥＴ）Ｆ２２は、ドレイン電極が端子Ｐ１に、ソース電極が容量ＣとインダクタＬとを介して接地端子に、ゲート電極が抵抗Ｒを介して制御端子Ｖ４に、それぞれ接続されている。トランジスタ（シャントＦＥＴ）Ｆ２３は、ドレイン電極が端子Ｐ２に、ソース電極が容量ＣとインダクタＬとを介して接地端子に、ゲート電極が抵抗Ｒを介して制御端子Ｖ１に、それぞれ接続されている。トランジスタ（シャントＦＥＴ）Ｆ２４は、ドレイン電極が端子Ｐ２に、ソース電極が容量ＣとインダクタＬとを介して接地端子に、ゲート電極が抵抗Ｒを介して制御端子Ｖ２に、それぞれ接続されている。なお、トランジスタＦ２１～Ｆ２４は、直列接続された容量ＣとインダクタＬとで構成される共振回路を介して接地端子に接続されているので、所望の周波数の信号を共振させて接地端子に流し、所望の周波数の信号を減衰させることができる。 The transistor (shunt FET) F21 has a drain electrode connected to the terminal P1, a source electrode connected to the ground terminal via the capacitor C and the inductor L, and a gate electrode connected to the control terminal V3 via the resistor R. The transistor (shunt FET) F22 has a drain electrode connected to the terminal P1, a source electrode connected to the ground terminal via the capacitor C and the inductor L, and a gate electrode connected to the control terminal V4 via the resistor R. The transistor (shunt FET) F23 has a drain electrode connected to the terminal P2, a source electrode connected to the ground terminal via the capacitor C and the inductor L, and a gate electrode connected to the control terminal V1 via the resistor R. The transistor (shunt FET) F24 has a drain electrode connected to the terminal P2, a source electrode connected to the ground terminal via the capacitor C and the inductor L, and a gate electrode connected to the control terminal V2 via the resistor R. Since the transistors F21 to F24 are connected to the ground terminal via a resonance circuit including a capacitor C and an inductor L connected in series, a signal having a desired frequency is resonated and passed to the ground terminal. A signal having a desired frequency can be attenuated.
　端子Ｐ１、Ｐ２に並列接続されるトランジスタＦ２１～Ｆ２４には、共通端子Ａ１、Ａ２と端子Ｐ１、Ｐ２との間に接続されたトランジスタＦ１１～Ｆ１４と同じ型の電界効果トランジスタを用いている。具体的には、トランジスタＦ１１～Ｆ１４及びトランジスタＦ２１～Ｆ２４は、ディプレッション型の電界効果トランジスタであり、半導体スイッチ回路１を、ディプレッション型の電界効果トランジスタのみで構成することで、ディプレッション型の電界効果トランジスタとエンハンスメント型の電界効果トランジスタとで構成する場合のようにピンチオフ電圧が無相関にばらつくことがなく、歩留まりを高めることが可能になる。なお、トランジスタＦ１１～Ｆ１４及びトランジスタＦ２１～Ｆ２４は、ディプレッション型又はエンハンスメント型の電界効果トランジスタに限定されるものではなく、同様の動作が可能な電界効果トランジスタであれば他の型の電界効果トランジスタであっても良い。 The transistors F21 to F24 connected in parallel to the terminals P1 and P2 are field effect transistors of the same type as the transistors F11 to F14 connected between the common terminals A1 and A2 and the terminals P1 and P2. Specifically, the transistors F11 to F14 and the transistors F21 to F24 are depletion type field effect transistors, and the depletion type field effect transistor is configured by configuring the semiconductor switch circuit 1 only with the depletion type field effect transistor. And the enhancement type field effect transistor, the pinch-off voltage does not vary uncorrelated and the yield can be increased. Note that the transistors F11 to F14 and the transistors F21 to F24 are not limited to depletion type or enhancement type field effect transistors, and other types of field effect transistors may be used as long as they are field effect transistors capable of performing the same operation. There may be.
　次に、本発明の実施の形態１に係る半導体スイッチ回路１の動作について説明する。半導体スイッチ回路１は、（表２）に示すように制御端子Ｖ１～Ｖ４にハイレベル（Ｈ）又はローレベル（Ｌ）の電位の制御電圧を供給することで、共通端子Ａ１、Ａ２と、端子Ｐ１、Ｐ２とが導通するように制御することができる。 Next, the operation of the semiconductor switch circuit 1 according to the first embodiment of the present invention will be described. As shown in Table 2, the semiconductor switch circuit 1 supplies a control voltage having a high level (H) or low level (L) potential to the control terminals V1 to V4, so that the common terminals A1 and A2 and the terminals It can be controlled so that P1 and P2 are conducted.
Figure JPOXMLDOC01-appb-T000002
Figure JPOXMLDOC01-appb-T000002
　（表２）に示すように、制御端子Ｖ１にハイレベルの電位の制御電圧が、制御端子Ｖ２～Ｖ４にローレベルの電位の制御電圧が、それぞれ供給された場合、トランジスタＦ１１がオン状態、トランジスタＦ１２～Ｆ１４及びトランジスタＦ２１、Ｆ２２、Ｆ２４がオフ状態となるので、共通端子Ａ１と、端子Ｐ１とが導通する。このとき、トランジスタＦ２３がオン状態となるので、不要な高周波信号を端子Ｐ２に流すことなく接地端子に流すことができる。制御端子Ｖ２にハイレベルの電位の制御電圧が、制御端子Ｖ１、Ｖ３、Ｖ４にローレベルの電位の制御電圧が、それぞれ供給された場合、トランジスタＦ１２がオン状態、トランジスタＦ１１、Ｆ１３、Ｆ１４及びトランジスタＦ２１、Ｆ２２、Ｆ２３がオフ状態となるので、共通端子Ａ２と、端子Ｐ１とが導通する。このとき、トランジスタＦ２４がオン状態となるので、不要な高周波信号を端子Ｐ２に流すことなく接地端子に流すことができる。 As shown in Table 2, when a control voltage having a high level potential is supplied to the control terminal V1 and a control voltage having a low level potential is supplied to the control terminals V2 to V4, the transistor F11 is turned on. Since the transistors F12 to F14 and the transistors F21, F22, and F24 are turned off, the common terminal A1 is electrically connected to the terminal P1. At this time, since the transistor F23 is turned on, an unnecessary high-frequency signal can be supplied to the ground terminal without flowing to the terminal P2. When a control voltage having a high level potential is supplied to the control terminal V2 and a control voltage having a low level potential is supplied to the control terminals V1, V3, and V4, the transistor F12 is turned on, the transistors F11, F13, and F14, and the transistor Since F21, F22, and F23 are turned off, the common terminal A2 and the terminal P1 are conducted. At this time, since the transistor F24 is turned on, an unnecessary high-frequency signal can be supplied to the ground terminal without flowing to the terminal P2.
　制御端子Ｖ３にハイレベルの電位の制御電圧が、制御端子Ｖ１、Ｖ２、Ｖ４にローレベルの電位の制御電圧が、それぞれ供給された場合、トランジスタＦ１３がオン状態、トランジスタＦ１１、Ｆ１２、Ｆ１４及びトランジスタＦ２２～Ｆ２４がオフ状態となるので、共通端子Ａ１と、端子Ｐ２とが導通する。このとき、トランジスタＦ２１がオン状態となるので、不要な高周波信号を端子Ｐ１に流すことなく接地端子に流すことができる。制御端子Ｖ４にハイレベルの電位の制御電圧が、制御端子Ｖ１～Ｖ３にローレベルの電位の制御電圧が、それぞれ供給された場合、トランジスタＦ１４がオン状態、トランジスタＦ１１～Ｆ１３及びトランジスタＦ２１、Ｆ２３、Ｆ２４がオフ状態となるので、共通端子Ａ２と、端子Ｐ２とが導通する。このとき、トランジスタＦ２２がオン状態となるので、不要な高周波信号を端子Ｐ１に流すことなく接地端子に流すことができる。 When a control voltage having a high level potential is supplied to the control terminal V3 and a control voltage having a low level potential is supplied to the control terminals V1, V2, and V4, the transistor F13 is turned on, the transistors F11, F12, F14, and the transistor Since F22 to F24 are turned off, the common terminal A1 and the terminal P2 are conducted. At this time, since the transistor F21 is turned on, an unnecessary high-frequency signal can be supplied to the ground terminal without flowing to the terminal P1. When a control voltage having a high level potential is supplied to the control terminal V4 and a control voltage having a low level potential is supplied to the control terminals V1 to V3, the transistor F14 is turned on, the transistors F11 to F13, and the transistors F21, F23, Since F24 is turned off, the common terminal A2 and the terminal P2 are conducted. At this time, since the transistor F22 is turned on, an unnecessary high-frequency signal can be supplied to the ground terminal without flowing to the terminal P1.
　半導体スイッチ回路１では、一つの共通端子（例えばＡ１）と、一つの端子（例えばＰ１）とが導通する場合、他の端子（例えばＰ２）に並列接続された二つのトランジスタＦ２３、Ｆ２４のうち、少なくとも一つのトランジスタ（例えばＦ２３）がオン状態となるように制御されている。そのため、トランジスタＦ２３は、不要な高周波信号を端子Ｐ２に流すことなく接地端子に流すことができる。特に、共通端子Ａ１と端子Ｐ１との間を流れる高周波信号が、端子Ｐ２に流入することを防ぐことができるので、端子Ｐ１、Ｐ２の間のアイソレーション特性を向上させることができる。 In the semiconductor switch circuit 1, when one common terminal (for example, A1) and one terminal (for example, P1) are conducted, of the two transistors F23 and F24 connected in parallel to the other terminal (for example, P2), Control is performed so that at least one transistor (for example, F23) is turned on. Therefore, the transistor F23 can flow an unnecessary high-frequency signal to the ground terminal without flowing to the terminal P2. In particular, since a high frequency signal flowing between the common terminal A1 and the terminal P1 can be prevented from flowing into the terminal P2, the isolation characteristic between the terminals P1 and P2 can be improved.
　以上のように、本発明の実施の形態１に係る半導体スイッチ回路１は、トランジスタＦ２１～Ｆ２４が、トランジスタＦ１１～Ｆ１４と同じ型の電界効果トランジスタであり、一つの共通端子Ａ１（Ａ２）と、一つの端子Ｐ１（Ｐ２）とが導通する場合、他の端子Ｐ２（Ｐ１）に並列接続された二つのトランジスタＦ２３、Ｆ２４（Ｆ２１、Ｆ２２）のうち、少なくとも一つのトランジスタがオン状態となるように制御することで、端子Ｐ１、Ｐ２の間のアイソレーション特性を向上させることができ、さらにトランジスタＦ１１～Ｆ１４と異なる型（エンハンスメント型又はディプレッション型）の電界効果トランジスタで構成されるロジック回路を用いることなく、同じ型の電界効果トランジスタのみで構成されるので、製造コストを低減することができる。また、ゲート幅が狭い電界効果トランジスタで構成されるロジック回路を用いることがないため、ＥＳＤ（静電気放電）に対する耐性が向上するとともに、ロジック回路の占有面積が不要となり半導体スイッチ回路を小型化することができる。 As described above, in the semiconductor switch circuit 1 according to the first embodiment of the present invention, the transistors F21 to F24 are field effect transistors of the same type as the transistors F11 to F14, and one common terminal A1 (A2) When one terminal P1 (P2) conducts, at least one of the two transistors F23 and F24 (F21, F22) connected in parallel to the other terminal P2 (P1) is turned on. By controlling, the isolation characteristic between the terminals P1 and P2 can be improved, and a logic circuit composed of a field effect transistor of a different type (enhancement type or depletion type) from the transistors F11 to F14 is used. And is made up of only the same type of field effect transistors. It can be reduced. In addition, since a logic circuit composed of a field effect transistor having a narrow gate width is not used, resistance against ESD (electrostatic discharge) is improved, and the area occupied by the logic circuit is not required, and the semiconductor switch circuit is miniaturized. Can do.
　また、本発明の実施の形態１に係る半導体スイッチ回路１は、複数の端子に対して複数の共通端子を備えているため、複数の共通端子が必要な機器に組み込むことが可能となる。 In addition, since the semiconductor switch circuit 1 according to Embodiment 1 of the present invention includes a plurality of common terminals with respect to a plurality of terminals, it can be incorporated into a device that requires a plurality of common terminals.
　さらに、トランジスタＦ１１～Ｆ１４及びトランジスタＦ２１～Ｆ２４のそれぞれのゲート電極に接続されている抵抗Ｒは、全て同じ抵抗値であっても、それぞれ異なる抵抗値であっても良い。抵抗Ｒの抵抗値は、半導体スイッチ回路１が所望の動作ができる値であれば良い。また、トランジスタＦ２１～Ｆ２４のそれぞれのソース電極に接続されている容量Ｃの容量値及びインダクタＬのインダクタンスは、全て同じ値であっても、それぞれ異なる値であっても良い。容量Ｃの容量値及びインダクタＬのインダクタンスは、半導体スイッチ回路１が所望の動作ができる値であれば良い。 Further, the resistors R connected to the gate electrodes of the transistors F11 to F14 and the transistors F21 to F24 may all have the same resistance value or different resistance values. The resistance value of the resistor R may be a value that allows the semiconductor switch circuit 1 to perform a desired operation. Further, the capacitance value of the capacitor C connected to the source electrode of each of the transistors F21 to F24 and the inductance of the inductor L may be the same value or different values. The capacitance value of the capacitor C and the inductance of the inductor L may be values that allow the semiconductor switch circuit 1 to perform a desired operation.
　さらに、本発明の実施の形態１に係る半導体スイッチ回路１では、端子Ｐ１、Ｐ２のそれぞれに二つのトランジスタＦ２１とＦ２２、トランジスタＦ２３とＦ２４を並列接続しているが、端子Ｐ１、Ｐ２の間の双方向でアイソレーション特性を向上させる必要がなければ、端子Ｐ１又は端子Ｐ２のいずれか一方にのみ二つのトランジスタＦ２１、Ｆ２２又はトランジスタＦ２３、Ｆ２４を並列接続する構成でも良い。 Furthermore, in the semiconductor switch circuit 1 according to the first embodiment of the present invention, two transistors F21 and F22 and transistors F23 and F24 are connected in parallel to the terminals P1 and P2, respectively. If it is not necessary to improve the isolation characteristics in both directions, a configuration in which two transistors F21 and F22 or transistors F23 and F24 are connected in parallel only to either the terminal P1 or the terminal P2 may be employed.
　（実施の形態２）
　図２は、本発明の実施の形態２に係る半導体スイッチ回路の構成例を示す回路図である。本発明の実施の形態２に係る半導体スイッチ回路２は、実施の形態１の構成とは異なり、共通端子Ａ１、Ａ２に並列接続されたトランジスタ（第２トランジスタ）Ｆ２１～Ｆ２４を備えている。図２に示す半導体スイッチ回路２は、二つの共通端子Ａ１、Ａ２と、二つの端子Ｐ１、Ｐ２と、四つの制御端子Ｖ１、Ｖ２、Ｖ３、Ｖ４と、共通端子Ａ１、Ａ２と端子Ｐ１、Ｐ２との間に接続された四つのトランジスタ（第１トランジスタ）Ｆ１１～Ｆ１４と、共通端子Ａ１に並列接続されたトランジスタ（第２トランジスタ）Ｆ２１、Ｆ２２と、共通端子Ａ２に並列接続されたトランジスタ（第２トランジスタ）Ｆ２３、Ｆ２４とを備える。なお、半導体スイッチ回路２は、共通端子が二つ、端子が二つのＤＰＤＴ型半導体スイッチ回路の構成に限定されるものではなく、共通端子がｍ（ｍは２以上の自然数）個、端子がｎ（ｎは２以上の自然数）個のｍＰｎＴ型半導体スイッチ回路の構成であっても良い。共通端子がｍ個、端子がｎ個の構成の半導体スイッチ回路２の場合、共通端子Ａ１～Ａｍと端子Ｐ１～Ｐｎとの間に接続されるトランジスタはｍ×ｎ個、ｍ個の各共通端子Ａ１～Ａｍに並列接続されるトランジスタはｎ×（ｍ－１）個となる。 (Embodiment 2)
FIG. 2 is a circuit diagram showing a configuration example of the semiconductor switch circuit according to the second embodiment of the present invention. Unlike the configuration of the first embodiment, the semiconductor switch circuit 2 according to the second embodiment of the present invention includes transistors (second transistors) F21 to F24 connected in parallel to the common terminals A1 and A2. The semiconductor switch circuit 2 shown in FIG. 2 includes two common terminals A1, A2, two terminals P1, P2, four control terminals V1, V2, V3, V4, common terminals A1, A2, and terminals P1, P2. Transistors (first transistors) F11 to F14 connected to each other, transistors (second transistors) F21 and F22 connected in parallel to the common terminal A1, and transistors (first transistors) connected in parallel to the common terminal A2. 2 transistors) F23 and F24. The semiconductor switch circuit 2 is not limited to the configuration of the DPDT type semiconductor switch circuit having two common terminals and two terminals. The number of common terminals is m (m is a natural number of 2 or more), and the number of terminals is n. It may be a configuration of mPnT type semiconductor switch circuits (n is a natural number of 2 or more). In the case of the semiconductor switch circuit 2 configured with m common terminals and n terminals, the number of transistors connected between the common terminals A1 to Am and the terminals P1 to Pn is mxn common terminals. The number of transistors connected in parallel to A1 to Am is n × (m−1).
　トランジスタＦ１１は、ドレイン電極が端子Ｐ１に、ソース電極が共通端子Ａ１に、ゲート電極が抵抗Ｒを介して制御端子Ｖ１に、それぞれ接続されている。トランジスタＦ１２は、ドレイン電極が端子Ｐ１に、ソース電極が共通端子Ａ２に、ゲート電極が抵抗Ｒを介して制御端子Ｖ２に、それぞれ接続されている。トランジスタＦ１３は、ドレイン電極が端子Ｐ２に、ソース電極が共通端子Ａ１に、ゲート電極が抵抗Ｒを介して制御端子Ｖ３に、それぞれ接続されている。トランジスタＦ１４は、ドレイン電極が端子Ｐ２に、ソース電極が共通端子Ａ２に、ゲート電極が抵抗Ｒを介して制御端子Ｖ４に、それぞれ接続されている。 The transistor F11 has a drain electrode connected to the terminal P1, a source electrode connected to the common terminal A1, and a gate electrode connected to the control terminal V1 via a resistor R. The transistor F12 has a drain electrode connected to the terminal P1, a source electrode connected to the common terminal A2, and a gate electrode connected to the control terminal V2 via the resistor R. The transistor F13 has a drain electrode connected to the terminal P2, a source electrode connected to the common terminal A1, and a gate electrode connected to the control terminal V3 via the resistor R. The transistor F14 has a drain electrode connected to the terminal P2, a source electrode connected to the common terminal A2, and a gate electrode connected to the control terminal V4 via the resistor R.
　トランジスタ（シャントＦＥＴ）Ｆ２１は、ドレイン電極が共通端子Ａ１に、ソース電極が容量ＣとインダクタＬとを介して接地端子に、ゲート電極が抵抗Ｒを介して制御端子Ｖ４に、それぞれ接続されている。トランジスタ（シャントＦＥＴ）Ｆ２２は、ドレイン電極が共通端子Ａ１に、ソース電極が容量ＣとインダクタＬとを介して接地端子に、ゲート電極が抵抗Ｒを介して制御端子Ｖ２に、それぞれ接続されている。トランジスタ（シャントＦＥＴ）Ｆ２３は、ドレイン電極が共通端子Ａ２に、ソース電極が容量ＣとインダクタＬとを介して接地端子に、ゲート電極が抵抗Ｒを介して制御端子Ｖ１に、それぞれ接続されている。トランジスタ（シャントＦＥＴ）Ｆ２４は、ドレイン電極が共通端子Ａ２に、ソース電極が容量ＣとインダクタＬとを介して接地端子に、ゲート電極が抵抗Ｒを介して制御端子Ｖ３に、それぞれ接続されている。なお、トランジスタＦ２１～Ｆ２４は、直列接続された容量ＣとインダクタＬとで構成される共振回路を介して接地端子に接続されているので、所望の周波数の信号を共振させて接地端子に流し、所望の周波数の信号を減衰させることができる。 The transistor (shunt FET) F21 has a drain electrode connected to the common terminal A1, a source electrode connected to the ground terminal via the capacitor C and the inductor L, and a gate electrode connected to the control terminal V4 via the resistor R. . The transistor (shunt FET) F22 has a drain electrode connected to the common terminal A1, a source electrode connected to the ground terminal via the capacitor C and the inductor L, and a gate electrode connected to the control terminal V2 via the resistor R. . The transistor (shunt FET) F23 has a drain electrode connected to the common terminal A2, a source electrode connected to the ground terminal via the capacitor C and the inductor L, and a gate electrode connected to the control terminal V1 via the resistor R. . The transistor (shunt FET) F24 has a drain electrode connected to the common terminal A2, a source electrode connected to the ground terminal via the capacitor C and the inductor L, and a gate electrode connected to the control terminal V3 via the resistor R. . Since the transistors F21 to F24 are connected to the ground terminal via a resonance circuit including a capacitor C and an inductor L connected in series, a signal having a desired frequency is resonated and passed to the ground terminal. A signal having a desired frequency can be attenuated.
　共通端子Ａ１、Ａ２に並列接続されるトランジスタＦ２１～Ｆ２４には、共通端子Ａ１、Ａ２と端子Ｐ１、Ｐ２との間に接続されたトランジスタＦ１１～Ｆ１４と同じ型の電界効果トランジスタを用いている。具体的には、トランジスタＦ１１～Ｆ１４及びトランジスタＦ２１～Ｆ２４は、ディプレッション型の電界効果トランジスタであり、半導体スイッチ回路２を、ディプレッション型の電界効果トランジスタのみで構成することで、ディプレッション型の電界効果トランジスタとエンハンスメント型の電界効果トランジスタとで構成する場合のようにピンチオフ電圧が無相関にばらつくことがなく、歩留まりを高めることが可能になる。なお、トランジスタＦ１１～Ｆ１４及びトランジスタＦ２１～Ｆ２４は、ディプレッション型又はエンハンスメント型の電界効果トランジスタに限定されるものではなく、同様の動作が可能な電界効果トランジスタであれば他の型の電界効果トランジスタであっても良い。 As the transistors F21 to F24 connected in parallel to the common terminals A1 and A2, field effect transistors of the same type as the transistors F11 to F14 connected between the common terminals A1 and A2 and the terminals P1 and P2 are used. Specifically, the transistors F11 to F14 and the transistors F21 to F24 are depletion type field effect transistors, and the depletion type field effect transistors are formed by configuring the semiconductor switch circuit 2 only with the depletion type field effect transistors. And the enhancement type field effect transistor, the pinch-off voltage does not vary uncorrelated and the yield can be increased. Note that the transistors F11 to F14 and the transistors F21 to F24 are not limited to depletion type or enhancement type field effect transistors, and other types of field effect transistors may be used as long as they are field effect transistors capable of performing the same operation. There may be.
　次に、本発明の実施の形態２に係る半導体スイッチ回路２の動作について説明する。半導体スイッチ回路２は、前述の（表２）に示すように制御端子Ｖ１～Ｖ４にハイレベル（Ｈ）又はローレベル（Ｌ）の電位の制御電圧を供給することで、共通端子Ａ１、Ａ２と、端子Ｐ１、Ｐ２とが導通するように制御することができる。 Next, the operation of the semiconductor switch circuit 2 according to the second embodiment of the present invention will be described. As shown in Table 2 above, the semiconductor switch circuit 2 supplies a control voltage having a high level (H) or low level (L) potential to the control terminals V1 to V4, thereby causing the common terminals A1, A2 and The terminals P1 and P2 can be controlled to conduct.
　（表２）に示すように、制御端子Ｖ１にハイレベルの電位の制御電圧が、制御端子Ｖ２～Ｖ４にローレベルの電位の制御電圧が、それぞれ供給された場合、トランジスタＦ１１がオン状態、トランジスタＦ１２～Ｆ１４及びトランジスタＦ２１、Ｆ２２、Ｆ２４がオフ状態となるので、共通端子Ａ１と、端子Ｐ１とが導通する。このとき、トランジスタＦ２３がオン状態となるので、不要な高周波信号を共通端子Ａ２に流すことなく接地端子に流すことができる。制御端子Ｖ２にハイレベルの電位の制御電圧が、制御端子Ｖ１、Ｖ３、Ｖ４にローレベルの電位の制御電圧が、それぞれ供給された場合、トランジスタＦ１２がオン状態、トランジスタＦ１１、Ｆ１３、Ｆ１４及びトランジスタＦ２１、Ｆ２３、Ｆ２４がオフ状態となるので、共通端子Ａ２と、端子Ｐ１とが導通する。このとき、トランジスタＦ２２がオン状態となるので、不要な高周波信号を共通端子Ａ１に流すことなく接地端子に流すことができる。 As shown in Table 2, when a control voltage having a high level potential is supplied to the control terminal V1 and a control voltage having a low level potential is supplied to the control terminals V2 to V4, the transistor F11 is turned on. Since the transistors F12 to F14 and the transistors F21, F22, and F24 are turned off, the common terminal A1 is electrically connected to the terminal P1. At this time, since the transistor F23 is turned on, an unnecessary high-frequency signal can be supplied to the ground terminal without flowing to the common terminal A2. When a control voltage having a high level potential is supplied to the control terminal V2 and a control voltage having a low level potential is supplied to the control terminals V1, V3, and V4, the transistor F12 is turned on, the transistors F11, F13, and F14, and the transistor Since F21, F23, and F24 are turned off, the common terminal A2 and the terminal P1 are conducted. At this time, since the transistor F22 is turned on, an unnecessary high-frequency signal can be passed to the ground terminal without flowing to the common terminal A1.
　制御端子Ｖ３にハイレベル、制御端子Ｖ１、Ｖ２、Ｖ４にローレベルの電位の制御電圧が供給された場合、トランジスタＦ１３がオン状態、トランジスタＦ１１、Ｆ１２、Ｆ１４及びトランジスタＦ２１～Ｆ２３がオフ状態となるので、共通端子Ａ１と、端子Ｐ２とが導通する。このとき、トランジスタＦ２４がオン状態となるので、不要な高周波信号を共通端子Ａ２に流すことなく接地端子に流すことができる。制御端子Ｖ４にハイレベル、制御端子Ｖ１～Ｖ３にローレベルの電位の制御電圧が供給された場合、トランジスタＦ１４がオン状態、トランジスタＦ１１～Ｆ１３及びトランジスタＦ２２～Ｆ２４がオフ状態となるので、共通端子Ａ２と、端子Ｐ２とが導通する。このとき、トランジスタＦ２１がオン状態となるので、不要な高周波信号を共通端子Ａ１に流すことなく接地端子に流すことができる。 When a high-level control voltage is supplied to the control terminal V3 and a low-level control voltage is supplied to the control terminals V1, V2, and V4, the transistor F13 is turned on, and the transistors F11, F12, and F14 and the transistors F21 to F23 are turned off. Therefore, the common terminal A1 and the terminal P2 are conducted. At this time, since the transistor F24 is turned on, an unnecessary high-frequency signal can be supplied to the ground terminal without flowing to the common terminal A2. When a control voltage having a high level is supplied to the control terminal V4 and a low level control voltage is supplied to the control terminals V1 to V3, the transistor F14 is turned on and the transistors F11 to F13 and the transistors F22 to F24 are turned off. A2 is electrically connected to the terminal P2. At this time, since the transistor F21 is turned on, an unnecessary high-frequency signal can be supplied to the ground terminal without flowing to the common terminal A1.
　半導体スイッチ回路２では、一つの共通端子（例えばＡ１）と、一つの端子（例えばＰ１）とが導通する場合、他の共通端子（例えばＡ２）に並列接続された二つのトランジスタＦ２３、Ｆ２４のうち、少なくとも一つのトランジスタ（例えばＦ２３）がオン状態となるように制御されている。そのため、トランジスタＦ２３は、不要な高周波信号を共通端子Ａ２に流すことなく接地端子に流すことができる。特に、共通端子Ａ１と端子Ｐ１との間を流れる高周波信号が、端子Ｐ２に流入することを防ぐことができるので、共通端子Ａ１、Ａ２の間のアイソレーション特性を向上させることができる。 In the semiconductor switch circuit 2, when one common terminal (for example, A1) and one terminal (for example, P1) are conducted, of the two transistors F23 and F24 connected in parallel to the other common terminal (for example, A2). The at least one transistor (for example, F23) is controlled to be turned on. Therefore, the transistor F23 can flow an unnecessary high-frequency signal to the ground terminal without flowing to the common terminal A2. In particular, since a high-frequency signal flowing between the common terminal A1 and the terminal P1 can be prevented from flowing into the terminal P2, the isolation characteristics between the common terminals A1 and A2 can be improved.
　以上のように、本発明の実施の形態２に係る半導体スイッチ回路２は、トランジスタＦ２１～Ｆ２４が、トランジスタＦ１１～Ｆ１４と同じディプレッション型又はエンハンスメント型の電界効果トランジスタであり、一つの共通端子Ａ１（Ａ２）と、一つの端子Ｐ１（Ｐ２）とが導通する場合、他の共通端子Ａ２（Ａ１）に並列接続された二つのトランジスタＦ２３、Ｆ２４（Ｆ２１、Ｆ２２）のうち、少なくとも一つのトランジスタがオン状態となるように制御することで、共通端子Ａ１、Ａ２の間のアイソレーション特性を向上させることができ、さらにトランジスタＦ１１～Ｆ１４と異なる型（エンハンスメント型又はディプレッション型）の電界効果トランジスタで構成されるロジック回路を用いることなく、同じ型の電界効果トランジスタのみで構成されるので、製造コストを低減することができる。また、ゲート幅が狭いトランジスタで構成されるロジック回路を用いることがないため、ＥＳＤ（静電気放電）に対する耐性が向上するとともに、ロジック回路の占有面積が不要となり半導体スイッチ回路を小型化することができる。 As described above, in the semiconductor switch circuit 2 according to the second embodiment of the present invention, the transistors F21 to F24 are the same depletion type or enhancement type field effect transistors as the transistors F11 to F14, and one common terminal A1 ( When A2) and one terminal P1 (P2) are conducted, at least one of the two transistors F23 and F24 (F21, F22) connected in parallel to the other common terminal A2 (A1) is turned on. By controlling to be in a state, the isolation characteristic between the common terminals A1 and A2 can be improved, and further, it is configured by a field effect transistor of a different type (enhancement type or depletion type) from the transistors F11 to F14. The same type of field effect without using logic circuits Because the consist only of transistors, it is possible to reduce the manufacturing cost. In addition, since a logic circuit including a transistor having a narrow gate width is not used, resistance against ESD (electrostatic discharge) is improved, and an area occupied by the logic circuit is not required, and the semiconductor switch circuit can be downsized. .
　また、本発明の実施の形態２に係る半導体スイッチ回路２は、複数の端子に対して複数の共通端子を備えているため、複数の共通端子が必要な機器に組み込むことが可能となる。 In addition, since the semiconductor switch circuit 2 according to the second embodiment of the present invention includes a plurality of common terminals with respect to a plurality of terminals, it can be incorporated into a device that requires a plurality of common terminals.
　さらに、トランジスタＦ１１～Ｆ１４及びトランジスタＦ２１～Ｆ２４のそれぞれのゲート電極に接続されている抵抗Ｒは、全て同じ抵抗値であっても、それぞれ異なる抵抗値であっても良い。抵抗Ｒの抵抗値は、半導体スイッチ回路２が所望の動作ができる値であれば良い。また、トランジスタＦ２１～Ｆ２４のそれぞれのソース電極に接続されている容量Ｃの容量値及びインダクタＬのインダクタンスは、全て同じ値であっても、それぞれ異なる値であっても良い。容量Ｃの容量値及びインダクタＬのインダクタンスは、半導体スイッチ回路２が所望の動作ができる値であれば良い。 Further, the resistors R connected to the gate electrodes of the transistors F11 to F14 and the transistors F21 to F24 may all have the same resistance value or different resistance values. The resistance value of the resistor R may be a value that allows the semiconductor switch circuit 2 to perform a desired operation. Further, the capacitance value of the capacitor C connected to the source electrode of each of the transistors F21 to F24 and the inductance of the inductor L may be the same value or different values. The capacitance value of the capacitor C and the inductance of the inductor L may be values that allow the semiconductor switch circuit 2 to perform a desired operation.
　さらに、本発明の実施の形態２に係る半導体スイッチ回路２では、共通端子Ａ１、Ａ２のそれぞれに二つのトランジスタＦ２１とＦ２２、トランジスタＦ２３とＦ２４を並列接続しているが、共通端子Ａ１、Ａ２の間の双方向でアイソレーション特性を向上させる必要がなければ、共通端子Ａ１又は共通端子Ａ２のいずれか一方にのみ二つのトランジスタＦ２１、Ｆ２２又はトランジスタＦ２３、Ｆ２４を並列接続する構成でも良い。 Furthermore, in the semiconductor switch circuit 2 according to the second embodiment of the present invention, two transistors F21 and F22 and transistors F23 and F24 are connected in parallel to the common terminals A1 and A2, respectively. If it is not necessary to improve the isolation characteristics in both directions, two transistors F21 and F22 or transistors F23 and F24 may be connected in parallel only to either the common terminal A1 or the common terminal A2.
　（実施の形態３）
　図３は、本発明の実施の形態３に係る半導体スイッチ回路の構成例を示す回路図である。本発明の実施の形態３に係る半導体スイッチ回路３は、実施の形態１及び２の構成を組み合わせ、端子Ｐ１、Ｐ２に並列接続されたトランジスタ（第２トランジスタ）Ｆ２１～Ｆ２４と、共通端子Ａ１、Ａ２に並列接続されたトランジスタ（第３トランジスタ）Ｆ３１～Ｆ３４とを備えている。図３に示す半導体スイッチ回路３は、二つの共通端子Ａ１、Ａ２と、二つの端子Ｐ１、Ｐ２と、四つの制御端子Ｖ１、Ｖ２、Ｖ３、Ｖ４と、共通端子Ａ１、Ａ２と端子Ｐ１、Ｐ２との間に接続された四つのトランジスタ（第１トランジスタ）Ｆ１１～Ｆ１４と、端子Ｐ１に並列接続されたトランジスタ（第２トランジスタ）Ｆ２１、Ｆ２２と、端子Ｐ２に並列接続されたトランジスタ（第２トランジスタ）Ｆ２３、Ｆ２４と、共通端子Ａ１に並列接続されたトランジスタ（第３トランジスタ）Ｆ３１、Ｆ３２と、共通端子Ａ２に並列接続されたトランジスタ（第３トランジスタ）Ｆ３３、Ｆ３４とを備える。なお、半導体スイッチ回路３は、共通端子が二つ、端子が二つのＤＰＤＴ型半導体スイッチ回路の構成に限定されるものではなく、共通端子がｍ（ｍは２以上の自然数）個、端子がｎ（ｎは２以上の自然数）個のｍＰｎＴ型半導体スイッチ回路の構成であっても良い。共通端子がｍ個、端子がｎ個の構成の半導体スイッチ回路３の場合、共通端子Ａ１～Ａｍと端子Ｐ１～Ｐｎとの間に接続されるトランジスタはｍ×ｎ個、ｍ個の各共通端子Ａ１～Ａｍに並列接続されるトランジスタはｎ×（ｍ－１）個、ｎ個の各端子Ｐ１～Ｐｎに並列接続されるトランジスタはｍ×（ｎ－１）個となる。 (Embodiment 3)
FIG. 3 is a circuit diagram showing a configuration example of the semiconductor switch circuit according to the third embodiment of the present invention. The semiconductor switch circuit 3 according to the third embodiment of the present invention combines the configurations of the first and second embodiments, and includes transistors (second transistors) F21 to F24 connected in parallel to the terminals P1 and P2, and a common terminal A1, Transistors (third transistors) F31 to F34 connected in parallel to A2. The semiconductor switch circuit 3 shown in FIG. 3 includes two common terminals A1, A2, two terminals P1, P2, four control terminals V1, V2, V3, V4, common terminals A1, A2, and terminals P1, P2. Transistors (first transistors) F11 to F14 connected to each other, transistors (second transistors) F21 and F22 connected in parallel to the terminal P1, and transistors (second transistors) connected in parallel to the terminal P2 ) F23, F24, transistors (third transistors) F31, F32 connected in parallel to the common terminal A1, and transistors (third transistors) F33, F34 connected in parallel to the common terminal A2. The semiconductor switch circuit 3 is not limited to the configuration of a DPDT type semiconductor switch circuit having two common terminals and two terminals, and there are m common terminals (m is a natural number of 2 or more) and n terminals. It may be a configuration of mPnT type semiconductor switch circuits (n is a natural number of 2 or more). In the case of the semiconductor switch circuit 3 having a configuration with m common terminals and n terminals, m × n transistors and m common terminals are connected between the common terminals A1 to Am and the terminals P1 to Pn. There are n × (m−1) transistors connected in parallel to A1 to Am, and m × (n−1) transistors connected in parallel to the n terminals P1 to Pn.
　トランジスタＦ１１～Ｆ１４の接続は、図１に示す実施の形態１に係る半導体スイッチ回路１のトランジスタＦ１１～Ｆ１４の接続と同じであるため、詳細な説明は省略する。また、トランジスタＦ２１～Ｆ２４の接続は、図１に示す実施の形態１に係る半導体スイッチ回路１のトランジスタＦ２１～Ｆ２４の接続と同じであるため、詳細な説明は省略する。さらに、トランジスタ（シャントＦＥＴ）Ｆ３１～Ｆ３４の接続は、図２に示す実施の形態２に係る半導体スイッチ回路２のトランジスタＦ２１～Ｆ２４の接続と同じであるため、詳細な説明は省略する。 Since the connections of the transistors F11 to F14 are the same as the connections of the transistors F11 to F14 of the semiconductor switch circuit 1 according to the first embodiment shown in FIG. 1, detailed description thereof is omitted. Further, since the connections of the transistors F21 to F24 are the same as the connections of the transistors F21 to F24 of the semiconductor switch circuit 1 according to the first embodiment shown in FIG. 1, detailed description thereof is omitted. Furthermore, since the connections of the transistors (shunt FETs) F31 to F34 are the same as the connections of the transistors F21 to F24 of the semiconductor switch circuit 2 according to the second embodiment shown in FIG.
　次に、本発明の実施の形態３に係る半導体スイッチ回路３の動作について説明する。半導体スイッチ回路３は、前述の（表２）に示すように制御端子Ｖ１～Ｖ４にハイレベル（Ｈ）又はローレベル（Ｌ）の電位の制御電圧を供給することで、共通端子Ａ１、Ａ２と、端子Ｐ１、Ｐ２とが導通するように制御することができる。 Next, the operation of the semiconductor switch circuit 3 according to the third embodiment of the present invention will be described. As shown in Table 2 above, the semiconductor switch circuit 3 supplies a control voltage having a high level (H) or low level (L) potential to the control terminals V1 to V4, so that the common terminals A1, A2 and The terminals P1 and P2 can be controlled to conduct.
　（表２）に示すように、制御端子Ｖ１にハイレベルの電位の制御電圧が、制御端子Ｖ２～Ｖ４にローレベルの電位の制御電圧が、それぞれ供給された場合、トランジスタＦ１１がオン状態、トランジスタＦ１２～Ｆ１４及びトランジスタＦ２１、Ｆ２２、Ｆ２４、トランジスタＦ３１、Ｆ３２、Ｆ３４がオフ状態となるので、共通端子Ａ１と、端子Ｐ１とが導通する。このとき、トランジスタＦ２３、トランジスタＦ３３がオン状態となるので、不要な高周波信号を共通端子Ａ２及び端子Ｐ２に流すことなく接地端子に流すことができる。制御端子Ｖ２にハイレベルの電位の制御電圧が、制御端子Ｖ１、Ｖ３、Ｖ４にローレベルの電位の制御電圧が、それぞれ供給された場合、トランジスタＦ１２がオン状態、トランジスタＦ１１、Ｆ１３、Ｆ１４及びトランジスタＦ２１～Ｆ２３、トランジスタＦ３１、Ｆ３３、Ｆ３４がオフ状態となるので、共通端子Ａ２と、端子Ｐ１とが導通する。このとき、トランジスタＦ２４、Ｆ３２がオン状態となるので、不要な高周波信号を共通端子Ａ１及び端子Ｐ２に流すことなく接地端子に流すことができる。 As shown in Table 2, when a control voltage having a high level potential is supplied to the control terminal V1 and a control voltage having a low level potential is supplied to the control terminals V2 to V4, the transistor F11 is turned on. Since the transistors F12 to F14, the transistors F21, F22, and F24 and the transistors F31, F32, and F34 are turned off, the common terminal A1 and the terminal P1 are brought into conduction. At this time, since the transistor F23 and the transistor F33 are turned on, an unnecessary high-frequency signal can be supplied to the ground terminal without flowing to the common terminal A2 and the terminal P2. When a control voltage having a high level potential is supplied to the control terminal V2 and a control voltage having a low level potential is supplied to the control terminals V1, V3, and V4, the transistor F12 is turned on, the transistors F11, F13, and F14, and the transistor Since F21 to F23 and the transistors F31, F33, and F34 are turned off, the common terminal A2 and the terminal P1 are brought into conduction. At this time, since the transistors F24 and F32 are turned on, an unnecessary high-frequency signal can be supplied to the ground terminal without flowing to the common terminal A1 and the terminal P2.
　制御端子Ｖ３にハイレベルの電位の制御電圧が、制御端子Ｖ１、Ｖ２、Ｖ４にローレベルの電位の制御電圧が、それぞれ供給された場合、トランジスタＦ１３がオン状態、トランジスタＦ１１、Ｆ１２、Ｆ１４及びトランジスタＦ２２～Ｆ２４、トランジスタＦ３１～Ｆ３３がオフ状態となるので、共通端子Ａ１と、端子Ｐ２とが導通する。このとき、トランジスタＦ２１、トランジスタＦ３４がオン状態となるので、不要な高周波信号を共通端子Ａ２及び端子Ｐ１に流すことなく接地端子に流すことができる。制御端子Ｖ４にハイレベルの電位の制御電圧が、制御端子Ｖ１～Ｖ３にローレベルの電位の制御電圧が、それぞれ供給された場合、トランジスタＦ１４がオン状態、トランジスタＦ１１～Ｆ１３及びトランジスタＦ２１、Ｆ２３、Ｆ２４、トランジスタＦ３２～Ｆ３４がオフ状態となるので、共通端子Ａ２と、端子Ｐ２とが導通する。このとき、トランジスタＦ２２、トランジスタＦ３１がオン状態となるので、不要な高周波信号を共通端子Ａ１及び端子Ｐ１に流すことなく接地端子に流すことができる。 When a control voltage having a high level potential is supplied to the control terminal V3 and a control voltage having a low level potential is supplied to the control terminals V1, V2, and V4, the transistor F13 is turned on, the transistors F11, F12, F14, and the transistor Since F22 to F24 and transistors F31 to F33 are turned off, the common terminal A1 and the terminal P2 are brought into conduction. At this time, since the transistor F21 and the transistor F34 are turned on, an unnecessary high-frequency signal can be supplied to the ground terminal without flowing to the common terminal A2 and the terminal P1. When a control voltage having a high level potential is supplied to the control terminal V4 and a control voltage having a low level potential is supplied to the control terminals V1 to V3, the transistor F14 is turned on, the transistors F11 to F13, and the transistors F21, F23, Since F24 and the transistors F32 to F34 are turned off, the common terminal A2 and the terminal P2 are brought into conduction. At this time, since the transistor F22 and the transistor F31 are turned on, an unnecessary high frequency signal can be supplied to the ground terminal without flowing to the common terminal A1 and the terminal P1.
　半導体スイッチ回路３では、一つの共通端子（例えばＡ１）と、一つの端子（例えばＰ１）とが導通する場合、他の端子（例えばＰ２）に並列接続された二つのトランジスタＦ２３、Ｆ２４のうち、少なくとも一つのトランジスタ（例えばＦ２３）がオン状態、他の共通端子（例えばＡ２）に並列接続された二つのトランジスタＦ３３、Ｆ３４のうち、少なくとも一つのトランジスタ（例えばＦ３３）がオン状態となるように制御されている。そのため、トランジスタＦ２３、トランジスタＦ３３は、不要な高周波信号を共通端子Ａ２及び端子Ｐ２に流すことなく接地端子に流すことができ、共通端子Ａ１、Ａ２の間、及び端子Ｐ１、Ｐ２の間のアイソレーション特性を向上させることができる。 In the semiconductor switch circuit 3, when one common terminal (for example, A1) and one terminal (for example, P1) conduct, among the two transistors F23 and F24 connected in parallel to the other terminal (for example, P2), Control is performed so that at least one transistor (for example, F23) is turned on, and at least one of the two transistors F33 and F34 connected in parallel to the other common terminal (for example, A2) is turned on. Has been. Therefore, the transistor F23 and the transistor F33 can flow an unnecessary high-frequency signal to the ground terminal without flowing to the common terminal A2 and the terminal P2, and the isolation between the common terminals A1 and A2 and between the terminals P1 and P2. Characteristics can be improved.
　以上のように、本発明の実施の形態３に係る半導体スイッチ回路３は、トランジスタＦ２１～Ｆ２４、Ｆ３１～Ｆ３４が、トランジスタＦ１１～Ｆ１４と同じ型の電界効果トランジスタであり、一つの共通端子Ａ１（Ａ２）と、一つの端子Ｐ１（Ｐ２）とが導通する場合、他の共通端子Ａ２（Ａ１）に並列接続された二つのトランジスタＦ３３、Ｆ３４（Ｆ３１、Ｆ３２）のうち、少なくとも一つのトランジスタがオン状態、他の端子Ｐ２（Ｐ１）に並列接続された二つのトランジスタＦ２３、Ｆ２４（Ｆ２１、Ｆ２２）のうち、少なくとも一つのトランジスタがオン状態となるように制御することで、共通端子Ａ１、Ａ２の間、及び端子Ｐ１、Ｐ２の間のアイソレーション特性を向上させることができ、さらにトランジスタＦ１１～Ｆ１４及びトランジスタＦ２１～Ｆ２４と異なる型（エンハンスメント型又はディプレッション型）の電界効果トランジスタで構成されるロジック回路を用いることなく、同じ型の電界効果トランジスタのみで構成されるので、製造コストを低減することができる。また、ゲート幅が狭い電界効果トランジスタで構成されるロジック回路を用いることがないため、ＥＳＤ（静電気放電）に対する耐性が向上するとともに、ロジック回路の占有面積が不要となり半導体スイッチ回路を小型化することができる。 As described above, in the semiconductor switch circuit 3 according to the third embodiment of the present invention, the transistors F21 to F24 and F31 to F34 are field effect transistors of the same type as the transistors F11 to F14, and one common terminal A1 ( When A2) and one terminal P1 (P2) are conducted, at least one of the two transistors F33 and F34 (F31, F32) connected in parallel to the other common terminal A2 (A1) is turned on. By controlling so that at least one of the two transistors F23 and F24 (F21 and F22) connected in parallel to the other terminal P2 (P1) is turned on, the common terminals A1 and A2 And the isolation characteristics between the terminals P1 and P2, and the transistors F11 to F1 In addition, since it is composed of only the same type of field effect transistors without using a logic circuit composed of field effect transistors of a different type (enhancement type or depletion type) from the transistors F21 to F24, the manufacturing cost can be reduced. it can. In addition, since a logic circuit composed of a field effect transistor having a narrow gate width is not used, resistance against ESD (electrostatic discharge) is improved, and the area occupied by the logic circuit is not required, and the semiconductor switch circuit is miniaturized. Can do.
　また、本発明の実施の形態３に係る半導体スイッチ回路３は、複数の端子に対して複数の共通端子を備えているため、複数の共通端子が必要な機器に組み込むことが可能となる。 In addition, since the semiconductor switch circuit 3 according to the third embodiment of the present invention includes a plurality of common terminals with respect to a plurality of terminals, it can be incorporated into a device that requires a plurality of common terminals.
　さらに、トランジスタＦ１１～Ｆ１４、トランジスタＦ２１～Ｆ２４、及びトランジスタＦ３１～Ｆ３４のそれぞれのゲート電極に接続されている抵抗Ｒは、全て同じ抵抗値であっても、それぞれ異なる抵抗値であっても良い。抵抗Ｒの抵抗値は、半導体スイッチ回路３が所望の動作ができる値であれば良い。また、トランジスタＦ２１～Ｆ２４、トランジスタＦ３１～Ｆ３４のそれぞれのソース電極に接続されている容量Ｃの容量値及びインダクタＬのインダクタンスは、全て同じ値であっても、それぞれ異なる値であっても良い。容量Ｃの容量値及びインダクタＬのインダクタンスも、半導体スイッチ回路３が所望の動作ができる値であれば良い。 Furthermore, the resistors R connected to the gate electrodes of the transistors F11 to F14, the transistors F21 to F24, and the transistors F31 to F34 may all have the same resistance value or different resistance values. The resistance value of the resistor R may be a value that allows the semiconductor switch circuit 3 to perform a desired operation. The capacitance value of the capacitor C connected to the source electrode of each of the transistors F21 to F24 and the transistors F31 to F34 and the inductance of the inductor L may all be the same value or may be different values. The capacitance value of the capacitor C and the inductance of the inductor L may be values that allow the semiconductor switch circuit 3 to perform a desired operation.
　さらに、本発明の実施の形態３に係る半導体スイッチ回路３では、共通端子Ａ１、Ａ２及び端子Ｐ１、Ｐ２のそれぞれに二つのトランジスタＦ３１とＦ３２、トランジスタＦ３３とＦ３４、トランジスタＦ２１とＦ２２、トランジスタＦ２３とＦ２４を並列接続しているが、共通端子Ａ１、Ａ２の間の双方向でアイソレーション特性を向上させる必要がなければ、共通端子Ａ１又は共通端子Ａ２のいずれか一方にのみ二つのトランジスタＦ３１、Ｆ３２又はトランジスタＦ３３、Ｆ３４を並列接続する構成でも良く、また端子Ｐ１、Ｐ２の間の双方向でアイソレーション特性を向上させる必要がなければ、端子Ｐ１又は端子Ｐ２のいずれか一方にのみ二つのトランジスタＦ２１、Ｆ２２又はトランジスタＦ２３、Ｆ２４を並列接続する構成でも良い。 Furthermore, in the semiconductor switch circuit 3 according to the third embodiment of the present invention, two transistors F31 and F32, transistors F33 and F34, transistors F21 and F22, transistors F23 and F2 are connected to the common terminals A1 and A2 and terminals P1 and P2, respectively. Although F24 is connected in parallel, if it is not necessary to improve the isolation characteristics in both directions between the common terminals A1 and A2, the two transistors F31 and F32 are provided only in either the common terminal A1 or the common terminal A2. Alternatively, the transistors F33 and F34 may be connected in parallel, and if it is not necessary to improve the isolation characteristics in both directions between the terminals P1 and P2, the two transistors F21 are provided only at either the terminal P1 or the terminal P2. F22 or transistors F23 and F24 connected in parallel It may be.
　なお、本発明は上記実施例に限定されるものではなく、本発明の趣旨の範囲内であれば多種の変形、置換等が可能であることは言うまでもない。 It should be noted that the present invention is not limited to the above-described embodiments, and it goes without saying that various modifications and substitutions are possible within the scope of the present invention.
　１、２、３　半導体スイッチ回路
　Ａ１、Ａ２　共通端子
　Ｐ１、Ｐ２　端子
　Ｆ１１～Ｆ１４、Ｆ２１～Ｆ２４、Ｆ３１～Ｆ３４　トランジスタ 1, 2, 3 Semiconductor switch circuit A1, A2 Common terminal P1, P2 terminal F11 to F14, F21 to F24, F31 to F34 Transistors

Claims (7)

  1. 　第１乃至第ｍ（ｍは２以上の自然数）の共通端子と、
    　第１乃至第ｎ（ｎは２以上の自然数）の端子と、
    　第１乃至第ｍの前記共通端子と第１乃至第ｎの前記端子との間に接続され、一の共通端子と、一の端子とが導通するように制御することが可能なｍ×ｎ個の第１トランジスタと、
    　少なくとも一の端子に並列接続されたｍ×（ｎ－１）個の第２トランジスタと
    　を備え、
    　前記第１トランジスタ及び前記第２トランジスタは、同じディプレッション型又は同じエンハンスメント型の電界効果トランジスタであり、
    　一の共通端子と、一の端子とが導通する場合、他の端子に並列接続された第２トランジスタのうち、少なくとも一の第２トランジスタがオン状態となるように制御することを特徴とする半導体スイッチ回路。     First to m-th (m is a natural number of 2 or more) common terminals;
    First to nth (n is a natural number of 2 or more) terminals;
    M × n connected between the first to m-th common terminals and the first to n-th terminals, and can be controlled so that one common terminal and one terminal are conductive. A first transistor of
    And m × (n−1) second transistors connected in parallel to at least one terminal,
    The first transistor and the second transistor are field effect transistors of the same depletion type or the same enhancement type,
    A semiconductor characterized in that when one common terminal and one terminal are electrically connected, at least one second transistor is controlled to be in an on state among second transistors connected in parallel to the other terminal. Switch circuit.
  2. 　前記第２トランジスタは、共振回路を介して接地端子に接続されていることを特徴とする請求項１に記載の半導体スイッチ回路。 The semiconductor switch circuit according to claim 1, wherein the second transistor is connected to a ground terminal via a resonance circuit.
  3. 　少なくとも一の共通端子に並列接続されたｎ×（ｍ－１）個の第３トランジスタをさらに備え、
    　前記第３トランジスタは、前記第１トランジスタ及び前記第２トランジスタと同じ型の電界効果トランジスタであり、
    　一の共通端子と一の端子とが導通する場合、他の共通端子に並列接続された第３トランジスタのうち、少なくとも一の第３トランジスタがオン状態となるように制御することを特徴とする請求項１又は２に記載の半導体スイッチ回路。     Further comprising n × (m−1) third transistors connected in parallel to at least one common terminal;
    The third transistor is a field effect transistor of the same type as the first transistor and the second transistor;
    When one common terminal and one terminal are electrically connected, control is performed such that at least one third transistor is turned on among the third transistors connected in parallel to the other common terminal. Item 3. The semiconductor switch circuit according to Item 1 or 2.
  4. 　前記第３トランジスタは、共振回路を介して接地端子に接続されていることを特徴とする請求項３に記載の半導体スイッチ回路。 4. The semiconductor switch circuit according to claim 3, wherein the third transistor is connected to a ground terminal via a resonance circuit.
  5. 　第１乃至第ｍ（ｍは２以上の自然数）の共通端子と、
    　第１乃至第ｎ（ｎは２以上の自然数）の端子と、
    　第１乃至第ｍの前記共通端子と第１乃至第ｎの前記端子との間に接続され、一の共通端子と一の端子とが導通するように制御することが可能なｍ×ｎ個の第１トランジスタと、
    　少なくとも一の共通端子に並列接続されたｎ×（ｍ－１）個の第２トランジスタと
    　を備え、
    　前記第１トランジスタ及び前記第２トランジスタは、同じディプレッション型又は同じエンハンスメント型の電界効果トランジスタであり、
    　一の共通端子と一の端子とが導通する場合、他の共通端子に並列接続された第２トランジスタのうち、少なくとも一の第２トランジスタがオン状態となるように制御することを特徴とする半導体スイッチ回路。     First to m-th (m is a natural number of 2 or more) common terminals;
    First to nth (n is a natural number of 2 or more) terminals;
    M × n connected between the first to m-th common terminals and the first to n-th terminals, and can be controlled so that one common terminal and one terminal are conductive. A first transistor;
    And n × (m−1) second transistors connected in parallel to at least one common terminal,
    The first transistor and the second transistor are field effect transistors of the same depletion type or the same enhancement type,
    When one common terminal is electrically connected to one terminal, a semiconductor is controlled so that at least one second transistor is turned on among second transistors connected in parallel to the other common terminal Switch circuit.
  6. 　前記第２トランジスタは、共振回路を介して接地端子に接続されていることを特徴とする請求項５に記載の半導体スイッチ回路。 6. The semiconductor switch circuit according to claim 5, wherein the second transistor is connected to a ground terminal via a resonance circuit.
  7. 　前記第１乃至第３トランジスタは、ディプレッション型の電界効果トランジスタであることを特徴とする請求項１乃至６のいずれか一項に記載の半導体スイッチ回路。 The semiconductor switch circuit according to any one of claims 1 to 6, wherein the first to third transistors are depletion type field effect transistors.
PCT/JP2011/067244 2010-08-18 2011-07-28 Semiconductor switch circuit WO2012023401A1 (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0955682A (en) * 1995-08-10 1997-02-25 Sony Corp Switch semiconductor integrated circuit and communication terminal equipment
JP2000341105A (en) * 1999-05-27 2000-12-08 Nec Kansai Ltd High frequency changeover switching circuit ic
JP2002043911A (en) * 2000-07-27 2002-02-08 Murata Mfg Co Ltd Semiconductor switch circuit and semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0955682A (en) * 1995-08-10 1997-02-25 Sony Corp Switch semiconductor integrated circuit and communication terminal equipment
JP2000341105A (en) * 1999-05-27 2000-12-08 Nec Kansai Ltd High frequency changeover switching circuit ic
JP2002043911A (en) * 2000-07-27 2002-02-08 Murata Mfg Co Ltd Semiconductor switch circuit and semiconductor device

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