WO2012003685A1 - Circuit for improving voltage-resistance of devices - Google Patents

Circuit for improving voltage-resistance of devices Download PDF

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Publication number
WO2012003685A1
WO2012003685A1 PCT/CN2010/078657 CN2010078657W WO2012003685A1 WO 2012003685 A1 WO2012003685 A1 WO 2012003685A1 CN 2010078657 W CN2010078657 W CN 2010078657W WO 2012003685 A1 WO2012003685 A1 WO 2012003685A1
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WO
WIPO (PCT)
Prior art keywords
circuit
tube
source
voltage
diode
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Application number
PCT/CN2010/078657
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French (fr)
Chinese (zh)
Inventor
葛良安
姜德来
Original Assignee
英飞特电子（杭州）有限公司
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Publication of WO2012003685A1 publication Critical patent/WO2012003685A1/en

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Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0048—Circuits or arrangements for reducing losses
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33507—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters
    • H02M3/33523—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters with galvanic isolation between input and output of both the power stage and the feedback loop
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • the present invention relates to the field of power electronics, and in particular to a circuit for improving the withstand voltage of a device.
  • the design of a suitable switching power supply can encounter difficulties in selecting high-voltage transistor switching devices.
  • the traditional switching power supply design requires the use of a transistor with a withstand voltage of 1000V or higher as the switching device.
  • transistors with a withstand voltage of 1000V or more are relatively special devices, which will cause difficulty in selection and high cost.
  • FIG. 1 the figure is a circuit diagram for improving the withstand voltage of the device provided in the prior art.
  • two NMOS transistors Q1 and Q2 are connected in series to provide withstand voltage capability.
  • the lower tube Q1 is directly driven by the PWM control circuit.
  • Q1 When Q1 is turned from on to off, the drain and source of Q1. The voltage between the poles rises.
  • the voltage between the drain and the source of Q1 approaches the voltage of the Zener diode ZD1, the voltage between the gate and the source of the upper transistor Q2 will be lower than the turn-on threshold voltage. Therefore, Q2 also enters the off state.
  • the voltage shared by Q1 is determined by the regulation value of Zener ZD1.
  • the voltage between the drain and source drops, and resistor R1 supplies the drive current to Q2, which turns Q2 on.
  • the driving energy for the upper tube Q2 is the energy of the resistor R1 taken from the input voltage Vin. Since the input voltage Vin is high voltage (usually higher than the grid voltage), R1 is subject to its own power consumption. The limitation is that it can not provide a large driving current when Q2 is turned on. This will make the conduction speed of Q2 slow, and the switching loss and conduction loss of Q2 are large. Therefore, the efficiency of this circuit is low, and it is usually only applicable to power. Small occasions.
  • the circuit provided in Fig. 2 (Application No. 200810028422.4 of Chinese Patent Application) is similar to the circuit shown in Fig. 1.
  • the circuit shown in Fig. 2 has a capacitor C2 connected in parallel with the Zener diode D4. When C2 is turned on, C2 discharge can improve the driving of the upper tube Q1.
  • the resistor R4 and the diode D3 are connected in series between the gate and the source of Q1 in place of the Zener diode ZD2 in FIG.
  • the driving energy for the upper tube Q1 is the energy of the resistor R1 taken from the input voltage Vin. Since the input voltage Vin is high voltage (usually higher than the grid voltage), the resistor R1 is subject to its own power consumption. The limit does not provide a large drive current for Q1 turn-on; when the down transistor Q2 turns off, the Q2 drain voltage rises and C2 charges until the voltage across the terminals reaches the regulated value of D4 (usually a few hundred volts); When the switching transistors Q1 and Q2 are turned on, the capacitor C2 will discharge through the gate of Q1 until it is equal to the gate driving voltage of the switching transistor Q1 (ten volts). Although the discharge of C2 can improve the driving capability of Q1, but during the switching process In the charge and discharge, there will be a large loss. Therefore, the circuit can be applied to a higher power level than the circuit shown in Fig. 1, but the efficiency is still low.
  • the circuit shown in Figure 3 has the following disadvantages: although the ability to drive the upper tube SW2 is improved, the device that drives SW2 is the capacitor CB1.
  • the capacitor CB1 and the capacitor CB2 are still charged and discharged at a high voltage. Therefore, the capacitor CB1 provides a driving energy to the upper tube SW2, and a large loss occurs in the balance process of the CB1 and CB2 voltages.
  • the technical problem to be solved by the present invention is to provide a circuit for improving the withstand voltage of a device, which can improve the withstand voltage capability of the device and reduce the loss of the circuit.
  • Embodiments of the present invention provide a circuit for improving a withstand voltage of a device, including: a first voltage stabilizing device, a first diode, an upper NMOS transistor, and a lower NMOS transistor;
  • the gate of the upper NMOS transistor is connected to the cathode of the first diode, the anode of the first diode is connected to the positive terminal of the power supply, and the negative terminal of the power supply is connected to the source of the lower NMOS transistor; the gate of the upper NMOS transistor passes through the first stable The voltage device is connected to the source of the NMOS transistor;
  • the source of the upper NMOS transistor is connected to the drain of the NMOS transistor
  • a drain of the upper NMOS transistor and a gate of the lower NMOS transistor respectively serve as a first output of the circuit and a first input;
  • a source of the lower NMOS transistor serves as a common terminal of the second input and the second output of the circuit.
  • a first capacitor connected between the positive terminal and the negative terminal of the power source is further included.
  • the first voltage stabilizing device is a Zener diode, or a transient voltage suppression diode TVS.
  • a clamp protection module is further coupled between the gate and the source of the upper NMOS transistor.
  • the clamp protection module is a Zener diode or a transient voltage suppression diode TVS.
  • the circuit is packaged into a single semiconductor device including four pins or pins, and the four pins or pins are respectively the first input terminal, the first output terminal, and the power supply positive terminal. And a common end of the second input of the second input.
  • the circuit acts as a switching transistor connected to the primary winding in the flyback circuit.
  • the circuit acts as a switching tube in the BUCK circuit.
  • the circuit acts as a switching tube in the BOOST circuit.
  • the invention provides a circuit for improving the withstand voltage of a device, comprising: a first voltage stabilizing device, a first diode, an upper IGBT tube and a lower IGBT tube;
  • the gate of the upper IGBT tube is connected to the cathode of the first diode, the anode of the first diode is connected to the positive end of the power source, and the negative end of the power source is connected to the source of the IGBT tube; the gate of the upper IGBT tube passes through the first stable Pressing the device to connect the source of the IGBT tube;
  • the source of the upper IGBT tube is connected to the drain of the IGBT tube
  • the drain of the upper IGBT tube and the gate of the lower IGBT tube respectively serve as a first output end and a first input end of the circuit;
  • the source of the lower IGBT transistor serves as the common terminal of the second input and the second output of the circuit.
  • a first capacitor connected between the positive terminal and the negative terminal of the power source is further included.
  • the first voltage stabilizing device is a Zener diode, or a transient voltage suppression diode TVS.
  • a clamp protection module is also provided in parallel between the gate and the emitter of the upper IGBT tube.
  • the clamp protection module is a Zener diode or a transient voltage suppression diode TVS.
  • the circuit is packaged into a single semiconductor device including four pins or pins, and the four pins or pins are respectively the first input terminal, the first output terminal, and the power supply positive terminal. And a common end of the second input of the second input.
  • the circuit acts as a switching transistor connected to the primary winding in the flyback circuit.
  • the circuit acts as a switching transistor in the BUCK circuit.
  • the circuit acts as a switching tube in the BOOST circuit.
  • the present invention has the following advantages:
  • the circuit for improving the withstand voltage of the device provided by the present invention provides the driving voltage supplied to the upper NMOS transistor directly from the power source, so that no conversion circuit is required.
  • the power supply only needs to provide the driving energy required when the upper NMOS transistor is turned on, and there is no other loss; when the lower NMOS transistor is turned off, the first diode supplies the power supply and the first voltage stabilizing device. Separate, so no additional losses are incurred. Therefore, the circuit provided by the embodiment of the invention can reduce the loss.
  • FIG. 1 is a circuit diagram of improving the withstand voltage of a device provided in the prior art
  • FIG. 2 is a circuit diagram of another method for improving the withstand voltage of a device provided in the prior art
  • FIG. 3 is another circuit diagram for improving the withstand voltage of the device provided in the prior art
  • Embodiment 1 of the present invention is a circuit diagram of Embodiment 1 of the present invention.
  • Embodiment 5 is a circuit for improving the withstand voltage of a device according to Embodiment 2 of the present invention.
  • Figure 6 is an application circuit of the circuit provided by the present invention.
  • Figure 7 is still another application circuit of the circuit provided by the present invention.
  • Figure 8 is another application circuit of the circuit provided by the present invention.
  • FIG. 4 the figure is a circuit diagram of Embodiment 1 of the present invention.
  • the circuit for improving the withstand voltage of the device includes: a first voltage stabilizing device, a first diode D1, an upper NMOS transistor Q2, and a lower NMOS transistor Q1;
  • the gate of the upper NMOS transistor Q2 is connected to the cathode of the first diode D1, the anode of the first diode D1 is connected to the positive terminal of the power supply, the negative terminal of the power supply is connected to the source of the lower NMOS transistor Q1; the gate of the upper NMOS transistor Q2 is passed
  • the first voltage stabilizing device is connected to the source of the NMOS transistor Q1;
  • the source of the upper NMOS transistor Q2 is connected to the drain of the NMOS transistor Q1;
  • the drain of the upper NMOS transistor Q2 and the gate of the lower NMOS transistor Q1 serve as a first output terminal and a first input terminal of the circuit, respectively; the source of the lower NMOS transistor Q1 serves as a second input terminal and a second of the circuit.
  • the source of the lower NMOS transistor Q1 serves as both the second output of the circuit and the second input of the circuit. Therefore, for the circuit as a whole, the second input and the second output The end is a public end.
  • the input signal Vd at the input end may be a pulse driving signal, and the pulse driving signal may be a PWM signal, or a PFM signal, or a PWM+PFM signal.
  • circuit shown in Fig. 4 may further include a first capacitor C1 connected between the positive terminal of the power supply (Vcc) and the negative terminal of the power supply (the common terminal of the second input terminal and the second output terminal).
  • the first voltage stabilizing device is preferably a Zener diode (such as the Zener diode ZD1 shown in FIG. 4), and the first voltage stabilizing device may also be a Transient Voltage Suppressor (TVS). Or other devices that limit voltage, etc.
  • Zener diode such as the Zener diode ZD1 shown in FIG. 4
  • TVS Transient Voltage Suppressor
  • the lower NMOS transistor Q1 is directly driven by the pulse driving signal control circuit, wherein Vd is a pulse driving signal.
  • the driving voltage of Q2 is directly from Vcc, and does not require any conversion circuit.
  • Vcc only provides the energy required for gate conduction driving, and there is no other loss;
  • Q1 is turned off, the first Diode D1 separates Vcc from Zener ZD1 and does not create additional losses. Therefore, the circuit provided by the embodiment of the present invention can reduce the loss.
  • the circuit within the dashed box can be packaged into a single semiconductor that includes four pins or pins.
  • the four pins or pins are the first pin, the second pin, the third pin and the fourth pin, respectively, which are described in detail below with reference to the accompanying drawings.
  • the first pin 1 (ie, the common terminal of the second input terminal and the second output terminal of the circuit) is the low voltage terminal of the independent semiconductor device
  • the second pin 2 (ie, the first input of the circuit)
  • the terminal is the driving terminal (Vd) of the individual semiconductor device
  • the third pin 3 (ie, the first output of the circuit) is the high voltage terminal of the independent semiconductor device
  • the fourth pin 4 is the power terminal (Vcc).
  • the individual semiconductor device can be used to replace a switching transistor (such as a MOS transistor or an IGBT) in a circuit, especially a high voltage device.
  • a switching transistor such as a MOS transistor or an IGBT
  • the first pin, the second pin, and the third pin of the device correspond to the source, gate, and drain of the MOS transistor, respectively.
  • the first, second, and third pins of the device correspond to the emitter, gate, and collector of the IGBT, respectively.
  • the switch can replace power devices that correspond to other alternative MOSFETs or IGBTs.
  • a DC voltage source Vcc needs to be connected between the fourth pin and the first pin.
  • the reference ground of the power supply terminal (Vcc) and the driver terminal (Vd) is the first pin of the device.
  • the embodiment of the present invention further provides a circuit for improving the withstand voltage of a device.
  • the figure is a circuit for improving the withstand voltage of the device according to the second embodiment of the present invention.
  • the circuit for improving the withstand voltage of the device provided by this embodiment differs from the first embodiment in that the clamp protection module is added.
  • the clamp protection module is connected in parallel between the gate and source of Q2 to clamp the gate voltage of Q2 within a safe range.
  • the clamp protection module can be a voltage regulator tube, or a TVS tube, etc.
  • the clamp protection module in this embodiment is a voltage regulator tube, such as the second voltage regulator tube ZD2 shown in FIG.
  • the embodiment shown in FIG. 5 can also package the circuit in the virtual frame into a single semiconductor device including four pins or pins, and the corresponding relationship between the package device and the switch tube and the corresponding relationship in FIG. The same, will not be described here.
  • the upper tube and the lower tube in the circuit for improving the withstand voltage of the device provided by the above embodiments are both NMOS tubes. It can be understood that the upper tube and the lower tube can also be IGBT tubes, except that the upper tube and the lower tube are different. In addition, the circuits in other parts are the same. Therefore, its working principle will not be described here.
  • the circuit for improving the withstand voltage of the device includes: a first voltage stabilizing device, a first diode, an upper IGBT tube and a lower IGBT tube;
  • the gate of the upper IGBT tube is connected to the cathode of the first diode, the anode of the first diode is connected to the positive end of the power supply, and the negative end of the power supply is connected to the source of the IGBT tube;
  • the gate of the upper IGBT tube passes through the first voltage stabilizing device Connect the source of the IGBT tube;
  • the drain of the upper IGBT tube and the gate of the lower IGBT tube respectively serve as a first output end and a first input end of the circuit;
  • the source of the lower IGBT transistor serves as the common terminal of the second input and the second output of the circuit.
  • the above-mentioned improved device withstand voltage circuit may further include a first capacitor connected between the positive terminal of the power supply (Vcc) and the negative terminal of the power supply (the common terminal of the second input terminal and the second output terminal).
  • the first voltage stabilizing device may be a Zener diode, or may be a TVS tube (ie, a transient voltage suppression diode), or other voltage limiting device.
  • circuit for improving the withstand voltage of the device provided by all the above embodiments of the present invention can be used as a single semiconductor device as a whole. Several typical applications of this circuit as stand-alone semiconductor devices are described below.
  • FIG. 6 the figure shows an application circuit of the circuit provided by the present invention.
  • the circuit or the individual semiconductor device provided by the present invention is applied to the flyback circuit in this embodiment.
  • the circuit for improving the withstand voltage of the device provided by the present invention is used as an independent switching device.
  • the first output end of the circuit is connected to the same name end of the primary winding of the transformer T1.
  • the positive terminal of the input voltage Vin of the flyback circuit is connected to the non-identical end of the primary winding
  • the negative terminal is connected to the common end of the second input end and the second output end of the circuit of the present invention
  • the same name end of the secondary winding of the transformer T1 passes the second second
  • the pole tube D2 is connected to the positive terminal of the output
  • the non-identical end of the secondary winding of the transformer T1 is connected to the negative terminal of the flyback circuit.
  • a second capacitor C2 is connected in parallel between the forward output of the flyback circuit and the negative terminal of the output.
  • a typical application of a flyback circuit is in a switching power supply with an input voltage of Vin and an output voltage of Vo. If the input voltage Vin is large, the voltage resistance of the switch tube is required to be high and the withstand voltage is high.
  • this figure is yet another application circuit of the circuit provided by the present invention.
  • the circuit or the independent semiconductor device provided by the present invention is applied to the BUCK circuit in this embodiment.
  • the circuit for improving the withstand voltage of the device provided by the present invention is used as a separate switching device, and the first output end of the circuit is connected to the second diode D2 in the BUCK circuit.
  • the anode, the common input of the second input end and the second output end of the circuit is connected to the BUCK electric The negative terminal of the input voltage Vin.
  • the cathode of the second diode D2 is connected to the positive terminal of the input voltage Vin and the positive terminal of the output voltage Vo, the anode is also connected to one end of the first inductor L1, and the other end of the first inductor L1 is connected to the negative terminal of the output voltage Vo, the output voltage A second capacitor C2 is connected in parallel between the positive and negative ends of Vo.
  • this figure is yet another application circuit of the circuit provided by the present invention.
  • the circuit or individual semiconductor device provided by the present invention is applied to the BOOST circuit in this embodiment.
  • a circuit for providing a device withstand voltage provided by the present invention which is used as a separate switching device as a whole, and the first output end of the circuit is connected to the second diode in the BOOST circuit.
  • the anode, the common end of the second input end and the second output end of the circuit is connected to the input voltage Vin negative end of the BOOST circuit and the negative end of the output voltage Vo.
  • the anode of the second diode D2 is connected to the positive terminal of the input voltage Vin through the first inductor L1, and the cathode is connected to the positive terminal of the output voltage Vo.
  • the second capacitor C2 is connected in parallel between the positive and negative terminals of the output voltage Vo.
  • the circuit or the independent semiconductor device provided by the embodiment of the invention connects the two switch tubes in series to improve the withstand voltage capability, and has a simple circuit structure and low power consumption; when used as a separate semiconductor package device in a switching power supply product, Save costs and increase product reliability.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Electronic Switches (AREA)
  • Dc-Dc Converters (AREA)

Abstract

A circuit for improving voltage-resistance of devices includes a first regulator (ZD1), a first diode (D1), an upper NMOS (Q2) and a lower NMOS (Q1). The gate of the upper NMOS (Q2) is connected to the cathode of the first diode (D1). The anode of the first diode (D1) is connected to the positive terminal of a power source (Vcc). The negative terminal of the power source (Vcc) is connected to the source of the lower NMOS (Q1). The gate of the upper NMOS (Q2) is connected to the source of the lower NMOS (Q1) through the first regulator (ZD1). The source of the upper NMOS (Q2) is connected to the drain of the lower NMOS (Q1). The drain of the upper NMOS (Q2) and the gate of the lower NMOS (Q1) respectively serve as a first output terminal (3) and a first input terminal (2) of the circuit. The source of the lower NMOS (Q1) serves as the common terminal (1) of a second input terminal and a second output terminal of the circuit. The power loss is reduced with the circuit.

Description

一种提高器件耐压的电路  Circuit for improving device withstand voltage
本申请要求于 2010年 7月 7日提交中国专利局、申请号为 201010222601.9、 发明名称为"一种提高器件耐压的电路"的中国专利申请的优先权，其全部内容 通过引用结合在本申请中。  The present application claims priority to Chinese Patent Application No. 201010222601.9, entitled "A Circuit for Improving Voltage Withstand Voltage", filed on July 7, 2010, the entire contents of which is incorporated herein by reference. in.
技术领域 Technical field
本发明涉及电力电子技术领域， 特别涉及一种提高器件耐压的电路。  The present invention relates to the field of power electronics, and in particular to a circuit for improving the withstand voltage of a device.
背景技术 Background technique
对于较高的电网电压， 例如 480VAC电网，设计适用的开关电源会遇到高 耐压晶体管开关器件的选取困难的问题。对于 480VAC电网来说， 考虑到电网 电压的波动以及设计裕量，使用传统的开关电源设计方案需要选用耐压 1000V 以上的晶体管作为开关器件。 但是耐压 1000V以上的晶体管属于相对比较特 殊的器件， 因此将造成选取困难、 成本较高的问题。  For higher grid voltages, such as the 480 VAC grid, the design of a suitable switching power supply can encounter difficulties in selecting high-voltage transistor switching devices. For the 480VAC grid, considering the fluctuation of the grid voltage and the design margin, the traditional switching power supply design requires the use of a transistor with a withstand voltage of 1000V or higher as the switching device. However, transistors with a withstand voltage of 1000V or more are relatively special devices, which will cause difficulty in selection and high cost.
现有技术中为了解决耐高压晶体管选取困难、成本高的问题提出了几个方 案， 首先参见图 1 , 该图为现有技术中提供的提高器件耐压的电路图。  In the prior art, several solutions have been proposed in order to solve the problem of high-voltage transistor selection difficulty and high cost. First, referring to FIG. 1, the figure is a circuit diagram for improving the withstand voltage of the device provided in the prior art.
图 1所示电路中用两个 NMOS管 Q1和 Q2串联来提供耐压能力，其中下 管 Q1受 PWM控制电路的直接驱动， 当 Q1由导通变为关断时， Q1的漏极和 源极之间的电压升高，当 Q1的漏极和源极之间的电压接近稳压管 ZD1的电压 时， 上管 Q2的栅极和源极之间的电压将低于导通门槛电压， 因此， Q2也进 入关断状态。 当 Q1和 Q2均关断时， Q1分担的电压由稳压管 ZD1的稳压值 决定。 当 Q1 由关断转为导通时， 其漏极和源极之间的电压将下降， 电阻 R1 将为 Q2提供驱动电流， 从而使 Q2也导通。  In the circuit shown in Figure 1, two NMOS transistors Q1 and Q2 are connected in series to provide withstand voltage capability. The lower tube Q1 is directly driven by the PWM control circuit. When Q1 is turned from on to off, the drain and source of Q1. The voltage between the poles rises. When the voltage between the drain and the source of Q1 approaches the voltage of the Zener diode ZD1, the voltage between the gate and the source of the upper transistor Q2 will be lower than the turn-on threshold voltage. Therefore, Q2 also enters the off state. When both Q1 and Q2 are turned off, the voltage shared by Q1 is determined by the regulation value of Zener ZD1. When Q1 turns from off to on, the voltage between the drain and source drops, and resistor R1 supplies the drive current to Q2, which turns Q2 on.
但是， 图 1所示的电路存在以下缺点： 为上管 Q2提供驱动能量的是电阻 R1取自输入电压 Vin的能量，由于输入电压 Vin是高压（通常高于电网电压 ), R1受自身功耗的限制， 不能在 Q2导通时提供较大的驱动电流， 这样将使 Q2 的导通速度慢， Q2的开关损耗和导通损耗较大， 因此该电路的效率低， 通常 只适用于功率艮小的场合。  However, the circuit shown in Figure 1 has the following disadvantages: The driving energy for the upper tube Q2 is the energy of the resistor R1 taken from the input voltage Vin. Since the input voltage Vin is high voltage (usually higher than the grid voltage), R1 is subject to its own power consumption. The limitation is that it can not provide a large driving current when Q2 is turned on. This will make the conduction speed of Q2 slow, and the switching loss and conduction loss of Q2 are large. Therefore, the efficiency of this circuit is low, and it is usually only applicable to power. Small occasions.
参见图 2, 该图为现有技术中提供的另一种耐高压的电路图。  Referring to Figure 2, there is shown another circuit diagram of high voltage withstand capability provided in the prior art.
图 2提供的电路（中国专利申请的申请号为 200810028422.4 )与图 1所示 的电路相似， 图 2所示的电路在稳压管 D4上并联电容 C2。 Q2导通时 C2放电可以改善上管 Q1的驱动。 Q1栅极和源极之间用电阻 R4和二极管 D3串联代替图 1中的稳压管 ZD2。 The circuit provided in Fig. 2 (Application No. 200810028422.4 of Chinese Patent Application) is similar to the circuit shown in Fig. 1. The circuit shown in Fig. 2 has a capacitor C2 connected in parallel with the Zener diode D4. When C2 is turned on, C2 discharge can improve the driving of the upper tube Q1. The resistor R4 and the diode D3 are connected in series between the gate and the source of Q1 in place of the Zener diode ZD2 in FIG.
但是图 2所示电路仍然存在以下缺点： 为上管 Q1提供驱动能量的是电阻 R1取自输入电压 Vin的能量，由于输入电压 Vin是高压（通常高于电网电压 ), 电阻 R1受自身功耗的限制， 不能为 Q1导通提供较大的驱动电流； 当下管 Q2 关断后， Q2漏极电压上升， C2充电， 直到两端电压达到 D4的稳压值（通常 为几百伏）； 而在开关管 Q1,Q2导通时， 电容 C2会通过 Q1门极放电， 直到等 于开关管 Q1的门极驱动电压 （十几伏）， C2的放电虽然能提高 Q1的驱动能 力， 但在开关过程中的充放电， 会产生较大损耗。 因此该电路和图 1所示电路 相比可适用于更大功率等级的场合， 但效率仍然较低。  However, the circuit shown in Figure 2 still has the following disadvantages: The driving energy for the upper tube Q1 is the energy of the resistor R1 taken from the input voltage Vin. Since the input voltage Vin is high voltage (usually higher than the grid voltage), the resistor R1 is subject to its own power consumption. The limit does not provide a large drive current for Q1 turn-on; when the down transistor Q2 turns off, the Q2 drain voltage rises and C2 charges until the voltage across the terminals reaches the regulated value of D4 (usually a few hundred volts); When the switching transistors Q1 and Q2 are turned on, the capacitor C2 will discharge through the gate of Q1 until it is equal to the gate driving voltage of the switching transistor Q1 (ten volts). Although the discharge of C2 can improve the driving capability of Q1, but during the switching process In the charge and discharge, there will be a large loss. Therefore, the circuit can be applied to a higher power level than the circuit shown in Fig. 1, but the efficiency is still low.
现有技术中还提供一种改进方案 （US2008/0080212 )如图 3 所示， 上管 SW2导通时所需的较大驱动电流由电容 CB1提供。 上管 SW2和下关 SW1关 断时的电压分配由电容 CB1和电容 CB2的电压决定， 而 CB1和 CB2的分压 由绕组 NP1和 NP2的变比决定。  An improvement scheme (US2008/0080212) is also provided in the prior art. As shown in Fig. 3, the larger drive current required when the upper tube SW2 is turned on is provided by the capacitor CB1. The voltage distribution when the upper tube SW2 and the lower switch SW1 are turned off is determined by the voltages of the capacitors CB1 and CB2, and the divided voltages of the CB1 and CB2 are determined by the ratio of the windings NP1 and NP2.
但是图 3所示的电路存在以下缺点：虽然驱动上管 SW2的能力得到改善， 但是， 驱动 SW2的器件为电容 CB1。 与图 2的现有技术存在相同的问题， 即 电容 CB1和电容 CB2仍为高压充放电。 因此， 电容 CB1在给上管 SW2提供 驱动能量的过程， 以及 CB1和 CB2电压的平衡过程存在较大损耗。 发明内容  However, the circuit shown in Figure 3 has the following disadvantages: although the ability to drive the upper tube SW2 is improved, the device that drives SW2 is the capacitor CB1. The same problem as the prior art of Fig. 2 is that the capacitor CB1 and the capacitor CB2 are still charged and discharged at a high voltage. Therefore, the capacitor CB1 provides a driving energy to the upper tube SW2, and a large loss occurs in the balance process of the CB1 and CB2 voltages. Summary of the invention
本发明要解决的技术问题是提供一种提高器件耐压的电路，能够提高器件 的耐压能力， 并且降低电路的损耗。  The technical problem to be solved by the present invention is to provide a circuit for improving the withstand voltage of a device, which can improve the withstand voltage capability of the device and reduce the loss of the circuit.
本发明实施例提供一种提高器件耐压的电路， 包括： 第一稳压器件、 第一 二极管、 上 NMOS管和下 NMOS管；  Embodiments of the present invention provide a circuit for improving a withstand voltage of a device, including: a first voltage stabilizing device, a first diode, an upper NMOS transistor, and a lower NMOS transistor;
上 NMOS管的栅极连接第一二极管的阴极， 第一二极管的阳极连接电源 的正端， 电源的负端连接下 NMOS管的源极； 上 NMOS管的栅极通过第一稳 压器件接下 NMOS管的源极；  The gate of the upper NMOS transistor is connected to the cathode of the first diode, the anode of the first diode is connected to the positive terminal of the power supply, and the negative terminal of the power supply is connected to the source of the lower NMOS transistor; the gate of the upper NMOS transistor passes through the first stable The voltage device is connected to the source of the NMOS transistor;
上 NMOS管的源极连接下 NMOS管的漏极；  The source of the upper NMOS transistor is connected to the drain of the NMOS transistor;
上 NMOS管的漏极和下 NMOS管的栅极分别作为该电路的第一输出端和 第一输入端； 下 NM0S管的源极作为该电路的第二输入端和第二输出端的公 共端。 a drain of the upper NMOS transistor and a gate of the lower NMOS transistor respectively serve as a first output of the circuit and a first input; a source of the lower NMOS transistor serves as a common terminal of the second input and the second output of the circuit.
优选地， 还包括连接在电源的正端和负端之间的第一电容。  Preferably, a first capacitor connected between the positive terminal and the negative terminal of the power source is further included.
优选地， 所述第一稳压器件为稳压管， 或瞬变电压抑制二极管 TVS。 优选地， 还包括并联于上 NMOS管的栅极和源极之间的箝位保护模块。 优选地， 所述箝位保护模块为稳压管， 或瞬变电压抑制二极管 TVS。 优选地， 所述电路为封装成一个包括四个管脚或引脚的独立半导体器件， 所述四个管脚或引脚分别为所述第一输入端、 第一输出端、 电源正端、 和第二 输入端第二输出端的公共端。  Preferably, the first voltage stabilizing device is a Zener diode, or a transient voltage suppression diode TVS. Preferably, a clamp protection module is further coupled between the gate and the source of the upper NMOS transistor. Preferably, the clamp protection module is a Zener diode or a transient voltage suppression diode TVS. Preferably, the circuit is packaged into a single semiconductor device including four pins or pins, and the four pins or pins are respectively the first input terminal, the first output terminal, and the power supply positive terminal. And a common end of the second input of the second input.
优选地， 所述电路作为反激电路中与原边绕组连接的开关管。  Preferably, the circuit acts as a switching transistor connected to the primary winding in the flyback circuit.
优选地， 所述电路作为 BUCK电路中的开关管。  Preferably, the circuit acts as a switching tube in the BUCK circuit.
优选地， 所述电路作为 BOOST电路中的开关管。  Preferably, the circuit acts as a switching tube in the BOOST circuit.
本发明提供一种提高器件耐压的电路， 包括： 第一稳压器件、第一二极管、 上 IGBT管和下 IGBT管；  The invention provides a circuit for improving the withstand voltage of a device, comprising: a first voltage stabilizing device, a first diode, an upper IGBT tube and a lower IGBT tube;
上 IGBT管的门极连接第一二极管的阴极， 第一二极管的阳极连接电源的 正端， 电源的负端连接下 IGBT管的源极； 上 IGBT管的栅极通过第一稳压器 件接下 IGBT管的源极；  The gate of the upper IGBT tube is connected to the cathode of the first diode, the anode of the first diode is connected to the positive end of the power source, and the negative end of the power source is connected to the source of the IGBT tube; the gate of the upper IGBT tube passes through the first stable Pressing the device to connect the source of the IGBT tube;
上 IGBT管的源极连接下 IGBT管的漏极；  The source of the upper IGBT tube is connected to the drain of the IGBT tube;
上 IGBT管的漏极和下 IGBT管的栅极分别作为该电路的第一输出端和第 一输入端；  The drain of the upper IGBT tube and the gate of the lower IGBT tube respectively serve as a first output end and a first input end of the circuit;
下 IGBT管的源极作为该电路的第二输入端和第二输出端的公共端。  The source of the lower IGBT transistor serves as the common terminal of the second input and the second output of the circuit.
优选地， 还包括连接在电源的正端和负端之间的第一电容。  Preferably, a first capacitor connected between the positive terminal and the negative terminal of the power source is further included.
优选地， 所述第一稳压器件为稳压管， 或瞬变电压抑制二极管 TVS。 优选地， 还包括并联于上 IGBT管的门极和发射极之间的箝位保护模块。 优选地， 所述箝位保护模块为稳压管， 或瞬变电压抑制二极管 TVS。 优选地， 所述电路为封装成一个包括四个管脚或引脚的独立半导体器件， 所述四个管脚或引脚分别为所述第一输入端、 第一输出端、 电源正端、 和第二 输入端第二输出端的公共端。  Preferably, the first voltage stabilizing device is a Zener diode, or a transient voltage suppression diode TVS. Preferably, a clamp protection module is also provided in parallel between the gate and the emitter of the upper IGBT tube. Preferably, the clamp protection module is a Zener diode or a transient voltage suppression diode TVS. Preferably, the circuit is packaged into a single semiconductor device including four pins or pins, and the four pins or pins are respectively the first input terminal, the first output terminal, and the power supply positive terminal. And a common end of the second input of the second input.
优选地， 所述电路作为反激电路中与原边绕组连接的开关管。 优选地， 所述电路作为 BUCK电路中的开关管。 Preferably, the circuit acts as a switching transistor connected to the primary winding in the flyback circuit. Preferably, the circuit acts as a switching transistor in the BUCK circuit.
优选地， 所述电路作为 BOOST电路中的开关管。  Preferably, the circuit acts as a switching tube in the BOOST circuit.
与现有技术相比， 本发明具有以下优点：  Compared with the prior art, the present invention has the following advantages:
本发明提供的提高器件耐压的电路， 提供给上 NMOS管的驱动电压直接 来自于电源， 因此不需任何转换电路。 当上 NMOS管导通时， 电源只需提供 上 NMOS管门极导通时所需要的驱动能量， 没有其它损耗； 当下 NMOS管关 断时， 第一二极管将电源与第一稳压器件分开， 因此也不产生额外的损耗。 因 此， 本发明实施例提供的电路可以降低损耗。  The circuit for improving the withstand voltage of the device provided by the present invention provides the driving voltage supplied to the upper NMOS transistor directly from the power source, so that no conversion circuit is required. When the upper NMOS transistor is turned on, the power supply only needs to provide the driving energy required when the upper NMOS transistor is turned on, and there is no other loss; when the lower NMOS transistor is turned off, the first diode supplies the power supply and the first voltage stabilizing device. Separate, so no additional losses are incurred. Therefore, the circuit provided by the embodiment of the invention can reduce the loss.
附图说明 DRAWINGS
图 1是现有技术中提供的提高器件耐压的电路图；  1 is a circuit diagram of improving the withstand voltage of a device provided in the prior art;
图 2是现有技术中提供的又一种提高器件耐压的电路图；  2 is a circuit diagram of another method for improving the withstand voltage of a device provided in the prior art;
图 3是现有技术中提供的另一种提高器件耐压的电路图；  FIG. 3 is another circuit diagram for improving the withstand voltage of the device provided in the prior art; FIG.
图 4是本发明实施例一提供的电路图；  4 is a circuit diagram of Embodiment 1 of the present invention;
图 5是本发明实施例二提供的提高器件耐压的电路；  5 is a circuit for improving the withstand voltage of a device according to Embodiment 2 of the present invention;
图 6是本发明提供的电路的一种应用电路；  Figure 6 is an application circuit of the circuit provided by the present invention;
图 7是本发明提供的电路的又一种应用电路；  Figure 7 is still another application circuit of the circuit provided by the present invention;
图 8是本发明提供的电路的另一种应用电路。  Figure 8 is another application circuit of the circuit provided by the present invention.
具体实施方式 detailed description
为使本发明的上述目的、 特征和优点能够更加明显易懂， 下面结合附图对 本发明的具体实施方式做详细的说明。  The above described objects, features and advantages of the present invention will become more apparent from the aspects of the appended claims.
参见图 4, 该图为本发明实施例一提供的电路图。  Referring to FIG. 4, the figure is a circuit diagram of Embodiment 1 of the present invention.
本发明实施例提供的提高器件耐压的电路包括： 第一稳压器件、 第一二极 管 Dl、 上 NMOS管 Q2和下 NMOS管 Q1 ;  The circuit for improving the withstand voltage of the device provided by the embodiment of the invention includes: a first voltage stabilizing device, a first diode D1, an upper NMOS transistor Q2, and a lower NMOS transistor Q1;
上 NMOS管 Q2的栅极连接第一二极管 D1的阴极， 第一二极管 D1的阳 极连接电源正端， 电源负端连接下 NMOS管 Q1的源极； 上 NMOS管 Q2的 栅极通过第一稳压器件接下 NMOS管 Q1的源极；  The gate of the upper NMOS transistor Q2 is connected to the cathode of the first diode D1, the anode of the first diode D1 is connected to the positive terminal of the power supply, the negative terminal of the power supply is connected to the source of the lower NMOS transistor Q1; the gate of the upper NMOS transistor Q2 is passed The first voltage stabilizing device is connected to the source of the NMOS transistor Q1;
上 NMOS管 Q2的源极连接下 NMOS管 Q1的漏极；  The source of the upper NMOS transistor Q2 is connected to the drain of the NMOS transistor Q1;
上 NMOS管 Q2的漏极和下 NMOS管 Q1的栅极分别作为该电路的第一 输出端和第一输入端；下 NMOS管 Q1的源极作为该电路的第二输入端和第二 输出端的公共端； The drain of the upper NMOS transistor Q2 and the gate of the lower NMOS transistor Q1 serve as a first output terminal and a first input terminal of the circuit, respectively; the source of the lower NMOS transistor Q1 serves as a second input terminal and a second of the circuit. The common end of the output;
可以理解的是，所述下 NMOS管 Q1的源极既作为该电路的第二输出端又 作为该电路的第二输入端， 因此， 对于该电路整体来说， 第二输入端和第二输 出端是一个公共端。  It can be understood that the source of the lower NMOS transistor Q1 serves as both the second output of the circuit and the second input of the circuit. Therefore, for the circuit as a whole, the second input and the second output The end is a public end.
其中， 输入端的输入信号 Vd可以为脉冲驱动信号， 该脉冲驱动信号可以 是 PWM信号， 或 PFM信号， 或 PWM+PFM信号等。  The input signal Vd at the input end may be a pulse driving signal, and the pulse driving signal may be a PWM signal, or a PFM signal, or a PWM+PFM signal.
此外， 图 4所示的电路还可以包括第一电容 C1 , 连接在电源正端 （Vcc ) 与电源负端 （第二输入端和第二输出端的公共端）之间。  In addition, the circuit shown in Fig. 4 may further include a first capacitor C1 connected between the positive terminal of the power supply (Vcc) and the negative terminal of the power supply (the common terminal of the second input terminal and the second output terminal).
本实施例中第一稳压器件优选釆用稳压管（如图 4中所示的稳压管 ZD1 ) , 第一稳压器件还可以是瞬变电压抑制二极管 （ TVS , Transient Voltage Suppressor ) , 或其它限制电压的器件等。  In this embodiment, the first voltage stabilizing device is preferably a Zener diode (such as the Zener diode ZD1 shown in FIG. 4), and the first voltage stabilizing device may also be a Transient Voltage Suppressor (TVS). Or other devices that limit voltage, etc.
下面结合图 4详细说明本发明实施例提供的该电路的工作原理。  The working principle of the circuit provided by the embodiment of the present invention is described in detail below with reference to FIG.
下 NMOS管 Q1受脉冲驱动信号控制电路的直接驱动， 其中 Vd为脉冲驱 动信号。  The lower NMOS transistor Q1 is directly driven by the pulse driving signal control circuit, wherein Vd is a pulse driving signal.
当 Q1受脉冲驱动信号的驱动由导通变为关断时， Q1的漏极和源极之间的 电压升高， 第一二极管 D1承受反压关断， 当 Q1的漏极和源极之间的电压接 近稳压管 ZD1的稳压值时， 上 NMOS管 Q2的栅极和源极之间的电压低于导 通门槛电压， Q2也将进入关断状态。 当 Q1和 Q2都关断时， Q1漏源两端分 担的电压由稳压管 ZD1的稳压值决定。  When Q1 is driven to turn off by the driving of the pulse driving signal, the voltage between the drain and the source of Q1 rises, and the first diode D1 is subjected to back-voltage shutdown, when the drain and source of Q1 When the voltage between the poles is close to the regulation value of the Zener diode ZD1, the voltage between the gate and the source of the upper NMOS transistor Q2 is lower than the turn-on threshold voltage, and Q2 will also enter the off state. When both Q1 and Q2 are turned off, the voltage shared across the drain and source of Q1 is determined by the regulation value of Zener ZD1.
当 Q1的栅极有高电平驱动时， Q1的漏极和源极之间的电压将下降直至完 全导通。 当 Q1 的漏极和源极两端的电压较低时， 第一二极管 D1导通， Vcc 进而为 Q2提供足够的驱动电压和电流， 使 Q2也导通。 Vcc由于只需要提供 Q2能导通的门极驱动电压， 因此幅值很低， 一般十几 V左右即可满足要求。 当 Vcc连接线较长时， 增加电容 C1 , 可起到滤波作用。  When the gate of Q1 is driven high, the voltage between the drain and source of Q1 will drop until it is fully turned on. When the voltage across the drain and source of Q1 is low, the first diode D1 conducts, and Vcc provides sufficient drive voltage and current for Q2 to turn Q2 on. Since Vcc only needs to provide the gate driving voltage that Q2 can conduct, the amplitude is very low, generally about ten V can meet the requirements. When the Vcc connection line is long, the capacitor C1 is added to filter.
本发明中， Q2的驱动电压直接来自于 Vcc, 不需任何转换电路， 在 Q2导 通时， Vcc只提供门极导通驱动所需要的能量， 没有其它损耗； 在 Q1关断时， 第一二极管 D1将 Vcc与稳压管 ZD1分开， 也不产生额外的损耗。 因此， 本 发明实施例提供的电路可以降低损耗。  In the present invention, the driving voltage of Q2 is directly from Vcc, and does not require any conversion circuit. When Q2 is turned on, Vcc only provides the energy required for gate conduction driving, and there is no other loss; when Q1 is turned off, the first Diode D1 separates Vcc from Zener ZD1 and does not create additional losses. Therefore, the circuit provided by the embodiment of the present invention can reduce the loss.
图 4中，虚框内的电路可以封装成一个包括四个管脚或引脚的独立半导体 器件， 该四个管脚或引脚分别为第一引脚、 第二引脚、 第三引脚和第四引脚， 下面结合附图进行详细的介绍。 In Figure 4, the circuit within the dashed box can be packaged into a single semiconductor that includes four pins or pins. The four pins or pins are the first pin, the second pin, the third pin and the fourth pin, respectively, which are described in detail below with reference to the accompanying drawings.
如图 4所示，第一引脚 1 (即该电路的第二输入端和第二输出端的公共端 ) 为该独立半导体器件的低压端， 第二引脚 2 (即该电路的第一输入端）为该独 立半导体器件的驱动端（Vd ) , 第三引脚 3 (即该电路的第一输出端）为该独 立半导体器件的高压端， 第四引脚 4为电源端 （Vcc ) 。  As shown in FIG. 4, the first pin 1 (ie, the common terminal of the second input terminal and the second output terminal of the circuit) is the low voltage terminal of the independent semiconductor device, and the second pin 2 (ie, the first input of the circuit) The terminal is the driving terminal (Vd) of the individual semiconductor device, the third pin 3 (ie, the first output of the circuit) is the high voltage terminal of the independent semiconductor device, and the fourth pin 4 is the power terminal (Vcc).
该独立半导体器件可以用于替换电路中的开关管 （如 MOS管或 IGBT ) , 尤其是高压器件。 当替换 MOS管时， 该器件的第一引脚、 第二引脚和第三引 脚分别对应 MOS管的源极、 栅极和漏极。 当替换 IGBT管时， 该器件的第一 引脚、 第二引脚和第三引脚分别对应 IGBT的发射极、 门极和集电极。 当替换 双极性晶体管时， 该器件的第一引脚、 第二引脚和第三引脚分别对应双极性晶 体管的发射极、门极和集电极。另外该开关管还可以替换对应其它可替代 MOS 管或 IGBT的功率器件。 另外， 该独立半导体器件在工作时， 需要在第四引脚 和第一引脚之间接入直流电压源 Vcc。 其中， 电源端 （Vcc )和驱动端 （Vd ) 的参考地是该器件的第一引脚。  The individual semiconductor device can be used to replace a switching transistor (such as a MOS transistor or an IGBT) in a circuit, especially a high voltage device. When the MOS transistor is replaced, the first pin, the second pin, and the third pin of the device correspond to the source, gate, and drain of the MOS transistor, respectively. When replacing the IGBT tube, the first, second, and third pins of the device correspond to the emitter, gate, and collector of the IGBT, respectively. When a bipolar transistor is replaced, the first, second, and third pins of the device correspond to the emitter, gate, and collector of the bipolar transistor, respectively. In addition, the switch can replace power devices that correspond to other alternative MOSFETs or IGBTs. In addition, when the independent semiconductor device is in operation, a DC voltage source Vcc needs to be connected between the fourth pin and the first pin. The reference ground of the power supply terminal (Vcc) and the driver terminal (Vd) is the first pin of the device.
本发明实施例还提供一种提高器件耐压的电路， 参见图 5, 该图为本发明 实施例二提供的提高器件耐压的电路。  The embodiment of the present invention further provides a circuit for improving the withstand voltage of a device. Referring to FIG. 5, the figure is a circuit for improving the withstand voltage of the device according to the second embodiment of the present invention.
本实施例提供的提高器件耐压的电路与实施例一的区别是增加了箝位保 护模块。 如图 5所示， Q2 的栅极和源极之间并联箝位保护模块， 可以将 Q2 的栅极电压箝位在安全范围之内。 该箝位保护模块可以由稳压管， 或 TVS管 等，本实施例中的箝位保护模块为一个稳压管，如图 5所示的第二稳压管 ZD2。 图 5 所示的实施例同样可以将虚框内的电路可以封装成一个包括四个管脚或 引脚的独立半导体器件，该封装器件与开关管的对应关系与图 4中所述的对应 关系相同， 在此不再赘述。  The circuit for improving the withstand voltage of the device provided by this embodiment differs from the first embodiment in that the clamp protection module is added. As shown in Figure 5, the clamp protection module is connected in parallel between the gate and source of Q2 to clamp the gate voltage of Q2 within a safe range. The clamp protection module can be a voltage regulator tube, or a TVS tube, etc. The clamp protection module in this embodiment is a voltage regulator tube, such as the second voltage regulator tube ZD2 shown in FIG. The embodiment shown in FIG. 5 can also package the circuit in the virtual frame into a single semiconductor device including four pins or pins, and the corresponding relationship between the package device and the switch tube and the corresponding relationship in FIG. The same, will not be described here.
需要说明的是， 以上实施例提供的提高器件耐压的电路中的上管和下管均 是 NMOS管， 可以理解的是上管和下管也可以为 IGBT管， 除了上管和下管 不同外， 其他部分的电路均相同。 因此， 其工作原理在此不再赘述。  It should be noted that the upper tube and the lower tube in the circuit for improving the withstand voltage of the device provided by the above embodiments are both NMOS tubes. It can be understood that the upper tube and the lower tube can also be IGBT tubes, except that the upper tube and the lower tube are different. In addition, the circuits in other parts are the same. Therefore, its working principle will not be described here.
本实施例提供的提高器件耐压的电路包括： 第一稳压器件、 第一二极管、 上 IGBT管和下 IGBT管； 上 IGBT管的门极连接第一二极管的阴极， 第一二极管的阳极连接电源正 端， 电源负端连接下 IGBT管的源极； 上 IGBT管的栅极通过第一稳压器件接 下 IGBT管的源极； The circuit for improving the withstand voltage of the device provided by the embodiment includes: a first voltage stabilizing device, a first diode, an upper IGBT tube and a lower IGBT tube; The gate of the upper IGBT tube is connected to the cathode of the first diode, the anode of the first diode is connected to the positive end of the power supply, and the negative end of the power supply is connected to the source of the IGBT tube; the gate of the upper IGBT tube passes through the first voltage stabilizing device Connect the source of the IGBT tube;
上 IGBT管的漏极和下 IGBT管的栅极分别作为该电路的第一输出端和第 一输入端；  The drain of the upper IGBT tube and the gate of the lower IGBT tube respectively serve as a first output end and a first input end of the circuit;
下 IGBT管的源极作为该电路的第二输入端和第二输出端的公共端。  The source of the lower IGBT transistor serves as the common terminal of the second input and the second output of the circuit.
此外，上述提高器件耐压电路还可以包括第一电容，连接在电源正端（ Vcc ) 与电源负端 （第二输入端和第二输出端的公共端）之间。  Furthermore, the above-mentioned improved device withstand voltage circuit may further include a first capacitor connected between the positive terminal of the power supply (Vcc) and the negative terminal of the power supply (the common terminal of the second input terminal and the second output terminal).
上述第一稳压器件可以为稳压管， 还可以是 TVS管 （即瞬变电压抑制二 极管） ， 或其它限制电压的器件等。  The first voltage stabilizing device may be a Zener diode, or may be a TVS tube (ie, a transient voltage suppression diode), or other voltage limiting device.
需要说明的是，本发明以上所有实施例提供的提高器件耐压的电路整体可 以作为一个独立的半导体器件来使用。下面介绍几种典型的该电路作为独立半 导体器件的应用场合。  It should be noted that the circuit for improving the withstand voltage of the device provided by all the above embodiments of the present invention can be used as a single semiconductor device as a whole. Several typical applications of this circuit as stand-alone semiconductor devices are described below.
参见图 6, 该图为本发明提供的电路的一种应用电路。  Referring to Figure 6, the figure shows an application circuit of the circuit provided by the present invention.
本发明提供的电路或独立半导体器件在本实施例中是应用于反激电路。 如图 6所示， 虚框内是本发明提供的提高器件耐压的电路， 其整体作为一 个独立的开关器件使用， 所述电路的第一输出端连接变压器 T1的原边绕组的 同名端，反激电路输入电压 Vin的正端连接原边绕组的非同名端， 负端连接本 发明电路的第二输入端和第二输出端的公共端， 变压器 T1的副边绕组的同名 端通过第二二极管 D2连接输出正端， 变压器 T1的副边绕组的非同名端连接 反激电路输出负端。 反激电路输出正端和输出负端之间并联第二电容 C2。  The circuit or the individual semiconductor device provided by the present invention is applied to the flyback circuit in this embodiment. As shown in FIG. 6, in the virtual frame, the circuit for improving the withstand voltage of the device provided by the present invention is used as an independent switching device. The first output end of the circuit is connected to the same name end of the primary winding of the transformer T1. The positive terminal of the input voltage Vin of the flyback circuit is connected to the non-identical end of the primary winding, the negative terminal is connected to the common end of the second input end and the second output end of the circuit of the present invention, and the same name end of the secondary winding of the transformer T1 passes the second second The pole tube D2 is connected to the positive terminal of the output, and the non-identical end of the secondary winding of the transformer T1 is connected to the negative terminal of the flyback circuit. A second capacitor C2 is connected in parallel between the forward output of the flyback circuit and the negative terminal of the output.
其中反激电路的典型应用是应用在开关电源中， 其输入电压为 Vin, 输出 电压为 Vo。 如果输入电压 Vin较大， 此时就需要开关管的耐压能力较强， 耐 压较高。  A typical application of a flyback circuit is in a switching power supply with an input voltage of Vin and an output voltage of Vo. If the input voltage Vin is large, the voltage resistance of the switch tube is required to be high and the withstand voltage is high.
参见图 7, 该图为本发明提供的电路的又一种应用电路。  Referring to Figure 7, this figure is yet another application circuit of the circuit provided by the present invention.
本发明提供的电路或独立半导体器件在本实施例中是应用于 BUCK电路。 如图 7所示， 虚框内是本发明提供的提高器件耐压的电路， 其整体作为一 个独立的开关器件使用， 所述电路的第一输出端连接 BUCK电路中的第二二 极管 D2的阳极，所述电路的第二输入端和第二输出端的公共端连接 BUCK电 路输入电压 Vin的负端。 The circuit or the independent semiconductor device provided by the present invention is applied to the BUCK circuit in this embodiment. As shown in FIG. 7, in the virtual frame, the circuit for improving the withstand voltage of the device provided by the present invention is used as a separate switching device, and the first output end of the circuit is connected to the second diode D2 in the BUCK circuit. The anode, the common input of the second input end and the second output end of the circuit is connected to the BUCK electric The negative terminal of the input voltage Vin.
第二二极管 D2的阴极连接输入电压 Vin的正端和输出电压 Vo的正端， 阳极还连接第一电感 L1的一端，第一电感 L1的另一端连接输出电压 Vo的负 端， 输出电压 Vo的正端和负端之间并联第二电容 C2。  The cathode of the second diode D2 is connected to the positive terminal of the input voltage Vin and the positive terminal of the output voltage Vo, the anode is also connected to one end of the first inductor L1, and the other end of the first inductor L1 is connected to the negative terminal of the output voltage Vo, the output voltage A second capacitor C2 is connected in parallel between the positive and negative ends of Vo.
参见图 8, 该图为本发明提供的电路的又一种应用电路。  Referring to Figure 8, this figure is yet another application circuit of the circuit provided by the present invention.
本发明提供的电路或独立半导体器件在本实施例中是应用于 BOOST 电 路。  The circuit or individual semiconductor device provided by the present invention is applied to the BOOST circuit in this embodiment.
如图 8所示， 虚框内是本发明提供的提供器件耐压的电路， 其整体作为一 个独立的开关器件使用， 所述电路的第一输出端连接 BOOST电路中的第二二 极管的阳极， 所述电路的第二输入端和第二输出端的公共端连接 BOOST电路 的输入电压 Vin负端和输出电压 Vo负端。  As shown in FIG. 8, within the virtual frame is a circuit for providing a device withstand voltage provided by the present invention, which is used as a separate switching device as a whole, and the first output end of the circuit is connected to the second diode in the BOOST circuit. The anode, the common end of the second input end and the second output end of the circuit is connected to the input voltage Vin negative end of the BOOST circuit and the negative end of the output voltage Vo.
第二二极管 D2的阳极通过第一电感 L1连接输入电压 Vin的正端， 阴极 连接输出电压 Vo的正端。  The anode of the second diode D2 is connected to the positive terminal of the input voltage Vin through the first inductor L1, and the cathode is connected to the positive terminal of the output voltage Vo.
输出电压 Vo的正端和负端之间并联第二电容 C2。  The second capacitor C2 is connected in parallel between the positive and negative terminals of the output voltage Vo.
需要说明的是， 以上仅是本发明提供的电路或独立半导体器件的典型应用 电路图， 可以理解的是，应用本发明实施例提供的耐高压的电路或独立半导体 器件不局限应用于这几种场合， 在其他电路拓朴应用的场合也同样适用，在此 不再——举例介绍。  It should be noted that the above is only a typical application circuit diagram of the circuit or the independent semiconductor device provided by the present invention. It can be understood that the high voltage resistant circuit or the independent semiconductor device provided by the embodiment of the present invention is not limited to these applications. The same applies to other circuit topology applications, no longer here - for example.
以上仅是以 NMOS管为例进行介绍的应用场合，可以理解的是，应用 IGBT 管也可以完成相同的功能， 因此， 在此不再赘述。  The above is only an application where the NMOS transistor is taken as an example. It can be understood that the same function can be performed by using the IGBT tube, and therefore, no further description is provided here.
本发明实施例提供的电路或独立半导体器件， 将两个开关管串联， 从而提 高耐压能力， 并且电路结构简单， 功耗小； 当作为一个独立的半导体封装器件 应用于开关电源类产品中， 节约成本， 提高产品的可靠性。  The circuit or the independent semiconductor device provided by the embodiment of the invention connects the two switch tubes in series to improve the withstand voltage capability, and has a simple circuit structure and low power consumption; when used as a separate semiconductor package device in a switching power supply product, Save costs and increase product reliability.
以上所述，仅是本发明的较佳实施例而已， 并非对本发明作任何形式上的 限制。 虽然本发明已以较佳实施例揭露如上， 然而并非用以限定本发明。 任何 熟悉本领域的技术人员， 在不脱离本发明技术方案范围情况下， 都可利用上述 揭示的方法和技术内容对本发明技术方案做出许多可能的变动和修饰 ,或修改 为等同变化的等效实施例。 因此， 凡是未脱离本发明技术方案的内容， 依据本 发明的技术实质对以上实施例所做的任何简单修改、等同变化及修饰， 均仍属 于本发明技术方案保护的范围内。 The above description is only a preferred embodiment of the invention and is not intended to limit the invention in any way. Although the present invention has been disclosed above in the preferred embodiments, it is not intended to limit the invention. Any person skilled in the art can make many possible variations and modifications to the technical solutions of the present invention by using the methods and technical contents disclosed above, or modify the equivalents of equivalent changes without departing from the scope of the technical solutions of the present invention. Example. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments in accordance with the technical spirit of the present invention are still present without departing from the technical scope of the present invention. It is within the scope of the technical solution of the present invention.

Claims

权 利 要 求 Rights request
1、 一种提高器件耐压的电路， 其特征在于， 包括： 第一稳压器件、 第一 二极管、 上 NM0S管和下 NM0S管；  A circuit for improving the withstand voltage of a device, comprising: a first voltage stabilizing device, a first diode, an upper NM0S tube, and a lower NM0S tube;
上 NM0S管的栅极连接第一二极管的阴极， 第一二极管的阳极连接电源 的正端， 电源的负端连接下 NM0S管的源极； 上 NMOS管的栅极通过第一稳 压器件接下 NMOS管的源极；  The gate of the upper NM0S tube is connected to the cathode of the first diode, the anode of the first diode is connected to the positive end of the power supply, and the negative end of the power supply is connected to the source of the NM0S tube; the gate of the upper NMOS tube passes through the first stable The voltage device is connected to the source of the NMOS transistor;
上 NMOS管的源极连接下 NMOS管的漏极；  The source of the upper NMOS transistor is connected to the drain of the NMOS transistor;
上 NMOS管的漏极和下 NMOS管的栅极分别作为该电路的第一输出端和 第一输入端； 下 NMOS管的源极作为该电路的第二输入端和第二输出端的公 共端。  The drains of the upper NMOS transistor and the gate of the lower NMOS transistor respectively serve as a first output terminal and a first input terminal of the circuit; the source of the lower NMOS transistor serves as a common terminal of the second input terminal and the second output terminal of the circuit.
2、 根据权利要求 1所述的电路， 其特征在于， 还包括连接在电源的正端 和负端之间的第一电容。  2. The circuit of claim 1 further comprising a first capacitor coupled between the positive and negative terminals of the power supply.
3、 根据权利要求 2所述的电路， 其特征在于， 所述第一稳压器件为稳压 管， 或瞬变电压抑制二极管 TVS。  3. The circuit according to claim 2, wherein the first voltage stabilizing device is a Zener diode or a transient voltage suppression diode TVS.
4、 根据权利要求 3所述的电路， 其特征在于， 还包括并联于上 NMOS管 的栅极和源极之间的箝位保护模块。  4. The circuit of claim 3, further comprising a clamp protection module coupled between the gate and the source of the upper NMOS transistor.
5、 根据权利要求 4所述的电路， 其特征在于， 所述箝位保护模块为稳压 管， 或瞬变电压抑制二极管 TVS。  5. The circuit according to claim 4, wherein the clamp protection module is a Zener diode or a transient voltage suppression diode TVS.
6、 根据权利要求 5所述的电路， 其特征在于， 所述电路为封装成一个包 括四个管脚或引脚的独立半导体器件，所述四个管脚或引脚分别为所述第一输 入端、 第一输出端、 电源正端、 和第二输入端第二输出端的公共端。  6. The circuit of claim 5, wherein the circuit is packaged as a single semiconductor device comprising four pins or pins, the four pins or pins being the first The common terminal of the input terminal, the first output terminal, the power supply positive terminal, and the second input terminal and the second output terminal.
7、 根据权利要求 1-6任一项所述的电路， 其特征在于， 所述电路作为反 激电路中与原边绕组连接的开关管。  The circuit according to any one of claims 1 to 6, wherein the circuit functions as a switching transistor connected to the primary winding in the flyback circuit.
8、根据权利要求 1-6任一项所述的电路，其特征在于，所述电路作为 BUCK 电路中的开关管。  8. A circuit according to any of claims 1-6, characterized in that the circuit acts as a switching tube in a BUCK circuit.
9、 根据权利要求 1-6 任一项所述的电路， 其特征在于， 所述电路作为 BOOST电路中的开关管。  9. A circuit according to any of claims 1-6, characterized in that the circuit acts as a switching tube in the BOOST circuit.
10、 一种提高器件耐压的电路， 其特征在于， 包括： 第一稳压器件、 第一 二极管、 上 IGBT管和下 IGBT管； 上 IGBT管的门极连接第一二极管的阴极， 第一二极管的阳极连接电源的 正端， 电源的负端连接下 IGBT管的源极； 上 IGBT管的栅极通过第一稳压器 件接下 IGBT管的源极； 10. A circuit for improving a withstand voltage of a device, comprising: a first voltage stabilizing device, a first diode, an upper IGBT tube, and a lower IGBT tube; The gate of the upper IGBT tube is connected to the cathode of the first diode, the anode of the first diode is connected to the positive end of the power source, and the negative end of the power source is connected to the source of the IGBT tube; the gate of the upper IGBT tube passes through the first stable Pressing the device to connect the source of the IGBT tube;
上 IGBT管的源极连接下 IGBT管的漏极；  The source of the upper IGBT tube is connected to the drain of the IGBT tube;
上 IGBT管的漏极和下 IGBT管的栅极分别作为该电路的第一输出端和第 一输入端；  The drain of the upper IGBT tube and the gate of the lower IGBT tube respectively serve as a first output end and a first input end of the circuit;
下 IGBT管的源极作为该电路的第二输入端和第二输出端的公共端。  The source of the lower IGBT transistor serves as the common terminal of the second input and the second output of the circuit.
11、 根据权利要求 10所述的电路， 其特征在于， 还包括连接在电源的正 端和负端之间的第一电容。  11. The circuit of claim 10, further comprising a first capacitor coupled between the positive and negative terminals of the power supply.
12、 根据权利要求 11所述的电路， 其特征在于， 所述第一稳压器件为稳 压管， 或瞬变电压抑制二极管 TVS。  The circuit according to claim 11, wherein the first voltage stabilizing device is a voltage stabilizing tube or a transient voltage suppressing diode TVS.
13、 根据权利要求 12所述的电路， 其特征在于， 还包括并联于上 IGBT 管的门极和发射极之间的箝位保护模块。  13. The circuit of claim 12, further comprising a clamp protection module coupled between the gate and the emitter of the upper IGBT transistor.
14、 根据权利要求 13所述的电路， 其特征在于， 所述箝位保护模块为稳 压管， 或瞬变电压抑制二极管 TVS。  14. The circuit of claim 13, wherein the clamp protection module is a stabilizing tube, or a transient voltage suppression diode TVS.
15、 根据权利要求 14所述的电路， 其特征在于， 所述电路为封装成一个 包括四个管脚或引脚的独立半导体器件，所述四个管脚或引脚分别为所述第一 输入端、 第一输出端、 电源正端、 和第二输入端第二输出端的公共端。  15. The circuit of claim 14, wherein the circuit is packaged as a single semiconductor device comprising four pins or pins, the four pins or pins being the first The common terminal of the input terminal, the first output terminal, the power supply positive terminal, and the second input terminal and the second output terminal.
16、 根据权利要求 10-15任一项所述的电路， 其特征在于， 所述电路作为 反激电路中与原边绕组连接的开关管。  16. A circuit according to any one of claims 10-15, characterized in that the circuit acts as a switching tube connected to the primary winding in the flyback circuit.
17、 根据权利要求 10-15任一项所述的电路， 其特征在于， 所述电路作为 BUCK电路中的开关管。  17. A circuit according to any of claims 10-15, characterized in that said circuit acts as a switching tube in a BUCK circuit.
18、 根据权利要求 10-15任一项所述的电路， 其特征在于， 所述电路作为 BOOST电路中的开关管。  18. Circuit according to any of the claims 10-15, characterized in that the circuit acts as a switching tube in the BOOST circuit.
PCT/CN2010/078657 2010-07-07 2010-11-12 Circuit for improving voltage-resistance of devices WO2012003685A1 (en)

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