WO2012000146A1 - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

Info

Publication number
WO2012000146A1
WO2012000146A1 PCT/CN2010/001486 CN2010001486W WO2012000146A1 WO 2012000146 A1 WO2012000146 A1 WO 2012000146A1 CN 2010001486 W CN2010001486 W CN 2010001486W WO 2012000146 A1 WO2012000146 A1 WO 2012000146A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
fin
source
semiconductor device
forming
Prior art date
Application number
PCT/CN2010/001486
Other languages
English (en)
French (fr)
Inventor
朱慧珑
骆志炯
尹海洲
Original Assignee
中国科学院微电子研究所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 中国科学院微电子研究所 filed Critical 中国科学院微电子研究所
Priority to US13/003,873 priority Critical patent/US8598595B2/en
Publication of WO2012000146A1 publication Critical patent/WO2012000146A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/66803—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants

Definitions

  • the present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a FinFET (Fin Field Effect Transistor) used as a non-volatile memory cell (NVM) formed on a SOKS semiconductor On Insulator (semiconductor-on-insulator) substrate.
  • FinFET Fin Field Effect Transistor
  • NVM non-volatile memory cell
  • MOSFETs metal oxide semiconductor field effect transistors
  • a conventional planar MOSFET includes a sandwich structure composed of a gate electrode, a gate dielectric layer, and a semiconductor layer, and includes a channel region under the gate electrode and source/drain regions on both sides of the channel region in the semiconductor layer.
  • a silicide layer can be formed on the source/drain regions, and the silicide layer is connected to the source/drain electrodes through the via holes, thereby reducing the parasitic resistance and parasitic capacitance of the device.
  • the planar MOSFET is adversely affected by the short channel effect, causing the threshold voltage of the device to fluctuate as the channel length changes.
  • a FinFET formed on the SOI is disclosed in US Patent No. 6,413, 802 to Chenming Hu et al., including a channel region formed in the middle of a fin of a semiconductor material, and Source/drain regions formed at both ends of the fin.
  • the gate electrode surrounds the channel region (i.e., the double gate structure) on both sides of the channel region, so that the inversion layer is formed on each side of the channel.
  • the thickness of the channel region in the fin is so thin that the entire channel region can be controlled by the gate, thereby suppressing the short channel effect.
  • the capacitive coupling between the source/drain regions and the gate limits the freedom of device design. If it is desired to reduce the parasitic resistance, it is necessary to increase the thickness of the source/drain regions. However, an increase in the thickness of the source/drain regions will result in an increase in the coupling area between the source/drain regions and the gate, resulting in an increase in parasitic capacitance, and vice versa. Therefore, those skilled in the art cannot achieve a simultaneous reduction in parasitic resistance and parasitic capacitance using a conventional FinFET structure. As a result, in the conventional FinFET, the delay is increased due to the large value of the time constant RC, which in turn lowers the switching speed of the device.
  • An object of the present invention is to provide an NVM device capable of suppressing a short channel effect and increasing an access speed. Another object of the present invention is to further provide an NVM device that utilizes stress to improve device performance.
  • a semiconductor device comprising: an SOI substrate; a semiconductor fin formed on the SOI substrate, the fin comprising a first side and a second side opposite to the surface of the SOI substrate, a groove having a groove opposite to the first side surface, the groove facing away from the first side opening; a channel region formed between the groove of the first side and the second side of the fin; the source region and the drain region are formed On both sides of the channel region on the fin; a gate stack formed on the SOI substrate adjacent to the first side of the fin; wherein the gate stack includes: a first gate dielectric layer facing away from the first side and adjacent to the channel region Forming; a first conductor layer facing away from the first side and adjacent to the first gate dielectric layer; a second gate dielectric layer facing away from the first side and adjacent to a side surface of the first conductor layer; the second conductor layer, facing away from the first The side surface is formed adjacent to a side surface of the second gate dielectric layer.
  • a method of fabricating a semiconductor device comprising: providing a SOI substrate; forming a semiconductor fin on the SOI substrate, the fin comprising a first side opposite the surface of the SOI substrate And a second side; forming a gate stack on the SOI substrate, facing away from the first side surface and forming a first gate dielectric layer adjacent to the channel region; facing away from the first side surface and adjacent to the first gate dielectric layer to form a first conductor a second gate dielectric layer is formed away from the first side surface and adjacent to a side surface of the first conductor layer; a second conductor layer is formed adjacent to a side surface of the second gate dielectric layer facing away from the first side surface; a source region is formed at both ends of the fin and a drain region; a position on the fin adjacent to the second side
  • the etching causes the second side to form a groove, the groove being opposed to the first side and facing away from the first side opening, and a channel region is formed between the first side
  • the semiconductor device is used as an NVM in which a first conductor layer in a gate stack is used as a floating gate for storing charges, and a second conductor layer is used as a control gate.
  • the semiconductor device of the present invention includes a semiconductor fin, but its structure is different from that of a conventional FinFET because its gate is disposed only on one side of the fin and extends away from the fin, and the conventional FinFET is disposed in a double gate structure. And surrounding the channel region of the middle portion of the fin. Moreover, the source/drain regions are provided at both ends of the fin, extending in a direction opposite to the direction in which the gate extends.
  • the gate electrode extending in parallel with the source/drain regions between the source/drain regions is not included in the semiconductor device of the present invention, so that there is no capacitive coupling between the source/drain regions and the gate, thereby reducing the parasitic capacitance. Further, the semiconductor device of the present invention allows the parasitic resistance to be reduced by using a thicker source/drain region.
  • the thickness of the source and drain regions is larger than the channel region, the length of the conduction path of the carriers can be reduced, thereby further reducing parasitic effects related to parasitic capacitance and parasitic resistance.
  • a stress layer can be formed in the source/drain regions to increase the stress in the channel region, thereby increasing the mobility of carriers, thereby further increasing the switching speed of the device.
  • the self-aligned channel region is very thin: about 5-40rnn. Also, in a preferred process, the thickness of the channel region is further reduced by the ultra-steep back-off well (SSRW) process. Even if the gate is provided only on one side of the channel, the channel region can be completely controlled by the gate, thereby reducing the effect of the short channel effect.
  • SSRW ultra-steep back-off well
  • channeling is inhibited by the channel region of the fin structure, and the gate, source/drain regions extending away from the fin in opposite directions are used to reduce parasitic capacitance and parasitic resistance while utilizing stress
  • the layer increases the mobility of carriers in the channel region.
  • the semiconductor device of the present invention increases the access speed and threshold voltage of the NVM, and also reduces the power consumption of the device.
  • 1A and 1B are a three-dimensional perspective view and a plan view schematically illustrating a structure of a semiconductor device according to the present invention, and lines ⁇ - ⁇ ', 1- and 2- 2' represent the cut-out positions of the following cross-sectional views.
  • 2 to 9 are cross-sectional views of the semiconductor structure formed along the line A-A' of the respective steps of the method of fabricating a semiconductor device in accordance with the present invention, showing respective steps of forming a fin region and a gate region.
  • 10-16 are cross-sectional views of the semiconductor structure formed along the 1-turn line of the subsequent steps of the method of fabricating a semiconductor device in accordance with the present invention, showing various steps of forming source/drain regions.
  • 17-18 are cross-sectional views of the semiconductor structure formed along the line A-A' of the subsequent steps of the method of fabricating a semiconductor device in accordance with the present invention, showing various steps of forming a channel region.
  • 19A, 19B, 20A, 20B are cross-sectional views of the semiconductor structure formed along the line A-A' and line 2-2', respectively, in a subsequent step of the method of fabricating a semiconductor device according to the present invention, wherein the source/ The steps of forming a silicide layer on the drain region and the gate. detailed description
  • the SOI substrate as an initial structure includes, for example, silicon on insulator, silicon germanium on insulator, and a semiconductor material stack on the insulator.
  • the semiconductor material stack includes, for example, a III-V semiconductor such as GaAs, InP, GaN, SiC;
  • the gate conductor layer may be a metal layer, a doped polysilicon layer, or a stacked gate conductor including a metal layer and a doped polysilicon layer.
  • the material of the conductor layer is TaC, TiN, TaTbN, TaErN, TaYbN, TaSiN, HfSiN, MoSiN, RuTax, NiTax, MoNx, TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSix, Ni3Si, Pt, Ru, Ir, Mo, HfRu , RuOx and a combination of the various metallic materials described.
  • the gate dielectric layer may be composed of SiO 2 or a high-k material having a dielectric constant greater than SiO 2 or other materials, including, for example, oxides, nitrides, oxynitrides, silicates, aluminates, titanates, wherein, oxidation thereof include, for example Si0 2, Hf0 2 Zr0 2, A1 2 0 3, Ti0 2, L3 ⁇ 40:. t, include nitrides such as Si, including silicates such as HfSiOx, e.g. aluminates comprising LaA10: , titanium
  • the acid salt includes, for example, SrTiO 3
  • the oxynitride includes, for example, SiON.
  • the gate dielectric layer may be formed not only by materials well known to those skilled in the art, but also materials for the gate dielectric layer which are bursting in the future.
  • FIGS. 1A and 1B are a three-dimensional perspective view and a plan view schematically illustrating a structure of a semiconductor device in accordance with the present invention.
  • Lines A-A', 1-1 ', 2-2' in Fig. 1B indicate the cut-off positions of the cross-sectional views, wherein the line AA' is perpendicular to the channel length direction and passes through the gate, and the line 1- ⁇ along the channel length The direction passes through the channel region, and line 2-2' follows the length of the channel and passes through the insulating material fill between the source/drain regions.
  • the left side surface of the fin in Fig. 1B is referred to as a first side surface
  • the right side surface is referred to as a second side surface.
  • the second side has a groove at a position opposite to the middle of the first side, and the groove faces away from the first side port.
  • a semiconductor device 100 is formed on a SOI substrate, including a channel region 11 at a middle portion of a semiconductor fin, source regions 12 and drain regions 13 at both ends thereof, and fins disposed at the fins a gate stack on the first side, including a first gate dielectric layer 16, a first conductor layer 17, a second gate dielectric layer 18, and a second conductor layer 19, and a recess for filling the second side of the fin Insulation filler.
  • the first side and the second side are opposite sides of the S0I substrate, and the directions of the two sides may be substantially perpendicular to the SOI substrate.
  • the semiconductor device 100 is used as an NVM in which a first conductor layer 17 in a gate stack is used as a floating gate for storing electric charges, and a second conductor layer 19 is used as a control gate.
  • the gate stack includes: a first gate dielectric layer 16 formed away from the first side and adjacent to the channel region 11; a first conductor layer 17 formed away from the first side and adjacent to the first gate dielectric layer 16; 18, facing away from the first side and adjacent to the side surface of the first conductor layer 17; the second conductor layer 19 is formed adjacent to the side surface of the second gate dielectric layer 18 away from the first side.
  • the fins are formed by the SOI layer in the SOI substrate.
  • the groove of the second side is filled with an insulating material such as Si.
  • the channel region is located between the first side and the recess of the second side, and the channel region is thin, for example, in the range of about 5-40 nm. This thickness is similar to the thickness of the channel region in a conventional FinFET and can be formed using a similar self-aligned process.
  • the inventors have found that although a double gate structure is not employed, if the thickness of the channel region is within the above range, the gate electrode on the first side of the fin can still act on the entire channel region, thereby suppressing the short channel effect.
  • the semiconductor device further includes stressors 14 and 15 for applying stress to the source region 12 and the drain region 13.
  • the stress layers 14 and 15 are adjacent to the source region 12 and the drain region, respectively, and the contact area is as large as possible, so that the contact resistances of the stress layers 14 and 15 with the source region 12 and the drain region 13 are minimized.
  • the source region 12 and the drain region 13 are stepped, and the stress layers 14 and 15 are located in the step portion, so that one side and the bottom of the stress layers 14 and 15 are in contact with the source region 12 and the drain region 13.
  • the materials of the stress layers 14 and 15 should be capable of creating stresses in the channel region that are beneficial for improving transistor performance.
  • the stress layers 14 and 15 should apply tensile stress in the source/drain direction to the channel region to increase the mobility of electrons as carriers.
  • the stress layers 14 and 15 should apply a compressive stress in the source/drain direction to the channel region to increase the mobility of holes as carriers.
  • the stress layers 14, 15 are respectively located in the source region 12 in contact with the source (not shown), and the drain region 13 is in contact with the drain (not shown).
  • the conductive paths between, therefore, the stress layers 14, 15 should also be electrically conductive.
  • Si or C materials doped with As or P can be used, and for p-type MOSFETs, SiGe materials doped with B or In can be used.
  • Source region 12, drain region 13 and gate conductor 19 are not shown in FIGS. 1A and 1B, such as sidewall spacers, silicide layers, source contacts, drain contacts, and gate contacts. , an interlayer insulating layer, a via hole formed in the interlayer insulating layer, a passivation layer, and the like.
  • the method of fabricating a semiconductor device of the present invention begins with a SOI substrate which is a laminate including a bottom substrate 21, a BOX (Buried Oxide) 22, and a top semiconductor layer 23.
  • SOI substrate which is a laminate including a bottom substrate 21, a BOX (Buried Oxide) 22, and a top semiconductor layer 23.
  • the SiGe layer 24 and the thickness of the Ge content of about 5-15% and the thickness of about 3-20 nm are epitaxially grown on the SOI wafer by a known deposition process such as PVD, CVD, atomic layer deposition, sputtering, or the like.
  • the Si layer 25 may be formed in a separate deposition step, or may be formed in situ by using a Si target or a precursor after epitaxially growing the SiGe layer 24.
  • an Hf0 2 layer 26 having a thickness of about 3- lOrim is formed on the Si layer 25 by atomic layer deposition, magnetron sputtering or the like.
  • a strip-shaped photoresist pattern 27 is formed on the Hf0 2 layer 26 by a conventional photolithography process including exposure and development steps.
  • the Hf0 2 layer 26, the Si layer 25, and the SiGe layer are removed by dry etching, such as ion milling, plasma etching, reactive ion etching, laser ablation, or the like using the photoresist pattern 27 as a mask.
  • a portion of 24 forms a laminated structure of the pattern of the Hf0 2 layer 26, the Si layer 25, and the SiGe layer 24.
  • reactive ion etching it can be carried out in two steps.
  • the gas composition of the etching atmosphere is selected such that a portion of the 0 2 layer 26 and the Si layer 25 is removed and stopped at the top of the SiGe layer 24.
  • the second step by changing the gas composition of the etching atmosphere, causes a portion of the SiGe layer 24 to be removed and stopped on the top semiconductor layer 23 of the SOI substrate. It is known in the art that in reactive ion etching, one of the SiGe layer and the Si layer can be selectively removed by changing the gas composition of the etching atmosphere.
  • the photoresist pattern 27 is removed by dissolving or ashing in a solvent.
  • a conformal oxide layer 28 having a thickness of about 2 to 5 nm is formed on the patterned stacked structure and the exposed portion of the top semiconductor layer 23 of the SOI substrate.
  • the thin oxide layer can be formed by a known deposition process such as PVD, CVD, atomic layer deposition, sputtering, and the like. Then, a conformal nitride layer is first formed, and then a portion of the layer is removed, thereby forming a nitride spacer having a thickness of about 5 to 50 nm on both sides of the stacked structure including the Hf0 2 layer 26, the Si layer 25, and the SiGe layer 24. 29.
  • a photoresist layer pattern 30 is formed on the structure shown in FIG. 4 by a conventional photolithography process including an exposure and development step to block the left side wall and the left side portion of the patterned laminate structure. .
  • the right side wall is removed by isotropic etching, for example, conventional wet etching using an etchant solution.
  • the side walls of the right side can be removed in three steps.
  • Ge is implanted into the side wall on the right side by the oblique ion implantation using the resist pattern 30 as a mask to cause defects.
  • the photoresist pattern 30 is removed by dissolving or ashing in a solvent.
  • the right side wall is selectively removed relative to the left side wall by wet etching or dry etching.
  • the gas composition of the etch atmosphere is selected, such as by reactive ion etching, to selectively remove portions of the oxide layer 28 that are exposed on the surface of the semiconductor structure.
  • the gas composition of the etching atmosphere is changed, for example, by reactive ion etching.
  • the top semiconductor layer of the SOI substrate i.e., the exposed portion of the SOI layer, is selectively removed to form the semiconductor fins 23' in a self-aligned manner.
  • a conformal oxide (eg, Hf0 2 ) having a thickness of about 2 to 4 nm is sequentially formed on the surface of the semiconductor structure shown in FIG. 6 by, for example, CVD (Chemical Vapor Deposition) or ALD (Atomic Layer Deposition).
  • the oxide thin layer 26', the metal layer 31, the nitride layer 32, and the polysilicon layer 33 will form a first gate dielectric layer 16, a first conductor layer 17, a second gate dielectric layer 18, and a second, respectively.
  • Conductor layer 19 The first gate dielectric layer 16, the first conductor layer 17, the second gate dielectric layer 18, and the second conductor layer 19 may be selected with reference to the materials of the foregoing gate dielectric layer and gate conductor.
  • the polysilicon layer 33 may be doped in situ to improve conductivity.
  • a polysilicon layer 33 covers the entire top of the semiconductor structure. Then, the polysilicon layer 33 is planarized (CMP). The planarization process is stopped at the top of the nitride layer 32, thereby obtaining a flat surface of the semiconductor structure.
  • a portion of the polysilicon layer 33 is selectively removed from the nitride layer 32 by wet etching or thousand etching, and the polysilicon layer 33 is etched back.
  • a blanket oxide layer 34 is then formed over the entire surface of the semiconductor structure, such as by CVD.
  • the oxide layer 34 is planarized to remove a portion of the nitride layer 32 above the fins 23' and stop at the top of the metal layer 31, thereby obtaining a flat surface of the semiconductor structure. As a result, the oxide layer 34 fills the portion of the polysilicon layer 33 which is removed by etch back.
  • a nitride layer 35 is formed on the surface of the semiconductor structure, for example, by CVD.
  • a strip of photoresist pattern 36 is formed for defining the gate region of the device by a conventional photolithography process including exposure and development steps.
  • the nitride layer 35, the oxide layer 34, the polysilicon layer 33, and the like are sequentially removed by dry etching such as ion milling, plasma etching, reactive ion etching, and laser ablation.
  • dry etching such as ion milling, plasma etching, reactive ion etching, and laser ablation.
  • a portion of the nitride layer 32, the metal layer 31, and the thin oxide layer 26' on both sides of the fin 23' is stopped at the top of the BOX 22 in the SOI substrate.
  • a cross-sectional view of the semiconductor structure along the line is shown in Fig. 10.
  • the etching step using the photoresist pattern 36 as a mask obtains a laminate of the nitride layer 35, the metal layer 31, and the oxide thin layer 26' over the S i layer 25.
  • a portion of the fins 23', the SiGe layer 24, and the Si layer 25 may be removed by an additional mask forming step and an etching step before or after the above etching step to define the length of the fins.
  • the dimension L of the fin 23' defined thereby is shown in Fig. 10 in the horizontal direction.
  • a portion of the Si layer 25 and the SiGe layer 24 is sequentially removed by dry etching, such as ion milling, plasma etching, reactive ion etching, laser ablation, using the photoresist pattern 36 as a mask.
  • dry etching such as ion milling, plasma etching, reactive ion etching, laser ablation
  • a multilayer stack 101 including a nitride layer 35, a metal layer 31, an oxide thin layer 26, a Si layer 25, and a SiGe layer 24 is formed over the fins 23'.
  • the photoresist pattern 36 is removed by dissolving or ashing in a solvent.
  • a conformal oxide layer 37 having a thickness of about 2 to 5 nm and a conformal nitride layer 38 having a thickness of about 10 to 20 nm are sequentially formed on the entire surface of the semiconductor structure, for example, by CVD.
  • etching such as ion milling, plasma etching, reactive ion etching, laser ablation A portion of the layer 38, the etch stops at the surface of the oxide layer 37, thereby forming nitride spacers 38 on the sides of the fins 23' and the multilayer stack 101, respectively.
  • the oxide layer 37 is removed by dry etching, such as ion milling, plasma etching, reactive ion etching, laser ablation, using the multilayer stack 101 and the nitride side walls 38 on both sides as a hard mask.
  • dry etching such as ion milling, plasma etching, reactive ion etching, laser ablation
  • a portion of the semiconductor material of the surface and the fins 23' is exposed, thereby forming openings 39 at both ends of the fins 23 in the length direction (i.e., the horizontal direction in the drawing).
  • a thin layer of semiconductor material having a thickness of about lOrnn is retained at the bottom of the opening 39. This thin layer of semiconductor material is part of the S0I layer in the SOI substrate.
  • the etching step is self-aligned, wherein the size of the opening 39 is substantially determined by the oxide layer 37 and the nitride spacer 38.
  • Figure 14 illustrates an optional step in certain embodiments for performing halo implantation from the mouth 39 to the middle portion of the fin 23' using dip ion implantation.
  • B or BF2 is used as a dopant.
  • pMOSFET use As or P as a dopant.
  • Figure 15 illustrates an optional step in some embodiments that utilizes tilt ion implantation to extend the implant into the middle portion of the fin 23' (extension implantation for an n-type MOSFET using As or P as a dopant. M0SFET, using B or BF2 as a dopant.
  • the extended implant uses a smaller angle of inclination and a larger energy, so that in the extended implant, most of the implanted ions pass through a thin layer of semiconductor material at the bottom of the opening 39, so that the thin layer of the semiconductor material is not amorphous. Chemical.
  • an appropriate amount of source/drain ion implantation may be performed.
  • the cornice 39 provides a window for ion implantation, and the nitride layer 35, the oxide layer 37, and the nitride spacer 38 on the surface of the semiconductor structure provide a hard mask, the above-described extension implantation, halo implantation, and source / Drain injection can be performed in situ, reducing the number of masks and simplifying the process.
  • the formed semiconductor structure is annealed, such as a spike anneal step (the spike anneal anneal step is used to activate the dopant implanted through the previous implant step and eliminate the damage caused by the implant.
  • a spike anneal step is used to activate the dopant implanted through the previous implant step and eliminate the damage caused by the implant.
  • the dopant distribution in the semiconductor fin 23' is as shown in Fig. 16, and a source region 12 and a drain region 13 are formed at the bottom of the opening 39, respectively, in phase with the source region 12 and the drain region 13.
  • the adjacent locations respectively form a source extension 12' and a drain extension 13', respectively forming a source adjacent to the source extension 12' and the drain extension 13' and extending toward the intermediate portion of the fin 23' Halo zone 12" and leak halo zone 13".
  • the stress layer 40 and the epitaxial silicon layer 41 thereon are sequentially epitaxially grown in the opening 39 by a known deposition process such as PVD, CVD, atomic layer deposition, sputtering, or the like. Due to epitaxial growth, the stress layer 40 is only formed in the open The thin layer of semiconductor material at the bottom of the port 39 eliminates the need for an additional mask.
  • the material of the stress layer 40 is SiGe having a Ge content of about 20-50% and is doped in situ in B. After epitaxial growth, a compressive stress is generated in the direction of the drain region of the channel region, which can enhance the performance of the pMOSFET.
  • the material of the stress layer 40 is a C content of about 0.5 to 2% of Si: C and in situ doped with As or! 3. After epitaxial growth, tensile stress is generated in the direction of the drain and drain of the channel region, which can enhance the performance of the nMOSFET.
  • the formed semiconductor structure is oxidized, and the top of the epitaxial silicon layer 41 is oxidized to form an oxidized thin layer 37' having a thickness of about 3 to 10 rim.
  • the epitaxial silicon layer 41 formed on top of the stress layer 40 is used to obtain good quality Si0 2 .
  • the oxide layer 34 formed in the step shown in FIG. 8 is used as a hard mask, and the metal layer 31 is sequentially removed by dry etching such as ion milling etching, plasma etching, reactive ion etching, and laser ablation.
  • dry etching such as ion milling etching, plasma etching, reactive ion etching, and laser ablation.
  • a thin portion of the nitride thin layer 26', the Si layer 25, the SiGe layer 24, and the fins 23' are stopped at the top of the BOX 22 of the SOI substrate to form the opening 42 in a self-aligned manner.
  • the oxide layer 28 and the nitride spacer 29 act as a hard mask defining the intermediate position thickness of the fin 23', that is, the thickness of the intermediate position of the fin 23' is reduced to be substantially equal to the oxide layer 28.
  • a laminate comprising a portion of the nitride thin layer 26', the metal layer 31, the nitride layer 32, the polysilicon layer 33, and the oxide layer 34 remains.
  • the laminate material on the right side of the opening 42 can serve as a gate region of an adjacent MOSFET (not shown), and the filling material in the opening 42 can be shallow. The role of the trench isolation zone.
  • the nitride spacers 38 formed in the step shown in Fig. 12 are also present on the side faces of the gate stack.
  • the ultra-steep back-off (SSRW) process can also be utilized to further reduce the thickness of the fins 23'.
  • the SSRW is disposed in the fin 23' adjacent the channel region and adjacent to the second side of the fin opposite the first side adjacent the nitride thin layer 26'. See the following documents for the formation process of SSRW:
  • the following two steps are performed to remove the side wall 38 on the left side.
  • Ge is implanted into the spacer on the left side by tilt ion implantation using the oxide layer 34 as a mask to cause damage.
  • the left side wall is selectively removed from the right side wall by wet etching or dry etching.
  • a thin layer 34' of a conformal oxide having a thickness of about 2 - 5 ⁇ is formed on the entire surface of the semiconductor structure, for example, by CVD.
  • Nitride is then deposited, for example by CVD, to a thickness at least capable of filling the cornice 42.
  • the nitride is selectively etched back relative to the oxide layer 34' such that the nitride layer around the opening is completely removed leaving the nitride fill material 43 only in the cornice.
  • the exposed portions of oxide layer 34' are selectively removed relative to nitride fill material 43 by dry etching, such as ion milling, plasma etching, reactive ion etching, laser ablation.
  • dry etching such as ion milling, plasma etching, reactive ion etching, laser ablation.
  • the etch leaves only the portion of the oxide sidewall 34' that fills the sidewalls and bottom of the opening, thereby exposing the upper and left surface of the polysilicon layer 33 in the gate stack, and the extension of the source and drain regions.
  • the etch also removes a portion of the buried oxide layer 22 of the SOI substrate.
  • a portion of the upper and left side surfaces of the polysilicon layer 33 in the gate stack, and at least a portion of the epitaxial silicon layer 41 of the source and drain regions are converted into silicidation by a conventional silicidation process.
  • the layer 44 is formed to reduce the contact resistance between the gate, source/drain and corresponding metal contacts.
  • a Ni layer having a thickness of about 5 to 12 nm is first deposited, and then heat-treated at a temperature of 300 to 500 ° C for 1 to 10 seconds, so that at least a portion of the polysilicon layer 33 and the epitaxial silicon layer 41 form NiSi, and finally wet.
  • the etching removes unreacted Ni.
  • an interlayer insulating layer, a via hole in the interlayer insulating layer, and an upper surface of the interlayer insulating layer are formed on the obtained semiconductor structure according to a method known in the art. Wiring or electrodes to complete other parts of the semiconductor device.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Thin Film Transistor (AREA)

Description

半导体器件及其制造方法 技术领域
本发明涉及一种半导体器件及其制造方法，更具体地，涉及在 SOKSemiconductor On Insulator,绝缘体上半导体）衬底上形成的用作非挥发性存储单元（NVM)的 FinFET (鳍式场效应晶体管）。 背景技术
集成电路技术的一个重要发展方向是金属氧化物半导体场效应晶体管 （M0SFET) 的尺寸按比例缩小， 以提高集成度和降低制造成本。然而， 众所周知的是随着 M0SFET 的尺寸减小会产生短沟道效应。 在 M0SFET的尺寸按比例缩小时， 栅极的有效长度减 小， 使得实际上由栅极电压控制的耗尽层电荷的比例减少， 从而阈值电压随沟道长度 减小而下降。
常规的平面 M0SFET包括由栅电极、 栅介质层和半导体层构成的三明治结构， 在 半导体层中包括位于栅电极下方的沟道区和位于沟道区两侧的源 /漏区。在源 /漏区上 可以形成硅化物层， 利用通孔将硅化物层与源 /漏电极相连， 从而减小了器件的寄生 电阻和寄生电容。 平面 M0SFET受到短沟道效应的不利影响， 导致器件的阈值电压随 沟道长度的变化而波动。
为了抑制短沟道效果， 在 Chenming Hu等人的美国专利 US6, 413, 802中公幵了 在 S0I上形成的 FinFET, 包括在半导体材料的鳍片 （fin ) 的中间形成的沟道区， 以 及在鳍片两端形成的源 /漏区。栅电极在沟道区的两个侧面包围沟道区（即双栅结构）， 从而反型层形成在沟道各个侧面上。鳍片中的沟道区厚度很薄， 使得整个沟道区都能 受到栅极的控制， 因此能够起到抑制短沟道效应的作用。
然而， 在常规的 FinFET中， 由于在源 /漏区之间存在着与源 /漏区平行延伸的栅 极，并且源 /漏区与栅极之间的距离很近，因此在源 /漏区和栅极之间存在着电容耦合， 导致了寄生电阻和寄生电容较大的问题。
源 /漏区和栅极之间的电容耦合限制了器件设计的自由度。 如果希望减小寄生电 阻， 则需要增加源 /漏区的厚度。 然而， 源 /漏区厚度的增加将导致源 /漏区与栅极之 间的耦合面积增加， 从而导致寄生电容的增加， 反之亦然。 因此， 本领域的技术人员 还不能利用常规的 FinFET结构实现寄生电阻和寄生电容的同时减小。 结果， 在常规的 FinFET中， 由于时间常数 RC的值较大而导致延迟增加， 进而降 低了器件的开关速度。
本发明人在美国专利 US7， 087， 952提出了使用 FinFET的一种 NVM， 其中每一个 FinFET 包括位于半导体鳍片一侧上的控制栅极以位于半导体鳍片相对的另一侧上的 浮栅。在浮栅型存储器中， 电荷从衬底隧穿通过第一栅介质层，到达并储存在浮栅中， 在未供电的情况下仍然可以保存。 电荷的数量影响 FinFET的阈值电压 （Vth )， 从而 可以区分逻辑值 1或 0。
本发明人在美国专利 US7， 619， 276提出了使用 FinFET的另一种 NVM， 其中每一 个 FinFET包括位于半导体鳍片一侧上的浮栅， 以及位于半导体鳍片两侧上的控制栅 极， 并且沿着鳍片延伸方向的控制栅极长度大于浮栅长度。
然而， 在上述使用 FinFET的 NVM中， 仍然存在着常规的 FinFET中的问题。 由于 在源 /漏区和栅极之间存在着电容瑀合， 使得 NVM的存取速度较低。 发明内容
本发明的目的是提供一种能够抑制短沟道效应并提高存取速度的 NVM器件。 本发明的另一目的是进一步提供利用应力提高器件性能的 NVM器件。
根据本发明的一方面， 提供一种半导体器件， 包括： S0I衬底； 半导体鳍片， 形 成于 S0I衬底上， 鳍片包括立于 S0I衬底表面相对的第一侧面和第二侧面， 第二侧面 相对于第一侧面的中间位置具有凹槽， 凹槽背离第一侧面开口； 沟道区， 形成于鳍片 上第一侧面与第二侧面的凹槽之间； 源区和漏区， 形成于鳍片上沟道区的两侧； 栅堆 叠， 与鳍片的第一侧面邻接形成在 S0I衬底上； 其中， 栅堆叠包括： 第一栅介质层， 背离第一侧面且与沟道区邻接形成； 第一导体层， 背离第一侧面且与第一栅介质层邻 接形成；第二栅介质层，背离第一侧面且与第一导体层的侧面邻接形成；第二导体层， 背离第一侧面与第二栅介质层的侧面邻接形成。
根据本发明的另一方面， 提供了一种制造半导体器件的方法， 包括： 提供 S0I衬 底； 在 S0I衬底上形成半导体鳍片， 鳍片包括立于 S0I衬底表面且相对的第一侧面和 第二侧面； 在 S0I衬底上形成栅堆叠， 包拮： 背离第一侧面且与沟道区邻接形成第一 栅介质层； 背离第一侧面且与第一栅介质层邻接形成第一导体层； 背离第一侧面且与 第一导体层的侧面邻接形成第二栅介质层；背离第一侧面与第二栅介质层的侧面邻接 形成第二导体层； 在鳍片两端形成源区和漏区； 在鳍片上与第二侧面邻接的位置进行 刻蚀使得第二侧面形成凹槽， 凹槽相对于第一侧面的中间位置且背离第一侧面开口， 则在第一侧面与凹槽之间形成了沟道区。
该半导体器件用作 NVM， 其中栅堆叠中的第一导体层用作存储电荷的浮栅， 第二 导体层用作控制栅。
应当注意，本发明的半导体器件包含半导体鳍片，但其结构不同于常规的 FinFET, 因为其栅极仅设置在鳍片的一个侧面上并背离鳍片延伸， 而常规的 FinFET设置成双 栅结构并包围鳍片的中间部分的沟道区。 而且， 源 /漏区设置在鳍片的两端， 朝着与 栅极的延伸方向相反的方向延伸。
在本发明的半导体器件中没有包括在源 /漏区之间与源 /漏区平行延伸的栅极， 因 此不存在源 /漏区与栅极之间的电容耦合， 从而减小了寄生电容。 进一步地， 本发明 的半导体器件允许通过使用较厚的源 /漏区而减小寄生电阻。
由于源区和漏区的厚度大于沟道区， 能够减小载流子的传导路径长度， 从而进一 步减小与寄生电容和寄生电阻有关的寄生作用。
另外， 还可以在源 /漏区中形成应力层， 用来增加沟道区的应力， 能够提高载流 子的迁移率， 从而进一步提高器件的开关速度。
为了有效地控制短沟道效应， 自对准沟道区非常薄： 约为 5-40rnn。 并且， 在优选 的工艺中， 利用超陡后退阱 （SSRW )工艺进一步减小了沟道区的厚度。 即使仅在沟道 的一侧设置栅极， 沟道区仍然可以受到栅极的完全控制， 从而减小了短沟道效应的影 响。
在最佳的实施例中， 利用鳍片结构的沟道区抑制了沟道效应， 利用沿相反方向背 离鰭片延伸的栅极、 源 /漏区减小了寄生电容和寄生电阻， 同时利用应力层提高了沟 道区中载流子的迁移率。
因而， 本发明的半导体器件提高了 NVM的存取速度和阈值电压， 并且还降低了器 件的功耗。 附图说明
图 1A和 1B是示意性说明根据本发明的半导体器件的结构的三维透视图和俯视 图， 线 Α- Α'、 1- 和 2- 2 ' 表示以下截面图的截取位置。
图 2- 9是根据本发明的制造半导体器件的方法的各个步骤所形成的半导体结构沿 A-A'线的截面图， 其中示出了形成鳍片区域和栅极区域的各个步骤。 图 10-16是根据本发明的制造半导体器件的方法的后续步骤所形成的半导体结构 沿 1-Γ线的截面图， 其中示出了形成源 /漏区的各个步骤。
图 17-18是根据本发明的制造半导体器件的方法的后续步骤所形成的半导体结构 沿 A- A'线的截面图， 其中示出了形成沟道区的各个步骤。
图 19A、 19B、 20A、 20B分别是根据本发明的制造半导体器件的方法的后续步骤 所形成的半导体结构沿 A-A'线和 2-2'线的截面图，其中示出了在源 /漏区和栅极上形 成硅化物层的各个步骤。 具体实施方式
以下将参照附图更详细地描述本发明。 在各个附图中， 相同的元件采用类似的附 图标记来表示。 为了清楚起见， 附图中的各个部分没有按比例绘制。
应当理解， 在描述器件的结构时， 当将一层、 一个区域称为位于另一层、 另一个 区域 "上面"或 "上方" 时， 可以指直接位于另一层、 另一个区域上面， 或者在其与 另一层、 另一个区域之间还包含其它的层或区域。 并且， 如果将器件翻转， 该一层、 一个区域将位于另一层、 另一个区域 "下面"或 "下方" 。
如果为了描述直接位于另一层、 另一个区域上面的情形， 本文将采用 "直接 在……上面"或 "在……上面并与之邻接" 的表述方式。
在下文中描述了本发明的许多特定的细节， 例如器件的结构、 材料、 尺寸、 处理 工艺和技术， 以便更清楚地理解本发明。 但正如本领域的技术人员能够理解的那样， 可以不按照这些特定的细节来实现本发明。
除非在下文中特别指出，半导体器件中的各个部分可以由本领域的技术人员公知 的材料构成。 作为初始结构的 S0I衬底例如包括绝缘体上硅、 绝缘体上硅锗、 以及绝 缘体上的半导体材料叠层。该半导体材料叠层例如包括 III-V族半导体，如 GaAs、InP、 GaN、 SiC；。 栅极导体层可以是金属层、 掺杂多晶硅层、 或包括金属层和掺杂多晶硅层 的叠层栅导体。 导体层的材料为 TaC、 TiN、 TaTbN、 TaErN、 TaYbN、 TaSiN、 HfSiN、 MoSiN、 RuTax、 NiTax, MoNx、 TiSiN、 TiCN、 TaAlC、 TiAlN、 TaN、 PtSix、 Ni3Si、 Pt、 Ru、 Ir、 Mo、 HfRu、 RuOx和所述各种金属材料的组合。 栅介质层可以由 Si02或 介电常数大于 Si02的高 k材料或其他材料构成，例如包括氧化物、氮化物、氧氮化物、 硅酸盐、 铝酸盐、 钛酸盐， 其中， 氧化物例如包括 Si02、 Hf02. Zr02、 A1203、 Ti02、 L¾0:t, 氮化物例如包括 Si ， 硅酸盐例如包括 HfSiOx, 铝酸盐例如包括 LaA10:,， 钛 酸盐例如包括 SrTi03, 氧氮化物例如包括 SiON。并且， 栅介质层不仅可以由本领域的 技术人员公知的材料形成， 也可以采用将来幵发的用于栅介质层的材料。
图 1A和 1B是示意性说明根据本发明的半导体器件的结构的三维透视图和俯视 图。 图 1B中的线 A- A'、 1-1 ' 、 2-2 ' 表示截面图的截取位置， 其中线 A-A' 垂直于 沟道长度方向并经过栅极， 线 1- Γ 沿着沟道长度方向并经过沟道区， 线 2-2' 沿着 沟道长度方向并经过源 /漏区之间的绝缘材料填充物。
为了说明的方便起见， 将图 1B中鳍片的左侧侧面称为第一侧面， 右侧侧面称为 第二侧面。第二侧面与第一侧面中间相对的位置处具有凹槽，凹槽背离第一侧面幵口。
如图 1A和 1B所示， 在 S0I衬底上形成了半导体器件 100， 包括位于半导体鳍片 的中间部分的沟道区 11、 位于其两端的源区 12和漏区 13、 设置在鳍片的第一侧面上 的栅堆叠，包括第一栅介质层 16、第一导体层 17、第二栅介质层 18和第二导体层 19, 以及用于填充鳍片的第二侧面中的凹槽的绝缘材料填充物。 其中， 第一侧面和第二侧 面为立于 S0I衬底上且相对的两个侧面，这两个侧面的方向可以基本垂直于 S0I衬底。
该半导体器件 100用作 NVM，其中栅堆叠中的第一导体层 17用作存储电荷的浮栅， 第二导体层 19用作控制栅。
栅堆叠包括： 第一栅介质层 16, 背离第一侧面且与沟道区 11邻接形成； 第一导 体层 17, 背离第一侧面且与第一栅介质层 16邻接形成； 第二栅介质层 18， 背离第一 侧面且与第一导体层 17的侧面邻接形成； 第二导体层 19， 背离第一侧面与第二栅介 质层 18的侧面邻接形成。
具体地， 鳍片由 S0I衬底中的 S0I层形成。
第二侧面的凹槽内填充有绝缘材料，例如 Si. 。沟道区位于第一侧面与第二侧面 的凹槽之间， 沟道区厚度很薄， 例如在约 5-40nm的范围内。 该厚度与常规的 FinFET 中的沟道区的厚度相近， 并可以采用类似的自对准工艺形成。
本发明人发现， 尽管未采用双栅结构， 但如果沟道区的厚度在上述范围， 位于鳍 片第一侧面的栅极仍然可以作用在整个沟道区上， 从而抑制短沟道效应。
优选地， 该半导体器件还包括用于向源区 12 和漏区 13 施加应力的应力层 ( stressor ) 14和 15。 应力层 14和 15分别与源区 12和漏区邻接， 并且接触面积尽 可能大， 使得应力层 14和 15与源区 12和漏区 13的接触电阻最小。 如图 1A和 1B所 示， 源区 12和漏区 13为台阶形状， 应力层 14和 15位于台阶部分中， 从而应力层 14 和 15的一个侧面及底部与源区 12和漏区 13接触。 应力层 14和 15的材料应当能够在沟道区中产生有利于提高晶体管性能的应力。 当形成的器件是 nMOSFET时， 应力层 14和 15应当向沟道区施加沿源 /漏极方向的拉 应力， 以提高作为载流子的电子的迁移率。相反， 当晶体管是 PM0SFET时， 应力层 14 和 15应当向沟道区施加沿源 /漏极方向的压应力，以提高作为载流子的空穴的迁移率。
应当注意， 在图 1A和 1B所示的半导体器件结构的实例中， 应力层 14、 15分别 位于源区 12与源极接触 （未示出）、 漏区 13与漏极接触 （未示出） 之间的导电路径 上， 因此应力层 14、 15还应当是导电性的。 对于 π型 M0SFET, 可以采用掺 As或 P 的 Si : C材料， 而对于 p型 M0SFET, 可以采用掺杂 B或 In的 SiGe材料。
在图 1A和 1B中没有示出源区 12、 漏区 13及栅极导体 19上方的附加层和部分， 例如栅极的侧墙、 硅化物层、 源极接触、 漏极接触和栅极接触、 层间绝缘层、 在层间 绝缘层中形成的通孔以及钝化层等。
在下文描述制造该半导体器件的步骤中，将说明与该半导体器件密切相关的一些 附加层和部分， 但省去了对本领域公知的那些附加层和部分（如源极接触、 漏极接触 和栅极接触） 的详细描述。 为了简明起见， 可以在一幅图中描述经过数个步骤后获得 的半导体结构。
参见图 2， 本发明的制造半导体器件的方法开始于 S0I衬底， S0I衬底是包括底 部衬底 21、 BOX (Buried Oxide, 埋氧层） 22和顶部半导体层 23的叠层。
通过已知的淀积工艺， 如 PVD、 CVD、 原子层淀积、 溅射等， 在 S0I晶片上依次外 延生长 Ge含量约为 5-15%、 厚度约为 3- 20nm的 SiGe层 24和厚度约为 30- lOOnm的 Si层 25。 Si层 25可以在单独的淀积步骤中形成，也可以在外延生长 SiGe层 24之后 通过使用 Si靶或前体原位形成。
然后，通过原子层淀积、磁控溅射或其他方法，在 Si层 25上形成厚度约为 3- lOrim 的 Hf02层 26。
参见图 3， 通过包括曝光和显影步骤的常规光刻工艺， 在 Hf02层 26上形成了条 形的光抗蚀剂图案 27。
参见图 4， 利用光抗蚀图案 27作为掩模， 通过干法蚀刻， 如离子铣蚀刻、 等离子 蚀刻、 反应离子蚀刻、 激光烧蚀或其他方法， 去除 Hf02层 26、 Si层 25、 SiGe层 24 的一部分， 形成 Hf02层 26、 Si层 25、 SiGe层 24的构图的叠层结构。
如果采用反应离子蚀刻， 可以分为两个步骤进行。 在第一步骤， 选择蚀刻气氛的 气体组分， 使得去除 02层 26和 Si层 25的一部分， 并在 SiGe层 24顶部停止。 在 第二步骤， 通过改变蚀刻气氛的气体组分， 使得去除 SiGe层 24的一部分， 并在 S0I 衬底的顶部半导体层 23上停止。 本领域的技术人员已知在反应离子蚀刻中， 可以通 过改变蚀刻气氛的气体组分控制材料的选择性去除 SiGe层和 Si层中的一种。
然后， 通过在溶剂中溶解或灰化去除光抗蚀剂图案 27。
在构图的叠层结构和 S0I 衬底的顶部半导体层 23 的暴露部分上形成厚度约为 2-5nm的共形氧化物层 28。
氧化物薄层可通过己知的淀积工艺形成， 如 PVD、 CVD、 原子层淀积、 溅射等。 然后， 首先形成共形氮化物层， 然后去除该层的一部分， 从而在包括 Hf02层 26、 Si层 25、 SiGe层 24的叠层结构两侧形成厚度约为 5-50nm的氮化物侧墙 29。
参见图 5， 通过包括曝光和显影步骤的常规光刻工艺， 在图 4所示的结构上形成 光抗蚀剂层图案 30， 以遮挡左侧的侧墙以及构图的叠层结构的左侧部分。
利用抗蚀剂图案 30作为掩模， 通过各向同性蚀刻， 例如使用蚀刻剂溶液的常规 湿法蚀刻， 去除右侧的侧墙。
替代地， 可以分为三个歩骤去除右侧的侧墙。 在第一步骤， 利用抗蚀剂图案 30 作为掩模， 利用倾角离子注入在右侧的侧墙中注入 Ge 以造成缺陷。 在第二步骤， 通 过在溶剂中溶解或灰化去除光抗蚀剂图案 30。在第三步骤，通过湿法蚀刻或干法蚀刻， 相对于左侧的侧墙选择性地去除右侧的侧墙。
参见图 6， 在去除右侧的侧墙之后， 选择蚀刻气氛的气体组分， 例如通过反应离 子蚀刻选择性地去除氧化物层 28在半导体结构的表面上暴露的部分。 接着， 利用氧 化物层 28的剩余部分、 侧墙 29和包括 Hf02层 26、 Si层 25、 SiGe层 24的叠层结构 作为硬掩模， 改变蚀刻气氛的气体组分， 例如通过反应离子蚀刻选择性去除 S0I衬底 的顶部半导体层， 即 S0I层的暴露部分， 以自对准的方式形成半导体鳍片 23' 。
参见图 7， 例如通过 CVD (化学气相淀积）或 ALD (原子层淀积）， 在图 6所示的 半导体结构表面上依次形成厚度约为 2- 4nm的共形氧化物（如 Hf02)薄层 26 ' 、厚度 约为 3- lOnm的共形金属 （如 TiN， 金属陶瓷）层 31、 厚度约为 5- 15nm的共形氮化物 层 32、 以及覆盖的多晶硅层 33。 在随后的步骤中， 氧化物薄层 26'、 金属层 31、 氮 化物层 32和多晶硅层 33将分别形成第一栅介质层 16、 第一导体层 17、 第二栅介质 层 18和第二导体层 19。 第一栅介质层 16、 第一导体层 17、 第二栅介质层 18和第二 导体层 19可以参照前述的栅介质层和栅极导体的材料选择。
优选地， 可以对多晶硅层 33进行原位掺杂以提高导电性。 多晶硅层 33覆盖半导体结构的整个顶部。 然后， 对多晶硅层 33进行平面化处理 ( CMP ) o 该平面化处理停止在氮化物层 32的顶部， 从而获得了半导体结构的平整表 面。
参见图 8， 通过湿法蚀刻或千法蚀刻， 相对于氮化物层 32选择性地去除多晶硅 层 33的一部分， 对多晶硅层 33进行回蚀刻。 然后， 例如通过 CVD, 在半导体结构的 整个表面上形成覆盖的氧化物层 34。
对氧化物层 34进行平面化处理，该平面化处理去除氮化物层 32的位于鳍片 23 ' 上方的一部分， 并且停止在金属层 31 的顶部， 从而获得了半导体结构的平整表面。 结果， 氧化物层 34填充了多晶硅层 33的通过回蚀刻去除的部分。
然后， 例如通过 CVD, 在半导体结构的表面上形成氮化物层 35。
参见图 9， 通过包括曝光和显影步骤的常规光刻工艺， 形成条形的光抗蚀剂图案 36 , 用于限定器件的栅极区域。
然后， 利用光抗蚀剂图案 36作为掩模， 通过干法蚀刻， 如离子铣蚀刻、 等离子 蚀刻、 反应离子蚀刻、 激光烧蚀， 依次去除氮化物层 35、 氧化物层 34、 多晶硅层 33、 氮化物层 32、 金属层 31、 氧化物薄层 26 ' 的位于鳍片 23 ' 两侧的一部分， 该蚀刻在 S0I衬底中的 BOX 22的顶部停止。
与图 9所示的半导体结构沿 A-A' 线的截面图相对应，在图 10中示出了半导体结 构沿卜 线的截面图。 利用光抗蚀图案 36作为掩模的蚀刻步骤获得了位于 S i层 25 上方的氮化物层 35、 金属层 31、 氧化物薄层 26 ' 的叠层。
在上述蚀刻步骤之前或之后， 通过附加的掩模形成步骤和蚀刻步骤， 可以去除鳍 片 23 ' 、 SiGe层 24和 Si层 25的一部分， 以限定鳍片的长度。 在图 10中示出了由 此限定的鰭片 23'沿水平方向的尺寸 L。
参见图 11， 仍然利用光抗蚀剂图案 36作为掩模， 通过干法蚀刻， 如离子铣蚀刻、 等离子蚀刻、 反应离子蚀刻、 激光烧蚀， 依次去除 Si层 25和 SiGe层 24的一部分， 该蚀刻在鳍片 23 ' 的顶部停止。 结果， 在鳍片 23 ' 上方形成了包括氮化物层 35、 金 属层 31、 氧化物薄层 26， 、 Si层 25、 SiGe层 24的多层叠层 101。
参见图 12， 通过在溶剂中溶解或灰化去除光抗蚀剂图案 36。
然后， 例如通过 CVD， 在半导体结构的整个表面上依次形成厚度约为 2- 5nm的共 形氧化物层 37和厚度约为 10- 20nm的共形氮化物层 38。
通过干法蚀刻， 如离子铣蚀刻、 等离子蚀刻、 反应离子蚀刻、 激光烧蚀， 去除氮 化物层 38的一部分，该蚀刻在氧化物层 37的表面停止，从而在鳍片 23' 和多层叠层 101的两侧分别形成氮化物侧墙 38。
参见图 13， 利用多层叠层 101及两侧的氮化物侧墙 38作为硬掩模， 通过干法蚀 刻， 如离子铣蚀刻、 等离子蚀刻、 反应离子蚀刻、 激光烧蚀， 去除氧化物层 37的暴 露表面及鳍片 23 ' 的一部分半导体材料， 从而在鳍片 23沿长度方向 （即图中的水平 方向）的两端形成开口 39。在开口 39的底部保留了厚度约为 lOrnn的半导体材料薄层， 这一半导体材料薄层即为 S0I衬底中的 S0I层的一部分。
该蚀刻步骤是自对准的，其中开口 39的尺寸基本上由氧化物层 37和氮化物侧墙 38确定。
图 14示出了某些实施例中的可选步骤， 利用倾角离子注入从幵口 39向鳍片 23' 的中间部分进行晕环注入 （halo implantation)。 对于 nMOSFET, 采用 B或 BF2作为 掺杂剂。 对于 pMOSFET, 采用 As或 P作为掺杂剂。
图 15示出了某些实施例中的可选步骤，利用倾角离子注入向鳍片 23'的中间部分 进行延伸注入 ( extension implantation 对于 n型 M0SFET, 采用 As或 P作为掺杂 剂。 对于 p型 M0SFET, 采用 B或 BF2作为掺杂剂。
与晕环注入相比， 延伸注入采用的倾角较小而能量较大， 从而在延伸注入中， 大 多数注入的离子穿过开口 39底部的半导体材料薄层， 使得该半导体材料薄层没有非 晶化。
可选地， 可以进行适量的源 /漏区离子注入。
由于幵口 39提供了离子注入的窗口， 并且位于半导体结构的表面上的氮化物层 35、 氧化物层 37、 氮化物侧墙 38提供了硬掩模， 因此上述延伸注入、 晕环注入和源 / 漏区注入可以在原位进行， 从而减少了掩模数量并简化了工艺。
参见图 16，对所形成的半导体结构进行退火处理，例如尖峰退火（spike anneal 退火步骤用来激活通过先前的注入步骤而注入的掺杂剂并消除注入导致的损伤。
经过退火处理之后， 在半导体鳍片 23' 中的掺杂剂分布如图 16中所示， 在开口 39的底部分别形成了源区 12和漏区 13，在与源区 12和漏区 13相邻的位置分别形成 了源延伸区 12 ' 和漏延伸区 13 ' ，在与源延伸区 12 ' 和漏延伸区 13' 相邻并朝着鳍 片 23 ' 的中间部分延伸的位置分别形成了源晕环区 12"和漏晕环区 13 " 。
然后， 通过己知的淀积工艺， 如 PVD、 CVD、 原子层淀积、 溅射等， 在开口 39中 依次外延生长应力层 40及其上的外延硅层 41。由于外延生长，应力层 40仅形成在开 口 39底部的半导体材料薄层上， 从而不需要使用额外的掩模。对于 pMOSFET, 应力层 40的材料是 Ge含量约为 20- 50%的 SiGe并原位掺 B，外延生长后，在沟道区延源漏方 向产生压应力， 这可以增强 pMOSFET的性能。 对于 nMOSFET, 应力层 40的材料是 C 含量约为 0. 5- 2%的 Si : C并原位掺 As或！3， 外延生长后， 在沟道区延源漏方向产生拉 应力， 这可以增强 nMOSFET的性能。
然后， 对所形成的半导体结构进行氧化处理， 外延硅层 41 的顶部发生氧化从而 形成厚度约为 3- lOrim的氧化薄层 37'。在应力层 40的顶部形成的外延硅层 41用于获 得良好质量的 Si02。
参见图 17， 利用在图 8所示的步骤中形成的氧化物层 34作为硬掩模， 通过干法 蚀刻， 如离子铣蚀刻、 等离子蚀刻、 反应离子蚀刻、 激光烧蚀， 依次去除金属层 31、 氮化物薄层 26' 、 Si层 25、 SiGe层 24、 鳍片 23' 的一部分， 该蚀刻在 S0I衬底的 BOX 22顶部停止， 从而以自对准的方式形成开口 42。 在步骤中， 氧化物层 28和氮化 物侧墙 29作为限定鳍片 23' 的中间位置厚度的硬掩模， 也即， 鳍片 23' 的中间位置 的厚度减小到大致等于氧化物层 28和氮化物侧墙 29的厚度之和的数值。即在本步骤 中将鳍片的中部形成凹槽， 并如下文所述， 该鳍片的中间位置将用于形成沟道区 11。 由于蚀刻所去除的材料（即包括 Si/SiGe/Si的叠层），在沟道区中的应力进一步增加， 此应力可进一步增强器件性能。
在幵口 42的右侧保留着包括氮化物薄层 26 ' 、金属层 31、氮化物层 32、 多晶硅 层 33、氧化物层 34的一部分的叠层材料。在制造含有相同结构的多个 M0SFET的集成 电路时， 位于开口 42右侧的叠层材料可以作为相邻的 M0SFET (未示出）的栅极区域， 而开口 42中的填充材料可以起到浅沟隔离区的作用。
此外， 在图 12所示步骤中形成的氮化物侧墙 38还存在于栅堆叠的侧面上。 在优选的工艺中， 还可以利用超陡后退阱（SSRW)工艺进一步减小鳍片 23' 的厚 度。 该 SSRW设置在鰭片 23 ' 中邻接沟道区并靠近鳍片的与邻接氮化物薄层 26' 的 第一侧面相对的第二侧面的位置。 有关 SSRW的形成工艺可参见以下文件：
1 ) G. G. Shahidi, D. A. Antoniadis and H. I. Smith, IEEE TED Vol. 36, p. 2605,
1989
2 ) C. Fiegna, H. Iwai, T. Wada, . Saito, E. Sangiorgi and B. Ricco, IEEE TED Vol. 41, p. 941, 1994.
3 ) J. B. Jacobs and D. A. Antoniadis, IEEE TED Vol. 42, p. 870, 1995. 4 ) S. E. Thompson, P. A. Packan and M. T. Bohr, VLSI Tech Symp. , p. 154, 1996. 然后， 执行如下两个步骤去除左侧的侧墙 38。 在第一步骤， 利用氧化物层 34作 为掩模， 利用倾角离子注入在左侧的侧墙中注入 Ge以造成损伤。 在第二步骤， 通过 湿法蚀刻或干法蚀刻， 相对于右侧的侧墙选择性地去除左侧的侧墙。
参见图 18， 例如通过 CVD, 在半导体结构的整个表面上形成厚度约为 2- 5ηπι的共 形氧化物薄层 34 ' 。 然后， 例如通过 CVD淀积氮化物， 其厚度至少能够填充幵口 42。 相对于氧化物层 34' ， 选择性地回蚀刻氮化物， 使得完全去除开口周围的氮化物层， 仅在幵口中留下氮化物填充材料 43。
参见图 19A和 19B， 通过干法蚀刻， 如离子铣蚀刻、 等离子蚀刻、 反应离子蚀刻、 激光烧蚀， 相对于氮化物填充材料 43选择性地去除氧化物层 34' 的暴露部分。
该蚀刻只留下氧化物层 34' 在己填充的开口侧壁和底部的部分，从而暴露出栅堆 叠中的多晶硅层 33的上表面和左侧表面， 以及源极区域和漏极区域的外延硅层 41的 上表面。 ' 该蚀刻也去除了 S0I衬底的掩埋氧化物层 22的一部分。
参见图 20A和 20B，利用常规的硅化工艺，将栅堆叠中的多晶硅层 33的上表面和 左侧表面的一部分， 以及源极区域和漏极区域的外延硅层 41 的至少一部分， 转化为 硅化物层 44， 以减小栅极、 源 /漏极与相应的金属接触之间的接触电阻。
例如，首先淀积厚度约为 5-12nm的 Ni层，然后在 300-500°C的温度下热处理 1 - 10 秒钟，使得多晶硅层 33和外延硅层 41的至少一部分形成 NiSi ,最后利用湿法蚀刻去 除未反应的 Ni。
在完成图 2- 20所示的步骤之后， 按照本领域公知的方法， 在所得到的半导体结 构上形成层间绝缘层、 位于层间绝缘层中的通孔、位于层间绝缘层上表面的布线或电 极， 从而完成半导体器件的其它部分。
以上描述只是为了示例说明和描述本发明， 而非意图穷举和限制本发明。 因此， 本发明不局限于所描述的实施例。 对于本领域的技术人员明显可知的变型或更改， 均 在本发明的保护范围之内。

Claims

权 利 要 求
1、 一种半导体器件， 包括：
S0I衬底； '
半导体鳍片， 形成于所述 S0I衬底上， 所述鳍片包括立于所述 S0I衬底表面相对 的第一侧面和第二侧面， 所述第二侧面相对于第一侧面的中间位置具有凹槽， 所述凹 槽背离所述第一侧面幵口；
沟道区， 形成于所述鳍片上第一侧面与第二侧面的凹槽之间；
源区和漏区， 形成于所述鳍片上所述沟道区的两侧；
栅堆叠， 与所述鳍片的第一侧面邻接形成在所述 S0I衬底上；
其中， 所述栅堆叠包括： 第一栅介质层， 背离所述第一侧面且与所述沟道区邻接 形成； 第一导体层， 背离所述第一侧面且与所述第一栅介质层邻接形成； 第二栅介质 层， 背离所述第一侧面且与所述第一导体层的侧面邻接形成： 第二导体层， 背离所述 第一侧面与所述第二栅介质层的侧面邻接形成。
2、 根据权利要求 1所述的半导体器件， 其中所述源区和漏区延伸到所述半导体 鳍片上所述凹槽的两侧。
3、 根据权利要求 1所述的半导体器件， 其中所述鳍片上的第二侧面的凹槽内填 充有介质材料。
4、 根据权利要求 1所述的半导体器件， 其中所述沟道区的厚度为 5- 40nm。
5、 根据权利要求 1所述的半导体器件， 进一步包括超陡后退阱， 形成于所述沟 道区与所述第二侧面的凹槽之间。
6、根据权利要求 1所述的半导体器件，其中所述第一导体层或第二导体层由 Ta (：、 TiN、 TaTbN、 TaErN、 TaYbN、 TaSiN、 HfSiN、 MoSiN、 RuTa NiTa,、 MoNx、 TiSiN、 TiCN、 TaAlC, TiAlN、 TaN、 PtSi,、 N S Pt、 Ru、 Ir、 Mo、 HfRu、 RuOx中的一种或多种的 组合形成。
7、 根据权利要求 1至 6中任一项所述的半导体器件还包括应力层， 所述应力层 设置在所述源区和漏区上， 并用于向所述源区和漏区施加应力。
8、 根据权利要求 7所述的半导体器件， 其中所述源区和漏区的形状为凹进的台 阶， 所述应力层设置在所述台阶部分中。
9、 根据权利要求 7所述的半导体器件， 其中所述应力层由 SiGe或 Si :C形成。
10、 根据权利要求 1至 6中任一项所述的半导体器件， 其中所述源区和漏区进一 步包括： 与所述源区和漏区邻接并朝着所述沟道区延伸的源延伸区和漏延伸区。
11、 根据权利要求 1至 6中任一项所述的半导体器件， 其中所述源区和漏区进一 步包括： 与所述源区和漏区邻接并朝着所述沟道区延伸的源晕环区和漏晕环区。
12、 根据权利要求 1至 6中任一项所述的半导体器件， 其中所述半导体鳍片由 所述 S0I衬底上的 S0I层形成。
13、 根据权利要求 12所述的半导体器件， 其中所述半导体鳍片形成在 BOX层上。
14、 一种制造半导体器件的方法， 包括：
提供 S0I衬底；
在所述 S0I衬底上形成半导体鳍片，所述鳍片包括立于所述 S0I衬底表面且相对 的第一侧面和第二侧面；
在所述 S0I衬底上形成栅堆叠， 包括： 背离所述第一侧面且与所述沟道区邻接形 成第一栅介质层； 背离所述第一侧面且与所述第一栅介质层邻接形成第一导体层； 背 离所述第一侧面且与所述第一导体层的侧面邻接形成第二栅介质层；背离所述第一侧 面与所述第二栅介质层的侧面邻接形成第二导体层；
在所述鳍片两端形成源区和漏区；
在所述鳍片上与所述第二侧面邻接的位置进行刻蚀使得所述第二侧面形成凹槽， 所述凹槽相对于所述第一侧面的中间位置且背离所述第一侧面幵口，则在所述第一侧 面与所述凹槽之间形成了沟道区。
15、 根据权利要求 14所述的方法， 其中形成半导体鳍片包括：
在所述 S0I衬底上构图形成叠层结构， 所述叠层结构包括 SiGe层、 Si层和绝缘 层；
在所述叠层结构的第一侧壁上形成阻挡层和氮化物侧墙； 以及
以所述阻挡层、 氮化物侧墙、 以及叠层结构为硬掩模， 选择性刻蚀所述 S0I衬底 上的 S0I层， 以形成半导体鳍片。
16、 根据权利要求 15所述的方法， 其中， 在所述鳍片上与所述第二侧面邻接的 位置进行刻蚀使得所述第二侧面形成凹槽， 包括：
以所述阻挡层、氮化物侧墙作为硬掩膜，对所述叠层结构和半导体鳍片进行刻蚀。
17、 根据权利要求 14所述的方法， 在形成沟道区之后， 进一步包括：
在所述第一侧面与所述凹槽之间形成超陡后退阱。
18、 根据权利要求 14所述的方法， 在所述鳍片两端形成源区和漏区包括- 在所述半导体鳍片的两端形成幵口， 所述开口的底部保留预定厚度的 S0I层， 以 形成源区和漏区；
19、 根据权利要求 18所述的方法， 进一步包括在所述幵口中外延生长 SiGe或 Si : C， 从而形成应力层。
20、 根据权利要求 19所述的方法， 在外延生长 SiGe或 Si : C之前， 该方法还包 括：
采用倾角离子注入， 从开口向鳍片的中间部分进行延伸注入以形成延伸区。
21、 根据权利要求 19所述的方法， 在外延生长 SiGe或 Si :C之前， 该方法还包 括：
釆用倾角离子注入， 从开口向鳍片的中间部分进行晕环注入以形成晕环区。
22、 根据权利要求 14至 21任一项所述的方法， 进一步包括： 在所述凹槽中填充 介质材料。
PCT/CN2010/001486 2010-06-30 2010-09-26 半导体器件及其制造方法 WO2012000146A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US13/003,873 US8598595B2 (en) 2010-06-30 2010-09-26 Semiconductor device and method for manufacturing the same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201010223470.6 2010-06-30
CN2010102234706A CN102315265B (zh) 2010-06-30 2010-06-30 半导体器件及其制造方法

Publications (1)

Publication Number Publication Date
WO2012000146A1 true WO2012000146A1 (zh) 2012-01-05

Family

ID=45401292

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2010/001486 WO2012000146A1 (zh) 2010-06-30 2010-09-26 半导体器件及其制造方法

Country Status (3)

Country Link
US (1) US8598595B2 (zh)
CN (1) CN102315265B (zh)
WO (1) WO2012000146A1 (zh)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102315265B (zh) * 2010-06-30 2013-12-04 中国科学院微电子研究所 半导体器件及其制造方法
KR102255174B1 (ko) 2014-10-10 2021-05-24 삼성전자주식회사 활성 영역을 갖는 반도체 소자 및 그 형성 방법
CN104730111A (zh) * 2015-03-27 2015-06-24 中国科学院上海微***与信息技术研究所 基于Si/SiGe/Si量子阱MOSFET的生物传感器及其制备方法
KR102326316B1 (ko) * 2015-04-10 2021-11-16 삼성전자주식회사 반도체 소자의 제조 방법
US10903210B2 (en) * 2015-05-05 2021-01-26 International Business Machines Corporation Sub-fin doped bulk fin field effect transistor (FinFET), Integrated Circuit (IC) and method of manufacture
WO2018111223A1 (en) * 2016-12-12 2018-06-21 Intel Corporation Hybrid finfet structure with bulk source/drain regions
CN108447914A (zh) * 2018-02-05 2018-08-24 华东师范大学 一种基于vo2的柔性薄膜晶体管及其应用

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6413802B1 (en) * 2000-10-23 2002-07-02 The Regents Of The University Of California Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture
CN1731589A (zh) * 2004-08-05 2006-02-08 株式会社东芝 半导体装置及其制造方法
US20070252211A1 (en) * 2006-04-26 2007-11-01 Atsushi Yagishita Semiconductor device and manufacturing method for semiconductor device
US20080171408A1 (en) * 2007-01-12 2008-07-17 International Business Machines Corporation Methods for forming dual fully silicided gates over fins of finfet devices

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6458662B1 (en) * 2001-04-04 2002-10-01 Advanced Micro Devices, Inc. Method of fabricating a semiconductor device having an asymmetrical dual-gate silicon-germanium (SiGe) channel MOSFET and a device thereby formed
CN100378901C (zh) * 2002-11-25 2008-04-02 国际商业机器公司 应变鳍型场效应晶体管互补金属氧化物半导体器件结构
KR100577562B1 (ko) * 2004-02-05 2006-05-08 삼성전자주식회사 핀 트랜지스터 형성방법 및 그에 따른 구조
US7002214B1 (en) * 2004-07-30 2006-02-21 International Business Machines Corporation Ultra-thin body super-steep retrograde well (SSRW) FET devices
US7087952B2 (en) * 2004-11-01 2006-08-08 International Business Machines Corporation Dual function FinFET, finmemory and method of manufacture
US7589387B2 (en) * 2005-10-05 2009-09-15 Taiwan Semiconductor Manufacturing Company, Ltd. SONOS type two-bit FinFET flash memory cell
US7361551B2 (en) * 2006-02-16 2008-04-22 Freescale Semiconductor, Inc. Method for making an integrated circuit having an embedded non-volatile memory
US7619276B2 (en) * 2007-07-30 2009-11-17 International Business Machines Corporation FinFET flash memory device with an extended floating back gate
US7898021B2 (en) * 2007-10-26 2011-03-01 International Business Machines Corporation Semiconductor fin based nonvolatile memory device and method for fabrication thereof
US7898857B2 (en) * 2008-03-20 2011-03-01 Micron Technology, Inc. Memory structure having volatile and non-volatile memory portions
CN102034865B (zh) * 2009-09-30 2012-07-04 中国科学院微电子研究所 半导体器件及其制造方法
CN102117828B (zh) * 2009-12-30 2013-02-06 中国科学院微电子研究所 半导体器件及其制造方法
EP2400498B1 (en) * 2010-06-25 2014-10-15 IMEC vzw Methods for operating a semiconductor device
CN102315265B (zh) * 2010-06-30 2013-12-04 中国科学院微电子研究所 半导体器件及其制造方法
CN102315224B (zh) * 2010-07-07 2014-01-15 中国科学院微电子研究所 使用FinFET的非易失性存储器件及其制造方法
US8247278B2 (en) * 2010-12-31 2012-08-21 Institute of Microelectronics, Chinese Academy of Sciences Method for manufacturing semiconductor device
US8962400B2 (en) * 2011-07-07 2015-02-24 Taiwan Semiconductor Manufacturing Company, Ltd. In-situ doping of arsenic for source and drain epitaxy
US8486770B1 (en) * 2011-12-30 2013-07-16 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming CMOS FinFET device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6413802B1 (en) * 2000-10-23 2002-07-02 The Regents Of The University Of California Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture
CN1731589A (zh) * 2004-08-05 2006-02-08 株式会社东芝 半导体装置及其制造方法
US20070252211A1 (en) * 2006-04-26 2007-11-01 Atsushi Yagishita Semiconductor device and manufacturing method for semiconductor device
US20080171408A1 (en) * 2007-01-12 2008-07-17 International Business Machines Corporation Methods for forming dual fully silicided gates over fins of finfet devices

Also Published As

Publication number Publication date
CN102315265A (zh) 2012-01-11
US8598595B2 (en) 2013-12-03
US20130161642A1 (en) 2013-06-27
CN102315265B (zh) 2013-12-04

Similar Documents

Publication Publication Date Title
US8741703B2 (en) Method for manufacturing FinFET with improved short channel effect and reduced parasitic capacitance
US8710556B2 (en) Semiconductor device comprising a Fin and method for manufacturing the same
US7759737B2 (en) Dual structure FinFET and method of manufacturing the same
US7388259B2 (en) Strained finFET CMOS device structures
US7538351B2 (en) Method for forming an SOI structure with improved carrier mobility and ESD protection
WO2013134899A1 (zh) 半导体器件及其制造方法
WO2012100463A1 (zh) 一种形成半导体结构的方法
WO2011127634A1 (zh) 半导体器件及其制造方法
US8598595B2 (en) Semiconductor device and method for manufacturing the same
US9929267B2 (en) N-type fin field-effect transistor and fabrication method thereof
US20120146142A1 (en) Mos transistor and method for manufacturing the same
US20150200275A1 (en) Finfet and method for manufacturing the same
CN103824775A (zh) FinFET及其制造方法
WO2013166733A1 (zh) FinFET及其制造方法
WO2014071754A1 (zh) 半导体结构及其制造方法
CN103779223A (zh) Mosfet的制造方法
WO2013159416A1 (zh) 一种半导体结构及其制造方法
WO2013053167A1 (zh) Mosfet及其制造方法
US10892339B2 (en) Gate first technique in vertical transport FET using doped silicon gates with silicide
WO2014131239A1 (zh) 半导体器件及其制造方法
US9142677B2 (en) FinFET having gate in place of sacrificial spacer source/drain mask
US20240113198A1 (en) Method of modulating multi-gate device channels and structures thereof
WO2014131240A1 (zh) 半导体器件的制造方法
WO2014121539A1 (zh) 半导体器件及其制造方法
WO2014071660A1 (zh) 半导体器件及其制造方法

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 13003873

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 10853852

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 10853852

Country of ref document: EP

Kind code of ref document: A1