WO2011141973A1 - Semiconductor device and method for manufacturing same - Google Patents

Semiconductor device and method for manufacturing same Download PDF

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Publication number
WO2011141973A1
WO2011141973A1 PCT/JP2010/005995 JP2010005995W WO2011141973A1 WO 2011141973 A1 WO2011141973 A1 WO 2011141973A1 JP 2010005995 W JP2010005995 W JP 2010005995W WO 2011141973 A1 WO2011141973 A1 WO 2011141973A1
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film
insulating film
gate insulating
gate
metal
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PCT/JP2010/005995
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French (fr)
Japanese (ja)
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中村成志
粉谷直樹
玉置徳彦
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パナソニック株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823456—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different shapes, lengths or dimensions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/82385—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different shapes, lengths or dimensions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane

Definitions

  • the present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, a semiconductor device including MISFETs (Metal Insulator Semiconductor Semiconductor Field Field Effect Transistor) having different gate widths and having a gate insulating film containing an adjustment metal. About.
  • MISFETs Metal Insulator Semiconductor Semiconductor Field Field Effect Transistor
  • the gate insulating film For the miniaturization of LSI, it is required to make the gate insulating film thinner. Therefore, in recent years, it has been studied to apply a high dielectric constant insulating film such as a hafnium (Hf) -based oxide film as the gate insulating film. Thereby, the electrical film thickness of the gate insulating film can be reduced while increasing the physical film thickness of the gate insulating film to suppress the leakage current.
  • a high dielectric constant insulating film such as a hafnium (Hf) -based oxide film
  • the threshold voltage of the MISFET (hereinafter referred to as MIS transistor) increases due to a phenomenon called Fermi level pinning.
  • MIS transistor the threshold voltage of the MISFET
  • the gate capacitance is reduced, a high electric field cannot be applied under the gate electrode, and the driving capability of the MIS transistor is reduced.
  • lanthanum La
  • a technique using an Hf-based oxide film has been proposed (see, for example, Patent Document 1).
  • the reason why the effective work function of the n-type MOS transistor can be shifted to the band edge side by using an Hf-based oxide film containing La as the gate insulating film is as follows. When La is included in the Hf-based oxide film, the flat band voltage shifts to the minus side, and therefore the effective work function of the n-type MOS transistor can be shifted to the band edge side.
  • FIG. 6 is a cross-sectional view in the gate length direction showing the configuration of a conventional semiconductor device.
  • the conventional semiconductor device shown in FIG. 6 includes an n-type MOS transistor nTr1 and a p-type MOS transistor pTr.
  • an element isolation region 102 is formed on the silicon substrate 101.
  • a P well diffusion layer 103 is formed in the first NMOS region of the silicon substrate 101.
  • an N well diffusion layer 104 is formed in the PMOS region of the silicon substrate 101.
  • a gate insulating film 117a and a gate electrode 116a are sequentially formed on the first NMOS region of the silicon substrate 101.
  • a gate insulating film 117b, a SiN film 109b, a La (O) film 111b, and a gate electrode 116b are sequentially formed on the PMOS region in the silicon substrate 101.
  • Source / drain diffusion layers 120a and 120b are formed below the sides of the gate electrodes 116a and 116b in the silicon substrate 101, respectively.
  • the gate insulating film 117a includes a silicon oxide film 105a and a high dielectric constant gate insulating film (HfSiO film containing La) 106a.
  • the gate insulating film 117b includes the silicon oxide film 105b and the HfSiON film 110b not including La.
  • the gate electrode 116a includes a WSi film 114a, a barrier metal 113a, and a doped polycrystalline silicon film 115a.
  • the gate electrode 116b includes a W film 112b, a barrier metal 113b, and a doped polycrystalline silicon film 115b.
  • FIG. 7 is a cross-sectional view in the gate width direction showing the configuration of a conventional semiconductor device.
  • the same components as those shown in FIG. 6 are denoted by the same reference numerals as those shown in FIG. Therefore, in the description of FIG. 7, the description similar to the description of FIG.
  • the conventional semiconductor device shown in FIG. 7 includes n-type MOS transistors nTr2 and nTr1, and a p-type MOS transistor pTr.
  • the gate width WTr2 of the n-type MOS transistor nTr2 is smaller than the gate width WTr1 of the n-type MOS transistor nTr1 (WTr2 ⁇ WTr1).
  • the semiconductor device shown in FIG. 7 includes the following components in addition to the same components as the semiconductor device shown in FIG. 7
  • a gate insulating film 117c and a gate electrode 116c are sequentially formed.
  • An SiN film 118c and a TEOS film 119c are sequentially formed on the side surface of the gate electrode 116c.
  • the figure shown in FIG. 7 is a cross-sectional view in the gate width direction and not in the gate length direction. Therefore, although not shown in FIG. A drain diffusion layer is formed.
  • the gate insulating film 117c includes a silicon oxide film 105c and a high dielectric constant gate insulating film (HfSiO film containing La) 106c.
  • the gate electrode 116c includes a WSi film 114c, a barrier metal 113c, and a doped polycrystalline silicon film 115c.
  • boron (B) or the like is provided immediately below the gate electrodes 116c and 116a in the active regions 101c and 101a.
  • P-type channel regions 121c and 121a containing p-type impurities are formed.
  • an n-type channel region 121b containing an n-type impurity is formed immediately below the gate electrode 116b in the active region 101b.
  • the p-type impurity contained in the channel regions 121c and 121a is diffused into the element isolation region 102 by the heat treatment performed after the formation of the channel regions 121c and 121a.
  • the gate width WTr2 is smaller than the gate width WTr1 (WTr2 ⁇ WTr1), the channel width of the channel region 121c is smaller than the channel width of the channel region 121a. For this reason, the proportion of the diffusion amount M121c in the channel region 121c is relatively large, while the proportion of the diffusion amount M121a in the channel region 121a is relatively small.
  • the average impurity concentration Y121c of the p-type impurity in the channel region 121c after manufacture is the average impurity concentration of the p-type impurity in the channel region 121c immediately after formation. It is significantly lower than X121c (Y121c ⁇ X121c).
  • the average impurity concentration Y121a of the p-type impurity in the channel region 121a after manufacture is the average of the p-type impurity in the channel region 121a immediately after formation.
  • the average impurity concentration Y121c of the p-type impurity in the channel region 121c after manufacture is lower than the average impurity concentration Y121a of the p-type impurity in the channel region 121a after manufacture (Y121c ⁇ Y121a).
  • the threshold voltage of the n-type MOS transistor decreases. For this reason, the threshold voltage of the n-type MOS transistor nTr2 is lower than the threshold voltage of the n-type MOS transistor nTr1.
  • the threshold voltage of the n-type MOS transistor is lowered. That is, the reverse narrow channel effect occurs in which the threshold voltage of the MOS transistor decreases as the gate width decreases.
  • the threshold voltages of the n-type MOS transistors nTr2 and nTr1 are lowered by using HfSiO films containing La as the high dielectric constant gate insulating films 106c and 106a.
  • the average impurity concentration of the p-type impurity in the channel region 121a having a large channel width is substantially the same as that immediately after formation after the manufacture, but the average impurity concentration of the p-type impurity in the channel region 121c having a small channel width. Therefore, the threshold voltage of the n-type MOS transistor nTr2 is lower than that immediately after formation, so that the threshold voltage of the n-type MOS transistor nTr1 becomes lower.
  • the threshold voltage of the n-type MOS transistor nTr1 having a large gate width WTr1 can be lowered to a desired threshold voltage
  • the threshold voltage of the n-type MOS transistor nTr2 having a small gate width WTr2 is There is a problem that the voltage becomes too low, becomes lower than the desired threshold voltage, and cannot be set to the desired threshold voltage.
  • an object of the present invention is to control the threshold voltage of the first and second MIS transistors to a desired threshold voltage in a semiconductor device including first and second MIS transistors having different gate widths. That is.
  • a semiconductor device is a semiconductor device including a first MIS transistor and a second MIS transistor, and the first MIS transistor is a first active in a semiconductor substrate.
  • the first gate insulating film and the second gate insulating film each include an adjustment metal, and the first gate width of the first MIS transistor is larger than the second gate width of the second MIS transistor. small, The average adjustment metal concentration of the adjustment metal in the first gate insulating film is lower than the average adjustment metal concentration of the adjustment metal in the second gate insulating film.
  • the average adjustment metal concentration of the adjustment metal (for example, La) in the first gate insulating film is set to the average adjustment metal concentration of the adjustment metal (for example, La) in the second gate insulating film. Lower than the metal concentration.
  • the effective work function of the first MIS transistor is changed to an effective work function close to the midgap, while the effective work function of the second MIS transistor is changed to an effective work function close to the band edge.
  • the threshold voltage of the transistor can be higher than the threshold voltage of the second MIS transistor.
  • the average impurity concentration of the first impurity (for example, p-type impurity) in the first channel region after manufacture is increased by the heat treatment performed after the formation of the first and second channel regions.
  • the threshold voltage of the first MIS transistor becomes lower than the threshold voltage of the second MIS transistor by lowering the average impurity concentration of the second impurity (eg, p-type impurity) in the two channel regions. Even so, as described above, the threshold voltage of the first MIS transistor can be made higher than the threshold voltage of the second MIS transistor. Therefore, comprehensively, the threshold voltage of the first MIS transistor and the threshold voltage of the second MIS transistor can be made the same.
  • the threshold voltage of the first and second MIS transistors can be controlled to a desired threshold voltage.
  • the first gate width is 100 nm or less and the second gate width is 200 nm or more.
  • the first MIS transistor and the second MIS transistor are n-type MIS transistors, and the adjustment metal is lanthanum.
  • the average adjustment metal concentration of the adjustment metal in the first high dielectric constant insulating film is higher than the average adjustment metal concentration of the adjustment metal in the second high dielectric constant insulating film. And low.
  • the first gate insulating film includes a first interface layer formed on the first active region and a first high dielectric constant insulating film formed on the first interface layer.
  • the second gate insulating film includes a second interface layer formed on the second active region and a second high dielectric constant insulating film formed on the second interface layer. It is preferable to become.
  • the first interface layer and the second interface layer are preferably made of a silicon oxide film.
  • the first high dielectric constant insulating film and the second high dielectric constant insulating film are preferably made of a metal oxide having a relative dielectric constant of 10 or more.
  • the first gate electrode includes a first metal film formed on the first gate insulating film and a first silicon film formed on the first metal film.
  • the second gate electrode is preferably composed of a second metal film formed on the second gate insulating film and a second silicon film formed on the second metal film.
  • a method for manufacturing a semiconductor device includes a first MIS having a first gate insulating film and a first gate electrode formed on a first active region in a semiconductor substrate.
  • a method for manufacturing a semiconductor device comprising: a transistor; and a second MIS transistor having a second gate insulating film and a second gate electrode formed on a second active region in the semiconductor substrate.
  • An adjustment metal is introduced into one region to form a first gate insulating film formation film, while an adjustment metal is introduced into a second region located on the second active region in the gate insulation film formation film.
  • the first gate insulating film forming film and the second gate insulating film forming film are patterned to form a first gate insulating film and a gate electrode made of the first gate insulating film forming film on the first active region.
  • a first gate electrode made of a film is formed, while a second gate insulating film made of a second gate insulating film forming film and a second gate electrode made of a gate electrode forming film are formed on the second active region
  • the first gate width of the first MIS transistor is smaller than the second gate width of the second MIS transistor.
  • the first gate insulating film is formed. Average adjustment gold of adjustment metal in the film
  • the first gate insulating film forming film and the second gate insulating film forming film are formed so that the concentration is lower than the average adjusting metal concentration of the adjusting metal in the second gate insulating film forming film. It is characterized by that.
  • the average adjustment metal concentration of the adjustment metal (for example, La) in the first gate insulating film formation film is set to the adjustment metal in the second gate insulation film formation film. Lower than the average metal concentration for adjustment.
  • the effective work function of the first MIS transistor is changed to an effective work function close to the midgap, while the effective work function of the second MIS transistor is changed to an effective work function close to the band edge.
  • the threshold voltage of the transistor can be higher than the threshold voltage of the second MIS transistor.
  • the average impurity concentration of the first impurity (for example, p-type impurity) in the first channel region after manufacture is increased by the heat treatment performed after the formation of the first and second channel regions.
  • the threshold voltage of the first MIS transistor becomes lower than the threshold voltage of the second MIS transistor by lowering the average impurity concentration of the second impurity (eg, p-type impurity) in the two channel regions. Even so, as described above, the threshold voltage of the first MIS transistor can be made higher than the threshold voltage of the second MIS transistor. Therefore, comprehensively, the threshold voltage of the first MIS transistor and the threshold voltage of the second MIS transistor can be made the same.
  • the threshold voltage of the first and second MIS transistors can be controlled to a desired threshold voltage.
  • the step (b) includes a first adjustment metal having a first film thickness and including an adjustment metal on the first region in the gate insulating film formation film.
  • a step (b1) of forming a film, and a step (b2) of forming a second adjustment metal film having the second film thickness and including the adjustment metal on the second region in the gate insulating film formation film And after the steps (b1) and (b2), the first gate insulating film is formed by introducing the adjusting metal in the first adjusting metal film into the first region of the gate insulating film forming film by heat treatment.
  • the first film thickness is preferably thinner than the second film thickness.
  • the step (b) includes a step (b1) of forming an adjustment metal film containing an adjustment metal on the gate insulating film formation film, and a step (b1).
  • the adjusting metal in the adjusting metal film is introduced into the first region of the gate insulating film forming film by the first heat treatment to form the first gate insulating film forming film, and the adjusting metal film in the adjusting metal film is adjusted.
  • a second gate insulating film forming film is formed by additionally introducing the adjusting metal in the adjusting metal film into the second region of the gate insulating film forming film by a second heat treatment.
  • the average adjustment metal concentration of the adjustment metal in the first gate insulating film is greater than the average adjustment metal concentration of the adjustment metal in the second gate insulating film.
  • FIGS. 1A to 1C are diagrams showing a configuration of a semiconductor device according to the first embodiment of the present invention
  • FIG. 1A is a plan view
  • FIG. 1A is a cross-sectional view taken along the line Ib-Ib shown in FIG. 1 (a cross-sectional view in the gate width direction).
  • FIG. 1C is a cross-sectional view taken along the line Ic-Ic shown in FIG. ).
  • FIGS. 2A to 2C are cross-sectional views in the gate width direction showing the method of manufacturing the semiconductor device according to the second embodiment of the present invention in the order of steps.
  • FIGS. 3A to 3C are cross-sectional views in the gate width direction showing the method of manufacturing the semiconductor device according to the second embodiment of the present invention in the order of steps.
  • FIGS. 4A to 4C are cross-sectional views in the gate width direction showing the method of manufacturing the semiconductor device according to the second embodiment of the present invention in the order of steps.
  • FIGS. 5A to 5C are cross-sectional views in the gate width direction showing the method of manufacturing the semiconductor device according to the modification of the second embodiment of the present invention in the order of steps.
  • FIG. 6 is a cross-sectional view in the gate length direction showing the configuration of a conventional semiconductor device.
  • FIG. 7 is a cross-sectional view in the gate width direction showing the configuration of a conventional semiconductor device.
  • 1A to 1C are diagrams showing a configuration of a semiconductor device according to the first embodiment of the present invention
  • FIG. 1A is a plan view
  • FIG. 1B is a diagram of FIG.
  • FIG. 1A is a cross-sectional view taken along the line Ib-Ib shown in FIG. 1A (a cross-sectional view in the gate width direction).
  • FIG. 1C is a cross-sectional view taken along the line Ic-Ic shown in FIG. ).
  • FIG. 1A for the sake of simplicity, only the first and second active regions and the first and second gate electrodes surrounded by the element isolation region 11 are illustrated.
  • the “first nMIS region” refers to a region where an n-type first MIS transistor is formed.
  • the “second nMIS region” refers to a region where an n-type second MIS transistor is formed.
  • the first MIS transistor is a transistor used for, for example, an SRAM (Static Random Access Memory).
  • the second MIS transistor is a transistor used in a logic circuit, for example.
  • the semiconductor device includes a first MIS transistor Tr1 and a second MIS transistor Tr2.
  • a first active region 10a surrounded by the element isolation region 11 is formed in the first nMIS region of the semiconductor substrate.
  • a second active region 10b surrounded by the element isolation region 11 is formed in the second nMIS region in the semiconductor substrate.
  • a first gate insulating film (see FIGS. 1B and 1C: 15A) and a first gate electrode 20A are sequentially formed on the first active region 10a.
  • a second gate insulating film (see FIGS. 1B and 1C: 15B) and a second gate electrode 20B are sequentially formed on the second active region 10b.
  • the first gate width W1 of the first MIS transistor Tr1 is smaller than the second gate width W2 of the second MIS transistor Tr2 (W1 ⁇ W2).
  • the first gate width W1 is, for example, 100 nm or less.
  • the second gate width W2 is, for example, 200 nm or more.
  • first and second gate widths W1 and W2 refer to the widths of the first and second active regions 10a and 10b in the gate width direction.
  • a p-type well region 12 is formed in the semiconductor substrate 10.
  • the first MIS transistor Tr1 includes a first gate insulating film 15A formed on the first active region 10a and the first gate insulating film 15A.
  • the first gate electrode 20A formed in the first active region 10a, the p-type first channel region 13a formed immediately below the first gate electrode 20A in the first active region 10a, and the side surface of the first gate electrode 20A The first offset spacer 21a formed above, and the first n-type extension region 22a formed below the side of the first gate electrode 20A in the first active region 10a (particularly, FIG.
  • the second MIS transistor Tr2 includes a second gate insulating film 15B formed on the second active region 10b and a second gate insulating film 15B.
  • the second sidewall 23b formed on the side surface of the second gate electrode 20B via the second offset spacer 21b, and the second sidewall 23b outside the second active region 10b.
  • the first channel region 13a contains a first impurity (for example, a p-type impurity).
  • the second channel region 13b includes a second impurity (for example, a p-type impurity).
  • the average impurity concentration of the p-type impurity in the first channel region 13a is lower than the average impurity concentration of the p-type impurity in the second channel region 13b.
  • the average impurity concentration of the p-type impurity in the first channel region (see FIG. 2 (a): 13A) immediately after the formation and the second impurity immediately after the formation.
  • the average impurity concentration of the p-type impurity in the channel region is the same.
  • the average impurity concentration of the p-type impurity in the first channel region 13a after manufacture is lower than the average impurity concentration of the p-type impurity in the second channel region 13b after manufacture.
  • the first and second gate insulating films 15A and 15B each contain an adjustment metal (for example, La).
  • the average adjusting metal concentration of the adjusting metal in the first gate insulating film 15A is lower than the average adjusting metal concentration of the adjusting metal in the second gate insulating film 15B.
  • the first gate insulating film 15A has a first interface layer 14a and a first high dielectric constant insulating film 15a containing an adjustment metal.
  • the second gate insulating film 15B has a second interface layer 14b and a second high dielectric constant insulating film 15b containing an adjustment metal.
  • the average adjusting metal concentration of the adjusting metal in the first high dielectric constant insulating film 15a is lower than the average adjusting metal concentration of the adjusting metal in the second high dielectric constant insulating film 15b.
  • the average La concentration of La in the first high dielectric constant insulating film 15a is, for example, 20% or less.
  • the average La concentration of La in the second high dielectric constant insulating film 15b is, for example, 25%.
  • the first and second high dielectric constant insulating films 15a and 15b are made of, for example, a metal oxide having a relative dielectric constant of 10 or more, specifically, for example, HfSiO containing La.
  • the first and second interface layers 14a and 14b are made of, for example, a silicon oxide film.
  • the first gate electrode 20A has a first metal film 19a and a first silicon film 20a.
  • the second gate electrode 20B has a second metal film 19b and a second silicon film 20b.
  • the average adjustment metal concentration of the adjustment metal (for example, La) in the first gate insulating film 15A is set to the average adjustment metal concentration of the adjustment metal (for example, La) in the second gate insulating film 15B.
  • the effective work function of the first MIS transistor Tr1 is set to an effective work function close to the midgap, while the effective work function of the second MIS transistor Tr2 is set to an effective work function close to the band edge.
  • the threshold voltage of the second MIS transistor Tr1 can be made higher than the threshold voltage of the second MIS transistor Tr2.
  • the average impurity concentration of the p-type impurity in the first channel region 13a after manufacture is increased in the second channel region 13b after manufacture by the heat treatment performed after the formation of the first and second channel regions.
  • the threshold voltage of the first MIS transistor Tr1 may be lower than the threshold voltage of the second MIS transistor Tr2 due to being lower than the average impurity concentration of the p-type impurity at The threshold voltage of the first MIS transistor Tr1 can be made higher than the threshold voltage of the second MIS transistor Tr2. Therefore, comprehensively, the threshold voltage of the first MIS transistor Tr1 and the threshold voltage of the second MIS transistor Tr2 can be made the same.
  • the average adjustment metal concentration of the adjustment metal in the first gate insulating film 15A is made lower than the average adjustment metal concentration of the adjustment metal in the second gate insulating film 15B. It is possible to compensate for the difference in threshold voltage between the first and second MIS transistors Tr1 and Tr2, which is caused by the difference in the average impurity concentration of the p-type impurities in the first and second channel regions 13a and 13b. Therefore, the threshold voltages of the first and second MIS transistors Tr1 and Tr2 can be controlled to a desired threshold voltage.
  • the LSI can be highly integrated while controlling the threshold voltage of the MIS transistor to a desired threshold voltage, so that the high integration of the LSI can be accelerated.
  • the memory is highly integrated while controlling the threshold voltage of the first MIS transistor Tr1 to a desired threshold voltage. Therefore, high integration of the memory can be accelerated.
  • FIGS. 3A to 3C, and FIGS. 4A to 4C are described below with respect to a method for manufacturing a semiconductor device according to the second embodiment of the present invention.
  • the description will be given with reference.
  • 2A to 4C are cross-sectional views in the gate width direction showing the method of manufacturing the semiconductor device according to the second embodiment of the present invention in the order of steps.
  • the first nMIS region, the first pMIS region, the second pMIS region, and the second nMIS region are shown in order from the left side.
  • the “first pMIS region” refers to a region where a p-type third MIS transistor is formed.
  • the “second pMIS region” refers to a region where a p-type fourth MIS transistor is formed.
  • the first and third MIS transistors are transistors used for SRAM, for example.
  • the second and fourth MIS transistors are transistors used in a logic circuit, for example.
  • FIGS. 2 (a) to 4 (c) the same reference numerals as those shown in FIGS. 1 (a) to (c) are attached to the same components as those in the first embodiment.
  • silicon oxide is formed on an upper portion of a semiconductor substrate 10 made of, for example, silicon (Si) by, for example, STI (Shallow Trench Isolation), for example, in a trench having a depth of 200 nm to 400 nm.
  • the element isolation region 11 in which the film (SiO 2 film) is embedded is selectively formed.
  • first and second active regions 10 a and 10 b surrounded by the element isolation region 11 are formed in the first and second nMIS regions of the semiconductor substrate 10.
  • third and fourth active regions 10 c and 10 d surrounded by the element isolation region 11 are formed in the first and second pMIS regions in the semiconductor substrate 10.
  • the width of the first active region 10a in the gate width direction (ie, the first gate width) W1 is smaller than the width of the second active region 10b in the gate width direction (ie, the second gate width) W2 ( W1 ⁇ W2).
  • the first gate width W1 is, for example, 100 nm or less.
  • the second gate width W2 is, for example, 200 nm or more.
  • the width of the third active region 10c in the gate width direction (ie, the third gate width) is smaller than the width of the fourth active region 10d in the gate width direction (ie, the fourth gate width).
  • first and second p-type well regions 12x and 12y are formed in the first and second nMIS regions in the semiconductor substrate 10.
  • the n-type well region 12z is formed in the first and second pMIS regions in the semiconductor substrate 10.
  • first and second active regions 10a and 10b for example, boron (B).
  • a p-type impurity is implanted.
  • p-type first and second channel regions 13A and 13B are formed above the first and second active regions 10a and 10b.
  • ion implantation for example, arsenic (As) or the like is implanted into the third and fourth active regions 10c and 10d under an ion implantation condition of an implantation energy of 85 keV and an implantation dose of 7 ⁇ 10 12 ions / cm 2 , for example.
  • An n-type impurity is implanted.
  • n-type third and fourth channel regions 13C and 13D are formed above the third and fourth active regions 10c and 10d.
  • the average impurity concentration of n-type impurities in the third channel region 13C and the average impurity concentration of n-type impurities in the fourth channel region 13D are the same.
  • the surface portions of the first, third, fourth, and second active regions 10a, 10c, 10d, and 10b are formed by, for example, heat treatment in an atmosphere containing oxygen gas. Oxidize.
  • the first, third, fourth, and second active regions 10a, 10c, 10d, and 10b are formed of, for example, a silicon oxide film having a thickness of 1 nm to 2 nm.
  • Two interface layers 14A, 14C, 14D, and 14B are formed.
  • the entire surface of the semiconductor substrate 10 is made of a HfSiO film having a film thickness of, for example, 1 nm to 2 nm.
  • a dielectric insulating film 15 is formed.
  • first, third, fourth, and second interface layers 14A, 14C, 14D, and 14B are formed on the first, third, fourth, and second active regions 10a, 10c, 10d, and 10b. Then, a gate insulating film forming film having the high dielectric constant insulating film 15 is formed.
  • an adjustment metal film 16 containing, for example, aluminum (Al) with a film thickness of 0.5 nm to 1.5 nm is formed on the high dielectric constant insulating film 15 by, for example, sputtering or ALD (Atomic Layer Deposition).
  • a resist Re1 is formed on the protective film 17 by lithography to open the first and second nMIS regions and cover the first and second pMIS regions. Thereafter, the portions formed in the first and second nMIS regions in the protective film 17 and the adjustment metal film 16 are removed by wet etching, for example, using the resist Re1 as a mask. Thereafter, the resist Re1 is removed.
  • the first n and first pMIS regions are opened and the second p and second nMIS regions are covered on the adjustment metal film 18 by lithography.
  • a resist Re2 is formed.
  • the resist Re2 may be any resist that opens at least a region corresponding to the first active region 10a.
  • the portion formed in the first n and first pMIS regions in the adjustment metal film 18 is removed by wet etching, for example, using the resist Re2 as a mask, and the portion is thinned.
  • the film thickness of the portion is set to, for example, 0.2 nm to 0.8 nm.
  • the film thickness of the portion is set based on the first and second gate widths (see FIG. 2A: W1 and W2) and the film thickness of the adjustment metal film 18.
  • the first region located on the first active region 10a is formed on the first region.
  • a first adjustment metal film 18a having a thickness of 1 (for example, 0.2 nm to 0.8 nm) is formed.
  • a second adjustment metal having a second film thickness (for example, 0.5 nm to 1.5 nm) on the second region located on the second active region 10b in the gate insulating film formation film.
  • a film 18b is formed.
  • heat treatment is performed at 700 ° C. for 120 seconds, for example.
  • the adjustment metal (for example, La) in the first adjustment metal film 18a is applied to the first region in the gate insulating film formation film (particularly, on the first active region 10a in the high dielectric constant insulating film 15).
  • the first gate insulating film forming film 15X having the first interface layer 14A and the first high dielectric constant insulating film 15x containing the adjusting metal is formed.
  • the first high dielectric constant insulating film 15x is made of, for example, an HfSiO film containing La.
  • the adjustment metal (for example, Al) in the adjustment metal film 16 is moved to the third and fourth regions (particularly, on the third and fourth active regions 10c and 10d in the gate insulating film formation film).
  • the third dielectric layer 15 is introduced into the third and fourth active regions 10c and 10d) in the high dielectric constant insulating film 15, and the third high and the fourth interface layers 14C and 14D and the third metal including the adjusting metal are introduced.
  • a third gate insulating film forming film 15Z having a dielectric constant insulating film 15z is formed.
  • the third high dielectric constant insulating film 15z is made of, for example, an HfSiO film containing Al.
  • the adjustment metal (for example, La) in the second adjustment metal film 18b is applied to the second region in the gate insulating film formation film (in particular, on the second active region 10b in the high dielectric constant insulating film 15).
  • the second gate insulating film forming film 15Y having the second interface layer 14B and the second high dielectric constant insulating film 15y containing the adjusting metal is formed.
  • the second high dielectric constant insulating film 15y is made of, for example, an HfSiO film containing La.
  • the first film thickness (for example, 0.2 nm to 0.8 nm) of the first adjustment metal film 18a is set to the second film thickness (for example, 0.5 nm to 1.5 nm) of the second adjustment metal film 18b.
  • the average adjustment metal concentration of the adjustment metal in the first high dielectric constant insulating film 15x is set to be smaller than the average adjustment metal concentration of the adjustment metal in the second high dielectric constant insulating film 15y. Can be lowered.
  • the average La concentration of La in the first high dielectric constant insulating film 15x is, for example, 20% or less.
  • the average La concentration of La in the second high dielectric constant insulating film 15y is, for example, 25%.
  • the unreacted portions of the first and second adjustment metal films 18a and 18b, the unreacted portions of the protective film 17 and the adjustment metal film 16, for example, by wet etching. remove parts sequentially.
  • a metal film 19 made of, for example, a TiN film having a thickness of 10 nm to 20 nm is formed on the first, third, and second gate insulating film forming films 15X, 15Z, and 15Y by, for example, ALD.
  • a silicon film 20 made of a polysilicon film having a film thickness of, for example, 70 nm to 100 nm is formed on the metal film 19 by, eg, CVD.
  • a gate electrode forming film having the metal film 19 and the silicon film 20 is formed on the first, third, and second gate insulating film forming films 15X, 15Z, and 15Y.
  • a resist (not shown) is formed on the silicon film 20 by lithography. Thereafter, the gate electrode forming film and the first, third, and second gate insulating film forming films 15X, 15Z, and 15Y are sequentially patterned by etching using the resist as a mask.
  • the first gate electrode 20A and the third gate electrode 20C are integrally formed.
  • the fourth gate electrode 20D and the second gate electrode 20B are integrally formed.
  • the average adjustment metal concentration of the adjustment metal (for example, La) in the first high dielectric constant insulating film 15a is the average adjustment metal concentration of the adjustment metal (for example, La) in the second high dielectric constant insulating film 15b. Lower than.
  • the average adjustment metal concentration of the adjustment metal (for example, Al) in the third high dielectric constant insulating film 15c is the same.
  • the first and first cross sections are I-shaped.
  • Third, fourth and second offset spacers 31a, 31c, 31d and 31b are formed.
  • the first offset spacer 31a and the third offset spacer 31c are integrally formed.
  • the fourth offset spacer 31d and the second offset spacer 31b are integrally formed.
  • first and second active regions are not shown in FIG. 4C.
  • First and second n-type extension implantation regions are formed under the sides of the first and second gate electrodes 20A and 20B in 10a and 10b.
  • first and second p-type extension implantation regions are formed in the third and fourth active regions 10c and 10d below the third and fourth gate electrodes 20C and 20D.
  • first, third, fourth, and second gate electrodes 20A, 20C, 20D, and 20B are formed on the side surfaces of the first, third, fourth, and second gate electrodes 20A, 20C, 20D, and 20B.
  • First, third, fourth and second sidewalls 33a, 33c, 33d and 33b are formed via offset spacers 31a, 31c, 31d and 31b.
  • the first sidewall 33a and the third sidewall 33c are integrally formed.
  • the fourth sidewall 33d and the second sidewall 33b are integrally formed.
  • first and second n-types are formed outside the first and second sidewalls 33a and 33b in the first and second active regions 10a and 10b.
  • a source / drain implantation region is formed.
  • first and second p-type source / drain implantation regions are formed on the outer sides of the third and fourth sidewalls 33c and 33d in the third and fourth active regions 10c and 10d.
  • heat treatment is performed at 1000 ° C. for 1 second.
  • the n-type impurities contained in the first and second n-type extension implantation regions are activated to form the first and second n-type extension regions (see FIG. 1C: 22a and 22b).
  • p-type impurities contained in the first and second p-type extension implantation regions are activated to form first and second p-type extension regions.
  • the n-type impurity contained in the first and second n-type source / drain implantation regions is activated, and the first and second n-type source / drain regions (see FIG. 1 (c): 24a and 24b).
  • the p-type impurities contained in the first and second p-type source / drain implantation regions are activated to form first and second p-type source / drain regions.
  • the semiconductor device according to this embodiment can be manufactured.
  • the average impurity concentration of the p-type impurity in the first channel region 13A immediately after formation (see FIG. 2A) and the second channel region 13B immediately after formation (see FIG. 2A) is the same.
  • the heat treatment performed after the formation of the first and second channel regions 13A and 13B (for example, the n-type impurities contained in the first and second n-type source / drain implantation regions, and the first and second channel regions)
  • the p-type impurities contained in the first and second channel regions 13A and 13B are caused to enter the element isolation region 11 by heat treatment for activating the p-type impurities contained in the p-type source / drain implantation region.
  • the average impurity concentration of the p-type impurity in the first channel region 13a after manufacture is the same as that in the second channel region 13b after manufacture (see FIG. 4C). It becomes lower than the average impurity concentration of the p-type impurity.
  • the average impurity concentration of the n-type impurity is the same.
  • the heat treatment performed after the formation of the third and fourth channel regions 13C and 13D for example, the n-type impurities contained in the first and second n-type source / drain implantation regions, and the first and second The n-type impurities contained in the third and fourth channel regions 13C and 13D are caused to enter the element isolation region 11 by heat treatment for activating the p-type impurities contained in the p-type source / drain implantation region.
  • the average impurity concentration of the n-type impurity in the third channel region 13c after manufacture is the same as that in the fourth channel region 13d after manufacture (see FIG. 4C). It becomes lower than the average impurity concentration of n-type impurities.
  • the first MIS transistor Tr1 includes the same components as the first MIS transistor Tr1 in the first embodiment. However, in the present embodiment, the first gate electrode 20A is formed integrally with the third gate electrode 20C as shown in FIG. 4C, so that the first gate electrode 20A is formed on the side surface of the first gate electrode 20A. The first sidewall 33a is formed on the side surface other than the side surface adjacent to the third gate electrode 20C via the first offset spacer 31a.
  • the second MIS transistor Tr2 includes the same components as the second MIS transistor Tr2 in the first embodiment. However, in the present embodiment, the second gate electrode 20B is formed integrally with the fourth gate electrode 20D as shown in FIG. 4C, so that the second gate electrode 20B is formed on the side surface of the second gate electrode 20B. The second sidewall 33b is formed on the side surface other than the side surface adjacent to the fourth gate electrode 20D via the second offset spacer 31b.
  • the third and fourth MIS transistors Tr3 and Tr4 have third and fourth gate insulating films 15C, 15C formed on the third and fourth active regions 10c and 10d, respectively.
  • 15D the third and fourth gate electrodes 20C and 20D formed on the third and fourth gate insulating films 15C and 15D, and the third and fourth gates in the third and fourth active regions 10c and 10d.
  • N-type third and fourth channel regions 13c and 13d formed immediately below the gate electrodes 20C and 20D, and third and third channels formed on the side surfaces of the third and fourth gate electrodes 20C and 20D.
  • the third and fourth gate insulating films 15C and 15D have third and fourth interface layers 14c and 14d and third and fourth high dielectric constant insulating films 15c and 15d.
  • the third and fourth gate electrodes 20C and 20D have third and fourth metal films 19c and 19d and third and fourth silicon films 20c and 20d.
  • the average adjustment metal concentration of the adjustment metal (for example, La) in the first gate insulating film 15A is lower than the average adjustment metal concentration of the adjustment metal (for example, La) in the second gate insulating film 15B.
  • the average adjustment metal concentration of the adjustment metal (for example, Al) in the third gate insulating film 15C and the average adjustment metal concentration of the adjustment metal (for example, Al) in the fourth gate insulating film 15D are as follows. The same.
  • the average adjustment metal concentration of the adjustment metal (for example, La) in the first high dielectric constant insulating film 15a is the average adjustment metal concentration of the adjustment metal (for example, La) in the second high dielectric constant insulating film 15b. Lower than.
  • the average adjustment metal concentration of the adjustment metal (for example, Al) in the third high dielectric constant insulating film 15c and for the average adjustment of the adjustment metal (for example, Al) in the fourth high dielectric constant insulating film 15d The metal concentration is the same.
  • the average impurity concentration of the p-type impurity in the first channel region 13a is lower than the average impurity concentration of the p-type impurity in the second channel region 13b.
  • the average impurity concentration of n-type impurities in the third channel region 13c is lower than the average impurity concentration of n-type impurities in the fourth channel region 13d.
  • the manufacturing method of the semiconductor device including the first, third, fourth, and second MIS transistors has been described.
  • the semiconductor according to the first embodiment is manufactured by the same manufacturing method as the present embodiment.
  • a device that is, a semiconductor device including first and second MIS transistors
  • the semiconductor device according to the first embodiment can be manufactured by sequentially performing the same processes as those shown in the region.
  • FIGS. 5 (a) to 5 (c) A method for manufacturing a semiconductor device according to a modification of the second embodiment of the present invention will be described below with reference to FIGS. 5 (a) to 5 (c).
  • 5A to 5C are cross-sectional views in the gate width direction showing the method of manufacturing the semiconductor device according to the modification of the second embodiment of the present invention in the order of steps.
  • 5 (a) to 5 (c) the same reference numerals as those shown in FIGS. 2 (a) to 4 (c) are assigned to the same constituent elements as those in the second embodiment. Therefore, in this modification, the description similar to that of the second embodiment is omitted as appropriate.
  • steps similar to those shown in FIGS. 2A to 2C in the second embodiment are sequentially performed.
  • the adjustment metal film 18 containing La having a thickness of 0.5 nm to 1.5 nm, for example, is formed on the entire surface of the semiconductor substrate 10 by, for example, sputtering.
  • a heat treatment (first heat treatment) is performed at 650 ° C. for 120 seconds.
  • the adjustment metal (for example, La) in the adjustment metal film 18 is removed from the first region in the gate insulating film formation film (particularly, the region located on the first active region 10a in the high dielectric constant insulating film 15).
  • the first gate insulating film forming film 15X having the first interface layer 14A and the first high dielectric constant insulating film 15x containing the adjusting metal is formed.
  • the adjustment metal (for example, Al) in the adjustment metal film 16 is applied to the third and fourth regions in the gate insulating film formation film (in particular, the third and fourth active regions in the high dielectric constant insulating film 15). 10c and 10d), a high dielectric constant insulating film 15w containing an adjustment metal is formed.
  • the adjustment metal (for example, La) in the adjustment metal film 18 is applied to the second region in the gate insulating film formation film (in particular, the region located on the second active region 10b in the high dielectric constant insulating film 15). ) To form a high dielectric constant insulating film 15v containing an adjustment metal.
  • Re3 is formed.
  • the portion of the adjustment metal film 18 located on the first gate insulating film forming film 15X is removed by wet etching, for example, using the resist Re3 as a mask.
  • heat treatment (second heat treatment) is performed at 900 ° C. for 30 seconds.
  • the adjustment metal (for example, Al) in the adjustment metal film 16 is additionally introduced into the third and fourth regions (particularly, the high dielectric constant insulating film 15w including the adjustment metal) in the gate insulating film formation film. Then, the third gate insulating film forming film 15Z having the third high dielectric constant insulating film 15z including the third and fourth interface layers 14C and 14D and the adjusting metal is formed.
  • the adjustment metal (for example, La) in the adjustment metal film 18 is additionally introduced into the second region (particularly, the high dielectric constant insulating film 15v including the adjustment metal) in the gate insulating film formation film, A second gate insulating film forming film 15Y having the second interface layer 14B and the second high dielectric constant insulating film 15y containing the adjusting metal is formed.
  • the semiconductor device according to this modification can be manufactured.
  • the adjustment metal in the adjustment metal film 18 is removed from the first and second regions (particularly, the high region) in the gate insulating film formation film by the first heat treatment.
  • the adjusting metal is additionally introduced only into the second region in the gate insulating film formation film (particularly, the region located on the second active region 10b in the high dielectric constant insulating film 15). Therefore, the average adjustment metal concentration of the adjustment metal in the first high dielectric constant insulating film 15x is made lower than the average adjustment metal concentration of the adjustment metal in the second high dielectric constant insulating film 15y.
  • the average adjusting metal concentration of the adjusting metal in the first gate insulating film forming film 15X can be made lower than the average adjusting metal concentration of the adjusting metal in the second gate insulating film forming film 15Y. Can do.
  • the first adjustment metal film 18a having the first film thickness is formed on the first region in the gate insulating film formation film 15.
  • the second adjustment metal film 18b having a second film thickness larger than the first film thickness is formed on the second region in the gate insulating film formation film 15, FIG. c)
  • the case where heat treatment is performed at 700 ° C. for 120 seconds has been described as a specific example, but the present invention is not limited to this.
  • the first and second gate insulating film formation films may be formed by the method described in the modification of the second embodiment.
  • the first and second gate insulating film forming films may be formed by the method described below.
  • steps similar to those shown in FIGS. 2A to 2B in the second embodiment are sequentially performed.
  • portions of the protective film 17 and the adjustment metal film 16 other than the portion covered with the resist that is, the central region in the first nMIS region and the portion formed in the second nMIS region
  • the resist is removed.
  • the step shown in FIG. 3B (that is, the first n, pMIS region in the adjustment metal film 18).
  • the step shown in FIG. 3 (c) in the second embodiment (that is, the adjustment metal in the adjustment metal film is increased by heat treatment without performing the same step as the step of thinning the portion formed in FIG. 3).
  • a step similar to that in the step of introducing the dielectric constant insulating film) is performed.
  • the region located on the first active region in the high dielectric constant insulating film during the heat treatment for introducing the adjustment metal (for example, La) in the adjustment metal film into the high dielectric constant insulating film While only the central portion is in contact with the adjustment metal film, the entire region of the region located on the second active region in the high dielectric constant insulating film is in contact with the adjustment metal film. Therefore, the average adjustment metal concentration of the adjustment metal in the first high dielectric constant insulating film can be made lower than the average adjustment metal concentration of the adjustment metal in the second high dielectric constant insulating film.
  • the average adjusting metal concentration of the adjusting metal in the first gate insulating film forming film can be made lower than the average adjusting metal concentration of the adjusting metal in the second gate insulating film forming film.
  • the average adjustment metal concentration of the adjustment metal (for example, Al) in the third gate insulating film 15C and the adjustment metal in the fourth gate insulating film 15D (for example, the case where the average adjustment metal concentration of Al) is the same has been described as a specific example, but the present invention is not limited to this.
  • the average impurity concentration of the n-type impurity in the third channel region 13c is increased in the fourth channel region 13d by the heat treatment performed after the formation of the third and fourth channel regions 13C and 13D. It becomes lower than the average impurity concentration of n-type impurities. For this reason, the threshold voltage of the third MIS transistor Tr3 may be lower than the threshold voltage of the fourth MIS transistor Tr4.
  • the average adjusting metal concentration of the adjusting metal in the third gate insulating film is made lower than the average adjusting metal concentration of the adjusting metal in the fourth gate insulating film.
  • the present invention is not limited to this.
  • other lanthanoid elements or magnesium (Mg) may be used instead of La.
  • the case where Al is used as the adjustment metal contained in the third and fourth gate insulating films 15C and 15D has been described as a specific example.
  • tantalum oxide (TaO) may be used instead of Al.
  • the present invention can control the threshold voltage of the first and second MIS transistors to a desired threshold voltage, and thus includes the first and second MIS transistors having different gate widths. It is useful for a semiconductor device and a method for manufacturing the same.

Abstract

Disclosed is a semiconductor device which is provided with a first MIS transistor (Tr1), and a second MIS transistor (Tr2). The first MIS transistor is provided with: a first gate insulating film (15A), which is formed on a first active region (10a), and which has a first high-dielectric-constant insulating film (15a); and a first gate electrode (20A) formed on the first gate insulating film. The second MIS transistor is provided with: a second gate insulating film (15B), which is formed on a second active region (10b), and which has a second high-dielectric-constant insulating film (15b); and a second gate electrode (20B) formed on the second gate insulating film. Each of the first gate insulating film and the second gate insulating film includes a metal for adjustment. The first gate width (W1) of the first MIS transistor is smaller than the second gate width (W2) of the second MIS transistor. The average concentration of the metal for adjustment in the first gate insulating film is lower than that in the second gate insulating film.

Description

半導体装置及びその製造方法Semiconductor device and manufacturing method thereof
　本発明は、半導体装置及びその製造方法に関し、特に、ゲート幅が互いに異なり、且つ、調整用金属を含むゲート絶縁膜を有するＭＩＳＦＥＴ（Metal Insulator Semiconductor Field Effect Transistor）を備えた半導体装置及びその製造方法に関する。 The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, a semiconductor device including MISFETs (Metal Insulator Semiconductor Semiconductor Field Field Effect Transistor) having different gate widths and having a gate insulating film containing an adjustment metal. About.
　ＬＳＩの微細化のために、ゲート絶縁膜の薄膜化が要求されている。このため、近年、ゲート絶縁膜として、例えばハフニウム（Ｈｆ）系酸化膜等の高誘電率絶縁膜を適用することが検討されている。これにより、ゲート絶縁膜の物理的な膜厚を厚くしてリーク電流を抑制しつつ、ゲート絶縁膜の電気的な膜厚を薄くすることができる。 For the miniaturization of LSI, it is required to make the gate insulating film thinner. Therefore, in recent years, it has been studied to apply a high dielectric constant insulating film such as a hafnium (Hf) -based oxide film as the gate insulating film. Thereby, the electrical film thickness of the gate insulating film can be reduced while increasing the physical film thickness of the gate insulating film to suppress the leakage current.
　しかしながら、ゲート絶縁膜として高誘電率絶縁膜を用い、ゲート電極として従来のポリシリコン膜を用いた場合、フェルミレベルピニングと呼ばれる現象により、ＭＩＳＦＥＴ（以下、ＭＩＳトランジスタという）の閾値電圧が高くなるという短所がある。また、この場合、ゲート電極の空乏化と呼ばれる現象により、ゲート容量が小さくなり、ゲート電極下に高い電界を印加することができず、ＭＩＳトランジスタの駆動能力が低下するという短所もある。 However, when a high dielectric constant insulating film is used as the gate insulating film and a conventional polysilicon film is used as the gate electrode, the threshold voltage of the MISFET (hereinafter referred to as MIS transistor) increases due to a phenomenon called Fermi level pinning. There are disadvantages. Further, in this case, due to a phenomenon called depletion of the gate electrode, the gate capacitance is reduced, a high electric field cannot be applied under the gate electrode, and the driving capability of the MIS transistor is reduced.
　そこで、ゲート電極として、従来のポリシリコン膜に代わって、金属膜を用いる技術が提案されている。ゲート絶縁膜として高誘電率絶縁膜を用い、ゲート電極として金属膜を用いた場合、ｎ型ＭＩＳトランジスタの閾値電圧とｐ型ＭＩＳトランジスタの閾値電圧とを、それぞれ、互いに独立して制御する必要がある。 Therefore, a technique has been proposed in which a metal film is used as the gate electrode instead of the conventional polysilicon film. When a high dielectric constant insulating film is used as the gate insulating film and a metal film is used as the gate electrode, it is necessary to control the threshold voltage of the n-type MIS transistor and the threshold voltage of the p-type MIS transistor independently of each other. is there.
　そこで、ｎ型ＭＯＳ（Metal Oxide Semiconductor）トランジスタの実効仕事関数を、バンドエッジ側へシフトさせて、ｎ型ＭＯＳトランジスタの閾値電圧を低くする為に、ゲート絶縁膜として、例えばランタン（Ｌａ）を含むＨｆ系酸化膜を用いる技術が提案されている（例えば特許文献１参照）。ゲート絶縁膜として、Ｌａを含むＨｆ系酸化膜を用いることにより、ｎ型ＭＯＳトランジスタの実効仕事関数を、バンドエッジ側へシフトさせることができるのは、次のような理由による。Ｈｆ系酸化膜にＬａを含ませると、フラットバンド電圧がマイナス側へシフトするため、ｎ型ＭＯＳトランジスタの実効仕事関数をバンドエッジ側へシフトさせることができる。 Therefore, in order to lower the threshold voltage of the n-type MOS transistor by shifting the effective work function of the n-type MOS (Metal Oxide Semiconductor) transistor to the band edge side, for example, lanthanum (La) is included as a gate insulating film. A technique using an Hf-based oxide film has been proposed (see, for example, Patent Document 1). The reason why the effective work function of the n-type MOS transistor can be shifted to the band edge side by using an Hf-based oxide film containing La as the gate insulating film is as follows. When La is included in the Hf-based oxide film, the flat band voltage shifts to the minus side, and therefore the effective work function of the n-type MOS transistor can be shifted to the band edge side.
　以下、従来の半導体装置の構成について、図６を参照しながら説明する。図６は、従来の半導体装置の構成を示すゲート長方向の断面図である。 Hereinafter, the configuration of a conventional semiconductor device will be described with reference to FIG. FIG. 6 is a cross-sectional view in the gate length direction showing the configuration of a conventional semiconductor device.
　図６に示す従来の半導体装置は、ｎ型ＭＯＳトランジスタｎＴｒ１と、ｐ型ＭＯＳトランジスタｐＴｒとを備えている。 The conventional semiconductor device shown in FIG. 6 includes an n-type MOS transistor nTr1 and a p-type MOS transistor pTr.
　図６に示すように、シリコン基板１０１の上部には、素子分離領域１０２が形成されている。シリコン基板１０１における第１のＮＭＯＳ領域には、Ｐウェル拡散層１０３が形成されている。一方、シリコン基板１０１におけるＰＭＯＳ領域には、Ｎウェル拡散層１０４が形成されている。 As shown in FIG. 6, an element isolation region 102 is formed on the silicon substrate 101. A P well diffusion layer 103 is formed in the first NMOS region of the silicon substrate 101. On the other hand, an N well diffusion layer 104 is formed in the PMOS region of the silicon substrate 101.
　シリコン基板１０１における第１のＮＭＯＳ領域上には、ゲート絶縁膜１１７ａ及びゲート電極１１６ａが順次形成されている。一方、シリコン基板１０１におけるＰＭＯＳ領域上には、ゲート絶縁膜１１７ｂ、ＳｉＮ膜１０９ｂ、Ｌａ（Ｏ）膜１１１ｂ及びゲート電極１１６ｂが順次形成されている。 On the first NMOS region of the silicon substrate 101, a gate insulating film 117a and a gate electrode 116a are sequentially formed. On the other hand, on the PMOS region in the silicon substrate 101, a gate insulating film 117b, a SiN film 109b, a La (O) film 111b, and a gate electrode 116b are sequentially formed.
　ゲート電極１１６ａ，１１６ｂの側面上には、ＳｉＮ膜１１８ａ，１１８ｂ及びＴＥＯＳ膜１１９ａ，１１９ｂが順次形成されている。シリコン基板１０１におけるゲート電極１１６ａ，１１６ｂの側方下には、ソース・ドレイン拡散層１２０ａ，１２０ｂが形成されている。 On the side surfaces of the gate electrodes 116a and 116b, SiN films 118a and 118b and TEOS films 119a and 119b are sequentially formed. Source / drain diffusion layers 120a and 120b are formed below the sides of the gate electrodes 116a and 116b in the silicon substrate 101, respectively.
　ゲート絶縁膜１１７ａは、シリコン酸化膜１０５ａ及び高誘電率ゲート絶縁膜（Ｌａを含むＨｆＳｉＯ膜）１０６ａを有する。一方、ゲート絶縁膜１１７ｂは、シリコン酸化膜１０５ｂ及びＬａを含まないＨｆＳｉＯＮ膜１１０ｂを有する。 The gate insulating film 117a includes a silicon oxide film 105a and a high dielectric constant gate insulating film (HfSiO film containing La) 106a. On the other hand, the gate insulating film 117b includes the silicon oxide film 105b and the HfSiON film 110b not including La.
　ゲート電極１１６ａは、ＷＳｉ膜１１４ａ、バリアメタル１１３ａ及びドープト多結晶シリコン膜１１５ａを有する。一方、ゲート電極１１６ｂは、Ｗ膜１１２ｂ、バリアメタル１１３ｂ及びドープト多結晶シリコン膜１１５ｂを有する。 The gate electrode 116a includes a WSi film 114a, a barrier metal 113a, and a doped polycrystalline silicon film 115a. On the other hand, the gate electrode 116b includes a W film 112b, a barrier metal 113b, and a doped polycrystalline silicon film 115b.
特開２００９－１９４３５２号公報JP 2009-194352 A
　しかしながら、従来の半導体装置の製造方法を用いて、ゲート幅が互いに異なるｎ型ＭＯＳトランジスタと、ｐ型ＭＯＳトランジスタとを備えた半導体装置を製造した場合、以下に示す問題がある。この問題について、図７を参照しながら説明する。図７は、従来の半導体装置の構成を示すゲート幅方向の断面図である。図７において、図６に示す構成要素と同様の構成要素には、図６に示す符号と同一の符号を付す。従って、図７の説明では、図６の説明と同様の説明を適宜省略する。 However, when a conventional semiconductor device manufacturing method is used to manufacture a semiconductor device having an n-type MOS transistor and a p-type MOS transistor having different gate widths, there are the following problems. This problem will be described with reference to FIG. FIG. 7 is a cross-sectional view in the gate width direction showing the configuration of a conventional semiconductor device. In FIG. 7, the same components as those shown in FIG. 6 are denoted by the same reference numerals as those shown in FIG. Therefore, in the description of FIG. 7, the description similar to the description of FIG.
　図７に示す従来の半導体装置は、ｎ型ＭＯＳトランジスタｎＴｒ２，ｎＴｒ１と、ｐ型ＭＯＳトランジスタｐＴｒとを備えている。ｎ型ＭＯＳトランジスタｎＴｒ２のゲート幅ＷTr2は、ｎ型ＭＯＳトランジスタｎＴｒ１のゲート幅ＷTr1よりも小さい（ＷTr2＜ＷTr1）。 The conventional semiconductor device shown in FIG. 7 includes n-type MOS transistors nTr2 and nTr1, and a p-type MOS transistor pTr. The gate width WTr2 of the n-type MOS transistor nTr2 is smaller than the gate width WTr1 of the n-type MOS transistor nTr1 (WTr2 <WTr1).
　図７に示す半導体装置は、図６に示す半導体装置と同様の構成要素に加えて、さらに、以下の構成要素を備えている。 The semiconductor device shown in FIG. 7 includes the following components in addition to the same components as the semiconductor device shown in FIG.
　シリコン基板１０１における第２のＮＭＯＳ領域上には、ゲート絶縁膜１１７ｃ及びゲート電極１１６ｃが順次形成されている。ゲート電極１１６ｃの側面上には、ＳｉＮ膜１１８ｃ及びＴＥＯＳ膜１１９ｃが順次形成されている。図７に示す図は、ゲート幅方向の断面図であり、ゲート長方向の断面図ではないため、図７には図示されないが、シリコン基板１０１におけるゲート電極１１６ｃの側方下には、ソース・ドレイン拡散層が形成されている。 On the second NMOS region in the silicon substrate 101, a gate insulating film 117c and a gate electrode 116c are sequentially formed. An SiN film 118c and a TEOS film 119c are sequentially formed on the side surface of the gate electrode 116c. The figure shown in FIG. 7 is a cross-sectional view in the gate width direction and not in the gate length direction. Therefore, although not shown in FIG. A drain diffusion layer is formed.
　ゲート絶縁膜１１７ｃは、シリコン酸化膜１０５ｃ及び高誘電率ゲート絶縁膜（Ｌａを含むＨｆＳｉＯ膜）１０６ｃを有する。ゲート電極１１６ｃは、ＷＳｉ膜１１４ｃ、バリアメタル１１３ｃ及びドープト多結晶シリコン膜１１５ｃを有する。 The gate insulating film 117c includes a silicon oxide film 105c and a high dielectric constant gate insulating film (HfSiO film containing La) 106c. The gate electrode 116c includes a WSi film 114c, a barrier metal 113c, and a doped polycrystalline silicon film 115c.
　図６において符号の付与が省略されているが、シリコン基板１０１における第２，第１のＮＭＯＳ，ＰＭＯＳ領域には、素子分離領域１０２に囲まれた活性領域１０１ｃ，１０１ａ，１０１ｂが形成されている。 In FIG. 6, reference numerals are omitted, but active regions 101 c, 101 a, and 101 b surrounded by the element isolation region 102 are formed in the second and first NMOS and PMOS regions of the silicon substrate 101. .
　図６において図示が省略されているが、ｎ型ＭＯＳトランジスタｎＴｒ１，ｎＴｒ２の閾値電圧を制御する為に、活性領域１０１ｃ，１０１ａにおけるゲート電極１１６ｃ，１１６ａの直下には、例えばボロン（Ｂ）等のｐ型不純物を含むｐ型のチャネル領域１２１ｃ，１２１ａが形成されている。一方、ｐ型ＭＯＳトランジスタｐＴｒの閾値電圧を制御する為に、活性領域１０１ｂにおけるゲート電極１１６ｂの直下には、ｎ型不純物を含むｎ型のチャネル領域１２１ｂが形成されている。 Although not shown in FIG. 6, in order to control the threshold voltages of the n-type MOS transistors nTr1 and nTr2, for example, boron (B) or the like is provided immediately below the gate electrodes 116c and 116a in the active regions 101c and 101a. P- type channel regions 121c and 121a containing p-type impurities are formed. On the other hand, in order to control the threshold voltage of the p-type MOS transistor pTr, an n-type channel region 121b containing an n-type impurity is formed immediately below the gate electrode 116b in the active region 101b.
　チャネル領域１２１ｃとチャネル領域１２１ａとは、同一の工程で形成されるため、形成直後のチャネル領域１２１ｃ中におけるｐ型不純物の平均不純物濃度Ｘ121cと、形成直後のチャネル領域１２１ａ中におけるｐ型不純物の平均不純物濃度Ｘ121aとは、同じである（Ｘ121c＝Ｘ121a）。 Since the channel region 121c and the channel region 121a are formed in the same process, the average impurity concentration X121c of the p-type impurity in the channel region 121c immediately after formation and the average of the p-type impurity in the channel region 121a immediately after formation. The impurity concentration X121a is the same (X121c = X121a).
　しかしながら、チャネル領域１２１ｃ，１２１ａの形成後に施される熱処理により、チャネル領域１２１ｃ，１２１ａ中に含まれるｐ型不純物が、素子分離領域１０２中に拡散する。 However, the p-type impurity contained in the channel regions 121c and 121a is diffused into the element isolation region 102 by the heat treatment performed after the formation of the channel regions 121c and 121a.
　上述の通り、チャネル領域１２１ｃとチャネル領域１２１ａとは、同一の工程で形成されるため、形成後に施される熱処理の回数及び条件等は、チャネル領域１２１ｃとチャネル領域１２１ａとで同じである。このため、チャネル領域１２１ｃ中から素子分離領域１０２中に拡散するｐ型不純物の拡散量Ｍ121cと、チャネル領域１２１ａ中から素子分離領域１０２中に拡散するｐ型不純物の拡散量Ｍ121aとは、同じである（Ｍ121c＝Ｍ121a）。 As described above, since the channel region 121c and the channel region 121a are formed in the same process, the number and conditions of the heat treatment performed after the formation are the same in the channel region 121c and the channel region 121a. Therefore, the diffusion amount M121c of the p-type impurity diffusing from the channel region 121c into the element isolation region 102 is the same as the diffusion amount M121a of the p-type impurity diffusing from the channel region 121a into the element isolation region 102. Yes (M121c = M121a).
　ゲート幅ＷTr2は、ゲート幅ＷTr1よりも小さい（ＷTr2＜ＷTr1）ため、チャネル領域１２１ｃのチャネル幅は、チャネル領域１２１ａのチャネル幅よりも小さい。このため、チャネル領域１２１ｃにおける拡散量Ｍ121cが占める割合は、比較的大きい一方、チャネル領域１２１ａにおける拡散量Ｍ121aが占める割合は、比較的小さい。 Since the gate width WTr2 is smaller than the gate width WTr1 (WTr2 <WTr1), the channel width of the channel region 121c is smaller than the channel width of the channel region 121a. For this reason, the proportion of the diffusion amount M121c in the channel region 121c is relatively large, while the proportion of the diffusion amount M121a in the channel region 121a is relatively small.
　チャネル領域１２１ｃにおける拡散量Ｍ121cが占める割合は、比較的大きいため、製造後のチャネル領域１２１ｃ中におけるｐ型不純物の平均不純物濃度Ｙ121cは、形成直後のチャネル領域１２１ｃ中におけるｐ型不純物の平均不純物濃度Ｘ121cよりも、顕著に低くなる（Ｙ121c＜Ｘ121c）。 Since the proportion of the diffusion amount M121c in the channel region 121c is relatively large, the average impurity concentration Y121c of the p-type impurity in the channel region 121c after manufacture is the average impurity concentration of the p-type impurity in the channel region 121c immediately after formation. It is significantly lower than X121c (Y121c <X121c).
　一方、チャネル領域１２１ａにおける拡散量Ｍ121aが占める割合は、比較的小さいため、製造後のチャネル領域１２１ａ中におけるｐ型不純物の平均不純物濃度Ｙ121aは、形成直後のチャネル領域１２１ａ中におけるｐ型不純物の平均不純物濃度Ｘ121aよりも、顕著に低くなることはなく、平均不純物濃度Ｙ121aは、平均不純物濃度Ｘ121aと実質的に同じである（Ｙ121a＝Ｘ121a）。 On the other hand, since the proportion of the diffusion amount M121a in the channel region 121a is relatively small, the average impurity concentration Y121a of the p-type impurity in the channel region 121a after manufacture is the average of the p-type impurity in the channel region 121a immediately after formation. The impurity concentration is not significantly lower than the impurity concentration X121a, and the average impurity concentration Y121a is substantially the same as the average impurity concentration X121a (Y121a = X121a).
　従って、製造後のチャネル領域１２１ｃ中におけるｐ型不純物の平均不純物濃度Ｙ121cは、製造後のチャネル領域１２１ａ中におけるｐ型不純物の平均不純物濃度Ｙ121aよりも低くなる（Ｙ121c＜Ｙ121a）。一般に、チャネル領域中におけるｐ型不純物の平均不純物濃度が低くなるに連れて、ｎ型ＭＯＳトランジスタの閾値電圧が低くなる。このため、ｎ型ＭＯＳトランジスタｎＴｒ２の閾値電圧は、ｎ型ＭＯＳトランジスタｎＴｒ１の閾値電圧よりも低くなる。 Therefore, the average impurity concentration Y121c of the p-type impurity in the channel region 121c after manufacture is lower than the average impurity concentration Y121a of the p-type impurity in the channel region 121a after manufacture (Y121c <Y121a). Generally, as the average impurity concentration of p-type impurities in the channel region decreases, the threshold voltage of the n-type MOS transistor decreases. For this reason, the threshold voltage of the n-type MOS transistor nTr2 is lower than the threshold voltage of the n-type MOS transistor nTr1.
　このように、従来では、チャネル幅が小さくなるに連れて、製造後のチャネル領域中におけるｐ型不純物の平均不純物濃度が、形成直後のチャネル領域中におけるｐ型不純物の平均不純物濃度よりも低くなるため、ｎ型ＭＯＳトランジスタの閾値電圧が低下する。即ち、ゲート幅が小さくなるに連れてＭＯＳトランジスタの閾値電圧が低下する逆ナローチャネル効果が発生する。 Thus, conventionally, as the channel width becomes smaller, the average impurity concentration of the p-type impurity in the channel region after manufacture becomes lower than the average impurity concentration of the p-type impurity in the channel region immediately after formation. Therefore, the threshold voltage of the n-type MOS transistor is lowered. That is, the reverse narrow channel effect occurs in which the threshold voltage of the MOS transistor decreases as the gate width decreases.
　以上のように、従来では、高誘電率ゲート絶縁膜１０６ｃ，１０６ａとして、Ｌａを含むＨｆＳｉＯ膜を用いることにより、ｎ型ＭＯＳトランジスタｎＴｒ２，ｎＴｒ１の閾値電圧を低くする。一方、チャネル幅の大きいチャネル領域１２１ａ中におけるｐ型不純物の平均不純物濃度は、製造後が形成直後と実質的に同じになるものの、チャネル幅の小さいチャネル領域１２１ｃ中におけるｐ型不純物の平均不純物濃度は、製造後が形成直後よりも低くなるため、ｎ型ＭＯＳトランジスタｎＴｒ２の閾値電圧が、ｎ型ＭＯＳトランジスタｎＴｒ１の閾値電圧よりも低くなる。 As described above, conventionally, the threshold voltages of the n-type MOS transistors nTr2 and nTr1 are lowered by using HfSiO films containing La as the high dielectric constant gate insulating films 106c and 106a. On the other hand, the average impurity concentration of the p-type impurity in the channel region 121a having a large channel width is substantially the same as that immediately after formation after the manufacture, but the average impurity concentration of the p-type impurity in the channel region 121c having a small channel width. Therefore, the threshold voltage of the n-type MOS transistor nTr2 is lower than that immediately after formation, so that the threshold voltage of the n-type MOS transistor nTr1 becomes lower.
　このため、従来では、ゲート幅ＷTr1の大きいｎ型ＭＯＳトランジスタｎＴｒ１の閾値電圧を低くして、所望の閾値電圧にすることは可能なものの、ゲート幅ＷTr2の小さいｎ型ＭＯＳトランジスタｎＴｒ２の閾値電圧が低くなり過ぎて、所望の閾値電圧よりも低くなり、所望の閾値電圧にすることができないという問題がある。 Therefore, conventionally, although the threshold voltage of the n-type MOS transistor nTr1 having a large gate width WTr1 can be lowered to a desired threshold voltage, the threshold voltage of the n-type MOS transistor nTr2 having a small gate width WTr2 is There is a problem that the voltage becomes too low, becomes lower than the desired threshold voltage, and cannot be set to the desired threshold voltage.
　前記に鑑み、本発明の目的は、ゲート幅が互いに異なる第１，第２のＭＩＳトランジスタを備えた半導体装置において、第１，第２のＭＩＳトランジスタの閾値電圧を、所望の閾値電圧に制御することである。 In view of the above, an object of the present invention is to control the threshold voltage of the first and second MIS transistors to a desired threshold voltage in a semiconductor device including first and second MIS transistors having different gate widths. That is.
　前記の目的を達成するため、本発明に係る半導体装置は、第１のＭＩＳトランジスタ及び第２のＭＩＳトランジスタを備えた半導体装置であって、第１のＭＩＳトランジスタは、半導体基板における第１の活性領域上に形成され、第１の高誘電率絶縁膜を有する第１のゲート絶縁膜と、第１のゲート絶縁膜上に形成された第１のゲート電極とを備え、第２のＭＩＳトランジスタは、半導体基板における第２の活性領域上に形成され、第２の高誘電率絶縁膜を有する第２のゲート絶縁膜と、第２のゲート絶縁膜上に形成された第２のゲート電極とを備え、第１のゲート絶縁膜及び第２のゲート絶縁膜は、それぞれ調整用金属を含み、第１のＭＩＳトランジスタの第１のゲート幅は、第２のＭＩＳトランジスタの第２のゲート幅よりも小さく、第１のゲート絶縁膜中における調整用金属の平均調整用金属濃度は、第２のゲート絶縁膜中における調整用金属の平均調整用金属濃度に比べて低いことを特徴とし、第１の活性領域における第１のゲート電極の直下に形成された第１の不純物を含む第１のチャネル領域と、第２の活性領域における第２のゲート電極の直下に形成された第２の不純物を含む第２のチャネル領域とを備え、第１のチャネル領域中における第１の不純物の平均不純物濃度は、第２のチャネル領域中における第２の不純物の平均不純物濃度に比べて低いことが好ましい。 In order to achieve the above object, a semiconductor device according to the present invention is a semiconductor device including a first MIS transistor and a second MIS transistor, and the first MIS transistor is a first active in a semiconductor substrate. A first gate insulating film formed on the region and having a first high dielectric constant insulating film; and a first gate electrode formed on the first gate insulating film; and the second MIS transistor includes: A second gate insulating film formed on the second active region of the semiconductor substrate and having a second high dielectric constant insulating film; and a second gate electrode formed on the second gate insulating film. The first gate insulating film and the second gate insulating film each include an adjustment metal, and the first gate width of the first MIS transistor is larger than the second gate width of the second MIS transistor. small, The average adjustment metal concentration of the adjustment metal in the first gate insulating film is lower than the average adjustment metal concentration of the adjustment metal in the second gate insulating film. A first channel region including a first impurity formed immediately below the first gate electrode and a second channel including a second impurity formed immediately below the second gate electrode in the second active region. It is preferable that the average impurity concentration of the first impurity in the first channel region is lower than the average impurity concentration of the second impurity in the second channel region.
　本発明に係る半導体装置によると、第１のゲート絶縁膜中における調整用金属（例えばＬａ）の平均調整用金属濃度を、第２のゲート絶縁膜中における調整用金属（例えばＬａ）の平均調整用金属濃度よりも低くする。これにより、第１のＭＩＳトランジスタの実効仕事関数を、ミッドギャップ寄りの実効仕事関数にする一方、第２のＭＩＳトランジスタの実効仕事関数を、バンドエッジ寄りの実効仕事関数にして、第１のＭＩＳトランジスタの閾値電圧を、第２のＭＩＳトランジスタの閾値電圧よりも、高くすることができる。 According to the semiconductor device of the present invention, the average adjustment metal concentration of the adjustment metal (for example, La) in the first gate insulating film is set to the average adjustment metal concentration of the adjustment metal (for example, La) in the second gate insulating film. Lower than the metal concentration. As a result, the effective work function of the first MIS transistor is changed to an effective work function close to the midgap, while the effective work function of the second MIS transistor is changed to an effective work function close to the band edge. The threshold voltage of the transistor can be higher than the threshold voltage of the second MIS transistor.
　このため、第１，第２のチャネル領域の形成後に施される熱処理によって、製造後の第１のチャネル領域中における第１の不純物（例えばｐ型不純物）の平均不純物濃度が、製造後の第２のチャネル領域中における第２の不純物（例えばｐ型不純物）の平均不純物濃度よりも低くなることにより、第１のＭＩＳトランジスタの閾値電圧が、第２のＭＩＳトランジスタの閾値電圧よりも、低くなることがあっても、上述の通り、第１のＭＩＳトランジスタの閾値電圧を、第２のＭＩＳトランジスタの閾値電圧よりも、高くすることができる。このため、総合的には、第１のＭＩＳトランジスタの閾値電圧と、第２のＭＩＳトランジスタの閾値電圧とを、同じにすることができる。 For this reason, the average impurity concentration of the first impurity (for example, p-type impurity) in the first channel region after manufacture is increased by the heat treatment performed after the formation of the first and second channel regions. The threshold voltage of the first MIS transistor becomes lower than the threshold voltage of the second MIS transistor by lowering the average impurity concentration of the second impurity (eg, p-type impurity) in the two channel regions. Even so, as described above, the threshold voltage of the first MIS transistor can be made higher than the threshold voltage of the second MIS transistor. Therefore, comprehensively, the threshold voltage of the first MIS transistor and the threshold voltage of the second MIS transistor can be made the same.
　このように、第１のゲート絶縁膜中における調整用金属の平均調整用金属濃度を、第２のゲート絶縁膜中における調整用金属の平均調整用金属濃度よりも低くすることにより、第１，第２のチャネル領域中における第１，第２の不純物の平均不純物濃度の差異に起因して発生する第１，第２のＭＩＳトランジスタの閾値電圧の差異を補償することができる。従って、第１，第２のＭＩＳトランジスタの閾値電圧を、所望の閾値電圧に制御することができる。 In this way, by making the average adjustment metal concentration of the adjustment metal in the first gate insulating film lower than the average adjustment metal concentration of the adjustment metal in the second gate insulating film, It is possible to compensate for a difference in threshold voltage between the first and second MIS transistors caused by a difference in average impurity concentration between the first and second impurities in the second channel region. Therefore, the threshold voltage of the first and second MIS transistors can be controlled to a desired threshold voltage.
　本発明に係る半導体装置において、第１のゲート幅は、１００ｎｍ以下であり、第２のゲート幅は、２００ｎｍ以上であることが好ましい。 In the semiconductor device according to the present invention, it is preferable that the first gate width is 100 nm or less and the second gate width is 200 nm or more.
　本発明に係る半導体装置において、第１のＭＩＳトランジスタ及び第２のＭＩＳトランジスタは、ｎ型ＭＩＳトランジスタであり、調整用金属は、ランタンであることが好ましい。 In the semiconductor device according to the present invention, it is preferable that the first MIS transistor and the second MIS transistor are n-type MIS transistors, and the adjustment metal is lanthanum.
　本発明に係る半導体装置において、第１の高誘電率絶縁膜中における調整用金属の平均調整用金属濃度は、第２の高誘電率絶縁膜中における調整用金属の平均調整用金属濃度に比べて低いことが好ましい。 In the semiconductor device according to the present invention, the average adjustment metal concentration of the adjustment metal in the first high dielectric constant insulating film is higher than the average adjustment metal concentration of the adjustment metal in the second high dielectric constant insulating film. And low.
　本発明に係る半導体装置において、第１のゲート絶縁膜は、第１の活性領域上に形成された第１の界面層と、第１の界面層上に形成された第１の高誘電率絶縁膜とからなり、第２のゲート絶縁膜は、第２の活性領域上に形成された第２の界面層と、第２の界面層上に形成された第２の高誘電率絶縁膜とからなることが好ましい。 In the semiconductor device according to the present invention, the first gate insulating film includes a first interface layer formed on the first active region and a first high dielectric constant insulating film formed on the first interface layer. And the second gate insulating film includes a second interface layer formed on the second active region and a second high dielectric constant insulating film formed on the second interface layer. It is preferable to become.
　本発明に係る半導体装置において、第１の界面層及び第２の界面層は、シリコン酸化膜からなることが好ましい。 In the semiconductor device according to the present invention, the first interface layer and the second interface layer are preferably made of a silicon oxide film.
　本発明に係る半導体装置において、第１の高誘電率絶縁膜及び第２の高誘電率絶縁膜は、比誘電率が１０以上の金属酸化物からなることが好ましい。 In the semiconductor device according to the present invention, the first high dielectric constant insulating film and the second high dielectric constant insulating film are preferably made of a metal oxide having a relative dielectric constant of 10 or more.
　本発明に係る半導体装置において、第１のゲート電極は、第１のゲート絶縁膜上に形成された第１の金属膜と、第１の金属膜上に形成された第１のシリコン膜とからなり、第２のゲート電極は、第２のゲート絶縁膜上に形成された第２の金属膜と、第２の金属膜上に形成された第２のシリコン膜とからなることが好ましい。 In the semiconductor device according to the present invention, the first gate electrode includes a first metal film formed on the first gate insulating film and a first silicon film formed on the first metal film. Thus, the second gate electrode is preferably composed of a second metal film formed on the second gate insulating film and a second silicon film formed on the second metal film.
　前記の目的を達成するため、本発明に係る半導体装置の製造方法は、半導体基板における第１の活性領域上に形成された第１のゲート絶縁膜及び第１のゲート電極を有する第１のＭＩＳトランジスタと、半導体基板における第２の活性領域上に形成された第２のゲート絶縁膜及び第２のゲート電極を有する第２のＭＩＳトランジスタとを備えた半導体装置の製造方法であって、第１の活性領域及び第２の活性領域の上に、高誘電率絶縁膜を有するゲート絶縁膜形成膜を形成する工程（ａ）と、ゲート絶縁膜形成膜における第１の活性領域上に位置する第１の領域に調整用金属を導入して第１のゲート絶縁膜形成膜を形成する一方、ゲート絶縁膜形成膜における第２の活性領域上に位置する第２の領域に調整用金属を導入して第２のゲート絶縁膜形成膜を形成する工程（ｂ）と、第１のゲート絶縁膜形成膜及び第２のゲート絶縁膜形成膜の上に、ゲート電極形成膜を形成する工程（ｃ）と、ゲート電極形成膜、第１のゲート絶縁膜形成膜及び第２のゲート絶縁膜形成膜をパターニングして、第１の活性領域上に第１のゲート絶縁膜形成膜からなる第１のゲート絶縁膜及びゲート電極形成膜からなる第１のゲート電極を形成する一方、第２の活性領域上に第２のゲート絶縁膜形成膜からなる第２のゲート絶縁膜及びゲート電極形成膜からなる第２のゲート電極を形成する工程（ｄ）とを備え、第１のＭＩＳトランジスタの第１のゲート幅は、第２のＭＩＳトランジスタの第２のゲート幅よりも小さく、工程（ｂ）では、第１のゲート絶縁膜形成膜中における調整用金属の平均調整用金属濃度が、第２のゲート絶縁膜形成膜中における調整用金属の平均調整用金属濃度に比べて低くなるように、第１のゲート絶縁膜形成膜及び第２のゲート絶縁膜形成膜を形成することを特徴とする。 In order to achieve the above object, a method for manufacturing a semiconductor device according to the present invention includes a first MIS having a first gate insulating film and a first gate electrode formed on a first active region in a semiconductor substrate. A method for manufacturing a semiconductor device, comprising: a transistor; and a second MIS transistor having a second gate insulating film and a second gate electrode formed on a second active region in the semiconductor substrate. A step (a) of forming a gate insulating film forming film having a high dielectric constant insulating film on the active region and the second active region, and a first position located on the first active region in the gate insulating film forming film An adjustment metal is introduced into one region to form a first gate insulating film formation film, while an adjustment metal is introduced into a second region located on the second active region in the gate insulation film formation film. Second gate break A step (b) of forming a film forming film, a step (c) of forming a gate electrode forming film on the first gate insulating film forming film and the second gate insulating film forming film, and a gate electrode forming film The first gate insulating film forming film and the second gate insulating film forming film are patterned to form a first gate insulating film and a gate electrode made of the first gate insulating film forming film on the first active region. A first gate electrode made of a film is formed, while a second gate insulating film made of a second gate insulating film forming film and a second gate electrode made of a gate electrode forming film are formed on the second active region The first gate width of the first MIS transistor is smaller than the second gate width of the second MIS transistor. In step (b), the first gate insulating film is formed. Average adjustment gold of adjustment metal in the film The first gate insulating film forming film and the second gate insulating film forming film are formed so that the concentration is lower than the average adjusting metal concentration of the adjusting metal in the second gate insulating film forming film. It is characterized by that.
　本発明に係る半導体装置の製造方法によると、第１のゲート絶縁膜形成膜中における調整用金属（例えばＬａ）の平均調整用金属濃度を、第２のゲート絶縁膜形成膜中における調整用金属の平均調整用金属濃度よりも低くする。これにより、第１のＭＩＳトランジスタの実効仕事関数を、ミッドギャップ寄りの実効仕事関数にする一方、第２のＭＩＳトランジスタの実効仕事関数を、バンドエッジ寄りの実効仕事関数にして、第１のＭＩＳトランジスタの閾値電圧を、第２のＭＩＳトランジスタの閾値電圧よりも、高くすることができる。 According to the method for manufacturing a semiconductor device of the present invention, the average adjustment metal concentration of the adjustment metal (for example, La) in the first gate insulating film formation film is set to the adjustment metal in the second gate insulation film formation film. Lower than the average metal concentration for adjustment. As a result, the effective work function of the first MIS transistor is changed to an effective work function close to the midgap, while the effective work function of the second MIS transistor is changed to an effective work function close to the band edge. The threshold voltage of the transistor can be higher than the threshold voltage of the second MIS transistor.
　このため、第１，第２のチャネル領域の形成後に施される熱処理によって、製造後の第１のチャネル領域中における第１の不純物（例えばｐ型不純物）の平均不純物濃度が、製造後の第２のチャネル領域中における第２の不純物（例えばｐ型不純物）の平均不純物濃度よりも低くなることにより、第１のＭＩＳトランジスタの閾値電圧が、第２のＭＩＳトランジスタの閾値電圧よりも、低くなることがあっても、上述の通り、第１のＭＩＳトランジスタの閾値電圧を、第２のＭＩＳトランジスタの閾値電圧よりも、高くすることができる。このため、総合的には、第１のＭＩＳトランジスタの閾値電圧と、第２のＭＩＳトランジスタの閾値電圧とを、同じにすることができる。 For this reason, the average impurity concentration of the first impurity (for example, p-type impurity) in the first channel region after manufacture is increased by the heat treatment performed after the formation of the first and second channel regions. The threshold voltage of the first MIS transistor becomes lower than the threshold voltage of the second MIS transistor by lowering the average impurity concentration of the second impurity (eg, p-type impurity) in the two channel regions. Even so, as described above, the threshold voltage of the first MIS transistor can be made higher than the threshold voltage of the second MIS transistor. Therefore, comprehensively, the threshold voltage of the first MIS transistor and the threshold voltage of the second MIS transistor can be made the same.
　このように、第１のゲート絶縁膜形成膜中における調整用金属の平均調整用金属濃度を、第２のゲート絶縁膜形成膜中における調整用金属の平均調整用金属濃度よりも低くすることにより、第１，第２のチャネル領域中における第１，第２の不純物の平均不純物濃度の差異に起因して発生する第１，第２のＭＩＳトランジスタの閾値電圧の差異を補償することができる。従って、第１，第２のＭＩＳトランジスタの閾値電圧を、所望の閾値電圧に制御することができる。 Thus, by making the average adjustment metal concentration of the adjustment metal in the first gate insulating film formation film lower than the average adjustment metal concentration of the adjustment metal in the second gate insulation film formation film. The difference between the threshold voltages of the first and second MIS transistors generated due to the difference in the average impurity concentration of the first and second impurities in the first and second channel regions can be compensated. Therefore, the threshold voltage of the first and second MIS transistors can be controlled to a desired threshold voltage.
　本発明に係る半導体装置の製造方法において、工程（ｂ）は、ゲート絶縁膜形成膜における第１の領域上に、第１の膜厚を有し且つ調整用金属を含む第１の調整用金属膜を形成する工程（ｂ１）と、ゲート絶縁膜形成膜における第２の領域上に、第２の膜厚を有し且つ調整用金属を含む第２の調整用金属膜を形成する工程（ｂ２）と、工程（ｂ１）及び工程（ｂ２）の後に、熱処理により第１の調整用金属膜中の調整用金属をゲート絶縁膜形成膜における第１の領域に導入して第１のゲート絶縁膜形成膜を形成すると共に、第２の調整用金属膜中の調整用金属をゲート絶縁膜形成膜における第２の領域に導入して第２のゲート絶縁膜形成膜を形成する工程（ｂ３）とを備え、第１の膜厚は、第２の膜厚に比べて薄いことが好ましい。 In the method for manufacturing a semiconductor device according to the present invention, the step (b) includes a first adjustment metal having a first film thickness and including an adjustment metal on the first region in the gate insulating film formation film. A step (b1) of forming a film, and a step (b2) of forming a second adjustment metal film having the second film thickness and including the adjustment metal on the second region in the gate insulating film formation film And after the steps (b1) and (b2), the first gate insulating film is formed by introducing the adjusting metal in the first adjusting metal film into the first region of the gate insulating film forming film by heat treatment. A step (b3) of forming a formation film and introducing the adjustment metal in the second adjustment metal film into the second region of the gate insulation film formation film to form the second gate insulation film formation film; The first film thickness is preferably thinner than the second film thickness.
　本発明に係る半導体装置の製造方法において、工程（ｂ）は、ゲート絶縁膜形成膜上に、調整用金属を含む調整用金属膜を形成する工程（ｂ１）と、工程（ｂ１）の後に、第１の熱処理により調整用金属膜中の調整用金属をゲート絶縁膜形成膜における第１の領域に導入して第１のゲート絶縁膜形成膜を形成すると共に、調整用金属膜中の調整用金属をゲート絶縁膜形成膜における第２の領域に導入する工程（ｂ２）と、工程（ｂ２）の後に、調整用金属膜における第１のゲート絶縁膜形成膜上に位置する部分を除去する工程（ｂ３）と、工程（ｂ３）の後に、第２の熱処理により調整用金属膜中の調整用金属をゲート絶縁膜形成膜における第２の領域に追加導入して第２のゲート絶縁膜形成膜を形成する工程（ｂ４）とを備えていることが好ましい。 In the method for manufacturing a semiconductor device according to the present invention, the step (b) includes a step (b1) of forming an adjustment metal film containing an adjustment metal on the gate insulating film formation film, and a step (b1). The adjusting metal in the adjusting metal film is introduced into the first region of the gate insulating film forming film by the first heat treatment to form the first gate insulating film forming film, and the adjusting metal film in the adjusting metal film is adjusted. A step (b2) of introducing a metal into the second region of the gate insulating film forming film, and a step of removing a portion of the adjustment metal film located on the first gate insulating film forming film after the step (b2). After step (b3) and step (b3), a second gate insulating film forming film is formed by additionally introducing the adjusting metal in the adjusting metal film into the second region of the gate insulating film forming film by a second heat treatment. A step (b4) of forming Preferred.
　本発明に係る半導体装置及びその製造方法によると、第１のゲート絶縁膜中における調整用金属の平均調整用金属濃度を、第２のゲート絶縁膜中における調整用金属の平均調整用金属濃度よりも低くすることにより、第１，第２のチャネル領域中における第１，第２の不純物の平均不純物濃度の差異に起因して発生する第１，第２のＭＩＳトランジスタの閾値電圧の差異を補償することができる。従って、第１，第２のＭＩＳトランジスタの閾値電圧を、所望の閾値電圧に制御することができる。 According to the semiconductor device and the manufacturing method thereof according to the present invention, the average adjustment metal concentration of the adjustment metal in the first gate insulating film is greater than the average adjustment metal concentration of the adjustment metal in the second gate insulating film. To compensate for the difference in the threshold voltage of the first and second MIS transistors caused by the difference in the average impurity concentration of the first and second impurities in the first and second channel regions. can do. Therefore, the threshold voltage of the first and second MIS transistors can be controlled to a desired threshold voltage.
図１(a) ～(c) は、本発明の第１の実施形態に係る半導体装置の構成を示す図であり、図１(a) は平面図であり、図１(b) は図１(a) に示すIb-Ib線における断面図（ゲート幅方向の断面図）であり、図１(c) は図１(a) に示すIc-Ic線における断面図（ゲート長方向の断面図）である。FIGS. 1A to 1C are diagrams showing a configuration of a semiconductor device according to the first embodiment of the present invention, FIG. 1A is a plan view, and FIG. 1A is a cross-sectional view taken along the line Ib-Ib shown in FIG. 1 (a cross-sectional view in the gate width direction). FIG. 1C is a cross-sectional view taken along the line Ic-Ic shown in FIG. ). 図２(a) ～(c) は、本発明の第２の実施形態に係る半導体装置の製造方法を工程順に示すゲート幅方向の断面図である。FIGS. 2A to 2C are cross-sectional views in the gate width direction showing the method of manufacturing the semiconductor device according to the second embodiment of the present invention in the order of steps. 図３(a) ～(c) は、本発明の第２の実施形態に係る半導体装置の製造方法を工程順に示すゲート幅方向の断面図である。FIGS. 3A to 3C are cross-sectional views in the gate width direction showing the method of manufacturing the semiconductor device according to the second embodiment of the present invention in the order of steps. 図４(a) ～(c) は、本発明の第２の実施形態に係る半導体装置の製造方法を工程順に示すゲート幅方向の断面図である。FIGS. 4A to 4C are cross-sectional views in the gate width direction showing the method of manufacturing the semiconductor device according to the second embodiment of the present invention in the order of steps. 図５(a) ～(c) は、本発明の第２の実施形態の変形例に係る半導体装置の製造方法を工程順に示すゲート幅方向の断面図である。FIGS. 5A to 5C are cross-sectional views in the gate width direction showing the method of manufacturing the semiconductor device according to the modification of the second embodiment of the present invention in the order of steps. 図６は、従来の半導体装置の構成を示すゲート長方向の断面図である。FIG. 6 is a cross-sectional view in the gate length direction showing the configuration of a conventional semiconductor device. 図７は、従来の半導体装置の構成を示すゲート幅方向の断面図である。FIG. 7 is a cross-sectional view in the gate width direction showing the configuration of a conventional semiconductor device.
　以下に、本発明の各実施形態について図面を参照しながら説明する。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
　（第１の実施形態）
　以下に、本発明の第１の実施形態に係る半導体装置について、図１(a) ～(c) を参照しながら説明する。図１(a) ～(c) は、本発明の第１の実施形態に係る半導体装置の構成を示す図であり、図１(a) は平面図であり、図１(b) は図１(a) に示すIb-Ib線における断面図（ゲート幅方向の断面図）であり、図１(c) は図１(a) に示すIc-Ic線における断面図（ゲート長方向の断面図）である。図１(a) において、簡略的に図示する為に、素子分離領域１１に囲まれた第１，第２の活性領域、及び第１，第２のゲート電極のみを図示する。図１(a) ～(c) 、及び後述の図２(a) ～図５(c) において、「第１のｎＭＩＳ領域」とは、ｎ型の第１のＭＩＳトランジスタが形成される領域をいう。「第２のｎＭＩＳ領域」とは、ｎ型の第２のＭＩＳトランジスタが形成される領域をいう。第１のＭＩＳトランジスタは、例えばＳＲＡＭ（Static Random Access Memory）に用いられるトランジスタである。第２のＭＩＳトランジスタは、例えばロジック回路に用いられるトランジスタである。 (First embodiment)
A semiconductor device according to the first embodiment of the present invention will be described below with reference to FIGS. 1 (a) to 1 (c). 1A to 1C are diagrams showing a configuration of a semiconductor device according to the first embodiment of the present invention, FIG. 1A is a plan view, and FIG. 1B is a diagram of FIG. FIG. 1A is a cross-sectional view taken along the line Ib-Ib shown in FIG. 1A (a cross-sectional view in the gate width direction). FIG. 1C is a cross-sectional view taken along the line Ic-Ic shown in FIG. ). In FIG. 1A, for the sake of simplicity, only the first and second active regions and the first and second gate electrodes surrounded by the element isolation region 11 are illustrated. In FIGS. 1A to 1C and FIGS. 2A to 5C described later, the “first nMIS region” refers to a region where an n-type first MIS transistor is formed. Say. The “second nMIS region” refers to a region where an n-type second MIS transistor is formed. The first MIS transistor is a transistor used for, for example, an SRAM (Static Random Access Memory). The second MIS transistor is a transistor used in a logic circuit, for example.
　図１(a) ～(c) に示すように、本実施形態に係る半導体装置は、第１のＭＩＳトランジスタＴｒ１と、第２のＭＩＳトランジスタＴｒ２とを備えている。 As shown in FIGS. 1A to 1C, the semiconductor device according to this embodiment includes a first MIS transistor Tr1 and a second MIS transistor Tr2.
　図１(a) に示すように、半導体基板における第１のｎＭＩＳ領域には、素子分離領域１１に囲まれた第１の活性領域１０ａが形成されている。半導体基板における第２のｎＭＩＳ領域には、素子分離領域１１に囲まれた第２の活性領域１０ｂが形成されている。第１の活性領域１０ａ上には、第１のゲート絶縁膜（図１(b),(c)：１５Ａ参照）及び第１のゲート電極２０Ａが順次形成されている。第２の活性領域１０ｂ上には、第２のゲート絶縁膜（図１(b),(c)：１５Ｂ参照）及び第２のゲート電極２０Ｂが順次形成されている。 As shown in FIG. 1A, a first active region 10a surrounded by the element isolation region 11 is formed in the first nMIS region of the semiconductor substrate. In the second nMIS region in the semiconductor substrate, a second active region 10b surrounded by the element isolation region 11 is formed. A first gate insulating film (see FIGS. 1B and 1C: 15A) and a first gate electrode 20A are sequentially formed on the first active region 10a. A second gate insulating film (see FIGS. 1B and 1C: 15B) and a second gate electrode 20B are sequentially formed on the second active region 10b.
　第１のＭＩＳトランジスタＴｒ１の第１のゲート幅Ｗ１は、第２のＭＩＳトランジスタＴｒ２の第２のゲート幅Ｗ２よりも小さい（Ｗ１＜Ｗ２）。第１のゲート幅Ｗ１は、例えば１００ｎｍ以下である。第２のゲート幅Ｗ２は、例えば２００ｎｍ以上である。ここで、「第１，第２のゲート幅Ｗ１，Ｗ２」とは、第１，第２の活性領域１０ａ，１０ｂのゲート幅方向の幅をいう。 The first gate width W1 of the first MIS transistor Tr1 is smaller than the second gate width W2 of the second MIS transistor Tr2 (W1 <W2). The first gate width W1 is, for example, 100 nm or less. The second gate width W2 is, for example, 200 nm or more. Here, “first and second gate widths W1 and W2” refer to the widths of the first and second active regions 10a and 10b in the gate width direction.
　図１(b) ～(c) に示すように、半導体基板１０には、ｐ型ウェル領域１２が形成されている。 As shown in FIGS. 1B to 1C, a p-type well region 12 is formed in the semiconductor substrate 10.
　第１のＭＩＳトランジスタＴｒ１は、図１(b) ～(c) に示すように、第１の活性領域１０ａ上に形成された第１のゲート絶縁膜１５Ａと、第１のゲート絶縁膜１５Ａ上に形成された第１のゲート電極２０Ａと、第１の活性領域１０ａにおける第１のゲート電極２０Ａの直下に形成されたｐ型の第１のチャネル領域１３ａと、第１のゲート電極２０Ａの側面上に形成された第１のオフセットスペーサ２１ａと、第１の活性領域１０ａにおける第１のゲート電極２０Ａの側方下に形成された第１のｎ型エクステンション領域２２ａ（特に、図１(c) 参照）と、第１のゲート電極２０Ａの側面上に第１のオフセットスペーサ２１ａを介して形成された第１のサイドウォール２３ａと、第１の活性領域１０ａにおける第１のサイドウォール２３ａの外側方下に形成された第１のｎ型ソースドレイン領域２４ａ（特に、図１(c) 参照）とを備えている。 As shown in FIGS. 1B to 1C, the first MIS transistor Tr1 includes a first gate insulating film 15A formed on the first active region 10a and the first gate insulating film 15A. The first gate electrode 20A formed in the first active region 10a, the p-type first channel region 13a formed immediately below the first gate electrode 20A in the first active region 10a, and the side surface of the first gate electrode 20A The first offset spacer 21a formed above, and the first n-type extension region 22a formed below the side of the first gate electrode 20A in the first active region 10a (particularly, FIG. 1C) The first sidewall 23a formed on the side surface of the first gate electrode 20A via the first offset spacer 21a, and the outside of the first sidewall 23a in the first active region 10a. Square first n-type source drain region 24a formed under (especially FIG. 1 (c) refer) and a.
　第２のＭＩＳトランジスタＴｒ２は、図１(b) ～(c) に示すように、第２の活性領域１０ｂ上に形成された第２のゲート絶縁膜１５Ｂと、第２のゲート絶縁膜１５Ｂ上に形成された第２のゲート電極２０Ｂと、第２の活性領域１０ｂにおける第２のゲート電極２０Ｂの直下に形成されたｐ型の第２のチャネル領域１３ｂと、第２のゲート電極２０Ｂの側面上に形成された第２のオフセットスペーサ２１ｂと、第２の活性領域１０ｂにおける第２のゲート電極２０Ｂの側方下に形成された第２のｎ型エクステンション領域２２ｂ（特に、図１(c) 参照）と、第２のゲート電極２０Ｂの側面上に第２のオフセットスペーサ２１ｂを介して形成された第２のサイドウォール２３ｂと、第２の活性領域１０ｂにおける第２のサイドウォール２３ｂの外側方下に形成された第２のｎ型ソースドレイン領域２４ｂ（特に、図１(c) 参照）とを備えている。 As shown in FIGS. 1B to 1C, the second MIS transistor Tr2 includes a second gate insulating film 15B formed on the second active region 10b and a second gate insulating film 15B. The second gate electrode 20B formed in the second active region 10b, the p-type second channel region 13b formed immediately below the second gate electrode 20B in the second active region 10b, and the side surface of the second gate electrode 20B The second offset spacer 21b formed above, and the second n-type extension region 22b formed below the side of the second gate electrode 20B in the second active region 10b (in particular, FIG. 1C) The second sidewall 23b formed on the side surface of the second gate electrode 20B via the second offset spacer 21b, and the second sidewall 23b outside the second active region 10b. The second n-type source drain region 24b formed under the square (in particular, FIG. 1 (c) refer) and a.
　第１のチャネル領域１３ａは、第１の不純物（例えばｐ型不純物）を含む。第２のチャネル領域１３ｂは、第２の不純物（例えばｐ型不純物）を含む。第１のチャネル領域１３ａ中におけるｐ型不純物の平均不純物濃度は、第２のチャネル領域１３ｂ中におけるｐ型不純物の平均不純物濃度よりも低い。なお、後述の第２の実施形態にも記載の通り、形成直後の第１のチャネル領域（図２(a)：１３Ａ参照）中におけるｐ型不純物の平均不純物濃度と、形成直後の第２のチャネル領域（図２(a)：１３Ｂ参照）中におけるｐ型不純物の平均不純物濃度とは、同じである。しかしながら、第１，第２のチャネル領域の形成後に施される熱処理（例えば、第１，第２のｎ型ソースドレイン注入領域中に含まれるｎ型不純物を活性化させる為の熱処理等）により、第１，第２のチャネル領域中に含まれるｐ型不純物が、素子分離領域１１中に拡散する。このため、製造後の第１のチャネル領域１３ａ中におけるｐ型不純物の平均不純物濃度は、製造後の第２のチャネル領域１３ｂ中におけるｐ型不純物の平均不純物濃度よりも低くなる。 The first channel region 13a contains a first impurity (for example, a p-type impurity). The second channel region 13b includes a second impurity (for example, a p-type impurity). The average impurity concentration of the p-type impurity in the first channel region 13a is lower than the average impurity concentration of the p-type impurity in the second channel region 13b. As described in the second embodiment described later, the average impurity concentration of the p-type impurity in the first channel region (see FIG. 2 (a): 13A) immediately after the formation and the second impurity immediately after the formation. The average impurity concentration of the p-type impurity in the channel region (see FIG. 2A: 13B) is the same. However, by heat treatment (for example, heat treatment for activating n-type impurities contained in the first and second n-type source / drain implantation regions) performed after the formation of the first and second channel regions, The p-type impurity contained in the first and second channel regions diffuses into the element isolation region 11. For this reason, the average impurity concentration of the p-type impurity in the first channel region 13a after manufacture is lower than the average impurity concentration of the p-type impurity in the second channel region 13b after manufacture.
　第１，第２のゲート絶縁膜１５Ａ，１５Ｂは、それぞれ調整用金属（例えばＬａ）を含む。第１のゲート絶縁膜１５Ａ中における調整用金属の平均調整用金属濃度は、第２のゲート絶縁膜１５Ｂ中における調整用金属の平均調整用金属濃度よりも低い。 The first and second gate insulating films 15A and 15B each contain an adjustment metal (for example, La). The average adjusting metal concentration of the adjusting metal in the first gate insulating film 15A is lower than the average adjusting metal concentration of the adjusting metal in the second gate insulating film 15B.
　第１のゲート絶縁膜１５Ａは、第１の界面層１４ａと、調整用金属を含む第１の高誘電率絶縁膜１５ａとを有する。第２のゲート絶縁膜１５Ｂは、第２の界面層１４ｂと、調整用金属を含む第２の高誘電率絶縁膜１５ｂとを有する。第１の高誘電率絶縁膜１５ａ中における調整用金属の平均調整用金属濃度は、第２の高誘電率絶縁膜１５ｂ中における調整用金属の平均調整用金属濃度よりも低い。具体的には、第１の高誘電率絶縁膜１５ａ中におけるＬａの平均Ｌａ濃度は、例えば２０％以下である。第２の高誘電率絶縁膜１５ｂ中におけるＬａの平均Ｌａ濃度は、例えば２５％である。 The first gate insulating film 15A has a first interface layer 14a and a first high dielectric constant insulating film 15a containing an adjustment metal. The second gate insulating film 15B has a second interface layer 14b and a second high dielectric constant insulating film 15b containing an adjustment metal. The average adjusting metal concentration of the adjusting metal in the first high dielectric constant insulating film 15a is lower than the average adjusting metal concentration of the adjusting metal in the second high dielectric constant insulating film 15b. Specifically, the average La concentration of La in the first high dielectric constant insulating film 15a is, for example, 20% or less. The average La concentration of La in the second high dielectric constant insulating film 15b is, for example, 25%.
　第１，第２の高誘電率絶縁膜１５ａ，１５ｂは、例えば比誘電率が１０以上の金属酸化物からなり、具体的には例えば、Ｌａを含むＨｆＳｉＯからなる。第１，第２の界面層１４ａ，１４ｂは、例えばシリコン酸化膜からなる。 The first and second high dielectric constant insulating films 15a and 15b are made of, for example, a metal oxide having a relative dielectric constant of 10 or more, specifically, for example, HfSiO containing La. The first and second interface layers 14a and 14b are made of, for example, a silicon oxide film.
　第１のゲート電極２０Ａは、第１の金属膜１９ａと、第１のシリコン膜２０ａとを有する。第２のゲート電極２０Ｂは、第２の金属膜１９ｂと、第２のシリコン膜２０ｂとを有する。 The first gate electrode 20A has a first metal film 19a and a first silicon film 20a. The second gate electrode 20B has a second metal film 19b and a second silicon film 20b.
　本実施形態によると、第１のゲート絶縁膜１５Ａ中における調整用金属（例えばＬａ）の平均調整用金属濃度を、第２のゲート絶縁膜１５Ｂ中における調整用金属（例えばＬａ）の平均調整用金属濃度よりも低くする。これにより、第１のＭＩＳトランジスタＴｒ１の実効仕事関数を、ミッドギャップ寄りの実効仕事関数にする一方、第２のＭＩＳトランジスタＴｒ２の実効仕事関数を、バンドエッジ寄りの実効仕事関数にして、第１のＭＩＳトランジスタＴｒ１の閾値電圧を、第２のＭＩＳトランジスタＴｒ２の閾値電圧よりも、高くすることができる。 According to this embodiment, the average adjustment metal concentration of the adjustment metal (for example, La) in the first gate insulating film 15A is set to the average adjustment metal concentration of the adjustment metal (for example, La) in the second gate insulating film 15B. Lower than metal concentration. As a result, the effective work function of the first MIS transistor Tr1 is set to an effective work function close to the midgap, while the effective work function of the second MIS transistor Tr2 is set to an effective work function close to the band edge. The threshold voltage of the second MIS transistor Tr1 can be made higher than the threshold voltage of the second MIS transistor Tr2.
　このため、第１，第２のチャネル領域の形成後に施される熱処理によって、製造後の第１のチャネル領域１３ａ中におけるｐ型不純物の平均不純物濃度が、製造後の第２のチャネル領域１３ｂ中におけるｐ型不純物の平均不純物濃度よりも低くなることにより、第１のＭＩＳトランジスタＴｒ１の閾値電圧が、第２のＭＩＳトランジスタＴｒ２の閾値電圧よりも、低くなることがあっても、上述の通り、第１のＭＩＳトランジスタＴｒ１の閾値電圧を、第２のＭＩＳトランジスタＴｒ２の閾値電圧よりも、高くすることができる。このため、総合的には、第１のＭＩＳトランジスタＴｒ１の閾値電圧と、第２のＭＩＳトランジスタＴｒ２の閾値電圧とを、同じにすることができる。 For this reason, the average impurity concentration of the p-type impurity in the first channel region 13a after manufacture is increased in the second channel region 13b after manufacture by the heat treatment performed after the formation of the first and second channel regions. Even if the threshold voltage of the first MIS transistor Tr1 may be lower than the threshold voltage of the second MIS transistor Tr2 due to being lower than the average impurity concentration of the p-type impurity at The threshold voltage of the first MIS transistor Tr1 can be made higher than the threshold voltage of the second MIS transistor Tr2. Therefore, comprehensively, the threshold voltage of the first MIS transistor Tr1 and the threshold voltage of the second MIS transistor Tr2 can be made the same.
　このように、第１のゲート絶縁膜１５Ａ中における調整用金属の平均調整用金属濃度を、第２のゲート絶縁膜１５Ｂ中における調整用金属の平均調整用金属濃度よりも低くすることにより、第１，第２のチャネル領域１３ａ，１３ｂ中におけるｐ型不純物の平均不純物濃度の差異に起因して発生する第１，第２のＭＩＳトランジスタＴｒ１，Ｔｒ２の閾値電圧の差異を補償することができる。従って、第１，第２のＭＩＳトランジスタＴｒ１，Ｔｒ２の閾値電圧を、所望の閾値電圧に制御することができる。 As described above, the average adjustment metal concentration of the adjustment metal in the first gate insulating film 15A is made lower than the average adjustment metal concentration of the adjustment metal in the second gate insulating film 15B. It is possible to compensate for the difference in threshold voltage between the first and second MIS transistors Tr1 and Tr2, which is caused by the difference in the average impurity concentration of the p-type impurities in the first and second channel regions 13a and 13b. Therefore, the threshold voltages of the first and second MIS transistors Tr1 and Tr2 can be controlled to a desired threshold voltage.
　このため、ＬＳＩの高集積化に伴い、逆ナローチャネル効果が発生する（即ち、ＭＩＳトランジスタのゲート幅が小さくなるに連れてＭＩＳトランジスタの閾値電圧が低下する）ことがあっても、ゲート絶縁膜中における調整用金属の平均調整用金属濃度を低くすることにより、逆ナローチャネル効果に起因するＭＩＳトランジスタの閾値電圧の低下を補償することができる。このため、ＭＩＳトランジスタの閾値電圧を、所望の閾値電圧に制御しながら、ＬＳＩを高集積化することができるので、ＬＳＩの高集積化を加速することができる。 For this reason, even if the LSI is highly integrated, the reverse narrow channel effect occurs (that is, the threshold voltage of the MIS transistor decreases as the gate width of the MIS transistor decreases). By reducing the average adjustment metal concentration of the adjustment metal in the medium, it is possible to compensate for a decrease in the threshold voltage of the MIS transistor due to the reverse narrow channel effect. For this reason, the LSI can be highly integrated while controlling the threshold voltage of the MIS transistor to a desired threshold voltage, so that the high integration of the LSI can be accelerated.
　例えば、第１のＭＩＳトランジスタＴｒ１を、ＳＲＡＭ等のメモリを構成するトランジスタとして用いた場合、第１のＭＩＳトランジスタＴｒ１の閾値電圧を、所望の閾値電圧に制御しながら、メモリを高集積化することができるので、メモリの高集積化を加速することができる。 For example, when the first MIS transistor Tr1 is used as a transistor constituting a memory such as an SRAM, the memory is highly integrated while controlling the threshold voltage of the first MIS transistor Tr1 to a desired threshold voltage. Therefore, high integration of the memory can be accelerated.
　（第２の実施形態）
　以下に、本発明の第２の実施形態に係る半導体装置の製造方法について、図２(a) ～(c) 、図３(a) ～(c) 及び図４(a) ～(c) を参照しながら説明する。図２(a) ～図４(c) は、本発明の第２の実施形態に係る半導体装置の製造方法を工程順に示すゲート幅方向の断面図である。図２(a) ～図４(c) において、左側から順に、第１のｎＭＩＳ領域、第１のｐＭＩＳ領域、第２のｐＭＩＳ領域及び第２のｎＭＩＳ領域を示す。図２(a) ～図４(c) において、「第１のｐＭＩＳ領域」とは、ｐ型の第３のＭＩＳトランジスタが形成される領域をいう。「第２のｐＭＩＳ領域」とは、ｐ型の第４のＭＩＳトランジスタが形成される領域をいう。第１，第３のＭＩＳトランジスタは、例えばＳＲＡＭに用いられるトランジスタである。第２，第４のＭＩＳトランジスタは、例えばロジック回路に用いられるトランジスタである。また、図２(a) ～図４(c) において、第１の実施形態における構成要素と同一の構成要素には、図１(a) ～(c) に示す符号と同一の符号を付す。 (Second Embodiment)
2A to 2C, FIGS. 3A to 3C, and FIGS. 4A to 4C are described below with respect to a method for manufacturing a semiconductor device according to the second embodiment of the present invention. The description will be given with reference. 2A to 4C are cross-sectional views in the gate width direction showing the method of manufacturing the semiconductor device according to the second embodiment of the present invention in the order of steps. 2A to 4C, the first nMIS region, the first pMIS region, the second pMIS region, and the second nMIS region are shown in order from the left side. In FIG. 2A to FIG. 4C, the “first pMIS region” refers to a region where a p-type third MIS transistor is formed. The “second pMIS region” refers to a region where a p-type fourth MIS transistor is formed. The first and third MIS transistors are transistors used for SRAM, for example. The second and fourth MIS transistors are transistors used in a logic circuit, for example. In FIGS. 2 (a) to 4 (c), the same reference numerals as those shown in FIGS. 1 (a) to (c) are attached to the same components as those in the first embodiment.
　まず、図２(a) に示すように、例えばＳＴＩ（Shallow Trench Isolation）法により、例えばシリコン（Ｓｉ）からなる半導体基板１０の上部に、例えば深さが２００ｎｍ～４００ｎｍのトレンチ内に例えばシリコン酸化膜（ＳｉＯ2膜）が埋め込まれた素子分離領域１１を選択的に形成する。これにより、半導体基板１０における第１，第２のｎＭＩＳ領域に、素子分離領域１１に囲まれた第１，第２の活性領域１０ａ，１０ｂを形成する。それと共に、半導体基板１０における第１，第２のｐＭＩＳ領域に、素子分離領域１１に囲まれた第３，第４の活性領域１０ｃ，１０ｄを形成する。第１の活性領域１０ａのゲート幅方向の幅（即ち、第１のゲート幅）Ｗ１は、第２の活性領域１０ｂのゲート幅方向の幅（即ち、第２のゲート幅）Ｗ２よりも小さい（Ｗ１＜Ｗ２）。第１のゲート幅Ｗ１は、例えば１００ｎｍ以下である。第２のゲート幅Ｗ２は、例えば２００ｎｍ以上である。第３の活性領域１０ｃのゲート幅方向の幅（即ち、第３のゲート幅）は、第４の活性領域１０ｄのゲート幅方向の幅（即ち、第４のゲート幅）よりも小さい。 First, as shown in FIG. 2A, for example, silicon oxide is formed on an upper portion of a semiconductor substrate 10 made of, for example, silicon (Si) by, for example, STI (Shallow Trench Isolation), for example, in a trench having a depth of 200 nm to 400 nm. The element isolation region 11 in which the film (SiO 2 film) is embedded is selectively formed. As a result, first and second active regions 10 a and 10 b surrounded by the element isolation region 11 are formed in the first and second nMIS regions of the semiconductor substrate 10. At the same time, third and fourth active regions 10 c and 10 d surrounded by the element isolation region 11 are formed in the first and second pMIS regions in the semiconductor substrate 10. The width of the first active region 10a in the gate width direction (ie, the first gate width) W1 is smaller than the width of the second active region 10b in the gate width direction (ie, the second gate width) W2 ( W1 <W2). The first gate width W1 is, for example, 100 nm or less. The second gate width W2 is, for example, 200 nm or more. The width of the third active region 10c in the gate width direction (ie, the third gate width) is smaller than the width of the fourth active region 10d in the gate width direction (ie, the fourth gate width).
　その後、半導体基板１０における第１，第２のｎＭＩＳ領域に、第１，第２のｐ型ウェル領域１２ｘ，１２ｙを形成する。一方、半導体基板１０における第１，第２のｐＭＩＳ領域に、ｎ型ウェル領域１２ｚを形成する。 Thereafter, first and second p- type well regions 12x and 12y are formed in the first and second nMIS regions in the semiconductor substrate 10. On the other hand, the n-type well region 12z is formed in the first and second pMIS regions in the semiconductor substrate 10.
　その後、イオン注入により、例えば注入エネルギーが１０ｋｅＶ，注入ドーズ量が５×１０12ｉｏｎｓ／ｃｍ2のイオン注入条件で、第１，第２の活性領域１０ａ，１０ｂに、例えばボロン（Ｂ）等のｐ型不純物を注入する。これにより、第１，第２の活性領域１０ａ，１０ｂの上部に、ｐ型の第１，第２のチャネル領域１３Ａ，１３Ｂを形成する。一方、イオン注入により、例えば注入エネルギーが８５ｋｅＶ，注入ドーズ量が７×１０12ｉｏｎｓ／ｃｍ2のイオン注入条件で、第３，第４の活性領域１０ｃ，１０ｄに、例えばヒ素（Ａｓ）等のｎ型不純物を注入する。これにより、第３，第４の活性領域１０ｃ，１０ｄの上部に、ｎ型の第３，第４のチャネル領域１３Ｃ，１３Ｄを形成する。 After that, by ion implantation, for example, an implantation energy of 10 keV and an implantation dose of 5 × 10 12 ions / cm 2 are implanted into the first and second active regions 10a and 10b, for example, boron (B). A p-type impurity is implanted. As a result, p-type first and second channel regions 13A and 13B are formed above the first and second active regions 10a and 10b. On the other hand, by ion implantation, for example, arsenic (As) or the like is implanted into the third and fourth active regions 10c and 10d under an ion implantation condition of an implantation energy of 85 keV and an implantation dose of 7 × 10 12 ions / cm 2 , for example. An n-type impurity is implanted. As a result, n-type third and fourth channel regions 13C and 13D are formed above the third and fourth active regions 10c and 10d.
　このとき、第１のチャネル領域１３Ａと第２のチャネル領域１３Ｂとは、同一のイオン注入条件で形成されるため、形成直後の第１のチャネル領域１３Ａ中におけるｐ型不純物の平均不純物濃度Ｘ13Aと、形成直後の第２のチャネル領域１３Ｂ中におけるｐ型不純物の平均不純物濃度Ｘ13Bとは、同じである（Ｘ13A＝Ｘ13B）。同様に、第３のチャネル領域１３Ｃ中におけるｎ型不純物の平均不純物濃度と、第４のチャネル領域１３Ｄ中におけるｎ型不純物の平均不純物濃度とは、同じである。 At this time, since the first channel region 13A and the second channel region 13B are formed under the same ion implantation conditions, the average impurity concentration X13A of the p-type impurity in the first channel region 13A immediately after the formation is The average impurity concentration X13B of the p-type impurity in the second channel region 13B immediately after formation is the same (X13A = X13B). Similarly, the average impurity concentration of n-type impurities in the third channel region 13C and the average impurity concentration of n-type impurities in the fourth channel region 13D are the same.
　次に、図２(b) に示すように、例えば酸素ガスを含む雰囲気中での熱処理により、第１，第３，第４，第２の活性領域１０ａ，１０ｃ，１０ｄ，１０ｂの表面部を酸化する。これにより、第１，第３，第４，第２の活性領域１０ａ，１０ｃ，１０ｄ，１０ｂ上に、例えば膜厚が１ｎｍ～２ｎｍのシリコン酸化膜からなる第１，第３，第４，第２の界面層１４Ａ，１４Ｃ，１４Ｄ，１４Ｂを形成する。 Next, as shown in FIG. 2B, the surface portions of the first, third, fourth, and second active regions 10a, 10c, 10d, and 10b are formed by, for example, heat treatment in an atmosphere containing oxygen gas. Oxidize. As a result, the first, third, fourth, and second active regions 10a, 10c, 10d, and 10b are formed of, for example, a silicon oxide film having a thickness of 1 nm to 2 nm. Two interface layers 14A, 14C, 14D, and 14B are formed.
　その後、例えばＭＯＣＶＤ（Metal Organic Chemical Vapor Deposition）法により、原料として例えばテトラジメチルアミノシリコン及びテトラジエチルアミノハフニウムを用いて、半導体基板１０上の全面に、例えば膜厚が１ｎｍ～２ｎｍのＨｆＳｉＯ膜からなる高誘電率絶縁膜１５を形成する。 After that, for example, by MOCVD (Metal-Organic-Chemical-Vapor-Deposition) method, using, for example, tetradimethylaminosilicon and tetradiethylaminohafnium as raw materials, the entire surface of the semiconductor substrate 10 is made of a HfSiO film having a film thickness of, for example, 1 nm to 2 nm. A dielectric insulating film 15 is formed.
　このようにして、第１，第３，第４，第２の活性領域１０ａ，１０ｃ，１０ｄ，１０ｂ上に、第１，第３，第４，第２の界面層１４Ａ，１４Ｃ，１４Ｄ，１４Ｂ及び高誘電率絶縁膜１５を有するゲート絶縁膜形成膜を形成する。 In this manner, the first, third, fourth, and second interface layers 14A, 14C, 14D, and 14B are formed on the first, third, fourth, and second active regions 10a, 10c, 10d, and 10b. Then, a gate insulating film forming film having the high dielectric constant insulating film 15 is formed.
　その後、例えばスパッタ法又はＡＬＤ（Atomic Layer Deposition）法により、高誘電率絶縁膜１５上に、例えば膜厚が０．５ｎｍ～１．５ｎｍのアルミニウム（Ａｌ）を含む調整用金属膜１６を形成する。その後、例えばスパッタ法又はＡＬＤ法により、調整用金属膜１６上に、例えば膜厚が１０ｎｍ～２０ｎｍの窒化チタン膜（ＴｉＮ膜）からなる保護膜１７を形成する。 Thereafter, an adjustment metal film 16 containing, for example, aluminum (Al) with a film thickness of 0.5 nm to 1.5 nm is formed on the high dielectric constant insulating film 15 by, for example, sputtering or ALD (Atomic Layer Deposition). . Thereafter, a protective film 17 made of a titanium nitride film (TiN film) having a film thickness of 10 nm to 20 nm, for example, is formed on the adjustment metal film 16 by, for example, sputtering or ALD.
　次に、図２(c) に示すように、リソグラフィにより、保護膜１７上に、第１，第２のｎＭＩＳ領域を開口し且つ第１，第２のｐＭＩＳ領域を覆うレジストＲｅ１を形成する。その後、例えばウェットエッチングにより、レジストＲｅ１をマスクとして、保護膜１７及び調整用金属膜１６における第１，第２のｎＭＩＳ領域に形成された部分を除去する。その後、レジストＲｅ１を除去する。 Next, as shown in FIG. 2C, a resist Re1 is formed on the protective film 17 by lithography to open the first and second nMIS regions and cover the first and second pMIS regions. Thereafter, the portions formed in the first and second nMIS regions in the protective film 17 and the adjustment metal film 16 are removed by wet etching, for example, using the resist Re1 as a mask. Thereafter, the resist Re1 is removed.
　次に、図３(a) に示すように、例えばスパッタ法により、半導体基板１０上の全面に、例えば膜厚が０．５ｎｍ～１．５ｎｍのＬａを含む調整用金属膜１８を形成する。 Next, as shown in FIG. 3A, an adjustment metal film 18 containing La having a thickness of 0.5 nm to 1.5 nm, for example, is formed on the entire surface of the semiconductor substrate 10 by, for example, sputtering.
　次に、図３(b) に示すように、リソグラフィにより、調整用金属膜１８上に、第１のｎ，第１のｐＭＩＳ領域を開口し且つ第２のｐ，第２のｎＭＩＳ領域を覆うレジストＲｅ２を形成する。なお、レジストＲｅ２は、少なくとも第１の活性領域１０ａと対応する領域を開口するレジストであればよい。その後、例えばウェットエッチングにより、レジストＲｅ２をマスクとして、調整用金属膜１８における第１のｎ，第１のｐＭＩＳ領域に形成された部分を除去して、該部分を薄膜化する。これにより、該部分の膜厚を、例えば０．２ｎｍ～０．８ｎｍにする。該部分の膜厚は、第１，第２のゲート幅（図２(a)：Ｗ１，Ｗ２参照）及び調整用金属膜１８の膜厚に基づいて設定される。 Next, as shown in FIG. 3B, the first n and first pMIS regions are opened and the second p and second nMIS regions are covered on the adjustment metal film 18 by lithography. A resist Re2 is formed. The resist Re2 may be any resist that opens at least a region corresponding to the first active region 10a. Thereafter, the portion formed in the first n and first pMIS regions in the adjustment metal film 18 is removed by wet etching, for example, using the resist Re2 as a mask, and the portion is thinned. Thereby, the film thickness of the portion is set to, for example, 0.2 nm to 0.8 nm. The film thickness of the portion is set based on the first and second gate widths (see FIG. 2A: W1 and W2) and the film thickness of the adjustment metal film 18.
　このようにして、第１～第４の界面層１４Ａ～１４Ｄ及び高誘電率絶縁膜１５を有するゲート絶縁膜形成膜における、第１の活性領域１０ａ上に位置する第１の領域上に、第１の膜厚（例えば０．２ｎｍ～０．８ｎｍ）を有する第１の調整用金属膜１８ａを形成する。一方、該ゲート絶縁膜形成膜における、第２の活性領域１０ｂ上に位置する第２の領域上に、第２の膜厚（例えば０．５ｎｍ～１．５ｎｍ）を有する第２の調整用金属膜１８ｂを形成する。 In this manner, in the gate insulating film forming film having the first to fourth interface layers 14A to 14D and the high dielectric constant insulating film 15, the first region located on the first active region 10a is formed on the first region. A first adjustment metal film 18a having a thickness of 1 (for example, 0.2 nm to 0.8 nm) is formed. On the other hand, a second adjustment metal having a second film thickness (for example, 0.5 nm to 1.5 nm) on the second region located on the second active region 10b in the gate insulating film formation film. A film 18b is formed.
　その後、レジストＲｅ２を除去する。 Thereafter, the resist Re2 is removed.
　次に、図３(c) に示すように、例えば７００℃，１２０秒の熱処理を行う。 Next, as shown in FIG. 3C, heat treatment is performed at 700 ° C. for 120 seconds, for example.
　これにより、第１の調整用金属膜１８ａ中の調整用金属（例えばＬａ）を、ゲート絶縁膜形成膜における第１の領域（特に、高誘電率絶縁膜１５における第１の活性領域１０ａ上に位置する領域）に導入して、第１の界面層１４Ａ及び調整用金属を含む第１の高誘電率絶縁膜１５ｘを有する第１のゲート絶縁膜形成膜１５Ｘを形成する。第１の高誘電率絶縁膜１５ｘは、例えばＬａを含むＨｆＳｉＯ膜からなる。 As a result, the adjustment metal (for example, La) in the first adjustment metal film 18a is applied to the first region in the gate insulating film formation film (particularly, on the first active region 10a in the high dielectric constant insulating film 15). The first gate insulating film forming film 15X having the first interface layer 14A and the first high dielectric constant insulating film 15x containing the adjusting metal is formed. The first high dielectric constant insulating film 15x is made of, for example, an HfSiO film containing La.
　それと共に、調整用金属膜１６中の調整用金属（例えばＡｌ）を、ゲート絶縁膜形成膜における第３，第４の活性領域１０ｃ，１０ｄ上に位置する第３，第４の領域（特に、高誘電率絶縁膜１５における第３，第４の活性領域１０ｃ，１０ｄ上に位置する領域）に導入して、第３，第４の界面層１４Ｃ，１４Ｄ及び調整用金属を含む第３の高誘電率絶縁膜１５ｚを有する第３のゲート絶縁膜形成膜１５Ｚを形成する。第３の高誘電率絶縁膜１５ｚは、例えばＡｌを含むＨｆＳｉＯ膜からなる。 At the same time, the adjustment metal (for example, Al) in the adjustment metal film 16 is moved to the third and fourth regions (particularly, on the third and fourth active regions 10c and 10d in the gate insulating film formation film). The third dielectric layer 15 is introduced into the third and fourth active regions 10c and 10d) in the high dielectric constant insulating film 15, and the third high and the fourth interface layers 14C and 14D and the third metal including the adjusting metal are introduced. A third gate insulating film forming film 15Z having a dielectric constant insulating film 15z is formed. The third high dielectric constant insulating film 15z is made of, for example, an HfSiO film containing Al.
　それと共に、第２の調整用金属膜１８ｂ中の調整用金属（例えばＬａ）を、ゲート絶縁膜形成膜における第２の領域（特に、高誘電率絶縁膜１５における第２の活性領域１０ｂ上に位置する領域）に導入して、第２の界面層１４Ｂ及び調整用金属を含む第２の高誘電率絶縁膜１５ｙを有する第２のゲート絶縁膜形成膜１５Ｙを形成する。第２の高誘電率絶縁膜１５ｙは、例えばＬａを含むＨｆＳｉＯ膜からなる。 At the same time, the adjustment metal (for example, La) in the second adjustment metal film 18b is applied to the second region in the gate insulating film formation film (in particular, on the second active region 10b in the high dielectric constant insulating film 15). The second gate insulating film forming film 15Y having the second interface layer 14B and the second high dielectric constant insulating film 15y containing the adjusting metal is formed. The second high dielectric constant insulating film 15y is made of, for example, an HfSiO film containing La.
　第１の調整用金属膜１８ａの第１の膜厚（例えば０．２ｎｍ～０．８ｎｍ）を、第２の調整用金属膜１８ｂの第２の膜厚（例えば０．５ｎｍ～１．５ｎｍ）よりも薄くするため、第１の高誘電率絶縁膜１５ｘ中における調整用金属の平均調整用金属濃度を、第２の高誘電率絶縁膜１５ｙ中における調整用金属の平均調整用金属濃度よりも低くすることができる。第１の高誘電率絶縁膜１５ｘ中におけるＬａの平均Ｌａ濃度は、例えば２０％以下である。第２の高誘電率絶縁膜１５ｙ中におけるＬａの平均Ｌａ濃度は、例えば２５％である。 The first film thickness (for example, 0.2 nm to 0.8 nm) of the first adjustment metal film 18a is set to the second film thickness (for example, 0.5 nm to 1.5 nm) of the second adjustment metal film 18b. The average adjustment metal concentration of the adjustment metal in the first high dielectric constant insulating film 15x is set to be smaller than the average adjustment metal concentration of the adjustment metal in the second high dielectric constant insulating film 15y. Can be lowered. The average La concentration of La in the first high dielectric constant insulating film 15x is, for example, 20% or less. The average La concentration of La in the second high dielectric constant insulating film 15y is, for example, 25%.
　次に、図４(a) に示すように、例えばウェットエッチングにより、第１，第２の調整用金属膜１８ａ，１８ｂにおける未反応の部分、保護膜１７及び調整用金属膜１６における未反応の部分を順次除去する。その後、例えばＡＬＤ法により、第１，第３，第２のゲート絶縁膜形成膜１５Ｘ，１５Ｚ，１５Ｙ上に、例えば膜厚が１０ｎｍ～２０ｎｍのＴｉＮ膜からなる金属膜１９を形成する。その後、例えばＣＶＤ法により、金属膜１９上に、例えば膜厚が７０ｎｍ～１００ｎｍのポリシリコン膜からなるシリコン膜２０を形成する。 Next, as shown in FIG. 4A, the unreacted portions of the first and second adjustment metal films 18a and 18b, the unreacted portions of the protective film 17 and the adjustment metal film 16, for example, by wet etching. Remove parts sequentially. Thereafter, a metal film 19 made of, for example, a TiN film having a thickness of 10 nm to 20 nm is formed on the first, third, and second gate insulating film forming films 15X, 15Z, and 15Y by, for example, ALD. Thereafter, a silicon film 20 made of a polysilicon film having a film thickness of, for example, 70 nm to 100 nm is formed on the metal film 19 by, eg, CVD.
　このようにして、第１，第３，第２のゲート絶縁膜形成膜１５Ｘ，１５Ｚ，１５Ｙ上に、金属膜１９及びシリコン膜２０を有するゲート電極形成膜を形成する。 In this manner, a gate electrode forming film having the metal film 19 and the silicon film 20 is formed on the first, third, and second gate insulating film forming films 15X, 15Z, and 15Y.
　次に、図４(b) に示すように、リソグラフィにより、シリコン膜２０上に、レジスト（図示省略）を形成する。その後、エッチングにより、レジストをマスクとして、ゲート電極形成膜及び第１，第３，第２のゲート絶縁膜形成膜１５Ｘ，１５Ｚ，１５Ｙを順次パターニングする。 Next, as shown in FIG. 4B, a resist (not shown) is formed on the silicon film 20 by lithography. Thereafter, the gate electrode forming film and the first, third, and second gate insulating film forming films 15X, 15Z, and 15Y are sequentially patterned by etching using the resist as a mask.
　これにより、第１の活性領域１０ａ上に、第１の界面層１４ａ及び調整用金属を含む第１の高誘電率絶縁膜１５ａを有する第１のゲート絶縁膜１５Ａ、並びに第１の金属膜１９ａ及び第１のシリコン膜２０ａを有する第１のゲート電極２０Ａを順次形成する。 As a result, the first gate insulating film 15A having the first interface layer 14a and the first high dielectric constant insulating film 15a containing the adjustment metal on the first active region 10a, and the first metal film 19a. Then, the first gate electrode 20A having the first silicon film 20a is sequentially formed.
　それと共に、第３の活性領域１０ｃ上に、第３の界面層１４ｃ及び調整用金属を含む第３の高誘電率絶縁膜１５ｃを有する第３のゲート絶縁膜１５Ｃ、並びに第３の金属膜１９ｃ及び第３のシリコン膜２０ｃを有する第３のゲート電極２０Ｃを順次形成する。 At the same time, the third gate insulating film 15C having the third interface layer 14c and the third high dielectric constant insulating film 15c containing the adjusting metal on the third active region 10c, and the third metal film 19c. Then, the third gate electrode 20C having the third silicon film 20c is sequentially formed.
　それと共に、第４の活性領域１０ｄ上に、第４の界面層１４ｄ及び調整用金属を含む第４の高誘電率絶縁膜１５ｄを有する第４のゲート絶縁膜１５Ｄ、並びに第４の金属膜１９ｄ及び第４のシリコン膜２０ｄを有する第４のゲート電極２０Ｄを順次形成する。 At the same time, the fourth gate insulating film 15D having the fourth interface layer 14d and the fourth high dielectric constant insulating film 15d including the adjusting metal on the fourth active region 10d, and the fourth metal film 19d. Then, a fourth gate electrode 20D having the fourth silicon film 20d is sequentially formed.
　それと共に、第２の活性領域１０ｂ上に、第２の界面層１４ｂ及び調整用金属を含む第２の高誘電率絶縁膜１５ｂを有する第２のゲート絶縁膜１５Ｂ、並びに第２の金属膜１９ｂ及び第２のシリコン膜２０ｂを有する第２のゲート電極２０Ｂを順次形成する。 At the same time, the second gate insulating film 15B having the second interface layer 14b and the second high dielectric constant insulating film 15b containing the adjusting metal on the second active region 10b, and the second metal film 19b. Then, the second gate electrode 20B having the second silicon film 20b is sequentially formed.
　第１のゲート電極２０Ａと第３のゲート電極２０Ｃとは、一体に形成されている。第４のゲート電極２０Ｄと第２のゲート電極２０Ｂとは、一体に形成されている。 The first gate electrode 20A and the third gate electrode 20C are integrally formed. The fourth gate electrode 20D and the second gate electrode 20B are integrally formed.
　第１の高誘電率絶縁膜１５ａ中における調整用金属（例えばＬａ）の平均調整用金属濃度は、第２の高誘電率絶縁膜１５ｂ中における調整用金属（例えばＬａ）の平均調整用金属濃度よりも低い。一方、第３の高誘電率絶縁膜１５ｃ中における調整用金属（例えばＡｌ）の平均調整用金属濃度と、第４の高誘電率絶縁膜１５ｄ中における調整用金属（例えばＡｌ）の平均調整用金属濃度とは、同じである。 The average adjustment metal concentration of the adjustment metal (for example, La) in the first high dielectric constant insulating film 15a is the average adjustment metal concentration of the adjustment metal (for example, La) in the second high dielectric constant insulating film 15b. Lower than. On the other hand, for the average adjustment metal concentration of the adjustment metal (for example, Al) in the third high dielectric constant insulating film 15c, and for the average adjustment of the adjustment metal (for example, Al) in the fourth high dielectric constant insulating film 15d. The metal concentration is the same.
　次に、図４(c) に示すように、第１，第３，第４，第２のゲート電極２０Ａ，２０Ｃ，２０Ｄ，２０Ｂの側面上に、断面形状がＩ字状の第１，第３，第４，第２のオフセットスペーサ３１ａ，３１ｃ，３１ｄ，３１ｂを形成する。第１のオフセットスペーサ３１ａと第３のオフセットスペーサ３１ｃとは、一体に形成されている。第４のオフセットスペーサ３１ｄと第２のオフセットスペーサ３１ｂとは、一体に形成されている。 Next, as shown in FIG. 4C, on the side surfaces of the first, third, fourth and second gate electrodes 20A, 20C, 20D and 20B, the first and first cross sections are I-shaped. Third, fourth and second offset spacers 31a, 31c, 31d and 31b are formed. The first offset spacer 31a and the third offset spacer 31c are integrally formed. The fourth offset spacer 31d and the second offset spacer 31b are integrally formed.
　その後、図４(c) に示す図は、ゲート幅方向の断面図であり、ゲート長方向の断面図ではないため、図４(c) には図示されないが、第１，第２の活性領域１０ａ，１０ｂにおける第１，第２のゲート電極２０Ａ，２０Ｂの側方下に、第１，第２のｎ型エクステンション注入領域を形成する。一方、第３，第４の活性領域１０ｃ，１０ｄにおける第３，第４のゲート電極２０Ｃ，２０Ｄの側方下に、第１，第２のｐ型エクステンション注入領域を形成する。 4C is a cross-sectional view in the gate width direction and is not a cross-sectional view in the gate length direction. Therefore, the first and second active regions are not shown in FIG. 4C. First and second n-type extension implantation regions are formed under the sides of the first and second gate electrodes 20A and 20B in 10a and 10b. On the other hand, first and second p-type extension implantation regions are formed in the third and fourth active regions 10c and 10d below the third and fourth gate electrodes 20C and 20D.
　その後、図４(c) に示すように、第１，第３，第４，第２のゲート電極２０Ａ，２０Ｃ，２０Ｄ，２０Ｂの側面上に、第１，第３，第４，第２のオフセットスペーサ３１ａ，３１ｃ，３１ｄ，３１ｂを介して、第１，第３，第４，第２のサイドウォール３３ａ，３３ｃ，３３ｄ，３３ｂを形成する。第１のサイドウォール３３ａと第３のサイドウォール３３ｃとは、一体に形成されている。第４のサイドウォール３３ｄと第２のサイドウォール３３ｂとは、一体に形成されている。 Thereafter, as shown in FIG. 4C, the first, third, fourth, and second gate electrodes 20A, 20C, 20D, and 20B are formed on the side surfaces of the first, third, fourth, and second gate electrodes 20A, 20C, 20D, and 20B. First, third, fourth and second sidewalls 33a, 33c, 33d and 33b are formed via offset spacers 31a, 31c, 31d and 31b. The first sidewall 33a and the third sidewall 33c are integrally formed. The fourth sidewall 33d and the second sidewall 33b are integrally formed.
　その後、図４(c) には図示されないが、第１，第２の活性領域１０ａ，１０ｂにおける第１，第２のサイドウォール３３ａ，３３ｂの外側方下に、第１，第２のｎ型ソースドレイン注入領域を形成する。一方、第３，第４の活性領域１０ｃ，１０ｄにおける第３，第４のサイドウォール３３ｃ，３３ｄの外側方下に、第１，第２のｐ型ソースドレイン注入領域を形成する。 Thereafter, although not shown in FIG. 4 (c), the first and second n-types are formed outside the first and second sidewalls 33a and 33b in the first and second active regions 10a and 10b. A source / drain implantation region is formed. On the other hand, first and second p-type source / drain implantation regions are formed on the outer sides of the third and fourth sidewalls 33c and 33d in the third and fourth active regions 10c and 10d.
　その後、例えば１０００℃，１秒の熱処理を行う。 Then, for example, heat treatment is performed at 1000 ° C. for 1 second.
　これにより、第１，第２のｎ型エクステンション注入領域中に含まれるｎ型不純物を活性化して、第１，第２のｎ型エクステンション領域（図１(c)：２２ａ，２２ｂ参照）を形成する。一方、第１，第２のｐ型エクステンション注入領域中に含まれるｐ型不純物を活性化して、第１，第２のｐ型エクステンション領域を形成する。 As a result, the n-type impurities contained in the first and second n-type extension implantation regions are activated to form the first and second n-type extension regions (see FIG. 1C: 22a and 22b). To do. On the other hand, p-type impurities contained in the first and second p-type extension implantation regions are activated to form first and second p-type extension regions.
　それと共に、第１，第２のｎ型ソースドレイン注入領域中に含まれるｎ型不純物を活性化して、第１，第２のｎ型ソースドレイン領域（図１(c)：２４ａ，２４ｂ参照）を形成する。一方、第１，第２のｐ型ソースドレイン注入領域中に含まれるｐ型不純物を活性化して、第１，第２のｐ型ソースドレイン領域を形成する。 At the same time, the n-type impurity contained in the first and second n-type source / drain implantation regions is activated, and the first and second n-type source / drain regions (see FIG. 1 (c): 24a and 24b). Form. On the other hand, the p-type impurities contained in the first and second p-type source / drain implantation regions are activated to form first and second p-type source / drain regions.
　以上のようにして、本実施形態に係る半導体装置を製造することができる。 As described above, the semiconductor device according to this embodiment can be manufactured.
　本実施形態では、形成直後の第１のチャネル領域１３Ａ（図２(a) 参照）中におけるｐ型不純物の平均不純物濃度と、形成直後の第２のチャネル領域１３Ｂ（図２(a) 参照）中におけるｐ型不純物の平均不純物濃度とは、同じである。しかしながら、第１，第２のチャネル領域１３Ａ，１３Ｂの形成後に施される熱処理（例えば、第１，第２のｎ型ソースドレイン注入領域中に含まれるｎ型不純物、及び第１，第２のｐ型ソースドレイン注入領域中に含まれるｐ型不純物を活性化させる為の熱処理等）により、第１，第２のチャネル領域１３Ａ，１３Ｂ中に含まれるｐ型不純物が、素子分離領域１１中に拡散する。このため、製造後の第１のチャネル領域１３ａ（図４(c) 参照）中におけるｐ型不純物の平均不純物濃度は、製造後の第２のチャネル領域１３ｂ（図４(c) 参照）中におけるｐ型不純物の平均不純物濃度よりも低くなる。 In the present embodiment, the average impurity concentration of the p-type impurity in the first channel region 13A immediately after formation (see FIG. 2A) and the second channel region 13B immediately after formation (see FIG. 2A) The average impurity concentration of the p-type impurities therein is the same. However, the heat treatment performed after the formation of the first and second channel regions 13A and 13B (for example, the n-type impurities contained in the first and second n-type source / drain implantation regions, and the first and second channel regions) The p-type impurities contained in the first and second channel regions 13A and 13B are caused to enter the element isolation region 11 by heat treatment for activating the p-type impurities contained in the p-type source / drain implantation region. Spread. For this reason, the average impurity concentration of the p-type impurity in the first channel region 13a after manufacture (see FIG. 4C) is the same as that in the second channel region 13b after manufacture (see FIG. 4C). It becomes lower than the average impurity concentration of the p-type impurity.
　同様に、形成直後の第３のチャネル領域１３Ｃ（図２(a) 参照）中におけるｎ型不純物の平均不純物濃度と、形成直後の第４のチャネル領域１３Ｄ（図２(a) 参照）中におけるｎ型不純物の平均不純物濃度とは、同じである。しかしながら、第３，第４のチャネル領域１３Ｃ，１３Ｄの形成後に施される熱処理（例えば、第１，第２のｎ型ソースドレイン注入領域中に含まれるｎ型不純物、及び第１，第２のｐ型ソースドレイン注入領域中に含まれるｐ型不純物を活性化させる為の熱処理等）により、第３，第４のチャネル領域１３Ｃ，１３Ｄ中に含まれるｎ型不純物が、素子分離領域１１中に拡散する。このため、製造後の第３のチャネル領域１３ｃ（図４(c) 参照）中におけるｎ型不純物の平均不純物濃度は、製造後の第４のチャネル領域１３ｄ（図４(c) 参照）中におけるｎ型不純物の平均不純物濃度よりも低くなる。 Similarly, the average impurity concentration of the n-type impurity in the third channel region 13C (see FIG. 2A) immediately after the formation and the fourth channel region 13D (see FIG. 2A) immediately after the formation. The average impurity concentration of the n-type impurity is the same. However, the heat treatment performed after the formation of the third and fourth channel regions 13C and 13D (for example, the n-type impurities contained in the first and second n-type source / drain implantation regions, and the first and second The n-type impurities contained in the third and fourth channel regions 13C and 13D are caused to enter the element isolation region 11 by heat treatment for activating the p-type impurities contained in the p-type source / drain implantation region. Spread. Therefore, the average impurity concentration of the n-type impurity in the third channel region 13c after manufacture (see FIG. 4C) is the same as that in the fourth channel region 13d after manufacture (see FIG. 4C). It becomes lower than the average impurity concentration of n-type impurities.
　第１のＭＩＳトランジスタＴｒ１は、第１の実施形態における第１のＭＩＳトランジスタＴｒ１と同様の構成要素を備えている。但し、本実施形態では、第１のゲート電極２０Ａが、図４(c) に示すように、第３のゲート電極２０Ｃと一体に形成されているため、第１のゲート電極２０Ａの側面のうち、第３のゲート電極２０Ｃと隣接する側面以外の側面上に、第１のオフセットスペーサ３１ａを介して、第１のサイドウォール３３ａが形成されている。 The first MIS transistor Tr1 includes the same components as the first MIS transistor Tr1 in the first embodiment. However, in the present embodiment, the first gate electrode 20A is formed integrally with the third gate electrode 20C as shown in FIG. 4C, so that the first gate electrode 20A is formed on the side surface of the first gate electrode 20A. The first sidewall 33a is formed on the side surface other than the side surface adjacent to the third gate electrode 20C via the first offset spacer 31a.
　第２のＭＩＳトランジスタＴｒ２は、第１の実施形態における第２のＭＩＳトランジスタＴｒ２と同様の構成要素を備えている。但し、本実施形態では、第２のゲート電極２０Ｂが、図４(c) に示すように、第４のゲート電極２０Ｄと一体に形成されているため、第２のゲート電極２０Ｂの側面のうち、第４のゲート電極２０Ｄと隣接する側面以外の側面上に、第２のオフセットスペーサ３１ｂを介して、第２のサイドウォール３３ｂが形成されている。 The second MIS transistor Tr2 includes the same components as the second MIS transistor Tr2 in the first embodiment. However, in the present embodiment, the second gate electrode 20B is formed integrally with the fourth gate electrode 20D as shown in FIG. 4C, so that the second gate electrode 20B is formed on the side surface of the second gate electrode 20B. The second sidewall 33b is formed on the side surface other than the side surface adjacent to the fourth gate electrode 20D via the second offset spacer 31b.
　第３，第４のＭＩＳトランジスタＴｒ３，Ｔｒ４は、図４(c) に示すように、第３，第４の活性領域１０ｃ，１０ｄ上に形成された第３，第４のゲート絶縁膜１５Ｃ，１５Ｄと、第３，第４のゲート絶縁膜１５Ｃ，１５Ｄ上に形成された第３，第４のゲート電極２０Ｃ，２０Ｄと、第３，第４の活性領域１０ｃ，１０ｄにおける第３，第４のゲート電極２０Ｃ，２０Ｄの直下に形成されたｎ型の第３，第４のチャネル領域１３ｃ，１３ｄと、第３，第４のゲート電極２０Ｃ，２０Ｄの側面上に形成された第３，第４のオフセットスペーサ３１ｃ，３１ｄと、第３，第４の活性領域１０ｃ，１０ｄにおける第３，第４のゲート電極２０Ｃ，２０Ｄの側方下に形成された第１，第２のｐ型エクステンション領域と、第３，第４のゲート電極２０Ｃ，２０Ｄの側面上に第３，第４のオフセットスペーサ３１ｃ，３１ｄを介して形成された第３，第４のサイドウォール３３ｃ，３３ｄと、第３，第４の活性領域１０ｃ，１０ｄにおける第３，第４のサイドウォール３３ｃ，３３ｄの外側方下に形成された第１，第２のｐ型ソースドレイン領域とを備えている。 As shown in FIG. 4C, the third and fourth MIS transistors Tr3 and Tr4 have third and fourth gate insulating films 15C, 15C formed on the third and fourth active regions 10c and 10d, respectively. 15D, the third and fourth gate electrodes 20C and 20D formed on the third and fourth gate insulating films 15C and 15D, and the third and fourth gates in the third and fourth active regions 10c and 10d. N-type third and fourth channel regions 13c and 13d formed immediately below the gate electrodes 20C and 20D, and third and third channels formed on the side surfaces of the third and fourth gate electrodes 20C and 20D. Four offset spacers 31c and 31d, and first and second p-type extension regions formed laterally below the third and fourth gate electrodes 20C and 20D in the third and fourth active regions 10c and 10d. And the third and fourth gate electrodes 20 , 20D through third and fourth offset spacers 31c, 31d on the side surface, and third third and fourth active regions 10c, 10d in the third active region 10c, 10d. , First and second p-type source / drain regions formed outside the fourth sidewalls 33c and 33d.
　第３，第４のゲート絶縁膜１５Ｃ，１５Ｄは、第３，第４の界面層１４ｃ，１４ｄと、第３，第４の高誘電率絶縁膜１５ｃ，１５ｄとを有する。第３，第４のゲート電極２０Ｃ，２０Ｄは、第３，第４の金属膜１９ｃ，１９ｄと、第３，第４のシリコン膜２０ｃ，２０ｄとを有する。 The third and fourth gate insulating films 15C and 15D have third and fourth interface layers 14c and 14d and third and fourth high dielectric constant insulating films 15c and 15d. The third and fourth gate electrodes 20C and 20D have third and fourth metal films 19c and 19d and third and fourth silicon films 20c and 20d.
　第１のゲート絶縁膜１５Ａ中における調整用金属（例えばＬａ）の平均調整用金属濃度は、第２のゲート絶縁膜１５Ｂ中における調整用金属（例えばＬａ）の平均調整用金属濃度よりも低い。一方、第３のゲート絶縁膜１５Ｃ中における調整用金属（例えばＡｌ）の平均調整用金属濃度と、第４のゲート絶縁膜１５Ｄ中における調整用金属（例えばＡｌ）の平均調整用金属濃度とは、同じである。 The average adjustment metal concentration of the adjustment metal (for example, La) in the first gate insulating film 15A is lower than the average adjustment metal concentration of the adjustment metal (for example, La) in the second gate insulating film 15B. On the other hand, the average adjustment metal concentration of the adjustment metal (for example, Al) in the third gate insulating film 15C and the average adjustment metal concentration of the adjustment metal (for example, Al) in the fourth gate insulating film 15D are as follows. The same.
　第１の高誘電率絶縁膜１５ａ中における調整用金属（例えばＬａ）の平均調整用金属濃度は、第２の高誘電率絶縁膜１５ｂ中における調整用金属（例えばＬａ）の平均調整用金属濃度よりも低い。一方、第３の高誘電率絶縁膜１５ｃ中における調整用金属（例えばＡｌ）の平均調整用金属濃度と、第４の高誘電率絶縁膜１５ｄ中における調整用金属（例えばＡｌ）の平均調整用金属濃度とは、同じである。 The average adjustment metal concentration of the adjustment metal (for example, La) in the first high dielectric constant insulating film 15a is the average adjustment metal concentration of the adjustment metal (for example, La) in the second high dielectric constant insulating film 15b. Lower than. On the other hand, for the average adjustment metal concentration of the adjustment metal (for example, Al) in the third high dielectric constant insulating film 15c and for the average adjustment of the adjustment metal (for example, Al) in the fourth high dielectric constant insulating film 15d. The metal concentration is the same.
　第１のチャネル領域１３ａ中におけるｐ型不純物の平均不純物濃度は、第２のチャネル領域１３ｂ中におけるｐ型不純物の平均不純物濃度よりも低い。同様に、第３のチャネル領域１３ｃ中におけるｎ型不純物の平均不純物濃度は、第４のチャネル領域１３ｄ中におけるｎ型不純物の平均不純物濃度よりも低い。 The average impurity concentration of the p-type impurity in the first channel region 13a is lower than the average impurity concentration of the p-type impurity in the second channel region 13b. Similarly, the average impurity concentration of n-type impurities in the third channel region 13c is lower than the average impurity concentration of n-type impurities in the fourth channel region 13d.
　本実施形態によると、第１の実施形態と同様の効果を得ることができる。 According to this embodiment, the same effect as that of the first embodiment can be obtained.
　本実施形態では、第１，第３，第４，第２のＭＩＳトランジスタを備えた半導体装置の製造方法について説明したが、本実施形態と同様の製造方法により、第１の実施形態に係る半導体装置（即ち、第１，第２のＭＩＳトランジスタを備えた半導体装置）を製造することができる。具体的には、図２(a) における第１，第２のｎＭＩＳ領域に示す工程と同様の工程を行った後、図３(a) ～図４(c) における第１，第２のｎＭＩＳ領域に示す工程と同様の工程を順次行うことにより、第１の実施形態に係る半導体装置を製造することができる。 In the present embodiment, the manufacturing method of the semiconductor device including the first, third, fourth, and second MIS transistors has been described. However, the semiconductor according to the first embodiment is manufactured by the same manufacturing method as the present embodiment. A device (that is, a semiconductor device including first and second MIS transistors) can be manufactured. Specifically, after performing the same process as that shown in the first and second nMIS regions in FIG. 2 (a), the first and second nMISs in FIGS. 3 (a) to 4 (c) are used. The semiconductor device according to the first embodiment can be manufactured by sequentially performing the same processes as those shown in the region.
　＜第２の実施形態の変形例＞
　以下に、本発明の第２の実施形態の変形例に係る半導体装置の製造方法について、図５(a) ～(c) を参照しながら説明する。図５(a) ～(c) は、本発明の第２の実施形態の変形例に係る半導体装置の製造方法を工程順に示すゲート幅方向の断面図である。図５(a) ～(c) において、第２の実施形態における構成要素と同一の構成要素には、図２(a) ～図４(c) に示す符号と同一の符号を付す。従って、本変形例では、第２の実施形態と同様の説明を適宜省略する。 <Modification of Second Embodiment>
A method for manufacturing a semiconductor device according to a modification of the second embodiment of the present invention will be described below with reference to FIGS. 5 (a) to 5 (c). 5A to 5C are cross-sectional views in the gate width direction showing the method of manufacturing the semiconductor device according to the modification of the second embodiment of the present invention in the order of steps. 5 (a) to 5 (c), the same reference numerals as those shown in FIGS. 2 (a) to 4 (c) are assigned to the same constituent elements as those in the second embodiment. Therefore, in this modification, the description similar to that of the second embodiment is omitted as appropriate.
　まず、第２の実施形態における図２(a) ～(c) に示す工程と同様の工程を順次行う。 First, steps similar to those shown in FIGS. 2A to 2C in the second embodiment are sequentially performed.
　次に、図３(a) に示す工程と同様の工程を行う。具体的には、例えばスパッタ法により、半導体基板１０上の全面に、例えば膜厚が０．５ｎｍ～１．５ｎｍのＬａを含む調整用金属膜１８を形成する。 Next, the same process as that shown in FIG. Specifically, the adjustment metal film 18 containing La having a thickness of 0.5 nm to 1.5 nm, for example, is formed on the entire surface of the semiconductor substrate 10 by, for example, sputtering.
　次に、図５(a) に示すように、例えば６５０℃，１２０秒の熱処理（第１の熱処理）を行う。 Next, as shown in FIG. 5A, for example, a heat treatment (first heat treatment) is performed at 650 ° C. for 120 seconds.
　これにより、調整用金属膜１８中の調整用金属（例えばＬａ）を、ゲート絶縁膜形成膜における第１の領域（特に、高誘電率絶縁膜１５における第１の活性領域１０ａ上に位置する領域）に導入して、第１の界面層１４Ａ及び調整用金属を含む第１の高誘電率絶縁膜１５ｘを有する第１のゲート絶縁膜形成膜１５Ｘを形成する。 Thus, the adjustment metal (for example, La) in the adjustment metal film 18 is removed from the first region in the gate insulating film formation film (particularly, the region located on the first active region 10a in the high dielectric constant insulating film 15). The first gate insulating film forming film 15X having the first interface layer 14A and the first high dielectric constant insulating film 15x containing the adjusting metal is formed.
　それと共に、調整用金属膜１６中の調整用金属（例えばＡｌ）を、ゲート絶縁膜形成膜における第３，第４の領域（特に、高誘電率絶縁膜１５における第３，第４の活性領域１０ｃ，１０ｄ上に位置する領域）に導入して、調整用金属を含む高誘電率絶縁膜１５ｗを形成する。 At the same time, the adjustment metal (for example, Al) in the adjustment metal film 16 is applied to the third and fourth regions in the gate insulating film formation film (in particular, the third and fourth active regions in the high dielectric constant insulating film 15). 10c and 10d), a high dielectric constant insulating film 15w containing an adjustment metal is formed.
　それと共に、調整用金属膜１８中の調整用金属（例えばＬａ）を、ゲート絶縁膜形成膜における第２の領域（特に、高誘電率絶縁膜１５における第２の活性領域１０ｂ上に位置する領域）に導入して、調整用金属を含む高誘電率絶縁膜１５ｖを形成する。 At the same time, the adjustment metal (for example, La) in the adjustment metal film 18 is applied to the second region in the gate insulating film formation film (in particular, the region located on the second active region 10b in the high dielectric constant insulating film 15). ) To form a high dielectric constant insulating film 15v containing an adjustment metal.
　次に、図５(b) に示すように、リソグラフィにより、調整用金属膜１８上に、第１のｎＭＩＳ領域を開口し且つ第１，第２のｐＭＩＳ領域及び第２のｎＭＩＳ領域を覆うレジストＲｅ３を形成する。その後、例えばウェットエッチングにより、レジストＲｅ３をマスクとして、調整用金属膜１８における第１のゲート絶縁膜形成膜１５Ｘ上に位置する部分を除去する。 Next, as shown in FIG. 5B, a resist that opens the first nMIS region and covers the first and second pMIS regions and the second nMIS region on the adjustment metal film 18 by lithography. Re3 is formed. Thereafter, the portion of the adjustment metal film 18 located on the first gate insulating film forming film 15X is removed by wet etching, for example, using the resist Re3 as a mask.
　その後、レジストＲｅ３を除去する。 Thereafter, the resist Re3 is removed.
　次に、図５(c) に示すように、例えば９００℃，３０秒の熱処理（第２の熱処理）を行う。 Next, as shown in FIG. 5C, for example, heat treatment (second heat treatment) is performed at 900 ° C. for 30 seconds.
　これにより、調整用金属膜１６中の調整用金属（例えばＡｌ）を、ゲート絶縁膜形成膜における第３，第４の領域（特に、調整用金属を含む高誘電率絶縁膜１５ｗ）に追加導入して、第３，第４の界面層１４Ｃ，１４Ｄ及び調整用金属を含む第３の高誘電率絶縁膜１５ｚを有する第３のゲート絶縁膜形成膜１５Ｚを形成する。 Thereby, the adjustment metal (for example, Al) in the adjustment metal film 16 is additionally introduced into the third and fourth regions (particularly, the high dielectric constant insulating film 15w including the adjustment metal) in the gate insulating film formation film. Then, the third gate insulating film forming film 15Z having the third high dielectric constant insulating film 15z including the third and fourth interface layers 14C and 14D and the adjusting metal is formed.
　それと共に、調整用金属膜１８中の調整用金属（例えばＬａ）を、ゲート絶縁膜形成膜における第２の領域（特に、調整用金属を含む高誘電率絶縁膜１５ｖ）に追加導入して、第２の界面層１４Ｂ及び調整用金属を含む第２の高誘電率絶縁膜１５ｙを有する第２のゲート絶縁膜形成膜１５Ｙを形成する。 At the same time, the adjustment metal (for example, La) in the adjustment metal film 18 is additionally introduced into the second region (particularly, the high dielectric constant insulating film 15v including the adjustment metal) in the gate insulating film formation film, A second gate insulating film forming film 15Y having the second interface layer 14B and the second high dielectric constant insulating film 15y containing the adjusting metal is formed.
　次に、第２の実施形態における図４(a) ～(c) に示す工程と同様の工程を順次行う。 Next, steps similar to those shown in FIGS. 4A to 4C in the second embodiment are sequentially performed.
　以上のようにして、本変形例に係る半導体装置を製造することができる。 As described above, the semiconductor device according to this modification can be manufactured.
　本変形例では、図５(a) に示すように、第１の熱処理により、調整用金属膜１８中の調整用金属を、ゲート絶縁膜形成膜における第１，第２の領域（特に、高誘電率絶縁膜１５における第１，第２の活性領域１０ａ，１０ｂ上に位置する領域）に導入した後、図５(c) に示すように、第２の熱処理により、調整用金属膜１８中の調整用金属を、ゲート絶縁膜形成膜における第２の領域（特に、高誘電率絶縁膜１５における第２の活性領域１０ｂ上に位置する領域）にのみ追加導入する。このため、第１の高誘電率絶縁膜１５ｘ中における調整用金属の平均調整用金属濃度を、第２の高誘電率絶縁膜１５ｙ中における調整用金属の平均調整用金属濃度よりも低くすることができ、第１のゲート絶縁膜形成膜１５Ｘ中における調整用金属の平均調整用金属濃度を、第２のゲート絶縁膜形成膜１５Ｙ中における調整用金属の平均調整用金属濃度よりも低くすることができる。 In this modified example, as shown in FIG. 5A, the adjustment metal in the adjustment metal film 18 is removed from the first and second regions (particularly, the high region) in the gate insulating film formation film by the first heat treatment. After introduction into the first and second active regions 10a and 10b in the dielectric constant insulating film 15), as shown in FIG. 5 (c), by the second heat treatment, The adjusting metal is additionally introduced only into the second region in the gate insulating film formation film (particularly, the region located on the second active region 10b in the high dielectric constant insulating film 15). Therefore, the average adjustment metal concentration of the adjustment metal in the first high dielectric constant insulating film 15x is made lower than the average adjustment metal concentration of the adjustment metal in the second high dielectric constant insulating film 15y. The average adjusting metal concentration of the adjusting metal in the first gate insulating film forming film 15X can be made lower than the average adjusting metal concentration of the adjusting metal in the second gate insulating film forming film 15Y. Can do.
　本変形例によると、第２の実施形態と同様の効果を得ることができる。 According to this modification, the same effect as that of the second embodiment can be obtained.
　なお、第２の実施形態では、第１のゲート絶縁膜形成膜１５Ｘ、及び調整用金属の平均調整用金属濃度が第１のゲート絶縁膜形成膜１５Ｘよりも高い第２のゲート絶縁膜形成膜１５Ｙを形成する方法として、図３(a) ～(b) に示すように、ゲート絶縁膜形成膜１５における第１の領域上に、第１の膜厚を有する第１の調整用金属膜１８ａを形成する一方、ゲート絶縁膜形成膜１５における第２の領域上に、第１の膜厚よりも厚い第２の膜厚を有する第２の調整用金属膜１８ｂを形成した後、図３(c) に示すように、例えば７００℃，１２０秒の熱処理を行う場合を具体例に挙げて説明したが、本発明はこれに限定されるものではない。 In the second embodiment, the first gate insulating film forming film 15X and the second gate insulating film forming film in which the average adjusting metal concentration of the adjusting metal is higher than that of the first gate insulating film forming film 15X. As a method of forming 15Y, as shown in FIGS. 3A to 3B, the first adjustment metal film 18a having the first film thickness is formed on the first region in the gate insulating film formation film 15. On the other hand, after the second adjustment metal film 18b having a second film thickness larger than the first film thickness is formed on the second region in the gate insulating film formation film 15, FIG. c) As shown in (2), for example, the case where heat treatment is performed at 700 ° C. for 120 seconds has been described as a specific example, but the present invention is not limited to this.
　第１に例えば、上述の第２の実施形態の変形例に記載の方法により、第１，第２のゲート絶縁膜形成膜を形成してもよい。 First, for example, the first and second gate insulating film formation films may be formed by the method described in the modification of the second embodiment.
　第２に例えば、以下に記載の方法により、第１，第２のゲート絶縁膜形成膜を形成してもよい。 Second, for example, the first and second gate insulating film forming films may be formed by the method described below.
　まず、第２の実施形態における図２(a) ～(b) に示す工程と同様の工程を順次行う。 First, steps similar to those shown in FIGS. 2A to 2B in the second embodiment are sequentially performed.
　次に、第１，第２のｎＭＩＳ領域を開口し、且つ、第１，第２のｐＭＩＳ領域を覆うレジスト（図２(c)：Ｒｅ１参照）ではなく、第１のｎＭＩＳ領域における中央領域、及び第２のｎＭＩＳ領域を開口し、且つ、第１のｎＭＩＳ領域における周辺領域（中央領域以外の領域）、第１，第２のｐＭＩＳ領域を覆うレジストを形成する。このように、第１の活性領域と対応する領域における全領域を露出するレジスト（図２(c)：Ｒｅ１参照）ではなく、第１の活性領域と対応する領域における中央領域のみを露出するレジストを形成する。 Next, not the resist (see FIG. 2C: Re1) that opens the first and second nMIS regions and covers the first and second pMIS regions, but the central region in the first nMIS region, Then, a resist that opens the second nMIS region and covers the peripheral region (region other than the central region) and the first and second pMIS regions in the first nMIS region is formed. Thus, not the resist that exposes the entire region in the region corresponding to the first active region (see FIG. 2C: Re1), but the resist that exposes only the central region in the region corresponding to the first active region. Form.
　その後、保護膜１７及び調整用金属膜１６における、レジストで覆われた部分以外の部分（即ち、第１のｎＭＩＳ領域における中央領域、及び第２のｎＭＩＳ領域に形成された部分）を除去する。その後、レジストを除去する。 Thereafter, portions of the protective film 17 and the adjustment metal film 16 other than the portion covered with the resist (that is, the central region in the first nMIS region and the portion formed in the second nMIS region) are removed. Thereafter, the resist is removed.
　次に、第２の実施形態における図３(a) に示す工程と同様の工程を行った後、図３(b) に示す工程（即ち、調整用金属膜１８における第１のｎ，ｐＭＩＳ領域に形成された部分を薄膜化する工程）と同様の工程を行わずに、第２の実施形態における図３(c) に示す工程（即ち、熱処理により調整用金属膜中の調整用金属を高誘電率絶縁膜に導入する工程）と同様の工程を行う。 Next, after performing a step similar to the step shown in FIG. 3A in the second embodiment, the step shown in FIG. 3B (that is, the first n, pMIS region in the adjustment metal film 18). The step shown in FIG. 3 (c) in the second embodiment (that is, the adjustment metal in the adjustment metal film is increased by heat treatment without performing the same step as the step of thinning the portion formed in FIG. 3). A step similar to that in the step of introducing the dielectric constant insulating film) is performed.
　このようにすると、調整用金属膜中の調整用金属（例えばＬａ）を高誘電率絶縁膜に導入する為の熱処理時に、高誘電率絶縁膜における第１の活性領域上に位置する領域は、その中央部分のみが、調整用金属膜と接する一方、高誘電率絶縁膜における第２の活性領域上に位置する領域は、その全部分が、調整用金属膜と接する。このため、第１の高誘電率絶縁膜中における調整用金属の平均調整用金属濃度を、第２の高誘電率絶縁膜中における調整用金属の平均調整用金属濃度よりも低くすることができ、第１のゲート絶縁膜形成膜中における調整用金属の平均調整用金属濃度を、第２のゲート絶縁膜形成膜中における調整用金属の平均調整用金属濃度よりも低くすることができる。 In this case, the region located on the first active region in the high dielectric constant insulating film during the heat treatment for introducing the adjustment metal (for example, La) in the adjustment metal film into the high dielectric constant insulating film, While only the central portion is in contact with the adjustment metal film, the entire region of the region located on the second active region in the high dielectric constant insulating film is in contact with the adjustment metal film. Therefore, the average adjustment metal concentration of the adjustment metal in the first high dielectric constant insulating film can be made lower than the average adjustment metal concentration of the adjustment metal in the second high dielectric constant insulating film. The average adjusting metal concentration of the adjusting metal in the first gate insulating film forming film can be made lower than the average adjusting metal concentration of the adjusting metal in the second gate insulating film forming film.
　なお、第２の実施形態及びその変形例では、第３のゲート絶縁膜１５Ｃ中における調整用金属（例えばＡｌ）の平均調整用金属濃度と、第４のゲート絶縁膜１５Ｄ中における調整用金属（例えばＡｌ）の平均調整用金属濃度とを同じにする場合を具体例に挙げて説明したが、本発明はこれに限定されるものではない。 In the second embodiment and the modification thereof, the average adjustment metal concentration of the adjustment metal (for example, Al) in the third gate insulating film 15C and the adjustment metal in the fourth gate insulating film 15D ( For example, the case where the average adjustment metal concentration of Al) is the same has been described as a specific example, but the present invention is not limited to this.
　既述の通り、第３，第４のチャネル領域１３Ｃ，１３Ｄの形成後に施される熱処理により、第３のチャネル領域１３ｃ中におけるｎ型不純物の平均不純物濃度は、第４のチャネル領域１３ｄ中におけるｎ型不純物の平均不純物濃度よりも低くなる。このため、第３のＭＩＳトランジスタＴｒ３の閾値電圧が、第４のＭＩＳトランジスタＴｒ４の閾値電圧よりも低くなる虞がある。 As described above, the average impurity concentration of the n-type impurity in the third channel region 13c is increased in the fourth channel region 13d by the heat treatment performed after the formation of the third and fourth channel regions 13C and 13D. It becomes lower than the average impurity concentration of n-type impurities. For this reason, the threshold voltage of the third MIS transistor Tr3 may be lower than the threshold voltage of the fourth MIS transistor Tr4.
　そこで、第３のゲート絶縁膜中における調整用金属の平均調整用金属濃度を、第４のゲート絶縁膜中における調整用金属の平均調整用金属濃度よりも低くする。これにより、第３，第４のチャネル領域中におけるｎ型不純物の平均不純物濃度の差異に起因して発生する第３，第４のＭＩＳトランジスタの閾値電圧の差異を補償することができる。このため、第３，第４のＭＩＳトランジスタの閾値電圧を、所望の閾値電圧に制御することができる。 Therefore, the average adjusting metal concentration of the adjusting metal in the third gate insulating film is made lower than the average adjusting metal concentration of the adjusting metal in the fourth gate insulating film. As a result, it is possible to compensate for the difference in the threshold voltages of the third and fourth MIS transistors caused by the difference in the average impurity concentration of the n-type impurities in the third and fourth channel regions. For this reason, the threshold voltage of the third and fourth MIS transistors can be controlled to a desired threshold voltage.
　なお、第１の実施形態並びに第２の実施形態及びその変形例では、第１，第２のゲート絶縁膜１５Ａ，１５Ｂに含まれる調整用金属として、Ｌａを用いる場合を具体例に挙げて説明したが、本発明はこれに限定されるものではなく、例えば、Ｌａの代わりに、他のランタノイド元素又はマグネシウム（Ｍｇ）等を用いてもよい。 In the first embodiment, the second embodiment, and modifications thereof, the case where La is used as the adjustment metal contained in the first and second gate insulating films 15A and 15B will be described as a specific example. However, the present invention is not limited to this. For example, other lanthanoid elements or magnesium (Mg) may be used instead of La.
　また、第２の実施形態及びその変形例では、第３，第４のゲート絶縁膜１５Ｃ，１５Ｄに含まれる調整用金属として、Ａｌを用いる場合を具体例に挙げて説明したが、本発明はこれに限定されるものではなく、例えば、Ａｌの代わりに、酸化タンタル（ＴａＯ）等を用いてもよい。 In the second embodiment and its modification, the case where Al is used as the adjustment metal contained in the third and fourth gate insulating films 15C and 15D has been described as a specific example. For example, tantalum oxide (TaO) may be used instead of Al.
　以上説明したように、本発明は、第１，第２のＭＩＳトランジスタの閾値電圧を、所望の閾値電圧に制御することができるので、ゲート幅が互いに異なる第１，第２のＭＩＳトランジスタを備えた半導体装置及びその製造方法に有用である。 As described above, the present invention can control the threshold voltage of the first and second MIS transistors to a desired threshold voltage, and thus includes the first and second MIS transistors having different gate widths. It is useful for a semiconductor device and a method for manufacturing the same.
１０　半導体基板
１０ａ　第１の活性領域
１０ｂ　第２の活性領域
１０ｃ　第３の活性領域
１０ｄ　第４の活性領域
１１　素子分離領域
１２ｘ　第１のｐ型ウェル領域
１２ｙ　第２のｐ型ウェル領域
１２ｚ　ｎ型ウェル領域
１３Ａ，１３ａ　第１のチャネル領域
１３Ｂ，１３ｂ　第２のチャネル領域
１３Ｃ，１３ｃ　第３のチャネル領域
１３Ｄ，１３ｄ　第４のチャネル領域
１４Ａ，１４ａ　第１の界面層
１４Ｂ，１４ｂ　第２の界面層
１４Ｃ，１４ｃ　第３の界面層
１４Ｄ，１４ｄ　第４の界面層
１５　高誘電率絶縁膜
１５ｖ　高誘電率絶縁膜
１５ｗ　高誘電率絶縁膜
１５ｘ　第１の高誘電率絶縁膜
１５ｙ　第２の高誘電率絶縁膜
１５ｚ　第３の高誘電率絶縁膜
１５Ｘ　第１のゲート絶縁膜形成膜
１５Ｙ　第２のゲート絶縁膜形成膜
１５Ｚ　第３のゲート絶縁膜形成膜
１５ａ　第１の高誘電率絶縁膜
１５ｂ　第２の高誘電率絶縁膜
１５ｃ　第３の高誘電率絶縁膜
１５ｄ　第４の高誘電率絶縁膜
１５Ａ　第１のゲート絶縁膜
１５Ｂ　第２のゲート絶縁膜
１５Ｃ　第３のゲート絶縁膜
１５Ｄ　第４のゲート絶縁膜
１６　調整用金属膜
１７　保護膜
１８　調整用金属膜
１８ａ　第１の調整用金属膜
１８ｂ　第２の調整用金属膜
１９　金属膜
２０　シリコン膜
１９ａ　第１の金属膜
１９ｂ　第２の金属膜
１９ｃ　第３の金属膜
１９ｄ　第４の金属膜
２０ａ　第１のシリコン膜
２０ｂ　第２のシリコン膜
２０ｃ　第３のシリコン膜
２０ｄ　第４のシリコン膜
２０Ａ　第１のゲート電極
２０Ｂ　第２のゲート電極
２０Ｃ　第３のゲート電極
２０Ｄ　第４のゲート電極
２１ａ，３１ａ　第１のオフセットスペーサ
２１ｂ，３１ｂ　第２のオフセットスペーサ
３１ｃ　第３のオフセットスペーサ
３１ｄ　第４のオフセットスペーサ
２２ａ　第１のｎ型エクステンション領域
２２ｂ　第２のｎ型エクステンション領域
２３ａ，３３ａ　第１のサイドウォール
２３ｂ，３３ｂ　第２のサイドウォール
３３ｃ　第３のサイドウォール
３３ｄ　第４のサイドウォール
２４ａ　第１のｎ型ソースドレイン領域
２４ｂ　第２のｎ型ソースドレイン領域
Ｒｅ１～Ｒｅ３　レジスト
Ｗ１　第１のゲート幅
Ｗ２　第２のゲート幅 10 semiconductor substrate 10a first active region 10b second active region 10c third active region 10d fourth active region 11 element isolation region 12x first p-type well region 12y second p-type well region 12z n-type Well regions 13A, 13a First channel regions 13B, 13b Second channel regions 13C, 13c Third channel regions 13D, 13d Fourth channel regions 14A, 14a First interface layers 14B, 14b Second interface layers 14C, 14c Third interface layer 14D, 14d Fourth interface layer 15 High dielectric constant insulating film 15v High dielectric constant insulating film 15w High dielectric constant insulating film 15x First high dielectric constant insulating film 15y Second high dielectric constant Insulating film 15z Third high dielectric constant insulating film 15X First gate insulating film forming film 15Y Second gate insulating film forming film 15Z Third gate insulating film forming film 15a First High dielectric constant insulating film 15b Second high dielectric constant insulating film 15c Third high dielectric constant insulating film 15d Fourth high dielectric constant insulating film 15A First gate insulating film 15B Second gate insulating film 15C Third Gate insulating film 15D fourth gate insulating film 16 adjustment metal film 17 protective film 18 adjustment metal film 18a first adjustment metal film 18b second adjustment metal film 19 metal film 20 silicon film 19a first Metal film 19b second metal film 19c third metal film 19d fourth metal film 20a first silicon film 20b second silicon film 20c third silicon film 20d fourth silicon film 20A first gate electrode 20B 2nd gate electrode 20C 3rd gate electrode 20D 4th gate electrode 21a, 31a 1st offset spacer 21b, 31b 2nd offset spacer 31c 3rd offset Spacer 31d fourth offset spacer 22a first n-type extension region 22b second n-type extension region 23a, 33a first sidewall 23b, 33b second sidewall 33c third sidewall 33d fourth side Wall 24a First n-type source / drain region 24b Second n-type source / drain region Re1 to Re3 Resist W1 First gate width W2 Second gate width

Claims (12)

  1. 　第１のＭＩＳトランジスタ及び第２のＭＩＳトランジスタを備えた半導体装置であって、
    　前記第１のＭＩＳトランジスタは、
    　半導体基板における第１の活性領域上に形成され、第１の高誘電率絶縁膜を有する第１のゲート絶縁膜と、
    　前記第１のゲート絶縁膜上に形成された第１のゲート電極とを備え、
    　前記第２のＭＩＳトランジスタは、
    　前記半導体基板における第２の活性領域上に形成され、第２の高誘電率絶縁膜を有する第２のゲート絶縁膜と、
    　前記第２のゲート絶縁膜上に形成された第２のゲート電極とを備え、
    　前記第１のゲート絶縁膜及び前記第２のゲート絶縁膜は、それぞれ調整用金属を含み、
    　前記第１のＭＩＳトランジスタの第１のゲート幅は、前記第２のＭＩＳトランジスタの第２のゲート幅よりも小さく、
    　前記第１のゲート絶縁膜中における前記調整用金属の平均調整用金属濃度は、前記第２のゲート絶縁膜中における前記調整用金属の平均調整用金属濃度に比べて低いことを特徴とする半導体装置。     A semiconductor device comprising a first MIS transistor and a second MIS transistor,
    The first MIS transistor is
    A first gate insulating film formed on a first active region in a semiconductor substrate and having a first high dielectric constant insulating film;
    A first gate electrode formed on the first gate insulating film,
    The second MIS transistor is
    A second gate insulating film formed on a second active region in the semiconductor substrate and having a second high dielectric constant insulating film;
    A second gate electrode formed on the second gate insulating film,
    Each of the first gate insulating film and the second gate insulating film includes an adjustment metal,
    A first gate width of the first MIS transistor is smaller than a second gate width of the second MIS transistor;
    An average adjusting metal concentration of the adjusting metal in the first gate insulating film is lower than an average adjusting metal concentration of the adjusting metal in the second gate insulating film. apparatus.
  2. 　請求項１に記載の半導体装置において、
    　前記第１の活性領域における前記第１のゲート電極の直下に形成された第１の不純物を含む第１のチャネル領域と、
    　前記第２の活性領域における前記第２のゲート電極の直下に形成された第２の不純物を含む第２のチャネル領域とを備え、
    　前記第１のチャネル領域中における前記第１の不純物の平均不純物濃度は、前記第２のチャネル領域中における前記第２の不純物の平均不純物濃度に比べて低いことを特徴とする半導体装置。     The semiconductor device according to claim 1,
    A first channel region containing a first impurity formed immediately below the first gate electrode in the first active region;
    A second channel region containing a second impurity formed immediately below the second gate electrode in the second active region,
    The semiconductor device, wherein an average impurity concentration of the first impurity in the first channel region is lower than an average impurity concentration of the second impurity in the second channel region.
  3. 　請求項２に記載の半導体装置において、
    　前記第１のゲート幅は、１００ｎｍ以下であり、
    　前記第２のゲート幅は、２００ｎｍ以上であることを特徴とする半導体装置。     The semiconductor device according to claim 2,
    The first gate width is 100 nm or less;
    The semiconductor device according to claim 1, wherein the second gate width is 200 nm or more.
  4. 　請求項３に記載の半導体装置において、
    　前記第１のＭＩＳトランジスタ及び前記第２のＭＩＳトランジスタは、ｎ型ＭＩＳトランジスタであり、
    　前記調整用金属は、ランタンであることを特徴とする半導体装置。     The semiconductor device according to claim 3.
    The first MIS transistor and the second MIS transistor are n-type MIS transistors,
    The semiconductor device according to claim 1, wherein the adjustment metal is lanthanum.
  5. 　請求項４に記載の半導体装置において、
    　前記第１の高誘電率絶縁膜中における前記調整用金属の平均調整用金属濃度は、前記第２の高誘電率絶縁膜中における前記調整用金属の平均調整用金属濃度に比べて低いことを特徴とする半導体装置。     The semiconductor device according to claim 4,
    The average adjustment metal concentration of the adjustment metal in the first high dielectric constant insulating film is lower than the average adjustment metal concentration of the adjustment metal in the second high dielectric constant insulating film. A featured semiconductor device.
  6. 　請求項５に記載の半導体装置において、
    　前記第１のゲート絶縁膜は、前記第１の活性領域上に形成された第１の界面層と、前記第１の界面層上に形成された前記第１の高誘電率絶縁膜とからなり、
    　前記第２のゲート絶縁膜は、前記第２の活性領域上に形成された第２の界面層と、前記第２の界面層上に形成された前記第２の高誘電率絶縁膜とからなることを特徴とする半導体装置。     The semiconductor device according to claim 5,
    The first gate insulating film includes a first interface layer formed on the first active region and the first high dielectric constant insulating film formed on the first interface layer. ,
    The second gate insulating film includes a second interface layer formed on the second active region and the second high dielectric constant insulating film formed on the second interface layer. A semiconductor device.
  7. 　請求項６に記載の半導体装置において、
    　前記第１の界面層及び前記第２の界面層は、シリコン酸化膜からなることを特徴とする半導体装置。     The semiconductor device according to claim 6.
    The semiconductor device according to claim 1, wherein the first interface layer and the second interface layer are made of a silicon oxide film.
  8. 　請求項７に記載の半導体装置において、
    　前記第１の高誘電率絶縁膜及び前記第２の高誘電率絶縁膜は、比誘電率が１０以上の金属酸化物からなることを特徴とする半導体装置。     The semiconductor device according to claim 7,
    The first high dielectric constant insulating film and the second high dielectric constant insulating film are made of a metal oxide having a relative dielectric constant of 10 or more.
  9. 　請求項８に記載の半導体装置において、
    　前記第１のゲート電極は、前記第１のゲート絶縁膜上に形成された第１の金属膜と、前記第１の金属膜上に形成された第１のシリコン膜とからなり、
    　前記第２のゲート電極は、前記第２のゲート絶縁膜上に形成された第２の金属膜と、前記第２の金属膜上に形成された第２のシリコン膜とからなることを特徴とする半導体装置。     The semiconductor device according to claim 8,
    The first gate electrode includes a first metal film formed on the first gate insulating film and a first silicon film formed on the first metal film,
    The second gate electrode includes a second metal film formed on the second gate insulating film and a second silicon film formed on the second metal film. Semiconductor device.
  10. 　半導体基板における第１の活性領域上に形成された第１のゲート絶縁膜及び第１のゲート電極を有する第１のＭＩＳトランジスタと、前記半導体基板における第２の活性領域上に形成された第２のゲート絶縁膜及び第２のゲート電極を有する第２のＭＩＳトランジスタとを備えた半導体装置の製造方法であって、
    　前記第１の活性領域及び前記第２の活性領域の上に、高誘電率絶縁膜を有するゲート絶縁膜形成膜を形成する工程（ａ）と、
    　前記ゲート絶縁膜形成膜における前記第１の活性領域上に位置する第１の領域に調整用金属を導入して第１のゲート絶縁膜形成膜を形成する一方、前記ゲート絶縁膜形成膜における前記第２の活性領域上に位置する第２の領域に前記調整用金属を導入して第２のゲート絶縁膜形成膜を形成する工程（ｂ）と、
    　前記第１のゲート絶縁膜形成膜及び前記第２のゲート絶縁膜形成膜の上に、ゲート電極形成膜を形成する工程（ｃ）と、
    　前記ゲート電極形成膜、前記第１のゲート絶縁膜形成膜及び前記第２のゲート絶縁膜形成膜をパターニングして、前記第１の活性領域上に前記第１のゲート絶縁膜形成膜からなる第１のゲート絶縁膜及び前記ゲート電極形成膜からなる第１のゲート電極を形成する一方、前記第２の活性領域上に前記第２のゲート絶縁膜形成膜からなる第２のゲート絶縁膜及び前記ゲート電極形成膜からなる第２のゲート電極を形成する工程（ｄ）とを備え、
    　前記第１のＭＩＳトランジスタの第１のゲート幅は、前記第２のＭＩＳトランジスタの第２のゲート幅よりも小さく、
    　前記工程（ｂ）では、前記第１のゲート絶縁膜形成膜中における前記調整用金属の平均調整用金属濃度が、前記第２のゲート絶縁膜形成膜中における前記調整用金属の平均調整用金属濃度に比べて低くなるように、前記第１のゲート絶縁膜形成膜及び前記第２のゲート絶縁膜形成膜を形成することを特徴とする半導体装置の製造方法。     A first MIS transistor having a first gate insulating film and a first gate electrode formed on the first active region in the semiconductor substrate, and a second MIS transistor formed on the second active region in the semiconductor substrate. A method of manufacturing a semiconductor device comprising: a second MIS transistor having a gate insulating film and a second gate electrode;
    Forming a gate insulating film forming film having a high dielectric constant insulating film on the first active region and the second active region;
    An adjustment metal is introduced into a first region located on the first active region in the gate insulating film forming film to form a first gate insulating film forming film, while the gate insulating film forming film includes the (B) forming the second gate insulating film forming film by introducing the adjustment metal into the second region located on the second active region;
    A step (c) of forming a gate electrode formation film on the first gate insulation film formation film and the second gate insulation film formation film;
    The gate electrode forming film, the first gate insulating film forming film, and the second gate insulating film forming film are patterned to form a first gate insulating film forming film on the first active region. Forming a first gate electrode comprising the first gate insulating film and the gate electrode forming film, while forming a second gate insulating film comprising the second gate insulating film forming film on the second active region; Forming a second gate electrode made of a gate electrode formation film (d),
    A first gate width of the first MIS transistor is smaller than a second gate width of the second MIS transistor;
    In the step (b), the average adjusting metal concentration of the adjusting metal in the first gate insulating film forming film is equal to the average adjusting metal of the adjusting metal in the second gate insulating film forming film. A method of manufacturing a semiconductor device, wherein the first gate insulating film forming film and the second gate insulating film forming film are formed so as to be lower than a concentration.
  11. 　請求項１０に記載の半導体装置の製造方法において、
    　前記工程（ｂ）は、前記ゲート絶縁膜形成膜における前記第１の領域上に、第１の膜厚を有し且つ前記調整用金属を含む第１の調整用金属膜を形成する工程（ｂ１）と、前記ゲート絶縁膜形成膜における前記第２の領域上に、第２の膜厚を有し且つ前記調整用金属を含む第２の調整用金属膜を形成する工程（ｂ２）と、前記工程（ｂ１）及び前記工程（ｂ２）の後に、熱処理により前記第１の調整用金属膜中の前記調整用金属を前記ゲート絶縁膜形成膜における前記第１の領域に導入して前記第１のゲート絶縁膜形成膜を形成すると共に、前記第２の調整用金属膜中の前記調整用金属を前記ゲート絶縁膜形成膜における前記第２の領域に導入して前記第２のゲート絶縁膜形成膜を形成する工程（ｂ３）とを備え、
    　前記第１の膜厚は、前記第２の膜厚に比べて薄いことを特徴とする半導体装置の製造方法。     In the manufacturing method of the semiconductor device according to claim 10,
    The step (b) is a step (b1) of forming a first adjustment metal film having a first film thickness and including the adjustment metal on the first region in the gate insulating film formation film. And (b2) forming a second adjustment metal film having a second film thickness and including the adjustment metal on the second region in the gate insulating film formation film, After the step (b1) and the step (b2), the adjustment metal in the first adjustment metal film is introduced into the first region of the gate insulating film formation film by heat treatment to introduce the first Forming a gate insulating film forming film and introducing the adjusting metal in the second adjusting metal film into the second region of the gate insulating film forming film to form the second gate insulating film forming film; A step (b3) of forming
    The method of manufacturing a semiconductor device, wherein the first film thickness is thinner than the second film thickness.
  12. 　請求項１０に記載の半導体装置の製造方法において、
    　前記工程（ｂ）は、前記ゲート絶縁膜形成膜上に、前記調整用金属を含む調整用金属膜を形成する工程（ｂ１）と、前記工程（ｂ１）の後に、第１の熱処理により前記調整用金属膜中の前記調整用金属を前記ゲート絶縁膜形成膜における前記第１の領域に導入して前記第１のゲート絶縁膜形成膜を形成すると共に、前記調整用金属膜中の前記調整用金属を前記ゲート絶縁膜形成膜における前記第２の領域に導入する工程（ｂ２）と、前記工程（ｂ２）の後に、前記調整用金属膜における前記第１のゲート絶縁膜形成膜上に位置する部分を除去する工程（ｂ３）と、工程（ｂ３）の後に、第２の熱処理により前記調整用金属膜中の前記調整用金属を前記ゲート絶縁膜形成膜における前記第２の領域に追加導入して前記第２のゲート絶縁膜形成膜を形成する工程（ｂ４）とを備えていることを特徴とする半導体装置の製造方法。     In the manufacturing method of the semiconductor device according to claim 10,
    The step (b) includes a step (b1) of forming an adjustment metal film including the adjustment metal on the gate insulating film formation film, and a first heat treatment after the step (b1). The adjustment metal in the adjustment metal film is introduced into the first region of the gate insulation film formation film to form the first gate insulation film formation film, and the adjustment metal in the adjustment metal film is formed. After the step (b2) of introducing metal into the second region in the gate insulating film forming film and the step (b2), the metal is positioned on the first gate insulating film forming film in the adjustment metal film. After the step (b3) of removing the portion and the step (b3), the adjustment metal in the adjustment metal film is additionally introduced into the second region in the gate insulating film formation film by a second heat treatment. The second gate insulating film forming film The method of manufacturing a semiconductor device characterized by and a step (b4) to be formed.
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