WO2011135896A1 - Semiconductor device, and manufacturing method for same - Google Patents

Semiconductor device, and manufacturing method for same Download PDF

Info

Publication number
WO2011135896A1
WO2011135896A1 PCT/JP2011/053258 JP2011053258W WO2011135896A1 WO 2011135896 A1 WO2011135896 A1 WO 2011135896A1 JP 2011053258 W JP2011053258 W JP 2011053258W WO 2011135896 A1 WO2011135896 A1 WO 2011135896A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
film
insulating layer
buffer
semiconductor device
Prior art date
Application number
PCT/JP2011/053258
Other languages
French (fr)
Japanese (ja)
Inventor
博章 古川
Original Assignee
シャープ株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by シャープ株式会社 filed Critical シャープ株式会社
Publication of WO2011135896A1 publication Critical patent/WO2011135896A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
    • H01L29/78648—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate arranged on opposing sides of the channel

Definitions

  • the present invention relates to a semiconductor device having a light-shielding conductive layer and a method for manufacturing the same.
  • a semiconductor device having a light-shielding conductive layer on a substrate is known.
  • a semiconductor device for example, as disclosed in Japanese Patent Application Laid-Open No. 2002-108244, a light shielding film positioned between a thin film transistor and a substrate is connected to a constant potential source.
  • Japanese Patent Laid-Open No. 2002-108244 discloses a manufacturing method in which a contact hole extending to a light shielding layer and a contact hole extending to a semiconductor layer are simultaneously formed.
  • an electrical influence such as noise occurs due to a parasitic capacitance existing in the semiconductor device.
  • a method of adjusting the potential of the conductive layer having a light shielding property is considered. Specifically, a configuration in which the conductive layer is connected to, for example, a source wiring and the potential of the conductive layer is controlled is considered.
  • the etching time required for forming the conductive layer contact hole penetrating the plurality of layers is longer than the etching time required for forming the semiconductor layer contact hole extending to the semiconductor layer.
  • the inside of the semiconductor layer contact hole is Etching is excessive. That is, since etching is performed while the contact hole extending to the conductive layer is formed, the semiconductor layer may be excessively etched in the semiconductor layer contact hole, and the semiconductor layer may be reduced in thickness or penetrated. .
  • An object of the present invention is to prevent an excessive etching of a semiconductor layer when a contact hole extending to a semiconductor layer and a contact hole extending to a conductive layer are simultaneously formed by etching.
  • a method for manufacturing a semiconductor device includes a conductive layer forming step of forming a light-shielding conductive layer on a substrate, and an insulating layer forming step of forming an insulating layer on the substrate and the conductive layer.
  • a semiconductor layer forming step of forming an island-shaped semiconductor layer in either the insulating layer or on the insulating layer, and the insulating layer other than the region where the semiconductor layer is formed and on the conductive layer An insulating layer removing step for forming an insulating layer removing portion by removing a part of the insulating layer located on the substrate; an interlayer insulating layer forming step for forming an interlayer insulating layer above the substrate; and a surface of the interlayer insulating layer A contact hole that simultaneously forms a semiconductor layer contact hole extending from the surface of the interlayer insulating layer to the semiconductor layer and a conductive layer contact hole extending from the surface of the interlayer insulating layer to the conductive layer through the insulating layer removing portion by etching. It has a Le forming step.
  • FIG. 1 is a perspective view illustrating a schematic configuration of a display panel of a liquid crystal display device including the semiconductor device according to the first embodiment.
  • FIG. 2 is a cross-sectional view illustrating a schematic configuration of the semiconductor device according to the first embodiment.
  • FIG. 3A is a diagram illustrating a state in which a resist pattern for forming a removal portion is formed in the manufacturing process of the semiconductor device according to the first embodiment.
  • FIG. 3B is a diagram illustrating a state where a removal portion is formed in the manufacturing process of the semiconductor device according to the first embodiment.
  • FIG. 3C is a diagram illustrating a state in which a resist pattern for forming a contact hole is formed in the manufacturing process of the semiconductor device according to the first embodiment.
  • FIG. 3A is a diagram illustrating a state in which a resist pattern for forming a removal portion is formed in the manufacturing process of the semiconductor device according to the first embodiment.
  • FIG. 3B is a diagram illustrating a state where a removal portion is
  • FIG. 3D is a diagram illustrating a state in which the contact hole is formed in the manufacturing process of the semiconductor device according to the first embodiment.
  • FIG. 3E is a diagram illustrating a state in which the wiring, the protective film, and the transparent electrode are formed in the manufacturing process of the semiconductor device according to the first embodiment.
  • FIG. 4 is a cross-sectional view illustrating a schematic configuration of the semiconductor device according to the second embodiment.
  • FIG. 5A is a diagram illustrating a state in which a resist pattern for forming a removal portion is formed in the manufacturing process of the semiconductor device according to the second embodiment.
  • FIG. 5B is a diagram illustrating a state in which a removal portion is formed in the manufacturing process of the semiconductor device according to the second embodiment.
  • FIG. 5C is a diagram illustrating a state in which a resist pattern for forming a contact hole is formed in the manufacturing process of the semiconductor device according to the second embodiment.
  • FIG. 5D is a diagram illustrating a state in which contact holes are formed in the manufacturing process of the semiconductor device according to the second embodiment.
  • FIG. 5E is a diagram illustrating a state in which wiring, a protective film, and a transparent electrode are formed in the manufacturing process of the semiconductor device according to the second embodiment.
  • FIG. 6 is a cross-sectional view illustrating a schematic configuration of the semiconductor device according to the third embodiment.
  • FIG. 7A is a diagram illustrating a state in which a resist pattern for forming a removal portion is formed in the manufacturing process of the semiconductor device according to the third embodiment.
  • FIG. 7B is a diagram illustrating a state in which a removal portion is formed in the manufacturing process of the semiconductor device according to the third embodiment.
  • FIG. 7C is a diagram illustrating a state in which a resist pattern for forming a contact hole is formed in the manufacturing process of the semiconductor device according to the third embodiment.
  • FIG. 7D is a diagram illustrating a state in which contact holes are formed in the manufacturing process of the semiconductor device according to the third embodiment.
  • FIG. 7E is a diagram illustrating a state in which wiring, a protective film, and a transparent electrode are formed in the manufacturing process of the semiconductor device according to the third embodiment.
  • FIG. 8 is a cross-sectional view showing a schematic configuration of the semiconductor device according to the fourth embodiment.
  • FIG. 9A is a diagram illustrating a state in which a resist pattern for forming a removal portion is formed in the manufacturing process of the semiconductor device according to the fourth embodiment.
  • FIG. 9B is a diagram illustrating a state where a removal portion is formed in the manufacturing process of the semiconductor device according to the fourth embodiment.
  • FIG. 9C is a diagram illustrating a state in which a resist pattern for forming a contact hole is formed in the manufacturing process of the semiconductor device according to the fourth embodiment.
  • FIG. 9D is a diagram illustrating a state in which contact holes are formed in the manufacturing process of the semiconductor device according to the fourth embodiment.
  • FIG. 9E is a diagram illustrating a state in which the wiring, the protective film, and the transparent electrode are formed in the manufacturing process of the semiconductor device according to the fourth embodiment.
  • a method of manufacturing a semiconductor device includes: a conductive layer forming step of forming a light-shielding conductive layer on a substrate; and an insulating layer formation for forming an insulating layer on the substrate and the conductive layer.
  • the insulating layer includes a buffer layer and a gate insulating layer formed on the buffer layer.
  • the buffer layer and the gate insulating layer located on the conductive layer are formed. It is preferable that a part of each layer is removed to form the insulating layer removal portion (second method).
  • the time for forming the conductive layer contact hole is equal to or shorter than the time for forming the semiconductor layer contact hole in which at least the interlayer insulating layer needs to be etched. Therefore, since the etching time for forming the conductive layer contact hole and the semiconductor layer contact hole can be matched with the formation time of the semiconductor layer contact hole, it is possible to more reliably prevent the semiconductor layer from being excessively etched. .
  • the insulating layer includes a buffer layer, and in the insulating layer removing step, a part of the buffer layer located on the conductive layer is removed to form the insulating layer removing portion. Is preferred (third method).
  • a semiconductor layer is formed on the buffer layer so that the semiconductor layer is located between the buffer layer and the gate insulating layer.
  • the interlayer insulating film and the gate insulating film In the stagger type (top gate type) semiconductor device obtained by this method, in order to reach the semiconductor layer contact hole to the semiconductor layer, the interlayer insulating film and the gate insulating film must be etched. Even in the semiconductor device having such a configuration, when the above-described second or third method is used, the interlayer insulating film, or the interlayer insulating film and the gate insulating film are etched when the conductive layer contact hole is formed. Good. Therefore, the time for forming the conductive layer contact hole is equal to or less than the time for forming the semiconductor layer contact hole. Therefore, when the conductive layer contact hole is formed, the semiconductor layer can be prevented from being excessively etched.
  • a semiconductor layer is formed on the gate insulating layer formed on the buffer layer (fifth method).
  • the inverted stagger type (bottom gate type) semiconductor device obtained by this method if the above-described second or third method is used, it is not necessary to remove the buffer layer when forming the conductive layer contact hole. Therefore, the time for forming the conductive layer contact hole can be shortened accordingly. Therefore, when the conductive layer contact hole is formed, the semiconductor layer can be prevented from being excessively etched.
  • the method further includes a gate electrode forming step of forming a gate electrode on the insulating layer, and in the contact hole forming step, from the surface of the interlayer insulating layer to the gate electrode
  • the extending gate electrode contact hole is preferably formed at the same time (sixth method).
  • a semiconductor device includes a substrate, a light-shielding conductive layer formed on the substrate, an insulating layer formed on the substrate and the conductive layer, and in the insulating layer or A semiconductor layer formed on one of the insulating layers; an interlayer insulating layer formed over the substrate so as to cover the insulating layer and the semiconductor layer; and the conductive layer and the semiconductor in the interlayer insulating layer A wiring member extending to each of the layers, and the insulating layer is formed with an insulating layer removing portion in which at least a part of the conductive layer is removed except for the region where the semiconductor layer is formed. In the layer removal portion, the interlayer insulating layer and the wiring member extending to the conductive layer so as to penetrate the interlayer insulating layer are provided (seventh configuration).
  • the insulating layer preferably includes a buffer layer and a gate insulating layer formed on the buffer layer (eighth configuration).
  • the insulating layer includes a buffer layer, and the semiconductor layer is formed above the buffer layer (a ninth configuration).
  • the semiconductor layer is provided on the buffer layer so as to be positioned between the buffer layer and a gate insulating layer formed on the buffer layer.
  • the semiconductor layer is preferably provided on a gate insulating layer formed on the buffer layer (11th configuration).
  • the dimension of the structural member in each figure does not represent the dimension of an actual structural member, the dimension ratio of each structural member, etc. faithfully.
  • FIG. 1 shows a schematic configuration of a display panel 2 of a liquid crystal display device including the semiconductor device 1 according to the first embodiment. That is, the semiconductor device 1 according to the present embodiment is used for, for example, an active matrix substrate 3 constituting a display panel 2 of a liquid crystal display device.
  • the display panel 2 includes an active matrix substrate 3, a counter substrate 4, and a liquid crystal layer (not shown) sandwiched between them.
  • the display panel 2 is irradiated with light from a backlight device (not shown) of the liquid crystal display device.
  • the active matrix substrate 3 includes a substrate 30 on which many pixels are formed in a matrix.
  • the active matrix substrate 3 is provided with pixel electrodes and thin film transistors (TET: Thin Film Transistor, hereinafter referred to as “TFT”) corresponding to each pixel.
  • TFT Thin Film Transistor
  • the counter substrate 4 includes a counter electrode facing the pixel electrode and a color filter having a colored layer.
  • the liquid crystal display device controls the liquid crystal in the liquid crystal layer by driving the TFT of the active matrix substrate 3 in accordance with a signal from the driver 5 provided on the active matrix substrate 3, and displays an image on the display panel 2. Is configured to display.
  • FIG. 2 shows a schematic configuration of the semiconductor device 1 according to the present embodiment.
  • the TFT 10 is formed on the substrate 30, and a light shielding film 20 (light-shielding conductive layer) is formed between the substrate 30 and the TFT 10.
  • the light shielding film 20 is for preventing illumination light of the backlight device from being input to the TFT 10.
  • the substrate 30 is a translucent glass substrate constituting the active matrix substrate 3, for example. In all the drawings showing the cross section (including FIG. 2), only conductors and semiconductors in the drawing are hatched.
  • the TFT 10 is formed above the light shielding film 20 provided on the substrate 30. That is, the light shielding film 20 is formed in an island shape on the substrate 30, and the buffer film 21 is formed so as to cover the substrate 30 and the light shielding film 20.
  • the light shielding film 20 is a metal film (for example, Mo, W / TaN, MoW, Ti / Ti) containing tantalum (Ta) or titanium (Ti), tungsten (W), molybdenum (Mo), aluminum (Al), or the like as a main component. Al).
  • the buffer film 21 (insulating layer, buffer layer) is made of silicon oxide such as SiO 2 / SiNO or SiO 2 , SiN, silicon nitride, or the like.
  • the TFT 10 has an island-shaped silicon film 11 (semiconductor layer) formed on the buffer film 21.
  • the silicon film 11 is formed with a channel region and two semiconductor regions arranged in a plane so as to sandwich the channel region.
  • the silicon film 11 is made of polycrystalline silicon such as continuous grain boundary silicon (CGS) or low-temperature poly-silicon (LPS), ⁇ -Si, or the like.
  • Wires 12 and 13 are connected to the silicon film 11.
  • the wiring 12 is connected to the source electrode 31.
  • the wiring 13 is connected to the transparent electrode 25.
  • the source electrode 31 is made of a metal material such as Ti / Al / Ti or Ti / Al, TiN / Al / TiN, Mo / Al—Nd / Mo, or Mo / Al / Mo.
  • the transparent electrode 25 is made of a material such as ITO or ZnO.
  • a gate insulating film 22 (insulating layer, gate insulating layer) is formed so as to cover the buffer film 21 and the silicon film 11.
  • the gate insulating film 22 is made of SiO 2 or SiN, silicon oxide or silicon nitride such SiN / SiO 2.
  • the buffer film 21 and the gate insulating film 22 correspond to an insulating layer.
  • the gate electrode 14 of the TFT 10 is provided on the gate insulating film 22.
  • the gate electrode 14 is made of a metal material such as W / TaN or Mo, MoW, Ti / Al.
  • a wiring 15 (wiring member) is connected to the gate electrode 14. In the cross section shown in FIG. 2, the state in which the wiring 15 is connected to the gate electrode 14 on the right side is not shown, but as shown on the left side of FIG. A wiring 15 is connected to the gate electrode 14.
  • an interlayer insulating film 23 (interlayer insulating layer) is formed on the gate insulating film 22 so as to cover the gate insulating film 22 and the gate electrode 14.
  • a resin protective film 24 is formed on the interlayer insulating film 23.
  • the wiring 32 (wiring member) is connected to the light shielding film 20 outside the region where the TFT 10 having the above-described configuration is formed.
  • the wiring 32 is connected to the source electrode 31 although not particularly shown. Therefore, the potential of the light shielding film 20 is adjusted by the source electrode 31 through the wiring 32. As a result, the potential of the light shielding film 20 can be adjusted to reduce the influence of parasitic capacitance existing between the TFT 10 and the light shielding film 20.
  • the wiring 32 is connected to the source electrode 31 in this embodiment, but may be connected to other wiring.
  • the buffer film 21 and the gate insulating film 22 formed on the light shielding film 20 are surrounded by a portion surrounding the connection portion between the wiring 32 and the light shielding film 20.
  • the removal part 40 (insulating layer removal part) from which the is removed is formed. That is, the buffer film 21 and the gate insulating film 22 are not formed on the light shielding film 20 around the connection portion with the wiring 32, and only the interlayer insulating film 23 is formed.
  • FIGS. 3A to 3E are cross-sectional views showing the manufacturing process of the semiconductor device 1 in this embodiment.
  • a light shielding film 20 is formed on the substrate 30 to prevent the illumination light of the backlight device from entering the TFT 10 from one surface side (the lower side in the figure) of the substrate 30. To do.
  • a light-shielding thin film having a thickness of about 30 nm to 300 nm is formed on one surface (upper surface in the drawing) of the substrate 30 by a CVD (Chemical Vapor Deposition) method, a sputtering method, or the like.
  • a resist pattern is formed by photolithography to cover a region where the light shielding film 20 is to be formed (hereinafter referred to as a region to be formed), and the light shielding thin film is etched using this resist pattern as a mask. Thereby, the light shielding film 20 is obtained.
  • the light shielding film 20 is made of, for example, Mo.
  • a buffer film 21 is formed so as to cover the substrate 30 and the light shielding film 20.
  • the buffer film 21 is made of, for example, a laminated film of SiNO / SiO 2 .
  • the buffer film 21 is formed with a thickness of about 100 nm to 400 nm by a CVD method.
  • a silicon thin film made of, for example, CGS is formed on the buffer film 21 by a CVD method.
  • This silicon thin film is formed to have a thickness of 30 nm to 100 nm.
  • a resist pattern that covers a region where the silicon film 11 is to be formed is formed by photolithography, and the silicon thin film is etched using the resist pattern as a mask. Thereby, the silicon film 11 is obtained.
  • the silicon film 11 is doped by ion implantation or the like, and a source region and a drain region (not shown) are formed in the silicon film 11.
  • a gate insulating film 22 made of, for example, SiO 2 is formed on the buffer film 21 and the silicon film 11 by a CVD method.
  • the gate insulating film 22 is formed to have a thickness of 50 nm to 200 nm.
  • a metal film made of, for example, W / TaN is formed on the gate insulating film 22 by a sputtering method. This metal film is formed to have a thickness of 200 nm to 500 nm. Thereafter, a resist pattern that covers a region where the gate electrode 14 is to be formed is formed by photolithography, and the metal film is etched using the resist pattern as a mask. Thereby, the gate electrode 14 is obtained.
  • a resist pattern 41 is formed on the gate insulating film 22 and the gate electrode 14 so as to be opened above the light shielding film 20 and in a portion other than the region where the silicon film 11 is formed. That is, the resist pattern 41 has an opening that exposes a region where the removal portion 40 is to be formed in the gate insulating film 22.
  • the gate insulating film 22 and the buffer film 21 are etched using the resist pattern 41 as a mask. At this time, the gate insulating film 22 and the buffer film 21 are etched until the light shielding film 20 is exposed. As a result, the gate insulating film 22 and the buffer film 21 located above a part of the light shielding film 20 are removed, and the removal portion 40 is formed.
  • 3B is performed by wet etching using buffered hydrofluoric acid (BHF) or etching gas (C 4 F 8 , SF 6 , CF 4 , O 2 , Ar, H 2, etc.).
  • BHF buffered hydrofluoric acid
  • etching gas C 4 F 8 , SF 6 , CF 4 , O 2 , Ar, H 2, etc.
  • the dry etching used may be used.
  • the method which combined these wet etching and dry etching may be used.
  • an interlayer insulating film 23 made of, for example, a laminated film of SiO 2 / SiN is formed on the gate insulating film 22, the gate electrode 14, and the removal portion 40 by a CVD method. Form. Thereafter, a resist pattern 42 is formed on the interlayer insulating film 23.
  • the resist pattern 42 has an opening that exposes regions where the contact holes 43 to 46 where the wirings 15, 32, 13, and 12 are to be formed are exposed.
  • regions where the contact holes 46 and 45 are formed on the silicon film 11 in plan view (viewed from above). positioned. A region where a contact hole 43 (gate electrode contact hole) in which the wiring 15 is to be formed is located on the gate electrode 14 in plan view (viewed from above). A region in which the contact hole 44 (conductive layer contact hole) where the wiring 32 is to be formed is located in the removal portion 40 in plan view (viewed from above in the drawing).
  • the interlayer insulating film 23 and the gate insulating film 22 are etched using the resist pattern 42 as a mask.
  • contact holes 43 to 46 extending from the surface of the interlayer insulating film 23 to the gate electrode 14, the light shielding film 20, and the silicon film 11 are formed.
  • the etching at this time is preferably dry etching using an etching gas. Note that not all etching is performed by dry etching, but wet etching may be performed after most of the etching is performed by dry etching.
  • the buffer film 21 and the gate insulating film 22 are removed, and only the interlayer insulating film 23 is formed.
  • the film thickness that needs to be etched is the thickest in the regions where the contact holes 45 and 46 of the wirings 12 and 13 connected to the silicon film 11 are to be formed. That is, in the regions where the contact holes 43 and 44 of the wirings 15 and 32 are to be formed, only the interlayer insulating film 23 needs to be etched, whereas in the regions where the contact holes 45 and 46 of the wirings 13 and 12 are to be formed, interlayer insulation is performed. It is necessary to etch the film 23 and the gate insulating film 22.
  • the regions where the contact holes 43 to 46 are to be formed can be etched at a time based on the etching time of the regions where the contact holes 45 and 46 are to be formed. Therefore, it is possible to prevent the silicon film 11 from being excessively etched during the etching shown in FIG. 3D. Further, since the regions where the contact holes 43 and 44 of the wirings 15 and 32 are to be formed have substantially the same thickness of the interlayer insulating film 23, the gate electrode 14 is formed when the regions where the contact holes 43 and 44 are to be formed are etched simultaneously. Can be prevented from being excessively etched.
  • the step of forming the light shielding film 20 on the substrate 30 is a conductive layer forming step
  • the step of forming the buffer film 21 and the gate insulating film 22 on the substrate 30 and the light shielding film 20 is an insulating layer forming step.
  • the step of forming the silicon film 11 on the buffer film 21 corresponds to the semiconductor layer forming step
  • the step of forming the gate electrode 14 on the gate insulating film 22 corresponds to the gate electrode forming step.
  • the step of forming the removal portion 40 by removing the buffer film 21 and the gate insulating film 22 located above a part of the light shielding film 20 is the insulating layer removing step, and the step of forming the interlayer insulating layer 23 is the interlayer insulation.
  • the process of forming the contact holes 43 to 46 corresponds to the contact hole forming process.
  • the interlayer insulating film 23 is formed after removing the buffer film 21 and the gate insulating film 22 formed on the light shielding film 20 in the portion where the wiring 32 is connected to the light shielding film 20. Then, the regions where the plurality of contact holes 43 to 46 are to be formed are etched simultaneously. This eliminates the need to etch the buffer film 21 and the gate insulating film 22 in the region where the contact hole 44 is to be formed in the wiring 32 when simultaneously etching the region where the plurality of contact holes 43 to 46 are to be formed.
  • the silicon film 11 is formed in the formation regions of the contact holes 45 and 46 of the wirings 13 and 12 when simultaneously etching the formation regions of the contact holes 43 to 46. Excessive etching can be prevented.
  • the TFT 10 in this embodiment is a so-called top gate type in which the silicon film 11 is located between the buffer film 21 and the gate insulating film 22 and the gate electrode 14 is formed on the gate insulating film 22. TFT. Therefore, the film thickness that needs to be etched is the thickest in the regions where the contact holes 45 and 46 of the wirings 12 and 13 connected to the silicon film 11 are to be formed. Therefore, since the regions where the other contact holes 43 and 44 are to be formed can be etched in accordance with the time for etching the regions where the contact holes 45 and 46 are to be formed, the silicon film 11 is reduced or penetrated by the etching. Can be more reliably prevented.
  • the region where the contact hole 43 is to be formed in the wiring 15 connected to the gate electrode 14 and the region where the contact hole 44 is to be formed in the wiring 32 connected to the light shielding film 20 are the thickness of the interlayer insulating film 23 to be etched. Are almost the same. Therefore, it is possible to prevent the gate electrode 14 from being excessively etched when simultaneously forming the regions where the plurality of contact holes 43 to 46 are to be formed.
  • FIG. 4 shows a schematic configuration of a semiconductor device 50 according to the second embodiment. This embodiment is different from the first embodiment in the configuration of the removal unit 70 and the method for manufacturing the semiconductor device 50.
  • the same components as those in the first embodiment are denoted by the same reference numerals, and only different portions will be described.
  • the removal portion 70 (insulating layer removal portion) is formed only in the buffer film 51 (insulating layer, buffer layer). That is, a gate insulating film 52 (gate insulating layer) is formed on the light shielding film 20 around the connection portion with the wiring 32, and an interlayer insulating film 53 (interlayer insulating layer) is formed on the gate insulating film 52. Is formed.
  • This configuration shortens the time required for etching the formation region because the buffer film 51 does not exist in the formation region of the contact hole 44 of the wiring 32. Therefore, when the regions where the contact holes 43 to 46 of the wirings 15, 32, 13 and 12 are to be formed are etched simultaneously, the silicon film 11 connected to the wirings 12 and 13 and the gate electrode 14 connected to the wiring 15 are excessive. Etching can be suppressed.
  • FIGS. 5A to 5E are cross-sectional views showing the manufacturing process of the semiconductor device 50 in this embodiment.
  • the material and manufacturing method of each film constituting the semiconductor device 50 are the same as those in the first embodiment.
  • the illumination light of the backlight device is prevented from being incident on the TFT 60 from one surface side (the lower side of the drawing) of the substrate 30 on the substrate 30.
  • a light shielding film 20 is formed.
  • a buffer film 51 is formed so as to cover the substrate 30 and the light shielding film 20.
  • the silicon film 11 is formed on the buffer film 51 as in the first embodiment.
  • a resist pattern 71 is formed on the buffer film 51 and the silicon film 11 by photolithography so as to be opened above the light shielding film 20 and in a portion other than the region where the silicon film 11 is formed. That is, the resist pattern 71 has an opening that exposes a region where the removal portion 70 is to be formed in the buffer film 51.
  • the buffer film 51 is etched using the resist pattern 71 as a mask. At this time, the buffer film 51 is etched until the light shielding film 20 is exposed. As a result, the buffer film 51 located above a part of the light shielding film 20 is removed, and the removal portion 70 is formed.
  • the etching in FIG. 5B may be wet etching or dry etching, as in the first embodiment. Moreover, the method which combined these wet etching and dry etching may be used.
  • a gate insulating film 52 similar to that of the first embodiment is formed on the buffer film 51 and the silicon film 11, and a gate is formed on the gate insulating film 52.
  • the electrode 14 is formed.
  • an interlayer insulating film 53 is formed, and a resist pattern 72 having an opening that exposes regions where the contact holes 43 to 46 in which the wirings 15, 32, 13, and 12 are formed is exposed on the interlayer insulating film 53.
  • regions where the contact holes 45 and 46 in which the wirings 13 and 12 are to be formed are located on the silicon film 11 in plan view (viewed from above).
  • a region where the contact hole 43 where the wiring 15 is to be formed is located on the gate electrode 14 in plan view (viewed from above).
  • a region where the contact hole 44 where the wiring 32 is to be formed is located in the removal portion 70 in plan view (as viewed from above).
  • the interlayer insulating film 53 and the gate insulating film 52 are etched using the resist pattern 72 as a mask.
  • contact holes 43 to 46 extending from the surface of the interlayer insulating film 53 to the gate electrode 14, the light shielding film 20, and the silicon film 11 are formed.
  • the etching at this time is preferably dry etching using an etching gas. Note that it is not necessary to perform all etching by dry etching, and wet etching may be performed after most of the etching is performed by dry etching.
  • the buffer film 51 is removed, and only the gate insulating film 52 and the interlayer insulating film 53 are formed. Therefore, the film thickness that needs to be etched in the region where the contact hole 44 is to be formed is equivalent to the film thickness that needs to be etched in the region where the contact holes 45 and 46 of the wirings 13 and 12 are to be formed. Therefore, it is possible to prevent the silicon film 11 to which the wirings 12 and 13 are connected from being excessively etched when etching is performed simultaneously in the regions where the plurality of contact holes 44 to 46 are to be formed.
  • the wirings 15, 32, 13, 12 are formed in the contact holes 43 to 46, and the source electrode 31 is formed. Then, the protective film 24 and the transparent electrode 25 are formed on the interlayer insulating film 53. Thereby, the semiconductor device 50 is formed.
  • the step of forming the light shielding film 20 on the substrate 30 corresponds to the conductive layer forming step
  • the step of forming the buffer film 51 on the substrate 30 and the light shielding film 20 corresponds to the insulating layer forming step.
  • the process of forming the silicon film 11 on the buffer film 51 corresponds to the semiconductor layer forming process
  • the process of forming the gate electrode 14 on the gate insulating film 52 corresponds to the gate electrode forming process.
  • the step of removing the buffer film 51 located above a part of the light shielding film 20 to form the removal portion 70 is the insulating layer removing step
  • the step of forming the interlayer insulating layer 53 is the interlayer insulating layer forming step.
  • the process of forming the contact holes 43 to 46 corresponds to the contact hole forming process.
  • the gate insulating film 52 and the interlayer insulating film 53 are formed after removing the buffer film 51 formed on the light shielding film 20 in the portion where the wiring 32 is connected to the light shielding film 20. Then, the regions where the plurality of contact holes 43 to 46 are to be formed are etched simultaneously.
  • the film thickness that needs to be etched in the region where the contact hole 44 of the wiring 32 is to be formed is the film thickness that needs to be etched in the region where the contact holes 45 and 46 of the wiring 13 and 12 connected to the silicon film 11 are to be formed.
  • FIG. 6 shows a schematic configuration of a semiconductor device 100 according to the third embodiment.
  • the configuration of the TFT 110 is different from that of the first embodiment.
  • the same components as those in the first embodiment are denoted by the same reference numerals, and only different portions will be described.
  • the TFT 110 includes a silicon film 111 (semiconductor layer) formed on a gate insulating film 122 (insulating layer, gate insulating layer), and a buffer film 121 (insulating layer, buffer layer).
  • a silicon film 111 semiconductor layer
  • a gate insulating film 122 insulating layer, gate insulating layer
  • a buffer film 121 insulating layer, buffer layer
  • the wiring 132 (wiring member) connected to the light shielding film 20 is provided in the removing portion 140 (insulating layer removing portion) from which the buffer film 121 and the gate insulating film 122 are removed. That is, the removal portion 140 from which the buffer film 121 and the gate insulating film 122 are removed is formed on the light shielding film 20 around the connection portion with the wiring 132, and the interlayer insulation film 123 is formed in the removal portion 140. Is provided.
  • the contact hole 144 of the wiring 132 is scheduled to be formed when the formation regions of the contact holes 143 to 146 (see FIG. 7D) of the wirings 115, 132, 113, and 112 are simultaneously etched.
  • the etching time of the region can be shortened.
  • FIGS. 7A to 7E are cross-sectional views showing the manufacturing process of the semiconductor device 100 in this embodiment.
  • the material of each film constituting the semiconductor device 100 is the same as that in the first and second embodiments.
  • the illumination light of the backlight device is prevented from entering the TFT 110 from one surface side (the lower side of the drawing) of the substrate 30 on the substrate 30.
  • a light shielding film 20 is formed.
  • a buffer film 121 is formed so as to cover the substrate 30 and the light shielding film 20.
  • a metal film is formed on the buffer film 121 by sputtering. Thereafter, a resist pattern is formed by photolithography to cover a region where the gate electrode 114 is to be formed, and the metal film is etched using the resist pattern as a mask. Thereby, the gate electrode 114 is obtained.
  • a gate insulating film 122 similar to that of the first embodiment is formed on the buffer film 121 and the gate electrode 114 by a CVD method.
  • a silicon thin film is formed on the gate insulating film 122 by a CVD method.
  • a resist pattern that covers a region where the silicon film 111 is to be formed is formed by photolithography, and the silicon thin film is etched using the resist pattern as a mask. Thereby, the silicon film 111 is obtained.
  • a resist pattern 141 is formed on the gate insulating film 122 and the silicon film 111 so as to open above the light shielding film 20 and in a portion other than the region where the silicon film 111 is formed. That is, the resist pattern 141 has an opening that exposes a region where the removal portion 140 is to be formed in the gate insulating film 122.
  • the gate insulating film 122 and the buffer film 121 are etched using the resist pattern 141 as a mask. At this time, the gate insulating film 122 and the buffer film 121 are etched until the light shielding film 20 is exposed. As a result, the gate insulating film 122 and the buffer film 121 located above a part of the light shielding film 20 are removed, and the removal portion 140 is formed.
  • the etching in FIG. 7B may be wet etching or dry etching, as in the first embodiment. Moreover, the method which combined these wet etching and dry etching may be used.
  • an interlayer insulating film 123 is formed on the gate insulating film 122, the silicon film 111, and the removal portion 140 by a CVD method. Thereafter, a resist pattern 142 is formed on the interlayer insulating film 123 so as to open regions where the contact holes 143 to 146 in which the wirings 115, 132, 113, and 112 are formed are opened.
  • regions where the contact holes 145 and 146 semiconductor layer contact holes
  • regions where the contact holes 145 and 146 semiconductor layer contact holes
  • a region where the contact hole 143 (gate electrode contact hole) where the wiring 115 is to be formed is located on the gate electrode 114 in plan view (viewed from above).
  • a region in which the contact hole 144 (conductive layer contact hole) where the wiring 132 is to be formed is located in the removal portion 140 in plan view (viewed from above).
  • the interlayer insulating film 123 and the gate insulating film 122 are etched using the resist pattern 142 as a mask. Thereby, contact holes 143 to 146 extending from the surface of the interlayer insulating film 123 to the gate electrode 114, the light shielding film 20, and the silicon film 111 are formed.
  • the etching at this time is preferably dry etching using an etching gas. Note that it is not necessary to perform all etching by dry etching, and wet etching may be performed after most of the etching is performed by dry etching.
  • the buffer film 121 and the gate insulating film 122 are removed in the region where the contact hole 144 of the wiring 132 is to be formed, and only the interlayer insulating film 123 is formed. Therefore, the film thickness to be etched is the same in the region where the contact hole 144 of the wiring 132 is to be formed and the region where the contact holes 145 and 146 of the wiring 113 and 112 connected to the silicon film 111 are to be formed. Therefore, the silicon film 111 can be prevented from being excessively etched during the etching shown in FIG. 7D.
  • the film thickness to be etched is the thickest in the region where the contact hole 143 of the wiring 115 connected to the gate electrode 114 is to be formed. Therefore, the plurality of contact holes 143 to 146 can be etched simultaneously with reference to the time for etching the region. Since the region where the contact hole 143 is to be formed is only thicker than the other region by the amount of the gate insulating film 122, when simultaneously etching the contact holes 143 to 146, the light shielding film 20 and the silicon film 111 are formed. Can be prevented from being excessively etched.
  • wirings 115, 132, 113, 112 are formed in the contact holes 143 to 146, and a source electrode 131 is formed. Then, the protective film 24 and the transparent electrode 25 are formed on the interlayer insulating film 123. Thereby, the semiconductor device 100 is formed.
  • the process of forming the light shielding film 20 on the substrate 30 is a conductive layer forming process
  • the process of forming the buffer film 121 and the gate insulating film 122 on the substrate 30 and the light shielding film 20 is an insulating layer forming process.
  • the step of forming the silicon film 111 over the gate insulating film 122 corresponds to the semiconductor layer forming step
  • the step of forming the gate electrode 114 over the buffer film 121 corresponds to the gate electrode forming step.
  • the step of forming the removal portion 140 by removing the buffer film 121 and the gate insulating film 122 located above a part of the light shielding film 20 is the insulating layer removing step, and the step of forming the interlayer insulating layer 123 is the interlayer insulation.
  • the process of forming contact holes 143 to 146 corresponds to the contact hole forming process.
  • the removal portion 140 is formed after the silicon film 111 is formed on the gate insulating film 122.
  • the removal portion 140 may be formed before the silicon film 111 is formed.
  • the interlayer insulating film 123 is formed after removing the buffer film 121 and the gate insulating film 122 formed on the light shielding film 20 in the portion where the wiring 132 is connected to the light shielding film 20. Then, the regions where the plurality of contact holes 143 to 146 are to be formed are etched simultaneously. As a result, the film thickness etched in the region where the contact hole 144 of the wiring 132 is to be formed and the film thickness etched in the region where the contact holes 145 and 146 of the wiring 113 and 112 connected to the silicon film 111 are formed are reduced. It becomes possible to make it equivalent. Therefore, when the regions where the plurality of contact holes 143 to 146 are to be formed are etched simultaneously, the silicon film 111 can be prevented from being excessively etched in the regions where the contact holes 145 and 146 are to be formed.
  • the etching thickness of the contact hole 143 of the wiring 115 connected to the gate electrode 114 is the thickest, so that the plurality of contact holes 143 to 146 are formed with reference to the etching time of the formation region.
  • the region to be formed can be etched. This can prevent excessive etching of the gate electrode 114, the light shielding film 20, and the silicon film 111 when simultaneously etching regions where the plurality of contact holes 143 to 146 are to be formed.
  • FIG. 8 shows a schematic configuration of a semiconductor device 150 according to the fourth embodiment. This embodiment is different from the third embodiment in the configuration of the removal unit 170 and the method for manufacturing the semiconductor device 150.
  • the same components as those of the third embodiment are denoted by the same reference numerals, and only different portions will be described.
  • the removal portion 170 is formed only in the buffer film 151 (insulating layer, buffer layer). That is, the gate insulating film 152 (gate insulating layer) is formed on the light shielding film 20 around the connection portion with the wiring 132 (wiring member), and the interlayer insulating film 153 (interlayer insulating film) is formed on the gate insulating film 152. An insulating layer) is formed.
  • the etching time for the region to be formed can be shortened because the buffer film 151 does not exist in the region for forming the contact hole 144 in which the wiring 132 is formed. Therefore, when the regions where the contact holes 143 to 146 are to be formed are simultaneously etched in the wirings 115, 132, 113, and 112, the silicon film 111 connected to the wirings 113 and 112 and the gate electrode 114 connected to the wiring 115 are excessive. Etching can be suppressed.
  • FIGS. 9A to 9E are cross-sectional views showing the manufacturing process of the semiconductor device 150 in this embodiment.
  • the material and manufacturing method of each film constituting the semiconductor device 150 are the same as those in the third embodiment.
  • the illumination light of the backlight device is prevented from being incident on the TFT 160 on the substrate 30 from one surface side (the lower side of the drawing).
  • a light shielding film 20 is formed.
  • a buffer film 151 is formed so as to cover the substrate 30 and the light shielding film 20.
  • the gate electrode 114 is formed on the buffer film 151 as in the third embodiment.
  • a resist pattern 171 is formed on the buffer film 151 and on the gate electrode 114 by photolithography so as to open at a portion above the light shielding film 20 and other than the region where the gate electrode 114 is formed. That is, the resist pattern 171 has an opening that exposes a region where the removal portion 170 is to be formed in the buffer film 151.
  • the buffer film 151 is etched using the resist pattern 171 as a mask. At this time, the buffer film 151 is etched until the light shielding film 20 is exposed. As a result, the buffer film 151 located above a part of the light shielding film 20 is removed, and the removal unit 170 is formed.
  • the etching in FIG. 9B may be wet etching or dry etching, as in the third embodiment. Moreover, the method which combined these wet etching and dry etching may be used.
  • a gate insulating film 152 similar to that of the third embodiment is formed on the buffer film 151 and the gate electrode 114, and on the gate insulating film 152, A silicon film 111 similar to that of the third embodiment is formed. Thereafter, an interlayer insulating film 153 is formed, and a resist pattern 172 having an opening that exposes regions where the contact holes 143 to 146 in which the wirings 115, 132, 113, and 112 are formed is exposed on the interlayer insulating film 153.
  • regions where the contact holes 145 and 146 where the wirings 113 and 112 are formed are located on the silicon film 11 in plan view (viewed from above).
  • a region where the contact hole 143 is to be formed in which the wiring 115 is formed is located on the gate electrode 114 in plan view (viewed from above).
  • a region where the contact hole 144 is to be formed in which the wiring 132 is to be formed is located in the removal portion 170 in plan view (viewed from above).
  • the interlayer insulating film 153 and the gate insulating film 152 are etched using the resist pattern 172 as a mask.
  • the etching at this time is preferably dry etching using an etching gas. Note that it is not necessary to perform all etching by dry etching, and wet etching may be performed after most of the etching is performed by dry etching.
  • the buffer film 151 is removed, and only the gate insulating film 152 and the interlayer insulating film 153 are formed. Therefore, when simultaneously etching the regions where the wirings 112, 113, and 132 are to be formed, the entire etching time can be shortened because the buffer film 151 need not be etched in the regions where the wiring 132 is to be formed. Therefore, it is possible to prevent the silicon film 111 to which the wirings 112 and 113 are connected from being excessively etched when etching the regions where the plurality of contact holes 144 to 146 are to be formed.
  • the region where the contact hole 143 is to be formed in the wiring 115 connected to the gate electrode 114 and the region where the contact hole 144 is to be formed have the same etching thickness. Therefore, it is possible to prevent the gate electrode 114 from being excessively etched when simultaneously etching the plurality of contact holes 143 to 146.
  • wirings 115, 132, 113, and 112 are formed in the contact holes 143 to 146, and the source electrode 31 is formed. Then, the protective film 24 and the transparent electrode 25 are formed on the interlayer insulating film 153. Thereby, the semiconductor device 150 is formed.
  • the step of forming the light shielding film 20 on the substrate 30 corresponds to the conductive layer forming step
  • the step of forming the buffer film 151 on the substrate 30 and the light shielding film 20 corresponds to the insulating layer forming step
  • the step of forming the silicon film 111 over the gate insulating film 152 corresponds to the semiconductor layer formation step
  • the step of forming the gate electrode 114 over the buffer film 151 corresponds to the gate electrode formation step.
  • the step of removing the buffer film 151 located above a part of the light shielding film 20 to form the removed portion 170 is the insulating layer removing step
  • the step of forming the interlayer insulating layer 153 is the interlayer insulating layer forming step.
  • Each corresponds.
  • the process of forming contact holes 143 to 146 corresponds to the contact hole forming process.
  • the removal portion 170 is formed after the gate electrode 114 is formed on the buffer film 151.
  • the removal portion 170 may be formed before the gate electrode 114 is formed.
  • the gate insulating film 152 and the interlayer insulating film 153 are formed after removing the buffer film 151 formed on the light shielding film 20 in the portion where the wiring 132 is connected to the light shielding film 20. Then, the regions where the plurality of contact holes 143 to 146 are to be formed are etched simultaneously. Thus, the etching time can be shortened in the region where the contact hole 144 of the wiring 132 is to be formed, as compared with the case where the buffer film 151 is also etched at the same time. Accordingly, it is possible to prevent the silicon film 111 to which the wirings 112 and 113 are connected from being excessively etched when simultaneously etching the regions where the plurality of contact holes 143 to 146 are to be formed.
  • the region where the contact hole 143 is to be formed and the region where the contact hole 144 is to be formed in the wiring 115 connected to the gate electrode 114 have the same thickness, the plurality of contact holes 143 to 146 are etched simultaneously. In this case, the gate electrode 114 can be prevented from being excessively etched.
  • the contact holes 44 and 144 having a smaller diameter than the removal portions 40, 70, 140, and 170 are formed.
  • the diameter of the contact hole may be equal to or larger than that of the removed portion.
  • the buffer films 21, 51, 121, and 151 are all removed to expose the light shielding film 20.
  • part of the buffer film may be left as long as excessive etching of the silicon film when simultaneously etching a plurality of contact holes can be suppressed.
  • a semiconductor device having a three-terminal semiconductor element is illustrated.
  • the configuration of the first or second embodiment may be applied to a semiconductor device having a two-terminal semiconductor element (for example, a photodiode).
  • the semiconductor device having a two-terminal semiconductor element include, for example, a configuration in which the gate electrode is omitted and the silicon film 11 is formed as a PN junction or PIN junction diode in the first or second embodiment. .
  • This diode can be used as an optical sensor, for example.
  • the contact holes 43 and 143 extending to the gate electrodes 14 and 114, the contact holes 44 and 144 extending to the light shielding film 20, and the contact holes 45, 46, 145 and 146 extending to the silicon films 11 and 111 are formed. Forming at the same time. However, the contact holes 43, 143 extending to the gate electrodes 14, 114 may be formed separately from the other contact holes 43, 143, 45, 46, 145, 146.
  • the semiconductor device according to the present invention can be used for a semiconductor device in which wiring is connected to the light shielding film so that the potential of the light shielding film can be adjusted.

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Nonlinear Science (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Liquid Crystal (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

Disclosed is a manufacturing method for semiconductor devices which prevents excessive etching of the semiconductor layer when using etching to simultaneously form contact holes extending to the semiconductor layer and a contact hole extending to the conductive layer. A light-shielding film (20) is formed on a substrate (30). A buffer film (21), a gate insulating film (22), and a silicon film (11) are formed on the substrate (30) and the light-shielding film (20). A cleared section (40) is formed by removing a section of the buffer film (21) and the gate insulating film (22) which is disposed outside the area in which the silicon film (11) is formed and on the light-shielding film (20). An interlayer insulating film (23) is formed above the substrate (30). Etching is used to simultaneously form contact holes (45, 46) extending to the silicon film (11) and a contact hole extending to the light-shielding film (20) in the cleared section (40).

Description

半導体装置及びその製造方法Semiconductor device and manufacturing method thereof
　本発明は、遮光性の導電層を有する半導体装置、及び、その製造方法に関する。 The present invention relates to a semiconductor device having a light-shielding conductive layer and a method for manufacturing the same.
　従来より、基板上に遮光性の導電層を有する半導体装置が知られている。このような半導体装置では、例えば特開２００２－１０８２４４号公報に開示されるように、薄膜トランジスタと基板との間に位置する遮光膜が定電位源に接続されている。なお、前記特開２００２－１０８２４４号公報には、遮光層まで延びるコンタクトホールと半導体層まで延びるコンタクトホールとを同時に形成する製造方法が開示されている。 Conventionally, a semiconductor device having a light-shielding conductive layer on a substrate is known. In such a semiconductor device, for example, as disclosed in Japanese Patent Application Laid-Open No. 2002-108244, a light shielding film positioned between a thin film transistor and a substrate is connected to a constant potential source. Japanese Patent Laid-Open No. 2002-108244 discloses a manufacturing method in which a contact hole extending to a light shielding layer and a contact hole extending to a semiconductor layer are simultaneously formed.
　ところで、一般的に、半導体装置では、該半導体装置内に存在する寄生容量によってノイズ等の電気的な影響が生じる。この寄生容量による電気的な影響を低減するために、遮光性を有する導電層の電位を調整する方法が考えられている。具体的には、導電層を例えばソース配線等と接続して、該導電層の電位を制御する構成が考えられている。 By the way, generally, in a semiconductor device, an electrical influence such as noise occurs due to a parasitic capacitance existing in the semiconductor device. In order to reduce the electrical influence due to the parasitic capacitance, a method of adjusting the potential of the conductive layer having a light shielding property is considered. Specifically, a configuration in which the conductive layer is connected to, for example, a source wiring and the potential of the conductive layer is controlled is considered.
　導電層が基板上に形成されている構成の場合、上述のように導電層をソース配線に接続しようとすると、該導電層まで到達する導電層コンタクトホールを形成するためには、複数の層を除去するエッチングを行う必要がある。よって、複数の層を貫通する導電層コンタクトホールを形成するために必要なエッチング時間は、半導体層まで延びる半導体層コンタクトホールを形成するために必要なエッチング時間よりも長くなる。 In the case where the conductive layer is formed on the substrate, when the conductive layer is connected to the source wiring as described above, a plurality of layers are formed in order to form a conductive layer contact hole reaching the conductive layer. Etching to remove is necessary. Therefore, the etching time required for forming the conductive layer contact hole penetrating the plurality of layers is longer than the etching time required for forming the semiconductor layer contact hole extending to the semiconductor layer.
　そのため、前記特開２００２－１０８２４４号公報に開示されている構成のように、遮光層（導電層）まで延びるコンタクトホールと半導体層コンタクトホールとをエッチングによって同時形成する場合、半導体層コンタクトホール内が過剰にエッチングされてしまう。すなわち、導電層まで延びるコンタクトホールを形成している間、エッチングが行われるため、半導体層コンタクトホール内では、半導体層が過剰にエッチングされて該半導体層に膜減りや突き抜けが生じる可能性がある。 Therefore, when the contact hole extending to the light-shielding layer (conductive layer) and the semiconductor layer contact hole are formed simultaneously by etching as in the configuration disclosed in Japanese Patent Laid-Open No. 2002-108244, the inside of the semiconductor layer contact hole is Etching is excessive. That is, since etching is performed while the contact hole extending to the conductive layer is formed, the semiconductor layer may be excessively etched in the semiconductor layer contact hole, and the semiconductor layer may be reduced in thickness or penetrated. .
　本発明の目的は、半導体層まで延びるコンタクトホールと導電層まで延びるコンタクトホールとをエッチングによって同時に形成する際に、半導体層が過剰にエッチングされるのを防止することにある。 An object of the present invention is to prevent an excessive etching of a semiconductor layer when a contact hole extending to a semiconductor layer and a contact hole extending to a conductive layer are simultaneously formed by etching.
　本発明の一側面にかかる半導体装置の製造方法は、基板上に遮光性を有する導電層を形成する導電層形成工程と、前記基板上及び導電層上に、絶縁層を形成する絶縁層形成工程と、前記絶縁層内または該絶縁層上のいずれか一方に、島状の半導体層を形成する半導体層形成工程と、前記絶縁層のうち、前記半導体層の形成領域以外で且つ前記導電層上に位置する絶縁層の一部を除去して、絶縁層除去部を形成する絶縁層除去工程と、前記基板の上方に層間絶縁層を形成する層間絶縁層形成工程と、前記層間絶縁層の表面から前記半導体層まで延びる半導体層コンタクトホールと、前記層間絶縁層の表面から前記絶縁層除去部内を通過して前記導電層まで延びる導電層コンタクトホールと、をエッチングによって同時に形成するコンタクトホール形成工程と、を有する。 A method for manufacturing a semiconductor device according to one aspect of the present invention includes a conductive layer forming step of forming a light-shielding conductive layer on a substrate, and an insulating layer forming step of forming an insulating layer on the substrate and the conductive layer. A semiconductor layer forming step of forming an island-shaped semiconductor layer in either the insulating layer or on the insulating layer, and the insulating layer other than the region where the semiconductor layer is formed and on the conductive layer An insulating layer removing step for forming an insulating layer removing portion by removing a part of the insulating layer located on the substrate; an interlayer insulating layer forming step for forming an interlayer insulating layer above the substrate; and a surface of the interlayer insulating layer A contact hole that simultaneously forms a semiconductor layer contact hole extending from the surface of the interlayer insulating layer to the semiconductor layer and a conductive layer contact hole extending from the surface of the interlayer insulating layer to the conductive layer through the insulating layer removing portion by etching. It has a Le forming step.
　本発明により、半導体層までのコンタクトホールと導電層までのコンタクトホールとをエッチングによって同時に形成しても、半導体層の過剰なエッチングを防止することができる。 According to the present invention, excessive etching of the semiconductor layer can be prevented even if the contact hole to the semiconductor layer and the contact hole to the conductive layer are simultaneously formed by etching.
図１は、第１の実施形態にかかる半導体装置を備えた液晶表示装置の表示パネルの概略構成を示す斜視図である。FIG. 1 is a perspective view illustrating a schematic configuration of a display panel of a liquid crystal display device including the semiconductor device according to the first embodiment. 図２は、第１の実施形態にかかる半導体装置の概略構成を示す断面図である。FIG. 2 is a cross-sectional view illustrating a schematic configuration of the semiconductor device according to the first embodiment. 図３Ａは、第１の実施形態にかかる半導体装置の製造工程において、除去部を形成するためのレジストパターンを形成した状態を示す図である。FIG. 3A is a diagram illustrating a state in which a resist pattern for forming a removal portion is formed in the manufacturing process of the semiconductor device according to the first embodiment. 図３Ｂは、第１の実施形態にかかる半導体装置の製造工程において、除去部を形成した状態を示す図である。FIG. 3B is a diagram illustrating a state where a removal portion is formed in the manufacturing process of the semiconductor device according to the first embodiment. 図３Ｃは、第１の実施形態にかかる半導体装置の製造工程において、コンタクトホールを形成するためのレジストパターンを形成した状態を示す図である。FIG. 3C is a diagram illustrating a state in which a resist pattern for forming a contact hole is formed in the manufacturing process of the semiconductor device according to the first embodiment. 図３Ｄは、第１の実施形態にかかる半導体装置の製造工程において、コンタクトホールを形成した状態を示す図である。FIG. 3D is a diagram illustrating a state in which the contact hole is formed in the manufacturing process of the semiconductor device according to the first embodiment. 図３Ｅは、第１の実施形態にかかる半導体装置の製造工程において、配線、保護膜及び透明電極を形成した状態を示す図である。FIG. 3E is a diagram illustrating a state in which the wiring, the protective film, and the transparent electrode are formed in the manufacturing process of the semiconductor device according to the first embodiment. 図４は、第２の実施形態にかかる半導体装置の概略構成を示す断面図である。FIG. 4 is a cross-sectional view illustrating a schematic configuration of the semiconductor device according to the second embodiment. 図５Ａは、第２の実施形態にかかる半導体装置の製造工程において、除去部を形成するためのレジストパターンを形成した状態を示す図である。FIG. 5A is a diagram illustrating a state in which a resist pattern for forming a removal portion is formed in the manufacturing process of the semiconductor device according to the second embodiment. 図５Ｂは、第２の実施形態にかかる半導体装置の製造工程において、除去部を形成した状態を示す図である。FIG. 5B is a diagram illustrating a state in which a removal portion is formed in the manufacturing process of the semiconductor device according to the second embodiment. 図５Ｃは、第２の実施形態にかかる半導体装置の製造工程において、コンタクトホールを形成するためのレジストパターンを形成した状態を示す図である。FIG. 5C is a diagram illustrating a state in which a resist pattern for forming a contact hole is formed in the manufacturing process of the semiconductor device according to the second embodiment. 図５Ｄは、第２の実施形態にかかる半導体装置の製造工程において、コンタクトホールを形成した状態を示す図である。FIG. 5D is a diagram illustrating a state in which contact holes are formed in the manufacturing process of the semiconductor device according to the second embodiment. 図５Ｅは、第２の実施形態にかかる半導体装置の製造工程において、配線、保護膜及び透明電極を形成した状態を示す図である。FIG. 5E is a diagram illustrating a state in which wiring, a protective film, and a transparent electrode are formed in the manufacturing process of the semiconductor device according to the second embodiment. 図６は、第３の実施形態にかかる半導体装置の概略構成を示す断面図である。FIG. 6 is a cross-sectional view illustrating a schematic configuration of the semiconductor device according to the third embodiment. 図７Ａは、第３の実施形態にかかる半導体装置の製造工程において、除去部を形成するためのレジストパターンを形成した状態を示す図である。FIG. 7A is a diagram illustrating a state in which a resist pattern for forming a removal portion is formed in the manufacturing process of the semiconductor device according to the third embodiment. 図７Ｂは、第３の実施形態にかかる半導体装置の製造工程において、除去部を形成した状態を示す図である。FIG. 7B is a diagram illustrating a state in which a removal portion is formed in the manufacturing process of the semiconductor device according to the third embodiment. 図７Ｃは、第３の実施形態にかかる半導体装置の製造工程において、コンタクトホールを形成するためのレジストパターンを形成した状態を示す図である。FIG. 7C is a diagram illustrating a state in which a resist pattern for forming a contact hole is formed in the manufacturing process of the semiconductor device according to the third embodiment. 図７Ｄは、第３の実施形態にかかる半導体装置の製造工程において、コンタクトホールを形成した状態を示す図である。FIG. 7D is a diagram illustrating a state in which contact holes are formed in the manufacturing process of the semiconductor device according to the third embodiment. 図７Ｅは、第３の実施形態にかかる半導体装置の製造工程において、配線、保護膜及び透明電極を形成した状態を示す図である。FIG. 7E is a diagram illustrating a state in which wiring, a protective film, and a transparent electrode are formed in the manufacturing process of the semiconductor device according to the third embodiment. 図８は、第４の実施形態にかかる半導体装置の概略構成を示す断面図である。FIG. 8 is a cross-sectional view showing a schematic configuration of the semiconductor device according to the fourth embodiment. 図９Ａは、第４の実施形態にかかる半導体装置の製造工程において、除去部を形成するためのレジストパターンを形成した状態を示す図である。FIG. 9A is a diagram illustrating a state in which a resist pattern for forming a removal portion is formed in the manufacturing process of the semiconductor device according to the fourth embodiment. 図９Ｂは、第４の実施形態にかかる半導体装置の製造工程において、除去部を形成した状態を示す図である。FIG. 9B is a diagram illustrating a state where a removal portion is formed in the manufacturing process of the semiconductor device according to the fourth embodiment. 図９Ｃは、第４の実施形態にかかる半導体装置の製造工程において、コンタクトホールを形成するためのレジストパターンを形成した状態を示す図である。FIG. 9C is a diagram illustrating a state in which a resist pattern for forming a contact hole is formed in the manufacturing process of the semiconductor device according to the fourth embodiment. 図９Ｄは、第４の実施形態にかかる半導体装置の製造工程において、コンタクトホールを形成した状態を示す図である。FIG. 9D is a diagram illustrating a state in which contact holes are formed in the manufacturing process of the semiconductor device according to the fourth embodiment. 図９Ｅは、第４の実施形態にかかる半導体装置の製造工程において、配線、保護膜及び透明電極を形成した状態を示す図である。FIG. 9E is a diagram illustrating a state in which the wiring, the protective film, and the transparent electrode are formed in the manufacturing process of the semiconductor device according to the fourth embodiment.
　本発明の一実施形態にかかる半導体装置の製造方法は、基板上に遮光性を有する導電層を形成する導電層形成工程と、前記基板上及び導電層上に、絶縁層を形成する絶縁層形成工程と、前記絶縁層内または該絶縁層上のいずれか一方に、島状の半導体層を形成する半導体層形成工程と、前記絶縁層のうち、前記半導体層の形成領域以外で且つ前記導電層上に位置する絶縁層の一部を除去して、絶縁層除去部を形成する絶縁層除去工程と、前記基板の上方に層間絶縁層を形成する層間絶縁層形成工程と、前記層間絶縁層の表面から前記半導体層まで延びる半導体層コンタクトホールと、前記層間絶縁層の表面から前記絶縁層除去部内を通過して前記導電層まで延びる導電層コンタクトホールと、をエッチングによって同時に形成するコンタクトホール形成工程と、を有する（第１の方法）。 A method of manufacturing a semiconductor device according to an embodiment of the present invention includes: a conductive layer forming step of forming a light-shielding conductive layer on a substrate; and an insulating layer formation for forming an insulating layer on the substrate and the conductive layer. A semiconductor layer forming step of forming an island-shaped semiconductor layer in either the insulating layer or on the insulating layer; and the conductive layer other than the region where the semiconductor layer is formed in the insulating layer. An insulating layer removing step of forming a portion of the insulating layer located above to form an insulating layer removing portion; an interlayer insulating layer forming step of forming an interlayer insulating layer above the substrate; and A contact for simultaneously forming a semiconductor layer contact hole extending from the surface to the semiconductor layer and a conductive layer contact hole extending from the surface of the interlayer insulating layer through the insulating layer removal portion to the conductive layer by etching. It has a hole formation step, a (first method).
　上記の方法によって、半導体層コンタクトホールと導電層コンタクトホールとをエッチングによって同時に形成した場合でも、半導体層の過剰なエッチングを抑制できる。すなわち、導電層コンタクトホールを形成する部分の絶縁層を予め除去しておくことで、該導電層コンタクトホールを形成する際に絶縁層をエッチングする必要がなくなり、その分、導電層コンタクトホールの形成時間を短縮できる。よって、上述の方法により、導電層コンタクトホールを形成している間に、半導体層が過剰にエッチングされて該半導体層に膜減りや突き抜けが生じるのを防止できる。 Even when the semiconductor layer contact hole and the conductive layer contact hole are simultaneously formed by etching by the above method, excessive etching of the semiconductor layer can be suppressed. That is, by removing the insulating layer in the portion where the conductive layer contact hole is to be formed in advance, it is not necessary to etch the insulating layer when forming the conductive layer contact hole. You can save time. Therefore, by the above-described method, it is possible to prevent the semiconductor layer from being excessively etched during the formation of the conductive layer contact hole, resulting in film loss or penetration of the semiconductor layer.
　前記第１の方法において、前記絶縁層は、バッファ層と該バッファ層上に形成されるゲート絶縁層とからなり、前記絶縁層除去工程では、前記導電層上に位置する前記バッファ層及びゲート絶縁層のそれぞれ一部を除去して、前記絶縁層除去部を形成するのが好ましい（第２の方法）。 In the first method, the insulating layer includes a buffer layer and a gate insulating layer formed on the buffer layer. In the insulating layer removing step, the buffer layer and the gate insulating layer located on the conductive layer are formed. It is preferable that a part of each layer is removed to form the insulating layer removal portion (second method).
　これにより、導電層コンタクトホールを形成する際に、バッファ層及びゲート絶縁層をエッチングする必要がなくなり、層間絶縁膜のみをエッチングすればよい。したがって、導電層コンタクトホールを形成する時間は、少なくとも層間絶縁層をエッチングする必要がある半導体層コンタクトホールの形成時間と同等もしくはそれよりも短くなる。よって、導電層コンタクトホール及び半導体層コンタクトホールを形成する際のエッチング時間を、該半導体層コンタクトホールの形成時間に合わせることができるため、半導体層が過剰にエッチングされるのをより確実に防止できる。 This eliminates the need to etch the buffer layer and the gate insulating layer when forming the conductive layer contact hole, and only the interlayer insulating film needs to be etched. Therefore, the time for forming the conductive layer contact hole is equal to or shorter than the time for forming the semiconductor layer contact hole in which at least the interlayer insulating layer needs to be etched. Therefore, since the etching time for forming the conductive layer contact hole and the semiconductor layer contact hole can be matched with the formation time of the semiconductor layer contact hole, it is possible to more reliably prevent the semiconductor layer from being excessively etched. .
　前記第１の方法において、前記絶縁層は、バッファ層からなり、前記絶縁層除去工程では、前記導電層上に位置する前記バッファ層の一部を除去して前記絶縁層除去部を形成するのが好ましい（第３の方法）。 In the first method, the insulating layer includes a buffer layer, and in the insulating layer removing step, a part of the buffer layer located on the conductive layer is removed to form the insulating layer removing portion. Is preferred (third method).
　この方法によっても、導電層コンタクトホールを形成する際に、バッファ層をエッチングする必要がなくなるため、その分、導電層コンタクトホールの形成時間を短縮することができる。したがって、上述の方法により、導電層コンタクトホールを形成する際に、半導体層が過剰にエッチングされるのを抑制できる。 Also by this method, it is not necessary to etch the buffer layer when forming the conductive layer contact hole, so that the time for forming the conductive layer contact hole can be shortened accordingly. Therefore, when the conductive layer contact hole is formed by the above-described method, the semiconductor layer can be prevented from being excessively etched.
　前記第２または第３の方法において、前記半導体層形成工程では、前記バッファ層とゲート絶縁層との間に前記半導体層が位置するように、該バッファ層上に半導体層を形成するのが好ましい（第４の方法）。 In the second or third method, it is preferable that in the semiconductor layer forming step, a semiconductor layer is formed on the buffer layer so that the semiconductor layer is located between the buffer layer and the gate insulating layer. (Fourth method).
　この方法により得られるスタガ型（トップゲート型）の半導体装置では、半導体層コンタクトホールを半導体層まで到達させるためには、層間絶縁膜及びゲート絶縁膜をエッチングしなければならない。このような構成の半導体装置でも、上述の第２または第３の方法を用いれば、導電層コンタクトホールを形成する際に、層間絶縁膜、または、層間絶縁膜及びゲート絶縁膜を、エッチングすればよい。そのため、導電層コンタクトホールを形成する時間は、半導体層コンタクトホールを形成する時間と同等もしくはそれ以下になる。よって、導電層コンタクトホールを形成する際に、半導体層が過剰にエッチングされるのを防止できる。 In the stagger type (top gate type) semiconductor device obtained by this method, in order to reach the semiconductor layer contact hole to the semiconductor layer, the interlayer insulating film and the gate insulating film must be etched. Even in the semiconductor device having such a configuration, when the above-described second or third method is used, the interlayer insulating film, or the interlayer insulating film and the gate insulating film are etched when the conductive layer contact hole is formed. Good. Therefore, the time for forming the conductive layer contact hole is equal to or less than the time for forming the semiconductor layer contact hole. Therefore, when the conductive layer contact hole is formed, the semiconductor layer can be prevented from being excessively etched.
　前記第２または第３の方法において、前記半導体層形成工程では、前記バッファ層上に形成されるゲート絶縁層上に、半導体層を形成するのが好ましい（第５の方法）。 In the second or third method, it is preferable that in the semiconductor layer forming step, a semiconductor layer is formed on the gate insulating layer formed on the buffer layer (fifth method).
　この方法により得られる逆スタガ型（ボトムゲート型）の半導体装置においても、上述の第２または第３の方法を用いれば、導電層コンタクトホールを形成する際にバッファ層を除去する必要がない。よって、その分、導電層コンタクトホールを形成する時間を短縮できる。よって、導電層コンタクトホールを形成する際に、半導体層が過剰にエッチングされるのを抑制できる。 Also in the inverted stagger type (bottom gate type) semiconductor device obtained by this method, if the above-described second or third method is used, it is not necessary to remove the buffer layer when forming the conductive layer contact hole. Therefore, the time for forming the conductive layer contact hole can be shortened accordingly. Therefore, when the conductive layer contact hole is formed, the semiconductor layer can be prevented from being excessively etched.
　前記第１から第５のいずれか一つの方法において、前記絶縁層上にゲート電極を形成するゲート電極形成工程をさらに備え、前記コンタクトホール形成工程では、前記層間絶縁層の表面から前記ゲート電極まで延びるゲート電極コンタクトホールも同時に形成するのが好ましい（第６の方法）。 In any one of the first to fifth methods, the method further includes a gate electrode forming step of forming a gate electrode on the insulating layer, and in the contact hole forming step, from the surface of the interlayer insulating layer to the gate electrode The extending gate electrode contact hole is preferably formed at the same time (sixth method).
　これにより、導電層コンタクトホールを形成する際に前記第１から第５の方法を適用することで、ゲート電極も過剰にエッチングされるのを防止できる。すなわち、導電層コンタクトホールが形成される絶縁層の一部を予め除去しておくことで、該導電層コンタクトホールを形成する時間を短縮することができる。よって、導電層コンタクトホールを形成する際に、ゲート電極が過剰にエッチングされるのを防止できる。 Thereby, it is possible to prevent the gate electrode from being excessively etched by applying the first to fifth methods when forming the conductive layer contact hole. That is, by removing a part of the insulating layer in which the conductive layer contact hole is formed in advance, the time for forming the conductive layer contact hole can be shortened. Therefore, it is possible to prevent the gate electrode from being excessively etched when forming the conductive layer contact hole.
　本発明の一実施形態にかかる半導体装置は、基板と、該基板上に形成された遮光性を有する導電層と、前記基板上及び導電層上に形成された絶縁層と、該絶縁層内または該絶縁層上のいずれか一方に形成された半導体層と、前記絶縁層及び半導体層を覆うように前記基板の上方に形成された層間絶縁層と、該層間絶縁層内を前記導電層及び半導体層までそれぞれ延びる配線部材と、を備え、前記絶縁層には、前記半導体層の形成領域以外で且つ前記導電層上の少なくとも一部が除去された絶縁層除去部が形成されていて、該絶縁層除去部内には、前記層間絶縁層と該層間絶縁層を貫通するように前記導電層まで延びる前記配線部材とが設けられている（第７の構成）。 A semiconductor device according to an embodiment of the present invention includes a substrate, a light-shielding conductive layer formed on the substrate, an insulating layer formed on the substrate and the conductive layer, and in the insulating layer or A semiconductor layer formed on one of the insulating layers; an interlayer insulating layer formed over the substrate so as to cover the insulating layer and the semiconductor layer; and the conductive layer and the semiconductor in the interlayer insulating layer A wiring member extending to each of the layers, and the insulating layer is formed with an insulating layer removing portion in which at least a part of the conductive layer is removed except for the region where the semiconductor layer is formed. In the layer removal portion, the interlayer insulating layer and the wiring member extending to the conductive layer so as to penetrate the interlayer insulating layer are provided (seventh configuration).
　前記第７の構成において、前記絶縁層は、バッファ層と該バッファ層上に形成されたゲート絶縁層とからなるのが好ましい（第８の構成）。 In the seventh configuration, the insulating layer preferably includes a buffer layer and a gate insulating layer formed on the buffer layer (eighth configuration).
　前記第７の構成において、前記絶縁層は、バッファ層からなり、前記半導体層は、前記バッファ層の上方に形成されているのが好ましい（第９の構成）。 In the seventh configuration, it is preferable that the insulating layer includes a buffer layer, and the semiconductor layer is formed above the buffer layer (a ninth configuration).
　前記第８または第９の構成において、前記半導体層は、前記バッファ層と該バッファ層上に形成されたゲート絶縁層との間に位置するように、該バッファ層上に設けられているのが好ましい（第１０の構成）。 In the eighth or ninth configuration, the semiconductor layer is provided on the buffer layer so as to be positioned between the buffer layer and a gate insulating layer formed on the buffer layer. Preferred (tenth configuration).
　前記第８または第９の構成において、前記半導体層は、前記バッファ層上に形成されたゲート絶縁層上に設けられているのが好ましい（第１１の構成）。 In the eighth or ninth configuration, the semiconductor layer is preferably provided on a gate insulating layer formed on the buffer layer (11th configuration).
　以下、本発明の半導体装置の好ましい実施形態について、図面を参照しながら説明する。なお、各図中の構成部材の寸法は、実際の構成部材の寸法及び各構成部材の寸法比率等を忠実に表したものではない。 Hereinafter, preferred embodiments of the semiconductor device of the present invention will be described with reference to the drawings. In addition, the dimension of the structural member in each figure does not represent the dimension of an actual structural member, the dimension ratio of each structural member, etc. faithfully.
　［第１の実施形態］
　図１に、第１の実施形態にかかる半導体装置１を備えた液晶表示装置の表示パネル２の概略構成を示す。すなわち、本実施形態にかかる半導体装置１は、例えば、液晶表示装置の表示パネル２を構成するアクティブマトリクス基板３などに用いられる。 [First Embodiment]
FIG. 1 shows a schematic configuration of a display panel 2 of a liquid crystal display device including the semiconductor device 1 according to the first embodiment. That is, the semiconductor device 1 according to the present embodiment is used for, for example, an active matrix substrate 3 constituting a display panel 2 of a liquid crystal display device.
　表示パネル２は、アクティブマトリクス基板３と、対向基板４と、それらの間に挟みこまれる液晶層（図示省略）とを備えている。なお、表示パネル２には、液晶表示装置の図示しないバックライト装置から光が照射される。 The display panel 2 includes an active matrix substrate 3, a counter substrate 4, and a liquid crystal layer (not shown) sandwiched between them. The display panel 2 is irradiated with light from a backlight device (not shown) of the liquid crystal display device.
　アクティブマトリクス基板３は、多くの画素がマトリクス状に形成された基板３０を備えている。また、アクティブマトリクス基板３には、各画素に対応して画素電極や薄膜トランジスタ（ＴＥＴ：Ｔｈｉｎ　Ｆｉｌｍ　Ｔｒａｎｓｉｓｔｏｒ、以下、“ＴＦＴ”と呼ぶ）が設けられている。一方、対向基板４は、画素電極に対向する対向電極と、着色層を有するカラーフィルタと、を備えている。 The active matrix substrate 3 includes a substrate 30 on which many pixels are formed in a matrix. The active matrix substrate 3 is provided with pixel electrodes and thin film transistors (TET: Thin Film Transistor, hereinafter referred to as “TFT”) corresponding to each pixel. On the other hand, the counter substrate 4 includes a counter electrode facing the pixel electrode and a color filter having a colored layer.
　前記液晶表示装置は、アクティブマトリクス基板３のＴＦＴを、該アクティブマトリクス基板３に設けられたドライバ５からの信号に応じて駆動させることにより、液晶層内の液晶を制御し、表示パネル２に画像を表示するように構成されている。 The liquid crystal display device controls the liquid crystal in the liquid crystal layer by driving the TFT of the active matrix substrate 3 in accordance with a signal from the driver 5 provided on the active matrix substrate 3, and displays an image on the display panel 2. Is configured to display.
　図２に、本実施形態にかかる半導体装置１の概略構成を示す。この半導体装置１では、基板３０上にＴＦＴ１０が形成されていて、該基板３０とＴＦＴ１０との間に遮光膜２０（遮光性を有する導電層）が形成されている。この遮光膜２０は、バックライト装置の照明光が、ＴＦＴ１０に入力されるのを防止するためのものである。また、基板３０は、例えばアクティブマトリクス基板３を構成する透光性のガラス基板である。なお、断面を示す全ての図（図２も含む）において、図中の導体及び半導体のみにハッチングが施されている。 FIG. 2 shows a schematic configuration of the semiconductor device 1 according to the present embodiment. In the semiconductor device 1, the TFT 10 is formed on the substrate 30, and a light shielding film 20 (light-shielding conductive layer) is formed between the substrate 30 and the TFT 10. The light shielding film 20 is for preventing illumination light of the backlight device from being input to the TFT 10. The substrate 30 is a translucent glass substrate constituting the active matrix substrate 3, for example. In all the drawings showing the cross section (including FIG. 2), only conductors and semiconductors in the drawing are hatched.
　ＴＦＴ１０は、基板３０上に設けられた遮光膜２０の上方に形成されている。すなわち、基板３０上には、遮光膜２０が島状に形成されていて、該基板３０及び遮光膜２０を覆うようにバッファ膜２１が形成されている。遮光膜２０は、タンタル（Ｔａ）またはチタン（Ｔｉ）、タングステン（Ｗ）、モリブデン（Ｍｏ）、アルミニウム（Ａｌ）等を主成分とする金属膜（例えば、Ｍｏ、Ｗ／ＴａＮ、ＭｏＷ、Ｔｉ／Ａｌなど）からなる。また、バッファ膜２１（絶縁層、バッファ層）は、ＳｉＯ２／ＳｉＮＯまたはＳｉＯ２、ＳｉＮ等のシリコン酸化物やシリコン窒化物などからなる。 The TFT 10 is formed above the light shielding film 20 provided on the substrate 30. That is, the light shielding film 20 is formed in an island shape on the substrate 30, and the buffer film 21 is formed so as to cover the substrate 30 and the light shielding film 20. The light shielding film 20 is a metal film (for example, Mo, W / TaN, MoW, Ti / Ti) containing tantalum (Ta) or titanium (Ti), tungsten (W), molybdenum (Mo), aluminum (Al), or the like as a main component. Al). The buffer film 21 (insulating layer, buffer layer) is made of silicon oxide such as SiO 2 / SiNO or SiO 2 , SiN, silicon nitride, or the like.
　ＴＦＴ１０は、バッファ膜２１上に形成された島状のシリコン膜１１（半導体層）を有している。このシリコン膜１１には、特に図示しないが、チャネル領域と該チャンネル領域を挟むように２つの半導体領域とが面方向に並んで形成されている。シリコン膜１１は、連続粒界シリコン（ＣＧＳ：Ｃｏｎｔｉｎｕｏｕｓ　Ｇｒａｉｎ　Ｓｉｌｉｃｏｎ）や低温ポリシリコン（ＬＰＳ：Ｌｏｗ－ｔｅｍｐｅｒａｔｕｒｅ　Ｐｏｌｙ－ｓｉｌｉｃｏｎ）等の多結晶シリコン、α－Ｓｉなどからなる。 The TFT 10 has an island-shaped silicon film 11 (semiconductor layer) formed on the buffer film 21. Although not specifically shown, the silicon film 11 is formed with a channel region and two semiconductor regions arranged in a plane so as to sandwich the channel region. The silicon film 11 is made of polycrystalline silicon such as continuous grain boundary silicon (CGS) or low-temperature poly-silicon (LPS), α-Si, or the like.
　シリコン膜１１には、配線１２，１３（配線部材）が接続されている。配線１２は、ソース電極３１に接続されている。一方、配線１３は、透明電極２５に接続されている。ソース電極３１は、Ｔｉ／Ａｌ／ＴｉまたはＴｉ／Ａｌ、ＴｉＮ／Ａｌ／ＴｉＮ、Ｍｏ／Ａｌ-Ｎｄ／Ｍｏ、Ｍｏ／Ａｌ／Ｍｏ等の金属材料からなる。透明電極２５は、ＩＴＯやＺｎＯなどの材料からなる。 Wires 12 and 13 (wiring members) are connected to the silicon film 11. The wiring 12 is connected to the source electrode 31. On the other hand, the wiring 13 is connected to the transparent electrode 25. The source electrode 31 is made of a metal material such as Ti / Al / Ti or Ti / Al, TiN / Al / TiN, Mo / Al—Nd / Mo, or Mo / Al / Mo. The transparent electrode 25 is made of a material such as ITO or ZnO.
　バッファ膜２１上には、該バッファ膜２１及びシリコン膜１１を覆うようにゲート絶縁膜２２（絶縁層、ゲート絶縁層）が形成されている。ゲート絶縁膜２２は、ＳｉＯ２またはＳｉＮ、ＳｉＮ／ＳｉＯ２等のシリコン酸化物やシリコン窒化物などからなる。なお、この実施形態において、バッファ膜２１及びゲート絶縁膜２２が、絶縁層に対応する。 On the buffer film 21, a gate insulating film 22 (insulating layer, gate insulating layer) is formed so as to cover the buffer film 21 and the silicon film 11. The gate insulating film 22 is made of SiO 2 or SiN, silicon oxide or silicon nitride such SiN / SiO 2. In this embodiment, the buffer film 21 and the gate insulating film 22 correspond to an insulating layer.
　ゲート絶縁膜２２上には、ＴＦＴ１０のゲート電極１４が設けられている。ゲート電極１４は、Ｗ／ＴａＮまたはＭｏ、ＭｏＷ、Ｔｉ／Ａｌなどの金属材料からなる。ゲート電極１４には、配線１５（配線部材）が接続されている。なお、図２に示す断面では、右側のゲート電極１４に配線１５が接続されている状態は示されていないが、この図２の左側に一例を示すように、図２とは異なる断面において、ゲート電極１４に配線１５が接続されている。 The gate electrode 14 of the TFT 10 is provided on the gate insulating film 22. The gate electrode 14 is made of a metal material such as W / TaN or Mo, MoW, Ti / Al. A wiring 15 (wiring member) is connected to the gate electrode 14. In the cross section shown in FIG. 2, the state in which the wiring 15 is connected to the gate electrode 14 on the right side is not shown, but as shown on the left side of FIG. A wiring 15 is connected to the gate electrode 14.
　また、ゲート絶縁膜２２上には、該ゲート絶縁膜２２及びゲート電極１４を覆うように層間絶縁膜２３（層間絶縁層）が形成されている。この層間絶縁膜２３上には、樹脂製の保護膜２４が形成されている。 Further, an interlayer insulating film 23 (interlayer insulating layer) is formed on the gate insulating film 22 so as to cover the gate insulating film 22 and the gate electrode 14. A resin protective film 24 is formed on the interlayer insulating film 23.
　上述のような構成のＴＦＴ１０が形成されている領域以外で、遮光膜２０に配線３２（配線部材）が接続されている。この配線３２は、特に図示しないが、ソース電極３１に接続されている。よって、遮光膜２０は、配線３２を介してソース電極３１によって電位が調整される。これにより、遮光膜２０の電位を調整して、ＴＦＴ１０と遮光膜２０との間に存在する寄生容量による影響を低減することが可能となる。 The wiring 32 (wiring member) is connected to the light shielding film 20 outside the region where the TFT 10 having the above-described configuration is formed. The wiring 32 is connected to the source electrode 31 although not particularly shown. Therefore, the potential of the light shielding film 20 is adjusted by the source electrode 31 through the wiring 32. As a result, the potential of the light shielding film 20 can be adjusted to reduce the influence of parasitic capacitance existing between the TFT 10 and the light shielding film 20.
　なお、配線３２は、本実施形態ではソース電極３１に接続されているが、他の配線に接続されていてもよい。 The wiring 32 is connected to the source electrode 31 in this embodiment, but may be connected to other wiring.
　図２に示すように、遮光膜２０上に形成されたバッファ膜２１及びゲート絶縁膜２２のうち、配線３２と遮光膜２０との接続部分を囲む部分には、バッファ膜２１及びゲート絶縁膜２２が除去された除去部４０（絶縁層除去部）が形成されている。すなわち、配線３２との接続部分の周囲の遮光膜２０上には、バッファ膜２１やゲート絶縁膜２２が形成されておらず、層間絶縁膜２３のみが形成されている。 As shown in FIG. 2, in the buffer film 21 and the gate insulating film 22 formed on the light shielding film 20, the buffer film 21 and the gate insulating film 22 are surrounded by a portion surrounding the connection portion between the wiring 32 and the light shielding film 20. The removal part 40 (insulating layer removal part) from which the is removed is formed. That is, the buffer film 21 and the gate insulating film 22 are not formed on the light shielding film 20 around the connection portion with the wiring 32, and only the interlayer insulating film 23 is formed.
　（半導体装置の製造方法）
　次に、上述の構成を有する半導体装置１の製造方法を、図３Ａ～図３Ｅを用いて説明する。これらの図は、この実施形態における半導体装置１の製造工程を示す断面図である。 (Method for manufacturing semiconductor device)
Next, a method for manufacturing the semiconductor device 1 having the above-described configuration will be described with reference to FIGS. 3A to 3E. These drawings are cross-sectional views showing the manufacturing process of the semiconductor device 1 in this embodiment.
　最初に、図３Ａに示すように、基板３０上に、バックライト装置の照明光が該基板３０の一面側（図の下側）からＴＦＴ１０に入射するのを防止するための遮光膜２０を形成する。 First, as shown in FIG. 3A, a light shielding film 20 is formed on the substrate 30 to prevent the illumination light of the backlight device from entering the TFT 10 from one surface side (the lower side in the figure) of the substrate 30. To do.
　具体的には、まず、基板３０の一方の面（図の上面）に、ＣＶＤ（Ｃｈｅｍｉｃａｌ　Ｖａｐｏｒ　Ｄｅｐｏｓｉｔｉｏｎ）法やスパッタ法等によって、厚さが約３０ｎｍ～３００ｎｍの遮光薄膜を形成する。その後、フォトリソグラフィ法によって、遮光膜２０を形成する予定の領域（以下、形成予定領域という）を覆うレジストパターンを形成し、これをマスクとして、前記遮光薄膜をエッチングする。これにより、遮光膜２０が得られる。なお、本実施形態では、遮光膜２０は、例えばＭｏからなる。 Specifically, first, a light-shielding thin film having a thickness of about 30 nm to 300 nm is formed on one surface (upper surface in the drawing) of the substrate 30 by a CVD (Chemical Vapor Deposition) method, a sputtering method, or the like. Thereafter, a resist pattern is formed by photolithography to cover a region where the light shielding film 20 is to be formed (hereinafter referred to as a region to be formed), and the light shielding thin film is etched using this resist pattern as a mask. Thereby, the light shielding film 20 is obtained. In the present embodiment, the light shielding film 20 is made of, for example, Mo.
　続いて、基板３０及び遮光膜２０を覆うようにバッファ膜２１を形成する。このバッファ膜２１は、例えばＳｉＮＯ／ＳｉＯ２の積層膜からなる。バッファ膜２１は、ＣＶＤ法によって厚みが約１００ｎｍ～４００ｎｍに形成される。 Subsequently, a buffer film 21 is formed so as to cover the substrate 30 and the light shielding film 20. The buffer film 21 is made of, for example, a laminated film of SiNO / SiO 2 . The buffer film 21 is formed with a thickness of about 100 nm to 400 nm by a CVD method.
　次に、バッファ膜２１上に、例えばＣＧＳからなるシリコン薄膜をＣＶＤ法によって形成する。このシリコン薄膜は、厚みが３０ｎｍ～１００ｎｍになるように形成される。その後、フォトリソグラフィ法によって、シリコン膜１１の形成予定領域を覆うレジストパターンを形成し、これをマスクとしてシリコン薄膜をエッチングする。これにより、シリコン膜１１が得られる。このシリコン膜１１は、イオン注入等によりドープされ、該シリコン膜１１にソース領域及びドレイン領域（図示省略）が形成される。 Next, a silicon thin film made of, for example, CGS is formed on the buffer film 21 by a CVD method. This silicon thin film is formed to have a thickness of 30 nm to 100 nm. Thereafter, a resist pattern that covers a region where the silicon film 11 is to be formed is formed by photolithography, and the silicon thin film is etched using the resist pattern as a mask. Thereby, the silicon film 11 is obtained. The silicon film 11 is doped by ion implantation or the like, and a source region and a drain region (not shown) are formed in the silicon film 11.
　バッファ膜２１上及びシリコン膜１１上に、例えばＳｉＯ２からなるゲート絶縁膜２２をＣＶＤ法によって形成する。このゲート絶縁膜２２は、厚みが５０ｎｍ～２００ｎｍになるように形成される。 A gate insulating film 22 made of, for example, SiO 2 is formed on the buffer film 21 and the silicon film 11 by a CVD method. The gate insulating film 22 is formed to have a thickness of 50 nm to 200 nm.
　その後、ゲート絶縁膜２２上に、例えばＷ／ＴａＮからなる金属膜をスパッタ法によって形成する。この金属膜は、厚みが２００ｎｍ～５００ｎｍになるように形成される。その後、フォトリソグラフィ法によって、ゲート電極１４の形成予定領域を覆うレジストパターンを形成し、これをマスクとして金属膜をエッチングする。これにより、ゲート電極１４が得られる。 Thereafter, a metal film made of, for example, W / TaN is formed on the gate insulating film 22 by a sputtering method. This metal film is formed to have a thickness of 200 nm to 500 nm. Thereafter, a resist pattern that covers a region where the gate electrode 14 is to be formed is formed by photolithography, and the metal film is etched using the resist pattern as a mask. Thereby, the gate electrode 14 is obtained.
　そして、遮光膜２０の上方で且つシリコン膜１１が形成されている領域以外の部分で開口するように、ゲート絶縁膜２２上及びゲート電極１４上にレジストパターン４１を形成する。すなわち、レジストパターン４１は、ゲート絶縁膜２２における除去部４０の形成予定領域を露出させるような開口を有している。 Then, a resist pattern 41 is formed on the gate insulating film 22 and the gate electrode 14 so as to be opened above the light shielding film 20 and in a portion other than the region where the silicon film 11 is formed. That is, the resist pattern 41 has an opening that exposes a region where the removal portion 40 is to be formed in the gate insulating film 22.
　次に、図３Ｂに示すように、レジストパターン４１をマスクとしてゲート絶縁膜２２及びバッファ膜２１をエッチングする。このとき、該ゲート絶縁膜２２及びバッファ膜２１を、遮光膜２０が露出するまでエッチングを行う。これにより、遮光膜２０の一部の上方に位置するゲート絶縁膜２２及びバッファ膜２１が除去されて、除去部４０が形成される。 Next, as shown in FIG. 3B, the gate insulating film 22 and the buffer film 21 are etched using the resist pattern 41 as a mask. At this time, the gate insulating film 22 and the buffer film 21 are etched until the light shielding film 20 is exposed. As a result, the gate insulating film 22 and the buffer film 21 located above a part of the light shielding film 20 are removed, and the removal portion 40 is formed.
　なお、図３Ｂにおけるエッチングは、バッファードフッ酸（ＢＨＦ：Ｂｕｆｆｅｒｅｄ　Ｈｙｄｒｏｇｅｎ　Ｆｌｕｏｒｉｄｅ）を用いたウェットエッチングや、エッチングガス（Ｃ４Ｆ８、ＳＦ６、ＣＦ４、Ｏ２、Ａｒ、Ｈ２等）を用いたドライエッチングでもよい。また、これらのウェットエッチングとドライエッチングとを組み合わせた手法であってもよい。 3B is performed by wet etching using buffered hydrofluoric acid (BHF) or etching gas (C 4 F 8 , SF 6 , CF 4 , O 2 , Ar, H 2, etc.). The dry etching used may be used. Moreover, the method which combined these wet etching and dry etching may be used.
　レジストパターン４１を除去した後、図３Ｃに示すように、ゲート絶縁膜２２上、ゲート電極１４上及び除去部４０上に、例えばＳｉＯ２／ＳｉＮの積層膜からなる層間絶縁膜２３をＣＶＤ法によって形成する。その後、層間絶縁膜２３上に、配線１５，３２，１３，１２が形成されるコンタクトホール４３～４６の形成予定領域を露出させるような開口を有するレジストパターン４２を形成する。 After removing the resist pattern 41, as shown in FIG. 3C, an interlayer insulating film 23 made of, for example, a laminated film of SiO 2 / SiN is formed on the gate insulating film 22, the gate electrode 14, and the removal portion 40 by a CVD method. Form. Thereafter, a resist pattern 42 is formed on the interlayer insulating film 23. The resist pattern 42 has an opening that exposes regions where the contact holes 43 to 46 where the wirings 15, 32, 13, and 12 are to be formed are exposed.
　なお、図３Ｄに示すように、配線１２，１３が形成されるコンタクトホール４６，４５（半導体層コンタクトホール）の形成予定領域は、平面視（図の上方から見て）でシリコン膜１１上に位置している。配線１５が形成されるコンタクトホール４３（ゲート電極コンタクトホール）の形成予定領域は、平面視（図の上方から見て）でゲート電極１４上に位置している。配線３２が形成されるコンタクトホール４４（導電層コンタクトホール）の形成予定領域は、平面視（図の上方から見て）で除去部４０内に位置している。 As shown in FIG. 3D, regions where the contact holes 46 and 45 (semiconductor layer contact holes) where the wirings 12 and 13 are to be formed are formed on the silicon film 11 in plan view (viewed from above). positioned. A region where a contact hole 43 (gate electrode contact hole) in which the wiring 15 is to be formed is located on the gate electrode 14 in plan view (viewed from above). A region in which the contact hole 44 (conductive layer contact hole) where the wiring 32 is to be formed is located in the removal portion 40 in plan view (viewed from above in the drawing).
　続いて、図３Ｄに示すように、レジストパターン４２をマスクとして層間絶縁膜２３及びゲート絶縁膜２２をエッチングする。これにより、層間絶縁膜２３の表面から、それぞれ、ゲート電極１４、遮光膜２０及びシリコン膜１１まで延びるコンタクトホール４３～４６が形成される。このときのエッチングは、エッチングガスを用いたドライエッチングが好ましい。なお、全てのエッチングをドライエッチングで行うのではなく、大部分をドライエッチングで行った後、ウェットエッチングを行うようにしてもよい。 Subsequently, as shown in FIG. 3D, the interlayer insulating film 23 and the gate insulating film 22 are etched using the resist pattern 42 as a mask. Thus, contact holes 43 to 46 extending from the surface of the interlayer insulating film 23 to the gate electrode 14, the light shielding film 20, and the silicon film 11 are formed. The etching at this time is preferably dry etching using an etching gas. Note that not all etching is performed by dry etching, but wet etching may be performed after most of the etching is performed by dry etching.
　配線３２が形成されるコンタクトホール４４の形成予定領域では、バッファ膜２１及びゲート絶縁膜２２が除去されていて、層間絶縁膜２３のみが形成されている。そのため、エッチングが必要な膜厚は、シリコン膜１１に接続される配線１２，１３のコンタクトホール４５，４６の形成予定領域が最も厚くなっている。すなわち、配線１５，３２のコンタクトホール４３，４４の形成予定領域では、層間絶縁膜２３のみをエッチングすればよいのに対し、配線１３，１２のコンタクトホール４５，４６の形成予定領域では、層間絶縁膜２３及びゲート絶縁膜２２をエッチングする必要がある。したがって、コンタクトホール４５，４６の形成予定領域のエッチング時間を基準にして、コンタクトホール４３～４６の形成予定領域を一度にエッチングすることができる。よって、図３Ｄのエッチングの際に、シリコン膜１１が過剰にエッチングされるのを防止できる。さらに、配線１５，３２のコンタクトホール４３，４４の形成予定領域は、層間絶縁膜２３の厚みがほぼ同じであるため、コンタクトホール４３，４４の形成予定領域を同時にエッチングする際に、ゲート電極１４が過剰にエッチングされるのを防止できる。 In the region where the contact hole 44 is to be formed where the wiring 32 is to be formed, the buffer film 21 and the gate insulating film 22 are removed, and only the interlayer insulating film 23 is formed. For this reason, the film thickness that needs to be etched is the thickest in the regions where the contact holes 45 and 46 of the wirings 12 and 13 connected to the silicon film 11 are to be formed. That is, in the regions where the contact holes 43 and 44 of the wirings 15 and 32 are to be formed, only the interlayer insulating film 23 needs to be etched, whereas in the regions where the contact holes 45 and 46 of the wirings 13 and 12 are to be formed, interlayer insulation is performed. It is necessary to etch the film 23 and the gate insulating film 22. Therefore, the regions where the contact holes 43 to 46 are to be formed can be etched at a time based on the etching time of the regions where the contact holes 45 and 46 are to be formed. Therefore, it is possible to prevent the silicon film 11 from being excessively etched during the etching shown in FIG. 3D. Further, since the regions where the contact holes 43 and 44 of the wirings 15 and 32 are to be formed have substantially the same thickness of the interlayer insulating film 23, the gate electrode 14 is formed when the regions where the contact holes 43 and 44 are to be formed are etched simultaneously. Can be prevented from being excessively etched.
　レジストパターン４２を除去した後、図３Ｅに示すように、コンタクトホール４３～４６内に配線１２，１３，１５，３２を形成するとともに、ソース電極３１を形成する。そして、層間絶縁膜２３上に保護膜２４及び透明電極２５を形成する。これにより、半導体装置１が形成される。 After removing the resist pattern 42, as shown in FIG. 3E, wirings 12, 13, 15, and 32 are formed in the contact holes 43 to 46, and a source electrode 31 is formed. Then, a protective film 24 and a transparent electrode 25 are formed on the interlayer insulating film 23. Thereby, the semiconductor device 1 is formed.
　ここで、基板３０上に遮光膜２０を形成する工程が導電層形成工程に、該基板３０上及び遮光膜２０上にバッファ膜２１及びゲート絶縁膜２２を形成する工程が絶縁層形成工程に、それぞれ対応する。また、バッファ膜２１上にシリコン膜１１を形成する工程が半導体層形成工程に、ゲート絶縁膜２２上にゲート電極１４を形成する工程がゲート電極形成工程に、それぞれ対応する。 Here, the step of forming the light shielding film 20 on the substrate 30 is a conductive layer forming step, and the step of forming the buffer film 21 and the gate insulating film 22 on the substrate 30 and the light shielding film 20 is an insulating layer forming step. Each corresponds. The step of forming the silicon film 11 on the buffer film 21 corresponds to the semiconductor layer forming step, and the step of forming the gate electrode 14 on the gate insulating film 22 corresponds to the gate electrode forming step.
　さらに、遮光膜２０の一部の上方に位置するバッファ膜２１及びゲート絶縁膜２２を除去して除去部４０を形成する工程が絶縁層除去工程に、層間絶縁層２３を形成する工程が層間絶縁層形成工程に、それぞれ対応する。また、コンタクトホール４３～４６を形成する工程がコンタクトホール形成工程に対応する。 Further, the step of forming the removal portion 40 by removing the buffer film 21 and the gate insulating film 22 located above a part of the light shielding film 20 is the insulating layer removing step, and the step of forming the interlayer insulating layer 23 is the interlayer insulation. Each corresponds to the layer forming step. Further, the process of forming the contact holes 43 to 46 corresponds to the contact hole forming process.
　（第１の実施形態の効果）
　本実施形態では、配線３２が遮光膜２０に接続される部分において、該遮光膜２０上に形成されたバッファ膜２１及びゲート絶縁膜２２を除去した後、層間絶縁膜２３を形成した。そして、複数のコンタクトホール４３～４６の形成予定領域を同時にエッチングするようにした。これにより、複数のコンタクトホール４３～４６の形成予定領域を同時にエッチングする際に、配線３２のコンタクトホール４４の形成予定領域において、バッファ膜２１及びゲート絶縁膜２２をエッチングする必要がなくなる。よって、その分、エッチングする時間が短くなるため、複数のコンタクトホール４３～４６の形成予定領域を同時にエッチングする際に、配線１３，１２のコンタクトホール４５，４６の形成予定領域でシリコン膜１１が過剰にエッチングされるのを防止できる。 (Effects of the first embodiment)
In the present embodiment, the interlayer insulating film 23 is formed after removing the buffer film 21 and the gate insulating film 22 formed on the light shielding film 20 in the portion where the wiring 32 is connected to the light shielding film 20. Then, the regions where the plurality of contact holes 43 to 46 are to be formed are etched simultaneously. This eliminates the need to etch the buffer film 21 and the gate insulating film 22 in the region where the contact hole 44 is to be formed in the wiring 32 when simultaneously etching the region where the plurality of contact holes 43 to 46 are to be formed. Therefore, since the etching time is shortened accordingly, the silicon film 11 is formed in the formation regions of the contact holes 45 and 46 of the wirings 13 and 12 when simultaneously etching the formation regions of the contact holes 43 to 46. Excessive etching can be prevented.
　特に、本実施形態におけるＴＦＴ１０は、シリコン膜１１がバッファ膜２１とゲート絶縁膜２２との間に位置し、且つ、該ゲート絶縁膜２２上にゲート電極１４が形成された、いわゆるトップゲート型のＴＦＴである。そのため、エッチングが必要な膜厚は、シリコン膜１１に接続される配線１２，１３のコンタクトホール４５，４６の形成予定領域で最も厚くなる。よって、コンタクトホール４５，４６の形成予定領域をエッチングする時間に合わせて、他のコンタクトホール４３，４４の形成予定領域をエッチングすることができるため、エッチングによってシリコン膜１１に膜減りや突き抜けが生じるのをより確実に防止できる。 In particular, the TFT 10 in this embodiment is a so-called top gate type in which the silicon film 11 is located between the buffer film 21 and the gate insulating film 22 and the gate electrode 14 is formed on the gate insulating film 22. TFT. Therefore, the film thickness that needs to be etched is the thickest in the regions where the contact holes 45 and 46 of the wirings 12 and 13 connected to the silicon film 11 are to be formed. Therefore, since the regions where the other contact holes 43 and 44 are to be formed can be etched in accordance with the time for etching the regions where the contact holes 45 and 46 are to be formed, the silicon film 11 is reduced or penetrated by the etching. Can be more reliably prevented.
　さらに、ゲート電極１４に接続される配線１５のコンタクトホール４３の形成予定領域と、遮光膜２０に接続される配線３２のコンタクトホール４４の形成予定領域とは、エッチングされる層間絶縁膜２３の厚みがほぼ同じである。そのため、複数のコンタクトホール４３～４６の形成予定領域を同時にエッチングする際に、ゲート電極１４が過剰にエッチングされるのを防止できる。 Further, the region where the contact hole 43 is to be formed in the wiring 15 connected to the gate electrode 14 and the region where the contact hole 44 is to be formed in the wiring 32 connected to the light shielding film 20 are the thickness of the interlayer insulating film 23 to be etched. Are almost the same. Therefore, it is possible to prevent the gate electrode 14 from being excessively etched when simultaneously forming the regions where the plurality of contact holes 43 to 46 are to be formed.
　［第２の実施形態］
　図４に、第２の実施形態にかかる半導体装置５０の概略構成を示す。この実施形態は、除去部７０の構成及び半導体装置５０の製造方法が第１の実施形態とは異なる。以下の説明において、実施形態１と同一の構成には同一の符号を付し、異なる部分についてのみ説明する。 [Second Embodiment]
FIG. 4 shows a schematic configuration of a semiconductor device 50 according to the second embodiment. This embodiment is different from the first embodiment in the configuration of the removal unit 70 and the method for manufacturing the semiconductor device 50. In the following description, the same components as those in the first embodiment are denoted by the same reference numerals, and only different portions will be described.
　具体的には、この実施形態では、除去部７０（絶縁層除去部）はバッファ膜５１（絶縁層、バッファ層）のみに形成されている。すなわち、配線３２との接続部分の周囲の遮光膜２０上には、ゲート絶縁膜５２（ゲート絶縁層）が形成されていて、該ゲート絶縁膜５２上に層間絶縁膜５３（層間絶縁層）が形成されている。 Specifically, in this embodiment, the removal portion 70 (insulating layer removal portion) is formed only in the buffer film 51 (insulating layer, buffer layer). That is, a gate insulating film 52 (gate insulating layer) is formed on the light shielding film 20 around the connection portion with the wiring 32, and an interlayer insulating film 53 (interlayer insulating layer) is formed on the gate insulating film 52. Is formed.
　このような構成により、配線３２のコンタクトホール４４の形成予定領域にバッファ膜５１が存在しない分、該形成予定領域をエッチングする際の時間が短くなる。よって、配線１５，３２，１３，１２のコンタクトホール４３～４６の形成予定領域を同時にエッチングする際に、配線１２，１３に接続されるシリコン膜１１及び配線１５に接続されるゲート電極１４が過剰にエッチングされるのを抑制することができる。 This configuration shortens the time required for etching the formation region because the buffer film 51 does not exist in the formation region of the contact hole 44 of the wiring 32. Therefore, when the regions where the contact holes 43 to 46 of the wirings 15, 32, 13 and 12 are to be formed are etched simultaneously, the silicon film 11 connected to the wirings 12 and 13 and the gate electrode 14 connected to the wiring 15 are excessive. Etching can be suppressed.
　（半導体装置の製造方法）
　次に、この第２の実施形態における半導体装置５０の製造方法を、主に第１の実施形態と異なる部分について、図５Ａ～図５Ｅを用いて説明する。これらの図は、この実施形態における半導体装置５０の製造工程を示す断面図である。なお、半導体装置５０を構成する各膜の材料や製造方法は、第１の実施形態と同様である。 (Method for manufacturing semiconductor device)
Next, a method for manufacturing the semiconductor device 50 according to the second embodiment will be described with reference to FIGS. 5A to 5E, mainly on portions different from the first embodiment. These drawings are cross-sectional views showing the manufacturing process of the semiconductor device 50 in this embodiment. The material and manufacturing method of each film constituting the semiconductor device 50 are the same as those in the first embodiment.
　最初に、第１の実施形態と同様、図５Ａに示すように、基板３０上に、バックライト装置の照明光が該基板３０の一面側（図の下側）からＴＦＴ６０に入射するのを防止するための遮光膜２０を形成する。その後、基板３０及び遮光膜２０を覆うようにバッファ膜５１を形成する。そして、第１の実施形態と同様、バッファ膜５１上に、シリコン膜１１を形成する。 First, as in the first embodiment, as shown in FIG. 5A, the illumination light of the backlight device is prevented from being incident on the TFT 60 from one surface side (the lower side of the drawing) of the substrate 30 on the substrate 30. A light shielding film 20 is formed. Thereafter, a buffer film 51 is formed so as to cover the substrate 30 and the light shielding film 20. Then, the silicon film 11 is formed on the buffer film 51 as in the first embodiment.
　次に、フォトリソグラフィ法によって、遮光膜２０の上方で且つシリコン膜１１が形成されている領域以外の部分で開口するように、バッファ膜５１上及びシリコン膜１１上にレジストパターン７１を形成する。すなわち、レジストパターン７１は、バッファ膜５１における除去部７０の形成予定領域を露出させるような開口を有している。 Next, a resist pattern 71 is formed on the buffer film 51 and the silicon film 11 by photolithography so as to be opened above the light shielding film 20 and in a portion other than the region where the silicon film 11 is formed. That is, the resist pattern 71 has an opening that exposes a region where the removal portion 70 is to be formed in the buffer film 51.
　図５Ｂに示すように、レジストパターン７１をマスクとしてバッファ膜５１をエッチングする。このとき、該バッファ膜５１を、遮光膜２０が露出するまでエッチングを行う。これにより、遮光膜２０の一部の上方に位置するバッファ膜５１が除去されて、除去部７０が形成される。 As shown in FIG. 5B, the buffer film 51 is etched using the resist pattern 71 as a mask. At this time, the buffer film 51 is etched until the light shielding film 20 is exposed. As a result, the buffer film 51 located above a part of the light shielding film 20 is removed, and the removal portion 70 is formed.
　なお、図５Ｂにおけるエッチングは、第１の実施形態と同様、ウェットエッチングやドライエッチングでもよい。また、これらのウェットエッチングとドライエッチングとを組み合わせた手法であってもよい。 Note that the etching in FIG. 5B may be wet etching or dry etching, as in the first embodiment. Moreover, the method which combined these wet etching and dry etching may be used.
　レジストパターン７１を除去した後、図５Ｃに示すように、バッファ膜５１上及びシリコン膜１１上に、第１の実施形態と同様のゲート絶縁膜５２を形成し、該ゲート絶縁膜５２上にゲート電極１４を形成する。その後、層間絶縁膜５３を形成し、該層間絶縁膜５３上に、配線１５，３２，１３，１２が形成されるコンタクトホール４３～４６の形成予定領域を露出させるような開口を有するレジストパターン７２を形成する。 After removing the resist pattern 71, as shown in FIG. 5C, a gate insulating film 52 similar to that of the first embodiment is formed on the buffer film 51 and the silicon film 11, and a gate is formed on the gate insulating film 52. The electrode 14 is formed. Thereafter, an interlayer insulating film 53 is formed, and a resist pattern 72 having an opening that exposes regions where the contact holes 43 to 46 in which the wirings 15, 32, 13, and 12 are formed is exposed on the interlayer insulating film 53. Form.
　なお、図５Ｄに示すように、配線１３，１２が形成されるコンタクトホール４５，４６の形成予定領域は、平面視（図の上方から見て）でシリコン膜１１上に位置している。配線１５が形成されるコンタクトホール４３の形成予定領域は、平面視（図の上方から見て）でゲート電極１４上に位置している。配線３２が形成されるコンタクトホール４４の形成予定領域は、平面視（図の上方から見て）で除去部７０内に位置している。 As shown in FIG. 5D, regions where the contact holes 45 and 46 in which the wirings 13 and 12 are to be formed are located on the silicon film 11 in plan view (viewed from above). A region where the contact hole 43 where the wiring 15 is to be formed is located on the gate electrode 14 in plan view (viewed from above). A region where the contact hole 44 where the wiring 32 is to be formed is located in the removal portion 70 in plan view (as viewed from above).
　続いて、図５Ｄに示すように、レジストパターン７２をマスクとして層間絶縁膜５３及びゲート絶縁膜５２をエッチングする。これにより、層間絶縁膜５３の表面から、それぞれ、ゲート電極１４、遮光膜２０及びシリコン膜１１まで延びるコンタクトホール４３～４６が形成される。このときのエッチングは、エッチングガスを用いたドライエッチングが好ましい。なお、全てのエッチングをドライエッチングで行う必要はなく、大部分をドライエッチングで行った後、ウェットエッチングを行うようにしてもよい。 Subsequently, as shown in FIG. 5D, the interlayer insulating film 53 and the gate insulating film 52 are etched using the resist pattern 72 as a mask. Thus, contact holes 43 to 46 extending from the surface of the interlayer insulating film 53 to the gate electrode 14, the light shielding film 20, and the silicon film 11 are formed. The etching at this time is preferably dry etching using an etching gas. Note that it is not necessary to perform all etching by dry etching, and wet etching may be performed after most of the etching is performed by dry etching.
　配線３２のコンタクトホール４４の形成予定領域では、バッファ膜５１が除去されていて、ゲート絶縁膜５２及び層間絶縁膜５３のみが形成されている。そのため、コンタクトホール４４の形成予定領域でエッチングが必要な膜厚は、配線１３，１２のコンタクトホール４５，４６の形成予定領域でエッチングが必要な膜厚と同等になる。したがって、複数のコンタクトホール４４～４６の形成予定領域で同時にエッチングを行う際に、配線１２，１３が接続されるシリコン膜１１が過剰にエッチングされるのを防止できる。 In the region where the contact hole 44 of the wiring 32 is to be formed, the buffer film 51 is removed, and only the gate insulating film 52 and the interlayer insulating film 53 are formed. Therefore, the film thickness that needs to be etched in the region where the contact hole 44 is to be formed is equivalent to the film thickness that needs to be etched in the region where the contact holes 45 and 46 of the wirings 13 and 12 are to be formed. Therefore, it is possible to prevent the silicon film 11 to which the wirings 12 and 13 are connected from being excessively etched when etching is performed simultaneously in the regions where the plurality of contact holes 44 to 46 are to be formed.
　レジストパターン７２を除去した後、図５Ｅに示すように、コンタクトホール４３～４６内に配線１５，３２，１３，１２を形成するとともに、ソース電極３１を形成する。そして、層間絶縁膜５３上に保護膜２４及び透明電極２５を形成する。これにより、半導体装置５０が形成される。 After removing the resist pattern 72, as shown in FIG. 5E, the wirings 15, 32, 13, 12 are formed in the contact holes 43 to 46, and the source electrode 31 is formed. Then, the protective film 24 and the transparent electrode 25 are formed on the interlayer insulating film 53. Thereby, the semiconductor device 50 is formed.
　ここで、基板３０上に遮光膜２０を形成する工程が導電層形成工程に、該基板３０上及び遮光膜２０上にバッファ膜５１を形成する工程が絶縁層形成工程に、それぞれ対応する。また、バッファ膜５１上にシリコン膜１１を形成する工程が半導体層形成工程に、ゲート絶縁膜５２上にゲート電極１４を形成する工程がゲート電極形成工程に、それぞれ対応する。 Here, the step of forming the light shielding film 20 on the substrate 30 corresponds to the conductive layer forming step, and the step of forming the buffer film 51 on the substrate 30 and the light shielding film 20 corresponds to the insulating layer forming step. Further, the process of forming the silicon film 11 on the buffer film 51 corresponds to the semiconductor layer forming process, and the process of forming the gate electrode 14 on the gate insulating film 52 corresponds to the gate electrode forming process.
　さらに、遮光膜２０の一部の上方に位置するバッファ膜５１を除去して除去部７０を形成する工程が絶縁層除去工程に、層間絶縁層５３を形成する工程が層間絶縁層形成工程に、それぞれ対応する。また、コンタクトホール４３～４６を形成する工程がコンタクトホール形成工程に対応する。 Further, the step of removing the buffer film 51 located above a part of the light shielding film 20 to form the removal portion 70 is the insulating layer removing step, and the step of forming the interlayer insulating layer 53 is the interlayer insulating layer forming step. Each corresponds. Further, the process of forming the contact holes 43 to 46 corresponds to the contact hole forming process.
　（第２の実施形態の効果）
　本実施形態では、配線３２が遮光膜２０に接続される部分において、該遮光膜２０に形成されたバッファ膜５１を除去した後、ゲート絶縁膜５２及び層間絶縁膜５３を形成した。そして、複数のコンタクトホール４３～４６の形成予定領域を同時にエッチングするようにした。これにより、配線３２のコンタクトホール４４の形成予定領域でエッチングが必要な膜厚を、シリコン膜１１に接続される配線１３，１２のコンタクトホール４５，４６の形成予定領域でエッチングが必要な膜厚と同等にすることができる。したがって、複数のコンタクトホール４３～４６の形成予定領域を同時にエッチングする際に、配線１２，１３に接続されるシリコン膜１１が過剰にエッチングされるのを防止できる。 (Effect of 2nd Embodiment)
In the present embodiment, the gate insulating film 52 and the interlayer insulating film 53 are formed after removing the buffer film 51 formed on the light shielding film 20 in the portion where the wiring 32 is connected to the light shielding film 20. Then, the regions where the plurality of contact holes 43 to 46 are to be formed are etched simultaneously. Thus, the film thickness that needs to be etched in the region where the contact hole 44 of the wiring 32 is to be formed is the film thickness that needs to be etched in the region where the contact holes 45 and 46 of the wiring 13 and 12 connected to the silicon film 11 are to be formed. Can be equivalent. Therefore, it is possible to prevent the silicon film 11 connected to the wirings 12 and 13 from being excessively etched when simultaneously etching the regions where the plurality of contact holes 43 to 46 are to be formed.
　また、上述の構成により、複数のコンタクトホール４３～４６の形成予定領域を同時にエッチングする際に、コンタクトホール４３の形成予定領域では、バッファ膜５１をエッチングする必要がないため、その分、エッチング時間を短縮できる。よって、ゲート電極１４に接続される配線１５のコンタクトホール４３の形成予定領域でエッチングする時間が短縮されるため、ゲート電極１４が過剰にエッチングされるのを抑制できる。 Also, with the above-described configuration, when simultaneously etching the regions where the plurality of contact holes 43 to 46 are to be formed, it is not necessary to etch the buffer film 51 in the regions where the contact holes 43 are to be formed. Can be shortened. Accordingly, the time for etching in the region where the contact hole 43 of the wiring 15 connected to the gate electrode 14 is to be formed is shortened, so that the gate electrode 14 can be prevented from being excessively etched.
　［第３の実施形態］
　図６に、第３の実施形態にかかる半導体装置１００の概略構成を示す。この実施形態は、ＴＦＴ１１０の構成が第１の実施形態とは異なる。以下の説明において、実施形態１と同一の構成には同一の符号を付し、異なる部分についてのみ説明する。 [Third Embodiment]
FIG. 6 shows a schematic configuration of a semiconductor device 100 according to the third embodiment. In this embodiment, the configuration of the TFT 110 is different from that of the first embodiment. In the following description, the same components as those in the first embodiment are denoted by the same reference numerals, and only different portions will be described.
　具体的には、この実施形態では、ＴＦＴ１１０は、ゲート絶縁膜１２２（絶縁層、ゲート絶縁層）上にシリコン膜１１１（半導体層）が形成され、且つ、バッファ膜１２１（絶縁層、バッファ層）とゲート絶縁膜１２２との間にゲート電極１１４が形成された、いわゆるボトムゲート型のＴＦＴである。 Specifically, in this embodiment, the TFT 110 includes a silicon film 111 (semiconductor layer) formed on a gate insulating film 122 (insulating layer, gate insulating layer), and a buffer film 121 (insulating layer, buffer layer). This is a so-called bottom gate type TFT in which a gate electrode 114 is formed between the gate insulating film 122 and the gate insulating film 122.
　遮光膜２０に接続される配線１３２（配線部材）は、バッファ膜１２１及びゲート絶縁膜１２２が除去された除去部１４０（絶縁層除去部）内に設けられている。すなわち、配線１３２との接続部分の周辺の遮光膜２０上には、バッファ膜１２１及びゲート絶縁膜１２２が除去された除去部１４０が形成されていて、該除去部１４０内に層間絶縁膜１２３が設けられている。 The wiring 132 (wiring member) connected to the light shielding film 20 is provided in the removing portion 140 (insulating layer removing portion) from which the buffer film 121 and the gate insulating film 122 are removed. That is, the removal portion 140 from which the buffer film 121 and the gate insulating film 122 are removed is formed on the light shielding film 20 around the connection portion with the wiring 132, and the interlayer insulation film 123 is formed in the removal portion 140. Is provided.
　これにより、第１の実施形態と同様、配線１１５，１３２，１１３，１１２のコンタクトホール１４３～１４６（図７Ｄ参照）の形成予定領域を同時にエッチングする際に、配線１３２のコンタクトホール１４４の形成予定領域のエッチング時間を短縮することができる。 As a result, similar to the first embodiment, the contact hole 144 of the wiring 132 is scheduled to be formed when the formation regions of the contact holes 143 to 146 (see FIG. 7D) of the wirings 115, 132, 113, and 112 are simultaneously etched. The etching time of the region can be shortened.
　（半導体装置の製造方法）
　次に、この第３の実施形態における半導体装置１００の製造方法を、主に第１の実施形態と異なる部分について、図７Ａ～図７Ｅを用いて説明する。これらの図は、この実施形態における半導体装置１００の製造工程を示す断面図である。なお、半導体装置１００を構成する各膜の材料等は、第１及び第２の実施形態と同様である。 (Method for manufacturing semiconductor device)
Next, the manufacturing method of the semiconductor device 100 according to the third embodiment will be described with reference to FIGS. 7A to 7E, mainly on the differences from the first embodiment. These drawings are cross-sectional views showing the manufacturing process of the semiconductor device 100 in this embodiment. The material of each film constituting the semiconductor device 100 is the same as that in the first and second embodiments.
　最初に、第１の実施形態と同様、図７Ａに示すように、基板３０上に、バックライト装置の照明光が該基板３０の一面側（図の下側）からＴＦＴ１１０に入射するのを防止するための遮光膜２０を形成する。その後、基板３０及び遮光膜２０を覆うようにバッファ膜１２１を形成する。 First, as in the first embodiment, as shown in FIG. 7A, the illumination light of the backlight device is prevented from entering the TFT 110 from one surface side (the lower side of the drawing) of the substrate 30 on the substrate 30. A light shielding film 20 is formed. Thereafter, a buffer film 121 is formed so as to cover the substrate 30 and the light shielding film 20.
　次に、バッファ膜１２１上に、金属膜をスパッタ法によって形成する。その後、フォトリソグラフィ法によって、ゲート電極１１４の形成予定領域を覆うレジストパターンを形成し、これをマスクとして金属膜をエッチングする。これにより、ゲート電極１１４が得られる。 Next, a metal film is formed on the buffer film 121 by sputtering. Thereafter, a resist pattern is formed by photolithography to cover a region where the gate electrode 114 is to be formed, and the metal film is etched using the resist pattern as a mask. Thereby, the gate electrode 114 is obtained.
　バッファ膜１２１上及びゲート電極１１４上に、第１の実施形態と同様のゲート絶縁膜１２２をＣＶＤ法によって形成する。このゲート絶縁膜１２２上に、シリコン薄膜をＣＶＤ法によって形成する。その後、フォトリソグラフィ法によって、シリコン膜１１１の形成予定領域を覆うレジストパターンを形成し、これをマスクとしてシリコン薄膜をエッチングする。これにより、シリコン膜１１１が得られる。 A gate insulating film 122 similar to that of the first embodiment is formed on the buffer film 121 and the gate electrode 114 by a CVD method. A silicon thin film is formed on the gate insulating film 122 by a CVD method. Thereafter, a resist pattern that covers a region where the silicon film 111 is to be formed is formed by photolithography, and the silicon thin film is etched using the resist pattern as a mask. Thereby, the silicon film 111 is obtained.
　そして、遮光膜２０の上方で且つシリコン膜１１１が形成される領域以外の部分で開口するように、ゲート絶縁膜１２２上及びシリコン膜１１１上にレジストパターン１４１を形成する。すなわち、レジストパターン１４１は、ゲート絶縁膜１２２における除去部１４０の形成予定領域を露出させるような開口を有している。 Then, a resist pattern 141 is formed on the gate insulating film 122 and the silicon film 111 so as to open above the light shielding film 20 and in a portion other than the region where the silicon film 111 is formed. That is, the resist pattern 141 has an opening that exposes a region where the removal portion 140 is to be formed in the gate insulating film 122.
　図７Ｂに示すように、レジストパターン１４１をマスクとしてゲート絶縁膜１２２及びバッファ膜１２１をエッチングする。このとき、該ゲート絶縁膜１２２及びバッファ膜１２１を、遮光膜２０が露出するまでエッチングを行う。これにより、遮光膜２０の一部の上方に位置するゲート絶縁膜１２２及びバッファ膜１２１が除去されて、除去部１４０が形成される。 7B, the gate insulating film 122 and the buffer film 121 are etched using the resist pattern 141 as a mask. At this time, the gate insulating film 122 and the buffer film 121 are etched until the light shielding film 20 is exposed. As a result, the gate insulating film 122 and the buffer film 121 located above a part of the light shielding film 20 are removed, and the removal portion 140 is formed.
　なお、図７Ｂにおけるエッチングは、第１の実施形態と同様、ウェットエッチングやドライエッチングでもよい。また、これらのウェットエッチングとドライエッチングとを組み合わせた手法であってもよい。 Note that the etching in FIG. 7B may be wet etching or dry etching, as in the first embodiment. Moreover, the method which combined these wet etching and dry etching may be used.
　レジストパターン１４１を除去した後、図７Ｃに示すように、ゲート絶縁膜１２２上、シリコン膜１１１上及び除去部１４０上に、層間絶縁膜１２３をＣＶＤ法によって形成する。その後、層間絶縁膜１２３上に、配線１１５，１３２，１１３，１１２が形成されるコンタクトホール１４３～１４６の形成予定領域が開口するようなレジストパターン１４２を形成する。 After removing the resist pattern 141, as shown in FIG. 7C, an interlayer insulating film 123 is formed on the gate insulating film 122, the silicon film 111, and the removal portion 140 by a CVD method. Thereafter, a resist pattern 142 is formed on the interlayer insulating film 123 so as to open regions where the contact holes 143 to 146 in which the wirings 115, 132, 113, and 112 are formed are opened.
　なお、図７Ｄに示すように、配線１１３，１１２が形成されるコンタクトホール１４５，１４６（半導体層コンタクトホール）の形成予定領域は、平面視（図の上方から見て）でシリコン膜１１１上に位置している。配線１１５が形成されるコンタクトホール１４３（ゲート電極コンタクトホール）の形成予定領域は、平面視（図の上方から見て）でゲート電極１１４上に位置している。配線１３２が形成されるコンタクトホール１４４（導電層コンタクトホール）の形成予定領域は、平面視（図の上方から見て）で除去部１４０内に位置している。 As shown in FIG. 7D, regions where the contact holes 145 and 146 (semiconductor layer contact holes) where the wirings 113 and 112 are formed are formed on the silicon film 111 in plan view (viewed from above). positioned. A region where the contact hole 143 (gate electrode contact hole) where the wiring 115 is to be formed is located on the gate electrode 114 in plan view (viewed from above). A region in which the contact hole 144 (conductive layer contact hole) where the wiring 132 is to be formed is located in the removal portion 140 in plan view (viewed from above).
　続いて、図７Ｄに示すように、レジストパターン１４２をマスクとして層間絶縁膜１２３及びゲート絶縁膜１２２をエッチングする。これにより、層間絶縁膜１２３の表面から、それぞれ、ゲート電極１１４、遮光膜２０及びシリコン膜１１１まで延びるコンタクトホール１４３～１４６が形成される。このときのエッチングは、エッチングガスを用いたドライエッチングが好ましい。なお、全てのエッチングをドライエッチングで行う必要はなく、大部分をドライエッチングで行った後、ウェットエッチングを行うようにしてもよい。 Subsequently, as shown in FIG. 7D, the interlayer insulating film 123 and the gate insulating film 122 are etched using the resist pattern 142 as a mask. Thereby, contact holes 143 to 146 extending from the surface of the interlayer insulating film 123 to the gate electrode 114, the light shielding film 20, and the silicon film 111 are formed. The etching at this time is preferably dry etching using an etching gas. Note that it is not necessary to perform all etching by dry etching, and wet etching may be performed after most of the etching is performed by dry etching.
　第１の実施形態と同様、配線１３２のコンタクトホール１４４の形成予定領域では、バッファ膜１２１及びゲート絶縁膜１２２が除去されていて、層間絶縁膜１２３のみが形成されている。そのため、エッチングする膜厚は、配線１３２のコンタクトホール１４４の形成予定領域と、シリコン膜１１１に接続される配線１１３，１１２のコンタクトホール１４５，１４６の形成予定領域とで同等である。したがって、図７Ｄのエッチングの際に、シリコン膜１１１が過剰にエッチングされるのを防止できる。 As in the first embodiment, the buffer film 121 and the gate insulating film 122 are removed in the region where the contact hole 144 of the wiring 132 is to be formed, and only the interlayer insulating film 123 is formed. Therefore, the film thickness to be etched is the same in the region where the contact hole 144 of the wiring 132 is to be formed and the region where the contact holes 145 and 146 of the wiring 113 and 112 connected to the silicon film 111 are to be formed. Therefore, the silicon film 111 can be prevented from being excessively etched during the etching shown in FIG. 7D.
　さらに、エッチングする膜厚は、ゲート電極１１４に接続される配線１１５のコンタクトホール１４３の形成予定領域で最も厚くなる。そのため、当該領域をエッチングする時間を基準として、複数のコンタクトホール１４３～１４６を同時にエッチングすることができる。コンタクトホール１４３の形成予定領域では、他の領域に比べてゲート絶縁膜１２２の分、厚くなっているだけなので、複数のコンタクトホール１４３～１４６を同時にエッチングする際に、遮光膜２０及びシリコン膜１１１が過剰にエッチングされるのを防止できる。 Furthermore, the film thickness to be etched is the thickest in the region where the contact hole 143 of the wiring 115 connected to the gate electrode 114 is to be formed. Therefore, the plurality of contact holes 143 to 146 can be etched simultaneously with reference to the time for etching the region. Since the region where the contact hole 143 is to be formed is only thicker than the other region by the amount of the gate insulating film 122, when simultaneously etching the contact holes 143 to 146, the light shielding film 20 and the silicon film 111 are formed. Can be prevented from being excessively etched.
　レジストパターン１４２を除去した後、図７Ｅに示すように、コンタクトホール１４３～１４６内に配線１１５，１３２，１１３，１１２を形成するとともに、ソース電極１３１を形成する。そして、層間絶縁膜１２３上に保護膜２４及び透明電極２５を形成する。これにより、半導体装置１００が形成される。 After removing the resist pattern 142, as shown in FIG. 7E, wirings 115, 132, 113, 112 are formed in the contact holes 143 to 146, and a source electrode 131 is formed. Then, the protective film 24 and the transparent electrode 25 are formed on the interlayer insulating film 123. Thereby, the semiconductor device 100 is formed.
　ここで、基板３０上に遮光膜２０を形成する工程が導電層形成工程に、該基板３０上及び遮光膜２０上にバッファ膜１２１及びゲート絶縁膜１２２を形成する工程が絶縁層形成工程に、それぞれ対応する。また、ゲート絶縁膜１２２上にシリコン膜１１１を形成する工程が半導体層形成工程に、バッファ膜１２１上にゲート電極１１４を形成する工程がゲート電極形成工程に、それぞれ対応する。 Here, the process of forming the light shielding film 20 on the substrate 30 is a conductive layer forming process, and the process of forming the buffer film 121 and the gate insulating film 122 on the substrate 30 and the light shielding film 20 is an insulating layer forming process. Each corresponds. Further, the step of forming the silicon film 111 over the gate insulating film 122 corresponds to the semiconductor layer forming step, and the step of forming the gate electrode 114 over the buffer film 121 corresponds to the gate electrode forming step.
　さらに、遮光膜２０の一部の上方に位置するバッファ膜１２１及びゲート絶縁膜１２２を除去して除去部１４０を形成する工程が絶縁層除去工程に、層間絶縁層１２３を形成する工程が層間絶縁層形成工程に、それぞれ対応する。また、コンタクトホール１４３～１４６を形成する工程がコンタクトホール形成工程に対応する。 Further, the step of forming the removal portion 140 by removing the buffer film 121 and the gate insulating film 122 located above a part of the light shielding film 20 is the insulating layer removing step, and the step of forming the interlayer insulating layer 123 is the interlayer insulation. Each corresponds to the layer forming step. Further, the process of forming contact holes 143 to 146 corresponds to the contact hole forming process.
　なお、本実施形態では、ゲート絶縁膜１２２上にシリコン膜１１１を形成した後に、除去部１４０を形成しているが、シリコン膜１１１を形成する前に除去部１４０を形成してもよい。 In this embodiment, the removal portion 140 is formed after the silicon film 111 is formed on the gate insulating film 122. However, the removal portion 140 may be formed before the silicon film 111 is formed.
　（第３の実施形態の効果）
　本実施形態では、配線１３２が遮光膜２０に接続される部分において、該遮光膜２０上に形成されたバッファ膜１２１及びゲート絶縁膜１２２を除去した後、層間絶縁膜１２３を形成した。そして、複数のコンタクトホール１４３～１４６の形成予定領域を同時にエッチングするようにした。これにより、配線１３２のコンタクトホール１４４の形成予定領域でエッチングされる膜厚と、シリコン膜１１１に接続される配線１１３，１１２のコンタクトホール１４５，１４６の形成予定領域でエッチングされる膜厚とを同等にすることが可能になる。したがって、複数のコンタクトホール１４３～１４６の形成予定領域を同時にエッチングする際に、コンタクトホール１４５，１４６の形成予定領域でシリコン膜１１１が過剰にエッチングされるのを防止できる。 (Effect of the third embodiment)
In the present embodiment, the interlayer insulating film 123 is formed after removing the buffer film 121 and the gate insulating film 122 formed on the light shielding film 20 in the portion where the wiring 132 is connected to the light shielding film 20. Then, the regions where the plurality of contact holes 143 to 146 are to be formed are etched simultaneously. As a result, the film thickness etched in the region where the contact hole 144 of the wiring 132 is to be formed and the film thickness etched in the region where the contact holes 145 and 146 of the wiring 113 and 112 connected to the silicon film 111 are formed are reduced. It becomes possible to make it equivalent. Therefore, when the regions where the plurality of contact holes 143 to 146 are to be formed are etched simultaneously, the silicon film 111 can be prevented from being excessively etched in the regions where the contact holes 145 and 146 are to be formed.
　さらに、エッチングする膜厚は、ゲート電極１１４に接続される配線１１５のコンタクトホール１４３の形成予定領域が最も厚くなるため、該形成予定領域のエッチング時間を基準として、複数のコンタクトホール１４３～１４６の形成予定領域をエッチングすることができる。これにより、複数のコンタクトホール１４３～１４６の形成予定領域を同時にエッチングする際に、ゲート電極１１４、遮光膜２０、シリコン膜１１１が過剰にエッチングされるのを防止できる。 Further, the etching thickness of the contact hole 143 of the wiring 115 connected to the gate electrode 114 is the thickest, so that the plurality of contact holes 143 to 146 are formed with reference to the etching time of the formation region. The region to be formed can be etched. This can prevent excessive etching of the gate electrode 114, the light shielding film 20, and the silicon film 111 when simultaneously etching regions where the plurality of contact holes 143 to 146 are to be formed.
　［第４の実施形態］
　図８に、第４の実施形態にかかる半導体装置１５０の概略構成を示す。この実施形態は、除去部１７０の構成及び半導体装置１５０の製造方法が第３の実施形態とは異なる。以下の説明において、実施形態３と同一の構成には同一の符号を付し、異なる部分についてのみ説明する。 [Fourth Embodiment]
FIG. 8 shows a schematic configuration of a semiconductor device 150 according to the fourth embodiment. This embodiment is different from the third embodiment in the configuration of the removal unit 170 and the method for manufacturing the semiconductor device 150. In the following description, the same components as those of the third embodiment are denoted by the same reference numerals, and only different portions will be described.
　具体的には、この実施形態では、除去部１７０（絶縁層除去部）はバッファ膜１５１（絶縁層、バッファ層）のみに形成されている。すなわち、配線１３２（配線部材）との接続部分の周囲の遮光膜２０上には、ゲート絶縁膜１５２（ゲート絶縁層）が形成されていて、該ゲート絶縁膜１５２上に層間絶縁膜１５３（層間絶縁層）が形成されている。 Specifically, in this embodiment, the removal portion 170 (insulating layer removal portion) is formed only in the buffer film 151 (insulating layer, buffer layer). That is, the gate insulating film 152 (gate insulating layer) is formed on the light shielding film 20 around the connection portion with the wiring 132 (wiring member), and the interlayer insulating film 153 (interlayer insulating film) is formed on the gate insulating film 152. An insulating layer) is formed.
　このような構成により、配線１３２が形成されるコンタクトホール１４４の形成予定領域にバッファ膜１５１が存在しない分、該形成予定領域のエッチング時間を短くすることができる。よって、配線１１５，１３２，１１３，１１２のコンタクトホール１４３～１４６の形成予定領域を同時にエッチングする際に、配線１１３，１１２に接続されるシリコン膜１１１及び配線１１５に接続されるゲート電極１１４が過剰にエッチングされるのを抑制することができる。 With such a configuration, the etching time for the region to be formed can be shortened because the buffer film 151 does not exist in the region for forming the contact hole 144 in which the wiring 132 is formed. Therefore, when the regions where the contact holes 143 to 146 are to be formed are simultaneously etched in the wirings 115, 132, 113, and 112, the silicon film 111 connected to the wirings 113 and 112 and the gate electrode 114 connected to the wiring 115 are excessive. Etching can be suppressed.
　（半導体装置の製造方法）
　次に、この第４の実施形態における半導体装置１５０の製造方法を、主に第３の実施形態と異なる部分について、図９Ａ～図９Ｅを用いて説明する。これらの図は、この実施形態における半導体装置１５０の製造工程を示す断面図である。なお、半導体装置１５０を構成する各膜の材料や製造方法は、第３の実施形態と同様である。 (Method for manufacturing semiconductor device)
Next, a method for manufacturing the semiconductor device 150 according to the fourth embodiment will be described with reference to FIGS. 9A to 9E, mainly on differences from the third embodiment. These drawings are cross-sectional views showing the manufacturing process of the semiconductor device 150 in this embodiment. The material and manufacturing method of each film constituting the semiconductor device 150 are the same as those in the third embodiment.
　最初に、第３の実施形態と同様、図９Ａに示すように、基板３０上に、バックライト装置の照明光が該基板３０の一面側（図の下側）からＴＦＴ１６０に入射するのを防止するための遮光膜２０を形成する。その後、基板３０及び遮光膜２０を覆うようにバッファ膜１５１を形成する。そして、第３の実施形態と同様に、バッファ膜１５１上に、ゲート電極１１４を形成する。 First, as in the third embodiment, as shown in FIG. 9A, the illumination light of the backlight device is prevented from being incident on the TFT 160 on the substrate 30 from one surface side (the lower side of the drawing). A light shielding film 20 is formed. Thereafter, a buffer film 151 is formed so as to cover the substrate 30 and the light shielding film 20. Then, the gate electrode 114 is formed on the buffer film 151 as in the third embodiment.
　次に、フォトリソグラフィ法によって、遮光膜２０の上方で且つゲート電極１１４が形成される領域以外の部分で開口するように、バッファ膜１５１上及びゲート電極１１４上にレジストパターン１７１を形成する。すなわち、レジストパターン１７１は、バッファ膜１５１における除去部１７０の形成予定領域を露出させるような開口を有している。 Next, a resist pattern 171 is formed on the buffer film 151 and on the gate electrode 114 by photolithography so as to open at a portion above the light shielding film 20 and other than the region where the gate electrode 114 is formed. That is, the resist pattern 171 has an opening that exposes a region where the removal portion 170 is to be formed in the buffer film 151.
　図９Ｂに示すように、レジストパターン１７１をマスクとしてバッファ膜１５１をエッチングする。このとき、該バッファ膜１５１を、遮光膜２０が露出するまでエッチングを行う。これにより、遮光膜２０の一部の上方に位置するバッファ膜１５１が除去されて、除去部１７０が形成される。 As shown in FIG. 9B, the buffer film 151 is etched using the resist pattern 171 as a mask. At this time, the buffer film 151 is etched until the light shielding film 20 is exposed. As a result, the buffer film 151 located above a part of the light shielding film 20 is removed, and the removal unit 170 is formed.
　なお、図９Ｂにおけるエッチングは、第３の実施形態と同様、ウェットエッチングやドライエッチングでもよい。また、これらのウェットエッチングとドライエッチングとを組み合わせた手法であってもよい。 Note that the etching in FIG. 9B may be wet etching or dry etching, as in the third embodiment. Moreover, the method which combined these wet etching and dry etching may be used.
　レジストパターン１７１を除去した後、図９Ｃに示すように、バッファ膜１５１上及びゲート電極１１４上に、第３の実施形態と同様のゲート絶縁膜１５２を形成し、該ゲート絶縁膜１５２上に、第３の実施形態と同様のシリコン膜１１１を形成する。その後、層間絶縁膜１５３を形成し、該層間絶縁膜１５３上に、配線１１５，１３２，１１３，１１２が形成されるコンタクトホール１４３～１４６の形成予定領域を露出させるような開口を有するレジストパターン１７２を形成する。 After removing the resist pattern 171, as shown in FIG. 9C, a gate insulating film 152 similar to that of the third embodiment is formed on the buffer film 151 and the gate electrode 114, and on the gate insulating film 152, A silicon film 111 similar to that of the third embodiment is formed. Thereafter, an interlayer insulating film 153 is formed, and a resist pattern 172 having an opening that exposes regions where the contact holes 143 to 146 in which the wirings 115, 132, 113, and 112 are formed is exposed on the interlayer insulating film 153. Form.
　なお、図９Ｄに示すように、配線１１３，１１２が形成されるコンタクトホール１４５，１４６の形成予定領域は、平面視（図の上方から見て）でシリコン膜１１上に位置している。配線１１５が形成されるコンタクトホール１４３の形成予定領域は、平面視（図の上方から見て）でゲート電極１１４上に位置している。配線１３２が形成されるコンタクトホール１４４の形成予定領域は、平面視（図の上方から見て）で除去部１７０内に位置している。 As shown in FIG. 9D, regions where the contact holes 145 and 146 where the wirings 113 and 112 are formed are located on the silicon film 11 in plan view (viewed from above). A region where the contact hole 143 is to be formed in which the wiring 115 is formed is located on the gate electrode 114 in plan view (viewed from above). A region where the contact hole 144 is to be formed in which the wiring 132 is to be formed is located in the removal portion 170 in plan view (viewed from above).
　続いて、図９Ｄに示すように、レジストパターン１７２をマスクとして層間絶縁膜１５３及びゲート絶縁膜１５２をエッチングする。このときのエッチングは、エッチングガスを用いたドライエッチングが好ましい。なお、全てのエッチングをドライエッチングで行う必要はなく、大部分をドライエッチングで行った後、ウェットエッチングを行うようにしてもよい。 Subsequently, as shown in FIG. 9D, the interlayer insulating film 153 and the gate insulating film 152 are etched using the resist pattern 172 as a mask. The etching at this time is preferably dry etching using an etching gas. Note that it is not necessary to perform all etching by dry etching, and wet etching may be performed after most of the etching is performed by dry etching.
　配線１３２の形成予定領域では、バッファ膜１５１が除去されていて、ゲート絶縁膜１５２及び層間絶縁膜１５３のみが形成されている。そのため、配線１１２，１１３，１３２の形成予定領域を同時にエッチングする際に、配線１３２の形成予定領域でバッファ膜１５１をエッチングしなくてもよい分、全体のエッチング時間を短縮することができる。したがって、複数のコンタクトホール１４４～１４６の形成予定領域をエッチングする際に、配線１１２，１１３が接続されるシリコン膜１１１が過剰にエッチングされるのを防止できる。 In the region where the wiring 132 is to be formed, the buffer film 151 is removed, and only the gate insulating film 152 and the interlayer insulating film 153 are formed. Therefore, when simultaneously etching the regions where the wirings 112, 113, and 132 are to be formed, the entire etching time can be shortened because the buffer film 151 need not be etched in the regions where the wiring 132 is to be formed. Therefore, it is possible to prevent the silicon film 111 to which the wirings 112 and 113 are connected from being excessively etched when etching the regions where the plurality of contact holes 144 to 146 are to be formed.
　しかも、ゲート電極１１４に接続される配線１１５のコンタクトホール１４３の形成予定領域とコンタクトホール１４４の形成予定領域とは、エッチングする膜厚が同等になる。そのため、複数のコンタクトホール１４３～１４６を同時にエッチングする際に、ゲート電極１１４が過剰にエッチングされるのを防止できる。 In addition, the region where the contact hole 143 is to be formed in the wiring 115 connected to the gate electrode 114 and the region where the contact hole 144 is to be formed have the same etching thickness. Therefore, it is possible to prevent the gate electrode 114 from being excessively etched when simultaneously etching the plurality of contact holes 143 to 146.
　レジストパターン１７２を除去した後、図９Ｅに示すように、コンタクトホール１４３～１４６内に配線１１５，１３２，１１３，１１２を形成するとともに、ソース電極３１を形成する。そして、層間絶縁膜１５３上に保護膜２４及び透明電極２５を形成する。これにより、半導体装置１５０が形成される。 After removing the resist pattern 172, as shown in FIG. 9E, wirings 115, 132, 113, and 112 are formed in the contact holes 143 to 146, and the source electrode 31 is formed. Then, the protective film 24 and the transparent electrode 25 are formed on the interlayer insulating film 153. Thereby, the semiconductor device 150 is formed.
　ここで、基板３０上に遮光膜２０を形成する工程が導電層形成工程に、該基板３０上及び遮光膜２０上にバッファ膜１５１を形成する工程が絶縁層形成工程に、それぞれ対応する。また、ゲート絶縁膜１５２上にシリコン膜１１１を形成する工程が半導体層形成工程に、バッファ膜１５１上にゲート電極１１４を形成する工程がゲート電極形成工程に、それぞれ対応する。 Here, the step of forming the light shielding film 20 on the substrate 30 corresponds to the conductive layer forming step, and the step of forming the buffer film 151 on the substrate 30 and the light shielding film 20 corresponds to the insulating layer forming step. Further, the step of forming the silicon film 111 over the gate insulating film 152 corresponds to the semiconductor layer formation step, and the step of forming the gate electrode 114 over the buffer film 151 corresponds to the gate electrode formation step.
　さらに、遮光膜２０の一部の上方に位置するバッファ膜１５１を除去して除去部１７０を形成する工程が絶縁層除去工程に、層間絶縁層１５３を形成する工程が層間絶縁層形成工程に、それぞれ対応する。また、コンタクトホール１４３～１４６を形成する工程がコンタクトホール形成工程に対応する。 Further, the step of removing the buffer film 151 located above a part of the light shielding film 20 to form the removed portion 170 is the insulating layer removing step, and the step of forming the interlayer insulating layer 153 is the interlayer insulating layer forming step. Each corresponds. Further, the process of forming contact holes 143 to 146 corresponds to the contact hole forming process.
　なお、本実施形態では、バッファ膜１５１上にゲート電極１１４を形成した後に、除去部１７０を形成しているが、ゲート電極１１４を形成する前に除去部１７０を形成してもよい。 In this embodiment, the removal portion 170 is formed after the gate electrode 114 is formed on the buffer film 151. However, the removal portion 170 may be formed before the gate electrode 114 is formed.
　（第４の実施形態の効果）
　本実施形態では、配線１３２が遮光膜２０に接続される部分において、該遮光膜２０上に形成されたバッファ膜１５１を除去した後、ゲート絶縁膜１５２及び層間絶縁膜１５３を形成した。そして、複数のコンタクトホール１４３～１４６の形成予定領域を同時にエッチングするようにした。これにより、配線１３２のコンタクトホール１４４の形成予定領域において、バッファ膜１５１も同時にエッチングする場合に比べて、エッチング時間を短縮することができる。したがって、複数のコンタクトホール１４３～１４６の形成予定領域を同時にエッチングする際に、配線１１２，１１３が接続されるシリコン膜１１１が過剰にエッチングされるのを防止できる。 (Effect of the fourth embodiment)
In the present embodiment, the gate insulating film 152 and the interlayer insulating film 153 are formed after removing the buffer film 151 formed on the light shielding film 20 in the portion where the wiring 132 is connected to the light shielding film 20. Then, the regions where the plurality of contact holes 143 to 146 are to be formed are etched simultaneously. Thus, the etching time can be shortened in the region where the contact hole 144 of the wiring 132 is to be formed, as compared with the case where the buffer film 151 is also etched at the same time. Accordingly, it is possible to prevent the silicon film 111 to which the wirings 112 and 113 are connected from being excessively etched when simultaneously etching the regions where the plurality of contact holes 143 to 146 are to be formed.
　しかも、ゲート電極１１４に接続される配線１１５のコンタクトホール１４３の形成予定領域とコンタクトホール１４４の形成予定領域とは、エッチングする膜厚が同等になるため、複数のコンタクトホール１４３～１４６を同時にエッチングする際に、ゲート電極１１４が過剰にエッチングされるのを防止できる。 In addition, since the region where the contact hole 143 is to be formed and the region where the contact hole 144 is to be formed in the wiring 115 connected to the gate electrode 114 have the same thickness, the plurality of contact holes 143 to 146 are etched simultaneously. In this case, the gate electrode 114 can be prevented from being excessively etched.
　［その他の実施形態］
　以上、本発明の実施の形態を説明したが、上述した実施の形態は本発明を実施するための例示に過ぎない。よって、本発明は上述した実施の形態に限定されることなく、その趣旨を逸脱しない範囲内で上述した実施の形態を適宜変形して実施することが可能である。 [Other Embodiments]
While the embodiments of the present invention have been described above, the above-described embodiments are merely examples for carrying out the present invention. Therefore, the present invention is not limited to the above-described embodiment, and can be implemented by appropriately modifying the above-described embodiment without departing from the spirit thereof.
　前記各実施形態では、除去部４０，７０，１４０，１７０よりも小径のコンタクトホール４４，１４４を形成している。しかしながら、コンタクトホールの径を除去部と同等もしくはそれ以上にしてもよい。 In each of the above embodiments, the contact holes 44 and 144 having a smaller diameter than the removal portions 40, 70, 140, and 170 are formed. However, the diameter of the contact hole may be equal to or larger than that of the removed portion.
　前記各実施形態では、除去部４０，７０，１４０，１７０を形成する際に、バッファ膜２１，５１，１２１，１５１を全て除去して遮光膜２０を露出させている。しかしながら、複数のコンタクトホールを同時にエッチングする際のシリコン膜の過剰なエッチングを抑制することができれば、バッファ膜の一部を残してもよい。 In each of the above embodiments, when forming the removal portions 40, 70, 140, and 170, the buffer films 21, 51, 121, and 151 are all removed to expose the light shielding film 20. However, part of the buffer film may be left as long as excessive etching of the silicon film when simultaneously etching a plurality of contact holes can be suppressed.
　前記各実施形態では、三端子半導体素子（ＴＦＴ）を有する半導体装置を例示した。しかし、前記第１または第２の実施形態の構成を、二端子半導体素子（例えばフォトダイオード）を有する半導体装置に適用してもよい。二端子半導体素子を有する半導体装置の例としては、例えば、第１または第２の実施形態において、ゲート電極を省略し、シリコン膜１１をＰＮ接合またはＰＩＮ接合のダイオードとして形成した構成等が挙げられる。このダイオードは、例えば光センサとしての利用が可能である。 In each of the above embodiments, a semiconductor device having a three-terminal semiconductor element (TFT) is illustrated. However, the configuration of the first or second embodiment may be applied to a semiconductor device having a two-terminal semiconductor element (for example, a photodiode). Examples of the semiconductor device having a two-terminal semiconductor element include, for example, a configuration in which the gate electrode is omitted and the silicon film 11 is formed as a PN junction or PIN junction diode in the first or second embodiment. . This diode can be used as an optical sensor, for example.
　前記各実施形態では、ゲート電極１４，１１４まで延びるコンタクトホール４３，１４３と、遮光膜２０まで延びるコンタクトホール４４，１４４と、シリコン膜１１，１１１まで延びるコンタクトホール４５，４６，１４５，１４６とを同時に形成している。しかしながら、ゲート電極１４，１１４まで延びるコンタクトホール４３，１４３を、他のコンタクトホール４３，１４３，４５，４６，１４５，１４６とは別に形成してもよい。 In each of the embodiments, the contact holes 43 and 143 extending to the gate electrodes 14 and 114, the contact holes 44 and 144 extending to the light shielding film 20, and the contact holes 45, 46, 145 and 146 extending to the silicon films 11 and 111 are formed. Forming at the same time. However, the contact holes 43, 143 extending to the gate electrodes 14, 114 may be formed separately from the other contact holes 43, 143, 45, 46, 145, 146.
　本発明による半導体装置は、遮光膜の電位を調整可能なように該遮光膜に配線が接続された半導体装置に利用可能である。 The semiconductor device according to the present invention can be used for a semiconductor device in which wiring is connected to the light shielding film so that the potential of the light shielding film can be adjusted.

Claims (11)

  1. 　基板上に遮光性を有する導電層を形成する導電層形成工程と、
    　前記基板上及び導電層上に、絶縁層を形成する絶縁層形成工程と、
    　前記絶縁層内または該絶縁層上のいずれか一方に、島状の半導体層を形成する半導体層形成工程と、
    　前記絶縁層のうち、前記半導体層の形成領域以外で且つ前記導電層上に位置する絶縁層の一部を除去して、絶縁層除去部を形成する絶縁層除去工程と、
    　前記基板の上方に層間絶縁層を形成する層間絶縁層形成工程と、
    　前記層間絶縁層の表面から前記半導体層まで延びる半導体層コンタクトホールと、前記層間絶縁層の表面から前記絶縁層除去部内を通過して前記導電層まで延びる導電層コンタクトホールと、をエッチングによって同時に形成するコンタクトホール形成工程と、
    　を有する、半導体装置の製造方法。     A conductive layer forming step of forming a light-shielding conductive layer on the substrate;
    An insulating layer forming step of forming an insulating layer on the substrate and the conductive layer;
    A semiconductor layer forming step of forming an island-shaped semiconductor layer in either the insulating layer or on the insulating layer;
    An insulating layer removing step of forming an insulating layer removing portion by removing a part of the insulating layer located on the conductive layer other than the region where the semiconductor layer is formed,
    An interlayer insulating layer forming step of forming an interlayer insulating layer above the substrate;
    A semiconductor layer contact hole extending from the surface of the interlayer insulating layer to the semiconductor layer and a conductive layer contact hole extending from the surface of the interlayer insulating layer through the insulating layer removing portion to the conductive layer are simultaneously formed by etching. A contact hole forming step,
    A method for manufacturing a semiconductor device, comprising:
  2. 　前記絶縁層は、バッファ層と該バッファ層上に形成されるゲート絶縁層とからなり、
    　前記絶縁層除去工程では、前記導電層上に位置する前記バッファ層及びゲート絶縁層のそれぞれ一部を除去して、前記絶縁層除去部を形成する、請求項１に記載の半導体装置の製造方法。     The insulating layer comprises a buffer layer and a gate insulating layer formed on the buffer layer,
    2. The method of manufacturing a semiconductor device according to claim 1, wherein in the insulating layer removing step, a part of each of the buffer layer and the gate insulating layer located on the conductive layer is removed to form the insulating layer removing portion. .
  3. 　前記絶縁層は、バッファ層からなり、
    　前記絶縁層除去工程では、前記導電層上に位置する前記バッファ層の一部を除去して前記絶縁層除去部を形成する、請求項１に記載の半導体装置の製造方法。     The insulating layer comprises a buffer layer;
    2. The method of manufacturing a semiconductor device according to claim 1, wherein, in the insulating layer removing step, the insulating layer removing portion is formed by removing a part of the buffer layer located on the conductive layer.
  4. 　前記半導体層形成工程では、前記バッファ層とゲート絶縁層との間に前記半導体層が位置するように、該バッファ層上に半導体層を形成する、請求項２または３に記載の半導体装置の製造方法。 The semiconductor device manufacturing according to claim 2, wherein in the semiconductor layer forming step, a semiconductor layer is formed on the buffer layer so that the semiconductor layer is located between the buffer layer and the gate insulating layer. Method.
  5. 　前記半導体層形成工程では、前記バッファ層上に形成されるゲート絶縁層上に、半導体層を形成する、請求項２または３に記載の半導体装置の製造方法。 4. The method of manufacturing a semiconductor device according to claim 2, wherein in the semiconductor layer forming step, a semiconductor layer is formed on a gate insulating layer formed on the buffer layer.
  6. 　前記絶縁層上にゲート電極を形成するゲート電極形成工程をさらに備え、
    　前記コンタクトホール形成工程では、前記層間絶縁層の表面から前記ゲート電極まで延びるゲート電極コンタクトホールも同時に形成する、請求項１から５のいずれか一つに記載の半導体装置の製造方法。     A gate electrode forming step of forming a gate electrode on the insulating layer;
    6. The method of manufacturing a semiconductor device according to claim 1, wherein in the contact hole forming step, a gate electrode contact hole extending from the surface of the interlayer insulating layer to the gate electrode is also formed at the same time.
  7. 　基板と、
    　前記基板上に形成された遮光性を有する導電層と、
    　前記基板上及び導電層上に形成された絶縁層と、
    　前記絶縁層内または該絶縁層上のいずれか一方に形成された半導体層と、
    　前記絶縁層及び半導体層を覆うように前記基板の上方に形成された層間絶縁層と、
    　前記層間絶縁層内を前記導電層及び半導体層までそれぞれ延びる配線部材と、を備え、
    　前記絶縁層には、前記半導体層の形成領域以外で且つ前記導電層上の少なくとも一部が除去された絶縁層除去部が形成されていて、
    　前記絶縁層除去部内には、前記層間絶縁層と該層間絶縁層を貫通するように前記導電層まで延びる前記配線部材とが設けられている、半導体装置。     A substrate,
    A light-shielding conductive layer formed on the substrate;
    An insulating layer formed on the substrate and the conductive layer;
    A semiconductor layer formed either in the insulating layer or on the insulating layer;
    An interlayer insulating layer formed above the substrate so as to cover the insulating layer and the semiconductor layer;
    A wiring member extending to the conductive layer and the semiconductor layer in the interlayer insulating layer, and
    The insulating layer is formed with an insulating layer removing portion in which at least part of the conductive layer is removed except for the region where the semiconductor layer is formed,
    The semiconductor device, wherein the insulating layer removing portion includes the interlayer insulating layer and the wiring member extending to the conductive layer so as to penetrate the interlayer insulating layer.
  8. 　前記絶縁層は、バッファ層と該バッファ層上に形成されたゲート絶縁層とからなる、請求項７に記載の半導体装置。 The semiconductor device according to claim 7, wherein the insulating layer includes a buffer layer and a gate insulating layer formed on the buffer layer.
  9. 　前記絶縁層は、バッファ層からなり、
    　前記半導体層は、前記バッファ層の上方に形成されている、請求項７に記載の半導体装置。     The insulating layer comprises a buffer layer;
    The semiconductor device according to claim 7, wherein the semiconductor layer is formed above the buffer layer.
  10. 　前記半導体層は、前記バッファ層と該バッファ層上に形成されたゲート絶縁層との間に位置するように、該バッファ層上に設けられている、請求項８または９に記載の半導体装置。 10. The semiconductor device according to claim 8, wherein the semiconductor layer is provided on the buffer layer so as to be positioned between the buffer layer and a gate insulating layer formed on the buffer layer.
  11. 　前記半導体層は、前記バッファ層上に形成されたゲート絶縁層上に設けられている、請求項８または９に記載の半導体装置。 10. The semiconductor device according to claim 8, wherein the semiconductor layer is provided on a gate insulating layer formed on the buffer layer.
PCT/JP2011/053258 2010-04-27 2011-02-16 Semiconductor device, and manufacturing method for same WO2011135896A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2010102565 2010-04-27
JP2010-102565 2010-04-27

Publications (1)

Publication Number Publication Date
WO2011135896A1 true WO2011135896A1 (en) 2011-11-03

Family

ID=44861217

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2011/053258 WO2011135896A1 (en) 2010-04-27 2011-02-16 Semiconductor device, and manufacturing method for same

Country Status (1)

Country Link
WO (1) WO2011135896A1 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107452808A (en) * 2017-07-04 2017-12-08 京东方科技集团股份有限公司 Thin film transistor (TFT) and preparation method thereof, array base palte and display device
JP2020036012A (en) * 2018-08-30 2020-03-05 シャープ株式会社 Active matrix substrate, display device, and method of manufacturing active matrix substrate
WO2021196877A1 (en) * 2020-03-31 2021-10-07 京东方科技集团股份有限公司 Array substrate, display panel, display device and manufacturing method

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10189481A (en) * 1996-11-07 1998-07-21 Semiconductor Energy Lab Co Ltd Manufacture of semiconductor device
JP2005223015A (en) * 2004-02-03 2005-08-18 Nec Corp Thin-film transistor, tft board, and liquid crystal display
JP2010039413A (en) * 2008-08-08 2010-02-18 Hitachi Displays Ltd Display, and method for manufacturing the same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10189481A (en) * 1996-11-07 1998-07-21 Semiconductor Energy Lab Co Ltd Manufacture of semiconductor device
JP2005223015A (en) * 2004-02-03 2005-08-18 Nec Corp Thin-film transistor, tft board, and liquid crystal display
JP2010039413A (en) * 2008-08-08 2010-02-18 Hitachi Displays Ltd Display, and method for manufacturing the same

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107452808A (en) * 2017-07-04 2017-12-08 京东方科技集团股份有限公司 Thin film transistor (TFT) and preparation method thereof, array base palte and display device
CN107452808B (en) * 2017-07-04 2021-10-22 京东方科技集团股份有限公司 Thin film transistor, preparation method thereof, array substrate and display device
JP2020036012A (en) * 2018-08-30 2020-03-05 シャープ株式会社 Active matrix substrate, display device, and method of manufacturing active matrix substrate
WO2021196877A1 (en) * 2020-03-31 2021-10-07 京东方科技集团股份有限公司 Array substrate, display panel, display device and manufacturing method

Similar Documents

Publication Publication Date Title
US8957418B2 (en) Semiconductor device and display apparatus
JP3708637B2 (en) Liquid crystal display device
JP4543385B2 (en) Manufacturing method of liquid crystal display device
US20120199891A1 (en) Semiconductor device and method for manufacturing same
US8592811B2 (en) Active matrix substrate and display panel
US11610922B2 (en) Array substrate and display panel design improving aperture ratio
KR101486180B1 (en) A method for manufacturing active matrix substrate, display panel, and display device
US20200174300A1 (en) Display panel, method for manufacturing same, and display device
JP5120828B2 (en) Thin film transistor substrate and manufacturing method thereof, and liquid crystal display panel having the same and manufacturing method
JP2007173652A (en) Thin-film transistor, manufacturing method therefor, and display device having the same
KR20140003481A (en) Semiconductor device and display device
WO2011136071A1 (en) Semiconductor device, and manufacturing method for same
JP2002182243A (en) Transistor substrate for liquid crystal display and method for manufacturing the same
US8362623B2 (en) Semiconductor device and method for manufacturing the same
US20120307173A1 (en) Display device and method for fabricating the same
US10651209B2 (en) Semiconductor device and method for manufacturing same
JP4398601B2 (en) THIN FILM TRANSISTOR ARRAY SUBSTRATE, THIN FILM TRANSISTOR ARRAY SUBSTRATE MANUFACTURING METHOD, AND DISPLAY DEVICE
KR101484966B1 (en) Array substrate and method of fabricating the same
WO2011135896A1 (en) Semiconductor device, and manufacturing method for same
JPH0682826A (en) Active matrix substrate and its production
US20070153170A1 (en) Method of fabricating pixel structure
JP2010097077A (en) Display device and manufacturing method thereof
US9081243B2 (en) TFT substrate, method for producing same, and display device
JP2019169606A (en) Active matrix substrate and method of manufacturing the same
JP2010210732A (en) Liquid crystal display panel and method of manufacturing the same

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 11774681

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 11774681

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: JP