WO2011132310A1 - Information processing device and semiconductor storage device - Google Patents
Information processing device and semiconductor storage device Download PDFInfo
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- WO2011132310A1 WO2011132310A1 PCT/JP2010/057248 JP2010057248W WO2011132310A1 WO 2011132310 A1 WO2011132310 A1 WO 2011132310A1 JP 2010057248 W JP2010057248 W JP 2010057248W WO 2011132310 A1 WO2011132310 A1 WO 2011132310A1
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- optical signal
- data
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
- G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
- G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
- G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C2029/0411—Online error correction
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/005—Transfer gates, i.e. gates coupling the sense amplifier output to data lines, I/O lines or global bit lines
Definitions
- the present invention relates to an information processing apparatus and a semiconductor memory device.
- the DDR3 DRAM used as the main memory constitutes a 64-bit width module at 1.6 Gbps per bit, and a data rate of 38.4 GB / s is obtained by using three modules in parallel.
- a memory module having a data rate of 1 TB / s will be required in the future.
- the transmission speed per pin is required to be 32 Gbps.
- the transmission speed exceeds 10 Gbps, even when the transmission is performed at a distance of several tens of centimeters as in a printed circuit board, when an electric signal is used, reflection and interference of the signal become significant, and stable high-speed transmission becomes difficult. Therefore, it is desirable to use a transmission means with low loss and less interference such as optical transmission.
- Patent Document 1 discloses an information processing system that performs transmission using an optical interface between a CPU and a memory MEM, as shown in FIG.
- a CPU a bus control device (BUS CNTL), an electricity ⁇ light conversion unit (E ⁇ O), and a photoelectric conversion unit (O ⁇ E) are mounted on the host device (HOST).
- the bus control device the write data from the CPU is passed through a DC balance converter (DC-ENC), converted into serial data by a multiplexer (MUX), and then a check bit is added by an ECC encoder (ECC-ENC). The electrical-to-optical conversion is performed, and the optical signal is output to the optical bus (OPIO).
- DC-ENC DC balance converter
- MUX multiplexer
- ECC-ENC ECC encoder
- This write data is input to the photoelectric conversion unit (O ⁇ E) on the memory device (MEM BRD), and the error is corrected by the ECC decoder (ECC-DEC) on the bus control device (BUS MEM CNTL) on the memory device. After that, the data is converted into parallel data by a demultiplexer (DMUX) and then written to a memory (MEM).
- ECC-DEC ECC decoder
- read data read from the memory is error-corrected by the ECC decoder (ECC-DEC) of the bus controller (BUS MEM CNTL) on the memory device, and then converted to serial data by the multiplexer (MUX) The electrical-to-optical conversion is performed, and the optical signal is output to the optical bus (OPIO).
- This read data is input to the photoelectric conversion unit (O ⁇ E) on the host device (HOST), error-corrected by the ECC decoder (ECC-DEC) on the bus control device (BUS CNTL), and then demultiplexer ( DMUX) is converted into parallel data, and then read through the DC balance inverse converter (DC-DEC) to the CPU.
- ECC decoder ECC decoder
- MUX demultiplexer
- Patent Document 2 describes an example in which parallel data transmission is performed between a memory module in which a plurality of memory chips are arranged and a CPU in order to further improve the data transfer speed using such an optical interface.
- a plurality of memory chips MEMIC
- MEMMOD memory module substrate
- FIG. 30B these are an optical bus (OPIO), an input / output adapter ( Sends and receives data to and from the memory controller (MEM CNTL) via IOADPT.
- a converter (CONV) that performs parallel / serial conversion of data, an optical-electrical signal conversion circuit (OE), an address buffer (CAB), and a clock driver (CKD) are arranged on the memory module.
- the clock (LCLK) of the optical signal is supplied to the memory chip, converter, and address buffer in the module by the clock driver (CKD), and data transmission of each chip is performed in synchronization with LCLK.
- the data rate of the signal line by one optical interface is increased to 32 Gbps.
- the data rate is 32 Gbps, one bit is set. Since the transmission time is shortened to about 30 ps, it is very difficult to achieve such synchronization.
- the circuit delay for each signal generally differs depending on device variations and circuit placement locations on the chip. In order to synchronize such signals, it is necessary to add a variable delay circuit to each signal and change the delay amount so that the rising timing of the signal matches the rising timing of the clock. However, since even a wiring delay on a module of about 10 cm is several tens of ps, it is difficult to synchronize signal lines having a period of about 30 ps.
- an object of the present invention is to mount a plurality of memory chips, connect a plurality of signal lines output from the memory chip to an optical memory bus connected to a system LSI or CPU by an optical interface, and synchronize each signal line. It is to provide a memory module capable of speeding up to several tens of Gbps and stably transmitting data.
- each DRAM chip is divided into a plurality of DRAM cores, and the interface chip is divided into interface cores corresponding to each DRAM core.
- the DRAM core transmits / receives a command / address signal and a data signal to / from a corresponding memory controller core using a single optical interface via a corresponding interface chip.
- the command address signal and data signal include clock phase information.
- the clock recovery circuit recovers the clock from the command address signal and data signal, In addition to receiving an address and data, each DRAM core operates at an independent timing by this clock.
- FIG. 3 is a configuration diagram showing a plurality of DRAM cores in a DRAM chip and an interface core in an interface chip stacked thereon. It is a block diagram which shows the example which laminated
- FIG. 16 is a diagram illustrating an internal configuration example of one DRAM core disposed in the DRAM chip of FIG. 15.
- FIG. 20 is a diagram showing through via input / output circuits used in the DRAM core of FIG. 16 and the interface core of FIG. 19. It is a figure which shows the operation
- FIG. 20 is a block diagram which shows the structural example of the interface chip by the side of DRAM.
- FIG. 21 is a circuit diagram showing a connection example of a memory array, a sub word driver column, and a sense amplifier column used in the memory bank of FIG. 20.
- FIG. 21 is a circuit diagram showing an example (open bit line system) of a memory array used in the memory bank of FIG. 20.
- FIG. 21 is a circuit diagram illustrating a configuration example of a sense amplifier used in the memory bank of FIG. 20.
- FIG. 21 is a circuit diagram showing a configuration example of a sub word driver used in the memory bank of FIG. 20.
- optical bus using a wavelength multiplexing system It is a block diagram of the CPU side interface core using a wavelength division multiplexing system. It is a block diagram which shows the example of the memory using the conventional optical bus. It is a block diagram which shows the example of the memory module using the conventional optical bus.
- the PMOS transistor is distinguished from the NMOS transistor by adding an arrow symbol to the gate.
- the connection of the substrate potential of the MOS transistor is not specified, but the connection method is not particularly limited as long as the MOS transistor can operate normally.
- the memory module of the present embodiment described below uses a plurality of bit width optical interfaces between a system LSI or CPU chip having a plurality of CPU cores and a dynamic random access memory (DRAM).
- the memory core is divided into a plurality of memory cores that can communicate independently and can be operated independently, and the memory core corresponding to each CPU core uses a 1-bit optical interface to perform data input / output with an independent clock.
- This technology is useful when the CPU or system LSI with the configuration is connected to the DRAM via an optical interface. Not only this, but also when a logic chip such as an ASIC or DSP and a memory such as SRAM or FLASH are connected via an optical interface. Applicable.
- FIG. 1 is a conceptual diagram showing a configuration example of a plurality of DRAM chips (DRAMIC0-7) and interface chips (IFDIC0-7) in a memory module according to an embodiment of the present invention.
- the DRAM chip and the interface chip are stacked and mounted using a three-dimensional connection technique such as a through via.
- the DRAM chip includes four DRAM cores (DRAMC0-3)
- the interface chip includes four interface cores (IFDC0-3)
- each DRAM core uses an interface core having a corresponding number.
- the CPU transmits and receives data.
- Each DRAM core has a clock (CK), a command address signal (CAI), and a data signal (DQI) independently.
- Each DRAM core accepts an input of a command address at an independent timing, and inputs and outputs data. Is possible.
- Each interface core has a corresponding memory controller (described later) via an optical waveguide (WG) corresponding to one command / address optical signal (CA) and an optical waveguide corresponding to one data optical signal (DQ). Perform data transfer.
- WG optical waveguide
- CA command / address optical signal
- DQ data optical signal
- This module shows an example of an optical bus (OPIO) in which eight DRAM chips each having four DRAM cores are mounted and which is composed of 32 command / address optical waveguides and data optical waveguides.
- DRAMC0 DRAM core
- IFDC0 interface core
- IFD chip IFD chip
- a command / address clock (CKA) is taken out by a clock recovery circuit (CDR), and a command / address signal (CAI) converted into parallel data is taken in by using the command / address clock (CKA).
- the command address clock is input to the frequency divider (DIV), and a DRAM clock (CK) having a long period is generated.
- the command / address signal is input to the DRAM core (DRAMC0) by the DRAM clock, and operations such as writing and reading are started.
- DQI parallel data
- IFDC0 interface core
- CKA command / address clock
- CDR clock recovery circuit
- write data is input from the memory controller using an optical waveguide corresponding to the data signal (DQ0).
- DQ0 data signal
- These are multi-bit data on the CPU core, but are converted to serial data and transmitted to the data input / output terminal (DQ) on the interface core (IFDC0) for transmission as a single optical signal.
- the clock recovery circuit takes out the data clock (CKD) and uses it to take in the data signal (DQI) converted into parallel data.
- This data is input to the DRAM core (DRAMC0) by the DRAM clock (CK), and a write operation is performed.
- the memory controller can perform data transmission independently of many DRAM cores.
- the CPU side also has a many-core configuration, and this memory module can process independent memory accesses from a large number of cores at the same time, which can greatly improve the calculation performance.
- each interface core extracts the clock from the command / address signal and the data signal itself, transmits data at its own timing, and each DRAM core operates at an independent timing. There is no need to synchronize, and high-speed transmission of several tens of Gbps can be stably performed.
- FIG. 2 shows a timing diagram of data transmission / reception in the DRAM chip and the interface chip.
- DRAMC0 data transmission / reception of the DRAM core (DRAMC0, 1) on the DRAM chip (DRAMIC0) and the DRAM core (DRAMC3) on the DRAM chip (DRAMIC7) is shown.
- an activation command (ACT) and a row address (AX) are input as optical serial signals to CA0 of the corresponding interface core.
- a command / address clock (CKA) is taken out by a clock recovery circuit (CDR) and converted into a parallel signal (CAI).
- the activation command and the row address are transmitted to the DRAM core in synchronization with the DRAM clock (CK) generated by dividing the command / address clock, and the operation of the DRAM is started.
- a read command (READ) and a column address (AY) are input to CA0 and similarly transmitted to the DRAM core, and read data is read out.
- the data signal DQI output from the DRAM core is output as the data optical signal DQ0 from the interface core in synchronization with CKA.
- an activation command (ACT) and a row address (AX) are input as serial signals of optical signals to the corresponding interface core CA1, and transmitted to the DRAM core in the same manner as above.
- ACT activation command
- AX row address
- CA1 write command
- AY column address
- DQI parallel data signal
- the memory controller can perform data transmission independently of many DRAM cores.
- the CPU side also has a many-core configuration, and this memory module can process independent memory accesses from a large number of cores at the same time, which can greatly improve the calculation performance.
- each interface core extracts the clock from the command / address signal and the data signal itself, transmits data at its own timing, and each DRAM core operates at an independent timing. There is no need to synchronize, and high-speed transmission of several tens of Gbps can be stably performed.
- FIG. 3 is a diagram showing a state in which two DRAM modules (DRAMMOD0, 1) of the present invention and a CPU chip (CPUIC) are connected to an optical bus (OPIO).
- DRAMMOD0, 1 DRAM modules
- CPUIC CPU chip
- a plurality of DRAM chips (DRAMIC0-N) and interface chips (IFDIC0-N) are arranged on the DRAM module.
- the DRAM chip and the interface chip are stacked and mounted using a three-dimensional connection technique such as a through via.
- a plurality of CPU cores (CPUC0-M) and a plurality of memory controller blocks (MCB0-N) are arranged on the CPU.
- a signal output from the memory controller block is connected to an optical bus via an interface chip (IFCIC).
- IFCIC interface chip
- each memory controller block transmits and receives data only to and from the corresponding DRAM chip on each DRAM module. For example, if a memory access requested from a certain CPU core is received by a memory controller core included in the memory controller block 0, this memory controller core is the DRAM core included in the DRAM chip 0 on the DRAM module 0 or the DRAM module 1. To read and write data. In this way, since a plurality of memory controller cores can read and write data with the DRAM core at independent timing, it is not necessary to synchronize between different signals on the optical bus, and high-speed transmission is possible. It becomes possible.
- FIG. 4 is a diagram showing a connection relationship between the memory controller block (MCB0) on the CPU chip (CPUIC) and the DRAM chip (DRAMIC0) on the DRAM module (DRAMMOD0).
- MB0 memory controller block
- DRAMC0-3 DRAM cores
- IFDC interface cores
- a control circuit (CNTL) and four memory controller cores (MCC0-3) are arranged in the memory controller block (MCB0), and four interface cores (IFCC) are arranged on the interface chip (IFCIC).
- the DRAM core transmits / receives data to / from the memory controller core using the corresponding interface core.
- Each DRAM core has a DRAM clock (CK), a command / address signal (CAI), and a data signal (DQI) independently.
- CK DRAM clock
- CAI command / address signal
- DQI data signal
- Each interface core transfers data to and from a corresponding memory controller via an optical waveguide (WG) corresponding to one command / address optical signal (CA) and an optical waveguide corresponding to one data optical signal (DQ). I do.
- WG optical waveguide
- CA command / address optical signal
- DQ data optical signal
- this memory module will be described by taking the DRAM core 0 on the DRAM chip 0 and the MC core 0 on the CPU chip as an example.
- a case where a memory access input from a certain CPU core on the CPU chip to the memory controller block 0 is processed by the MC core 0 by the control circuit is shown.
- the MC core 0 inputs a multi-bit command / address signal (CAI) for the DRAM core 0 and a CPU clock (CKC) to the interface core (IFCC).
- CKC CPU clock
- the input CPU clock is multiplied by a PLL to generate a high-speed command / address clock (CKA).
- the command address (CAI) is converted into serial data in synchronization with CKA, then converted into an optical signal, and output from the command / address optical terminal (CAP) to the optical waveguide (CA0).
- This command / address signal is input as serial data to the command / address input terminal (CA) on the interface core (IFDC0).
- CA command / address input terminal
- IFDC0 interface core
- the data read from the DRAM core is converted into serial data. After the conversion, it is converted into an optical signal and output to the optical waveguide corresponding to the data signal (DQ0).
- This data is input to an interface core (IFCC) on an interface chip on the CPU side, converted from an optical signal to an electrical signal, and then a data clock (CKD) is taken out and used by a clock recovery circuit (CDR).
- CDR clock recovery circuit
- the data signal (DQI) converted into parallel data is taken in. This data is transmitted to the memory controller core (MCC0) by the CPU clock (CKC).
- a parallel data signal (DQI) is input from MCC0 to IFCC in synchronization with the memory controller clock, and serial data is synchronized with the command / address clock (CKA) in the clock recovery circuit (CDR). Is converted to an optical signal, output to the optical waveguide corresponding to the data signal (DQ0), and transmitted to the interface core (IFDC) on the DRAM-side interface chip. This data is transmitted to the DRAM core as described above, and writing is performed.
- DQI parallel data signal
- CKA command / address clock
- CDR clock recovery circuit
- one memory controller core and one DRAM core perform serial transmission using one command / address signal and one data signal, so that the memory controller is independent of many DRAM cores. Data transmission can be performed. Therefore, when connected to a CPU having a many-core configuration, the present memory module can simultaneously process independent memory accesses from a large number of CPU cores, so that the calculation performance can be greatly improved.
- each interface core extracts the clock from the command / address signal and the data signal itself, transmits data at its own timing, and each DRAM core operates at an independent timing. There is no need to synchronize, and high-speed transmission of several tens of Gbps can be stably performed.
- each core can operate in parallel with other cores. That is, each channel can transmit and receive data regardless of the state of other cores.
- each CPU core and DRAM core can operate in parallel, that is, by having a channel that can operate regardless of the state of other CPU cores and DRAM cores.
- it is possible to operate at any timing, unlike the case where the channel is shared, so an arbitration and synchronization mechanism is not required, and the information processing system
- the hardware configuration and the software configuration are simplified.
- FIG. 5 shows a block diagram when a DRAM chip (DRAMIC0), an interface chip (IFDIC), and a printed circuit board (BASE) are stacked by using a through via (VIA).
- Through-vias can have an interface with chips stacked above and below a specific chip by vias penetrating the chip.
- the DRAM chip includes four DRAM cores (DRAMC0-3), and the interface chip includes four interface cores (IFDC0-3).
- the DRAM core transmits / receives data to / from the CPU using an interface core having a corresponding number.
- each DRAM core can independently input / output a DRAM clock (CK), a command / address signal (CAI), and a data signal (DQI), a clock terminal (CKP), a command / address terminal ( Data is transmitted to and received from the interface core via a data input / output terminal (DQIP). It is possible to input and output data individually by receiving command and address inputs at independent timings.
- CK DRAM clock
- CAI command / address signal
- DQI data signal
- CKP clock terminal
- DQIP data input / output terminal
- the interface core includes a command / address optical terminal (CAP) and a data optical terminal (DQP) for inputting an optical signal from an optical waveguide through a printed circuit board, and a clock terminal (CKP) and a command / address terminal ( Data is transmitted to and received from the DRAM core via the CAIP) and data terminal (DQIP).
- the optical interface circuit (OPIF) performs conversion from an optical signal to an electrical signal and conversion from an electrical signal to an optical signal.
- the clock recovery circuit (CDR) performs clock extraction from the command / address signal and data signal, data capture, conversion from serial data to parallel data, and conversion from parallel data to serial data.
- the frequency divider divides the clock CKA extracted from the command / address signal and generates a DRAM clock (CK) having a low frequency.
- the power of the DRAM core and interface core is supplied from the printed circuit board to the power supply pad (VSP) in each core through a through via.
- the number of signal lines between the chips can be increased, thereby dividing the DRAM and the interface chip into a plurality of cores, which are independent of each other. It is possible to operate with a clock.
- FIG. 6 shows a block diagram when four DRAM chips (DRAMIC0-3), an interface chip (IFDIC), and a printed circuit board (BASE) are stacked using through vias (VIA).
- Through-vias can have an interface with chips stacked above and below a specific chip by vias penetrating the chip.
- DRAMC0 DRAM core
- IFDC0 interface core
- other DRAM cores are similarly connected to the interface core.
- the DRAM C0 included on the four chips uses IFDC0 to transmit and receive data to and from the CPU as in the case of FIG.
- a command decoder (CDC) is provided on the interface core, and a command / address signal (CAI) is sent to one of a plurality of stacked chips in accordance with an address from the memory controller core. ).
- CDC command decoder
- CAI command / address signal
- each chip has an independent chip selection signal or an ID number is assigned to each chip.
- FIG. 7 shows the structure of an optical interface / memory bus in which a memory module using an optical interface of the present invention and a CPU chip are connected by an optical waveguide.
- a sectional view is shown in (a), and a part of the top view is shown in (b).
- the DRAM module is configured by laminating a plurality of DRAM chips (DRAMIC) and an interface chip (IFDIC) on a printed circuit board (BASE).
- the CPU module (CPUMOD) is configured by stacking a CPU chip (CPUIC) and an interface chip (IFCIC) on a printed circuit board (BASE). These modules are arranged on a board substrate (SUB).
- a plurality of optical waveguides (WG) are wired in the board substrate, and optical signals are transmitted between corresponding terminals of the CPU module and the DRAM module. Can be transmitted.
- an optical coupler (COUP) is provided at the lower part of each DRAM module, and an optical signal input from the CPU can be branched from the optical waveguide at a certain rate and guided to the module. .
- the end portion of the optical waveguide is subjected to antireflection coating (AR), and almost 100% is transmitted without reflection of light.
- AR antireflection coating
- no signal reflection or interference occurs on the optical waveguide, and a stable signal with less waveform distortion can be transmitted.
- ML mirror structure having a surface inclined by 45 degrees with respect to the light traveling direction is created and reflected by 90 degrees.
- FIG. 8 shows the configuration of the interface core (IFDC) on the memory side interface chip (IFDIC), and its operation will be described with reference to the waveforms in FIG.
- the command / address optical signal (CA) is input from the memory controller to the command / address optical terminal (CAP) using the optical waveguide.
- This optical signal is converted into a current signal by a photodetector (PD) in an optical interface circuit (OPIF1), and then converted into a voltage signal by a transimpedance amplifier (TIA). From this signal, the command / address clock (CKA) is taken out in the PLL in the clock recovery circuit (CDR1).
- Command / address serial data (CAIS) latched by CKA is parallelized by a demultiplexer (DMUX).
- DMUX demultiplexer
- the transmitted serial data is 8 / 10B encoded so that the time during which the data does not change does not continue for a certain time or longer on the memory controller side. This is decoded by an 8 / 10B decoder (8 / 10BDEC) to convert it into a command / address signal (CAI) of parallel data and transmitted to the DRAM chip via an interface terminal (CAIP) of an electric signal.
- CAI includes address (A0-A10), bank address (BA0-BA1), row address strobe signal (RASB), column address strobe signal (CASB), write enable (WEB), chip selection signal (CSB), reset signal ( RESETB).
- FIG. 9 shows an example in which an activate command (ACT) and a row address (AX) are transmitted first, followed by a read command (READ) and a column address (AY).
- the command / address clock is input to the frequency dividing circuit (DIV) to generate a DRAM clock (CK) having a long period, and this is also transmitted to the DRAM chip via the clock terminal (CKP).
- the command / address signal is input to the DRAM core by the DRAM clock, and operations such as writing and reading are started.
- a parallel data signal (DQI) read from the DRAM core is input to the electrical signal interface terminal (DQIP) of the interface core (IFDC) by the DRAM clock.
- DQIP includes a DQ terminal (DQI0-3) and a data mask (DM).
- the parallel data is encoded by the 8 / 10B encoder (8 / 10BENC) so that the time during which the data does not change when serialized in the clock recovery circuit (CDR2) does not continue for a predetermined time or longer, and then the command address It is converted into serial output data (DOS) by a multiplexer (MUX) and a DQ latch in synchronization with the clock (CKA).
- MUX multiplexer
- CKA DQ latch
- the light output from the laser (LD) is converted into the data optical signal (DQ) by the modulator (MOD), and the light is transmitted from the data optical terminal (DQP) as shown in FIG. It is output to the waveguide and transmitted to the memory controller.
- an optical signal (DQ) corresponding to the write data is input from the memory controller to the data optical terminal (DQP) using the optical waveguide.
- This optical signal is converted into a current signal by a photodetector (PD) in an optical interface circuit (OPIF2), and then converted into a voltage signal by a transimpedance amplifier (TIA).
- the data clock (CKD) is taken out in the PLL in the clock recovery circuit (CDR2).
- Serial input data (DIS) taken in by the DQ latch by CKD is parallelized by the demultiplexer (DMUX).
- the transmitted serial data is 8 / 10B encoded so that the time during which the data does not change does not continue for a certain time or longer on the memory controller side.
- 8 / 10B decoder 8 / 10BDEC
- DQI write data signal
- DQIP electrical signal interface terminal
- each interface core extracts the clock from the command / address signal and the data signal itself, performs data transmission at its own timing, and each DRAM core operates at independent timing. It is not necessary to synchronize between them, and high-speed transmission of several tens of Gbps can be stably performed.
- FIG. 12 shows the configuration of the interface core (IFCC) on the CPU side interface chip (IFCIC).
- a command / address signal (CAI) of parallel data is input from the memory controller core to the command / address terminal (CAIP) by the CPU clock (CKC).
- CAI includes address (A0-A10), bank address (BA0-BA1), row address strobe signal (RASB), column address strobe signal (CASB), write enable (WEB), chip select (CS), and reset signal (RESETB). ) Is included.
- the parallel data is first encoded by the 8 / 10B encoder (8 / 10BENC) in the clock recovery circuit (CDR3) so that the time during which the data does not change when serialized does not continue for a certain time or longer, and then the CKC Is converted into command / address serial data (CAIS) by a multiplexer (MUX) and a latch in synchronization with a high-speed command / address clock (CKA) multiplied by PLL. Then, in the optical interface (OPIF3), the light output from the laser (LD) is converted into a command / address optical signal (CA) by a modulator (MOD), and the command / address optical terminal (CAP) is converted into an optical waveguide. Is output and transmitted to the DRAM module.
- CAIS command / address serial data
- MUX multiplexer
- CKA high-speed command / address clock
- a parallel data signal (DQI) transmitted from the memory controller core is input to the data terminal (DQIP) of the interface core (IFCC) by the CPU clock (CKC).
- DQIP includes a DQ terminal (DQI0-3) and a data mask (DM).
- the parallel data is encoded by the 8 / 10B encoder (8 / 10BENC) so that the time during which the data does not change when serialized in the clock recovery circuit (CDR2) does not continue for a predetermined time or longer, and then the command address In synchronization with the clock (CKA), the data is converted into serial output data (DOS) by a multiplexer (MUX) and a latch.
- DOS serial output data
- MUX multiplexer
- the light output from the laser (LD) is converted into the data optical signal (DQ) by the modulator (MOD), and output from the data optical terminal (DQP) to the optical waveguide, and the DRAM Transmitted to the module.
- an optical signal (DQ) corresponding to the read data is input from the DRAM module to the data optical terminal (DQP) using an optical waveguide.
- This optical signal is converted into a current signal by a photodetector (PD) in an optical interface circuit (OPIF2), and then converted into a voltage signal by a transimpedance amplifier (TIA).
- the data clock (CKD) is taken out in the PLL in the clock recovery circuit (CDR2).
- Serial input data (DIS) fetched by the CKD latch is parallelized by the demultiplexer (DMUX).
- the transmitted serial data is 8 / 10B encoded so that the time during which the data does not change does not continue for a certain time or longer on the memory controller side.
- 8 / 10B decoder 8 / 10BDEC
- read data (DQI) converted into parallel data is generated and transmitted to the DRAM chip via the data terminal (DQIP).
- each interface core extracts the clock from the command / address signal and the data signal itself, transmits data at its own timing, and each memory controller core operates at an independent timing. There is no need to synchronize the lines, and high-speed transmission of several tens of Gbps can be stably performed.
- FIG. 13 shows a configuration in the case where the memory side interface chip (IFDIC) shown in FIG. 8 is divided into an optical interface chip (IFD-OIC) and an electrical interface chip (IFD-EIC).
- IFD-OIC optical interface chip
- IFD-EIC electrical interface chip
- a plurality of optical interface cores (IFD-OC) are arranged in the optical interface chip
- a plurality of electric interface cores (IFD-EC) are arranged in the electric interface chip, and one set is shown in the figure.
- the operation of the circuit block included in each core is the same as that in FIG. 8, but for the command / address signal, the output of the optical interface circuit (OPIF1) in the optical interface core is sent via the command / address serial terminal (CASP).
- OPIF1 command / address serial terminal
- the clock recovery circuit (CDR1) in the electrical interface core To the through via (VIA), and this is input to the clock recovery circuit (CDR1) in the electrical interface core.
- the input signal (DIS) and output signal (DOS) of the clock recovery circuit in the electrical interface core are output to the through via via the serial input data terminal (DSP) and the serial output data terminal (QSP).
- the optical interface circuit (OPIF2) in the optical interface core is connected.
- FIG. 14 shows an example in which the electrical interface core (IFD-EC) of FIG. 13 is integrated on a DRAM chip.
- a plurality of DRAM cores and an electrical interface core are mounted on the DRAM chip, but only one set is shown here.
- the operation of each circuit block is the same as in FIG. In this case, the characteristics of the optical element can be improved by using a compound semiconductor substrate such as GaAs or InP for the optical interface chip as in FIG. 13, and the DRAM chip and the optical interface chip can be directly connected. Since there is no need to increase the number of chips, the cost of the package can be reduced.
- FIG. 15 is a plan view showing the configuration of a DRAM chip (DRAMIC).
- DRAM cores such as a plurality of DRAM cores (MEM0 to 7 (corresponding to DRAMC in FIG. 1 and the like; the same applies hereinafter)
- MEM0 to 7 corresponding to DRAMC in FIG. 1 and the like; the same applies hereinafter
- a transmission / reception circuit a power generation circuit, and the like in the chip.
- There are provided circuits hereinafter referred to as a common circuit (COMC)
- BUS bus
- a command / address terminal (CAIP) and a data terminal (DQIP) are arranged on the second side located on the chip center side.
- CAIP command / address terminal
- DQIP data terminal
- FIG. 16 is a plan view showing an internal configuration example of one DRAM core (MEM).
- a command / address terminal (CAIP), a data terminal (DQIP), and a clock terminal (CKP) are arranged on one side of the core.
- a plurality of memory banks (BANK) are arranged, and a read / write circuit (R / W AMP) is arranged between the memory bank and the data terminal.
- Defect relief fuses (FUSE) are arranged on both sides of the core.
- the command signals are a reset signal, a row address strobe, a column address strobe, a write enable and a chip select signal, and input / output terminals corresponding to these are provided in the command / address terminal area.
- Each input / output terminal is provided with a TSV input / output circuit to receive a command signal.
- the address signal is also input via a TSV input / output circuit provided for each terminal corresponding to the address signal (A0-A10) or the bank address signal (BA0-1).
- the command / address control circuit determines the operation mode of the DRAM chip, predecodes the address, controls the operation timing, and the like.
- the data signal is input / output to / from the data terminal (DQIP) via the TSV input / output circuit.
- the data signal includes a data input / output signal (DQ0-3) and a data mask signal (DML).
- DQ0-3 data input / output signal
- DML data mask signal
- the command / address terminal of the interface chip is arranged vertically below the printed circuit board (PCB) of the command / address terminal (CAIP) of the DRAM chip, and the printed circuit board (PCB) of the data terminal (DQIP) of the DRAM chip.
- the interface chip (IFDIC) and the DRAM chip (DRAMIC) are stacked and mounted so that the data terminals of the interface chip are arranged vertically below.
- a memory array (ARY) arranged in a plurality of arrays is arranged, and a sense amplifier array (SAA) and a sub word driver array (SWDA) are arranged around it. Be placed.
- a column decoder (YDEC) is arranged in parallel with the sense amplifier column on the outer periphery of the memory bank, a row decoder (XDEC) is arranged in parallel with the sub word driver column (SWDA), and an array control circuit is arranged in addition.
- the number of bits of the data input / output circuit is 4, but as an example, when a DRAM core is created as a DDR2-SDRAM base, 16 bits of data are paralleled in the memory array. The data is read out, converted into parallel-serial by a 4-to-1 multiplexer, and then output outside the chip.
- the DRAM core is based on DDR3-SDRAM or other DRAM, and the number of address terminals and data pins can be changed.
- FIG. 17 shows a TSV input / output circuit (TSVC) used in the DRAM core of FIG. 16 and the CPU core of FIG.
- This circuit includes an output circuit (OBC3) and an input circuit (IBC3), and a plurality of such circuits are provided on a DRAM chip (DRAMIC) and an interface chip (IFDIC).
- a through via pad (PAD) is provided at the ND terminal of the input / output circuit on the DRAM chip, and a similar pad is also provided at the NS terminal of the input / output circuit on the interface chip.
- the output circuit (OBC3) is activated on the DRAM chip to cause a potential change in ND. Since ND and NS are connected by the through via, this potential change is directly transmitted to the terminal NS on the interface chip side, amplified by the input circuit (IBC3), and reproduced as digital data.
- the output circuit is activated on the interface chip to generate a potential change in NS, and a voltage is applied to a terminal ND on the DRAM side connected to NS via. Is generated. This voltage is amplified by an input circuit on the DRAM side and reproduced into digital data.
- the operation will be described by paying attention to a set of TSV input / output circuits (TSVC) for receiving data.
- OBC3 the MOS transistors MP5 and MN5 are turned off when the output enable signal (OED) is in the inactive state (VSS).
- OED output enable signal
- VSS inactive state
- DOD data output terminal
- MN5 is turned on and ND is driven to VSS.
- the voltage of NS is pulled toward VSS.
- This signal is amplified by the amplifier circuit (AMP), the latch signal (LTS) is activated, the VSS level data is latched by the latch circuit (LTC), and is output to the data input terminal (DIS).
- DOD is VDD
- signal transitions having opposite polarities occur, and a VDD level signal is output to DIS.
- the through via method is characterized in that the voltage of VDD or VSS output from the output circuit is input to the input circuit, so that the circuit is simple and the reliability of signal transmission is high.
- FIG. 19 is a plan view showing a configuration of an interface chip chip (IFDIC).
- IFDIC interface chip chip
- IFDC0 to IFDC7 a plurality of interface cores capable of operating in parallel
- a circuit commonly provided for a plurality of DRAM cores such as a transmission / reception circuit and a power generation circuit (hereinafter referred to as a common circuit (COMC)).
- a bus (BUS) is wired between them.
- a command / address input terminal (CAIP) and a data input / output terminal (DQIP) are arranged on the second side located on the chip center side.
- CAIP command / address input terminal
- DQIP data input / output terminal
- FIG. 20 shows a configuration example inside the memory bank (BANK) in the DRAM core of FIG.
- a memory array (ARY) arranged in a plurality of arrays is arranged, and a sense amplifier array (SAA), a sub word driver array (SWDA), and a cross area (XP) are arranged around the memory array (ARY).
- a column decoder (YDEC) and a main amplifier column are arranged on the outer periphery of the memory bank (BANK) in parallel with the sense amplifier column, and a row decoder (XDEC) and an array control circuit (ACC) in parallel with the sub word driver column. Is placed.
- FIG. 21 is a plan view showing an example of a detailed arrangement relationship between the sense amplifier row and the sub word driver row in the DRAM core of FIG.
- the sense amplifiers (SA) in the sense amplifier array (SAA) are alternately arranged on the left and right with respect to the memory array (ARY), and are commonly connected to the bit line pairs (BLT / BLB) in the left and right memory arrays.
- the sub word drivers (SWD) in the sub word driver array (SWDA) are alternately arranged above and below the memory array and commonly connected to the word lines (WL) in the upper and lower memory arrays.
- the pitch between the sense amplifiers in the sense amplifier row can be increased to twice the pitch between the bit lines in the memory array, and between the sub word drivers in the sub word driver row. Can be increased to twice the pitch between the word lines in the memory array, so that miniaturization is facilitated.
- a local I / O line (LIO) is arranged in the sense amplifier row, and the local I / O line is connected to the main I / O line (MIO) via the switch (SW) in the cross area (XP). .
- FIG. 22 is a circuit diagram showing an example of the configuration of the memory array in the DRAM core of FIG.
- the memory array (ARY) is composed of a plurality of memory cells (MC).
- Each memory cell is a DRAM memory cell, and is composed of one MOS transistor (memory cell transistor) and one capacitor (Cs).
- One of the source and the drain of the memory cell transistor is connected to the bit line (BLT) or the reference bit line (BLB), the other of the source and the drain is connected to the storage node (SN), and the gate is the word line (WL). It is connected to the.
- One terminal of the capacitor (Cs) is connected to the storage node SN, and the other terminal is connected to the common plate (PL).
- the bit line and the reference bit line function as a bit line pair (complementary bit line) and are connected to the same sense amplifier.
- the sense amplifier rows are alternately arranged on the left and right with respect to the memory array, are connected in common to the bit line pairs in the left and right memory arrays, and are shared by both. Accordingly, in each sense amplifier row, adjacent sense amplifiers are arranged with a space corresponding to one bit line pair. By adopting such an arrangement, the pitch between the sense amplifiers is relaxed, so that the layout becomes easy and miniaturization becomes possible.
- an open bit line type array is used, and memory cells are arranged at the intersections of all word lines and bit lines. This has the effect of reducing the memory cell size.
- FIG. 23 is a circuit diagram showing an example of a sense amplifier in the DRAM core of FIG.
- the sense amplifier includes a precharge circuit (PCC), a cross couple amplifier (CC), and a read / write port (IOP).
- the precharge circuit equalizes the paired bit lines (BLT / BLB) when the bit line precharge signal (BLEQ) is activated, and precharges the bit line precharge level (VBLR).
- bit line voltage (VDL) is set to the same level as the power supply voltage (VCC) from the outside of the chip or a level obtained by stepping down the same.
- the bit line precharge level is set to this midpoint (VDL / 2).
- the P-side common source line (CSP) is set to the bit line voltage and the N-side common source line (CSN) is set to the ground potential.
- This circuit is driven to (VSS), amplifies the higher voltage of complementary bit lines to VDL, amplifies the lower voltage to VSS, and latches the amplified voltage.
- the read / write port (IOP) is a circuit that connects the local I / O line (LIOT / B) and the bit line pair when the column selection line (YS) is activated.
- the local I / O line is held at the precharge level during standby in order to prevent current consumption in the non-selected sense amplifier array.
- FIG. 24 is a circuit diagram showing an example of the configuration of the sub-word driver string in the DRAM core of FIG.
- the sub word driver array (SWDA) is composed of a plurality of sub word drivers (SWD). As shown in FIG. 21, the sub word driver column is arranged around the memory array.
- the sub word driver drives the word lines (WL) in the memory arrays arranged above and below. Further, since the sub word driver columns are alternately arranged with respect to the memory array, every other word line in the memory array is connected to the upper and lower sub word drivers.
- the sub word driver is composed of two N channel MOS transistors and one P channel MOS transistor.
- One N-channel MOS transistor has a gate connected to the main word line (MWLB), a drain connected to the word line, and a source connected to the voltage VKK.
- the other N-channel MOS transistor has a gate connected to a complementary sub word driver select line (FXB), a drain connected to a word line (WL), and a source connected to a voltage VKK.
- VKK is a standby word line voltage, which is generated by a voltage generation circuit (VGC) and is a negative voltage lower than the ground potential (VSS).
- the main word line is connected to the gate, the word line is connected to the drain, and the sub word driver selection line (FX) is connected to the source.
- FX sub word driver selection line
- Four sets of sub word driver selection lines (FX0 to FX4) are wired on one sub word driver column, and one of the four sub word drivers selected by one main word line is selected to be one The word line is activated.
- FIG. 25 is a circuit diagram showing an example of a cross area configuration in the DRAM core of FIG.
- the cross area (XP) includes a first local I / O line precharge circuit (LEQ1), a second local I / O line precharge circuit (LEQ2), a read / write gate (RGC), and a CS line driver ( CSD), CS line precharge circuit (SEQ), BLEQ signal driver (EQD), and FX line driver (FXD) are arranged.
- LQ1 first local I / O line precharge circuit
- LEQ2 second local I / O line precharge circuit
- RRC read / write gate
- CSD CS line driver
- SEQ CS line precharge circuit
- EQD BLEQ signal driver
- FXD FX line driver
- the first local I / O line precharge circuit precharges the local I / O line (LIO / LIOB) to VDL / 2 when the complementary precharge signal (BLEQB) is active.
- the second local I / O line precharge circuit precharges the local I / O line (LIO / LIOB) with the peripheral circuit voltage (VCL) when the read equalize signal (REQB) is active.
- the read / write gate is a circuit that connects a local I / O line (LIO / LIOB) and a main I / O line (MIO / MIOB) when a gate signal (TG / TGB) is activated. is there.
- the CS line driver drives the N-side common source line (CSN) to the ground voltage (VSS), and the P-side sense amplifier enable signal (SAP1B).
- the CS line precharge circuit is a circuit that precharges the P-side and N-side common source lines to VDL / 2 when a complementary precharge signal is activated.
- the BLEQ signal driver receives a complementary signal (BLEQB) of the precharge signal (BLEQ) and outputs an inverted signal thereof.
- the FX line driver receives the complementary sub word driver selection line (FXB) and outputs the inverted signal to the sub word driver line (FX).
- FIG. 26 is a diagram showing a state where two DRAM modules (DRAMMOD0, 1) of the present invention and a CPU chip (CPUIC) are connected to an optical bus (OPIO).
- DRAMMOD0, 1 DRAM modules
- CPUIC CPU chip
- OPIO optical bus
- this memory controller core uses an optical signal of wavelength ⁇ 0 to access DRAMIC0 on DRAMMOD0, and DRAMMOD1
- an optical signal having a wavelength ⁇ 1 is used.
- Optical signals having wavelengths of ⁇ 0 and ⁇ 1 are multiplexed on the optical waveguide constituting the optical bus, and transmission and reception can be performed without interfering with each other at the same time.
- one memory controller core can simultaneously access the DRAM cores on a plurality of DRAM modules, so the data transfer speed can be increased without increasing the number of optical waveguides. It becomes possible.
- FIG. 27 shows a cross-sectional view of an optical interface memory bus in which a memory module using an optical interface of the present invention and a CPU chip are connected by an optical waveguide.
- the optical coupler / filter COUP & FLT
- the optical coupler / filter at the bottom of each DRAM module receives an optical signal of a specific wavelength from an optical waveguide from an optical signal having a plurality of wavelengths ( ⁇ 0, ⁇ 1) input from the CPU. It is a point that can be branched to a module and led to a module.
- the length of the optical coupler / filter is L0, and the distance from the optical waveguide is D0, so that only the optical signal having the wavelength ⁇ 0 is branched.
- the length of the optical coupler / filter is L1, and the distance from the optical waveguide is D1, so that only the optical signal having the wavelength ⁇ 1 is branched.
- one memory controller core can simultaneously access the DRAM cores on a plurality of DRAM modules, so that the data transfer speed can be increased without increasing the number of optical waveguides. It becomes possible.
- FIG. 28 shows the configuration of the interface core (IFCC) on the CPU side interface chip (IFCIC) when performing wavelength multiplexing communication.
- the operation of the circuit blocks of the optical interfaces (OPIF2, OPIF3) and clock recovery circuits (CDR2, CDR3) is the same as that shown in FIG.
- the command address signal (CAI) of the electrical signals from CPU core 0 and CPU core 1 is converted into optical signals of wavelengths ⁇ 0 and ⁇ 1 by the clock recovery circuit (CDR3) and the optical interface (OPIF3), respectively. Then, they are multiplexed by a multiplexer (MIXW) and output by one optical interface terminal (CAP).
- MIXW multiplexer
- CAP optical interface terminal
- the write data of the electrical signals from the memory controller core 0 and the memory controller core 1 is the wavelength ⁇ 0, ⁇ 1 by the clock recovery circuit (CDR2) and the optical interface (OPIF2), respectively, as (DQIP) indicated earlier Are multiplexed by a multiplexer (MIXW), and output by one optical interface terminal (DQP).
- the read data the read data input to one optical interface terminal (DQP) is divided into optical signals of wavelengths ⁇ 0 and ⁇ 1 by a demultiplexer (DIVW), and the optical interface (OPIF2) and clock recovery circuit ( The signals are converted into parallel electrical signals by the CDR 2) and input to the memory controller core 0 and the memory controller 1.
- one memory controller core can simultaneously access the DRAM cores on a plurality of DRAM modules, so the data transfer speed can be increased without increasing the number of optical waveguides. It becomes possible.
- the invention described in this embodiment is based on the data rate of the signal line per line using an optical interface in a memory module in which a plurality of multi-core DRAM chips are arranged. Can be improved to several tens of Gbps, and even when tens of signal lines are input / output from the memory module, stable data transmission is possible, which contributes to an improvement in system performance.
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Abstract
There is a demand to increase the data transfer speed between dynamic random access memory (DRAM) and a system LSI or CPU chip having multiple CPU cores. In order to meet this demand, a memory module is disclosed which is mounted with multiple DRAM chips and multiple interface chips corresponding to each of the chips. Each DRAM chip is divided into multiple DRAM cores, and the interface chips are divided into interface cores corresponding to each DRAM core. Via the corresponding interface chip, the DRAM cores send and receive command address signals and data signals to and from the corresponding memory controller core by using each single optical interface.
Description
本発明は、情報処理装置ならびに半導体記憶装置に関する。
The present invention relates to an information processing apparatus and a semiconductor memory device.
現在、システムLSIやマイクロプロセッサにおいては、内部にCPU(中央演算処理装置)コアを複数設けるマルチコア構成が広まってきている。マルチコア構成をとると、チップのクロック周波数を過度に高めることなく、演算性能を増加することができるため、消費電力を低く抑えることができる特徴がある。1チップに搭載されるCPUコア数については、パソコンやサーバ向けマイクロプロセッサでは2から4コアを搭載しはじめており、今後はこの数が100以上に増加することも予想される。このようにCPUコア数が増加すると、それに伴って計算に必要なデータレートが高まる。
Currently, in system LSIs and microprocessors, a multi-core configuration in which a plurality of CPU (Central Processing Unit) cores are provided inside has become widespread. When the multi-core configuration is adopted, the calculation performance can be increased without excessively increasing the clock frequency of the chip, so that power consumption can be kept low. As for the number of CPU cores mounted on one chip, microprocessors for personal computers and servers are beginning to mount 2 to 4 cores, and this number is expected to increase to 100 or more in the future. As the number of CPU cores increases in this way, the data rate required for calculation increases accordingly.
現状、主記憶として用いられるDDR3 DRAMは1ビットあたり1.6Gbpsで64ビット幅のモジュールを構成し、これを3個並列に用いることで、38.4GB/sのデータレートを得ている。しかしながら、今後もデータレート向上の要求は高まるため、将来は1TB/sのデータレートを持つメモリモジュールが必要になる。
Currently, the DDR3 DRAM used as the main memory constitutes a 64-bit width module at 1.6 Gbps per bit, and a data rate of 38.4 GB / s is obtained by using three modules in parallel. However, since the demand for increasing the data rate will continue to increase, a memory module having a data rate of 1 TB / s will be required in the future.
このような高速な主記憶を実現するには、64ビットのバス幅のモジュールを、4個並列に用いたとしても、ピンあたりの伝送速度は32Gbpsが必要となる。10Gbpsを超えるとプリント基板のような数十センチの距離の伝送でも、電気信号を用いた場合、信号の反射や干渉が顕著になり、安定的な高速伝送が困難になる。したがって、光伝送のような低損失で干渉の少ない伝送手段を用いることが望ましい。
In order to realize such a high-speed main memory, even if four modules having a 64-bit bus width are used in parallel, the transmission speed per pin is required to be 32 Gbps. When the transmission speed exceeds 10 Gbps, even when the transmission is performed at a distance of several tens of centimeters as in a printed circuit board, when an electric signal is used, reflection and interference of the signal become significant, and stable high-speed transmission becomes difficult. Therefore, it is desirable to use a transmission means with low loss and less interference such as optical transmission.
特許文献1には、図29に示すように、CPUとメモリMEMの間で光インターフェースを用いて伝送をおこなう情報処理システムが示されている。ここで、ホスト装置(HOST)上にはCPU、バス制御装置(BUS CNTL)、電気→光変換部(E→O)、光電気変換部(O→E)が搭載されている。バス制御装置ではCPUからのライトデータに対してDCバランス変換部(DC-ENC)を通し、マルチプレクサ(MUX)でシリアルデータに変換した後、ECCエンコーダ(ECC-ENC)でチェックビットを付加した後、電気→光変換が行われ、光バス(OPIO)に光信号として出力される。このライトデータはメモリ装置(MEM BRD)上の光電気変換部(O→E)に入力され、メモリ装置上のバス制御装置(BUS MEM CNTL)上のECCデコーダ(ECC-DEC)において誤り訂正された後、デマルチプレクサ(DMUX)でパラレルデータに変換された後、メモリ(MEM)に書き込まれる。
Patent Document 1 discloses an information processing system that performs transmission using an optical interface between a CPU and a memory MEM, as shown in FIG. Here, a CPU, a bus control device (BUS CNTL), an electricity → light conversion unit (E → O), and a photoelectric conversion unit (O → E) are mounted on the host device (HOST). In the bus control device, the write data from the CPU is passed through a DC balance converter (DC-ENC), converted into serial data by a multiplexer (MUX), and then a check bit is added by an ECC encoder (ECC-ENC). The electrical-to-optical conversion is performed, and the optical signal is output to the optical bus (OPIO). This write data is input to the photoelectric conversion unit (O → E) on the memory device (MEM BRD), and the error is corrected by the ECC decoder (ECC-DEC) on the bus control device (BUS MEM CNTL) on the memory device. After that, the data is converted into parallel data by a demultiplexer (DMUX) and then written to a memory (MEM).
逆に、メモリから読み出されたリードデータはメモリ装置上のバス制御装置(BUS MEM CNTL)のECCデコーダ(ECC-DEC)で誤り訂正された後、マルチプレクサ(MUX)によりシリアルデータに変換した後、電気→光変換が行われ、光バス(OPIO)に光信号として出力される。このリードデータはホスト装置(HOST)上の光電気変換部(O→E)に入力され、バス制御装置(BUS CNTL)上のECCデコーダ(ECC-DEC)において誤り訂正された後、デマルチプレクサ(DMUX)でパラレルデータに変換された後、DCバランス逆変換部(DC-DEC)を通し、CPUに読み出される。
Conversely, read data read from the memory is error-corrected by the ECC decoder (ECC-DEC) of the bus controller (BUS MEM CNTL) on the memory device, and then converted to serial data by the multiplexer (MUX) The electrical-to-optical conversion is performed, and the optical signal is output to the optical bus (OPIO). This read data is input to the photoelectric conversion unit (O → E) on the host device (HOST), error-corrected by the ECC decoder (ECC-DEC) on the bus control device (BUS CNTL), and then demultiplexer ( DMUX) is converted into parallel data, and then read through the DC balance inverse converter (DC-DEC) to the CPU.
このような光インターフェースを用いて、さらにデータ転送速度を向上するために、メモリチップを複数配置したメモリモジュールとCPUの間で、並列データ伝送を行う例が特許文献2に記載されている。図30(a)に示すように、複数のメモリチップ(MEMIC)がメモリモジュール基板(MEMMOD)上に配置され、これらが図30(b)に示すように光バス(OPIO)、入出力アダプタ(IOADPT)を介して、メモリーコントローラ(MEM CNTL)とデータの送受信を行う。メモリモジュール上にはデータのパラレル・シリアル変換を行うコンバータ(CONV)と、光―電気信号変換回路(OE)、アドレスバッファ(CAB)、クロックドライバ(CKD)が配置されている。本構成では光信号のクロック(LCLK)がクロックドライバ(CKD)でモジュール内のメモリチップ、コンバータ、アドレスバッファに供給され、LCLKに同期して各チップのデータ伝送が行われる。
Patent Document 2 describes an example in which parallel data transmission is performed between a memory module in which a plurality of memory chips are arranged and a CPU in order to further improve the data transfer speed using such an optical interface. As shown in FIG. 30A, a plurality of memory chips (MEMIC) are arranged on a memory module substrate (MEMMOD), and as shown in FIG. 30B, these are an optical bus (OPIO), an input / output adapter ( Sends and receives data to and from the memory controller (MEM CNTL) via IOADPT. A converter (CONV) that performs parallel / serial conversion of data, an optical-electrical signal conversion circuit (OE), an address buffer (CAB), and a clock driver (CKD) are arranged on the memory module. In this configuration, the clock (LCLK) of the optical signal is supplied to the memory chip, converter, and address buffer in the module by the clock driver (CKD), and data transmission of each chip is performed in synchronization with LCLK.
マルチコア構成のシステムLSIやマイクロプロセッサとDRAMとの間で1TB/sのデータレートを実現するためには、前記のように一本の光インターフェースによる信号線のデータレートを32Gbpsにまで向上し、これを64ビット構成としてモジュールとし、さらに4モジュールを並列動作する必要がある。特許文献2で示した方式によれば、複数のチップから出力される多数のビットをモジュール内で単一のクロックに対してタイミングを同期させる必要があるが、データレートが32Gbpsになると1ビットを伝送する時間は約30psに短縮されるため、このような同期をとることが非常に困難になる。
In order to achieve a data rate of 1 TB / s between a multi-core system LSI or microprocessor and DRAM, as described above, the data rate of the signal line by one optical interface is increased to 32 Gbps. Must be a 64-bit configuration and 4 modules must be operated in parallel. According to the method shown in Patent Document 2, it is necessary to synchronize the timing of a large number of bits output from a plurality of chips with respect to a single clock within the module. However, when the data rate is 32 Gbps, one bit is set. Since the transmission time is shortened to about 30 ps, it is very difficult to achieve such synchronization.
信号ごとの回路遅延は、デバイスばらつきやチップ上の回路配置場所によって一般に異なっている。このような信号間の同期をとるためには各信号に可変遅延回路を追加し、信号の立ち上がりタイミングと、クロックの立ち上がりタイミングが一致するように、遅延量を変化させる必要がある。しかしながら、10cm程度のモジュール上の配線遅延だけでも数十psになるため、約30psの周期を持つ信号線の同期をとることは困難である。
The circuit delay for each signal generally differs depending on device variations and circuit placement locations on the chip. In order to synchronize such signals, it is necessary to add a variable delay circuit to each signal and change the delay amount so that the rising timing of the signal matches the rising timing of the clock. However, since even a wiring delay on a module of about 10 cm is several tens of ps, it is difficult to synchronize signal lines having a period of about 30 ps.
そこで、本発明の課題は複数のメモリチップを搭載し、メモリチップから出力される複数の信号線を光インターフェースによってシステムLSIやCPUと接続する光メモリバスに接続し、各信号線間の同期をとらずに数十Gbpsまで高速化し、安定的にデータ伝送可能なメモリモジュールを提供することである。
Therefore, an object of the present invention is to mount a plurality of memory chips, connect a plurality of signal lines output from the memory chip to an optical memory bus connected to a system LSI or CPU by an optical interface, and synchronize each signal line. It is to provide a memory module capable of speeding up to several tens of Gbps and stably transmitting data.
本願において開示される発明のうち、代表的な実施の形態の概要を簡単に説明すれば、次のとおりである。
Among the inventions disclosed in the present application, the outline of a typical embodiment will be briefly described as follows.
複数のDRAMチップと、各チップに対応した複数のインターフェースチップが搭載されたメモリモジュールにおいて、各DRAMチップは複数のDRAMコアに分割され、インターフェースチップには、各DRAMコアに対応したインターフェースコアに分割され、DRAMコアは対応したインターフェースチップを介して、対応したメモリコントローラコアとコマンド・アドレス信号、データ信号を各一本の光インターフェースを用いて送受信することを特徴とする。
In a memory module equipped with a plurality of DRAM chips and a plurality of interface chips corresponding to each chip, each DRAM chip is divided into a plurality of DRAM cores, and the interface chip is divided into interface cores corresponding to each DRAM core. The DRAM core transmits / receives a command / address signal and a data signal to / from a corresponding memory controller core using a single optical interface via a corresponding interface chip.
また、コマンド・アドレス信号、データ信号にクロックの位相情報が含まれており、それぞれのDRAMコアに対応したインターフェースコアにおいて、クロック再生回路でコマンド・アドレス信号、データ信号からクロックを再生してコマンド・アドレスとデータを受信するとともに、本クロックにより各DRAMコアが独立したタイミングで動作することを特徴とする。
The command address signal and data signal include clock phase information. In the interface core corresponding to each DRAM core, the clock recovery circuit recovers the clock from the command address signal and data signal, In addition to receiving an address and data, each DRAM core operates at an independent timing by this clock.
本願において開示される発明のうち、代表的な実施の形態によって得られる効果を簡単に説明すれば、システムの処理性能を高めることができる。
Of the inventions disclosed in this application, the processing performance of the system can be enhanced by simply explaining the effects obtained by the representative embodiments.
以下、本発明の実施の形態を図面に基づいて詳細に説明する。なお、実施の形態を説明するための全図において、同一の部材には原則として同一の符号を付し、その繰り返しの説明は省略する。また、図面において、PMOSトランジスタにはゲートに矢印の記号を付すことで、NMOSトランジスタと区別することとする。また、図面において、MOSトランジスタの基板電位の接続は明記していないが、MOSトランジスタが正常動作可能な範囲であれば、その接続方法は特に限定しない。
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted. In the drawings, the PMOS transistor is distinguished from the NMOS transistor by adding an arrow symbol to the gate. Further, in the drawing, the connection of the substrate potential of the MOS transistor is not specified, but the connection method is not particularly limited as long as the MOS transistor can operate normally.
なお、以降で述べる本実施の形態のメモリモジュールは、複数のCPUコアを有するシステムLSIまたはCPUチップと、ダイナミック型ランダムアクセスメモリ(DRAM)との間で複数のビット幅の光インターフェースを用いてデータ通信を行い、DRAM内部が独立動作可能な複数のメモリコアに分割され、それぞれのCPUコアと対応したメモリコアが1ビットの光インターフェースを用いて独立のクロックでデータ入出力を行う技術に関し、メニイコア構成のCPUやシステムLSIとDRAMを光インターフェースで接続した場合に有益な技術であり、これに限らず、ASICやDSP等のロジックチップとSRAM、FLASH等のメモリを光インターフェースで接続した場合にも適用可能である。
Note that the memory module of the present embodiment described below uses a plurality of bit width optical interfaces between a system LSI or CPU chip having a plurality of CPU cores and a dynamic random access memory (DRAM). The memory core is divided into a plurality of memory cores that can communicate independently and can be operated independently, and the memory core corresponding to each CPU core uses a 1-bit optical interface to perform data input / output with an independent clock. This technology is useful when the CPU or system LSI with the configuration is connected to the DRAM via an optical interface. Not only this, but also when a logic chip such as an ASIC or DSP and a memory such as SRAM or FLASH are connected via an optical interface. Applicable.
図1は、本発明の一実施の形態によるメモリモジュールにおいて、複数のDRAMチップ(DRAMIC0-7)とインターフェースチップ(IFDIC0-7)からなる構成例を示した概念図である。DRAMチップとインターフェースチップとは貫通ビア等の三次元接続技術を用いて積層されて実装される。ここではDRAMチップには4個のDRAMコア(DRAMC0-3)が含まれ、インターフェースチップには4個のインターフェースコア(IFDC0-3)が含まれ、DRAMコアはそれぞれ対応する番号のインターフェースコアを用いて、CPUとデータの送受信を行う。各DRAMコアはクロック(CK)、コマンド・アドレス信号(CAI)、データ信号(DQI)を独立に有しており、それぞれ独立したタイミングで、個々にコマンド・アドレスの入力を受け付け、データの入出力が可能である。
FIG. 1 is a conceptual diagram showing a configuration example of a plurality of DRAM chips (DRAMIC0-7) and interface chips (IFDIC0-7) in a memory module according to an embodiment of the present invention. The DRAM chip and the interface chip are stacked and mounted using a three-dimensional connection technique such as a through via. Here, the DRAM chip includes four DRAM cores (DRAMC0-3), the interface chip includes four interface cores (IFDC0-3), and each DRAM core uses an interface core having a corresponding number. The CPU transmits and receives data. Each DRAM core has a clock (CK), a command address signal (CAI), and a data signal (DQI) independently. Each DRAM core accepts an input of a command address at an independent timing, and inputs and outputs data. Is possible.
各インターフェースコアはそれぞれ一本のコマンド・アドレス光信号(CA)に対応した光導波路(WG)と一本のデータ光信号(DQ)に対応した光導波路を介して、対応した後述するメモリコントローラとデータ転送を行う。本モジュールでは4個のDRAMコアからなるDRAMチップを8個搭載し、32本のコマンド・アドレス光導波路とデータ光導波路で構成される光バス(OPIO)の例を示している。
Each interface core has a corresponding memory controller (described later) via an optical waveguide (WG) corresponding to one command / address optical signal (CA) and an optical waveguide corresponding to one data optical signal (DQ). Perform data transfer. This module shows an example of an optical bus (OPIO) in which eight DRAM chips each having four DRAM cores are mounted and which is composed of 32 command / address optical waveguides and data optical waveguides.
DRAMチップ(DRAMIC0)上のDRAMコア(DRAMC0)とIFDチップ(IFDIC0)上のインターフェースコア(IFDC0)を例にとって本メモリモジュール動作を説明するが、他のDRAMコアとインターフェースコアも同様な動作を行う。はじめに、メモリコントローラからコマンド・アドレス信号(CA0)に対応した光導波路を介してコマンドとアドレスが入力される。これらはCPUコア上では多ビットからなるデータであるが、一本の光信号で伝送するために、シリアルデータに変換されてインターフェースコア(IFDC0)上のコマンド・アドレス光端子(CA)に入力される。この光信号を電気信号に変換した後、クロック再生回路(CDR)において、コマンド・アドレスクロック(CKA)が取り出され、それを用いてパラレルデータに変換されたコマンド・アドレス信号(CAI)が取り込まれる。コマンド・アドレスクロックは分周回路(DIV)に入力され、周期が長いDRAMクロック(CK)が生成される。コマンド・アドレス信号はDRAMクロックにより、DRAMコア(DRAMC0)に入力され、ライト、リード等の動作が開始される。
The operation of the memory module will be described by taking the DRAM core (DRAMC0) on the DRAM chip (DRAMIC0) and the interface core (IFDC0) on the IFD chip (IFDIC0) as examples, but other DRAM cores and interface cores also perform the same operation. . First, a command and an address are input from the memory controller via an optical waveguide corresponding to the command / address signal (CA0). These are multi-bit data on the CPU core, but are converted to serial data and transmitted to the command / address optical terminal (CA) on the interface core (IFDC0) for transmission as a single optical signal. The After this optical signal is converted into an electrical signal, a command / address clock (CKA) is taken out by a clock recovery circuit (CDR), and a command / address signal (CAI) converted into parallel data is taken in by using the command / address clock (CKA). . The command address clock is input to the frequency divider (DIV), and a DRAM clock (CK) having a long period is generated. The command / address signal is input to the DRAM core (DRAMC0) by the DRAM clock, and operations such as writing and reading are started.
リード動作の場合DRAMコアから読み出されたパラレルデータ(DQI)がDRAMクロックによりインターフェースコア(IFDC0)に入力され、クロック再生回路(CDR)において、コマンド・アドレスクロック(CKA)に同期してシリアルデータに変換された後、光信号に変換されて、データ光信号(DQ0)に対応した光導波路に出力され、メモリコントローラに伝送される。
In the read operation, parallel data (DQI) read from the DRAM core is input to the interface core (IFDC0) by the DRAM clock, and serial data is synchronized with the command / address clock (CKA) in the clock recovery circuit (CDR). Is converted into an optical signal, output to the optical waveguide corresponding to the data optical signal (DQ0), and transmitted to the memory controller.
ライト動作の場合には、メモリコントローラからデータ信号(DQ0)に対応した光導波路を用いて、ライトデータが入力される。これらはCPUコア上では多ビットからなるデータであるが、一本の光信号で伝送するために、シリアルデータに変換されてとしてインターフェースコア(IFDC0)上のデータ入出力端子(DQ)に入力される。この光信号を電気信号に変換した後、クロック再生回路(CDR)において、データクロック(CKD)が取り出され、それを用いてパラレルデータに変換されたデータ信号(DQI)が取り込まれる。このデータはDRAMクロック(CK)により、DRAMコア(DRAMC0)に入力され、ライト動作が行われる。
In the case of a write operation, write data is input from the memory controller using an optical waveguide corresponding to the data signal (DQ0). These are multi-bit data on the CPU core, but are converted to serial data and transmitted to the data input / output terminal (DQ) on the interface core (IFDC0) for transmission as a single optical signal. The After this optical signal is converted into an electrical signal, the clock recovery circuit (CDR) takes out the data clock (CKD) and uses it to take in the data signal (DQI) converted into parallel data. This data is input to the DRAM core (DRAMC0) by the DRAM clock (CK), and a write operation is performed.
この構成により、メモリコントローラは多数のDRAMコアと独立してデータ伝送を行うことができる。後述するように現状の多数のシステムではCPU側もメニイコア構成となっており、本メモリモジュールは多数のコアからの独立したメモリアクセスを同時に処理できるため、演算性能を大幅に向上することができる。また、それぞれのインターフェースコアがコマンド・アドレス信号、データ信号自体からクロックを取り出し、独自のタイミングでデータ伝送を行い、またそれぞれのDRAMコアが独立したタイミングで動作を行うため、多数の信号線間で同期をとる必要がなく、数十Gbpsの高速伝送を安定的に行うことが可能となる。
With this configuration, the memory controller can perform data transmission independently of many DRAM cores. As will be described later, in a large number of current systems, the CPU side also has a many-core configuration, and this memory module can process independent memory accesses from a large number of cores at the same time, which can greatly improve the calculation performance. In addition, each interface core extracts the clock from the command / address signal and the data signal itself, transmits data at its own timing, and each DRAM core operates at an independent timing. There is no need to synchronize, and high-speed transmission of several tens of Gbps can be stably performed.
図2にDRAMチップおよびインターフェースチップにおけるデータ送受信のタイミング図を示す。ここではDRAMチップ(DRAMIC0)上のDRAMコア(DRAMC0,1)およびDRAMチップ(DRAMIC7)上のDRAMコア(DRAMC3)のデータ送受信を示している。
FIG. 2 shows a timing diagram of data transmission / reception in the DRAM chip and the interface chip. Here, data transmission / reception of the DRAM core (DRAMC0, 1) on the DRAM chip (DRAMIC0) and the DRAM core (DRAMC3) on the DRAM chip (DRAMIC7) is shown.
DRAMチップ(DRAMIC0)上のDRAMコア(DRAMC0)においては、まず、対応したインターフェースコアのCA0に光シリアル信号としてアクティベートコマンド(ACT)と行アドレス(AX)が入力される。これからクロック再生回路(CDR)でコマンド・アドレスクロック(CKA)が取り出され、パラレル信号(CAI)に変換される。コマンド・アドレスクロックから分周して作られたDRAMクロック(CK)に同期してDRAMコアにアクティベートコマンドと行アドレスが伝送され、DRAMの動作が開始される。続いて、CA0にリードコマンド(READ)と列アドレス(AY)が入力され、同様にDRAMコアに伝送され、リードデータの読み出しが行われる。DRAMコアから出力されたデータ信号DQIはCKAに同期してインターフェースコアからデータ光信号DQ0として出力される。
In the DRAM core (DRAMC0) on the DRAM chip (DRAMIC0), first, an activation command (ACT) and a row address (AX) are input as optical serial signals to CA0 of the corresponding interface core. From this, a command / address clock (CKA) is taken out by a clock recovery circuit (CDR) and converted into a parallel signal (CAI). The activation command and the row address are transmitted to the DRAM core in synchronization with the DRAM clock (CK) generated by dividing the command / address clock, and the operation of the DRAM is started. Subsequently, a read command (READ) and a column address (AY) are input to CA0 and similarly transmitted to the DRAM core, and read data is read out. The data signal DQI output from the DRAM core is output as the data optical signal DQ0 from the interface core in synchronization with CKA.
DRAMチップ0上のDRAMコア1においては、まず、対応したインターフェースコアのCA1に光信号のシリアル信号としてアクティベートコマンド(ACT)と行アドレス(AX)が入力され、上と同様にDRAMコアに伝送されて、DRAMの動作が開始される。続いて、CA1にライトコマンド(WRITE)と列アドレス(AY)が入力される。インターフェースコアに光信号としてライトデータDQ1が入力される。これからクロック再生回路(CDR)でデータクロック(CKD)が取り出され、パラレルなデータ信号(DQI)に変換される。これらのコマンド・列アドレスとデータがメモリコアに伝送されて、ライト動作が行われる。図に示すようにDRAMコア1の動作タイミング、クロックはDRAMコア0と独立している。
In the DRAM core 1 on the DRAM chip 0, first, an activation command (ACT) and a row address (AX) are input as serial signals of optical signals to the corresponding interface core CA1, and transmitted to the DRAM core in the same manner as above. Thus, the operation of the DRAM is started. Subsequently, a write command (WRITE) and a column address (AY) are input to CA1. Write data DQ1 is input as an optical signal to the interface core. From this, a data clock (CKD) is taken out by a clock recovery circuit (CDR) and converted into a parallel data signal (DQI). These command / column address and data are transmitted to the memory core, and a write operation is performed. As shown in the figure, the operation timing and clock of the DRAM core 1 are independent of those of the DRAM core 0.
DRAMチップ7上のDRAMコア3においても、DRAMチップ0上のDRAMコア0と同様にアクティベートコマンドとリードコマンドが実行される例を示したが、本動作もDRAMチップ0上のDRAMコア0とは同期をとらず、完全に独立したタイミングで動作を行う。
The example in which the activate command and the read command are executed in the DRAM core 3 on the DRAM chip 7 as well as the DRAM core 0 on the DRAM chip 0 has been shown. It operates at completely independent timing without synchronization.
この構成により、メモリコントローラは多数のDRAMコアと独立してデータ伝送を行うことができる。後述するように現状の多数のシステムではCPU側もメニイコア構成となっており、本メモリモジュールは多数のコアからの独立したメモリアクセスを同時に処理できるため、演算性能を大幅に向上することができる。また、それぞれのインターフェースコアがコマンド・アドレス信号、データ信号自体からクロックを取り出し、独自のタイミングでデータ伝送を行い、またそれぞれのDRAMコアが独立したタイミングで動作を行うため、多数の信号線間で同期をとる必要がなく、数十Gbpsの高速伝送を安定的に行うことが可能となる。
With this configuration, the memory controller can perform data transmission independently of many DRAM cores. As will be described later, in a large number of current systems, the CPU side also has a many-core configuration, and this memory module can process independent memory accesses from a large number of cores at the same time, which can greatly improve the calculation performance. In addition, each interface core extracts the clock from the command / address signal and the data signal itself, transmits data at its own timing, and each DRAM core operates at an independent timing. There is no need to synchronize, and high-speed transmission of several tens of Gbps can be stably performed.
図3は2個の本発明のDRAMモジュール(DRAMMOD0,1)とCPUチップ(CPUIC)が光バス(OPIO)に接続される様子を示す図である。DRAMモジュール上には複数のDRAMチップ(DRAMIC0-N)とインターフェースチップ(IFDIC0-N)が配置される。DRAMチップとインターフェースチップとは貫通ビア等の三次元接続技術を用いて積層されて実装される。CPU上には複数のCPUコア(CPUC0-M)と複数のメモリコントローラブロック(MCB0-N)が配置される。メモリコントローラブロックから出た信号はインターフェースチップ(IFCIC)を介して光バスに接続される。
FIG. 3 is a diagram showing a state in which two DRAM modules (DRAMMOD0, 1) of the present invention and a CPU chip (CPUIC) are connected to an optical bus (OPIO). A plurality of DRAM chips (DRAMIC0-N) and interface chips (IFDIC0-N) are arranged on the DRAM module. The DRAM chip and the interface chip are stacked and mounted using a three-dimensional connection technique such as a through via. A plurality of CPU cores (CPUC0-M) and a plurality of memory controller blocks (MCB0-N) are arranged on the CPU. A signal output from the memory controller block is connected to an optical bus via an interface chip (IFCIC).
ここで、個々のメモリコントローラブロック(MCB0―N)は各DRAMモジュール上の対応するDRAMチップとのみデータの送受信を行う。例えば、あるCPUコアから要求されたメモリアクセスがメモリコントローラブロック0に含まれるメモリコントローラコアで受け付けられたとすると、このメモリコントローラコアはDRAMモジュール0またはDRAMモジュール1上のDRAMチップ0に含まれるDRAMコアにアクセスを行い、データのリードライトを行う。このようにすることで、複数のメモリコントローラコアが独立したタイミングで、DRAMコアとデータのリードライトを行うことができるため、光バスにおいて、異なる信号間で同期を取る必要がなく、高速伝送が可能になる。
Here, each memory controller block (MCB0-N) transmits and receives data only to and from the corresponding DRAM chip on each DRAM module. For example, if a memory access requested from a certain CPU core is received by a memory controller core included in the memory controller block 0, this memory controller core is the DRAM core included in the DRAM chip 0 on the DRAM module 0 or the DRAM module 1. To read and write data. In this way, since a plurality of memory controller cores can read and write data with the DRAM core at independent timing, it is not necessary to synchronize between different signals on the optical bus, and high-speed transmission is possible. It becomes possible.
図4はCPUチップ(CPUIC)上のメモリコントローラブロック(MCB0)とDRAMモジュール(DRAMMOD0)上のDRAMチップ(DRAMIC0)との接続関係を示した図である。ここではDRAMチップには4個のDRAMコア(DRAMC0-3)が配置され、インターフェースチップ(IFDIC0)には4個のインターフェースコア(IFDC)が配置される。またメモリコントローラブロック(MCB0)には制御回路(CNTL)と4個のメモリコントローラコア(MCC0-3)が配置され、インターフェースチップ(IFCIC)上には4個のインターフェースコア(IFCC)が配置される。
FIG. 4 is a diagram showing a connection relationship between the memory controller block (MCB0) on the CPU chip (CPUIC) and the DRAM chip (DRAMIC0) on the DRAM module (DRAMMOD0). Here, four DRAM cores (DRAMC0-3) are arranged in the DRAM chip, and four interface cores (IFDC) are arranged in the interface chip (IFDIC0). In addition, a control circuit (CNTL) and four memory controller cores (MCC0-3) are arranged in the memory controller block (MCB0), and four interface cores (IFCC) are arranged on the interface chip (IFCIC). .
DRAMコアはそれぞれ対応するインターフェースコアを用いて、メモリコントローラコアとデータの送受信を行う。各DRAMコアはDRAMクロック(CK)、コマンド・アドレス信号(CAI)、データ信号(DQI)を独立に有しており、それぞれ独立したタイミングで、個々にコマンド・アドレスの入力を受け付け、データの入出力が可能である。
The DRAM core transmits / receives data to / from the memory controller core using the corresponding interface core. Each DRAM core has a DRAM clock (CK), a command / address signal (CAI), and a data signal (DQI) independently. Each DRAM core accepts an input of a command address at an independent timing and inputs data. Output is possible.
各インターフェースコアはそれぞれ一本のコマンド・アドレス光信号(CA)に対応した光導波路(WG)と一本のデータ光信号(DQ)に対応した光導波路を介して、対応したメモリコントローラとデータ転送を行う。
Each interface core transfers data to and from a corresponding memory controller via an optical waveguide (WG) corresponding to one command / address optical signal (CA) and an optical waveguide corresponding to one data optical signal (DQ). I do.
DRAMチップ0上のDRAMコア0とCPUチップ上のMCコア0を例にとって本メモリモジュールの動作を説明するが、他のDRAMコアとメモリコントローラコアも同様な動作を行う。CPUチップ上のあるCPUコアからメモリコントローラブロック0に入力されたメモリアクセスが制御回路により、MCコア0で処理される場合を示す。MCコア0はDRAMコア0に対する多ビットのコマンド・アドレス信号(CAI)、CPUクロック(CKC)をインターフェースコア(IFCC)に入力する。インターフェースコア上では入力されたCPUクロックをPLLで逓倍し、高速なコマンド・アドレスクロック(CKA)を生成する。クロック再生回路CDRにおいてコマンドアドレス(CAI)はCKAに同期してシリアルデータに変換された後、光信号に変換されて、コマンド・アドレス光端子(CAP)から光導波路(CA0)に出力される。
The operation of this memory module will be described by taking the DRAM core 0 on the DRAM chip 0 and the MC core 0 on the CPU chip as an example. A case where a memory access input from a certain CPU core on the CPU chip to the memory controller block 0 is processed by the MC core 0 by the control circuit is shown. The MC core 0 inputs a multi-bit command / address signal (CAI) for the DRAM core 0 and a CPU clock (CKC) to the interface core (IFCC). On the interface core, the input CPU clock is multiplied by a PLL to generate a high-speed command / address clock (CKA). In the clock recovery circuit CDR, the command address (CAI) is converted into serial data in synchronization with CKA, then converted into an optical signal, and output from the command / address optical terminal (CAP) to the optical waveguide (CA0).
このコマンド・アドレス信号はシリアルデータとしてインターフェースコア(IFDC0)上のコマンド・アドレス入力端子(CA)に入力され、先に述べたようにリード動作の場合DRAMコアから読み出されたデータがシリアルデータに変換された後、光信号に変換されて、データ信号(DQ0)に対応した光導波路に出力される。このデータはCPU側のインターフェースチップ上のインターフェースコア(IFCC)に入力され、光信号から電気信号に変換された後、クロック再生回路(CDR)において、データクロック(CKD)が取り出され、それを用いてパラレルデータに変換されたデータ信号(DQI)が取り込まれる。このデータはCPUクロック(CKC)により、メモリコントローラコア(MCC0)に伝達される。
This command / address signal is input as serial data to the command / address input terminal (CA) on the interface core (IFDC0). As described above, in the read operation, the data read from the DRAM core is converted into serial data. After the conversion, it is converted into an optical signal and output to the optical waveguide corresponding to the data signal (DQ0). This data is input to an interface core (IFCC) on an interface chip on the CPU side, converted from an optical signal to an electrical signal, and then a data clock (CKD) is taken out and used by a clock recovery circuit (CDR). The data signal (DQI) converted into parallel data is taken in. This data is transmitted to the memory controller core (MCC0) by the CPU clock (CKC).
ライト動作の場合は逆に、MCC0からIFCCにパラレルデータ信号(DQI)がメモリコントローラクロックに同期して入力され、クロック再生回路(CDR)において、コマンド・アドレスクロック(CKA)に同期してシリアルデータに変換された後、光信号に変換されて、データ信号(DQ0)に対応した光導波路に出力され、DRAM側のインターフェースチップ上のインターフェースコア(IFDC)に伝送される。このデータは先に述べたようにDRAMコアに伝送され、ライトが実行される。
Conversely, in the case of a write operation, a parallel data signal (DQI) is input from MCC0 to IFCC in synchronization with the memory controller clock, and serial data is synchronized with the command / address clock (CKA) in the clock recovery circuit (CDR). Is converted to an optical signal, output to the optical waveguide corresponding to the data signal (DQ0), and transmitted to the interface core (IFDC) on the DRAM-side interface chip. This data is transmitted to the DRAM core as described above, and writing is performed.
このように一つのメモリコントローラコアと、一つのDRAMコアが一本のコマンド・アドレス信号と、一本のデータ信号を用いてシリアル伝送を行う構成により、メモリコントローラは多数のDRAMコアと独立してデータ伝送を行うことができる。したがって、メニイコア構成のCPUと接続した場合に、本メモリモジュールは多数のCPUコアからの独立したメモリアクセスを同時に処理できるため、演算性能を大幅に向上することができる。また、それぞれのインターフェースコアがコマンド・アドレス信号、データ信号自体からクロックを取り出し、独自のタイミングでデータ伝送を行い、またそれぞれのDRAMコアが独立したタイミングで動作を行うため、多数の信号線間で同期をとる必要がなく、数十Gbpsの高速伝送を安定的に行うことが可能となる。
As described above, one memory controller core and one DRAM core perform serial transmission using one command / address signal and one data signal, so that the memory controller is independent of many DRAM cores. Data transmission can be performed. Therefore, when connected to a CPU having a many-core configuration, the present memory module can simultaneously process independent memory accesses from a large number of CPU cores, so that the calculation performance can be greatly improved. In addition, each interface core extracts the clock from the command / address signal and the data signal itself, transmits data at its own timing, and each DRAM core operates at an independent timing. There is no need to synchronize, and high-speed transmission of several tens of Gbps can be stably performed.
また、それぞれのコアは他のコアと並列して動作することができる。すなわち、それぞれのチャネルは、他のコアの状態に依らず、データの送受信を行うことが可能である。このようにして、光インターフェースを用いて、各CPUコア及び、DRAMコアが並列に動作可能な、すなわち、他のCPUコア及びDRAMコアの状態によらないで動作可能なチャネルを持つことで、データ送受信のバンド幅を向上させることが出来る上に、チャネルが共有されている場合と異なって、自由なタイミングで動作を行うことができるため、アービトレーションおよび同期化の仕組みが不要になり、情報処理システムを構築する際のハードウェア構成およびソフトウェアの構成が簡略化される利点がある。
Also, each core can operate in parallel with other cores. That is, each channel can transmit and receive data regardless of the state of other cores. In this way, using the optical interface, each CPU core and DRAM core can operate in parallel, that is, by having a channel that can operate regardless of the state of other CPU cores and DRAM cores. In addition to improving the bandwidth of transmission and reception, it is possible to operate at any timing, unlike the case where the channel is shared, so an arbitration and synchronization mechanism is not required, and the information processing system There is an advantage that the hardware configuration and the software configuration are simplified.
図5には貫通ビア(VIA)を用いてDRAMチップ(DRAMIC0)とインターフェースチップ(IFDIC)と、プリント基板(BASE)を積層した場合のブロック図を示す。貫通ビアはチップを貫いたビアによって、特定のチップの上下に積層したチップとのインターフェースを持つことができる。本例ではDRAMチップには4個のDRAMコア(DRAMC0-3)が含まれ、インターフェースチップには4個のインターフェースコア(IFDC0-3)が含まれる。DRAMコアはそれぞれ対応する番号のインターフェースコアを用いて、CPUとデータの送受信を行う。
FIG. 5 shows a block diagram when a DRAM chip (DRAMIC0), an interface chip (IFDIC), and a printed circuit board (BASE) are stacked by using a through via (VIA). Through-vias can have an interface with chips stacked above and below a specific chip by vias penetrating the chip. In this example, the DRAM chip includes four DRAM cores (DRAMC0-3), and the interface chip includes four interface cores (IFDC0-3). The DRAM core transmits / receives data to / from the CPU using an interface core having a corresponding number.
各DRAMコアはメモリアレイ(ARY)に加えて、DRAMクロック(CK)、コマンド・アドレス信号(CAI)、データ信号(DQI)を独立に入出力でき、クロック端子(CKP)、コマンド・アドレス端子(CAIP)、データ入出力端子(DQIP)を介して、インターフェースコアとデータを送受信する。それぞれ独立したタイミングで、個々にコマンド・アドレスの入力を受け付け、データの入出力が可能である。
In addition to the memory array (ARY), each DRAM core can independently input / output a DRAM clock (CK), a command / address signal (CAI), and a data signal (DQI), a clock terminal (CKP), a command / address terminal ( Data is transmitted to and received from the interface core via a data input / output terminal (DQIP). It is possible to input and output data individually by receiving command and address inputs at independent timings.
インターフェースコアは光導波路からプリント基板を介して、光信号を入力するコマンド・アドレス光端子(CAP)、データ光端子(DQP)を備え、また電気信号によりクロック端子(CKP)、コマンド・アドレス端子(CAIP)、データ端子(DQIP)を介して、DRAMコアとデータを送受信する。光インターフェース回路(OPIF)では光信号から電気信号への変換、および電気信号から光信号への変換を行う。クロック再生回路(CDR)ではコマンド・アドレス信号とデータ信号からのクロック抽出、データの取り込み、シリアルデータからパラレルデータへの変換、パラレルデータからシリアルデータへの変換を行う。分周回路(DIV)ではコマンド・アドレス信号から抽出したクロックCKAを分周し、周波数の低いDRAMクロック(CK)を発生する。DRAMコア、インターフェースコアの電源は各コア内の電源パッド(VSP)に対して、プリント基板から貫通ビアを介して供給される。
The interface core includes a command / address optical terminal (CAP) and a data optical terminal (DQP) for inputting an optical signal from an optical waveguide through a printed circuit board, and a clock terminal (CKP) and a command / address terminal ( Data is transmitted to and received from the DRAM core via the CAIP) and data terminal (DQIP). The optical interface circuit (OPIF) performs conversion from an optical signal to an electrical signal and conversion from an electrical signal to an optical signal. The clock recovery circuit (CDR) performs clock extraction from the command / address signal and data signal, data capture, conversion from serial data to parallel data, and conversion from parallel data to serial data. The frequency divider (DIV) divides the clock CKA extracted from the command / address signal and generates a DRAM clock (CK) having a low frequency. The power of the DRAM core and interface core is supplied from the printed circuit board to the power supply pad (VSP) in each core through a through via.
このように貫通ビアを用いてDRAMチップとインターフェースチップを積層することにより、チップ間の信号線の数を増加させることができ、これによってDRAMとインターフェースチップを複数のコアに分割し、それぞれ独立したクロックで動作させることが可能となる。
By laminating the DRAM chip and the interface chip using the through vias in this way, the number of signal lines between the chips can be increased, thereby dividing the DRAM and the interface chip into a plurality of cores, which are independent of each other. It is possible to operate with a clock.
図6には貫通ビア(VIA)を用いて4枚のDRAMチップ(DRAMIC0-3)とインターフェースチップ(IFDIC)と、プリント基板(BASE)を積層した場合のブロック図を示す。貫通ビアはチップを貫いたビアによって、特定のチップの上下に積層したチップとのインターフェースを持つことができる。本例ではDRAMチップに搭載される複数のDRAMコアのうちの一つのDRAMコア(DRAMC0)のみを示し、インターフェースチップに搭載される複数のインターフェースコアのうちの一つのインターフェースコア(IFDC0)のみを示すが、他のDRAMコアも同様にインターフェースコアと接続される。4チップ上に含まれるDRAMC0はIFDC0を用いて、図5の場合と同様にCPUとデータの送受信を行う。
FIG. 6 shows a block diagram when four DRAM chips (DRAMIC0-3), an interface chip (IFDIC), and a printed circuit board (BASE) are stacked using through vias (VIA). Through-vias can have an interface with chips stacked above and below a specific chip by vias penetrating the chip. In this example, only one DRAM core (DRAMC0) of the plurality of DRAM cores mounted on the DRAM chip is shown, and only one interface core (IFDC0) of the plurality of interface cores mounted on the interface chip is shown. However, other DRAM cores are similarly connected to the interface core. The DRAM C0 included on the four chips uses IFDC0 to transmit and receive data to and from the CPU as in the case of FIG.
図5の場合との違いはインターフェースコア上にコマンドデコーダ(CDC)が設けられており、メモリコントローラコアからのアドレスにしたがって、積層された複数のチップのうち一つのチップにコマンド・アドレス信号(CAI)を送信することである。この際、積層したチップを選択するために各チップに独立したチップ選択信号を持たせるか、または各チップにID番号をつける。本構成により、インターフェースチップに積層するDRAMの容量を増加させることができ、モジュールの個数やボードの面積を増加させずに大容量のメモリシステムを実現できるメリットがある。
The difference from the case of FIG. 5 is that a command decoder (CDC) is provided on the interface core, and a command / address signal (CAI) is sent to one of a plurality of stacked chips in accordance with an address from the memory controller core. ). At this time, in order to select the stacked chips, each chip has an independent chip selection signal or an ID number is assigned to each chip. With this configuration, there is an advantage that the capacity of the DRAM stacked on the interface chip can be increased, and a large-capacity memory system can be realized without increasing the number of modules and the board area.
図7には本発明の光インターフェースを用いたメモリモジュールとCPUチップとを光導波路で接続した光インターフェース・メモリバスの構造を示す。(a)に断面図、(b)に上面図の一部を示す。DRAMモジュールは複数のDRAMチップ(DRAMIC)とインターフェースチップ(IFDIC)がプリント基板(BASE)上に積層されて構成される。CPUモジュール(CPUMOD)はCPUチップ(CPUIC)とインターフェースチップ(IFCIC)がプリント基板(BASE)上に積層されて構成される。これらのモジュールはボード基板(SUB)上に配置されるが、ボード基板内には複数の光導波路(WG)が配線されており、CPUモジュールと、DRAMモジュールの対応する端子の間で光信号を伝送することができる。
FIG. 7 shows the structure of an optical interface / memory bus in which a memory module using an optical interface of the present invention and a CPU chip are connected by an optical waveguide. A sectional view is shown in (a), and a part of the top view is shown in (b). The DRAM module is configured by laminating a plurality of DRAM chips (DRAMIC) and an interface chip (IFDIC) on a printed circuit board (BASE). The CPU module (CPUMOD) is configured by stacking a CPU chip (CPUIC) and an interface chip (IFCIC) on a printed circuit board (BASE). These modules are arranged on a board substrate (SUB). A plurality of optical waveguides (WG) are wired in the board substrate, and optical signals are transmitted between corresponding terminals of the CPU module and the DRAM module. Can be transmitted.
(a)に示すように各DRAMモジュールの下部には光カップラー(COUP)が設けられており、CPUから入力された光信号を光導波路から一定の割合で分岐させて、モジュールへ導くことができる。光導波路の端部は無反射コーティング処理(AR)されており、光の反射が起きずに、ほぼ100%透過させている。これによって光導波路上で信号の反射や干渉が起きず、波形の乱れが少ない安定した信号を伝送することができる。光信号を曲げる際には、光の進行方向に対して45度傾いた面を持つミラー構造(ML)を作成し、90度反射させることにより行う。本構成により、一本の導波路によって複数のメモリモジュールとCPUとの間でデータの送受信が可能となるため、光導波路の本数を減らすことができ、ボードのサイズおよびコストを低減できるメリットがある。
As shown in (a), an optical coupler (COUP) is provided at the lower part of each DRAM module, and an optical signal input from the CPU can be branched from the optical waveguide at a certain rate and guided to the module. . The end portion of the optical waveguide is subjected to antireflection coating (AR), and almost 100% is transmitted without reflection of light. As a result, no signal reflection or interference occurs on the optical waveguide, and a stable signal with less waveform distortion can be transmitted. When the optical signal is bent, a mirror structure (ML) having a surface inclined by 45 degrees with respect to the light traveling direction is created and reflected by 90 degrees. With this configuration, data can be transmitted and received between a plurality of memory modules and a CPU with a single waveguide, so that the number of optical waveguides can be reduced, and the size and cost of the board can be reduced. .
図8にメモリ側インターフェースチップ(IFDIC)上のインターフェースコア(IFDC)の構成を示し、図9の波形でその動作の説明をする。メモリコントローラから光導波路を用いて、コマンド・アドレス光端子(CAP)にコマンド・アドレス光信号(CA)が入力される。この光信号は光インターフェース回路(OPIF1)内で、光検出器(PD)で電流信号に変換された後、トランスインピーダンスアンプ(TIA)で電圧信号に変換される。この信号からクロック再生回路(CDR1)内のPLLにおいて、コマンド・アドレスクロック(CKA)が取り出される。CKAによってラッチで取り込まれたコマンド・アドレスシリアルデータ(CAIS)をデマルチプレクサ(DMUX)で並列化する。送信されたシリアルデータは、メモリコントローラの側でデータの変化しない時間が一定時間以上連続しないように、8/10Bエンコードされている。これを8/10Bデコーダ(8/10BDEC)でデコードすることで、パラレルデータのコマンド・アドレス信号(CAI)に変換し、電気信号のインターフェース端子(CAIP)を介して、DRAMチップへと送信される。CAIにはアドレス(A0-A10)、バンクアドレス(BA0-BA1)、行アドレスストローブ信号(RASB)、列アドレスストローブ信号(CASB)、ライトイネーブル(WEB)、チップ選択信号(CSB)、リセット信号(RESETB)が含まれる。図9でははじめにアクティベートコマンド(ACT)と行アドレス(AX)、続いてリードコマンド(READ)と列アドレス(AY)を送信した例を示している。コマンド・アドレスクロックは分周回路(DIV)に入力され、周期が長いDRAMクロック(CK)が生成され、これもクロック端子(CKP)を介してDRAMチップへと送信される。コマンド・アドレス信号はこのDRAMクロックにより、DRAMコアに入力され、ライト、リード等の動作が開始される。
FIG. 8 shows the configuration of the interface core (IFDC) on the memory side interface chip (IFDIC), and its operation will be described with reference to the waveforms in FIG. The command / address optical signal (CA) is input from the memory controller to the command / address optical terminal (CAP) using the optical waveguide. This optical signal is converted into a current signal by a photodetector (PD) in an optical interface circuit (OPIF1), and then converted into a voltage signal by a transimpedance amplifier (TIA). From this signal, the command / address clock (CKA) is taken out in the PLL in the clock recovery circuit (CDR1). Command / address serial data (CAIS) latched by CKA is parallelized by a demultiplexer (DMUX). The transmitted serial data is 8 / 10B encoded so that the time during which the data does not change does not continue for a certain time or longer on the memory controller side. This is decoded by an 8 / 10B decoder (8 / 10BDEC) to convert it into a command / address signal (CAI) of parallel data and transmitted to the DRAM chip via an interface terminal (CAIP) of an electric signal. . CAI includes address (A0-A10), bank address (BA0-BA1), row address strobe signal (RASB), column address strobe signal (CASB), write enable (WEB), chip selection signal (CSB), reset signal ( RESETB). FIG. 9 shows an example in which an activate command (ACT) and a row address (AX) are transmitted first, followed by a read command (READ) and a column address (AY). The command / address clock is input to the frequency dividing circuit (DIV) to generate a DRAM clock (CK) having a long period, and this is also transmitted to the DRAM chip via the clock terminal (CKP). The command / address signal is input to the DRAM core by the DRAM clock, and operations such as writing and reading are started.
リード動作の場合DRAMコアから読み出されたパラレルのデータ信号(DQI)がDRAMクロックによりインターフェースコア(IFDC)の電気信号インターフェース端子(DQIP)に入力される。DQIPにはDQ端子(DQI0-3)、データマスク(DM)が含まれる。このパラレルデータは、クロック再生回路(CDR2)において、シリアル化したときにデータの変化しない時間が一定時間以上連続しないように、8/10Bエンコーダ(8/10BENC)でエンコードされた後、コマンド・アドレスクロック(CKA)に同期してマルチプレクサ(MUX)とDQラッチでシリアル出力データ(DOS)に変換される。その後、光インターフェース(OPIF2)内で、レーザー(LD)から出力された光を変調器(MOD)でデータ光信号(DQ)に変換し、図10に示すようにデータ光端子(DQP)から光導波路に出力され、メモリコントローラに伝送される。
In the case of a read operation, a parallel data signal (DQI) read from the DRAM core is input to the electrical signal interface terminal (DQIP) of the interface core (IFDC) by the DRAM clock. DQIP includes a DQ terminal (DQI0-3) and a data mask (DM). The parallel data is encoded by the 8 / 10B encoder (8 / 10BENC) so that the time during which the data does not change when serialized in the clock recovery circuit (CDR2) does not continue for a predetermined time or longer, and then the command address It is converted into serial output data (DOS) by a multiplexer (MUX) and a DQ latch in synchronization with the clock (CKA). Thereafter, in the optical interface (OPIF2), the light output from the laser (LD) is converted into the data optical signal (DQ) by the modulator (MOD), and the light is transmitted from the data optical terminal (DQP) as shown in FIG. It is output to the waveguide and transmitted to the memory controller.
ライト動作の場合には、メモリコントローラから光導波路を用いて、データ光端子(DQP)にライトデータに対応する光信号(DQ)が入力される。この光信号は光インターフェース回路(OPIF2)内で、光検出器(PD)で電流信号に変換された後、トランスインピーダンスアンプ(TIA)で電圧信号に変換される。この信号からクロック再生回路(CDR2)内のPLLにおいて、データクロック(CKD)が取り出される。CKDによってDQラッチで取り込まれたシリアル入力データ(DIS)をデマルチプレクサ(DMUX)で並列化する。送信されたシリアルデータは、メモリコントローラの側でデータの変化しない時間が一定時間以上連続しないように、8/10Bエンコードされている。これを8/10Bデコーダ(8/10BDEC)でデコードすることで、パラレルデータに変換されたライトデータ信号(DQI)を発生し、図11に示すように、電気信号のインターフェース端子(DQIP)を介して、DRAMチップへと送信される。
In the write operation, an optical signal (DQ) corresponding to the write data is input from the memory controller to the data optical terminal (DQP) using the optical waveguide. This optical signal is converted into a current signal by a photodetector (PD) in an optical interface circuit (OPIF2), and then converted into a voltage signal by a transimpedance amplifier (TIA). From this signal, the data clock (CKD) is taken out in the PLL in the clock recovery circuit (CDR2). Serial input data (DIS) taken in by the DQ latch by CKD is parallelized by the demultiplexer (DMUX). The transmitted serial data is 8 / 10B encoded so that the time during which the data does not change does not continue for a certain time or longer on the memory controller side. This is decoded by an 8 / 10B decoder (8 / 10BDEC) to generate a write data signal (DQI) converted into parallel data, and through an electrical signal interface terminal (DQIP) as shown in FIG. And transmitted to the DRAM chip.
この構成により、それぞれのインターフェースコアがコマンド・アドレス信号、データ信号自体からクロックを取り出し、独自のタイミングでデータ伝送を行い、またそれぞれのDRAMコアが独立したタイミングで動作を行うため、多数の信号線間で同期をとる必要がなく、数十Gbpsの高速伝送を安定的に行うことが可能となる。
With this configuration, each interface core extracts the clock from the command / address signal and the data signal itself, performs data transmission at its own timing, and each DRAM core operates at independent timing. It is not necessary to synchronize between them, and high-speed transmission of several tens of Gbps can be stably performed.
図12にCPU側インターフェースチップ(IFCIC)上のインターフェースコア(IFCC)の構成を示す。メモリコントローラコアから、パラレルデータのコマンド・アドレス信号(CAI)がCPUクロック(CKC)によりコマンド・アドレス端子(CAIP)に入力される。CAIにはアドレス(A0-A10)、バンクアドレス(BA0-BA1)、行アドレスストローブ信号(RASB)、列アドレスストローブ信号(CASB)、ライトイネーブル(WEB)、チップセレクト(CS)、リセット信号(RESETB)が含まれる。
FIG. 12 shows the configuration of the interface core (IFCC) on the CPU side interface chip (IFCIC). A command / address signal (CAI) of parallel data is input from the memory controller core to the command / address terminal (CAIP) by the CPU clock (CKC). CAI includes address (A0-A10), bank address (BA0-BA1), row address strobe signal (RASB), column address strobe signal (CASB), write enable (WEB), chip select (CS), and reset signal (RESETB). ) Is included.
このパラレルデータは、クロック再生回路(CDR3)において、まず、シリアル化したときにデータの変化しない時間が一定時間以上連続しないように、8/10Bエンコーダ(8/10BENC)でエンコードされた後、CKCをPLLで逓倍した高速なコマンド・アドレスクロック(CKA)に同期してマルチプレクサ(MUX)とラッチでコマンド・アドレスシリアルデータ(CAIS)に変換される。その後、光インターフェース(OPIF3)内で、レーザー(LD)から出力された光を変調器(MOD)でコマンド・アドレス光信号(CA)に変換し、コマンド・アドレス光端子(CAP)から光導波路に出力され、DRAMモジュールに伝送される。
The parallel data is first encoded by the 8 / 10B encoder (8 / 10BENC) in the clock recovery circuit (CDR3) so that the time during which the data does not change when serialized does not continue for a certain time or longer, and then the CKC Is converted into command / address serial data (CAIS) by a multiplexer (MUX) and a latch in synchronization with a high-speed command / address clock (CKA) multiplied by PLL. Then, in the optical interface (OPIF3), the light output from the laser (LD) is converted into a command / address optical signal (CA) by a modulator (MOD), and the command / address optical terminal (CAP) is converted into an optical waveguide. Is output and transmitted to the DRAM module.
ライト動作の場合メモリコントローラコアから送信されたパラレルなデータ信号(DQI)がCPUクロック(CKC)によりインターフェースコア(IFCC)のデータ端子(DQIP)に入力される。DQIPにはDQ端子(DQI0-3)、データマスク(DM)が含まれる。このパラレルデータは、クロック再生回路(CDR2)において、シリアル化したときにデータの変化しない時間が一定時間以上連続しないように、8/10Bエンコーダ(8/10BENC)でエンコードされた後、コマンド・アドレスクロック(CKA)に同期してマルチプレクサ(MUX)とラッチでシリアル出力データ(DOS)に変換される。その後、光インターフェース(OPIF2)内で、レーザー(LD)から出力された光を変調器(MOD)でデータ光信号(DQ)に変換し、データ光端子(DQP)から光導波路に出力され、DRAMモジュールに伝送される。
In the case of a write operation, a parallel data signal (DQI) transmitted from the memory controller core is input to the data terminal (DQIP) of the interface core (IFCC) by the CPU clock (CKC). DQIP includes a DQ terminal (DQI0-3) and a data mask (DM). The parallel data is encoded by the 8 / 10B encoder (8 / 10BENC) so that the time during which the data does not change when serialized in the clock recovery circuit (CDR2) does not continue for a predetermined time or longer, and then the command address In synchronization with the clock (CKA), the data is converted into serial output data (DOS) by a multiplexer (MUX) and a latch. Then, in the optical interface (OPIF2), the light output from the laser (LD) is converted into the data optical signal (DQ) by the modulator (MOD), and output from the data optical terminal (DQP) to the optical waveguide, and the DRAM Transmitted to the module.
リード動作の場合には、DRAMモジュールから光導波路を用いて、データ光端子(DQP)にリードデータに対応した光信号(DQ)が入力される。この光信号は光インターフェース回路(OPIF2)内で、光検出器(PD)で電流信号に変換された後、トランスインピーダンスアンプ(TIA)で電圧信号に変換される。この信号からクロック再生回路(CDR2)内のPLLにおいて、データクロック(CKD)が取り出される。CKDによってラッチで取り込まれたシリアル入力データ(DIS)をデマルチプレクサ(DMUX)で並列化する。送信されたシリアルデータは、メモリコントローラの側でデータの変化しない時間が一定時間以上連続しないように、8/10Bエンコードされている。これを8/10Bデコーダ(8/10BDEC)でデコードすることで、パラレルデータに変換されたリードデータ(DQI)を発生し、データ端子(DQIP)を介して、DRAMチップへと送信される。
In the case of a read operation, an optical signal (DQ) corresponding to the read data is input from the DRAM module to the data optical terminal (DQP) using an optical waveguide. This optical signal is converted into a current signal by a photodetector (PD) in an optical interface circuit (OPIF2), and then converted into a voltage signal by a transimpedance amplifier (TIA). From this signal, the data clock (CKD) is taken out in the PLL in the clock recovery circuit (CDR2). Serial input data (DIS) fetched by the CKD latch is parallelized by the demultiplexer (DMUX). The transmitted serial data is 8 / 10B encoded so that the time during which the data does not change does not continue for a certain time or longer on the memory controller side. By decoding this data with an 8 / 10B decoder (8 / 10BDEC), read data (DQI) converted into parallel data is generated and transmitted to the DRAM chip via the data terminal (DQIP).
この構成により、それぞれのインターフェースコアがコマンド・アドレス信号、データ信号自体からクロックを取り出し、独自のタイミングでデータ伝送を行い、またそれぞれのメモリコントローラコアが独立したタイミングで動作を行うため、多数の信号線間で同期をとる必要がなく、数十Gbpsの高速伝送を安定的に行うことが可能となる。
With this configuration, each interface core extracts the clock from the command / address signal and the data signal itself, transmits data at its own timing, and each memory controller core operates at an independent timing. There is no need to synchronize the lines, and high-speed transmission of several tens of Gbps can be stably performed.
図13には図8に示したメモリ側インターフェースチップ(IFDIC)を光インターフェースチップ(IFD-OIC)と、電気インターフェースチップ(IFD-EIC)に分けて実現した場合の構成を示す。光インターフェースチップには複数の光インターフェースコア(IFD-OC)、電気インターフェースチップには複数の電気インターフェースコア(IFD-EC)が配置されるが、図ではそのうちの一組を示している。それぞれのコアに含まれる回路ブロックの動作は図8と同等であるが、コマンド・アドレス信号については光インターフェースコア内の光インターフェース回路(OPIF1)の出力を、コマンド・アドレスシリアル端子(CASP)を介して貫通ビア(VIA)に出力し、これを電気インターフェースコア内のクロック再生回路(CDR1)に入力する。データ信号についても、電気インターフェースコア内のクロック再生回路の入力信号(DIS)、出力信号(DOS)を、シリアル入力データ端子(DSP)、シリアル出力データ端子(QSP)を介して貫通ビアに出力し、光インターフェースコア内の光インターフェース回路(OPIF2)と接続する。このように、インターフェースチップを分割することによって、光インターフェースチップにGaAs、InPなどの化合物半導体基板を用いて光素子の特性を向上し、電気インターフェースチップにSi基板を用いてCMOS論理回路を搭載することで、電子デバイスの集積度を上げ、消費電力を低減することが可能になる。
FIG. 13 shows a configuration in the case where the memory side interface chip (IFDIC) shown in FIG. 8 is divided into an optical interface chip (IFD-OIC) and an electrical interface chip (IFD-EIC). A plurality of optical interface cores (IFD-OC) are arranged in the optical interface chip, and a plurality of electric interface cores (IFD-EC) are arranged in the electric interface chip, and one set is shown in the figure. The operation of the circuit block included in each core is the same as that in FIG. 8, but for the command / address signal, the output of the optical interface circuit (OPIF1) in the optical interface core is sent via the command / address serial terminal (CASP). To the through via (VIA), and this is input to the clock recovery circuit (CDR1) in the electrical interface core. As for the data signal, the input signal (DIS) and output signal (DOS) of the clock recovery circuit in the electrical interface core are output to the through via via the serial input data terminal (DSP) and the serial output data terminal (QSP). The optical interface circuit (OPIF2) in the optical interface core is connected. Thus, by dividing the interface chip, the characteristics of the optical element are improved using a compound semiconductor substrate such as GaAs or InP for the optical interface chip, and a CMOS logic circuit is mounted using the Si substrate for the electrical interface chip. As a result, it is possible to increase the degree of integration of electronic devices and reduce power consumption.
図14は図13の電気インターフェースコア(IFD-EC)をDRAMチップ上に集積した例を示す。DRAMチップ上には複数のDRAMコアと電気インターフェースコアを搭載するが、ここでは一組のみを示している。それぞれの回路ブロックの動作は図8と同等である。この場合は図13と同様に光インターフェースチップにGaAs、InPなどの化合物半導体基板を用いて光素子の特性を向上することができる上、DRAMチップと光インターフェースチップを直接接続することが可能となり、チップ数を増加させる必要がないため、パッケージのコストを低減することができる。
FIG. 14 shows an example in which the electrical interface core (IFD-EC) of FIG. 13 is integrated on a DRAM chip. A plurality of DRAM cores and an electrical interface core are mounted on the DRAM chip, but only one set is shown here. The operation of each circuit block is the same as in FIG. In this case, the characteristics of the optical element can be improved by using a compound semiconductor substrate such as GaAs or InP for the optical interface chip as in FIG. 13, and the DRAM chip and the optical interface chip can be directly connected. Since there is no need to increase the number of chips, the cost of the package can be reduced.
図15は、DRAMチップ(DRAMIC)構成を示す平面図である。チップ内には複数の並列動作可能なDRAMコア(MEM0~7(図1等のDRAMCに対応。以下、同じ。))と、送受信回路、電源発生回路などの、複数のDRAMコアに対し共通に設けられている回路(以下、共通回路(COMC)という)があり、その間にバス(BUS)が配線されている。ここで、電源発生回路を共通に設けることで、小面積で回路設計をすることが可能となる。
FIG. 15 is a plan view showing the configuration of a DRAM chip (DRAMIC). Common to a plurality of DRAM cores such as a plurality of DRAM cores (MEM0 to 7 (corresponding to DRAMC in FIG. 1 and the like; the same applies hereinafter)), a transmission / reception circuit, a power generation circuit, and the like in the chip. There are provided circuits (hereinafter referred to as a common circuit (COMC)), and a bus (BUS) is wired between them. Here, by providing the power supply generation circuit in common, it is possible to design a circuit with a small area.
ここでは、2行×4列の8個のDRAMコアを配置した例を示しているが、各メモリコアの配置される領域のサイズを3mm角程度とすると、DRAMチップ全体が6mm×12mm角程度と、現状量産されているDRAMチップのチップサイズに近い値となり、従来並みの製造歩留や価格を実現することができて有利である。
Here, an example is shown in which 8 DRAM cores of 2 rows × 4 columns are arranged. If the size of the area where each memory core is arranged is about 3 mm square, the entire DRAM chip is about 6 mm × 12 mm square. This is a value close to the chip size of DRAM chips that are currently mass-produced, which is advantageous in that it can achieve the same manufacturing yield and price as before.
DRAMコア内で、コマンド・アドレス端子(CAIP)、及びデータ端子(DQIP)をチップ中央側に位置する第2辺に配置している。このように配置するとコマンド・アドレス端子およびデータ端子をチップの中央部に集中して配置することができる。このためDRAMチップとSoCのチップの形状が比較的大きく異なる場合にも、コマンド・アドレス端子とデータ端子の位置を合わせて積層することが容易になるという効果がある。
In the DRAM core, a command / address terminal (CAIP) and a data terminal (DQIP) are arranged on the second side located on the chip center side. With this arrangement, command / address terminals and data terminals can be concentrated in the center of the chip. For this reason, even when the shapes of the DRAM chip and the SoC chip are relatively different, it is easy to stack the command / address terminals and the data terminals together.
図16は1個のDRAMコア(MEM)の内部の構成例を示した平面図である。コア内の一辺にコマンド・アドレス端子(CAIP)、データ端子(DQIP)、クロック端子(CKP)を配置する。メモリバンク(BANK)を複数配置し、メモリバンクとデータ端子の間にリードライト回路(R/W AMP)を配置する。コアの両側の辺には欠陥救済用のフューズ(FUSE)を配置する。
FIG. 16 is a plan view showing an internal configuration example of one DRAM core (MEM). A command / address terminal (CAIP), a data terminal (DQIP), and a clock terminal (CKP) are arranged on one side of the core. A plurality of memory banks (BANK) are arranged, and a read / write circuit (R / W AMP) is arranged between the memory bank and the data terminal. Defect relief fuses (FUSE) are arranged on both sides of the core.
ここで、コマンド信号は、リセット信号、行アドレスストローブ、列アドレスストローブ、ライトイネーブル及びチップセレクト信号であり、これらに対応する入出力端子が、コマンド・アドレス端子領域に設けられる。それぞれの入出力端子にはTSV用入出力回路が設けられ、コマンド信号が入力される。また、アドレス信号も同様に、アドレス信号(A0-A10)又はバンクアドレス信号(BA0-1)に対応した端子毎に設けられたTSV用入出力回路を介して入力される。コマンド・アドレス制御回路では、DRAMチップの動作モードの決定、アドレスのプリデコード、動作タイミングの制御等が行われる。
Here, the command signals are a reset signal, a row address strobe, a column address strobe, a write enable and a chip select signal, and input / output terminals corresponding to these are provided in the command / address terminal area. Each input / output terminal is provided with a TSV input / output circuit to receive a command signal. Similarly, the address signal is also input via a TSV input / output circuit provided for each terminal corresponding to the address signal (A0-A10) or the bank address signal (BA0-1). The command / address control circuit determines the operation mode of the DRAM chip, predecodes the address, controls the operation timing, and the like.
データ端子(DQIP)には、データ信号がTSV用入出力回路を介して入出力される。ここでデータ信号はデータ入出力信号(DQ0-3)、データマスク信号(DML)からなる。DRAMクロック(CK)をDRAMコア毎に持つことで、複数DRAMコアが独立したタイミングで並列に動作可能なDRAMチップを実現できる。
The data signal is input / output to / from the data terminal (DQIP) via the TSV input / output circuit. Here, the data signal includes a data input / output signal (DQ0-3) and a data mask signal (DML). By having a DRAM clock (CK) for each DRAM core, a DRAM chip in which a plurality of DRAM cores can operate in parallel at independent timings can be realized.
ここで、DRAMチップのコマンド・アドレス端子(CAIP)のプリント基板(PCB)に対し鉛直下方に、インターフェースチップのコマンド・アドレス端子が配置され、DRAMチップのデータ端子(DQIP)のプリント基板(PCB)に対し鉛直下方に、インターフェースチップのデータ端子が配置されるようにインターフェースチップ(IFDIC)とDRAMチップ(DRAMIC)を積層して実装する。この構成により、チップ間のデータ伝送距離を短くすることが可能であり、データの転送効率が向上する。
Here, the command / address terminal of the interface chip is arranged vertically below the printed circuit board (PCB) of the command / address terminal (CAIP) of the DRAM chip, and the printed circuit board (PCB) of the data terminal (DQIP) of the DRAM chip. On the other hand, the interface chip (IFDIC) and the DRAM chip (DRAMIC) are stacked and mounted so that the data terminals of the interface chip are arranged vertically below. With this configuration, the data transmission distance between chips can be shortened, and the data transfer efficiency is improved.
メモリバンク(BANK)には、図16に示すように、複数のアレイ状に配置されたメモリアレイ(ARY)が配置され、その周囲にはセンスアンプ列(SAA)、サブワードドライバ列(SWDA)が配置される。またメモリバンクの外周にはセンスアンプ列と平行に列デコーダ(YDEC)が配置され、サブワードドライバ列(SWDA)と平行に行デコーダ(XDEC)が配置され、加えてアレイ制御回路が配置される。欠陥救済用フューズ(FUSE)をDRAMコア毎に持って欠陥メモリセルを同一のDRAMコア内の冗長メモリセルと置換することで、救済判定信号をコアの外に出す必要がなくなり、アクセス時間を短縮することができる。
In the memory bank (BANK), as shown in FIG. 16, a memory array (ARY) arranged in a plurality of arrays is arranged, and a sense amplifier array (SAA) and a sub word driver array (SWDA) are arranged around it. Be placed. A column decoder (YDEC) is arranged in parallel with the sense amplifier column on the outer periphery of the memory bank, a row decoder (XDEC) is arranged in parallel with the sub word driver column (SWDA), and an array control circuit is arranged in addition. By having a defect relief fuse (FUSE) for each DRAM core and replacing a defective memory cell with a redundant memory cell in the same DRAM core, it is not necessary to send a relief judgment signal out of the core, thereby shortening the access time. can do.
図16に示した構成は、データ入出力回路(DQ)のビット数が4ビットであるが、一例としてDRAMコアをDDR2-SDRAMベースとして作成する場合、メモリアレイ内部では16ビットのデータが並列に読み出され、これが4対1のマルチプレクサによりパラレル-シリアル変換された後、チップ外に出力される。また、DRAMコアとしてDDR3-SDRAMやその他のDRAMをベースとし、またアドレス端子、データピンの本数を変更することも可能である。
In the configuration shown in FIG. 16, the number of bits of the data input / output circuit (DQ) is 4, but as an example, when a DRAM core is created as a DDR2-SDRAM base, 16 bits of data are paralleled in the memory array. The data is read out, converted into parallel-serial by a 4-to-1 multiplexer, and then output outside the chip. The DRAM core is based on DDR3-SDRAM or other DRAM, and the number of address terminals and data pins can be changed.
図17は、図16のDRAMコア内、図19のCPUコア内で用いるTSV用入出力回路(TSVC)を示す。この回路は、出力回路(OBC3)と入力回路(IBC3)で構成され、DRAMチップ(DRAMIC)とインターフェースチップ(IFDIC)上に複数設けられる。DRAMチップ上の入出力回路のND端子に貫通ビア用のパッド(PAD)を設け、インターフェースチップ上の入出力回路のNS端子にも同様のパッドを設け、両者を貫通ビアで接続する。
FIG. 17 shows a TSV input / output circuit (TSVC) used in the DRAM core of FIG. 16 and the CPU core of FIG. This circuit includes an output circuit (OBC3) and an input circuit (IBC3), and a plurality of such circuits are provided on a DRAM chip (DRAMIC) and an interface chip (IFDIC). A through via pad (PAD) is provided at the ND terminal of the input / output circuit on the DRAM chip, and a similar pad is also provided at the NS terminal of the input / output circuit on the interface chip.
DRAMチップからインターフェースチップへデータを送信する場合には、DRAMチップ上で出力回路(OBC3)を活性化し、NDに電位変化を発生させる。貫通ビアでNDとNSが接続されているので、インターフェースチップ側の端子NSには、この電位変化がそのまま伝わり、入力回路(IBC3)で増幅され、デジタルデータへと再生される。これと反対にインターフェースチップからDRAMチップへデータを送信する場合には、インターフェースチップ上で出力回路を活性化してNSに電位変化を発生させ、NSとビアで接続されたDRAM側の端子NDに電圧を発生させる。この電圧をDRAM側の入力回路で増幅し、デジタルデータへと再生する。
When data is transmitted from the DRAM chip to the interface chip, the output circuit (OBC3) is activated on the DRAM chip to cause a potential change in ND. Since ND and NS are connected by the through via, this potential change is directly transmitted to the terminal NS on the interface chip side, amplified by the input circuit (IBC3), and reproduced as digital data. On the other hand, when data is transmitted from the interface chip to the DRAM chip, the output circuit is activated on the interface chip to generate a potential change in NS, and a voltage is applied to a terminal ND on the DRAM side connected to NS via. Is generated. This voltage is amplified by an input circuit on the DRAM side and reproduced into digital data.
図18では、データ受信を行う一組のTSV用入出力回路(TSVC)に注目して、動作を説明する。出力回路(OBC3)では、出力イネーブル信号(OED)が非活性状態(VSS)のときにはMOSトランジスタMP5、MN5はオフしている。OEDが活性化されVDDになると、データ出力端子(DOD)に対応して、MP5またはMN5がONする。DODがVSSのときは、MN5がオンし、NDがVSSにドライブされる。インターフェースチップ上ではNSの電圧がVSSに向って引かれる。この信号を増幅回路(AMP)で増幅するとともに、ラッチ信号(LTS)を活性化して、ラッチ回路(LTC)でVSSレベルのデータをラッチし、データ入力端子(DIS)に出力する。DODがVDDのときには、これらと逆極性の信号遷移が発生し、DISにはVDDレベルの信号が出力される。この方式を用いて貫通ビアを用いてDRAMコアとインターフェースコアとの間でデータ送受信を行うと、信号線数を多数に増やすことができるメリットがある。貫通ビア方式では出力回路で出力したVDDまたはVSSの電圧が入力回路に入力されるため、回路が単純で、信号伝送の信頼性が高いという特徴がある。
In FIG. 18, the operation will be described by paying attention to a set of TSV input / output circuits (TSVC) for receiving data. In the output circuit (OBC3), the MOS transistors MP5 and MN5 are turned off when the output enable signal (OED) is in the inactive state (VSS). When OED is activated and becomes VDD, MP5 or MN5 is turned on corresponding to the data output terminal (DOD). When DOD is VSS, MN5 is turned on and ND is driven to VSS. On the interface chip, the voltage of NS is pulled toward VSS. This signal is amplified by the amplifier circuit (AMP), the latch signal (LTS) is activated, the VSS level data is latched by the latch circuit (LTC), and is output to the data input terminal (DIS). When DOD is VDD, signal transitions having opposite polarities occur, and a VDD level signal is output to DIS. When data transmission / reception is performed between the DRAM core and the interface core using the through via using this method, there is an advantage that the number of signal lines can be increased to a large number. The through via method is characterized in that the voltage of VDD or VSS output from the output circuit is input to the input circuit, so that the circuit is simple and the reliability of signal transmission is high.
図19は、インターフェースチップチップ(IFDIC)の構成を示す平面図である。チップ内には複数の並列動作可能なインターフェースコア(IFDC0~7)と、送受信回路、電源発生回路などの、複数のDRAMコアに対し共通に設けられている回路(以下、共通回路(COMC)という)があり、その間にバス(BUS)が配線されている。ここで、電源発生回路を共通に設けることで、小面積で回路設計をすることが可能となる。
FIG. 19 is a plan view showing a configuration of an interface chip chip (IFDIC). In the chip, a plurality of interface cores (IFDC0 to IFDC7) capable of operating in parallel, a circuit commonly provided for a plurality of DRAM cores such as a transmission / reception circuit and a power generation circuit (hereinafter referred to as a common circuit (COMC)). ) And a bus (BUS) is wired between them. Here, by providing the power supply generation circuit in common, it is possible to design a circuit with a small area.
ここでは、2行×4列の8個のインターフェースコアを配置した例を示している。インターフェースコア内で、コマンド・アドレス入力端子(CAIP)、及びデータ入出力端子(DQIP)をチップ中央側に位置する第2辺に配置している。このように配置するとコマンド・アドレス入力端子およびデータ入出力端子をチップの中央部に集中して配置することができる。このためDRAMチップとインターフェースチップの形状が比較的大きく異なる場合にも、コマンド・アドレス入力端子とデータ入出力端子の位置を合わせて積層することが容易になるという効果がある。
Here, an example in which 8 interface cores of 2 rows × 4 columns are arranged is shown. In the interface core, a command / address input terminal (CAIP) and a data input / output terminal (DQIP) are arranged on the second side located on the chip center side. With this arrangement, the command / address input terminals and the data input / output terminals can be concentrated in the center of the chip. For this reason, even when the shapes of the DRAM chip and the interface chip are relatively different, it is easy to stack the command / address input terminals and the data input / output terminals together.
図20は、図16のDRAMコアにおけるメモリバンク(BANK)内部の構成例を示す。複数のアレイ状に配置されたメモリアレイ(ARY)が配置され、その周囲にはセンスアンプ列(SAA)、サブワードドライバ列(SWDA)、クロスエリア(XP)が配置される。また、メモリバンク(BANK)内の外周には、センスアンプ列と平行に列デコーダ(YDEC)およびメインアンプ列が配置され、サブワードドライバ列と平行に行デコーダ(XDEC)並びにアレイ制御回路(ACC)が配置される。
FIG. 20 shows a configuration example inside the memory bank (BANK) in the DRAM core of FIG. A memory array (ARY) arranged in a plurality of arrays is arranged, and a sense amplifier array (SAA), a sub word driver array (SWDA), and a cross area (XP) are arranged around the memory array (ARY). In addition, a column decoder (YDEC) and a main amplifier column are arranged on the outer periphery of the memory bank (BANK) in parallel with the sense amplifier column, and a row decoder (XDEC) and an array control circuit (ACC) in parallel with the sub word driver column. Is placed.
図21は、図16のDRAMコアにおいて、そのセンスアンプ列とサブワードドライバ列の詳細な配置関係の一例を示す平面図である。センスアンプ列(SAA)内のセンスアンプ(SA)は、メモリアレイ(ARY)に対して左右に交互配置され、左右のメモリアレイ内のビット線対(BLT/BLB)に共通接続される。同様に、サブワードドライバ列(SWDA)内のサブワードドライバ(SWD)も、メモリアレイに対して上下に交互配置され、上下のメモリアレイ内のワード線(WL)に共通接続される。このように配置することにより、センスアンプ列内において、センスアンプ間のピッチを、メモリアレイ内のビット線間のピッチの2倍に広げることができ、また、サブワードドライバ列内において、サブワードドライバ間のピッチを、メモリアレイ内のワード線間のピッチの2倍に広げることができるため、微細化が容易となる。またセンスアンプ列にはローカルI/O線(LIO)が配置され、ローカルI/O線はクロスエリア(XP)でスイッチ(SW)を介して、メインI/O線(MIO)と接続される。
FIG. 21 is a plan view showing an example of a detailed arrangement relationship between the sense amplifier row and the sub word driver row in the DRAM core of FIG. The sense amplifiers (SA) in the sense amplifier array (SAA) are alternately arranged on the left and right with respect to the memory array (ARY), and are commonly connected to the bit line pairs (BLT / BLB) in the left and right memory arrays. Similarly, the sub word drivers (SWD) in the sub word driver array (SWDA) are alternately arranged above and below the memory array and commonly connected to the word lines (WL) in the upper and lower memory arrays. By arranging in this way, the pitch between the sense amplifiers in the sense amplifier row can be increased to twice the pitch between the bit lines in the memory array, and between the sub word drivers in the sub word driver row. Can be increased to twice the pitch between the word lines in the memory array, so that miniaturization is facilitated. A local I / O line (LIO) is arranged in the sense amplifier row, and the local I / O line is connected to the main I / O line (MIO) via the switch (SW) in the cross area (XP). .
図22は、図16のDRAMコアにおいて、そのメモリアレイの構成の一例を示す回路図である。メモリアレイ(ARY)は、複数のメモリセル(MC)から構成されている。各メモリセルは、DRAMメモリセルとなっており、1個のMOSトランジスタ(メモリセルトランジスタ)および1個のキャパシタ(Cs)で構成される。メモリセルトランジスタのソース又はドレインの一方は、ビット線(BLT)又は参照ビット線(BLB)に接続され、ソース又はドレインの他方は、蓄積ノード(SN)に接続され、ゲートはワード線(WL)に接続されている。
FIG. 22 is a circuit diagram showing an example of the configuration of the memory array in the DRAM core of FIG. The memory array (ARY) is composed of a plurality of memory cells (MC). Each memory cell is a DRAM memory cell, and is composed of one MOS transistor (memory cell transistor) and one capacitor (Cs). One of the source and the drain of the memory cell transistor is connected to the bit line (BLT) or the reference bit line (BLB), the other of the source and the drain is connected to the storage node (SN), and the gate is the word line (WL). It is connected to the.
キャパシタ(Cs)の一方の端子は、蓄積ノードSNに接続され、他方の端子は共通プレート(PL)に接続される。なお、ビット線と参照ビット線は、ビット線対(相補ビット線)として機能し、同一のセンスアンプに接続される。センスアンプ列は、メモリアレイに対して左右に交互配置され、左右のメモリアレイ内のビット線対に共通に接続され、両者で共用される。また、これに伴い各センスアンプ列内では、隣接するセンスアンプがビット線対1つ分のスペースを挟んで配置されることになる。このような配置をとることにより、センスアンプ間のピッチが緩和されるためレイアウトが容易となり、微細化が可能となる。この図では開放型ビット線方式のアレイを用いており、全てのワード線とビット線の交点にメモリセルが配置されている。このためメモリセルサイズを縮小できる効果がある。
One terminal of the capacitor (Cs) is connected to the storage node SN, and the other terminal is connected to the common plate (PL). The bit line and the reference bit line function as a bit line pair (complementary bit line) and are connected to the same sense amplifier. The sense amplifier rows are alternately arranged on the left and right with respect to the memory array, are connected in common to the bit line pairs in the left and right memory arrays, and are shared by both. Accordingly, in each sense amplifier row, adjacent sense amplifiers are arranged with a space corresponding to one bit line pair. By adopting such an arrangement, the pitch between the sense amplifiers is relaxed, so that the layout becomes easy and miniaturization becomes possible. In this figure, an open bit line type array is used, and memory cells are arranged at the intersections of all word lines and bit lines. This has the effect of reducing the memory cell size.
図23は、図16のDRAMコアにおけるセンスアンプの一例を示す回路図である。センスアンプ(SA)内には、プリチャージ回路(PCC)と、クロスカップル・アンプ(CC)と、読み出し・書き込みポート(IOP)とが含まれている。プリチャージ回路は、ビット線プリチャージ信号(BLEQ)が活性化された時に対となるビット線(BLT/BLB)間をイコライズし、ビット線プリチャージレベル(VBLR)にプリチャージする。通常、ビット線電圧(VDL)はチップ外部からの電源電圧(VCC)と同レベルかまたはそれを降圧したレベルに設定する。ビット線プリチャージレベルは、この中点(VDL/2)に設定される。クロスカップル・アンプ(CC)は、ビット線上にメモリセルからの微小な読出し信号が発生した後に、P側共通ソース線(CSP)をビット線電圧に、N側共通ソース線(CSN)を接地電位(VSS)に駆動して、相補ビット線のうちの電圧の高い方をVDLに、低い方をVSSに増幅し、増幅された電圧をラッチする回路である。読み出し・書き込みポート(IOP)は、列選択線(YS)が活性化されたときにローカルI/O線(LIOT/B)とビット線対を接続する回路である。なお、ローカルI/O線は、非選択センスアンプ列での電流消費を防止するために、待機時にはプリチャージレベルに保持される。
FIG. 23 is a circuit diagram showing an example of a sense amplifier in the DRAM core of FIG. The sense amplifier (SA) includes a precharge circuit (PCC), a cross couple amplifier (CC), and a read / write port (IOP). The precharge circuit equalizes the paired bit lines (BLT / BLB) when the bit line precharge signal (BLEQ) is activated, and precharges the bit line precharge level (VBLR). Usually, the bit line voltage (VDL) is set to the same level as the power supply voltage (VCC) from the outside of the chip or a level obtained by stepping down the same. The bit line precharge level is set to this midpoint (VDL / 2). In the cross-coupled amplifier (CC), after a minute read signal from the memory cell is generated on the bit line, the P-side common source line (CSP) is set to the bit line voltage and the N-side common source line (CSN) is set to the ground potential. This circuit is driven to (VSS), amplifies the higher voltage of complementary bit lines to VDL, amplifies the lower voltage to VSS, and latches the amplified voltage. The read / write port (IOP) is a circuit that connects the local I / O line (LIOT / B) and the bit line pair when the column selection line (YS) is activated. The local I / O line is held at the precharge level during standby in order to prevent current consumption in the non-selected sense amplifier array.
図24は、図16のDRAMコアにおけるサブワードドライバ列の構成の一例を示す回路図である。サブワードドライバ列(SWDA)は、複数のサブワードドライバ(SWD)によって構成される。図21に示すように、サブワードドライバ列は、メモリアレイの周辺に配置される。サブワードドライバは上下に配置されるメモリアレイ内のワード線(WL)を駆動する。また、サブワードドライバ列はメモリアレイに対して交互配置されているため、メモリアレイ内のワード線は1本おきに上下のサブワードドライバに接続される。
FIG. 24 is a circuit diagram showing an example of the configuration of the sub-word driver string in the DRAM core of FIG. The sub word driver array (SWDA) is composed of a plurality of sub word drivers (SWD). As shown in FIG. 21, the sub word driver column is arranged around the memory array. The sub word driver drives the word lines (WL) in the memory arrays arranged above and below. Further, since the sub word driver columns are alternately arranged with respect to the memory array, every other word line in the memory array is connected to the upper and lower sub word drivers.
サブワードドライバは、NチャネルMOSトランジスタ2個とPチャネルMOSトランジスタ1個で構成される。一方のNチャネルMOSトランジスタは、ゲートにメインワード線(MWLB)が接続され、ドレインにワード線が接続され、ソースに電圧VKKが接続される。他方のNチャネルMOSトランジスタは、ゲートに相補サブワードドライバ選択線(FXB)、ドレインにワード線(WL)が接続され、ソースに電圧VKKが接続される。ここでVKKは待機時のワード線電圧であり、電圧発生回路(VGC)で生成され、接地電位(VSS)よりも低い負電圧である。
The sub word driver is composed of two N channel MOS transistors and one P channel MOS transistor. One N-channel MOS transistor has a gate connected to the main word line (MWLB), a drain connected to the word line, and a source connected to the voltage VKK. The other N-channel MOS transistor has a gate connected to a complementary sub word driver select line (FXB), a drain connected to a word line (WL), and a source connected to a voltage VKK. Here, VKK is a standby word line voltage, which is generated by a voltage generation circuit (VGC) and is a negative voltage lower than the ground potential (VSS).
PチャネルMOSトランジスタは、ゲートにメインワード線が接続され、ドレインにワード線が接続され、ソースにサブワードドライバ選択線(FX)が接続される。一つのサブワードドライバ列上に4組のサブワードドライバ選択線(FX0~4)が配線され、一本のメインワード線で選択される4個のサブワードドライバのうちいずれか1個を選択して1本のワード線が活性化される。
In the P-channel MOS transistor, the main word line is connected to the gate, the word line is connected to the drain, and the sub word driver selection line (FX) is connected to the source. Four sets of sub word driver selection lines (FX0 to FX4) are wired on one sub word driver column, and one of the four sub word drivers selected by one main word line is selected to be one The word line is activated.
図25は、図16のDRAMコアにおけるクロスエリアの構成の一例を示す回路図である。クロスエリア(XP)には、第一ローカルI/O線プリチャージ回路(LEQ1)と、第二ローカルI/O線プリチャージ回路(LEQ2)と、リードライトゲート(RGC)と、CS線ドライバ(CSD)と、CS線プリチャージ回路(SEQ)と、BLEQ信号ドライバ(EQD)と、FX線ドライバ(FXD)が配置される。
FIG. 25 is a circuit diagram showing an example of a cross area configuration in the DRAM core of FIG. The cross area (XP) includes a first local I / O line precharge circuit (LEQ1), a second local I / O line precharge circuit (LEQ2), a read / write gate (RGC), and a CS line driver ( CSD), CS line precharge circuit (SEQ), BLEQ signal driver (EQD), and FX line driver (FXD) are arranged.
第一ローカルI/O線プリチャージ回路(LEQ1)は、相補プリチャージ信号(BLEQB)が活性状態のときに、ローカルI/O線(LIO/LIOB)をVDL/2にプリチャージする。第二ローカルI/O線プリチャージ回路(LEQ2)はリード用イコライズ信号(REQB)が活性状態のときに、ローカルI/O線(LIO/LIOB)を周辺回路電圧(VCL)でプリチャージする。リードライトゲート(RGC)は、ゲート信号(TG/TGB)が活性化されたときに、ローカルI/O線(LIO/LIOB)とメインI/O線(MIO/MIOB)とを接続する回路である。
The first local I / O line precharge circuit (LEQ1) precharges the local I / O line (LIO / LIOB) to VDL / 2 when the complementary precharge signal (BLEQB) is active. The second local I / O line precharge circuit (LEQ2) precharges the local I / O line (LIO / LIOB) with the peripheral circuit voltage (VCL) when the read equalize signal (REQB) is active. The read / write gate (RGC) is a circuit that connects a local I / O line (LIO / LIOB) and a main I / O line (MIO / MIOB) when a gate signal (TG / TGB) is activated. is there.
CS線ドライバ(CSD)は、N側センスアンプイネーブル信号(SAN)が活性状態のときに、N側共通ソース線(CSN)を接地電圧(VSS)に駆動し、P側センスアンプイネーブル信号(SAP1B)が活性状態のときに、P側コモンソースを電源電圧(VSSレベル)に駆動する回路である。CS線プリチャージ回路(SEQ)は、相補プリチャージ信号が活性化されたときにP側、N側共通ソース線をVDL/2にプリチャージする回路である。BLEQ信号ドライバ(EQD)はプリチャージ信号(BLEQ)の相補信号(BLEQB)が入力され、その反転信号を出力する。FX線ドライバ(FXD)は、相補サブワードドライバ選択線(FXB)が入力され、その反転信号をサブワードドライバ線(FX)に出力する。
When the N-side sense amplifier enable signal (SAN) is active, the CS line driver (CSD) drives the N-side common source line (CSN) to the ground voltage (VSS), and the P-side sense amplifier enable signal (SAP1B). ) Is a circuit that drives the P-side common source to the power supply voltage (VSS level) when in the active state. The CS line precharge circuit (SEQ) is a circuit that precharges the P-side and N-side common source lines to VDL / 2 when a complementary precharge signal is activated. The BLEQ signal driver (EQD) receives a complementary signal (BLEQB) of the precharge signal (BLEQ) and outputs an inverted signal thereof. The FX line driver (FXD) receives the complementary sub word driver selection line (FXB) and outputs the inverted signal to the sub word driver line (FX).
図26は2個の本発明のDRAMモジュール(DRAMMOD0,1)とCPUチップ(CPUIC)が光バス(OPIO)に接続される様子を示す図である。図3との違いは、個々のメモリコントローラブロック(MCB)が各DRAMモジュール上の対応するDRAMチップとデータの送受信を行う際、それぞれのDRAMモジュールに対して異なる波長の光信号を用いて、波長多重送受信を行う点である。
FIG. 26 is a diagram showing a state where two DRAM modules (DRAMMOD0, 1) of the present invention and a CPU chip (CPUIC) are connected to an optical bus (OPIO). The difference from FIG. 3 is that when each memory controller block (MCB) transmits and receives data to and from the corresponding DRAM chip on each DRAM module, optical signals having different wavelengths are used for the respective DRAM modules. This is the point of performing multiplex transmission / reception.
例えば、あるCPUコアから要求されたメモリアクセスがMCB0に含まれるメモリコントローラコアで受け付けられたとすると、このメモリコントローラコアはDRAMMOD0上のDRAMIC0にアクセスを行う場合は、波長λ0の光信号を用い、DRAMMOD1上のDRAMIC0にアクセスを行う場合は、波長λ1の光信号を用いる。光バスを構成する光導波路にはλ0とλ1の波長の光信号が多重化され、同時に互いに干渉せずに送受信を行うことができる。このようにすることで、一つのメモリコントローラコアは、複数のDRAMモジュール上のDRAMコアに対して同時にアクセスを行うことができるため、光導波路の本数を増やさずにデータ転送速度を増加することが可能となる。
For example, if a memory access requested from a certain CPU core is received by a memory controller core included in MCB0, this memory controller core uses an optical signal of wavelength λ0 to access DRAMIC0 on DRAMMOD0, and DRAMMOD1 When accessing the above DRAMIC0, an optical signal having a wavelength λ1 is used. Optical signals having wavelengths of λ0 and λ1 are multiplexed on the optical waveguide constituting the optical bus, and transmission and reception can be performed without interfering with each other at the same time. In this way, one memory controller core can simultaneously access the DRAM cores on a plurality of DRAM modules, so the data transfer speed can be increased without increasing the number of optical waveguides. It becomes possible.
図27には本発明の光インターフェースを用いたメモリモジュールとCPUチップとを光導波路で接続した光インターフェース・メモリバスの断面図を示す。図7との違いは、各DRAMモジュールの下部の光カップラー兼フィルター(COUP&FLT)が、CPUから入力された複数の波長(λ0、λ1)の光信号から、特定の波長の光信号を光導波路から一定の割合で分岐させて、モジュールへ導くことができる点である。DRAMモジュール0では光カップラー兼フィルターの長さをL0、光導波路からの距離をD0とすることにより波長λ0の光信号のみを分岐させる。DRAMモジュール1では光カップラー兼フィルターの長さをL1、光導波路からの距離をD1とすることにより波長λ1の光信号のみを分岐させる。このようにすることで、一つのメモリコントローラコアは、複数のDRAMモジュール上のDRAMコアに対して同時にアクセスを行うことができるため、光導波路の本数を増やさずにデータ転送速度を増加することが可能となる。
FIG. 27 shows a cross-sectional view of an optical interface memory bus in which a memory module using an optical interface of the present invention and a CPU chip are connected by an optical waveguide. The difference from FIG. 7 is that the optical coupler / filter (COUP & FLT) at the bottom of each DRAM module receives an optical signal of a specific wavelength from an optical waveguide from an optical signal having a plurality of wavelengths (λ0, λ1) input from the CPU. It is a point that can be branched to a module and led to a module. In the DRAM module 0, the length of the optical coupler / filter is L0, and the distance from the optical waveguide is D0, so that only the optical signal having the wavelength λ0 is branched. In the DRAM module 1, the length of the optical coupler / filter is L1, and the distance from the optical waveguide is D1, so that only the optical signal having the wavelength λ1 is branched. By doing so, one memory controller core can simultaneously access the DRAM cores on a plurality of DRAM modules, so that the data transfer speed can be increased without increasing the number of optical waveguides. It becomes possible.
図28に波長多重化通信を行う場合のCPU側インターフェースチップ(IFCIC)上のインターフェースコア(IFCC)の構成を示す。光インターフェース(OPIF2,OPIF3)、クロック再生回路(CDR2、CDR3)の回路ブロックの動作は図12に示したものと同等である。CPUコア0、CPUコア1からの電気信号のコマンド・アドレス信号(CAI)が先に示したように、クロック再生回路(CDR3)、光インターフェース(OPIF3)によりそれぞれ波長λ0、λ1の光信号に変換され、合波器(MIXW)で合波されて、一つの光インターフェース端子(CAP)により、出力される。
FIG. 28 shows the configuration of the interface core (IFCC) on the CPU side interface chip (IFCIC) when performing wavelength multiplexing communication. The operation of the circuit blocks of the optical interfaces (OPIF2, OPIF3) and clock recovery circuits (CDR2, CDR3) is the same as that shown in FIG. As described above, the command address signal (CAI) of the electrical signals from CPU core 0 and CPU core 1 is converted into optical signals of wavelengths λ0 and λ1 by the clock recovery circuit (CDR3) and the optical interface (OPIF3), respectively. Then, they are multiplexed by a multiplexer (MIXW) and output by one optical interface terminal (CAP).
ライトデータについてもメモリコントローラコア0、メモリコントローラコア1からの電気信号のライトデータが(DQIP)が先に示したように、クロック再生回路(CDR2)、光インターフェース(OPIF2)によりそれぞれ波長λ0、λ1の光信号に変換され、合波器(MIXW)で合波されて、一つの光インターフェース端子(DQP)により、出力される。リードデータについては、一つの光インターフェース端子(DQP)に入力されたリードデータが分波器(DIVW)によって、波長λ0、λ1の光信号に分けられ、それぞれ光インターフェース(OPIF2)、クロック再生回路(CDR2)でパラレルな電気信号に変換されて、メモリコントローラコア0、メモリコントローラ1に入力される。
As for the write data, the write data of the electrical signals from the memory controller core 0 and the memory controller core 1 is the wavelength λ0, λ1 by the clock recovery circuit (CDR2) and the optical interface (OPIF2), respectively, as (DQIP) indicated earlier Are multiplexed by a multiplexer (MIXW), and output by one optical interface terminal (DQP). As for the read data, the read data input to one optical interface terminal (DQP) is divided into optical signals of wavelengths λ0 and λ1 by a demultiplexer (DIVW), and the optical interface (OPIF2) and clock recovery circuit ( The signals are converted into parallel electrical signals by the CDR 2) and input to the memory controller core 0 and the memory controller 1.
このようにすることで、一つのメモリコントローラコアは、複数のDRAMモジュール上のDRAMコアに対して同時にアクセスを行うことができるため、光導波路の本数を増やさずにデータ転送速度を増加することが可能となる。
In this way, one memory controller core can simultaneously access the DRAM cores on a plurality of DRAM modules, so the data transfer speed can be increased without increasing the number of optical waveguides. It becomes possible.
以上、実施例に基づいて説明してきたが、本実施例に記載される発明は、マルチコア構成のDRAMチップを複数配置したメモリモジュールにおいて、光インターフェースを用いて、1本あたりの信号線のデータレートを数十Gbpsに向上でき、メモリモジュールから数十本の信号線を入出力した場合でも、安定的なデータ伝送が可能となり、システムの性能向上に寄与することができる。
As described above, the invention described in this embodiment is based on the data rate of the signal line per line using an optical interface in a memory module in which a plurality of multi-core DRAM chips are arranged. Can be improved to several tens of Gbps, and even when tens of signal lines are input / output from the memory module, stable data transmission is possible, which contributes to an improvement in system performance.
8/10BDEC:8/10Bデコーダ、8/10BENC:8/10Bエンコーダ、A:アドレス、ACC:アレイ制御回路、ACT:アクティベートコマンド、ADD:アドレス信号、AMP:アンプ回路、AR:無反射コーティング処理、ARY:メモリアレイ、AX:行アドレス、AY:列アドレス、BA:バンクアドレス、BANK:メモリバンク、BASE:プリント基板、BC:バイアス回路、BL,BLT,BLB:ビット線、LEQ:ビット線プリチャージ信号、BUS:バス、CA:コマンド・アドレス光信号、CAI:コマンド・アドレス信号、CAP:コマンド・アドレス光端子、CAIP:コマンド・アドレス端子、CAIS:コマンド・アドレスシリアルデータ、CASB:列アドレスストローブ信号、CASP:コマンド・アドレスシリアル端子、CBUS:コア内バス、CC:クロスカップル・アンプ、CDC:コマンドデコーダ、CDR:クロック再生回路、CK:DRAMクロック、CKA:コマンド・アドレスクロック、CKC:CPUクロック、CKD:データクロック、CKP:クロック端子、COMC:共通回路、CONT:制御部、CNTL:制御回路、COUP:光カップラー、CPUIC:CPUチップ、CPUC:CPUコア、CSB:チップ選択信号、CSD:CS線ドライバ、CSN:N側共通ソース線、CSP:P側共通ソース線、Cs:キャパシタ、DIV:分周回路、DIVW:分波器、DIS:シリアル入力データ、DM:データマスク、DMUX:デマルチプレクサ、DOS:シリアル出力データ、DQ:データ光信号、DQI:データ信号、DQIP:データ端子、DQP:データ光端子、DRAMIC:DRAMチップ、DRAMIC:DRAMコア、DRAMMOD:DRAMモジュール、DSP:シリアル入力データ端子、QSP:シリアル出力データ端子、EQD:BLEQ信号ドライバ、FUSE:フューズ、FX:サブワードドライバ選択線、FXD:FX線ドライバ、IBC:入力回路、IBUS:内部バス、IBUSC:チップ内バス制御回路、IFCIC:CPU側インターフェースチップ、IFCC:CPU側インターフェースコア、IFDIC:DRAM側インターフェースチップ、IFDC:DRAM側インターフェースコア、IFD-EIC:電気インターフェースチップ、IFD-EC:電気インターフェースコア、IFD-OIC:光インターフェースチップ、IFD-OC:光インターフェースコア、LD:レーザー、LIO,LIOT,LIOB:ローカルIO線、LTC:ラッチ回路、MC:メモリセル、MCB:メモリコントローラブロック、MCC:メモリコントローラコア、MEM:DRAMコア、MIO,MIOT,MIOB:メインIO線、MIXW:合波器、ML:ミラー構造、MOD:変調器、MUX:マルチプレクサ、OBC:出力回路、OPIF:光インターフェース回路、OPIO:光バス、PCC:プリチャージ回路、PD:光検出器、RASB:行アドレスストローブ信号、READ:リードコマンド、RESETB:リセット信号、R/W AMP:リードライト回路、SA:センスアンプ、SAA:センスアンプ列、SEQ:CS線プリチャージ回路、SHR:センスアンプ分離信号、SN:蓄積ノード、SUB:ボード基板、SWD:サブワードドライバ、SWDA:サブワードドライバ列、TIA:トランスインピーダンスアンプ、TSVC:貫通ビア用入出力回路、VIA:貫通ビア、VSP:電源パッド、WEB:ライトイネーブル、WG:光導波路、WL:ワード線、WRITE:ライトコマンド、XDEC:行デコーダ、XP:クロスエリア、YDEC:列デコーダ、YS:列選択線。
8 / 10BDEC: 8 / 10B decoder, 8 / 10BENC: 8 / 10B encoder, A: address, ACC: array control circuit, ACT: activate command, ADD: address signal, AMP: amplifier circuit, AR: non-reflective coating processing, ARY: memory array, AX: row address, AY: column address, BA: bank address, BANK: memory bank, BASE: printed circuit board, BC: bias circuit, BL, BLT, BLB: bit line, LEQ: bit line precharge Signal, BUS: bus, CA: command address optical signal, CAI: command address signal, CAP: command address optical terminal, CAIP: command address terminal, CAIS: command address serial data, CASB: column address strobe signal , CAS : Command address serial terminal, CBUS: Core bus, CC: Cross-coupled amplifier, CDC: Command decoder, CDR: Clock recovery circuit, CK: DRAM clock, CKA: Command address clock, CKC: CPU clock, CKD: Data clock, CKP: Clock terminal, COMC: Common circuit, CONT: Control unit, CNTL: Control circuit, COUP: Optical coupler, CPUIC: CPU chip, CPUC: CPU core, CSB: Chip selection signal, CSD: CS line driver, CSN: N side common source line, CSP: P side common source line, Cs: capacitor, DIV: frequency divider, DIVW: duplexer, DIS: serial input data, DM: data mask, DMUX: demultiplexer, DOS: Serial output data, DQ: Optical signal, DQI: data signal, DQIP: data terminal, DQP: data optical terminal, DRAMIC: DRAM chip, DRAMIC: DRAM core, DRAMMOD: DRAM module, DSP: serial input data terminal, QSP: serial output data terminal, EQD : BLEQ signal driver, FUSE: fuse, FX: sub-word driver selection line, FXD: FX line driver, IBC: input circuit, IBUS: internal bus, IBUSC: intra-chip bus control circuit, IFCIC: CPU side interface chip, IFCC: CPU Side interface core, IFDIC: DRAM side interface chip, IFDC: DRAM side interface core, IFD-EIC: electrical interface chip, IFD-EC: electrical interface core, IFD-OIC: Optical interface chip, IFD-OC: Optical interface core, LD: Laser, LIO, LIOT, LIOB: Local IO line, LTC: Latch circuit, MC: Memory cell, MCB: Memory controller block, MCC: Memory controller Core, MEM: DRAM core, MIO, MIOT, MIOB: main IO line, MIXW: multiplexer, ML: mirror structure, MOD: modulator, MUX: multiplexer, OBC: output circuit, OPIF: optical interface circuit, OPIO: Optical bus, PCC: Precharge circuit, PD: Photo detector, RASB: Row address strobe signal, READ: Read command, RESETB: Reset signal, R / W AMP: Read / write circuit, SA: Sense amplifier, SAA: Sense amplifier Column, S EQ: CS line precharge circuit, SHR: sense amplifier separation signal, SN: storage node, SUB: board substrate, SWD: subword driver, SWDA: subword driver string, TIA: transimpedance amplifier, TSVC: input / output circuit for through via , VIA: Through-via, VSP: Power supply pad, WEB: Write enable, WG: Optical waveguide, WL: Word line, WRITE: Write command, XDEC: Row decoder, XP: Cross area, YDEC: Column decoder, YS: Column selection line.
8 / 10BDEC: 8 / 10B decoder, 8 / 10BENC: 8 / 10B encoder, A: address, ACC: array control circuit, ACT: activate command, ADD: address signal, AMP: amplifier circuit, AR: non-reflective coating processing, ARY: memory array, AX: row address, AY: column address, BA: bank address, BANK: memory bank, BASE: printed circuit board, BC: bias circuit, BL, BLT, BLB: bit line, LEQ: bit line precharge Signal, BUS: bus, CA: command address optical signal, CAI: command address signal, CAP: command address optical terminal, CAIP: command address terminal, CAIS: command address serial data, CASB: column address strobe signal , CAS : Command address serial terminal, CBUS: Core bus, CC: Cross-coupled amplifier, CDC: Command decoder, CDR: Clock recovery circuit, CK: DRAM clock, CKA: Command address clock, CKC: CPU clock, CKD: Data clock, CKP: Clock terminal, COMC: Common circuit, CONT: Control unit, CNTL: Control circuit, COUP: Optical coupler, CPUIC: CPU chip, CPUC: CPU core, CSB: Chip selection signal, CSD: CS line driver, CSN: N side common source line, CSP: P side common source line, Cs: capacitor, DIV: frequency divider, DIVW: duplexer, DIS: serial input data, DM: data mask, DMUX: demultiplexer, DOS: Serial output data, DQ: Optical signal, DQI: data signal, DQIP: data terminal, DQP: data optical terminal, DRAMIC: DRAM chip, DRAMIC: DRAM core, DRAMMOD: DRAM module, DSP: serial input data terminal, QSP: serial output data terminal, EQD : BLEQ signal driver, FUSE: fuse, FX: sub-word driver selection line, FXD: FX line driver, IBC: input circuit, IBUS: internal bus, IBUSC: intra-chip bus control circuit, IFCIC: CPU side interface chip, IFCC: CPU Side interface core, IFDIC: DRAM side interface chip, IFDC: DRAM side interface core, IFD-EIC: electrical interface chip, IFD-EC: electrical interface core, IFD-OIC: Optical interface chip, IFD-OC: Optical interface core, LD: Laser, LIO, LIOT, LIOB: Local IO line, LTC: Latch circuit, MC: Memory cell, MCB: Memory controller block, MCC: Memory controller Core, MEM: DRAM core, MIO, MIOT, MIOB: main IO line, MIXW: multiplexer, ML: mirror structure, MOD: modulator, MUX: multiplexer, OBC: output circuit, OPIF: optical interface circuit, OPIO: Optical bus, PCC: Precharge circuit, PD: Photo detector, RASB: Row address strobe signal, READ: Read command, RESETB: Reset signal, R / W AMP: Read / write circuit, SA: Sense amplifier, SAA: Sense amplifier Column, S EQ: CS line precharge circuit, SHR: sense amplifier separation signal, SN: storage node, SUB: board substrate, SWD: subword driver, SWDA: subword driver string, TIA: transimpedance amplifier, TSVC: input / output circuit for through via , VIA: Through-via, VSP: Power supply pad, WEB: Write enable, WG: Optical waveguide, WL: Word line, WRITE: Write command, XDEC: Row decoder, XP: Cross area, YDEC: Column decoder, YS: Column selection line.
Claims (19)
- 複数の第1メモリセルを有する第1情報記憶部と、
複数の第2メモリセルを有する第2情報記憶部と、
前記第1情報記憶部に対応にて設けられ、前記複数の第1メモリセルにアクセスするための第1コマンド・アドレス光信号が入力される第1インターフェース部と、
前記第2情報記憶部に対応して設けられ、前記複数の第2メモリセルにアクセスするための第2コマンド・アドレス光信号が入力される第2インターフェース部と、を具備し、
前記第1インターフェース部は、前記第1コマンド・アドレス光信号から第1アドレスクロックを抽出するための第1クロック再生回路を有するとともに、前記第1アドレスクロックに従って、前記第1コマンド・アドレス光信号から抽出された第1コマンド及び第1アドレスを電気信号として前記第1情報記憶部に出力し、
前記第2インターフェース部は、前記第2コマンド・アドレス光信号から第2アドレスクロックを抽出するための第2クロック再生回路を有するとともに、前記第2アドレスクロックに従って、前記第2コマンド・アドレス光信号から抽出された第2コマンド及び第2アドレスを電気信号として前記第2情報記憶部に出力することを特徴とする半導体記憶装置。 A first information storage unit having a plurality of first memory cells;
A second information storage unit having a plurality of second memory cells;
A first interface unit provided corresponding to the first information storage unit, to which a first command / address optical signal for accessing the plurality of first memory cells is input;
A second interface unit provided corresponding to the second information storage unit, to which a second command / address optical signal for accessing the plurality of second memory cells is input, and
The first interface unit includes a first clock recovery circuit for extracting a first address clock from the first command / address optical signal, and from the first command / address optical signal according to the first address clock. Outputting the extracted first command and first address as an electrical signal to the first information storage unit;
The second interface unit includes a second clock recovery circuit for extracting a second address clock from the second command / address optical signal, and from the second command / address optical signal according to the second address clock. A semiconductor memory device, wherein the extracted second command and second address are output to the second information storage unit as electrical signals. - 請求項1において、
前記第1情報記憶部と前記第2情報記憶部は、同一チップ上に形成されることを特徴とする半導体記憶装置。 In claim 1,
The semiconductor memory device, wherein the first information storage unit and the second information storage unit are formed on the same chip. - 請求項2において、
前記第1情報記憶部は、前記第1アドレスクロックを逓倍したクロックで動作し、
前記第2情報記憶部は、前記第2アドレスクロックを逓倍したクロックで動作し、
前記第1情報記憶部と前記第2情報記憶部は、各々独立して動作可能であることを特徴とする半導体記憶装置。 In claim 2,
The first information storage unit operates with a clock obtained by multiplying the first address clock,
The second information storage unit operates with a clock obtained by multiplying the second address clock,
The semiconductor memory device, wherein the first information storage unit and the second information storage unit can operate independently. - 請求項3において、
前記第1インターフェース部は、前記第1情報記憶部に記憶されるべき第1ライトデータ光信号が入力されるとともに、前記第1情報記憶部から読み出された第1リードデータ光信号を出力し、
前記第1インターフェース部は、前記第1ライトデータ光信号を、電気信号に変換した後、シリアル・パラレル変換を行い、前記第1ライトデータ光信号のバス幅より大きいバス幅で前記第1情報記憶部に出力し、
前記第1インターフェース部は、前記第1リードデータ光信号のバス幅より大きいバス幅で、前記第1情報記憶部から読み出されたデータを、パラレル・シリアル変換した後、光信号に変換し、前記第1リードデータ光信号として出力することを特徴とする半導体記憶装置。 In claim 3,
The first interface unit receives a first write data optical signal to be stored in the first information storage unit and outputs a first read data optical signal read from the first information storage unit. ,
The first interface unit converts the first write data optical signal into an electric signal, performs serial / parallel conversion, and stores the first information in a bus width larger than the bus width of the first write data optical signal. Output to
The first interface unit has a bus width larger than the bus width of the first read data optical signal, and the data read from the first information storage unit is converted into an optical signal after parallel-serial conversion, A semiconductor memory device that outputs the first read data optical signal. - 請求項4において、
前記第1インターフェース部は、前記第1クロック再生回路に接続される第1光インターフェース回路と、前記第1ライトデータ光信号が入力されると共に、前記第1リードデータ光信号を出力する第2光インターフェース回路と、前記第2光インターフェース回路に接続される第3クロック再生回路と、を更に有し、
前記第1光インターフェース回路は、前記第1コマンド・アドレス光信号を第1電流信号に変換する光検出器と、前記第1電流信号を第1電圧信号に変換し、第1コマンド・アドレスシリアルデータとする第1トランスインピーダンスアンプとを有し、
前記第1クロック再生回路は、前記第1コマンド・アドレスシリアルデータを受けて前記第1アドレスクロックを生成する第1PLL回路と、前記第1コマンド・アドレスシリアルデータを並列化する第1デマルチプレクサとを有し、
前記第2光インターフェース回路は、前記第1ライドデータ光信号を第2電流信号に変換する第2光検出器と、前記第2電流信号を第2電圧信号に変換し、第1ライトシリアルデータを生成する第2トランスインピーダンスアンプと、前記第1情報記憶部から読み出されたデータに従いレーザーから出力された光を変調することにより、前記第1リードデータ光信号を生成する第1光変調器を有し、
前記第3クロック再生回路は、前記第1ライトシリアルデータを受けて第1データクロックを生成する第2PLL回路と、前記第1ライトシリアルデータを並列化する第2デマルチプレクサと、前記第1情報記憶部から読み出されたデータを直列化し、前記第1光変調器に出力する第1マルチプレクサとを有することを特徴とする半導体記憶装置。 In claim 4,
A first optical interface circuit connected to the first clock recovery circuit; and a second light that receives the first write data optical signal and outputs the first read data optical signal. An interface circuit; and a third clock recovery circuit connected to the second optical interface circuit,
The first optical interface circuit converts the first command / address optical signal into a first current signal, converts the first current signal into a first voltage signal, and outputs first command / address serial data. A first transimpedance amplifier,
The first clock recovery circuit includes a first PLL circuit that receives the first command / address serial data and generates the first address clock, and a first demultiplexer that parallelizes the first command / address serial data. Have
The second optical interface circuit converts the first ride data optical signal into a second current signal, converts the second current signal into a second voltage signal, and converts the first write serial data into the second voltage signal. A second transimpedance amplifier to be generated, and a first optical modulator that generates the first read data optical signal by modulating light output from the laser in accordance with data read from the first information storage unit. Have
The third clock recovery circuit receives the first write serial data, generates a first data clock, a second PLL circuit, a second demultiplexer that parallelizes the first write serial data, and the first information storage. A semiconductor memory device comprising: a first multiplexer that serializes data read from the first unit and outputs the data to the first optical modulator. - 請求項5において、
前記第1インターフェース部は、前記第1情報記憶部とは異なるチップに形成され、
前記第2インターフェース部は、前記第2情報記憶部とは異なるチップに形成されることを特徴とする半導体記憶装置。 In claim 5,
The first interface unit is formed on a different chip from the first information storage unit,
The semiconductor memory device, wherein the second interface unit is formed on a different chip from the second information storage unit. - 請求項6において、
前記第1光インターフェース回路は、前記第1クロック再生回路とは異なるチップに形成され、
前記第2光インターフェース回路は、前記第3クロック再生回路とは異なるチップに形成されることを特徴とする半導体記憶装置。 In claim 6,
The first optical interface circuit is formed on a different chip from the first clock recovery circuit;
The semiconductor memory device, wherein the second optical interface circuit is formed on a different chip from the third clock recovery circuit. - 請求項5において、
前記第1情報記憶部と前記第1及び第3クロック再生回路は、同一チップ上に形成され、
前記第1及び第2光インターフェース回路は、前記第1情報記憶部とは異なるチップに形成されることを特徴とする半導体記憶装置。 In claim 5,
The first information storage unit and the first and third clock recovery circuits are formed on the same chip,
The semiconductor memory device, wherein the first and second optical interface circuits are formed on a chip different from the first information storage unit. - 請求項1において、
前記第1インターフェース部は、前記第1クロック再生回路に接続され、前記第1コマンド・アドレス光信号を電気信号に変換する第1光インターフェース回路と、入力された第1ライトデータ光信号を電気信号に変換すると共に、電気信号として入力されたデータを第1リードデータ光信号に変換し、前記第1リードデータ光信号を出力する第2光インターフェース回路と、前記第2光インターフェース回路に接続され、前記第1ライトデータ光信号から変換された前記電気信号から第1データクロックを抽出する第3クロック再生回路と、を更に有し、
前記第1及び第2光インターフェース回路は、前記第1情報記憶部とは異なるチップに形成され、
前記第1情報記憶部が設けられたチップと前記第1及び第2光インターフェース回路が設けられたチップは、基板に対し鉛直方向に積層されることを特徴とする半導体記憶装置。 In claim 1,
The first interface unit is connected to the first clock recovery circuit, converts a first command / address optical signal into an electrical signal, and an input first write data optical signal as an electrical signal. A second optical interface circuit that converts data input as an electrical signal into a first read data optical signal and outputs the first read data optical signal, and is connected to the second optical interface circuit, A third clock recovery circuit for extracting a first data clock from the electrical signal converted from the first write data optical signal;
The first and second optical interface circuits are formed on a different chip from the first information storage unit,
The semiconductor memory device, wherein the chip provided with the first information storage unit and the chip provided with the first and second optical interface circuits are stacked in a vertical direction with respect to the substrate. - 請求項9において、
前記第1及び第2光インターフェース回路が設けられたチップと前記第1情報記憶部とが設けられたチップとは、前記情報記憶部が設けられたチップを貫通する貫通電極により接続されることを特徴とする半導体記憶装置。 In claim 9,
The chip provided with the first and second optical interface circuits and the chip provided with the first information storage unit are connected by a through electrode penetrating the chip provided with the information storage unit. A semiconductor memory device. - 情報処理部と、
外部から第1リードデータ光信号が入力される第1インターフェース部と、外部から第2リードデータ光信号が入力される第2インターフェース部と、を有し、前記情報処理部に接続されるメモリコントロール部とを具備し、
前記第1インターフェース部は、前記第1リードデータ光信号から第1データクロックを抽出するための第1クロック再生回路を有するとともに、前記第1データクロックに従って、前記第1リードデータ光信号から抽出された第1リードデータを電気信号として出力し、
前記第2インターフェース部は、前記第2リードデータ光信号から第2データクロックを抽出するための第2クロック再生回路を有するとともに、前記第2データクロックに従って、前記第2リードデータ光信号から抽出された第2リードデータを電気信号としてすることを特徴とする情報処理装置。 An information processing unit;
A memory control having a first interface unit to which a first read data optical signal is input from the outside and a second interface unit to which a second read data optical signal is input from the outside, and is connected to the information processing unit And comprising
The first interface unit has a first clock recovery circuit for extracting a first data clock from the first read data optical signal, and is extracted from the first read data optical signal according to the first data clock. Output the first read data as an electrical signal,
The second interface unit includes a second clock recovery circuit for extracting a second data clock from the second read data optical signal, and is extracted from the second read data optical signal according to the second data clock. An information processing apparatus using the second read data as an electrical signal. - 請求項11において、
前記情報処理部は、第1CPUと、第2CPUと、を有し、
前記メモリコントロール部は、前記第1CPUの指示に従って動作を行うと共に、前記第1インターフェース部を有する第1メモリコントロールコアと、前記第2CPUの指示に従って動作を行うと共に、前記第2インターフェース部を有する第2メモリコントロールコアと、を有することを特徴とする情報処理装置。 In claim 11,
The information processing unit includes a first CPU and a second CPU,
The memory control unit operates in accordance with an instruction from the first CPU, operates in accordance with an instruction from the first CPU and the second CPU, and has a second interface unit. An information processing apparatus comprising: 2 memory control cores. - 請求項12において、
前記第1メモリコントロールコアと前記第2メモリコントロールコアは、独立したクロックで動作可能であることを特徴とする情報処理装置。 In claim 12,
The information processing apparatus, wherein the first memory control core and the second memory control core are operable with independent clocks. - 請求項13において、
前記第1インターフェース部は、前記情報処理装置の外部に第1コマンド・アドレス光信号を出力すると共に、前記情報処理装置の外部に第1ライトデータ光信号を出力し、
前記第2インターフェース部は、前記情報処理装置の外部に第2コマンド・アドレス光信号を出力すると共に、前記情報処理装置の外部に第2ライトデータ光信号を出力し、
前記第1インターフェース部は、前記第1リードデータ光信号を電気信号に変換することにより抽出された前記第1リードデータをシリアル・パラレル変換を行い、前記第1リードデータ光信号のバス幅より大きいバス幅で前記第1リードデータを前記情報処理装置の内部に出力し、前記第1インターフェース部に電気信号として入力される第1コマンド・アドレスをパラレル・シリアル変換を行った後、光信号に変換し、前記第1コマンド・アドレス光信号として出力し、前記第1インターフェース部に電気信号として入力される第1ライトデータをパラレル・シリアル変換した後、光信号に変換し、前記第1ライトデータ光信号として出力し、
前記第2インターフェース部は、前記第2リードデータ光信号を電気信号に変換することにより抽出された前記第2リードデータをシリアル・パラレル変換を行い、前記第2リードデータ光信号のバス幅より大きいバス幅で前記第2リードデータを前記情報処理装置の内部に出力し、前記第2インターフェース部に電気信号として入力される第2コマンド・アドレスをパラレル・シリアル変換を行った後、光信号に変換し、前記第2コマンド・アドレス光信号として出力し、前記第2インターフェース部に電気信号として入力される第2ライトデータをパラレル・シリアル変換した後、光信号に変換し、前記第2ライトデータ光信号として出力することを特徴とする情報処理装置。 In claim 13,
The first interface unit outputs a first command / address optical signal to the outside of the information processing apparatus, and outputs a first write data optical signal to the outside of the information processing apparatus,
The second interface unit outputs a second command / address optical signal to the outside of the information processing apparatus, and outputs a second write data optical signal to the outside of the information processing apparatus,
The first interface unit performs serial / parallel conversion on the first read data extracted by converting the first read data optical signal into an electrical signal, and is larger than a bus width of the first read data optical signal. The first read data is output to the inside of the information processing apparatus with a bus width, and the first command address input as an electric signal to the first interface unit is converted into an optical signal after parallel-serial conversion. The first write data output as the first command / address optical signal and converted into an optical signal after parallel-serial conversion of the first write data input as the electric signal to the first interface unit, and the first write data light Output as a signal,
The second interface unit performs serial / parallel conversion on the second read data extracted by converting the second read data optical signal into an electrical signal, and is larger than a bus width of the second read data optical signal. The second read data is output to the inside of the information processing device with a bus width, and the second command address input as an electric signal to the second interface unit is converted into an optical signal after parallel-serial conversion. The second write data that is output as the second command / address optical signal and input to the second interface unit as an electric signal is converted from the second write data to the optical signal after parallel / serial conversion. An information processing apparatus that outputs the signal as a signal. - 請求項14において、
前記第1インターフェース部は、第1PLL回路を更に有し、前記第1PLL回路から発生される第1クロックに従って、前記第1コマンド・アドレス光信号、及び、前記第1ライトデータ光信号を生成し、
前記第2インターフェース部は、第2PLL回路を更に有し、前記第2PLL回路から発生される第2クロックに従って、前記第2コマンド・アドレス光信号、及び、前記第2ライトデータ光信号を生成することを特徴とする情報処理装置。 In claim 14,
The first interface unit further includes a first PLL circuit, and generates the first command / address optical signal and the first write data optical signal according to a first clock generated from the first PLL circuit,
The second interface unit further includes a second PLL circuit, and generates the second command / address optical signal and the second write data optical signal in accordance with a second clock generated from the second PLL circuit. An information processing apparatus characterized by the above. - 情報処理部と、
第1情報記憶部、及び、第2情報記憶部を有する第1メモリモジュールと、
第3情報記憶部、及び、第4情報記憶部を有する第2メモリモジュールと、
前記情報処理部と前記第1及び第3情報記憶部との間で第1コマンド・アドレス光信号、及び、第1データ光信号を伝送する第1光導波路と、
前記情報処理部と前記第2及び第4情報記憶部との間で第2コマンド・アドレス光信号、及び、第2データ光信号を伝送する第2光導波路とを具備し、
前記第1光導波路と前記第2光導波路とは、独立して伝送可能であることを特徴とする情報処理装置。 An information processing unit;
A first memory module having a first information storage unit and a second information storage unit;
A second memory module having a third information storage unit and a fourth information storage unit;
A first optical waveguide for transmitting a first command / address optical signal and a first data optical signal between the information processing unit and the first and third information storage units;
A second optical waveguide for transmitting a second command / address optical signal and a second data optical signal between the information processing unit and the second and fourth information storage units;
The information processing apparatus, wherein the first optical waveguide and the second optical waveguide can be transmitted independently. - 請求項16において、
前記第1光導波路は、前記第1メモリモジュールの直下に前記第1光導波路に平行して配置される第1光カップラーと、前記第2メモリモジュールの直下に前記第1光導波路に平行して配置される第2光カップラーと、前記情報処理部の直下に光の進行方向に対し45度傾いた面をもつ第1ミラー構造と、前記第1ミラー構造と反対側の端部に設けられる第1無反射コーティング部とを有し、
前記第1光カップラーは、前記第1光導波路を介して伝送された光信号が一定の割合で結合すると共に、その一端が光の進行方向に対し45度傾いた面をもつ第2ミラー構造を有し、
前記第2光カップラーは、前記第1光導波路を介して伝送された光信号が一定の割合で結合すると共に、その一端が光の進行方向に対し45度傾いた面をもつ第3ミラー構造を有することを特徴とする情報処理装置。 In claim 16,
The first optical waveguide includes a first optical coupler disposed in parallel to the first optical waveguide directly below the first memory module, and parallel to the first optical waveguide directly below the second memory module. A second optical coupler disposed; a first mirror structure having a surface inclined by 45 degrees with respect to a traveling direction of light immediately below the information processing unit; and a first mirror structure provided at an end opposite to the first mirror structure. 1 non-reflective coating part,
The first optical coupler has a second mirror structure in which optical signals transmitted through the first optical waveguide are coupled at a constant rate, and one end thereof has a surface inclined by 45 degrees with respect to the light traveling direction. Have
The second optical coupler has a third mirror structure in which optical signals transmitted through the first optical waveguide are coupled at a constant rate, and one end thereof has a surface inclined by 45 degrees with respect to the light traveling direction. An information processing apparatus comprising: - 請求項16において、
前記情報処理部と前記第1情報記憶部は、第1の波長の光信号で前記第1コマンド・アドレス光信号及び前記第1データ光信号を送受信し、
前記情報処理部と前記第3情報記憶部は、前記第1の波長と異なる第2の波長の光信号で前記第1コマンド・アドレス光信号及び第1データ光信号を送受信し、
前記情報処理装置は、前記第1の波長の前記第1コマンド・アドレス光信号と前記第2の波長の前記第1コマンド・アドレス光信号とを重畳して出力することを特徴とする情報処理装置。 In claim 16,
The information processing unit and the first information storage unit transmit and receive the first command / address optical signal and the first data optical signal using an optical signal having a first wavelength,
The information processing unit and the third information storage unit transmit and receive the first command / address optical signal and the first data optical signal using an optical signal having a second wavelength different from the first wavelength,
The information processing apparatus superimposes and outputs the first command / address optical signal having the first wavelength and the first command / address optical signal having the second wavelength. . - 請求項18において、
前記第1光導波路は、前記第1メモリモジュールの直下に設けられ、前記第1の波長の前記第1コマンド・アドレス光信号及び前記第1データ光信号を選択して結合する第1光カップラー兼フィルターと、前記第2メモリモジュールの直下に設けられ、前記第2の波長の前記第1コマンド・アドレス光信号及び前記第1データ光信号を選択して結合する第2光カップラー兼フィルターと、を有することを特徴とする情報処理装置。
In claim 18,
The first optical waveguide is provided immediately below the first memory module, and serves as a first optical coupler that selectively couples the first command / address optical signal and the first data optical signal of the first wavelength. A filter, and a second optical coupler / filter provided immediately below the second memory module, which selectively combines the first command / address optical signal and the first data optical signal of the second wavelength. An information processing apparatus comprising:
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