WO2011122228A1 - 半導体内蔵基板 - Google Patents
半導体内蔵基板 Download PDFInfo
- Publication number
- WO2011122228A1 WO2011122228A1 PCT/JP2011/054881 JP2011054881W WO2011122228A1 WO 2011122228 A1 WO2011122228 A1 WO 2011122228A1 JP 2011054881 W JP2011054881 W JP 2011054881W WO 2011122228 A1 WO2011122228 A1 WO 2011122228A1
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- semiconductor element
- heat dissipation
- semiconductor
- layer
- wiring
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1434—Memory
- H01L2924/1435—Random access memory [RAM]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1434—Memory
- H01L2924/145—Read-only memory [ROM]
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
- H05K1/0203—Cooling of mounted components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10431—Details of mounted components
- H05K2201/10507—Involving several components
- H05K2201/10515—Stacked components
Definitions
- the present invention relates to a semiconductor-embedded substrate that incorporates a semiconductor element.
- the semiconductor-embedded substrate can suppress the mounting area of the semiconductor element by incorporating the semiconductor element in the built-in substrate.
- This semiconductor-embedded technology is expected as a high-density mounting technology that realizes further higher integration and higher functionality of a semiconductor device, and realizes package thinning, cost reduction, high frequency compatibility, low stress connection, and the like.
- the insulating layer is formed so as to cover the semiconductor element, most of the heat is trapped in or near the semiconductor element, and the temperature of the semiconductor element may be increased. .
- Patent Document 1 a semiconductor element 1002 is disposed on a metal plate 1001 serving as a support with an adhesive layer 1003 with a circuit surface facing upward, and the semiconductor element is embedded in an insulating layer 1004.
- a semiconductor-embedded substrate is disclosed in which a wiring layer 1005 is laminated thereon (see FIG. 17). According to Patent Document 1, by using the metal plate 1001 as a support for the semiconductor element 1002, it is possible to provide a semiconductor-embedded substrate that can suppress warping of the semiconductor element and has excellent heat dissipation characteristics.
- Patent Document 2 discloses a semiconductor-embedded substrate in which a semiconductor element is disposed on a substrate made of silicon having excellent thermal conductivity, and an insulating layer is formed on the silicon substrate so as to cover the semiconductor element. Has been. By utilizing the thermal conductivity of the silicon substrate, a low thermal resistance type semiconductor-embedded substrate can be manufactured. Patent Document 2 also describes that an electronic circuit including an active element or the like may be formed on the silicon substrate itself.
- an object of the present invention is to provide a semiconductor-embedded substrate using a semiconductor element as a substrate and having excellent heat dissipation.
- the present invention provides A first semiconductor element as a substrate; A second semiconductor element disposed on the circuit surface side of the first semiconductor element with the circuit surface facing in the same direction; An insulating layer containing the second semiconductor element; Including A heat dissipation layer is disposed between at least the first semiconductor element and the second semiconductor element; The heat dissipation layer is a substrate with a built-in semiconductor, wherein the heat dissipation layer is spread on the first semiconductor element and outside the second semiconductor element.
- heat dissipation layer between a first semiconductor element serving as a substrate and a second semiconductor element incorporated therein, heat dissipation can be improved, and malfunction due to heat can be suppressed. Can do.
- (A) It is a schematic top view which shows the state in which the thermal radiation layer is formed in the non-contact with the 1st electrode terminal.
- (B) It is a schematic top view which shows the state in which the thermal radiation layer is formed in contact with the 1st electrode terminal.
- (A) It is a schematic top view which shows the example of arrangement
- FIG. 1 It is a schematic top view which shows the state in which the thermal radiation layer was formed between the area
- A It is a schematic top view which shows the example of arrangement
- B It is a schematic top view which shows the state in which the thermal radiation layer was formed in the area
- FIG. 10 is a horizontal cross-sectional view taken along the dotted line Y in FIG. 9, and is a schematic cross-sectional view showing a state in which a heat dissipation via is formed on the heat dissipation layer.
- It is a schematic sectional drawing which shows the structural example of the board
- FIG. 6 is a cross-sectional process diagram illustrating an example of a method for manufacturing the semiconductor-embedded substrate of Embodiment 1. It is a schematic sectional drawing for demonstrating the structure of the conventional semiconductor built-in board
- the present invention uses the first semiconductor element as the substrate.
- a second semiconductor element is disposed on the first semiconductor element serving as the substrate, and the second semiconductor element is built in the insulating layer.
- the circuit surfaces of the first semiconductor element and the second semiconductor element are arranged in the same direction. That is, the second semiconductor element is disposed face up on the first semiconductor element disposed with the circuit surface facing upward.
- a heat dissipation layer is disposed between the first semiconductor element and the second semiconductor element, and the heat dissipation layer extends on the first semiconductor element and outside the second semiconductor element. .
- the present invention by using a semiconductor element as a substrate serving as a support, high integration and high functionality of a semiconductor-embedded substrate can be achieved.
- a semiconductor element as a substrate serving as a support
- high integration and high functionality of a semiconductor-embedded substrate can be achieved.
- the present invention can provide a semiconductor-embedded substrate capable of high integration and high functionality with excellent heat dissipation.
- FIG. 1 is a schematic cross-sectional view for explaining the semiconductor-embedded substrate of this embodiment.
- a heat dissipation layer 105 is formed on a first semiconductor element 101 as a substrate, and a second semiconductor element 102 is disposed on the heat dissipation layer 105.
- a first semiconductor element 101 and a second semiconductor element 102 are both arranged with their circuit surfaces facing upward, and are disposed with their circuit surfaces facing in the same direction.
- the first semiconductor element 101 and the second semiconductor element 102 have a first electrode terminal 103 and a second electrode terminal 104 on the circuit surface side, respectively.
- the heat dissipation layer 105 is disposed between the first semiconductor element 101 and the second semiconductor element serving as a substrate.
- An adhesive (not shown) may be disposed between the heat dissipation layer 105 and the second semiconductor element.
- the insulating layer 106 is disposed on the first semiconductor element 101 and the heat dissipation layer 105 and incorporates the second semiconductor element 102.
- a first wiring layer 109 is disposed on the insulating layer 106. At least one wiring of the first wiring layer 109 is electrically connected to the second electrode terminal 104 through an element via 108 formed in the insulating layer 106. In addition, at least one wiring of the first wiring layer 109 is electrically connected to the first electrode terminal 103 through a wiring via 107 formed in the insulating layer 106.
- the first wiring layer 109 is covered with the first wiring insulating layer 110, and the second wiring layer 112 is disposed on the first wiring insulating layer 110. At least one wiring of the second wiring layer 112 is electrically connected to at least one wiring of the first wiring layer 109 via the first via 111 formed in the first wiring insulating layer 110. Yes.
- the second wiring layer 112 is covered with the second wiring insulating layer 113, and the third wiring layer 115 is disposed on the second wiring insulating layer 113. At least one wiring of the third wiring layer 115 is electrically connected to at least one wiring of the second wiring layer 112 through a second via 114 formed in the second wiring insulating layer 113. Yes.
- the wiring layer includes wiring such as signal wiring, power supply wiring, and ground wiring.
- one or more other wiring layers can be provided on the side opposite to the substrate, that is, on the wiring layer side.
- an external connection terminal used for connection to an external substrate or the like can be provided on the outermost layer.
- a BGA ball is disposed on the external connection terminal and is connected to an external substrate such as a motherboard.
- the external connection terminal may be configured such that the wiring layer is opened in the solder resist. Further, the surface of the external connection terminal can be protected so that, for example, solder does not flow.
- the first wiring layer 109 and the second electrode terminal 104 are electrically connected using the element via 108.
- the present invention is not limited to this, and the element via is not limited thereto.
- a metal post provided on the electrode terminal can also be used.
- the metal via provided on the electrode terminal can be used instead of the wiring via 103.
- the heat dissipation layer 105 is formed on the first semiconductor element 101 serving as the substrate, and the second semiconductor element 102 is disposed on the heat dissipation layer 105.
- the first semiconductor element is a peripheral type in which electrode terminals are provided on the outer periphery of the surface.
- the heat dissipation layer 105 is disposed over at least the entire surface (back surface) opposite to the circuit surface of the second semiconductor element, and further expands on the first semiconductor element and outside the second semiconductor element. is doing. Further, the heat dissipation layer 105 is formed inside the plurality of first electrode terminals 103.
- the heat dissipation material used for the heat dissipation layer is not particularly limited as long as it has a higher thermal conductivity than the semiconductor element.
- the semiconductor element for example, silicon (Si), germanium (Ge), gallium arsenide (GaAs), gallium arsenide phosphorus (GaAsP), gallium nitride (GaN), silicon carbide (SiC), zinc oxide (ZnO), or the like is used. be able to.
- silicon is most often used as a semiconductor element, and in this case, a heat dissipation material having a higher thermal conductivity than silicon is used.
- the thermal conductivity of silicon is approximately 170 W / m ⁇ K
- a material having a thermal conductivity higher than 170 W / m ⁇ K can be preferably used as the heat dissipation material.
- the heat dissipation material include a metal material, a carbon material, or a resin material.
- Metal materials include metals, metal oxides, metal nitrides, metal carbides or alloys thereof, such as gold, silver, copper, aluminum, iron, platinum, titanium, aluminum oxide, aluminum nitride, titanium carbide, etc.
- the carbon material include diamond, graphite, and garbon nanotubes.
- the resin material include silicone resins and epoxy resins. Moreover, these may be mixed and used, for example, the mixed material of metal materials, such as metal powder, metal flakes, metal fiber, a metal filler, and a resin material can be used.
- the heat dissipation layer is not particularly limited, for example, after disposing the heat dissipation material using a sputtering method, a vacuum evaporation method, a plating method, or the like, it can be formed into a predetermined shape by a photolithography method.
- the heat dissipation layer is disposed between the first semiconductor element and the second semiconductor element, and extends on the first semiconductor element and outside the second semiconductor element. Moreover, it is preferable that the heat dissipation layer is disposed over at least the entire back surface of the second semiconductor element. Further, as shown in FIGS. 3 and 4, the heat dissipation layer can be formed such that a part of the heat dissipation layer is exposed to the outside. By exposing a part of the heat dissipation layer to the outside, heat can be efficiently radiated to the outside. 3 and 4, a dotted line 102 'indicates a position where the second semiconductor element is disposed. The position of the electrode terminal of the first semiconductor element can be arbitrarily changed by the rewiring layer.
- the heat dissipation layer is formed in a non-contact manner with the first electrode terminal and the wiring via.
- the first electrode terminal and the heat dissipation layer may be in contact with each other.
- the insulating material that can be used as the heat dissipation layer include aluminum nitride, titanium carbide, and aluminum oxide. It is preferable to form the heat dissipation layer using an insulating material because a problem does not occur even if it contacts the first electrode terminal or the wiring via, and the tolerance of design error is improved.
- the first electrode terminal 103 and the heat dissipation layer 105 are preferably formed in a non-contact manner.
- the heat dissipation layer is formed in contact with the first electrode terminal and over the entire surface of the first semiconductor element, and the end of the heat dissipation layer is exposed on the side surface of the built-in substrate. Yes.
- heat accumulated between the first semiconductor element and the second semiconductor element can be more effectively diffused to another region and radiated to the outside.
- the first electrode terminal and the heat dissipation layer may be formed in contact with each other as shown in FIG.
- Examples of semiconductor elements include transistors, ICs, and LSIs.
- CMOS Complementary Metal Oxide Semiconductor
- LSI Low-Integrated Circuit
- the first semiconductor element 101 it is preferable to use a peripheral type in which electrode terminals are provided outside the surface in order to place the second semiconductor element 102 in the center.
- the present invention is particularly limited to this. It is not a thing.
- the first semiconductor element 101 is a peripheral type in which electrode terminals are provided outside the surface.
- the present invention is not particularly limited to this, and the first electrode terminals 103 are not limited thereto.
- the first semiconductor element can include a rewiring layer on the circuit surface side.
- the rewiring layer is used to form the electrode terminal.
- the position can be changed.
- a method for forming the rewiring layer is disclosed in, for example, Japanese Patent Application Laid-Open No. 2006-32600 or Japanese Patent Application Laid-Open No. 2009-194022.
- it can be formed of a plurality of layers on a circuit surface of a semiconductor element by using a photolithography method.
- the first semiconductor element 101 also functions as a substrate.
- a metal plate such as copper has been used as a substrate of a semiconductor-embedded substrate.
- high integration and high functionality can be achieved by using a semiconductor element having a function as a substrate.
- the thickness of the first semiconductor element can be, for example, 50 to 1000 ⁇ m, and preferably 200 to 500 ⁇ m.
- the thickness of the second semiconductor element can be, for example, 50 to 500 ⁇ m, and preferably 50 to 100 ⁇ m.
- the first semiconductor element is constituted by a memory and the second semiconductor element is constituted by a logic.
- the first semiconductor element arranged on the lower side is constituted by a memory having a relatively small pad pitch and a relatively small number of pads
- the second semiconductor element arranged on the upper side has a relatively small pad pitch.
- a logic that is narrow and has a relatively large number of pads.
- logic generates a large amount of heat, and memory tends to be vulnerable to heat. Therefore, when the first semiconductor element is configured by a memory and the second semiconductor element is configured by logic, between the semiconductor elements. The heat generated by the logic is accumulated, and the memory element in that portion is easily damaged. Therefore, as in the present invention, by disposing a heat dissipation layer between the first semiconductor element constituted by the memory and the second semiconductor element constituted by the logic, it can be effectively diffused to other regions. And destruction of the memory element can be prevented.
- an adhesive layer may be provided between the second semiconductor element 102 and the heat dissipation layer 105.
- an adhesive agent used for a contact bonding layer For example, an epoxy resin, an epoxy acrylate resin, a urethane acrylate resin, a polyester resin, a phenol resin, a polyimide resin etc. can be used.
- an adhesive having good thermal conductivity for example, a silver paste can be used. From the viewpoint of thermal conductivity, the adhesive layer is preferably as thin as possible.
- the material for the insulating layer can be used without particular limitation as long as it is an insulating material.
- an insulator used for a normal wiring board can be used.
- the material for the insulating layer include an epoxy resin, an epoxy acrylate resin, a urethane acrylate resin, a polyester resin, a phenol resin, a polyimide resin, and a polynorbornene resin.
- other examples include BCB (Benzocyclobutene), PBO (Polybenzoxazole), and the like.
- polyimide resin and PBO are excellent in mechanical properties such as film strength, tensile elastic modulus, elongation at break, and the like, so that high reliability can be obtained.
- the material of the insulating layer may be either photosensitive or non-photosensitive.
- the insulating layer may be formed of a plurality of layers, but in this case, it is preferable to use the same material.
- the insulating layer 106 may be composed of a plurality of layers as described above.
- the insulating layer 106 is formed in a core layer having an opening for arranging the second semiconductor element and an opening in which the second semiconductor element is arranged. You may comprise from the filling resin with which it filled.
- the same material as that of the insulating layer can be used.
- the conductor used for the wiring layer and via is not particularly limited.
- copper, silver, gold, nickel, aluminum, and palladium are examples of copper, silver, gold, nickel, aluminum, and palladium.
- a metal containing at least one selected from the group consisting of or an alloy containing these as a main component can be used.
- Cu is preferably used as the conductor from the viewpoint of electrical resistance and cost.
- the via material is not particularly limited as long as it has conductivity, but other than the above, for example, a conductive material including a solder material, a thermosetting resin, and a conductive metal powder such as copper or silver.
- Resin paste can be used.
- the conductive resin paste is preferably a paste material containing nanoparticles as conductive particles.
- the conductive resin paste is more preferably a material in which the resin component volatilizes or a material in which the resin component sublimes when heated to approach the sintered body.
- the via is provided by a stable and rigid vapor deposition method, sputtering method, CVD (Chemical Vapor Deposition) method, ALD (Atomic Layer Deposition) method, electroless plating method, electrolytic plating method or the like.
- the manufacturing method include a method of providing a power supply layer by an evaporation method, a sputtering method, a CVD method, an ALD method, an electroless plating method, etc., and then setting a desired film thickness by an electrolytic plating method or an electroless plating method.
- the via opening diameter is preferably about 1 times the via film thickness, but is not limited thereto.
- the aspect ratio of the via height to the via diameter is preferably 0.3 or more, 3 or less, more preferably 0.5 or more and 1.5 or less, and still more preferably around 1.
- One or more second semiconductor elements can be provided on the first semiconductor element. As shown in FIG. 1, one second semiconductor element is preferably provided on the first semiconductor element, but the present invention is not particularly limited to this.
- the external connection terminal can be formed of, for example, at least one metal or alloy selected from the group consisting of gold, silver, copper, tin, and a solder material.
- nickel having a thickness of 3 ⁇ m and gold having a thickness of 0.5 ⁇ m can be sequentially laminated.
- the pitch is, for example, 50 to 1000 ⁇ m, and more preferably 50 to 500 ⁇ m.
- the heat dissipation layer is disposed on the first semiconductor element and in a region where the second semiconductor element is disposed and a region that does not face each functional block of the first semiconductor element. The form which is present will be described.
- a semiconductor element such as an LSI can be composed of various functional blocks such as an interface block, a drive block, an A / D conversion block, a logic circuit block, a CPU block, a memory block, or a compression circuit block.
- the semiconductor element is composed of functional blocks A to E indicated by dotted lines.
- Each functional block can be composed of basic elements.
- Each functional block is arranged at an arbitrary interval, and there is no basic element in the semiconductor element in the region between them. Therefore, if the heat dissipation layer is formed in a region that does not face the functional block, such as between the functional blocks, damage to the basic element can be suppressed.
- the first semiconductor element and the second semiconductor element can be formed in a region where the second semiconductor element is arranged and a region not facing each functional block of the first semiconductor element, the first semiconductor element and the second semiconductor element The heat accumulated between them can be diffused to other regions while suppressing damage to the basic element.
- the region where the second semiconductor element is disposed can be made slightly larger than the area on the back surface side of the second semiconductor element in consideration of the placement error.
- the shape of the heat dissipation layer shown in FIG. 7 will be described more specifically.
- the heat dissipation layer includes a heat dissipation plane 115a on which the second semiconductor element is disposed, and a heat dissipation path 115b extending from the heat dissipation plane.
- the path is disposed between the functional blocks of the first semiconductor element.
- the heat radiation path extending from the heat radiation plane is exposed on the side surface of the built-in substrate.
- the shape of the heat radiation plane in which the second semiconductor element is disposed is preferably the same shape as the back surface shape of the second semiconductor element, and in consideration of the placement error, the shape of the back surface side of the second semiconductor element is It is preferable that it is slightly larger than the area. For example, FIG.
- FIG. 6 is a vertical sectional view of the semiconductor-embedded substrate taken along the dotted line X in FIG. 7B.
- the thickness can be 50 to 200 ⁇ m.
- the functional blocks are arranged with an interval of 1 to 10 ⁇ m, for example.
- FIG. 8 shows a specific layout of functional blocks and heat dissipation layers.
- reference numeral 200 denotes a first semiconductor element.
- 201 is a CPU block.
- Reference numeral 202 denotes a ROM block.
- Reference numeral 203 denotes a first logic circuit block.
- Reference numeral 204 denotes a second logic circuit block.
- Reference numeral 205 denotes a RAM block.
- Reference numeral 206 denotes a third logic circuit block.
- Reference numeral 207 denotes a wiring.
- reference numeral 102 'denotes the arrangement position of the second semiconductor element, and the second semiconductor element is arranged at the center of the first semiconductor element.
- the heat dissipation layer 105 is formed in a region where the second semiconductor element is disposed and a region that does not face each functional block of the first semiconductor element. Moreover, the edge part of the thermal radiation layer 105 is exposed to all the side surfaces of a built-in board
- FIG. 9 is a schematic sectional view of the present embodiment.
- FIG. 10 is a horizontal cross-sectional view taken along the dotted line Y in FIG.
- a heat dissipation via 116 whose upper and lower surfaces are in contact with the heat dissipation layer 105 and the first wiring layer 109 is formed in the insulating layer 106.
- the heat dissipation via 116 functions as a path for radiating the heat of the heat dissipation layer 105 to the surface side of the built-in substrate.
- the heat dissipation via 116 is preferably not connected to the wiring via 107 via a wiring in order to prevent heat conduction to the first electrode terminal 103.
- the heat dissipation wiring in the wiring layer connected to the heat dissipation via 116 is preferably not electrically connected to the heat dissipation via.
- it is preferable that the heat dissipation via 116 is not connected to the wiring via 107 via a wiring in order to prevent heat conduction to the second electrode terminal 104.
- the heat dissipation wiring in the wiring layer connected to the heat dissipation via 116 can be connected to at least one of the external connection terminals on the outermost layer.
- a BGA ball is disposed on the external connection terminal, and heat can be efficiently radiated to the motherboard via the BGA ball.
- the same heat dissipation material as that described above and the conductor used for the via can be used.
- the heat radiating via 1 is formed using the same conductor as that used for the via, it can be formed by a plating method simultaneously with the wiring via. In this case, the opening is filled with a metal conductor, so-called filled via.
- FIG. 11 is a schematic cross-sectional view for explaining the present embodiment.
- FIG. 12 shows a heat dissipation layer 105 disposed on the second semiconductor element 101 and a heat dissipation path 118 on the heat dissipation layer 105 inside. It is a top view of a state where an adhesive layer 117 is disposed. As shown in FIG. 11, the heat dissipation passage 118 is provided inside so as to penetrate the adhesive layer 117.
- the heat dissipation passage 118 has an upper end in contact with the second semiconductor element 102 and a lower end in contact with the heat dissipation layer 105. With such a structure, heat generated in the second semiconductor element 102 can be efficiently radiated by the heat radiation layer 105.
- the heat dissipation passage can be formed, for example, by forming an opening in the adhesive layer and filling the opening with the heat dissipation material.
- the heat dissipation passage may be provided after the adhesive layer is formed on the heat dissipation layer, or may be provided in advance in the adhesive layer itself.
- the shape of the heat dissipation passage is not particularly limited, and for example, the horizontal cross section may be a polygonal shape such as a circle or a rectangle. Further, the diameter of the heat dissipation passage is not particularly limited, but can be, for example, about 5 to 300 ⁇ m.
- the shape of the plurality of heat radiation passages is not limited to the same shape, and a plurality of heat radiation passages having different shapes may be mixed.
- FIG. 13 is a schematic cross-sectional view for explaining this embodiment, and a second heat radiation path 119 is formed inside the second semiconductor element 102.
- the second heat radiation path 119 is made of a material having higher thermal conductivity than the material of the second semiconductor element.
- the second heat radiation path 119 has a lower end located on a surface opposite to the circuit surface of the second semiconductor element 102.
- the second heat radiation path 119 is formed so as not to penetrate the second semiconductor element.
- the second heat radiation path is not particularly limited.
- the second heat radiation path is formed by forming an opening by a D-RIE (Deep-Reactive Ion Etching) method or a laser method, and disposing the above heat radiation material in the opening. can do.
- the method for disposing the heat dissipation material in the opening include a metal melting method, an electrolytic plating method, an electroless plating method, a sputtering method, and a vapor deposition method.
- the position where the second heat radiation path is provided is not particularly limited, but the end located on the circuit surface side (the upper end in FIG. 11) is provided near a hot spot where power consumption is concentrated in the second semiconductor element. Is preferred. Examples of such hot spots include a logic circuit block and a CPU block. Therefore, it is preferable that the terminal located on the circuit surface side in the second heat radiation path is located below the logic circuit block or CPU block of the second semiconductor element.
- the second heat radiation path can be arranged in consideration of the arrangement of the electronic circuit of the second semiconductor element.
- a plurality of the second heat radiation paths can be formed in the second semiconductor element in a point symmetry or a line symmetry, for example, in plan view.
- the shape of the second heat radiation path is not particularly limited.
- the horizontal cross section may be a polygonal shape such as a circle or a rectangle.
- the diameter of the second heat radiation path is not particularly limited, but may be, for example, about 5 to 50 ⁇ m.
- the second heat radiation path may be formed in advance on the substrate of the semiconductor element, or may be formed after the semiconductor element is formed.
- a plurality of second heat radiation paths can be formed in the second semiconductor element, but the shape of the plurality of second heat radiation paths is not limited to the same, and a plurality of second heat radiation paths having different shapes are used.
- the heat dissipation paths may be mixed.
- the heat dissipation path 118 and the second heat dissipation path 119 are in contact with each other as shown in FIG. Each is preferably formed. That is, the heat dissipation passage 118 is preferably formed so as to penetrate through the adhesive layer 117 and be in contact with the second heat dissipation path 119 and the heat dissipation layer 105.
- FIG. 15 is a schematic cross-sectional view for explaining the present embodiment, in which a first heat radiation path 120 is formed inside the first semiconductor element 101.
- the first heat radiation path 120 is made of a material having higher thermal conductivity than the material of the first semiconductor element.
- the lower end of the first heat radiation path 120 is located on the surface opposite to the circuit surface of the first semiconductor element 101 and is exposed to the outside.
- the first heat radiation path 120 may be formed so as not to penetrate the first semiconductor element 101 as shown in FIG. Further, as shown in FIG. 15B, the first heat radiation path 120 may be formed so as to penetrate the first semiconductor element 101 and the upper end thereof may be in contact with the heat radiation layer 105. By configuring the first heat dissipation path 120 to be in contact with the heat dissipation layer 105, the heat of the heat dissipation layer 105 can be efficiently radiated to the outside.
- the first heat radiation path can be formed by the same method as the second heat radiation path.
- the position where the first heat radiation path is provided is not particularly limited, but when it is formed so as not to penetrate, the end located on the circuit surface side (the upper end in FIG. 15B) is concentrated in the first semiconductor element. It is preferably provided in the vicinity of the hot spot. Examples of such hot spots include a logic circuit block and a CPU block.
- the first heat radiation path is formed in consideration of the position so as not to destroy the function of the first semiconductor element.
- the first heat radiation path can be provided in a region where the functional block of the first semiconductor element does not exist.
- first heat radiation path can be arranged in consideration of the arrangement of the electronic circuit of the first semiconductor element.
- a plurality of first heat radiation paths can be formed in the second semiconductor element, for example, point-symmetrically or line-symmetrically in plan view.
- the shape of the first heat radiation path is not particularly limited, and for example, the horizontal cross section can be a polygonal shape such as a circle or a rectangle. Further, the diameter of the first heat radiation path is not particularly limited, but can be, for example, about 5 to 50 ⁇ m.
- the first heat radiation path may be formed in advance on the substrate of the semiconductor element, or may be formed after the semiconductor element is formed.
- a plurality of first heat radiation paths can be formed in the first semiconductor element, but the shape of the plurality of first heat radiation paths is not limited to the same one, and the plurality of first heat radiation paths having different shapes are used.
- the heat dissipation paths may be mixed.
- a heat sink is provided on the back surface of the first semiconductor element so that the first heat dissipation path and the heat sink are in contact with each other, whereby heat can be efficiently radiated from the outside through the first heat dissipation path. Can do.
- FIG. 7 is cross-sectional process diagrams for explaining a method for manufacturing the semiconductor-embedded substrate of the embodiment shown in FIG.
- a first semiconductor element 101 having a first electrode terminal 103 is prepared.
- the first semiconductor element 101 can be formed by a semiconductor process, and the form of the first semiconductor element 101 is desirably a wafer shape for high yield manufacturing.
- a heat dissipation layer 105 made of a heat dissipation material is formed on the circuit surface side of the first semiconductor element 101.
- the method for forming the heat dissipation layer can be selected in consideration of the heat dissipation material.
- electrolytic plating electroless plating
- transfer molding method compression molding method
- printing method vacuum press
- vacuum lamination spin coating method
- spin coating method A die coating method, a curtain coating method, or the like can be used.
- the second semiconductor element 102 having the second electrode terminal 104 is mounted on the heat dissipation layer 105 with the second electrode terminal 104 facing upward.
- the second semiconductor element 102 may be mounted on the heat dissipation layer using an adhesive layer.
- an insulating layer 106 is formed so as to contain the second semiconductor element 102.
- a wiring via 107 connected to the first electrode terminal 103 and an element via 108 connected to the second electrode terminal 104 are formed in the insulating layer 106.
- a transfer molding method for example, a transfer molding method, a compression molding method, a printing method, a vacuum press, a vacuum lamination, a spin coating method, a die coating method, a curtain coating method, or the like can be used.
- the opening of the wiring via 107 can be formed by using a photolithography method, for example, when the insulating layer 106 is made of a photosensitive material.
- the via opening should be formed by a laser processing method, a dry etching method, or a blast method.
- electrolytic plating, electroless plating, a printing method, a molten metal suction method, or the like can be used as a method for filling a via opening with a conductor.
- the element via 108 and the wiring via 107 are each formed by providing a metal post on the first electrode terminal 103 and the second electrode terminal 104 before forming the insulating layer 106, and laminating the insulating layer 106. Later, the surface of the insulating layer 106 may be shaved to expose the respective metal posts. Examples of the grinding method include buffing and CMP.
- wiring layers such as the first wiring layer 109, the second wiring layer 112, and the third wiring layer 115 are formed.
- the wiring layer can be formed using a metal such as Cu, Ni, Sn, or Au, for example, by a subtractive method, a semi-additive method, a full additive method, or the like.
- the subtractive method is disclosed, for example, in JP-A-10-51105.
- the subtractive method is a method of obtaining a desired wiring pattern by using a resist in which a copper foil provided on a substrate or a resin is formed in a desired pattern as an etching mask and removing the resist after the etching.
- the semi-additive method is disclosed in, for example, JP-A-9-64493.
- the semi-additive method is a method in which a power supply layer is formed, a resist is formed in a desired pattern, electrolytic plating is deposited in the resist opening, and the power supply layer is etched after removing the resist to obtain a desired wiring pattern. It is.
- the power feeding layer can be formed by, for example, electroless plating, sputtering, CVD, or the like.
- the full additive method is disclosed, for example, in JP-A-6-334334. In the full additive method, first, an electroless plating catalyst is adsorbed on the surface of a substrate or resin, and then a pattern is formed with a resist. Then, the catalyst is activated while leaving the resist as an insulating layer, and a metal is deposited in the opening of the insulating layer by an electroless plating method to obtain a desired wiring pattern.
- a transfer molding method As a method for forming the wiring insulating layer, a transfer molding method, a compression molding method, a printing method, a vacuum press, a vacuum lamination, a spin coating method, a die coating method, a curtain coating method, or the like can be used.
- an external connection terminal can be provided on the outermost layer.
- the external connection terminal may also serve as a signal wiring or a ground wiring.
- the external connection terminal can be formed by etching the solder resist so that a part of the signal wiring or the ground wiring is exposed.
Abstract
Description
基板としての第1の半導体素子と、
該第1の半導体素子の回路面側に回路面を同一方向に向けて配置された第2の半導体素子と、
該第2の半導体素子を内蔵する絶縁層と、
を含み、
少なくとも前記第1と半導体素子と前記第2の半導体素子との間に放熱層が配置されており、
該放熱層は前記第1の半導体素子上であって前記第2の半導体素子の外側に展開していることを特徴とする半導体内蔵基板である。
図1は、本実施形態の半導体内蔵基板について説明するための概略断面図である。
本実施形態では、放熱層が、第1の半導体素子の上であって、第2の半導体素子が配置される領域と、第1の半導体素子の各機能ブロックに面しない領域と、に配置されている形態について説明する。
本実施形態では、第1の配線層及び放熱層に接する放熱用ビアを絶縁層中に有する形態について説明する。
本実施形態では、放熱層と第2の半導体素子の間に配置した接着層中に放熱用通路を形成した形態について説明する。
本実施形態では、第2の半導体素子中に放熱用パスを有する形態について説明する。
本実施形態では、第1の半導体素子中に放熱用パスを有する形態について説明する。
図16(a)から(e)は、図1に示した実施形態の半導体内蔵基板の製造方法を説明するための断面工程図である。
102 第2の半導体素子
103 第1の電極端子
104 第2の電極端子
105 放熱層
115a 放熱プレーン
115b 放熱経路
106 絶縁層
107 配線用ビア
108 素子用ビア
109 第1の配線層
110 第1の配線絶縁層
111 第1の配線ビア
112 第2の配線層
113 第2の配線絶縁層
114 第2の配線ビア
115 第3の配線層
116 放熱用ビア
117 接着層
118 放熱用通路
119 第2の放熱用パス
120 第1の放熱用パス
Claims (19)
- 基板としての第1の半導体素子と、
該第1の半導体素子の回路面側に回路面を同一方向に向けて配置された第2の半導体素子と、
該第2の半導体素子を内蔵する絶縁層と、
を含み、
少なくとも前記第1と半導体素子と前記第2の半導体素子との間に放熱層が配置されており、
該放熱層は前記第1の半導体素子上であって前記第2の半導体素子の外側に展開していることを特徴とする半導体内蔵基板。 - 前記放熱層は少なくとも前記第2の半導体素子の回路面と反対側の面全体に亘って配置されている請求項1に記載の半導体内蔵基板。
- 前記放熱層の少なくとも一部は外部に露出している請求項1又は2に記載の半導体内蔵基板。
- 前記放熱層は、前記第2の半導体素子が配置される領域と、前記第1の半導体素子の各機能ブロックに面しない領域と、に配置されている請求項1乃至3のいずれかに記載の半導体内蔵基板。
- 前記放熱層は、前記第2の半導体素子が配置される放熱プレーンと、該放熱プレーンから延展する放熱経路と、を含み、
該放熱経路は、前記第1の半導体素子の各機能ブロックの間に配置されている請求項1乃至4のいずれかに記載の半導体内蔵基板。 - 前記放熱経路の端部は外部に露出している請求項5に記載の半導体内蔵基板。
- 放熱層は、前記第1の半導体素子及び前記第2の半導体素子より熱伝導率が高い材料を用いて形成されている請求項1乃至6のいずれかに記載の半導体内蔵基板。
- さらに、前記絶縁層を間にして前記第1の半導体素子及び前記第2の半導体素子に対向する第1の配線層を有し、
前記第1の配線層の少なくとも1つの配線は前記第2の半導体素子の電極端子と電気的に接続されており、
前記第1の配線層の少なくとも1つの配線は前記第1の半導体素子の電極端子と前記絶縁層中に形成された配線用ビアを介して電気的に接続されている請求項1乃至7のいずれかに記載の半導体内蔵基板。 - さらに、前記絶縁層内に前記第1の配線層及び前記放熱層に接する放熱用ビアを有する請求項8に記載の半導体内蔵基板。
- 前記放熱用ビアは、前記配線用ビアと配線で繋がっていない請求項9に記載の半導体内蔵基板。
- さらに、1層以上の第2の配線層と、最外層の外部接続用端子とを前記第1の配線層側に有し、
前記放熱用ビアと繋がる前記第1の配線層及び前記第2の配線層中の放熱用配線は、前記外部接続用端子の少なくとも1つと接続されている請求項9又は10に記載の半導体内蔵基板。 - 前記第2の半導体素子は、片方の末端が前記第2の半導体素子の回路面と反対側の面に位置し、かつ前記第2の半導体素子の材料より熱伝導性が高い材料からなる第2の放熱用パスを内部に有する請求項1乃至11のいずれかに記載の半導体内蔵基板。
- 前記第2の放熱用パスにおける前記第2の半導体素子の回路面と反対側の面に位置する末端と反対側の末端は、前記第2の半導体素子における論理回路ブロック又はCPUブロックに位置する請求項12に記載の半導体内蔵基板。
- 前記第2の半導体素子と前記放熱層との間に接着層を有する請求項1乃至13のいずれかに記載の半導体内蔵基板。
- 前記接着層は、前記第2の半導体素子と前記放熱層とに接する放熱用通路を含む請求項14に記載の半導体内蔵基板。
- 前記第2の半導体素子と前記放熱層との間に、放熱用通路を含む接着層を有し、
前記放熱用通路は、前記接着層を貫通して形成されており、前記第2の放熱用パスと前記放熱層とに接する請求項12又は13に記載の半導体内蔵基板。 - 前記第1の半導体素子は、片方の末端が前記第1の半導体素子の回路面と反対側の面に位置し、かつ前記第1の半導体素子の材料より熱伝導性が高い材料からなる第1の放熱用パスを内部に有する請求項1乃至16のいずれかに記載の半導体内蔵基板。
- 前記第1の放熱用パスは前記第1の半導体素子を貫通して設けられ、前記第1の半導体素子の回路面と反対側の面に位置する末端と反対側の末端は前記放熱層と接している請求項17に記載の半導体内蔵基板。
- 前記第1の半導体素子の回路面と反対側の面側にヒートシンクが設けられ、前記第1の放熱用パスは前記ヒートシンクに繋がっている請求項17又は18に記載の半導体内蔵基板。
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