WO2011120490A1 - Computersystem und verfahren zum vergleichen von ausgangssignalen - Google Patents
Computersystem und verfahren zum vergleichen von ausgangssignalen Download PDFInfo
- Publication number
- WO2011120490A1 WO2011120490A1 PCT/DE2011/000268 DE2011000268W WO2011120490A1 WO 2011120490 A1 WO2011120490 A1 WO 2011120490A1 DE 2011000268 W DE2011000268 W DE 2011000268W WO 2011120490 A1 WO2011120490 A1 WO 2011120490A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- processor cores
- comparison
- output signals
- output
- cots
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/1629—Error detection by comparing the output of redundant processing systems
- G06F11/1641—Error detection by comparing the output of redundant processing systems where the comparison is not performed by the redundant processing components
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/18—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits
- G06F11/183—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits by voting, the voting not being performed by the redundant components
- G06F11/184—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits by voting, the voting not being performed by the redundant components where the redundant components implement processing functionality
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/18—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits
- G06F11/187—Voting techniques
- G06F11/188—Voting techniques where exact match is not required
Definitions
- the invention relates to a computer system and a method for comparing output signals output by means of at least two COTS processor cores.
- the invention further relates to a computer program.
- test procedures require a particularly intensive examination of the design of the corresponding hardware and the software running thereon.
- test methods are time-consuming and expensive.
- development of appropriate hardware and software is expensive and time consuming.
- the hardware can often only be used for the respective safety-critical computer system.
- the invention includes the idea of providing or creating a computer system that can ensure data integrity through the use of multiple dissimilar processor cores. On the other hand, availability is increased by using multiple processors.
- the invention comprises an arrangement of a computer system with at least two, for example three, COTS processor cores and with an evaluation device connected to the at least two COTS processor cores for evaluating output signals by means of the COTS processor cores, the evaluation means comparing means for pairwise comparing the respective ones
- comparison means having output signals output, wherein the comparison means are further configured to output a comparison signal corresponding to the respective comparison of the output signals.
- NoC network-on-chip
- COTS processor cores For example, a network-on-chip (NoC) is connected to the COTS processor cores.
- a NoC is in particular a
- a system-on-chip (SoC) communication subsystem may be configured to communicate the output signals to external receivers.
- an external receiver may include, for example, a landing flap, a landing gear or a tail of an aircraft or a space shuttle.
- the NoC can be certified according to the RTCA DO-254 test procedure. However, it is not necessary for the NoC to successfully complete such or similar certification process. It is enough if the NoC is certified for the specific application. For example, the NoC may only be for one Memory access, communication, network, routing or pre-processing of data, for example as a filter, or certified for a combination thereof. Such a NoC is cheaper to manufacture and still allows a fail-safe and integrated computer system.
- the NoC may include memory consistency logic.
- a method is furthermore provided for comparing output signals output by means of at least two COTS processor cores, comprising the following steps:
- the step can be:
- a computer program is provided with program code for carrying out the method according to the invention when the computer program is executed on a computer.
- the invention thus encompasses the idea of comparing the output signals of COTS processor cores, which are connected to one another, for example, by means of a system-on-chip (SoC), in pairs, and to determine from these comparisons which output signal is integer.
- SoC system-on-chip
- the output signal corresponds to a result of a calculation performed by means of a COTS processor core.
- integer that the result lies within a certain Fault Tolerance range. Only if this is the case will there be no inadmissible system state changes. The system will have a valid state.
- SoC system-on-chip
- this includes
- NoC network-on-chip
- the NoC is an integral NoC.
- the NoC is with
- An Integral NoC in this context can be defined as a NoC, either after
- the comparison of the output signals may be at least partially performed by means of the COTS processor cores
- Processor core A has calculated the result 1 and processor core B has that
- Result 0 calculated.
- A now compares his result to the result of B and B compares his result to the result of A.
- a and B both determine that the results do not match and give the NoC a corresponding signal or comparison signal.
- the NoC becomes the information from this signal that the two results, 1 and 0, should be discarded since it can not be determined which result is correct.
- a and B come to a different result in the comparison, that is, for example, A determines that the results are not
- a and B will pass corresponding signals or comparison signals to the NoC.
- the NoC detects that at least one of the cores has calculated an incorrect result and rejects both results 1 and 0. In particular, this prevents any further processing of incorrect results.
- the external receiver comprises further comparison means for
- the receiver may for example comprise an actuator, which in particular in one
- Landing flap or integrated in a landing gear or in a tail unit Landing flap or integrated in a landing gear or in a tail unit.
- COTS is an abbreviation known to those skilled in the art and means: “Commercial of the shelf” or “components of the shelf”.
- COTS hardware includes hardware from mass-produced
- COTS processor cores can be, for example, processor cores of known processors of IBM, ARM, Intel, AMD or VIA, as used in particular in known mobile computer systems or personal computers (PC).
- PC personal computers
- AMD Athlon or AMD Phenom processors or processors may be used.
- the above list should not be understood as exhaustive. Rather, all processors can be used, which are also used in the usual embedded computers or personal computer (PC).
- PC personal computer
- These can be embedded processors, desktop processors and / or mobile processors. Since such processors have not usually been manufactured primarily for safety-critical applications, they do not have to pass through the test methods mentioned at the beginning, nor do they exist. But that means in particular that the manufacturing and development costs of such
- COTS processor cores are significantly lower compared to certified processors.
- the COTS processor cores can also be classified as non-certified
- processor cores are called. In particular, not certified according to any of the above test methods and development methods.
- COTS processor cores it is nevertheless possible by means of such COTS processor cores to create a computer system which can be used in safety-critical areas, in particular in the aerospace industry.
- COTS processor cores in the following non-limiting example, there should be three COTS processor cores, A, B and C, an evaluation device which has comparison means for pairwise comparing the respective output signals.
- the output of the COTS processor core A is compared with the output of the COTS processor core B. Further, the output of the COTS processor core B is compared with the output of the COTS processor core C and output of the COTS processor core C with the output of the COTS processor core A.
- the comparison means are used in the case of Compare this capture and output corresponding comparison signals.
- the comparison signals comprise, in particular, the information that the respective cores have output the same output signals, that is to say calculate the same result.
- the COTS processor core A calculates a different result than the COTS processor cores B and C
- the COTS processor core A will output a different output signal than the COTS processor cores B and C.
- the comparison means will compare the output signals from core A and core B and comparing the outputs of core A and C detect that the respective output signals are not equal and a corresponding one
- the comparison means will detect that the output signals of core B and core C are equal and output a corresponding comparison signal.
- the comparison signals comprise in particular the information that the cores B and C have output the same output signal, ie calculated the same result, and that the core A has outputting a different output signal compared to the cores B and C, ie a calculated another result. In this way, it is detected that two of the COTS processor cores, B and C, have calculated a different result than the third COTS processor core, A.
- COTS processor cores are provided.
- the COTS processor cores are comprised by a processor, in particular the COTS processor cores are integrated in the processor.
- the COTS processor cores may also each be comprised by a single processor, in particular integrated therein.
- the processor comprising the two COTS processor cores can also be broadly referred to as a multi-core processor.
- a plurality of multi-core processors can be provided.
- IC Computer system of an integrated circuit
- IC integrated circuit
- the individual electronic components in particular the COTS processor cores and / or the evaluation device, but also further electronic components, in particular further logic circuits, on a substrate,
- a semiconductor substrate is arranged and / or integrated, thereby enabling a particularly miniaturized and cost-effective design,
- SoC system-on-a-chip
- the COTS processor cores are physically connected to the comparison means. This means that the COTS processor cores with the comparison means each by means of a
- Output signals can be transmitted without a large time delay to the comparison means.
- a large time delay to the comparison means.
- Switching means may be provided, which is connected between one or more COTS processor cores and the comparison means, wherein the
- Switching device receives the output signals and then to the
- the switching device can be configured such that it transmits the output signals to the comparison means depending on a load condition of the comparison means. So can be avoided in an advantageous manner that already busy comparison means not yet further comparison calculations are charged, which can cause a significant time delay.
- the switch may be a bus, a routing device and / or a storage coherence device configured to ensure coherence in memories, such as RAM or caches, associated with the COTS processor cores.
- the switching device may also be referred to as a "network on a chip.”
- the NoC may also be comprised of an integrated circuit
- the NoC is certifiable for a safety-critical application, in particular according to one of the test methods mentioned at the outset, for example a verification method in accordance with DO-254 and / or DO-178b.
- a selection device connected to the comparison means is formed, which is configured in such a way, depending on the comparison signals
- the selection device comprises a logical OR circuit.
- the comparison means comprise logical AND circuits.
- the selection device is comprised by the COTS processor cores, in particular the selection device can be integrated in the COTS processor cores.
- the selection device and the evaluation device are integrated in a logic circuit device.
- the logic circuit device can be certified according to one of the test methods mentioned above, in particular by a method according to DO-254 and / or DO-178b test method.
- the selection device and / or the evaluation device can also be certifiable according to one of these test methods.
- a still fail-safe computer system is created in an advantageous manner, which is suitable for safety-critical applications, in particular in the aerospace industry.
- the three COTS processor cores are each formed as a logical or a physical COTS processor core. In another preferred embodiment of the invention, it may be provided that at least one of the three COTS processor cores is different from the other two COTS processor cores.
- Integrity regarding systematic errors can be achieved.
- a processor core may have a serial failure that causes the processor core to give erroneous results in certain calculations. This circumstance, however, is due to the processor cores different from this processor core
- one COTS processor core may be manufactured by AMD while the other two COTS processor cores are manufactured by Intel.
- the processor cores differ in their clock frequency and / or in their cache memory.
- processor cores with a lower clock frequency and / or with less cache memory than other processor cores can be used for less compute-intensive tasks, for example, for a signature calculation and / or a signature analysis.
- the additional processor cores with the higher clock frequency and / or with the larger cache memory can be used in particular for compute-intensive tasks.
- costs can advantageously be saved and nevertheless a highly integrated and redundant computer system can be created.
- the comparison signals are connected to a connected to the comparison means
- the selection device selects an output signal for further processing depending on the transmitted comparison signals.
- two output signals are classified as equal if respective parameters of the output signals lie within a predetermined error tolerance range.
- Such parameters may be, for example, digitized results of certain arithmetic operations whose deviation is within certain limits.
- the computer program is stored in a firmware of the evaluation device.
- the firmware may be stored in a rewritable memory,
- FIG. 1 shows a computer system according to the invention
- 2 shows the computer system according to the invention from FIG. 1 with a NoC
- FIG. 1 shows a computer system according to the invention
- 2 shows the computer system according to the invention from FIG. 1 with a NoC
- FIG. 1 shows a computer system according to the invention
- 2 shows the computer system according to the invention from FIG. 1 with a NoC
- FIG. 1 shows a computer system according to the invention
- Fig. 3 shows the computer system according to the invention from Fig. 2 with an external
- FIG. 4 shows the computer system according to the invention from FIG. 3, wherein the COTS processor cores have comparison means
- FIG. 5 shows a schematic view of the comparison means of the processor cores from FIG. 4 and FIG
- FIG. 6 shows the computer system according to the invention from FIG. 4 with an external one
- Fig. 1 shows a computer system 101 with three COTS-Prozessorkemen 103, 105 and 107, which are preferably not identical.
- the three COTS processor cores 103, 105 and 107 are integrated in a processor 109.
- the processor 109 is thus a Dreikemreaor.
- the processor 109 is thus a Dreikemreaor.
- Processor 109 may be a four-core, eight-core, or sixteen-core processor.
- the three COTS processor cores 103, 105 and 107 are each integrated in a separate processor.
- the computer system 101 further comprises a logic circuit device 1 1 1, in which an evaluation device 113 is integrated.
- the evaluation device 1 13 comprises three comparison means 15, 117 and 119.
- the comparison means 15 is connected to the COTS processor cores 103 and 107 and receives the respective output signals of the COTS processor cores 103 and 107.
- the comparison means 117 is provided with the COTS Processor core 103 and 105 and receives the respective output signals of the COTS processor cores 103 and 105.
- the Compare means 1 19 is connected to the COTS processor cores 105 and 107 and receives the respective output signals of the COTS processor cores 105 and 107.
- the comparison means 15, 17, and 19 each comprise a logical AND circuit.
- a selector 121 is integrated into the logic circuit device 1 1 1, which is connected to the comparison means 1 15, 1 17 and 1 19.
- the selector 121 comprises a logical OR circuit.
- the comparison means 15 will compare the respective output signals of the COTS processor cores 103 and 107 with each other and output a corresponding comparison signal and transmit them to the selector 121.
- the comparison signal comprises, in particular, the information as to whether respective parameters, for example phase, frequency and / or amplitude, of the output signals are within a predetermined error tolerance range. If the respective parameters are within the predetermined error tolerance range, the respective output signals are classified as equal.
- the comparison means 117 compares the respective output signals of the COTS processor cores 103 and 105.
- the comparison means 1 19 compares the respective output signals of the COTS processor cores 105 and 107. The comparison means 1 17 and 1 19 then enter analogously compare signal corresponding to the respective comparison and transmit it to the selection device 121.
- selector 121 may select one of the three output signals for further processing. If one of the three COTS processor cores 103, 105, and 107 has an output other than the other two COTS processor cores, the selector 121 becomes the other one
- Discard output signal because statistically it is more likely that this other output signal will be based on a wrong calculation than the respective output signals of the two other COTS processor cores which have output an equal output signal.
- the selector 121 will then select an output signal for further processing from the two equally classified output signals.
- Fig. 2 shows the computer system 101 of Fig. 1, wherein in addition a NoC 123 is connected to the three COTS processor cores 103, 105 and 107.
- the NoC 123 may be connected to an external receiver 125.
- the NoC 123 transmits the output signals to the external receiver 125.
- the NoC 123 may transmit the output signal selected by means of the selector 121 to the external receiver 125.
- the NoC 123 is certifiable, for example according to one of the above test methods, whereby it is not necessary that the NoC 123 has successfully passed the entire test procedure, but only test procedures for a specific application.
- Such an application may, in particular, be a memory access, a communication, a routing, a network or a pre-processing of data, for example filters, or a combination thereof.
- the NoC 123 may include a so-called "memory consistency logic", memory consistency logic (not shown)
- the external receiver 125 may include, for example, an actuator (not shown) or be integrated into one such as an actuator or an undercarriage of an aircraft or of a space shuttle, the actuator can then be controlled by means of the selected signal, for example, the flaps are extended, whereby incorrect calculations are discarded by means of the computer system 101, No false signal, in particular a control signal, can be transmitted to the actuator so that the actuator is controlled according to a correct control command. For example, a pilot of an aircraft may command to extend the flaps, according to one
- the three COTS processors 103, 105, and 107 each receive a measured aircraft velocity value and independently calculate a corresponding landing flap position. The respective flaps positions are then compared by means of the logic circuit means 111 and discarded any false landing flap positions. The NoC 123 then transmits a control signal associated with the correct landing flap position to the landing flaps, whereupon these extend or retract into the corresponding position. A false signal is not transmitted so that advantageously operation of the aircraft is particularly safe.
- the computer system 101 of FIG. 3 is shown, wherein the COTS processors 103, 105 and 107 each comprise comparison means 115a, 117a and 119a.
- the comparison means 115a, 117a and 119a are in particular formed so as to compare the output signals at least partially with one another, in particular in pairs.
- Comparative means 115a, 117a and 119a are outsourced, so to speak.
- the computing power of modern COTS processors is advantageously utilized efficiently.
- Comparative agents 117a and 119a are formed analogously.
- the comparison means 115a comprises three logical AND circuits 116a, 116b and 116c.
- Each logic circuit 116a, 116b and 116c will output the result of the pairwise comparison and transmit it to, for example, the NoC 123 and / or the logic circuit device 111.
- the NoC 123 and / or the logic circuit means 111 can then determine from the results of the comparison means 115a and also from the results of the comparison means 117a and 119a, whether the calculations are correct or whether and which
- this further comparison means 127 is arranged to compare the output signals of the COTS processor cores 103, 105 and 107 and / or the signals output from the comparison means 115a, 17a and 119a0 to determine a correct result and false ones Discard results.
- a comparison of the signals from the logic circuit means 111 is thus at least partially outsourced to the receiver 125, so to speak. It can be provided in particular that the further comparison means 127
- the NoC 123 then serves only for communication and for transmitting the output signals to the external receiver 125.
- a plurality of processor cores may be provided.
- too only two processor cores can be provided.
- the calculations of the two processor cores are then compared with each other and only if they match, a corresponding control signal to the external receiver, which may in particular include an actuator, transmitted.
- the external receiver which may in particular include an actuator
- the receiver will then compare the calculations with one another by means of the further comparison means and actuate the actuator only if they match, for example extend the flaps.
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Abstract
Description
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Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
AU2011235381A AU2011235381B2 (en) | 2010-03-30 | 2011-03-16 | Computer system and method for comparing output signals |
EP11717465A EP2553578A1 (de) | 2010-03-30 | 2011-03-16 | Computersystem und verfahren zum vergleichen von ausgangssignalen |
US13/638,438 US9612922B2 (en) | 2010-03-30 | 2011-03-16 | Computer system and method for comparing output signals |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102010013349A DE102010013349B4 (de) | 2010-03-30 | 2010-03-30 | Computersystem und Verfahren zum Vergleichen von Ausgangssignalen |
DE102010013349.3 | 2010-03-30 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2011120490A1 true WO2011120490A1 (de) | 2011-10-06 |
Family
ID=44116175
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/DE2011/000268 WO2011120490A1 (de) | 2010-03-30 | 2011-03-16 | Computersystem und verfahren zum vergleichen von ausgangssignalen |
Country Status (5)
Country | Link |
---|---|
US (1) | US9612922B2 (de) |
EP (1) | EP2553578A1 (de) |
AU (1) | AU2011235381B2 (de) |
DE (1) | DE102010013349B4 (de) |
WO (1) | WO2011120490A1 (de) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP2587378A1 (de) * | 2011-10-27 | 2013-05-01 | Diehl BGT Defence GmbH & Co.KG | Verfahren zum Betrieb einer Steuereinrichtung zum wenigstens teilweise autonomen Betrieb eines Fahrzeugs und Steuereinrichtung zur Durchführung solch eines Verfahrens |
EP2787401A1 (de) * | 2013-04-04 | 2014-10-08 | ABB Technology AG | Verfahren und Vorrichtung zur Steuerung einer physikalischen Einheit in einem Automatisierungssystem |
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DE102012212304A1 (de) * | 2012-07-13 | 2014-01-16 | Siemens Aktiengesellschaft | Anordnung mit einem Mikroprozessorsystem |
US8714494B2 (en) * | 2012-09-10 | 2014-05-06 | Siemens Industry, Inc. | Railway train critical systems having control system redundancy and asymmetric communications capability |
US9233698B2 (en) * | 2012-09-10 | 2016-01-12 | Siemens Industry, Inc. | Railway safety critical systems with task redundancy and asymmetric communications capability |
DE102013202253A1 (de) * | 2013-02-12 | 2014-08-14 | Paravan Gmbh | Schaltung zur Steuerung eines Beschleunigungs-, Brems- und Lenksystems eines Fahrzeugs |
KR101983125B1 (ko) * | 2014-05-08 | 2019-05-28 | 마이크로 모우션, 인코포레이티드 | 페일세이프 계산들을 수행하기 위한 방법 |
DE102015003194A1 (de) | 2015-03-12 | 2016-09-15 | Infineon Technologies Ag | Verfahren und Vorrichtung zum Handhaben von sicherheitskritischen Fehlern |
US9734006B2 (en) * | 2015-09-18 | 2017-08-15 | Nxp Usa, Inc. | System and method for error detection in a critical system |
ES2800321T3 (es) | 2016-01-05 | 2020-12-29 | Univ Carnegie Mellon | Arquitectura de seguridad para vehículos autónomos |
DE102017210156B4 (de) * | 2017-06-19 | 2021-07-22 | Zf Friedrichshafen Ag | Vorrichtung und Verfahren zum Ansteuern eines Fahrzeugmoduls |
JP2020145356A (ja) * | 2019-03-07 | 2020-09-10 | 株式会社東芝 | 集積回路装置 |
JP2021020648A (ja) * | 2019-07-30 | 2021-02-18 | マツダ株式会社 | 車両制御システム |
CN112667450B (zh) * | 2021-01-07 | 2022-05-06 | 浙江大学 | 一种可动态配置的多核处理器容错*** |
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- 2011-03-16 WO PCT/DE2011/000268 patent/WO2011120490A1/de active Application Filing
- 2011-03-16 EP EP11717465A patent/EP2553578A1/de not_active Withdrawn
- 2011-03-16 US US13/638,438 patent/US9612922B2/en active Active
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EP0496506A2 (de) * | 1991-01-25 | 1992-07-29 | Hitachi, Ltd. | Verarbeitungseinheit für einen Rechner und Rechnersystem mit einer solchen Einheit |
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EP2587378A1 (de) * | 2011-10-27 | 2013-05-01 | Diehl BGT Defence GmbH & Co.KG | Verfahren zum Betrieb einer Steuereinrichtung zum wenigstens teilweise autonomen Betrieb eines Fahrzeugs und Steuereinrichtung zur Durchführung solch eines Verfahrens |
EP2787401A1 (de) * | 2013-04-04 | 2014-10-08 | ABB Technology AG | Verfahren und Vorrichtung zur Steuerung einer physikalischen Einheit in einem Automatisierungssystem |
WO2014161660A1 (en) * | 2013-04-04 | 2014-10-09 | Abb Technology Ag | Method and apparatus for controlling a physical unit in an automation system |
US10114356B2 (en) | 2013-04-04 | 2018-10-30 | Abb Schweiz Ag | Method and apparatus for controlling a physical unit in an automation system |
Also Published As
Publication number | Publication date |
---|---|
US9612922B2 (en) | 2017-04-04 |
AU2011235381A1 (en) | 2012-09-27 |
DE102010013349A1 (de) | 2011-10-06 |
AU2011235381B2 (en) | 2016-01-14 |
EP2553578A1 (de) | 2013-02-06 |
DE102010013349B4 (de) | 2013-06-13 |
US20130060526A1 (en) | 2013-03-07 |
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