WO2011118512A1 - Insulated gate bipolar transistor - Google Patents

Insulated gate bipolar transistor Download PDF

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Publication number
WO2011118512A1
WO2011118512A1 PCT/JP2011/056503 JP2011056503W WO2011118512A1 WO 2011118512 A1 WO2011118512 A1 WO 2011118512A1 JP 2011056503 W JP2011056503 W JP 2011056503W WO 2011118512 A1 WO2011118512 A1 WO 2011118512A1
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Prior art keywords
gate
region
trench
gate electrode
insulating film
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PCT/JP2011/056503
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French (fr)
Japanese (ja)
Inventor
秀司 米田
慎 及川
憲治 澤村
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オンセミコンダクター・トレーディング・リミテッド
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Publication of WO2011118512A1 publication Critical patent/WO2011118512A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT

Definitions

  • the present invention relates to an insulated gate bipolar transistor, and more particularly to an insulated gate bipolar transistor having an enhanced hole accumulation effect.
  • IGBTs Insulated gate bipolar transistors
  • the IGBT is roughly classified into a PT (Punch Through) structure and an NPT (Non Punch Through) structure.
  • PT Plasma-Gate Bipolar Transistors
  • NPT Non Punch Through
  • the drift layer needs to have a thickness corresponding to it. If it does so, the cost by the epitaxial growth of a drift layer will increase.
  • the drift layer is formed by polishing an FZ (Float Zoning) wafer.
  • the collector layer is formed by injecting p + type impurities into the drift layer with a low dose. For this reason, the amount of holes injected from the collector layer into the drift layer is several orders of magnitude lower in the NPT structure than in the PT structure. In this case, the amount of holes discharged from the emitter electrode cannot be ignored.
  • attempts have been made in the past to suppress the discharge of holes.
  • the emitter region and the emitter electrode are connected in the first region between adjacent trenches to make the region a main cell, while the second region that is between adjacent trenches and is different from the first region.
  • a configuration is disclosed in which an interlayer insulating film is formed between the emitter region and the emitter electrode to make the region a dummy cell. Holes are injected into the base layer from the collector side when the IGBT is on. However, since the area of the main cell is reduced by such a configuration, holes are not easily discharged to the emitter side through the main cell. .
  • the present invention has been made in view of such a problem, and includes a one-conductivity-type semiconductor layer serving as a collector region, a reverse-conductivity-type semiconductor layer provided on the one-conductivity-type semiconductor layer, and a surface provided on the surface of the reverse-conductivity-type semiconductor layer.
  • a plurality of trenches extending in the first direction on the surface, a gate electrode provided in the trench via an insulating film, and provided on the surface of the reverse conductivity type semiconductor layer between the adjacent trenches;
  • One conductivity type base region separated from each other by the opposite conductivity type semiconductor layer in the direction, and an opposite conductivity type emitter region provided adjacent to the trench on the surface of the base region, adjacent in the first direction
  • Another insulating film provided on the opposite conductivity type semiconductor layer between the base regions and overlapping an end portion of the both base regions, and another gate electrode provided on the other insulating film.
  • the present invention relates to an NPT-structure IGBT having a stripe-shaped trench cell, in which a base region serving as a hole outflow path is provided separately in the extending direction of the trench, and an emitter electrode is formed on the surface of the drift layer where the base region is not disposed. Is provided to limit the path through which holes injected into the drift layer flow when the transistor is turned on, thereby enhancing the hole accumulation effect. Further, a planar structure transistor is disposed on the surface of the drift layer where the base region is not disposed to increase the number of electron supply sources, thereby suppressing the decrease in current density while enhancing the hole accumulation effect.
  • the following effects can be obtained.
  • a base region adjacent to a trench (trench gate) extending in a stripe shape is provided separately in the extending direction of the trench, and the emitter electrode and the drift layer are insulated from the surface of the drift layer between the two separated base regions.
  • An insulating film is provided.
  • the effect of accumulating holes can be enhanced by separating the base region.
  • insulation that insulates the electrode and the drift layer from the surface of the drift layer between regions where both base regions are not disposed.
  • a film is provided, and the base region where holes are separated from each other is limited to be drawn out as a path. Thereby, the hole accumulation effect in the drift layer can be enhanced, and the saturation voltage can be reduced.
  • the channel (inversion layer) length when the transistor is on can be increased, and the number of electron supply sources can be increased.
  • Separation between the base regions in the trench type cell results in separation of the interval between the cells, and the cell density of the transistor is reduced.
  • a significant reduction in cell density can be suppressed by arranging other cells of the planar structure at locations apart from the base region. Thereby, it is possible to reduce channel resistance and suppress a decrease in current density while enhancing the hole accumulation effect.
  • the trench (trench gate) is separated into a plurality of portions in the direction in which the trench extends and is provided only in the region where the base region is disposed, so that the trench (trench gate) extends in a stripe shape to the edge of the substrate.
  • an increase in gate capacitance in a region where both base regions are not disposed can be suppressed.
  • FIG. 1A is a plan view and FIG. 1B is a perspective sectional view for explaining an insulated gate bipolar transistor according to a first embodiment of the present invention.
  • FIG. 2 is a cross-sectional view illustrating the insulated gate bipolar transistor according to the first embodiment of the present invention.
  • FIG. 3 is a sectional view for explaining an insulated gate bipolar transistor according to the first embodiment of the present invention.
  • FIG. 4 is a cross-sectional view illustrating the insulated gate bipolar transistor according to the first embodiment of the present invention.
  • FIG. 5 is a cross-sectional view illustrating an insulated gate bipolar transistor according to the first embodiment of the present invention.
  • 6A is a plan view and FIG.
  • FIG. 6B is a perspective sectional view for explaining an insulated gate bipolar transistor according to a second embodiment of the present invention.
  • FIG. 7 is a cross-sectional view illustrating an insulated gate bipolar transistor according to the second embodiment of the present invention.
  • FIG. 8 is a cross-sectional view illustrating an insulated gate bipolar transistor according to the second embodiment of the present invention.
  • FIG. 9 is a cross-sectional view illustrating an insulated gate bipolar transistor according to the third embodiment of the present invention.
  • FIG. 1 is a diagram showing the IGBT 10A
  • FIG. 1A is a plan view of the main surface (front surface) side of the substrate of the IGBT 10A
  • FIG. 1B shows a part of the first region r1 in FIG. It is a perspective sectional view.
  • IGBT 10 ⁇ / b> A includes one-conductivity-type semiconductor layer 1, reverse-conductivity-type semiconductor layer 2, trench 31, insulating film 41, gate electrode 51, base region 21, emitter region 61, Another insulating film 42 and another gate electrode 52 are provided.
  • the substrate is formed by laminating an n ⁇ type semiconductor layer 2 on a high concentration p type (p ++ type) semiconductor layer 1 serving as a collector layer.
  • the n ⁇ type semiconductor layer 2 becomes a drift layer of the IGBT 10A (FIG. 1B).
  • the IGBT 10A of the present embodiment has an NPT structure, and the p ++ type semiconductor layer 1 is formed on an n ⁇ type FZ wafer (silicon wafer) by ion implantation of p ++ type impurities.
  • FIG. 1A shows a configuration in which the second region r2 is provided on the surface of the drift layer (n ⁇ type semiconductor layer) 2 and another gate electrode provided in the third region r3 on the surface of the drift layer 2. 52 patterns are shown superimposed. Further, the pattern of the interlayer insulating film 3 on the other gate electrode 52 is shown in the fourth region r4, and the other gate electrode 52 is shown by a one-dot chain line.
  • the emitter electrode on the substrate surface is omitted.
  • the plurality of trenches 31 are provided on the surface of the drift layer 2 in parallel with each other in a stripe shape extending in the Y direction in a plan view of the surface.
  • the trench 31 is covered with a gate insulating film 41 made of an oxide film, for example, and a gate electrode 51 made of a polysilicon layer doped with impurities is buried.
  • the trench 31, the gate insulating film 41 and the gate electrode 51 constitute a trench gate TG.
  • the trench gate TG constitutes the trench cell 11 of the IGBT 10A together with the adjacent emitter region 61, base region 21, and body region 71.
  • Base region 21 is a p-type impurity region provided on the surface of drift layer 2 between adjacent trenches 31.
  • the base region 21 is separated into a plurality by the drift layer 2 in the Y direction in which the trench gate TG extends, and is adjacent to a part of the trench gate TG.
  • the plurality of base regions 21 exist as regions separated from each other in an island shape by the trench gate TG and the drift layer 2. End portions of the base regions 21 adjacent to each other with the trench gate TG interposed therebetween (joint surface with the drift layer 2) are provided so as to be aligned in the X-plane direction.
  • the emitter region 61 is a high-concentration n-type (n + -type) impurity region provided on the surface of the base region 21 adjacent to the trench 31 (trench gate TG).
  • the emitter region 61 exists as an island-like region provided inside the base region 21.
  • Body region 71 is a high-concentration p-type (p + -type) impurity region provided between adjacent emitter regions 61 on the surface of base region 21.
  • Another gate insulating film 42 (not shown in FIG. 1A) is provided on the drift layer 2 between the base regions 21 adjacent in the Y direction.
  • the other gate insulating film 42 overlaps with the end portions of both adjacent base regions 41 and covers up to the end portions of the emitter regions 61 provided in the respective base regions 21.
  • the other gate electrode 52 is provided on the other gate insulating film 42.
  • the other gate insulating film 42 and the other gate electrode 52 constitute a planar gate PG.
  • the planar gate PG constitutes the planar cell 12 of the IGBT 10A together with the base region 21, the emitter region 61, and the body region 71 at both ends.
  • another gate electrode 52 continuously extends in the X direction orthogonal to the Y direction on the surface of the substrate.
  • the other gate electrode 52 is also provided on the trench gate TG, but the other gate insulating film 42 is removed at least on the gate electrode 51 to provide a contact hole CH ′. That is, in the region where the gate electrode 51 and the other gate electrode 52 intersect, these are overlapped and connected via the contact hole CH ′.
  • the other gate electrode 52 extends in the Y direction on the gate electrode 51 and is connected thereto.
  • the other gate electrode 52 continuously extends in the X direction, but the planar gate PG is provided only on the base region 21 adjacent in the Y direction.
  • An interlayer insulating film 3 is provided so as to cover the planar gate PG and the trench gate TG.
  • the interlayer insulating film 3 is provided with a contact hole CH (the second region r2 in FIG. 1A and a broken line in the third region r3) in which the emitter region 61 and the body region 71 are exposed in an island shape.
  • the pattern in plan view is a lattice pattern.
  • the gate electrode 51 and the other gate electrode 52 are formed so as to be connected to the gate routing wiring 8 formed around the IGBT 10A.
  • FIG. 2 is a cross-sectional view taken along the line aa in FIG.
  • a plurality of trench gates TG are provided on the surface of the drift layer 2 so as to be separated from each other.
  • the emitter region 61 is provided on both sides adjacent to the trench gate TG, and the body region 71 is provided between the adjacent emitter regions 61.
  • the depth of the base region 21 is shallower than the bottom of the trench 31, the depth of the body region 71 is shallower than the base region 21, and the depth of the emitter region 61 is shallower than the body region 71.
  • the trench gate TG and the base region 21, the emitter region 61, and the body region 71 sandwiched between the trench gates TG constitute the trench cell 11 of the IGBT 10A.
  • Another gate insulating film 42 is provided on the surface of the drift layer 2, and a part thereof is removed so that the gate electrode 51, the emitter region 61, and the body region 71 are exposed.
  • the other gate electrode 52 is patterned so as to overlap with the gate electrode 51 and is in contact with the gate electrode 51 through the contact hole CH ′ provided in the other gate insulating film 42.
  • Interlayer insulating film 3 is provided on another gate electrode 52, and contact hole CH is provided so that emitter region 61 and body region 71 are exposed.
  • the emitter electrode 4 is formed in a wide area so as to cover all the emitter regions 61.
  • the emitter electrode 4 is in contact with the emitter region 61 and the body region 71 through a contact hole CH provided in the interlayer insulating film 3.
  • a collector electrode 5 is provided on the back surface of the p ++ type semiconductor layer 1. Although illustration is omitted here, the guard ring 6 is formed to be deeper than the base region 21 around the IGBT 10A.
  • the gate routing wiring 8 is formed so that the upper and lower sides thereof are sandwiched between the interlayer insulating films 3 around the IGBT 10A.
  • FIG. 3 is a cross-sectional view taken along line bb in FIG.
  • a plurality of base regions 21 are formed separately from each other.
  • the body region 71 is formed so as to be positioned at the center on the surface of the base region 21.
  • the emitter region 61 is provided outside the body region 71 so as to surround it.
  • Another gate insulating film 42 is provided on the surface of the drift layer 2 between the adjacent base regions 21.
  • Another gate insulating film 42 is provided so as to cover the base region 21 and reach the end of the emitter region 61. Thereby, the emitter electrode 4 and the drift layer 2 are insulated.
  • Another gate electrode 52 is provided on the other gate insulating film 42 to constitute a planar gate PG.
  • An interlayer insulating film 3 is provided on the planar gate PG, and a contact hole CH in which the emitter region 61 and the body region 71 are exposed is provided in the interlayer insulating film 3.
  • the emitter electrode 4 is formed in a wide area so as to cover all the emitter regions 61. Then, the emitter region 61 and the body region 71 are contacted through a contact hole CH provided in the interlayer insulating film 3.
  • the planar gate PG, the base region 21, the emitter region 61, and the body region 71 at both ends thereof constitute the planar cell 12 of the IGBT 10A.
  • FIG. 4 is a cross-sectional view taken along the line cc of FIG.
  • FIG. 5 is a cross-sectional view taken along the line dd in FIG.
  • the base region 21, the emitter region 61, and the body region 71 are not formed.
  • the gate electrode 51 is formed so that one end and the other end thereof are connected to a gate routing wiring (not shown). Thereby, the gate electrode 51 is controlled according to the signal of the gate routing wiring.
  • the other gate electrode 52 provided on the surface of the drift layer 2 overlaps with and is connected to the gate electrode 51 in this cross section.
  • the other gate electrode 52 is also formed so that one end and the other end thereof are connected to the gate routing wiring, and is controlled according to the signal of the gate routing wiring.
  • Interlayer insulating film 3 is provided on another gate electrode 52, and emitter electrode 4 is provided thereon. Below, the effect
  • the base region 21 is connected to the emitter electrode 4, and holes injected into the drift layer 2 are discharged to the emitter electrode 4 through the nearest base region 21 that is a p-type impurity region.
  • the storage portion HA there is another gate between the emitter electrode 4 and the drift layer 2 (hereinafter referred to as the storage portion HA) between the base regions 21 indicated by the broken line.
  • the base region 21 is separated by the trench gate TG and the drift layer 2 and provided in an island shape, and the surface of the drift layer 2 where the base region 21 is not disposed is insulated from the emitter electrode 4.
  • holes may move between adjacent base regions 21, but in other regions, the holes move between one base region 21 and another base region 21, thereby forming an emitter electrode. There is no route discharged to 4.
  • FIG. 6 is a diagram illustrating a part of the IGBT 10B according to the second embodiment.
  • FIG. 6 is a diagram illustrating a part of the IGBT 10B according to the second embodiment.
  • FIG. 6A is a plan view
  • FIG. 6B is a part of the first region r1 in FIG. 6A. It is a perspective sectional view.
  • the illustration of the second region r2, the third region r3, and the fourth region r4 in FIG. 1A is the same as that in FIG. 7 is a cross-sectional view taken along the line c′-c ′ in FIG. 6, and
  • FIG. 8 is a cross-sectional view taken along the line d′-d ′ in FIG. 6.
  • the trench gate TG is separated into a plurality by the drift layer 2 in the Y direction.
  • Another gate insulating film 42 (not shown in FIG.
  • the other gate electrode 52 extends on the surface of the drift layer 2 between the separated trench gates TG.
  • the other gate electrode 52 overlaps with the gate electrode 51 at both ends, and extends on the gate electrode 51 in the Y direction.
  • the other gate insulating film 42 is not provided in the region where the other gate electrode 52 and the gate electrode 51 overlap. That is, the other gate electrode 52 and the gate electrode 51 are electrically connected through the contact hole CH ′ provided in the other gate insulating film 42. Since the configuration other than this is the same as that of the first embodiment, the description thereof is omitted.
  • the end portions (joint surfaces with the drift layer 2) of the base regions 21 adjacent to each other across the trench gate TG are provided so as to be aligned in the X plane direction.
  • the end of the trench 31 is provided so as to be aligned with the end of the base region 21 in the X direction.
  • a gate insulating film 41 is provided on the inner wall of the trench 31 and a gate electrode 51 is embedded.
  • the drift layer 2 extends in the X direction.
  • FIG. 7 a cross section taken along line c′-c ′ will be described. This cross section corresponds to a cross section taken along the line cc (FIG. 4) in the first embodiment.
  • the trench 31 is not provided in the drift layer 2.
  • Another gate insulating film 42 is provided on the surface of the drift layer 2.
  • the other gate insulating film 42 extends continuously in the X direction.
  • the d'-d 'line cross section is demonstrated. This cross section corresponds to a cross section taken along the line dd (FIG. 5) in the first embodiment.
  • the drift layer 2 is provided between adjacent trench gates TG, and the base region 21, the emitter region 61, and the body region 71 are not provided.
  • the gate electrode 51 is connected to the other gate electrode 52 through the contact hole CH ′ provided in the other gate insulating film 42.
  • the other gate insulating film 42, the other gate electrode 52, and the interlayer insulating film 3 are formed between the emitter electrode 4 and the drift layer 2 serving as the storage portion HA, holes are transferred to the base region. It is not discharged from the drift layer 2 between 21. For this reason, the effect of accumulating holes in the drift layer 2 serving as the accumulating portion HA can be enhanced.
  • the other configuration is the same as that of the first embodiment, the description thereof is omitted.
  • the operation of the IGBT 10B according to the second embodiment is the same as the operation of the IGBT 10A according to the first embodiment, and thus the description thereof is omitted.
  • the gate capacitance input capacitance
  • the trench gate TG is formed in the region where the transistor operation is not performed (inside the one-dot chain line). ing. For this reason, when a gate potential is applied to the gate electrode 51, a gate capacitance is generated although it does not contribute to the transistor operation.
  • the trench gate TG is omitted in a region where the base region 21 is not disposed (region not contributing to transistor operation: within a one-dot chain line). Thereby, an increase in useless gate capacity can be suppressed.
  • the other gate electrode 52 of the planar gate PG may be divided into a plurality of parts by the separation groove S. Thereby, an increase in gate capacitance (input capacitance) can be suppressed below the isolation trench S. Increasing the distance between two base regions 21 adjacent in the Y direction is advantageous for the hole accumulation effect in the accumulation portion HA. On the other hand, the width of the other gate electrode 52 is also widened, which causes an increase in gate capacitance in the central portion that does not overlap with the base region 21.
  • the isolation trench S in the central portion that does not contribute to channel formation, an increase in gate capacitance can be suppressed.
  • the other separated gate electrodes 521 and 522 are covered with one interlayer insulating film 3 and are connected, for example, at an inner portion of the gate routing wiring 8 of FIG. Since the other configuration is the same as that of the first embodiment or the second embodiment, the description thereof is omitted.
  • the gate routing wiring 8 is arranged outside the guard ring 6.
  • the present invention is not limited to this, and can be appropriately changed in design. Moreover, even if it is the structure which reversed said embodiment and the conductivity type, it can implement similarly.

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Abstract

In conventional IGBTs, accumulation quantity of holes is maintained by aggressively reducing the area rate of a main cell and suppressing the quantity of holes discharged to the emitter side, and conductivity modulation of a base layer is promoted. There has been, however, a problem of current density reduction due to the reduction of the area ratio of the main cell. Disclosed is an IGBT having a trench cell, wherein the base region is separated in the extending direction of the trench gate such that base regions are disposed in the direction that orthogonally intersects the extending direction of the trench gate. A planar gate is disposed on the drift layer surface between the separated base regions. The gate electrode of the planar gate and the gate electrode of the trench gate are connected on the trench gate.

Description

絶縁ゲート型バイポーラトランジスタInsulated gate bipolar transistor
　本発明は絶縁ゲート型バイポーラトランジスタに係り、特に正孔の蓄積効果を高めた絶縁ゲート型バイポーラトランジスタに関する。 The present invention relates to an insulated gate bipolar transistor, and more particularly to an insulated gate bipolar transistor having an enhanced hole accumulation effect.
　絶縁ゲート型バイポーラトランジスタ（以下、ＩＧＢＴ（Ｉｎｓｕｌａｔｅｄ−Ｇａｔｅ　Ｂｉｐｏｌａｒ　Ｔｒａｎｓｉｓｔｏｒ））は、パワーエレクトニクス分野におけるスイッチング素子として用いられている。
　ＩＧＢＴは、ＰＴ（Ｐｕｎｃｈ　Ｔｈｒｏｕｇｈ）構造とＮＰＴ（Ｎｏｎ　Ｐｕｎｃｈｉ　Ｔｈｒｏｕｇｈ）構造とに大別される。
　ＰＴ構造は、コレクタ層として半導体基板が用いられ、これにバッファ層、ドリフト層が順次エピタキシャル成長されたものである。ドリフト層は、高耐圧が要求されると、それに応じた厚さが必要となる。そうすると、ドリフト層のエピタキシャル成長によるコストが増大してしまう。
　これに対して、ＮＰＴ構造では、ドリフト層は、ＦＺ（Ｆｌｏａｔ　Ｚｏｎｉｎｇ）ウエハが研磨されて形成される。これにより、高耐圧が要求されても、製造コストの増大が抑制される。
　ところが、ＮＰＴ構造では、コレクタ層は、ｐ＋型不純物が低ドーズ量でドリフト層に注入されることにより形成される。このため、ＮＰＴ構造は、ＰＴ構造と比較すると、コレクタ層からドリフト層に注入される正孔の量が数桁低くなる。この場合、正孔がエミッタ電極から排出される量を無視できない。
　これを解決すべく、従来においても、正孔の排出を抑制する試みがなされてきた。例えば、特許文献１では、隣接するトレンチ間の第１領域ではエミッタ領域とエミッタ電極とを接続させることで当該領域をメインセルとする一方、隣接するトレンチ間であって第１領域と異なる第２領域ではエミッタ領域とエミッタ電極との間に層間絶縁膜を形成することで当該領域をダミーセルとする構成が開示されている。正孔はＩＧＢＴがオンの状態においてコレクタ側からベース層に注入されるわけであるが、このような構成によってメインセルの面積が減少するため、正孔がメインセルを通じてエミッタ側へ排出されにくくなる。 Insulated gate bipolar transistors (hereinafter referred to as IGBTs (Insulated-Gate Bipolar Transistors)) are used as switching elements in the field of power electronics.
The IGBT is roughly classified into a PT (Punch Through) structure and an NPT (Non Punch Through) structure.
In the PT structure, a semiconductor substrate is used as a collector layer, and a buffer layer and a drift layer are sequentially epitaxially grown thereon. When a high breakdown voltage is required, the drift layer needs to have a thickness corresponding to it. If it does so, the cost by the epitaxial growth of a drift layer will increase.
On the other hand, in the NPT structure, the drift layer is formed by polishing an FZ (Float Zoning) wafer. Thereby, even if a high breakdown voltage is required, an increase in manufacturing cost is suppressed.
However, in the NPT structure, the collector layer is formed by injecting p + type impurities into the drift layer with a low dose. For this reason, the amount of holes injected from the collector layer into the drift layer is several orders of magnitude lower in the NPT structure than in the PT structure. In this case, the amount of holes discharged from the emitter electrode cannot be ignored.
In order to solve this problem, attempts have been made in the past to suppress the discharge of holes. For example, in Patent Document 1, the emitter region and the emitter electrode are connected in the first region between adjacent trenches to make the region a main cell, while the second region that is between adjacent trenches and is different from the first region. In the region, a configuration is disclosed in which an interlayer insulating film is formed between the emitter region and the emitter electrode to make the region a dummy cell. Holes are injected into the base layer from the collector side when the IGBT is on. However, since the area of the main cell is reduced by such a configuration, holes are not easily discharged to the emitter side through the main cell. .
特開平８−１６７７１６号公報JP-A-8-167716
　上述のように、特許文献１に係る発明では、メインセルの面積比率を積極的に減少させることにより、正孔のエミッタ側への排出量を抑制して正孔の蓄積量を保ち、ベース層の伝導度変調を促進することができる。
　しかし、当該従来技術では、メインセルの面積比率が減少するため、電流密度が低下してしまう問題があった。 As described above, in the invention according to Patent Document 1, by actively reducing the area ratio of the main cell, the amount of holes discharged to the emitter side is suppressed, the amount of accumulated holes is maintained, and the base layer It is possible to promote conductivity modulation.
However, the conventional technique has a problem in that the current density decreases because the area ratio of the main cell decreases.
　本発明はかかる課題に鑑みてなされ、コレクタ領域となる一導電型半導体層と、該一導電型半導体層上に設けられた逆導電型半導体層と、前記逆導電型半導体層表面に設けられ該表面において第１方向に延在する複数のトレンチと、該トレンチ内に絶縁膜を介して設けられたゲート電極と、隣り合う前記トレンチ間の前記逆導電型半導体層表面に設けられ、前記第１方向において該逆導電型半導体層で互いに分離された一導電型のベース領域と、該ベース領域表面で前記トレンチに隣接して設けられた逆導電型のエミッタ領域と、前記第１方向において隣り合う前記ベース領域間の前記逆導電型半導体層上に設けられ前記両ベース領域の端部と重畳する他の絶縁膜と、該他の絶縁膜上に設けられた他のゲート電極と、を具備することにより解決するものである。
　本発明は、ストライプ状のトレンチ型セルを有するＮＰＴ構造のＩＧＢＴにおいて、正孔の流出経路となるベース領域をトレンチの延在方向において分離して設け、ベース領域が配置されないドリフト層表面にエミッタ電極との絶縁膜を設けて、トランジスタのオン時にドリフト層に注入された正孔の流出する経路を制限し、正孔の蓄積効果を高めるものである。
　更に、ベース領域が配置されないドリフト層表面に、プレーナー構造のトランジスタを配置して電子供給源を増やし、正孔の蓄積効果を高めつつ電流密度の低下を抑制するものである。 The present invention has been made in view of such a problem, and includes a one-conductivity-type semiconductor layer serving as a collector region, a reverse-conductivity-type semiconductor layer provided on the one-conductivity-type semiconductor layer, and a surface provided on the surface of the reverse-conductivity-type semiconductor layer. A plurality of trenches extending in the first direction on the surface, a gate electrode provided in the trench via an insulating film, and provided on the surface of the reverse conductivity type semiconductor layer between the adjacent trenches; One conductivity type base region separated from each other by the opposite conductivity type semiconductor layer in the direction, and an opposite conductivity type emitter region provided adjacent to the trench on the surface of the base region, adjacent in the first direction Another insulating film provided on the opposite conductivity type semiconductor layer between the base regions and overlapping an end portion of the both base regions, and another gate electrode provided on the other insulating film. By the solution It is intended to.
The present invention relates to an NPT-structure IGBT having a stripe-shaped trench cell, in which a base region serving as a hole outflow path is provided separately in the extending direction of the trench, and an emitter electrode is formed on the surface of the drift layer where the base region is not disposed. Is provided to limit the path through which holes injected into the drift layer flow when the transistor is turned on, thereby enhancing the hole accumulation effect.
Further, a planar structure transistor is disposed on the surface of the drift layer where the base region is not disposed to increase the number of electron supply sources, thereby suppressing the decrease in current density while enhancing the hole accumulation effect.
　本発明によれば、以下の効果が得られる、
　第１に、トレンチ型セルを有するＮＰＴ構造の絶縁ゲート型バイポーラトランジスタにおいて、トランジスタのオン時にドリフト層に注入された正孔の蓄積効果を高めることができる。
　すなわち、ストライプ状に延在するトレンチ（トレンチゲート）に隣接するベース領域を、トレンチの延在方向において分離して設け、分離された両ベース領域間のドリフト層表面にエミッタ電極とドリフト層を絶縁する絶縁膜を設ける。これにより、従来構造と比較して、ｐ型不純物領域であるベース領域を介して正孔が引き抜かれる経路を制限できるので、コレクタ層から注入された正孔が蓄積され易い構造を実現できる。
　正孔は直近のｐ型不純物領域を介して、エミッタ電極へ流出するので、ベース領域を分離することにより、正孔の蓄積効果を高めることができる。また、ドリフト層上には、両ベース領域を接続する電極（エミッタ電極）が存在しているため、両ベース領域が配置されない領域間のドリフト層表面に、当該電極とドリフト層とを絶縁する絶縁膜を設け、正孔が離間した両ベース領域のみを経路として引き抜かれるように制限する。
　これにより、ドリフト層における正孔の蓄積効果を高めることができ、飽和電圧の低減を図ることができる。
　加えて、離間したベース領域間のドリフト層（絶縁膜）上にプレーナー型のＩＧＢＴのセルを設けることにより、トランジスタのオン時のチャネル（反転層）長を稼ぎ、電子供給源を増やすことができる。トレンチ型のセルにおいてベース領域間を離間することは、当該セルの間隔を離間することとなり、トランジスタのセル密度が減少することになる。しかし、ベース領域を離間した箇所にプレーナー構造の他のセルを配置することで、セル密度の大幅な減少を抑制できる。
　これにより、正孔蓄積効果を高めつつ、チャネル抵抗を低減し、電流密度の低下を抑制できる。
　第２に、トレンチ（トレンチゲート）を、トレンチの延在方向において複数に分離し、ベース領域が配置される領域のみに設けることにより、基板の端部までストライプ状にトレンチ（トレンチゲート）が延在しベース領域が選択的に配置される構造と比較して、両ベース領域が配置されない領域（トランジスタ動作に寄与しない領域）におけるゲート容量の増加を抑制できる。 According to the present invention, the following effects can be obtained.
First, in an NPT structure insulated gate bipolar transistor having a trench type cell, the effect of accumulating holes injected into the drift layer when the transistor is turned on can be enhanced.
That is, a base region adjacent to a trench (trench gate) extending in a stripe shape is provided separately in the extending direction of the trench, and the emitter electrode and the drift layer are insulated from the surface of the drift layer between the two separated base regions. An insulating film is provided. As a result, the path through which holes are extracted through the base region, which is a p-type impurity region, can be limited as compared with the conventional structure, so that a structure in which holes injected from the collector layer are easily accumulated can be realized.
Since holes flow out to the emitter electrode through the nearest p-type impurity region, the effect of accumulating holes can be enhanced by separating the base region. In addition, since there is an electrode (emitter electrode) that connects both base regions on the drift layer, insulation that insulates the electrode and the drift layer from the surface of the drift layer between regions where both base regions are not disposed. A film is provided, and the base region where holes are separated from each other is limited to be drawn out as a path.
Thereby, the hole accumulation effect in the drift layer can be enhanced, and the saturation voltage can be reduced.
In addition, by providing a planar IGBT cell on the drift layer (insulating film) between the separated base regions, the channel (inversion layer) length when the transistor is on can be increased, and the number of electron supply sources can be increased. . Separation between the base regions in the trench type cell results in separation of the interval between the cells, and the cell density of the transistor is reduced. However, a significant reduction in cell density can be suppressed by arranging other cells of the planar structure at locations apart from the base region.
Thereby, it is possible to reduce channel resistance and suppress a decrease in current density while enhancing the hole accumulation effect.
Second, the trench (trench gate) is separated into a plurality of portions in the direction in which the trench extends and is provided only in the region where the base region is disposed, so that the trench (trench gate) extends in a stripe shape to the edge of the substrate. Compared with the structure in which the existing base region is selectively disposed, an increase in gate capacitance in a region where both base regions are not disposed (region not contributing to transistor operation) can be suppressed.
　図１は本発明の第１の実施形態の絶縁ゲート型バイポーラトランジスタを説明する（Ａ）平面図、（Ｂ）斜視断面図である。
　図２は本発明の第１の実施形態の絶縁ゲート型バイポーラトランジスタを説明する断面図である。
　図３は本発明の第１の実施形態の絶縁ゲート型バイポーラトランジスタを説明する断面図である。
　図４は本発明の第１の実施形態の絶縁ゲート型バイポーラトランジスタを説明する断面図である。
　図５は本発明の第１の実施形態の絶縁ゲート型バイポーラトランジスタを説明する断面図である。
　図６は本発明の第２の実施形態の絶縁ゲート型バイポーラトランジスタを説明する（Ａ）平面図、（Ｂ）斜視断面図である。
　図７は本発明の第２の実施形態の絶縁ゲート型バイポーラトランジスタを説明する断面図である。
　図８は本発明の第２の実施形態の絶縁ゲート型バイポーラトランジスタを説明する断面図である。
　図９は本発明の第３の実施形態の絶縁ゲート型バイポーラトランジスタを説明する断面図である。 FIG. 1A is a plan view and FIG. 1B is a perspective sectional view for explaining an insulated gate bipolar transistor according to a first embodiment of the present invention.
FIG. 2 is a cross-sectional view illustrating the insulated gate bipolar transistor according to the first embodiment of the present invention.
FIG. 3 is a sectional view for explaining an insulated gate bipolar transistor according to the first embodiment of the present invention.
FIG. 4 is a cross-sectional view illustrating the insulated gate bipolar transistor according to the first embodiment of the present invention.
FIG. 5 is a cross-sectional view illustrating an insulated gate bipolar transistor according to the first embodiment of the present invention.
6A is a plan view and FIG. 6B is a perspective sectional view for explaining an insulated gate bipolar transistor according to a second embodiment of the present invention.
FIG. 7 is a cross-sectional view illustrating an insulated gate bipolar transistor according to the second embodiment of the present invention.
FIG. 8 is a cross-sectional view illustrating an insulated gate bipolar transistor according to the second embodiment of the present invention.
FIG. 9 is a cross-sectional view illustrating an insulated gate bipolar transistor according to the third embodiment of the present invention.
　以下、図１から図９を参照して、本発明の実施形態について、ｎチャネル型ＮＰＴ−ＩＧＢＴを例に詳述する。
　はじめに、本発明の第１実施形態に係るＩＧＢＴ１０Ａの構成について、図１から図５を参照して具体的に説明する。図１はＩＧＢＴ１０Ａを示す図であり、図１（Ａ）がＩＧＢＴ１０Ａの基板の主面（表面）側の平面図であり、図１（Ｂ）が図１の第１領域ｒ１の一部を示す斜視断面図である。
　図１を参照して、ＩＧＢＴ１０Ａは、一導電型半導体層１と、逆導電型半導体層２と、トレンチ３１と、絶縁膜４１と、ゲート電極５１と、ベース領域２１と、エミッタ領域６１と、他の絶縁膜４２と、他のゲート電極５２を有する。
　基板は、コレクタ層となる高濃度のｐ型（ｐ＋＋型）半導体層１の上に、ｎ−型半導体層２を積層してなる。ｎ−型半導体層２はＩＧＢＴ１０Ａのドリフト層となる（図１（Ｂ））。
　尚、本実施形態のＩＧＢＴ１０Ａは、ＮＰＴ構造であり、ｎ−型のＦＺウエハ（シリコンウエハ）に、ｐ＋＋型不純物のイオン注入によりｐ＋＋型半導体層１を形成している。
　ここで、図１（Ａ）においては、第２領域ｒ２にドリフト層（ｎ−型半導体層）２表面に設けられる構成を示し、第３領域ｒ３にドリフト層２表面に設けられる他のゲート電極５２のパターン重ねて示した。また第４領域ｒ４に他のゲート電極５２上の層間絶縁膜３のパターンを示し、他のゲート電極５２を一点鎖線で示した。図１（Ａ）および図１（Ｂ）において、基板表面のエミッタ電極は省略している。
　複数のトレンチ３１は、ドリフト層２表面に、当該表面の平面視においてＹ方向に延びるストライプ状で、互いに平行に設けられる。トレンチ３１内は、例えば酸化膜などによるゲート絶縁膜４１で被覆され、不純物をドープしたポリシリコン層などによるゲート電極５１が埋設される。トレンチ３１とゲート絶縁膜４１とゲート電極５１によってトレンチゲートＴＧが構成される。トレンチゲートＴＧは、隣接するエミッタ領域６１、ベース領域２１、ボディ領域７１とともにＩＧＢＴ１０Ａのトレンチセル１１を構成する。
　ベース領域２１は、隣り合うトレンチ３１間のドリフト層２表面に設けられたｐ型不純物領域である。ベース領域２１は、トレンチゲートＴＧが延在するＹ方向において、ドリフト層２によって複数に分離され、トレンチゲートＴＧの一部と隣接する。複数のベース領域２１は、トレンチゲートＴＧとドリフト層２によって、互いに島状に分離した領域として存在する。
　トレンチゲートＴＧを挟んで隣り合うベース領域２１の端部（ドリフト層２との接合面）は、Ｘ平方向において揃うように設けられる。
　エミッタ領域６１は、トレンチ３１（トレンチゲートＴＧ）に隣接してベース領域２１表面に設けられた高濃度のｎ型（ｎ＋型）不純物領域である。エミッタ領域６１は、ベース領域２１の内側に設けられた島状の領域として存在する。
　ボディ領域７１は、ベース領域２１表面で隣り合うエミッタ領域６１の間に設けられた高濃度のｐ型（ｐ＋型）不純物領域である。
　他のゲート絶縁膜４２（図１（Ａ）では省略）は、Ｙ方向において隣り合うベース領域２１間のドリフト層２上に設けられる。他のゲート絶縁膜４２は、隣り合う両ベース領域４１の端部と重畳し、それぞれのベース領域２１に設けられたエミッタ領域６１の端部までを覆う。
　他のゲート電極５２は、他のゲート絶縁膜４２上に設けられる。他のゲート絶縁膜４２と他のゲート電極５２によってプレーナゲートＰＧが構成される。プレーナゲートＰＧは、両端のベース領域２１およびエミッタ領域６１、ボディ領域７１とともにＩＧＢＴ１０Ａのプレーナセル１２を構成する。
　図１では一部を省略しているが、図１（Ｂ）を参照して、他のゲート電極５２は、基板の表面において、Ｙ方向に直交するＸ方向に連続して延在する。他のゲート電極５２はトレンチゲートＴＧ上にも設けられるが、他のゲート絶縁膜４２は、少なくともゲート電極５１上では取り除かれ、コンタクトホールＣＨ’が設けられる。つまり、ゲート電極５１と他のゲート電極５２が交差する領域では、これらがコンタクトホールＣＨ’を介して重畳して接続する。他のゲート電極５２は、ゲート電極５１上においてＹ方向にも延在して、これと接続する。
　このように本実施形態では、他のゲート電極５２はＸ方向に連続して延在するが、プレーナゲートＰＧは、Ｙ方向において隣り合うベース領域２１上にのみ、設けられる。
　プレーナゲートＰＧおよびトレンチゲートＴＧ上を覆って、層間絶縁膜３が設けられる。層間絶縁膜３にはエミッタ領域６１およびボディ領域７１が島状に露出するコンタクトホールＣＨ（図１（Ａ）の第２領域ｒ２、第３領域ｒ３では破線）が設けられ、層間絶縁膜３の平面視におけるパターンは格子状となる。
　ゲート電極５１および他のゲート電極５２は、ＩＧＢＴ１０Ａの周囲に形成されたゲート引き回し配線８と接続されるように形成される。これにより、ゲート電極５１および他のゲート電極５２は、ゲート引き回し配線８の信号に応じて制御される。また、ｐ＋型不純物領域であるガードリング６は、ゲート引き回し配線８に囲まれた領域であって基板の周囲に形成される。
　図２は、図１（Ａ）のａ−ａ線の断面図である。
　トレンチゲートＴＧは、ドリフト層２表面に互いに離間して複数設けられる。エミッタ領域６１は、トレンチゲートＴＧに隣接してその両側に設けられ、ボディ領域７１は、隣り合うエミッタ領域６１間に設けられる。ベース領域２１の深さは、トレンチ３１の底部より浅く、ボディ領域７１の深さはベース領域２１より浅く、エミッタ領域６１の深さはボディ領域７１より浅い。
　トレンチゲートＴＧと、これに挟まれたベース領域２１、エミッタ領域６１およびボディ領域７１は、ＩＧＢＴ１０Ａのトレンチセル１１を構成する。
　ドリフト層２表面に他のゲート絶縁膜４２が設けられ、ゲート電極５１とエミッタ領域６１およびボディ領域７１が露出するようにその一部が取り除かれる。他のゲート電極５２は、ゲート電極５１と重畳するようにパターンニングされ、他のゲート絶縁膜４２に設けられたコンタクトホールＣＨ’を介してゲート電極５１とコンタクトする。他のゲート電極５２上に層間絶縁膜３が設けられ、エミッタ領域６１およびボディ領域７１が露出するようにコンタクトホールＣＨが設けられる。
　エミッタ電極４は、全てのエミッタ領域６１を覆うことができる程度の面積にて幅広く形成される。そして、エミッタ電極４は、層間絶縁膜３に設けたコンタクトホールＣＨを介して、エミッタ領域６１およびボディ領域７１とコンタクトする。ｐ＋＋型半導体層１の裏面にはコレクタ電極５が設けられる。
　ここでの図示は省略するが、ガードリング６は、ＩＧＢＴ１０Ａの周囲において、ベース領域２１よりも深くなるように形成される。また、ゲート引き回し配線８は、ＩＧＢＴ１０Ａの周囲において、その上下が層間絶縁膜３に挟まれるように形成される。
　図３は、図１（Ａ）のｂ−ｂ線の断面図である。
　ベース領域２１は、それぞれが離間して複数形成される。また、ボディ領域７１は、ベース領域２１の表面において、中心に位置するように形成される。エミッタ領域６１は、ボディ領域７１の外側でこれを囲んで設けられる。
　隣り合うベース領域２１間のドリフト層２表面に他のゲート絶縁膜４２が設けられる。他のゲート絶縁膜４２は、ベース領域２１上を覆い、エミッタ領域６１の端部に達して設けられる。これにより、エミッタ電極４とドリフト層２は絶縁される。
　他のゲート絶縁膜４２上には他のゲート電極５２が設けられてプレーナゲートＰＧを構成する。
　プレーナゲートＰＧ上には層間絶縁膜３が設けられ、層間絶縁膜３にはエミッタ領域６１とボディ領域７１が露出するコンタクトホールＣＨが設けられる。エミッタ電極４は、全てのエミッタ領域６１を覆うことができる程度の面積にて幅広く形成される。そして、層間絶縁膜３に設けられたコンタクトホールＣＨを介して、エミッタ領域６１およびボディ領域７１とコンタクトする。
　プレーナゲートＰＧと、その両端のベース領域２１、エミッタ領域６１、ボディ領域７１は、ＩＧＢＴ１０Ａのプレーナセル１２を構成する。
　図４は、図１（Ａ）のｃ−ｃ線の断面図である。
　ドリフト層２の表面において、トレンチゲートＴＧは、離間して複数設けられ、この断面においてはベース領域２１、エミッタ領域６１およびボディ領域７１は形成されない。
　トレンチゲートＴＧ間のドリフト層２表面に、他のゲート絶縁膜４２が設けられ、トレンチゲートＴＧおよびドリフト層２上に他のゲート電極５２が設けられる。他のゲート電極５２は、他のゲート絶縁膜４２に設けられたコンタクトホールＣＨ’を介してゲート電極５１上でこれとコンタクトする。
　層間絶縁膜３が他のゲート電極５２を全て覆って設けられ、その上にエミッタ電極４が設けられる。エミッタ電極４は、この断面においてドリフト層２と絶縁されている。
　図５は、図１（Ａ）のｄ−ｄ線の断面図である。
　この断面においては、ベース領域２１、エミッタ領域６１及びボディ領域７１は形成されない。一方、ゲート電極５１は、その一端及び他端が不図示のゲート引き回し配線と接続されるように形成される。これにより、ゲート電極５１は、ゲート引き回し配線の信号に応じて制御される。
　ドリフト層２の表面上に設けられる他のゲート電極５２は、この断面においては、ゲート電極５１と重畳し、これと接続する。また他のゲート電極５２も一端及び他端がゲート引き回し配線と接続されるように形成され、ゲート引き回し配線の信号に応じて制御される。
　他のゲート電極５２上に層間絶縁膜３が設けられ、その上にエミッタ電極４が設けられる。
　以下に、当該構成による作用について説明する。
　図２を参照して、ＩＧＢＴ１０Ａがオン状態のとき、すなわち、エミッタ電極４がアースに接続され、コレクタ電極５に正電圧が印加されると、ドリフト層２とベース領域２１とからなるｐｎ接合は逆バイアスとなる。この状態においてゲート電極５１にエミッタ電極４との間で閾値以上の正電圧が印加されると、ドリフト層２にはゲート電極５１に沿ってｎ型に反転したチャネルが形成される。すると、当該チャネルを介して、エミッタ領域６１からドリフト層２に電子が注入される。電子は、主に矢印の如く、ベース領域２１下方のドリフト層２を経路として移動する。これにより、コレクタ層１からドリフト層２に正孔が注入され、ドリフト層２において伝導度変調が生じて、ドリフト層２の抵抗が低くなる。
　ベース領域２１はエミッタ電極４と接続しており、ドリフト層２に注入された正孔は、ｐ型不純物領域である直近のベース領域２１を介してエミッタ電極４に排出される。
　このとき、ｂ−ｂ線における断面（図３）を参照すると、エミッタ電極４と、破線で示すベース領域２１間のドリフト層２（以下、蓄積部ＨＡと称する）との間には他のゲート絶縁膜４２、他のゲート電極５２および層間絶縁膜３が形成されているため、正孔は、ベース領域２１間のドリフト層２からは排出されない。
　また、ｃ−ｃ線における断面（図４）においても、ベース領域２１が配置されないため正孔が排出される経路がない。つまり、正孔の排出経路は島状に分離されたベース領域２１（図２）のみに制限されるため、正孔のエミッタ電極４への排出が抑制され、蓄積部ＨＡとなるドリフト層２における正孔の蓄積効果を高めることができる。
　従って、本実施形態では、ＩＧＢＴ１０Ａのオン状態において、蓄積部ＨＡに正孔が蓄積されやすく、エミッタ電極４から正孔が排出されにくい（正孔の排出経路が制限される）ため、伝導度変調効果が良好であり、飽和電圧の低減を図ることができる。
　本実施形態では、ベース領域２１をトレンチゲートＴＧとドリフト層２で分離して島状に設け、ベース領域２１が配置されないドリフト層２表面をエミッタ電極４と絶縁している。例えば図３の断面では隣り合うベース領域２１間を正孔が移動することもあるが、これ以外の領域において、１つのベース領域２１と他のベース領域２１間を正孔が移動してエミッタ電極４に排出される経路は有さない。つまり、正孔の排出経路は、島状のベース領域２１のみに制限されるので、良好に正孔を蓄積することができる。
　更に、本実施形態ではプレーナセル１２によって、電子供給源を確保できる。
　図２および図３を参照して説明する。ａ−ａ線断面（図２）において、ＩＧＢＴ１０Ａのオン時には、トレンチセル１１にチャネルが形成されてドリフト層２に電子が注入される。同時に、ｂ−ｂ線断面（図３）においては、プレーナゲートＰＧ両端のベース領域２１もｎ型に反転し、チャネルが形成される。そして、チャネルを介して、エミッタ領域６１からドリフト層２に電子が注入される（矢印）。つまり、ベース領域２１が配置されないドリフト層２においても、電子を多く供給することができる。
　正孔の排出経路となるベース領域２１は、その距離が離間している方が正孔の蓄積効果が高くなる。しかし、ベース領域２１間を離間することは、トレンチセル１１として動作する領域が低減することとなる。しかし、トレンチセル１１として動作しない領域に、プレーナセル１２を配置することにより、電子供給源を確保し、セル密度の減少を抑制できる。
　これにより、正孔蓄積効果を高めつつ、チャネル抵抗を低減し、電流密度の低下を抑制できる。
　図６から図８を参照して、本発明の第２の実施形態について説明する。図６は、第２の実施形態のＩＧＢＴ１０Ｂの一部を示す図であり、図６（Ａ）が平面図、図６（Ｂ）が図６（Ａ）の第１領域ｒ１の一部を示す斜視断面図である。また、図１（Ａ）の第２領域ｒ２、第３領域ｒ３、第４領域ｒ４の図示についての説明は図１（Ａ）と同様である。
　また、図７は、図６のｃ’−ｃ’線断面図であり、図８は、図６のｄ’−ｄ’線断面図である。
　図６を参照して本実施形態では、トレンチゲートＴＧは、Ｙ方向においてドリフト層２によって複数に分離される。分離されたトレンチゲートＴＧ間のドリフト層２表面には、他のゲート絶縁膜４２（図６（Ａ）では省略）が延在する。図６（Ｂ）を参照して他のゲート電極５２は両端がゲート電極５１と重畳し、ゲート電極５１上をＹ方向にも延在する。他のゲート電極５２とゲート電極５１が重畳する領域には他のゲート絶縁膜４２は設けられない。つまり他のゲート絶縁膜４２に設けたコンタクトホールＣＨ’を介して、他のゲート電極５２とゲート電極５１は電気的に接続する。これ以外の構成は、第１の実施形態と同様であるので、説明は省略する。
　第１の実施形態と同様に、トレンチゲートＴＧを挟んで隣り合うベース領域２１の端部（ドリフト層２との接合面）は、Ｘ平方向において揃うように設けられる。そして本実施形態では、トレンチ３１の端部はＸ方向においてベース領域２１の端部と揃うように設けられる。トレンチ３１内壁にゲート絶縁膜４１が設けられ、ゲート電極５１が埋設される。Ｙ方向において隣り合うトレンチゲートＴＧとベース領域２１の間に、ドリフト層２がＸ方向に延在する。
　図７を参照して、ｃ’−ｃ’線断面について説明する。この断面は、第１の実施形態のではｃ−ｃ線断面（図４）に相当する。
　この断面において、ドリフト層２にはトレンチ３１が設けられない。ドリフト層２表面には、他のゲート絶縁膜４２が設けられる。他のゲート絶縁膜４２は、Ｘ方向に連続して延在する。
　図８を参照して、ｄ’−ｄ’線断面について説明する。この断面は、第１の実施形態のではｄ−ｄ線断面（図５）に相当する。
　この断面において、隣り合うトレンチゲートＴＧ間にドリフト層２が設けられ、ベース領域２１、エミッタ領域６１およびボディ領域７１は設けられない。ゲート電極５１は、他のゲート絶縁膜４２に設けられたコンタクトホールＣＨ’を介して、他のゲート電極５２と接続する。
　すなわち、エミッタ電極４と、蓄積部ＨＡとなるドリフト層２との間には他のゲート絶縁膜４２、他のゲート電極５２および層間絶縁膜３が形成されているため、正孔は、ベース領域２１間のドリフト層２からは排出されない。このため、蓄積部ＨＡとなるドリフト層２における正孔の蓄積効果を高めることができる。
　これ以外の構成は、第１の実施形態と同様であるので説明は省略する。また、第２実施形態のＩＧＢＴ１０Ｂの動作は、第１の実施形態のＩＧＢＴ１０Ａの動作と同様であるので、説明は省略する。
　第２の実施形態では、第１の実施形態と比較して、ゲート容量（入力容量）を低減できる。図８と、第１の実施形態の図５を比較すると、第１の実施形態では、ベース領域２１が設けられないためトランジスタ動作を行わない領域（一点鎖線内）に、トレンチゲートＴＧが形成されている。このため、ゲート電極５１にゲート電位が印加されると、トランジスタ動作に寄与しないにもかかわらず、ゲート容量は、発生してしまう。
　これに対し、第２の実施形態（図８）では、ベース領域２１が配置されない領域（トランジスタ動作に寄与しない領域：一点鎖線内）において、トレンチゲートＴＧを省いている。これにより、無駄なゲート容量の増加を抑制できる。
　図９は、第３の実施形態のＩＧＢＴ１０Ｃを示す図であり、図１のｂ−ｂ線に相当する断面図である。
　プレーナゲートＰＧの他のゲート電極５２は、分離溝Ｓによって複数に分割された構造であってもよい。これにより、分離溝Ｓ下方において、ゲート容量（入力容量）の増加を抑制することができる。Ｙ方向において隣り合う２つのベース領域２１間の距離を広げると、蓄積部ＨＡにおける正孔の蓄積効果には有利である。一方で、他のゲート電極５２もその幅が広くなり、ベース領域２１と重畳していない中央部分においてはゲート容量の増加の原因となる。そこでチャネル形成に寄与しない中央部分に分離溝Ｓを設けることで、ゲート容量の増加を抑制できる。
　この場合、分離された他のゲート電極５２１、５２２は１つの層間絶縁膜３で被覆され、例えば図１のゲート引き回し配線８の内側部分において連結される。
　これ以外の構成は、第１の実施形態または第２の実施形態と同様であるので説明は省略する。
　尚、上記実施形態では、ゲート引き回し配線８がガードリング６の外側に配置されていた。しかし、本発明はこれに限定されず、設計上、適宜変更できる。
　また、上記の実施形態と導電型を逆にした構造であっても同様に実施できる。 Hereinafter, an embodiment of the present invention will be described in detail by taking an n-channel NPT-IGBT as an example with reference to FIGS.
First, the configuration of the IGBT 10A according to the first embodiment of the present invention will be specifically described with reference to FIGS. FIG. 1 is a diagram showing the IGBT 10A, FIG. 1A is a plan view of the main surface (front surface) side of the substrate of the IGBT 10A, and FIG. 1B shows a part of the first region r1 in FIG. It is a perspective sectional view.
Referring to FIG. 1, IGBT 10 </ b> A includes one-conductivity-type semiconductor layer 1, reverse-conductivity-type semiconductor layer 2, trench 31, insulating film 41, gate electrode 51, base region 21, emitter region 61, Another insulating film 42 and another gate electrode 52 are provided.
The substrate is formed by laminating an n− type semiconductor layer 2 on a high concentration p type (p ++ type) semiconductor layer 1 serving as a collector layer. The n − type semiconductor layer 2 becomes a drift layer of the IGBT 10A (FIG. 1B).
The IGBT 10A of the present embodiment has an NPT structure, and the p ++ type semiconductor layer 1 is formed on an n− type FZ wafer (silicon wafer) by ion implantation of p ++ type impurities.
Here, FIG. 1A shows a configuration in which the second region r2 is provided on the surface of the drift layer (n− type semiconductor layer) 2 and another gate electrode provided in the third region r3 on the surface of the drift layer 2. 52 patterns are shown superimposed. Further, the pattern of the interlayer insulating film 3 on the other gate electrode 52 is shown in the fourth region r4, and the other gate electrode 52 is shown by a one-dot chain line. In FIGS. 1A and 1B, the emitter electrode on the substrate surface is omitted.
The plurality of trenches 31 are provided on the surface of the drift layer 2 in parallel with each other in a stripe shape extending in the Y direction in a plan view of the surface. The trench 31 is covered with a gate insulating film 41 made of an oxide film, for example, and a gate electrode 51 made of a polysilicon layer doped with impurities is buried. The trench 31, the gate insulating film 41 and the gate electrode 51 constitute a trench gate TG. The trench gate TG constitutes the trench cell 11 of the IGBT 10A together with the adjacent emitter region 61, base region 21, and body region 71.
Base region 21 is a p-type impurity region provided on the surface of drift layer 2 between adjacent trenches 31. The base region 21 is separated into a plurality by the drift layer 2 in the Y direction in which the trench gate TG extends, and is adjacent to a part of the trench gate TG. The plurality of base regions 21 exist as regions separated from each other in an island shape by the trench gate TG and the drift layer 2.
End portions of the base regions 21 adjacent to each other with the trench gate TG interposed therebetween (joint surface with the drift layer 2) are provided so as to be aligned in the X-plane direction.
The emitter region 61 is a high-concentration n-type (n + -type) impurity region provided on the surface of the base region 21 adjacent to the trench 31 (trench gate TG). The emitter region 61 exists as an island-like region provided inside the base region 21.
Body region 71 is a high-concentration p-type (p + -type) impurity region provided between adjacent emitter regions 61 on the surface of base region 21.
Another gate insulating film 42 (not shown in FIG. 1A) is provided on the drift layer 2 between the base regions 21 adjacent in the Y direction. The other gate insulating film 42 overlaps with the end portions of both adjacent base regions 41 and covers up to the end portions of the emitter regions 61 provided in the respective base regions 21.
The other gate electrode 52 is provided on the other gate insulating film 42. The other gate insulating film 42 and the other gate electrode 52 constitute a planar gate PG. The planar gate PG constitutes the planar cell 12 of the IGBT 10A together with the base region 21, the emitter region 61, and the body region 71 at both ends.
Although a part is omitted in FIG. 1, with reference to FIG. 1B, another gate electrode 52 continuously extends in the X direction orthogonal to the Y direction on the surface of the substrate. The other gate electrode 52 is also provided on the trench gate TG, but the other gate insulating film 42 is removed at least on the gate electrode 51 to provide a contact hole CH ′. That is, in the region where the gate electrode 51 and the other gate electrode 52 intersect, these are overlapped and connected via the contact hole CH ′. The other gate electrode 52 extends in the Y direction on the gate electrode 51 and is connected thereto.
As described above, in the present embodiment, the other gate electrode 52 continuously extends in the X direction, but the planar gate PG is provided only on the base region 21 adjacent in the Y direction.
An interlayer insulating film 3 is provided so as to cover the planar gate PG and the trench gate TG. The interlayer insulating film 3 is provided with a contact hole CH (the second region r2 in FIG. 1A and a broken line in the third region r3) in which the emitter region 61 and the body region 71 are exposed in an island shape. The pattern in plan view is a lattice pattern.
The gate electrode 51 and the other gate electrode 52 are formed so as to be connected to the gate routing wiring 8 formed around the IGBT 10A. Thereby, the gate electrode 51 and the other gate electrode 52 are controlled according to the signal of the gate routing wiring 8. The guard ring 6 which is a p + type impurity region is a region surrounded by the gate routing wiring 8 and is formed around the substrate.
FIG. 2 is a cross-sectional view taken along the line aa in FIG.
A plurality of trench gates TG are provided on the surface of the drift layer 2 so as to be separated from each other. The emitter region 61 is provided on both sides adjacent to the trench gate TG, and the body region 71 is provided between the adjacent emitter regions 61. The depth of the base region 21 is shallower than the bottom of the trench 31, the depth of the body region 71 is shallower than the base region 21, and the depth of the emitter region 61 is shallower than the body region 71.
The trench gate TG and the base region 21, the emitter region 61, and the body region 71 sandwiched between the trench gates TG constitute the trench cell 11 of the IGBT 10A.
Another gate insulating film 42 is provided on the surface of the drift layer 2, and a part thereof is removed so that the gate electrode 51, the emitter region 61, and the body region 71 are exposed. The other gate electrode 52 is patterned so as to overlap with the gate electrode 51 and is in contact with the gate electrode 51 through the contact hole CH ′ provided in the other gate insulating film 42. Interlayer insulating film 3 is provided on another gate electrode 52, and contact hole CH is provided so that emitter region 61 and body region 71 are exposed.
The emitter electrode 4 is formed in a wide area so as to cover all the emitter regions 61. The emitter electrode 4 is in contact with the emitter region 61 and the body region 71 through a contact hole CH provided in the interlayer insulating film 3. A collector electrode 5 is provided on the back surface of the p ++ type semiconductor layer 1.
Although illustration is omitted here, the guard ring 6 is formed to be deeper than the base region 21 around the IGBT 10A. The gate routing wiring 8 is formed so that the upper and lower sides thereof are sandwiched between the interlayer insulating films 3 around the IGBT 10A.
FIG. 3 is a cross-sectional view taken along line bb in FIG.
A plurality of base regions 21 are formed separately from each other. The body region 71 is formed so as to be positioned at the center on the surface of the base region 21. The emitter region 61 is provided outside the body region 71 so as to surround it.
Another gate insulating film 42 is provided on the surface of the drift layer 2 between the adjacent base regions 21. Another gate insulating film 42 is provided so as to cover the base region 21 and reach the end of the emitter region 61. Thereby, the emitter electrode 4 and the drift layer 2 are insulated.
Another gate electrode 52 is provided on the other gate insulating film 42 to constitute a planar gate PG.
An interlayer insulating film 3 is provided on the planar gate PG, and a contact hole CH in which the emitter region 61 and the body region 71 are exposed is provided in the interlayer insulating film 3. The emitter electrode 4 is formed in a wide area so as to cover all the emitter regions 61. Then, the emitter region 61 and the body region 71 are contacted through a contact hole CH provided in the interlayer insulating film 3.
The planar gate PG, the base region 21, the emitter region 61, and the body region 71 at both ends thereof constitute the planar cell 12 of the IGBT 10A.
FIG. 4 is a cross-sectional view taken along the line cc of FIG.
On the surface of the drift layer 2, a plurality of trench gates TG are provided apart from each other, and the base region 21, the emitter region 61, and the body region 71 are not formed in this cross section.
Another gate insulating film 42 is provided on the surface of the drift layer 2 between the trench gates TG, and another gate electrode 52 is provided on the trench gate TG and the drift layer 2. The other gate electrode 52 is in contact with the gate electrode 51 through the contact hole CH ′ provided in the other gate insulating film 42.
Interlayer insulating film 3 is provided to cover all other gate electrodes 52, and emitter electrode 4 is provided thereon. The emitter electrode 4 is insulated from the drift layer 2 in this cross section.
FIG. 5 is a cross-sectional view taken along the line dd in FIG.
In this cross section, the base region 21, the emitter region 61, and the body region 71 are not formed. On the other hand, the gate electrode 51 is formed so that one end and the other end thereof are connected to a gate routing wiring (not shown). Thereby, the gate electrode 51 is controlled according to the signal of the gate routing wiring.
The other gate electrode 52 provided on the surface of the drift layer 2 overlaps with and is connected to the gate electrode 51 in this cross section. The other gate electrode 52 is also formed so that one end and the other end thereof are connected to the gate routing wiring, and is controlled according to the signal of the gate routing wiring.
Interlayer insulating film 3 is provided on another gate electrode 52, and emitter electrode 4 is provided thereon.
Below, the effect | action by the said structure is demonstrated.
Referring to FIG. 2, when IGBT 10A is on, that is, when emitter electrode 4 is connected to ground and a positive voltage is applied to collector electrode 5, the pn junction consisting of drift layer 2 and base region 21 is Reverse bias. In this state, when a positive voltage equal to or higher than the threshold value is applied to the gate electrode 51 between the emitter electrode 4, an n-type inverted channel is formed in the drift layer 2 along the gate electrode 51. Then, electrons are injected from the emitter region 61 into the drift layer 2 through the channel. Electrons move using the drift layer 2 below the base region 21 as a path, mainly as indicated by arrows. As a result, holes are injected from the collector layer 1 into the drift layer 2, conductivity modulation occurs in the drift layer 2, and the resistance of the drift layer 2 decreases.
The base region 21 is connected to the emitter electrode 4, and holes injected into the drift layer 2 are discharged to the emitter electrode 4 through the nearest base region 21 that is a p-type impurity region.
At this time, referring to the cross section taken along the line bb (FIG. 3), there is another gate between the emitter electrode 4 and the drift layer 2 (hereinafter referred to as the storage portion HA) between the base regions 21 indicated by the broken line. Since the insulating film 42, the other gate electrode 52, and the interlayer insulating film 3 are formed, holes are not discharged from the drift layer 2 between the base regions 21.
Also, in the cross section along the line cc (FIG. 4), there is no path through which holes are discharged because the base region 21 is not disposed. That is, since the hole discharge path is limited to only the base region 21 (FIG. 2) separated in an island shape, the discharge of holes to the emitter electrode 4 is suppressed, and in the drift layer 2 serving as the storage portion HA. The hole accumulation effect can be enhanced.
Therefore, in the present embodiment, in the ON state of the IGBT 10A, holes are easily accumulated in the accumulating portion HA, and holes are not easily discharged from the emitter electrode 4 (a hole discharge path is limited). The effect is good and the saturation voltage can be reduced.
In this embodiment, the base region 21 is separated by the trench gate TG and the drift layer 2 and provided in an island shape, and the surface of the drift layer 2 where the base region 21 is not disposed is insulated from the emitter electrode 4. For example, in the cross section of FIG. 3, holes may move between adjacent base regions 21, but in other regions, the holes move between one base region 21 and another base region 21, thereby forming an emitter electrode. There is no route discharged to 4. That is, since the hole discharge path is limited to the island-shaped base region 21, holes can be stored well.
Furthermore, in this embodiment, an electron supply source can be secured by the planar cell 12.
This will be described with reference to FIGS. In the cross section taken along the line aa (FIG. 2), when the IGBT 10A is turned on, a channel is formed in the trench cell 11 and electrons are injected into the drift layer 2. At the same time, in the cross section taken along the line bb (FIG. 3), the base regions 21 at both ends of the planar gate PG are also inverted to the n-type to form a channel. Then, electrons are injected from the emitter region 61 into the drift layer 2 through the channel (arrow). That is, a large amount of electrons can be supplied even in the drift layer 2 in which the base region 21 is not disposed.
The base region 21 serving as a hole discharge path has a higher hole accumulation effect when the distance is longer. However, separating the base regions 21 reduces the region operating as the trench cell 11. However, by arranging the planar cell 12 in a region that does not operate as the trench cell 11, an electron supply source can be secured and a decrease in cell density can be suppressed.
Thereby, it is possible to reduce channel resistance and suppress a decrease in current density while enhancing the hole accumulation effect.
A second embodiment of the present invention will be described with reference to FIGS. FIG. 6 is a diagram illustrating a part of the IGBT 10B according to the second embodiment. FIG. 6A is a plan view, and FIG. 6B is a part of the first region r1 in FIG. 6A. It is a perspective sectional view. Further, the illustration of the second region r2, the third region r3, and the fourth region r4 in FIG. 1A is the same as that in FIG.
7 is a cross-sectional view taken along the line c′-c ′ in FIG. 6, and FIG. 8 is a cross-sectional view taken along the line d′-d ′ in FIG. 6.
With reference to FIG. 6, in the present embodiment, the trench gate TG is separated into a plurality by the drift layer 2 in the Y direction. Another gate insulating film 42 (not shown in FIG. 6A) extends on the surface of the drift layer 2 between the separated trench gates TG. Referring to FIG. 6B, the other gate electrode 52 overlaps with the gate electrode 51 at both ends, and extends on the gate electrode 51 in the Y direction. The other gate insulating film 42 is not provided in the region where the other gate electrode 52 and the gate electrode 51 overlap. That is, the other gate electrode 52 and the gate electrode 51 are electrically connected through the contact hole CH ′ provided in the other gate insulating film 42. Since the configuration other than this is the same as that of the first embodiment, the description thereof is omitted.
Similarly to the first embodiment, the end portions (joint surfaces with the drift layer 2) of the base regions 21 adjacent to each other across the trench gate TG are provided so as to be aligned in the X plane direction. In this embodiment, the end of the trench 31 is provided so as to be aligned with the end of the base region 21 in the X direction. A gate insulating film 41 is provided on the inner wall of the trench 31 and a gate electrode 51 is embedded. Between the trench gate TG and the base region 21 adjacent in the Y direction, the drift layer 2 extends in the X direction.
With reference to FIG. 7, a cross section taken along line c′-c ′ will be described. This cross section corresponds to a cross section taken along the line cc (FIG. 4) in the first embodiment.
In this cross section, the trench 31 is not provided in the drift layer 2. Another gate insulating film 42 is provided on the surface of the drift layer 2. The other gate insulating film 42 extends continuously in the X direction.
With reference to FIG. 8, the d'-d 'line cross section is demonstrated. This cross section corresponds to a cross section taken along the line dd (FIG. 5) in the first embodiment.
In this cross section, the drift layer 2 is provided between adjacent trench gates TG, and the base region 21, the emitter region 61, and the body region 71 are not provided. The gate electrode 51 is connected to the other gate electrode 52 through the contact hole CH ′ provided in the other gate insulating film 42.
That is, since the other gate insulating film 42, the other gate electrode 52, and the interlayer insulating film 3 are formed between the emitter electrode 4 and the drift layer 2 serving as the storage portion HA, holes are transferred to the base region. It is not discharged from the drift layer 2 between 21. For this reason, the effect of accumulating holes in the drift layer 2 serving as the accumulating portion HA can be enhanced.
Since the other configuration is the same as that of the first embodiment, the description thereof is omitted. The operation of the IGBT 10B according to the second embodiment is the same as the operation of the IGBT 10A according to the first embodiment, and thus the description thereof is omitted.
In the second embodiment, the gate capacitance (input capacitance) can be reduced as compared with the first embodiment. Comparing FIG. 8 with FIG. 5 of the first embodiment, in the first embodiment, since the base region 21 is not provided, the trench gate TG is formed in the region where the transistor operation is not performed (inside the one-dot chain line). ing. For this reason, when a gate potential is applied to the gate electrode 51, a gate capacitance is generated although it does not contribute to the transistor operation.
On the other hand, in the second embodiment (FIG. 8), the trench gate TG is omitted in a region where the base region 21 is not disposed (region not contributing to transistor operation: within a one-dot chain line). Thereby, an increase in useless gate capacity can be suppressed.
FIG. 9 is a view showing the IGBT 10C of the third embodiment, and is a cross-sectional view corresponding to the line bb of FIG.
The other gate electrode 52 of the planar gate PG may be divided into a plurality of parts by the separation groove S. Thereby, an increase in gate capacitance (input capacitance) can be suppressed below the isolation trench S. Increasing the distance between two base regions 21 adjacent in the Y direction is advantageous for the hole accumulation effect in the accumulation portion HA. On the other hand, the width of the other gate electrode 52 is also widened, which causes an increase in gate capacitance in the central portion that does not overlap with the base region 21. Therefore, by providing the isolation trench S in the central portion that does not contribute to channel formation, an increase in gate capacitance can be suppressed.
In this case, the other separated gate electrodes 521 and 522 are covered with one interlayer insulating film 3 and are connected, for example, at an inner portion of the gate routing wiring 8 of FIG.
Since the other configuration is the same as that of the first embodiment or the second embodiment, the description thereof is omitted.
In the above embodiment, the gate routing wiring 8 is arranged outside the guard ring 6. However, the present invention is not limited to this, and can be appropriately changed in design.
Moreover, even if it is the structure which reversed said embodiment and the conductivity type, it can implement similarly.
１　　　　ｐ＋型半導体層
２　　　　ｎ−型半導体層（ドリフト層）
３　　　　層間絶縁膜
４　　　　エミッタ電極
５　　　　コレクタ電極
１０Ａ~１０Ｃ　　　ＩＧＢＴ
１１　　　トレンチセル
１２　　　プレーナセル
２１　　　ベース領域
３１　　　トレンチ
４１　　　ゲート絶縁膜
４２　　　他のゲート絶縁膜
５１　　　ゲート電極
５２　　　他のゲート電極
６１　　　エミッタ領域
７１　　　ボディ領域
ＴＧ　　　トレンチゲート
ＰＧ　　　プレーナゲート 1 p + type semiconductor layer 2 n− type semiconductor layer (drift layer)
3 Interlayer insulation film 4 Emitter electrode 5 Collector electrode 10A to 10C IGBT
11 trench cell 12 planar cell 21 base region 31 trench 41 gate insulating film 42 other gate insulating film 51 gate electrode 52 other gate electrode 61 emitter region 71 body region TG trench gate PG planar gate

Claims (5)

  1. 　コレクタ領域となる一導電型半導体層と、
    　該一導電型半導体層上に設けられた逆導電型半導体層と、
    　前記逆導電型半導体層表面に設けられ該表面において第１方向に延在する複数のトレンチと、
    　該トレンチ内に絶縁膜を介して設けられたゲート電極と、
    　隣り合う前記トレンチ間の前記逆導電型半導体層表面に設けられ、前記第１方向において該逆導電型半導体層で互いに分離された一導電型のベース領域と、
    　該ベース領域表面で前記トレンチに隣接して設けられた逆導電型のエミッタ領域と、
    　前記第１方向において隣り合う前記ベース領域間の前記逆導電型半導体層上に設けられ前記両ベース領域の端部と重畳する他の絶縁膜と、
    　該他の絶縁膜上に設けられた他のゲート電極と、
    を具備することを特徴とする絶縁ゲート型バイポーラトランジスタ。     One conductivity type semiconductor layer to be a collector region;
    A reverse conductivity type semiconductor layer provided on the one conductivity type semiconductor layer;
    A plurality of trenches provided on the surface of the reverse conductivity type semiconductor layer and extending in the first direction on the surface;
    A gate electrode provided in the trench via an insulating film;
    A base region of one conductivity type provided on the surface of the opposite conductivity type semiconductor layer between adjacent trenches and separated from each other by the opposite conductivity type semiconductor layer in the first direction;
    An emitter region of a reverse conductivity type provided adjacent to the trench at the surface of the base region;
    Another insulating film provided on the opposite conductivity type semiconductor layer between the base regions adjacent in the first direction and overlapping with end portions of both the base regions;
    Another gate electrode provided on the other insulating film;
    An insulated gate bipolar transistor comprising:
  2. 　前記他のゲート電極は、前記ゲート電極上を前記第１方向に延在し、前記ゲート電極と接続することを特徴とする請求項１に記載の絶縁ゲート型バイポーラトランジスタ。 The insulated gate bipolar transistor according to claim 1, wherein the other gate electrode extends on the gate electrode in the first direction and is connected to the gate electrode.
  3. 　前記他のゲート電極は、前記表面において前記第１方向に直交する第２方向に連続して延在することを特徴とする請求項２に記載の絶縁ゲート型バイポーラトランジスタ。 3. The insulated gate bipolar transistor according to claim 2, wherein the other gate electrode continuously extends in a second direction orthogonal to the first direction on the surface.
  4. 　前記トレンチは、前記第１方向において前記逆導電型半導体層で複数に分離されることを特徴とする請求項３に記載の絶縁ゲート型バイポーラトランジスタ。 4. The insulated gate bipolar transistor according to claim 3, wherein the trench is separated into a plurality by the reverse conductivity type semiconductor layer in the first direction.
  5. 　前記第２方向において前記トレンチの端部と前記ベース領域の端部が揃うことを特徴とする請求項４に記載の絶縁ゲート型バイポーラトランジスタ。 5. The insulated gate bipolar transistor according to claim 4, wherein an end portion of the trench and an end portion of the base region are aligned in the second direction.
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