WO2011117162A1

WO2011117162A1 - Optoelectronic sensor and method for detecting impinging-light attribute

Info

Publication number: WO2011117162A1
Application number: PCT/EP2011/054175
Authority: WO
Inventors: Michael Franke
Original assignee: Iee International Electronics & Engineering S.A.
Priority date: 2010-03-25
Filing date: 2011-03-21
Publication date: 2011-09-29

Abstract

For detecting an attribute (e.g. intensity or phase of modulation) of light impinging on a photosensitive region of an optoelectronic sensor, the following steps are carried out: ⋅ accumulating light-induced charge in a storage node; ⋅ detecting whether an amount of charge accumulated in the storage node exceeds a threshold; ⋅ if the amount of accumulated charge exceeds the threshold, withdrawing a predefined quantity of the accumulated charge from the storage node; ⋅ incrementing a counter each time the predefined quantity of the accumulated charge is withdrawn from the storage node, so as to obtain a count; and ⋅ outputting a signal indicative of the attribute of light based upon the count.

Description

OPTOELECTRONIC SENSOR AND METHOD FOR DETECTING IMPINGING-

LIGHT ATTRIBUTE

Field of the Invention

[0001 ] The present invention generally relates to sensors that perform "light integration" (i.e. accumulation or integration of light-induced charge) over a certain time and more specifically to time-of-flight (TOF) sensors.

Technical Background

[0002] Systems for creating a 3-D representation of a given portion of space have a variety of potential applications in many different fields. Examples are automotive sensor technology (e.g. vehicle occupant detection and classification), robotic sensor technology (e.g. object identification) or safety engineering (e.g. plant monitoring) to name only a few. As opposed to conventional 2-D imaging, a 3-D imaging system requires depth information about the target scene. In other words, the distances between one or more observed objects and an optical receiver of the system need to be determined. A well-known approach for distance measurement, which is used e.g. in radar applications, consists in timing the interval between emission and echo- return of a measurement signal. This so called time-of-flight (TOF) approach is based on the principle that, for a signal with known propagation speed in a given medium, the distance to be measured is given by the product of the propagation speed and the time the signal spends to travel back and forth.

[0003] In case of optical imaging systems, the measurement signal consists of light waves. For the purposes of the present description, the term "light" is to be understood as including visible, infrared (IR) and ultraviolet (UV) light.

[0004] Distance measurement by means of light waves generally requires varying the intensity of the emitted light in time. The TOF method can e.g. be implemented using the phase-shift technique or the pulse technique. With the phase-shift technique, the amplitude of the emitted light is periodically modulated (e.g. by sinusoidal modulation) and the phase of the modulation at emission is compared to the phase of the modulation at reception. With the pulse technique, light is emitted in discrete pulses without the requirement of periodicity. In phase-shift measurements, the modulation period is typically in the order of twice the difference between the maximum measurement distance and the minimum measurement distance divided by the velocity of light. In this approach, the propagation time interval is determined as phase difference by means of a phase comparison between the emitted and the received light signal. Such phase comparison requires synchronization of the demodulation signal with the emitted light signal. Due to the high propagation speed given by the velocity of light, a fundamental difficulty encountered in distance measurements based on the pulse technique or the phase-shift technique resides in the required temporal resolution of the measurement device. In fact, a spatial resolution in the order of centimetres requires a temporal resolution in the order of 10^"11 seconds (10 ps). The principles of range imaging based upon time-of-f light measurements are described in detail in EP 1 152 261 A1 (to Lange and Seitz) and WO 98/10255 (to Schwarte). A more detailed description of the technique can be found in Robert Lange's doctoral thesis "3D Time-of-Flight Distance Measurement with Custom Sol id-State Image Sensors in CMOS/CCD-Technology" (Department of Electrical Engineering and Computer Science at University of Siegen).

[0005] In TOF sensors, one typically collects a lot of (unmodulated) background light on top of the modulated light that carries the distance information. The useful signal thus may represent only a very small part of the total signal. Since the storage nodes for storing the light-induced charge have limited capacity, it is important to avoid that the storage nodes saturate with charge induced by background light or at least detect such an event if it cannot be avoided.

[0006] The high amount of background light is critical, since background light may drive the optoelectronic sensor into saturation. A method of operating a time-of-flight imager pixel that allows detecting saturation is disclosed in WO 2007/014818 A1 .

[0007] As the capacity of the storage nodes is limited, if the background light is strong, one option is to keep the integration time short in order to not drive the sensor into saturation. Consequently, the amount of signal charge (i.e. charge stemming from the modulated part of the received light) is very low, which causes a bad signal- to-noise ratio. To overcome this issue, an alternative solution is to continuously subtract a current that is common for the different storages of one TOF sensor pixel. It is then important that the currents for the different storage nodes are equal. If they are not equal (if there is a mismatch), that introduces an error that cannot be separated from the signal charge. If small MOS transistors are used as current sources, the mismatch between the currents may be in the range of 10% or more. Assuming that the background charge is 10 times higher than the signal charge and the mismatch is 10%, the error signal introduced by removing background charge may have the same amplitude as the signal charge.

[0008] Patent application WO 201 1/020629 describes how the accumulated DC (i.e. unmodulated) background charge can be subtracted during integration. The device has high channel matching. But the limiting factor can then be the demodulator. If its channel matching is bad, the effect of the idea is away.

Object of the invention

[0009] The object of the present invention is to provide an improved method and device for converting light impinging on a photosensitive area into an electrical signal.

General description of the invention

[0010] A first aspect of the present invention concerns a method of detecting an attribute (e.g. intensity or phase of modulation) of light impinging on a photosensitive region of an optoelectronic sensor. The method comprises the steps of

o accumulating light-induced charge in a storage node;

o detecting whether an amount of charge accumulated in the storage node exceeds a threshold;

o if the amount of accumulated charge exceeds the threshold, withdrawing a predefined quantity of the accumulated charge from the storage node;

o incrementing a counter each time the predefined quantity of the accumulated charge is withdrawn from the storage node, so as to obtain a count; and o outputting a signal indicative of the attribute of light based upon the count. [001 1 ] As will be appreciated, the risk of saturation of the storage node is significantly reduced because the predefined quantity ("qsub") of charge is withdrawn from the storage node each time it is detected that the charge already accumulated therein exceeds a threshold. The threshold is preferably chosen with sufficient safety margin below the filling limit of the storage node to avoid that the storage node fill up entirely between two subsequent subtraction events. The safety margin thus depends on "qsub". If the charge increases by more than the amount "qsub" between subsequent checks, the accumulated charge progressively "runs away", and the storage node risks to saturate. Assuming that "qsub" and the repetition rate of the checks are chosen so as to avoid that situation, the threshold should be lower than the filing limit of the storage node minus "qsub". This method also helps preventing overflow due to leakage (i.e. at high temperatures).

[0012] The invention is not bound to a specific demodulator or demodulation method. It is also useful for sensors other than those operating according to the TOF principle, as long as these sensors perform integration of light over time.

[0013] In order not to lose track of the total charge withdrawn from the storage node, the counter counts the subtraction events. The total charge withdrawn may be retrieved by calculating C ^* qsub, where C represents the count, i.e. the number of substraction events, and qsub represents the predefined amount of charge that is withdrawn from the storage node at each subtraction event.

[0014] According to a variant of the method, light-induced charge is also accumulated in a second storage node. The photoelectronic sensor may e.g. be configured in such a way that light-induced charge is accumulated alternately in a first and a second storage node. This may e.g. be the case in a so-called demodulator pixel (or photonic mixer device) of a TOF-detector (see e.g. WO 98/10255 for reference). In this variant of the invention, it is detected whether a second amount of charge accumulated in the second storage node exceeds a second threshold (which may be the same as or different from the above-mentioned first threshold). If the second amount of accumulated charge exceeds the second threshold, the predefined quantity of the accumulated charge is withdrawn from the second storage node. The counter is incremented each time the predefined quantity of the accumulated charge is withdrawn from the first storage node and decremented each time the predefined quantity of the accumulated charge is withdrawn from the second storage node. The count thus obtained is a differential count. As those skilled will appreciate, the common mode (or common background light) of the two storage nodes is eliminated in this variant of the invention. Accordingly, this variant is especially useful, where the common mode is not used in the later calculations.

[0015] Preferably, the residual amount of charge remaining in the storage node (after the predefined quantity of the accumulated charge has been withdrawn from the storage node one or more times or after it has been determined one or more times that the threshold has not been exceeded) is detected. The signal indicative of the attribute of light is then preferably output based upon the count and the residual amount of charge. The total amount of charge accumulated in the storage node is then equal to C ^* qsub + qres, where qres is the residual amount of charge.

[0016] Those skilled will note that there may be applications, where the residual amount of charge may simply be neglected.

[0017] If the counter is a digital counter, it already carries out a great part of an analog-to-digital conversion. The residual amount of charge may be converted separately. If necessary, the computation of C ^* qsub + qres may be effected in digital domain.

[0018] A second aspect of the invention concerns an optoelectronic sensor for detecting an attribute of light impinging thereon in accordance with the above- described method. Such optoelectronic sensor comprises

o a photosensitive region for generating a charge in response to light impinging on the region; o a storage node for accumulating the light-induced charge;

o a charge monitor operatively connected to the storage node for detecting whether an amount of charge accumulated in the storage node exceeds a threshold; o a dumping circuit responsive to the charge monitor for withdrawing a predefined quantity of the accumulated charge from the storage node if the amount of accumulated charge exceeds the threshold ;

o a counter connected to the charge monitor and/or the dumping circuit so as to provide a count incremented each time the predefined quantity of the accumulated charge is withdrawn from the storage node; and an output circuit connected to the counter for outputting an output signal indicative of the attribute of light based upon the count.

[0019] Preferably, the charge monitor comprises a comparator for comparing the amount of accumulated charge with the threshold.

[0020] The charge monitor also preferably comprises a buffer circuit with (very) high input impedance (e.g. a capacitively fed-back amplifier) between the storage node and the comparator in order to avoid that part of the accumulated charge leaks away across the comparator.

[0021 ] The optoelectronic sensor may further comprise

o a second storage node for accumulating light-induced charge;

o a second charge monitor operatively connected to the second storage node for detecting whether a second amount of charge accumulated in the second storage node exceeds a second threshold;

o a second dumping circuit responsive to the second charge monitor for withdrawing the predefined quantity of charge from the second storage node if the second amount of accumulated charge exceeds the second threshold.

[0022] A second counter may be connected to the second charge monitor and/or the second dumping circuit so as to provide a second count incremented each time the predefined quantity of the accumulated charge is withdrawn from the second storage node. Both counts are then preferably taken into account by the output circuit to output a signal indicative of the attribute of light.

[0023] Alternatively, the counter is a differential counter that increments its count each time the accumulated charge is withdrawn from the first storage node and decrements its count each time the predefined quantity of the accumulated charge is withdrawn from the second storage node.

[0024] Preferably an analog-to-digital converter is provided for converting the residual amount of charge remaining in the storage node (after the predefined quantity of the accumulated charge has been withdrawn from the storage node one or more times or after it has been determined one or more times that the threshold has not been exceeded) into a digital residual charge signal. The output circuit is in this case preferably connected to the analog-to-digital converter so as to be able to output its output signal based upon the count as well as the digital residual charge signal from the analog-to-digital converter.

[0025] As those skilled will appreciate, in a structure comprising a plurality of photosensitive regions (e.g. an imager chip), some components may be used in common for different photosensitive regions.

[0026] A preferred embodiment of the present invention relates to an imager chip that comprises a group of sensor pixels, each sensor pixel including at least one photosensitive region for generating a charge in response to light impinging on the region, and at least one storage node for accumulating the light-induced charge. The imager chip further comprises a group of counters, each one of the group of counters being associated with a sensor pixel. The imager chip could have one charge monitor and one dumping circuit per photosensitive region, in which case one would be faced with a mere juxtaposition of the above-described optoelectronic sensors. Preferably, the imager chip comprises one read-out circuit associated with the entire group of sensor pixels, the read-out circuit including a charge monitor operatively connectable to the storage node of each sensor pixel for detecting whether an amount of charge accumulated in the storage node exceeds a threshold and a dumping circuit responsive to the charge monitor for withdrawing a predefined quantity of the accumulated charge from the storage node if the amount of accumulated charge exceeds the threshold. The imager chip also comprises a controller (e.g. a microcontroller, an application-specific integrated circuit, a field-programmable gate array or the like) configured to sequentially interface each one of the group of sensor pixels with its associated counter via the read-out circuit in such a way that a count in the counter is incremented each time the predefined quantity of the accumulated charge is withdrawn from the storage node of the associated sensor pixel. An output circuit connected to the group of counters is provided for outputting a signal indicative of the attribute of light at each of the sensor pixels based upon the counts of the group of counters. Preferably each storage node of each pixel has its own charge dumping circuit or at least a short connection to its own special output of the charge dumping circuit. If each of the sensor pixels comprises more than one storage node; then one counter is required per storage node, or, in case of a differential counter, for each pair of storage nodes.

[0027] Typically the sensor pixels of the group of sensor pixels are arranged in a row or a column. The imager chip may comprise a plurality of groups of sensor pixels. Each group then preferably comprises its own read-out circuit. The sensor pixels of each group are preferably arranged in a row or a column.

[0028] The predefined quantity of the accumulated charge is preferably generated by a charge source. Examples of possible charge sources are detailed in document WO 201 1/020629 A1 , which is herewith included herein by reference in its entirety for those jurisdictions that permit such inclusion by reference, in particular in paragraphs [0045], [0046]-[0049], [0051 ]-[0053] and the corresponding drawings. Other devices like MOS transistors, operated as pulsed current sources, are considered less suitable due to low dynamic output impedance.

[0029] The invention enables the construction of a 3D time-of-flight sensor with improved sun robustness and leakage robustness.

[0030] The invention is not bound to a specific demodulator or demodulation method. It is further useful for sensors of others than TOF, if signals are integrated over time.

Short description of the drawings

[0031 ] The present invention will be more apparent from the following description of several not limiting embodiments with reference to the attached drawings, wherein:

Fig. 1 illustrates the overall timing for one pixel; Fig. 2 is a block diagram of a sensor pixel architecture according to a first example of the invention;

Fig. 3 is the block diagram of Fig. 2, where the pixel and sensor chip boundaries have been indicated

Fig. 4 shows a block diagram for counter overflow pre-detection and auto- integration-stop;

Fig. 5 illustrates the charge accumulated in a storage node as a function of time;

Fig. 6 illustrates an example of a matrix of sensor pixels configured and operating according to the invention;

Fig. 7 is a block diagram of a first sensor pixel architecture usable in the matrix of sensor pixels of Fig. 6;

Fig. 8 is a block diagram of a second sensor pixel architecture usable in the matrix of sensor pixels of Fig. 6.

Detailed description with respect to the figures

[0032] In the following, a sensor pixel will be discussed that comprises at least one storage nodes, in which charge carriers generated in the photo-sensitive region of the pixel are drawn into. During charge integration (accumulation) time, the storage fill content is checked for each raw signal (i.e. for each storage node) separately. If the fill content exceeds a given threshold, a defined quantity of charge is subtracted from the storage considered node. The number of subtractions is counted separately for each storage node. After integration the count is used together with the rest fill content of the storage node as the complete measure of the integrated signal at the storage considered. If the counting is done in a digital way, the count can be used as a first important part of an AD-converted representation of the accumulated signal. The rest fill content may be AD-converted in addition to get a higher digital resolution or it may be ignored.

[0033] Each sensor pixel has at least one storage node, at which the signal charge is accumulated over time (see Fig. 1 ). The accumulation of charge happens mainly during integration - at the start of integration (= end of reset) the photo generated charge start to be accumulated at the storage node. This is at time '0' of Fig. 5. During integration, the charge "qsub" is subtracted each time it is determined that the accumulated charge exceeds the predefined threshold. This is illustrated in Fig. 5 by the 'down jumps' of the charge on the storage node - each down jump corresponding to one subtraction event. When the integration stops, the accumulation of photo generated charge stops accordingly, but only in a rough way of consideration. In reality, some charge is still generated due to parasitic effects. Between stop of 'integration' and 'read out' (read out means here especially the conversion of the residual charge; in addition it means also the output of the counts and the AD converted residual charges via chip boundaries, but this is not time-critical because these values are in digital domain and do not suffer from parasitic accumulation or leakage), the sensor pixel may have to wait until the ADC is done with previous conversions. This phase is illustrated in Fig. 1 as the 'waitO' phase. The start time of 'read out' (='tfinal') in Fig. 1 is the same as the one illustrated in Fig. 5. In Fig. 5, the 'waitO' phase is not shown (or it has zero duration). In the 'waitO' phase the charge increase slope would be substantially smaller than in the 'integration' phase. In the present context, "parasitic accumulation" means generation and accumulation of charge due to parasitic effects (e.g. if the electronic shutter does not entirely isolate the storage node). "Leakage" occurs when a parasitic highly resistive connection of the storage node e.g. to ground or supply allows a small current to flow, which can charge or discharge the storage node even in the absence of light.

[0034] During accumulation time, the storage fill content, hereinafter noted "Q(t)", is compared to a threshold value. When it exceeds the threshold value, a defined charge quantity "qsub" is subtracted from the storage. This temporarily reduces the storage fill content "Q(t)".

[0035] Because of the parasitic accumulation and the leakage effects, it can be helpful to keep the check-and-subtraction-procedure running for those sensor pixels that are in 'waitO' phase, although other pixels may already be in read out phase.

[0036] The number of executed charge subtractions is counted. The count is hereinafter denoted as "N(t)". [0037] When reading out the storage at time "tfinal", the overall accumulated charge "Qfinal" of the storage node can be calculated by "Qfinal = N(tfinal) ^* qsub + Q(tfinal)".

[0038] N(t) can be stored in an analog storage. This can be, for example, a capacitance, to which a defined quantity of charge is added each time the count is increased. N(t) can also be stored in a digital storage - a digital counter for example. N(t) can also be stored in a multistage analogue storage (including one stage storing a signal according to the most significant bits of the count, a second stage storing a signal according to the less significant bits, etc. and an n-th stage storing a signal according to the least significant bits). N(t) can also be stored in a storage, which is a mixture of the upper (e.g. storing the most significant bits with more precision and robustness in a digital counting stage, the least significant bits in a more layout spacing analogue storage stage).

[0039] When N(t) is stored in a digital representation, it can directly be used as the first step of a digital representation of "Qfinal".

[0040] If differential signals of two storages shall be processed, it is possible to use an up-and-down counter "Ndiff(t)", where subtractions in the first storage are counted upwards and subtractions in the second storage are counted downwards ("Ndiff(t) = N1 (t) - N2(t)"). This is mainly useful for signals with expected strong DC content.

[0041 ] In the case of a differential counter, it can be useful to store the common mode of the differential signal (maybe with less resolution). The common mode can serve as a measure for the average of the overall captured charge. From this, the expected noise level (indicator of value reliability) of one pixel signal can be estimated. Furthermore, it may serve as a basis to calculate a grayscale intensity image.

[0042] "Q(tfinal)" can be converted by an AD converter.

[0043] If the predominant part of "Qfinal" is already converted to "N(tfinal)", the accuracy of "Q(tfinal)" has little influence on the accuracy of "Qfinal". Depending on the requirements, the accuracy of "Q(tfinal)" may be low or the AD conversion of "Q(tfinal)" may even be omitted. These considerations can help to make the ADC easier or omit it. They can further help to reduce the time for sensor read out because of faster or omitted final conversion.

[0044] The amount of charge "qsub" withdrawn from the storage node is considered constant during an integration interval. If "qsub" is subject to variations (e.g. due to external parameters like temperature, pressure, ageing, etc.), it may be measured from time to time, in order to reconstruct the amount of total accumulated charge. For the case that "qsub" is required for reconstruction, it can be measured repeatedly in the application. If there are no variations of "qsub" to be expected, one may determine "qsub" once after sensor fabrication and use that value for the entire lifetime of the sensor. There may be applications, which do not need any knowledge of the value of "qsub". In this case, the measuring "qsub" can be omitted.

a) Values that are measured during fabrication need to be stored in the hardware that belongs to the measured sensor chip.

b) Measurements in the application can be done for example for every single raw frame, for a complete set of raw frames (required i.e. to correct errors), once for several frame sets or after power on of the camera.

[0045] It may happen that the total amount of collected charge does not exceed the threshold set. In such case, no subtraction occurs ("N(tfinal)" = 0) and "qsub" is not required for reconstruction.

[0046] The amount of charge "qsub" preferably has low dependence on the storage fill content "Q(t)", since a measurement error will otherwise result. This requirement is fulfilled e.g. if "qsub" is provided by a charge source. As mentioned hereinabove, embodiments of such charge sources are described e.g. in document WO 201 1/020629.

[0047] Most 3D-TOF demodulators have a photosensitive area with at least two outputs (or signal paths), which are connected to corresponding storage nodes. These outputs shall be considered as channels here. Because the present method operates each channel independently from the others, high channel matching is not required, as would be the case for the method disclosed in WO 201 1/020629. This may enable the use of a charge source improved in terms of other parameters like size, speed or power dissipation. For example, each storage can have its own charge source. This can help to increase the operation speed, because the fill-and-output operation can happen at the same time in parallel for the channels. The used charge sources can have just one input and one output, so their size can be optimized more easily.

[0048] The channels of one pixel (inclusive demodulator, charge source and storage) may have mismatch to each other regarding offset, gain and nonlinearities. One technique to reduce these errors is the 4x4tap correction method (explained in EP1752793A1 ). The required functions can be implemented outside the chip, as a kind of post-processing of raw images.

[0049] Fig. 2 shows a block diagram of an example of an architecture to process the charge accumulated on one storage node.

a) The current "iinput(t)" represents the charge flowing into the storage node "pixel storage" considered. This current is reduced by the system feed back current "isub(t)" on the "Pixel storage" input node: "istore(t) = iinput(t) - isub(t)". b) The "Pixel storage" (i.e. the storage node) stores the charge "Q(t)" and gives rise to an output voltage "U(t)" reflecting the stored quantity of charge "Q(t)". "Q(t)" is the over time integrated charge from the current "istore(t)" starting from a storage reset at time "0" until the time "t". In simple embodiments, "Pixel storage" can be built by a capacitance, a parasitic capacitance, a capacitively fed back amplifier or something similar. c) A "Nondestructive read stage" generates an output "U'(t)" corresponding to "U(t)". It is required to enable checking of the storage fill content without destroying or influencing the stored charge. This functionality may be already included in the circuit representing the "Pixel storage"; for example, if the "Pixel storage" is provided as a capacitively fed back amplifier. The

"Nondestructive read stage" may be built by any kind of buffer, e.g. in a simple manner by a source follower stage.

d) A "Check stage" is connected to the "Nondestructive read stage" output "U'(t)".

It compares the measure "U'(t)" of the storage fill content with a predefined threshold "U'th". The "Check stage" can be provided as any kind of comparator circuit. If the storage fill content exceeds the given threshold at a time "t", a "Subtraction event" is started. The threshold "U'th" may also be adopted depending on storage position, time "t" related to overall timing or others to optimize the useable remaining storage fill quantity or to equalize the conditions between different storages (for instance, if the comparators in the check stage have different offsets due to fabrication tolerances, these offsets can be compensated by applying different thresholds). The event starts are represented in the figure by "c(t)". The signal "c(t)" which represents the (start of the) "Subtraction events", may be realized by a pulse or a rising or falling edge.

"c(t)" is connected to a "Charge Source Control" stage. This stage delivers the required control signals for the "Charge Source" in case of a "Subtraction event". The "Charge Source Control" stage can consist of a pattern generating circuit and controllable transfer gates. The pattern generating circuit generates the signal pattern required for the charge source to output the charge "qsub". It is preferably a digital circuit. The controllable transfer gates are controlled by the signal "c(t)", so that in the case of a "subtraction event" the generated signal pattern is passed through the transfer gates to the charge source. In the case of no "subtraction event" the transfer gates disconnect the charge source from the generated signal pattern. The pattern generating circuit may be shared for multiple storage channels. The transfer gates must be separate for each storage channel. The "Charge Source" generates as output a current "isub(t)", which is usually zero (when there is no subtraction event). In case of a "Subtraction event" "isub(t)" forms a short current pulse. The integral over time of one such current pulse is the charge quantity "qsub". The sign of "qsub" is inverse to the charge accumulated from "iinput(t)".

"c(t)" is connected to a "Count storage" (i.e. a counter), which counts the "Subtraction events" as "N(t)". The counter can e.g. be a capacitance, a digital counter, a multistage analogue storage. Because of "N(t)" is specific for each channel (each pair of channels for a differential counter), the "Count storage" must not be shared between pixel storage channels (or pair thereof, if the counter is a differential counter). g) An "ADC" is connected to "U'(t)" to convert it into a digital representation "s1 (t)". This is done after the end of signal integration (and after an optional wait phase), when "U'(t)" reflects the amount of residual charge on the storage node, in order to reconstruct the overall quantity of accumulated charge.

h) For reconstruction (e.g. the calculation of Qfinal = N(tfinal) ^* qsub + Q(tfinal) and of the light attribute to be detected) a "Reconstruction stage" (output circuit) is used. This reconstruction stage is preferably a digital circuit, because of s1 (t) and N(t) are preferably digital signals. The "Reconstruction stage" preferably implements at least one adder and a multiplier to achieve the above-mentioned calculation. The "Reconstruction stage" can be shared for all storage channels, if a serial reconstruction for all storage channels is sufficient for the timing requirements. Buffers may be used for electrical purposes to adopt driving capabilities to parasitic loads, especially at the connection to busses and at the chip border. The additional implementation of buffers and multiplexers can help to organize the share in a better way. In a preferable embodiment the "Reconstruction stage" is located outside the sensor chip. In that case it is helpful to have a multiplexer inside the chip to reduce the number of separate output channels. The "Reconstruction stage" can e.g. be implemented in a FPGA.

a) In case of a matrix of sensor pixels, some parts of the above-discussed components may be shared by some or all of the sensor pixels, e.g. to optimize the pixel size. Fig. 3 illustrates one option to locate functions outside the pixel.

[0050] For 4x4tap correction, each sensor pixel needs to have four channels (and thus four storage nodes), which accumulate charge during different phases, in particular 0°, 90°, 180° and 270°, of the modulation cycles. The charge accumulated in each storage node is then determined according to the present method. The charge values thus obtained represent sampling points of the demodulated light wave; one at 0°, one at 90°, one at 180°, one at 270°. Four Subframes are measured, where the clock of the illumination is shifted against the demodulators toggle gate control by 90° between the subframes. The 4x4tap correction takes those sampling points from the four subframes that belong to the 0° phase and sums them up to have one resulting value for the sampling point "0°". The same is done for the sampling points 90°, 180°, 270°. The four resulting values are now handled like four samples at 0°, 90°, 180° and 270°, respectively. The effect of the summing up is that each of the final samples contains a contribution of each of the channels. Differences between the channels are thus averaged out.

[0051 ] Four subframes are taken to build up one corrected image. Each of these subframes is captured with a specific phase shift of the illumination clock. To reduce the amount of chip read out for one corrected image, the combination of the different "N(tfinal)" per subframe can already be done inside the sensor chip: Channel exchange switches are inserted directly in front of the "Count Storage"; for each single subframe, the channel exchange switches are set to the state that belongs to the state of the 4x4tap-correction-subframe. By doing so, "N(tfinal)" needs to be read out just once for one corrected image. The idea behind is that the 4x4tap correction is a linear operation of the four different Qfinal, which belong to one pixel for each of the four subframes that are required for 4x4tap correction. Because Qfinal is a sum of two terms namely N(tfinal)^*qsub and Q(tfinal), the 4x4tap calculation can be carried out for these terms separately, and the combination (addition) of the separate results can be achieved in a second step. Furthermore, the 4x4tap calculation of "N(tfinal)^*qsub" can be done in two steps: firstly the 4x4tap calculation for all the different N(tfinal) and secondly the multiplication of the result with qsub.

[0052] If "Q(tfinal)" cannot be disregarded, it is possible to carry out the combination of the data of the four subframes already on the sensor chip. But if "Q(tfinal)" is combined in the analogue representation, it is more error sensitive and the required circuitry is challenging. Furthermore, problems with leakage could become more important.

[0053] Because each intra-pixel storage node is prevented from overflow due to the invention, the overall amount of accumulated charge is just limited by the maximum count of the counter. For many applications it will be possible to implement a counter that is large enough and that never saturates (within a given range of operating conditions). If that is not possible or sufficient for an application, overflow detection can be implemented for the counter.

[0054] Further it is possible to implement an "Auto-integration-stop", to prevent the counter from overflowing. Therefore an Overflow pre-detection" is preferably implemented as illustrated in Fig. 4: if one of the counters (0 to n) associated with a particular pixel, exceeds a threshold at an arbitrary time "tstop", no more subtraction is counted for that pixel. Whether the subtractions are counted or not, the subtraction events are preferably continued to prevent an overflow of the storage nodes into neighbouring pixels and storage nodes.

[0055] A pixel in the sense of the present document can also be a sub-pixel. For example it can be the group of channels that belong to one optical detector. In the case of a pixel that consists of two optical detectors, and each detector has its own demodulator with two outputs, then the pixel can be considered as a group of two sub-pixels, where each sub-pixel means one detector with its demodulator and the corresponding two output channels.

[0056] For post processing, i.e. for calibration, it can be of interest to know the absolute power of the incident modulated and background light that impinged on a pixel during the considered capture. To recalculate these information from the raw results, the integration time needs to be known. In the case of an "Auto-integration- stop" as described above, the integration time is known from "tstop". In this case "tstop" is stored during capture for each pixel.

[0057] Because it is possible to place the circuitry of "Auto-integration-stop" (see Fig. 4: "Count Gate", "Overflow Pre-Detection") outside the pixel, no further circuitry is required inside the pixel for storing the stop time "tstop".

[0058] Fig. 6 shows an imager chip including an n x m matrix of sensor pixels (only four sensor pixels are shown in order not to overload the drawing). Each sensor pixel includes a photosensitive region for generating a charge in response to light impinging thereon (not explicitly shown in Fig. 6) and two storage nodes (pins 1 and 3 in each pixel) wherein light-induced charge is accumulated. Each sensor pixel also includes a dumping circuit for withdrawing a predefined amount of charge from each storage node. As shown in Figs. 7 and 8, there may be one dumping circuit ("charge source control part B") for both storage nodes (Fig. 7) or one per storage node (Fig. 8). Turning again to Fig. 6, the imager chip also includes an n x m matrix of counters (count storages CS), each of which is associated with one of the sensor pixels. In fact, the sensor pixel in row i and column j of the sensor pixel matrix is associated with the counter in row i and column j of the counter matrix. To each column of sensor pixels belongs a read-out circuit, which comprises a first charge monitor (i.e. non-destructive read stage rd and check stage chk) operatively connectable to the first storage node (pin 1 ) of each sensor pixel of the corresponding column and a second charge monitor for operatively connectable to the second storage node (pin 3) of each sensor pixel of the corresponding column. Each readout circuit is connected to only one sensor pixel at a time. This will be explained in more detail with respect to Figs. 7 and 8 below. When connected to a sensor pixel, each read-out circuit checks whether the amount of charge accumulated in said storage node exceeds the predefined charge threshold (qth in Fig. 5). Each read-out circuit also comprises a dumping circuit control (ctl) connected with its input terminal to the check stage charge monitor and with its output to the dumping circuits of the sensor pixels.

[0059] The imager chip further comprises a controller (not shown in the figures), which is configured to sequentially interface, via the read-out circuit of a given column, each one of the sensor pixels of that column with its associated counter. The controller controls the sensor pixels and the counters via sensor-enable signal lines (Fig. 6: "en_1 ", "en_i") and counter-enable signal lines (Fig. 6: "ens_1 ", "ensj"). Each sensor-enable signal line is connected to all the sensor pixels of one row (at sensor pixel pin 6). Likewise, each counter-enable signal line is connected to all the counters of one row (at counter pin 6). The controller interfaces all the sensor pixels of a row i with their corresponding counters (in row i of the counter matrix) by outputting an "enable" signal on the i-th sensor-enable signal line and the i-th counter-enable signal line. At the same time, all the other sensor pixels and counters receive a "disable" signal. The controller applies the "enable" signal to one row after the other. When the last row is reached, the process restarts with the first row.

[0060] When the "enable" signal is applied to a sensor pixel: o The first and the second buffers (Figs. 7 and 8: nondestructive read stage part A) of the first and second storage node connect themselves to the check stage via the readout circuit (Figs.7 and 8: non-destructive read stage part B). As a consequence, the check stage checks whether the charge accumulated in the first and second storage node, respectively, exceeds the threshold (qth). The results of the comparisons are output by the check stage and passed to the sensor pixel via the dumping circuit control (Fig. 7 and 8: as signals c"1 (t) and c"2(t)). These signals thus indicate whether there is a need for a charge withdrawal in the sensor pixel.

o The one or more dumping circuits of the sensor pixel are switched responsive to the control signal applied by the dumping circuit controls on sensor pixel pins 2 and 4. This means that the one or more dumping circuits of that pixel will withdraw the predetermined amount of charge from the first and/or the second storage node when the signals (Figs. 7 and 8: c"1 (t) and c"2(t)) from the readout circuit so indicate.

[0061 ] Similarly, when the "enable" signal is applied to the corresponding counter, it is responsive to the signals output by the check stages of the charge monitors (i.e. signals c1 (t) and c2(t) in Figs. 7 and 8 applied to counter pins 7 and 9, respectively (see Fig. 6)). Depending on the counter implementation, each counter may keep a separate count for each storage node of its associated sensor pixel, or a differential count, etc. In the embodiment of Fig. 6, the counters are digital counters, so that their counts (Fig. 6: N1 (t) on counter pin 8 and N2(t) on counter pin 10) can directly be used by downstream digital circuits.

[0062] The imager chip also includes an ADC to convert the residual charges in each storage node into a digital signal (Fig. 6: s1 ) and a multiplexer, which is connected to the different counters to output the counts on a multiplexed signal (Fig. 6: N). A digital reconstruction stage (Fig. 6: Reco) finally recombines the different digital signals to retrieve the information searched. In Fig. 6, the reconstruction stage is drawn outside the chip boundary but there may be implementations wherein it is integrated on the chip. [0063] It should be noted that the sensor pixels are not totally disabled when the "disable" signal is applied to them (or when the "enable" signal is absent). While a sensor pixel is disconnected from (or not interacting with) the read-out circuit, it continues to accumulate charge in its storage nodes.

[0064] Figs. 6, 7 and 8 relate to the case of demodulation sensor pixels: light- induced charge is collected in the first or the second storage node of a sensor pixel depending on the phase of a (de)modulation signal applied on sensor pixel pin(s) 5 (Figs. 7 and 8: tg1 (t) and tg2(t)). Possible implementations of the photonic mixing structure can be found in the prior art (see e.g. the documents mentioned in the Technical Background section) and thus need not be discussed herein. The (de)modulation signal is typically derived from a modulated light source.

[0065] As an alternative to carrying out the charge subtraction events pixel-by-pixel (or row-by-row), as described hereinabove, a flag may be set for each storage node for which a charge subtraction is necessary. The controller may later (e.g. after having processed a plurality of rows or all the rows) initiate a common subtraction operation, in which those storage nodes (and only those) participate, for which the flag has been set. In other words, when the flag is not set for one or more of its storage nodes, the sensor pixel will ignore the signal triggering the subtraction operation in respect of these storage nodes.

[0066] An architecture alternative to that of Fig. 6 would be place the complete check-and-subtraction-loop into the sensor pixels. This has the advantage that less communication needs to be made over the matrix column wires. Therefore, such alternative architecture can be faster. The drawback is that more circuitry needs to be placed inside the sensor pixels, making it necessary to enlarge the sensor pixels or to reduce the light-sensitive area.

[0067] As those skilled will appreciate there is an interesting alternative to measuring the residual charge "Q(tfinal)" when integration is over. According to this alternative, the time of the last subtraction (Fig. 5: "tlastsub") is stored in a memory. As can easily be deduced from Fig. 5, the total charge Qtot accumulated until the time "tlastsub" may be calculated as: Qtot(tlastsub) = qth-qO + qsub^*(N(tlastsub)-1 ). To extrapolate Qtot to the time "tfinal", one may calculate: Qtot(tfinal) = Qtot(tlastsub) ^* tfinal / tlastsub. This calculation bases on the assumption that Qtot has a linear slope over time. The advantage of this method is that no conversion of "Q(tfinal)" is required, "tlastsub" and "tfinal" can easily be measured, e.g. using a digital timer. The disadvantage of this alternative is that the threshold "qth" needs to be arrived at at least once. This can require a long integration time.

[0068] While specific embodiments have been described in detail, those with ordinary skill in the art will appreciate that various modifications and alternatives to those details could be developed in light of the overall teachings of the disclosure. Accordingly, the particular arrangements disclosed are meant to be illustrative only and not limiting as to the scope of the invention, which is to be given the full breadth of the appended claims and any and all equivalents thereof.

Claims

1 . Method of detecting an attribute of light impinging on a photosensitive region of an optoelectronic sensor, said method comprising

accumulating light-induced charge in a storage node;

detecting whether an amount of charge accumulated in said storage node exceeds a threshold;

if said amount of accumulated charge exceeds said threshold, withdrawing a predefined quantity of said accumulated charge from said storage node; characterised by incrementing a counter each time said predefined quantity of said accumulated charge is withdrawn from said storage node, so as to obtain a count; and outputting a signal indicative of said attribute of light based upon said count.

2. Method as claimed in claim 1 , wherein said attribute of light comprises intensity and/or modulation phase.

3. Method as claimed in claim 1 or 2, comprising

accumulating light-induced charge in a second storage node;

detecting whether a second amount of charge accumulated in said second storage node exceeds a second threshold;

if said second amount of accumulated charge exceeds said second threshold, withdrawing said predefined quantity of said accumulated charge from said second storage node; and

decrementing said counter each time said predefined quantity of said accumulated charge is withdrawn from said second storage node, said count being a differential count.

4. Method as claimed in claim 3, wherein said second threshold and said threshold are equal.

5. Method as claimed in any one of claims 1 to 3, further comprising detecting a residual amount of charge in said storage node remaining in said storage node and wherein said signal indicative of said attribute of light is output based upon said count and said residual amount of charge.

6. Optoelectronic sensor for detecting an attribute of light impinging thereon, comprising

a photosensitive region for generating a charge in response to light impinging on said region;

a storage node for accumulating said light-induced charge;

a charge monitor operatively connected to said storage node for detecting whether an amount of charge accumulated in said storage node exceeds a threshold;

a dumping circuit responsive to said charge monitor for withdrawing a predefined quantity of said accumulated charge from said storage node if said amount of accumulated charge exceeds said threshold ;

a counter connected to said charge monitor and/or said dumping circuit so as to provide a count incremented each time said predefined quantity of said accumulated charge is withdrawn from said storage node; and an output circuit connected to said counter for outputting an output signal indicative of said attribute of light based upon said count.

7. Optoelectronic sensor as claimed in claim 6, wherein said charge monitor comprises a comparator for comparing said amount of accumulated charge with said threshold.

8. Optoelectronic sensor as claimed in claim 7, wherein said charge monitor comprises a buffer circuit with high input impedance between said storage node and said comparator.

9. Optoelectronic sensor as claimed in any one of claims 6 to 8, comprising a second storage node for accumulating light-induced charge;

a second charge monitor operatively connected to said second storage node for detecting whether a second amount of charge accumulated in said second storage node exceeds a second threshold;

a second dumping circuit responsive to said second charge monitor for withdrawing said predefined quantity of charge from said second storage node if said second amount of accumulated charge exceeds said second threshold.

10. Optoelectronic sensor as claimed in claim 9, comprising a second counter connected to said second charge monitor and/or said second dumping circuit so as to provide a second count incremented each time said predefined quantity of said accumulated charge is withdrawn from said second storage node; and wherein said output circuit is connected to said counter and to said second counter for outputting a signal indicative of said attribute of light based upon said count and said second count.

1 1 . Optoelectronic sensor as claimed in claim 9, wherein said counter is also connected to said second charge monitor and/or said second dumping circuit so as to provide a differential count incremented each time said predefined quantity of said accumulated charge is withdrawn from said storage node and decremented each time said predefined quantity of said accumulated charge is withdrawn from said second storage node.

12. Optoelectronic sensor as claimed in any one of claims 6 to 1 1 , comprising an analog-to-digital converter for converting a residual amount of charge remaining in said storage node into a digital residual charge signal, and wherein said output circuit is also connected to said analog-to-digital converter for outputting an output signal indicative of said attribute of light based upon said count and said digital residual charge signal.

13. Imager chip, comprising

a group of sensor pixels, each sensor pixel including

a photosensitive region for generating a charge in response to light impinging on said region; and

a storage node for accumulating said light-induced charge;

a dumping circuit for withdrawing a predefined quantity of said accumulated charge from said storage node;

a group of counters, each of said group of counters being associated with a sensor pixel;

a read-out circuit associated with said group of sensor pixels, said read-out circuit including a charge monitor operatively connectable to the storage node of each sensor pixel for detecting whether an amount of charge accumulated in said storage node exceeds a threshold; said charge monitor, when connected to a sensor pixel, causing the corresponding dumping circuit to withdraw said predefined quantity of said accumulated charge from said storage node if said amount of accumulated charge exceeds said threshold;

a controller configured to sequentially interface each one of said group of sensor pixels with its associated counter via said read-out circuit in such a way that a count in said counter is incremented each time said predefined quantity of said accumulated charge is withdrawn from the storage node of the associated sensor pixel; and

an output circuit connected to said group of counters for outputting a signal indicative of said attribute of light at each of said sensor pixels based upon the counts of the group of counters.

14. Imager chip, as claimed in claim 13, wherein said group of sensor pixels are arranged in a row or a column.

15. Imager chip, as claimed in claim 13, comprising a plurality of groups of sensor pixels, wherein the sensor pixels of each group are arranged in a row or a column.