WO2011105557A1 - Substrate for growing semiconductor, and light emitting element - Google Patents

Substrate for growing semiconductor, and light emitting element Download PDF

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Publication number
WO2011105557A1
WO2011105557A1 PCT/JP2011/054320 JP2011054320W WO2011105557A1 WO 2011105557 A1 WO2011105557 A1 WO 2011105557A1 JP 2011054320 W JP2011054320 W JP 2011054320W WO 2011105557 A1 WO2011105557 A1 WO 2011105557A1
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Prior art keywords
substrate
protrusion
semiconductor layer
light emitting
single crystal
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PCT/JP2011/054320
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French (fr)
Japanese (ja)
Inventor
和博 西薗
安田　隆則
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京セラ株式会社
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Priority to JP2012501885A priority Critical patent/JPWO2011105557A1/en
Publication of WO2011105557A1 publication Critical patent/WO2011105557A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/0242—Crystalline insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02428—Structure
    • H01L21/0243—Surface structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02658—Pretreatments
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/025—Physical imperfections, e.g. particular concentration or distribution of impurities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen

Definitions

  • the present invention relates to a semiconductor growth substrate and a light emitting device using the semiconductor growth substrate.
  • a technique for forming a light emitting element composed of an optical semiconductor layer that emits ultraviolet light, blue light, green light or the like on a semiconductor growth substrate has been proposed.
  • Such a light emitting element is disclosed in, for example, Japanese Patent Application Laid-Open No. 2005-277374.
  • Embodiments of the present invention are intended to provide a semiconductor growth substrate capable of improving the light emission efficiency, and a light emitting device in which an optical semiconductor layer is grown on the semiconductor growth substrate.
  • a substrate for semiconductor growth according to an embodiment of the present invention includes a plurality of protrusions having an upper surface with a part of the main surface protruding upward on the main surface of the substrate, and the protrusion grows a semiconductor crystal on the upper surface.
  • the crystal growth surface is made to have a texture in which the cross-sectional area decreases from the lower side to the upper side, and the side surface has a texture formed by overlapping a large number of columnar crystals having different heights.
  • a light emitting device includes an optical semiconductor layer grown on the above-described semiconductor growth substrate so as to cover the protrusions.
  • FIG. 3 is a cross-sectional view of the light emitting element shown in FIG. 2 and corresponds to a cross section taken along line B-B ′ of FIG. 2.
  • FIG. 5 is a cross-sectional view showing a step of the manufacturing process of the semiconductor growth substrate according to the embodiment of the present invention, corresponding to a cross section taken along line B-B ′ of FIG. 2. It is sectional drawing which shows 1 process of the manufacturing process of the board
  • FIG. 9 is a cross-sectional view showing a modification of the manufacturing process of the semiconductor growth substrate shown in FIGS. It is sectional drawing which shows the modification of the board
  • FIG. 1A is a perspective view of a light emitting device 2 on which the light emitting element 1 according to the present embodiment is mounted
  • FIG. 1B is a cross-sectional view of the light emitting device 2 shown in FIG. This corresponds to a cross section taken along line AA ′ in FIG.
  • the light emitting device 2 includes a mounting substrate 4 provided with lead electrodes 3 and a light emitting element 1 mounted on the mounting substrate 4.
  • the mounting substrate 4 has an extraction electrode 3 for conducting from the mounting surface 4A of the mounting substrate 4 to the extraction surface 4B.
  • a mounting substrate 4 can be formed by laminating ceramic materials or the like.
  • the first bonding electrode 5 and the second bonding electrode 6 are interposed between the first electrode layer 7 and the second electrode layer 8 of the light emitting element 1 described later and the extraction electrode 3, respectively, so that they are electrically bonded to each other. Is provided.
  • solder such as gold-tin, paste, conductive material such as gold, nickel, aluminum, titanium, or chromium can be used.
  • the light emitting element 1 is electrically connected to the extraction electrode 3 via the first bonding electrode 5 and the second bonding electrode 6 described above, and mounted on the mounting surface 4A.
  • the light emitting element 1 is mounted in a flip-chip connection so as to extract light emitted from the optical semiconductor layer 11 from a semiconductor growth substrate 10 to be described later.
  • the mold resin 9 is filled in the opening of the mounting substrate 4 so as to cover the light emitting element 1 mounted on the mounting substrate 4.
  • the mold resin 9 can be electrically insulated from the surroundings, and the reliability can be improved.
  • FIG. 2 is a perspective view of the light-emitting element 1 according to the present embodiment
  • FIG. 3 is a cross-sectional view of the light-emitting element 1 shown in FIG. 2, which corresponds to a cross section taken along line B-B ′ of FIG.
  • the light-emitting element 1 includes a semiconductor growth substrate 10 and an optical semiconductor layer 11 grown on the semiconductor growth substrate 10.
  • the substrate 10 for semiconductor growth is composed of a single crystal substrate 10a having protrusions 10b raised from the main surface 10A.
  • a material capable of growing the optical semiconductor layer 11 can be used.
  • a crystalline material such as sapphire, gallium nitride, aluminum nitride, or zinc oxide can be used.
  • the semiconductor growth substrate 10 has a plan view shape set to a polygonal shape such as a rectangular shape or a circular shape.
  • the thickness of the semiconductor growth substrate 10 is set to 2 ⁇ m or more and 1000 ⁇ m or less, for example.
  • the thickness of the semiconductor growth substrate 10 refers to the thickness from the lower surface 10B of the single crystal substrate 10a to the upper surface 10A 'of the protrusion 10b.
  • a material that can be easily removed as the semiconductor growth substrate 10 or a light-transmitting material may be used. By forming the semiconductor growth substrate 10 with such a material, the light emitted from the light emitting layer 11b can be efficiently extracted from the semiconductor growth substrate 10 side of the light emitting layer 11b.
  • the protrusion 10b is provided integrally with the single crystal substrate 10a so as to protrude upward from the main surface 10A of the single crystal substrate 10a.
  • the upper surface 10A 'of the protrusion 10b is a crystal growth surface.
  • the crystal growth plane refers to a plane in which crystal planes of the crystal lattice are aligned so that a semiconductor can be easily grown.
  • As the crystal growth surface for example, when sapphire is used, a crystal plane such as an A plane, a C plane, or an R plane of the crystal lattice can be used.
  • the projection 10b has a planar shape, for example, a polygonal shape such as a hexagonal shape or a rectangular shape, or a circular shape.
  • the protrusion 10b can be set so that the area of the upper surface 10A ′ is, for example, 0.2 ⁇ m 2 or more and 15 ⁇ m 2 or less. Further, the upper surface 10A ′ of the protrusion 10b can be provided such that the area occupied by the main surface 10A of the single crystal substrate 10a is, for example, 20% or more and 80% or less.
  • the protrusion 10a can be provided so that the cross-sectional area, which is the area of the cross section in the direction perpendicular to the vertical direction, decreases from the bottom to the top. Therefore, the protrusion 10a has a vertical cross-sectional shape that is a polygonal shape such as a trapezoidal shape or a quadrangular shape.
  • the protrusion 10b can be set so that the height from the main surface 10A of the single crystal substrate 10a to the upper surface 10A 'of the protrusion 10b is, for example, not less than 0.5 ⁇ m and not more than 200 ⁇ m.
  • FIG. 4 shows an SEM photograph in which the protrusion 10b is seen in perspective
  • FIG. 4B shows an SEM photograph in which the protrusion 10b is viewed from the side.
  • the SEM photograph was obtained by observing a single crystal substrate in which a conductive material was laminated on the entire surface by 10 nm or less after providing protrusions on the single crystal substrate made of sapphire.
  • the texture 12 is provided so that a large number of columnar crystals 12 ′ extend and overlap from the lower end to the upper end between the lower end and the upper end of the protrusion 10 b. .
  • the texture 12 has a so-called scaly shape by being configured such that a large number of columnar crystals 12 ′ overlap. Further, since the plurality of columnar crystals 12 'are provided integrally with the protrusion 10b, the entire outer surface of the protrusion 10b has a stepped structure due to the columnar crystal 12'.
  • the columnar crystal 12 ' is provided so that the length from the lower end to the upper end is different. Thereby, the plurality of columnar crystals 12 'are arranged such that the top surfaces thereof are different in height from the main surface 10A of the single crystal substrate 10a.
  • the columnar crystal 12 ′ having a top surface lower than the height of the protrusion 10b can be set such that the height from the main surface 10A to the top surface of the single crystal substrate 10a is, for example, 0.5 ⁇ m or more and 10 ⁇ m or less. it can.
  • the height from the boundary between the protrusion 10b and the single crystal substrate 10a may be used.
  • the columnar crystal 12 ' when comparing the portion located below the columnar crystal 12 'with the portion located above the columnar crystal 12', the columnar crystal 12 'is located under the projection 10b when viewed from the side.
  • the width is set to be large.
  • the lateral width of the columnar crystal 12 'when viewed from the side can be set to, for example, 50 nm or more and 500 nm or less.
  • the columnar crystal 12 ' is provided integrally with the protrusion 10b so that a part of the outer surface protrudes from the lower surface of the protrusion 10b in a variety of directions from the bottom to the top.
  • the protrusion 10b has a texture 12 by arranging such a plurality of columnar crystals 12 'so as to be folded.
  • the plurality of grooves provided on the outer surface of the protrusion 10b have shapes that are cut out in various shapes such as a V shape or a square shape when the protrusion 10b is viewed in cross section.
  • the depth of the groove from the outer surface to the inside of the protrusion 10b can be set to 1 nm or more and 1 ⁇ m or less, for example.
  • channel can be set to 10 nm or more and 1 micrometer or less, for example.
  • An optical semiconductor layer 11 is provided on the semiconductor growth substrate 10 as shown in FIG.
  • the optical semiconductor layer 11 is configured by sequentially laminating a first semiconductor layer 11a, a light emitting layer 11b, and a second semiconductor layer 11c.
  • the entire thickness of the optical semiconductor layer 11 is, for example, 0.1 ⁇ m or more and 20 ⁇ m or less.
  • the refractive index of each layer of the optical semiconductor layer 11 can be set to, for example, 1.80 or more and 2.70 or less when gallium nitride is used.
  • a III-V semiconductor can be used as the optical semiconductor layer 11.
  • group III-V semiconductors include group III nitride semiconductors, gallium phosphide, gallium arsenide, and the like.
  • group III nitride semiconductor a mixed crystal made of at least one nitride of boron, aluminum, gallium, or indium can be used.
  • gallium nitride can be used.
  • the first semiconductor layer 11a is provided on the single crystal substrate 10a so as to cover the protrusion 10b.
  • the dislocations 13 extend in the thickness direction.
  • the dislocations 13 are formed by shifting the crystal lattice of the semiconductor. Examples of the dislocation 13 include edge dislocations and helical dislocations. Dislocations 13, that is, crystal lattice misalignment, are likely to occur because the first semiconductor layer 11a and the single crystal substrate 10a have different lattice constants.
  • the first semiconductor layer 11a is set to have a thickness of 1 ⁇ m or more and 10 ⁇ m or less.
  • the light emitting layer 11b is provided on the first semiconductor layer 11a.
  • a multilayer quantum well structure in which a quantum well structure composed of a barrier layer with a wide forbidden band and a well layer with a narrow forbidden band is regularly stacked a plurality of times can be used.
  • a mixed crystal composed of nitride of indium and gallium with the composition ratio of indium and gallium adjusted can be used.
  • the light emitting layer 11b configured as described above emits light having a wavelength of 350 nm to 600 nm, for example. Since the light emitting layer 11b is provided on the first semiconductor layer 11a, when the dislocation 13 extends in the first semiconductor layer 11a, the dislocation 13 is easily transferred to the light emitting layer 11b.
  • the second semiconductor layer 11c is provided on the light emitting layer 11b.
  • the second semiconductor layer 11c is set so as to exhibit an opposite conductivity type to the first semiconductor layer 11a by using either electrons or holes as majority carriers.
  • a method for imparting conductivity type to the semiconductor layer for example, a method of mixing magnesium or silicon as an impurity can be used.
  • the first electrode layer 7 is provided on the first semiconductor layer 11a, and the second electrode layer 8 is provided on the second semiconductor layer 11c.
  • a voltage is applied to the optical semiconductor layer 11 by such two electrode layers.
  • the material for the electrode layer include aluminum, titanium, nickel, chromium, indium, tin, molybdenum, silver, gold, niobium, tantalum, vanadium, platinum, lead, and beryllium, tin oxide, indium oxide, and indium oxide.
  • An oxide such as tin, or an alloy film such as a gold-silicon alloy, a gold-germanium alloy, a gold-zinc alloy, or a gold-beryllium alloy can be preferably used.
  • such an electrode layer may be formed by laminating layers selected from the above materials.
  • the dislocations 13 extending from the single crystal substrate 10a into the optical semiconductor layer 11 are formed.
  • the number can be controlled.
  • the outer surface of the protrusion 10b has a texture 12 composed of a plurality of columnar crystals 12 '. Therefore, on the surface of the outer surface of the protrusion 10b, the outer surface can be roughened in the vertical direction and the outer peripheral direction of the outer surface, and the crystal planes of the crystal lattice of the single crystal substrate 10a can be made uneven. Therefore, when the optical semiconductor layer 11 is grown on the semiconductor growth substrate 10, it is difficult to grow a crystal on the rough outer surface, so that it is difficult to grow a crystal on the outer surface of the protrusion 10b. .
  • dislocations 13 there are a plurality of dislocations 13 extending from the semiconductor growth substrate 10 located in the optical semiconductor layer 11, and the number of dislocations 13 extending from the main surface 10A of the single crystal substrate 10a extends from the outer surface of the protrusion 10b.
  • the number of dislocations 13 is decreasing.
  • the number of dislocations 13 extending from the outer surface of the protrusion 10b can be reduced, and the number of dislocations 13 extending in the thickness direction of the optical semiconductor layer 11 can be reduced.
  • the number of dislocations 13 extending in the thickness direction of the optical semiconductor layer 11 in the first region 14 that does not overlap the upper surface 10A ′ of the protrusion 10b is reduced when the optical semiconductor layer 11 and the semiconductor growth substrate 10 are seen through in plan. be able to.
  • the crystal quality of the optical semiconductor layer 11 in the first region 14 can be improved, and the light emission efficiency of the light emitted from the light emitting element 1 can be improved.
  • a region that does not overlap the upper surface 10A ′ of the protrusion 10b is a first region 14, and a region that overlaps the upper surface 10A ′ of the protrusion 10b is a second region 15. Each is shown.
  • the optical semiconductor layer grows on the outer surface of the protrusion to generate dislocations extending from the outer surface of the protrusions, and the dislocations extend in the thickness direction of the optical semiconductor layer.
  • a large number of dislocations exist in the optical semiconductor layer, and the light emission efficiency of the light emitting element is likely to be lowered.
  • the dislocations since many dislocations extend in the thickness direction of the optical semiconductor layer, when a voltage is applied to the light-emitting element, the dislocations have an electric resistance value smaller than the bulk resistance of the optical semiconductor layer and are short-circuited. And electrostatic breakdown are likely to occur, leading to a decrease in reliability.
  • the texture 12 on the outer surface of the protrusion 10b is composed of a plurality of columnar crystals 12 '. Therefore, when the light emitted from the optical semiconductor layer 11 is extracted from the single crystal substrate 10a side, the light emitted from the optical semiconductor layer 11 is less likely to be reflected to the optical semiconductor layer 11 side at the interface with the semiconductor growth substrate 10. Can do. Therefore, the light extraction efficiency of the light emitting element 1 can be improved.
  • the light emitted from the optical semiconductor layer 11 in the first region 14 can be easily incident on the single crystal substrate 10a from the outer surface of the protrusion 10b. Since the light semiconductor layer 11 is easily incident on the single crystal substrate 10a in this manner, the light can be refracted so that the refraction angle is larger than the incident angle. Light can be refracted in the direction of the second region 15. Therefore, even when the light emission efficiency of the optical semiconductor layer 11 in the first region 14 is improved, the light emission unevenness of the light emitting element 1 can be suppressed.
  • the semiconductor growth substrate 10 As described above, by using the semiconductor growth substrate 10 according to the embodiment of the present invention, it is possible to provide the light emitting element 1 capable of improving the crystal quality of the optical semiconductor layer 11 and improving the light extraction efficiency. it can.
  • the tip of the single crystal substrate 10a whose height position from the main surface 10A is partway along the side surface of the projection 10b may be partially reduced in the upward direction.
  • the columnar crystal 12 ′ is smaller as the outer cross-sectional area is upward when viewed in plan, and the width of the columnar crystal 12 ′ is smaller as viewed from the side when viewed from the side. Is provided.
  • the top surface of the columnar crystal 12 ' is inclined with respect to the main surface 10A of the single crystal substrate 10a by decreasing the tip of the columnar crystal 12' upward.
  • the tip of the columnar crystal 12 ′ becomes smaller toward the upper side, the light emitted from the light emitting layer 11b can be easily incident at an angle smaller than the critical angle at the interface with the single crystal substrate 10a. . Therefore, it can be made more difficult to be reflected at the interface between the optical semiconductor layer 11 and the single crystal substrate 10a. As a result, when the light emitted from the optical semiconductor layer 11 is extracted from the single crystal substrate 10a side, the light extraction efficiency of the light emitting element 1 can be improved.
  • the light emitted from the first region 14 of the optical semiconductor layer 11 can be made incident on the second region 15 by the texture 12, unevenness in light emission can be further improved.
  • the columnar crystal 12 ′ may have a structure that becomes smaller as the cross-sectional area goes upward.
  • a tapered shape in which the tip (top surface) of the columnar crystal 12 'is disposed above can be used.
  • an annular recess 16 is formed on the main surface 10A of the single crystal substrate 10 so as to surround the raised protrusion 10b.
  • a recess 16 can be provided such that the depth from the main surface 10A of the single crystal substrate 10 to the lower end of the recess 16 is, for example, not less than 0.1 ⁇ m and not more than 3 ⁇ m.
  • An annular recess 16 formed so as to surround the protrusion 10b is disposed so as to be in contact with the outer surface of the protrusion 10b. Therefore, the protrusion 10b is provided so as to protrude upward so that the lower end of the outer surface becomes the lower end of the recess 16.
  • the light emitted from the light emitting layer 11b can be made difficult to be reflected by the recess 16 toward the optical semiconductor layer 11 side.
  • the light emitted from 11b can be efficiently extracted from the single crystal substrate 10a side. As a result, the light extraction efficiency of the light emitting element 1 can be improved.
  • 5 to 10 are cross-sectional views for explaining a method for manufacturing the light-emitting element 1, and show a portion corresponding to a cross section taken along line AA ′ of the light-emitting element 1 shown in FIG.
  • a resist pattern 17 having a through hole 17a in which a part of the single crystal substrate 10a is exposed is formed on the single crystal substrate 10a.
  • a material that can be easily removed later can be selected, and the thickness can be set to 0.1 ⁇ m or more and 10 ⁇ m or less, for example.
  • Such a resist pattern 17 can be provided by a conventional photoresist method or the like.
  • a part of the upper surface 10A 'of the single crystal substrate 10a can be exposed. Note that a region where a part of the single crystal substrate 10a is exposed is defined as a first exposed region 18a.
  • the planar shape of the through hole 17 may be set to the shape of the upper surface 10A 'of the protrusion 10b.
  • a laminated film 19 is formed by filling a mask material in the first exposed region 18a of the single crystal substrate 10a.
  • the thickness of the laminated film 19 may be set from the selection ratio between the mask material and the etching depth, and can be set to 400 nm or more and 900 nm or less, for example.
  • a chlorine-based gas that easily reacts with sapphire can be suitably used as a reactive gas.
  • a method of laminating the mask material on the single crystal substrate 10a for example, a sputtering method, a vapor deposition method or the like can be used.
  • the sputtering method is used, the mask material can be buried in the through-hole 17a with good coverage. it can.
  • the laminated film 19 may be formed by laminating a plurality of different mask materials.
  • the etching rate can be changed depending on the layer of each mask material when the single crystal substrate 10a described later is etched.
  • the protrusion 10b is formed on the single crystal substrate 10a, and the texture 12 composed of a plurality of columnar crystals 12 'is formed on the protrusion 10b. Can do.
  • the resist pattern 17 is removed to form a mask pattern 20 having a second exposed region 18b in which a part of the single crystal substrate 10a is exposed.
  • a mask pattern 20 by forming a mask pattern 20 using a metal material as a mask material, when the resist pattern 17 is removed, part of the outer peripheral surface of each mask 20a constituting the mask pattern 20 is also removed. Is done.
  • a plurality of grooves are formed on the outer peripheral surface of each mask 20a constituting the mask pattern 20.
  • Such a plurality of grooves are provided from the lower end to the upper end of the mask 20a.
  • the width of the groove can be set to be 10 nm or more and 1 ⁇ m or less, for example.
  • the reason why the plurality of grooves are easily formed on the outer peripheral surface of the mask 20a in this way is that the mask pattern 20 using a metal material has crystal lumps.
  • the single crystal substrate 10a is partially removed in the thickness direction by etching the second exposed region 18b and the mask pattern 20 of the single crystal substrate 10a.
  • the protrusion 10b is provided on the single crystal substrate 10a, and the texture 12 composed of the plurality of columnar crystals 12 'is formed on the outer surface of the protrusion 10b.
  • etching wet etching, dry etching, or the like can be used.
  • productivity can be improved by performing dry etching in a chlorine-based gas atmosphere that easily reacts with sapphire.
  • the texture 12 provided on the outer surface of the protrusion 10b can be formed by dry etching from above the single crystal substrate 10a. . This is because the etching rate of the single crystal substrate 10a can be partially changed by the grooves and crystal lumps formed on the outer peripheral surface of the mask 20a.
  • a semiconductor growth substrate 10 is produced in which a texture 12 composed of a plurality of columnar crystals 12 'is formed on the outer surface of the protrusion 10b. can do.
  • the optical semiconductor layer 11 is formed on the protrusion 10b of the semiconductor growth substrate 10 by lateral growth.
  • growth conditions such as a composition ratio, a growth temperature, and a growth pressure may be adjusted in each layer.
  • the growth rate of the first semiconductor layer 11a can be controlled in the vertical direction and the horizontal direction with respect to the main surface 10A of the single crystal substrate 10a, and the first semiconductor layer 11a is controlled in the horizontal direction. Can be grown.
  • a texture 12 composed of a plurality of columnar crystals 12 ' is provided on the outer surface of the protrusion 10b. Therefore, when the first semiconductor layer 11a is grown on the semiconductor growth substrate 10, the first semiconductor layer 11a is difficult to grow on the outer surface of the protrusion 10b. That is, it is possible to suppress the occurrence of dislocations 13 extending in the thickness direction of the first semiconductor layer 11a from the outer surface of the protrusion 10b.
  • the first semiconductor layer 11a is laterally grown on the semiconductor growth substrate 10, the first semiconductor layer 11a grows on the main surface 10A of the exposed single crystal substrate 10a. As a result, the space between the adjacent protrusions 10b is filled with the first semiconductor layer 11a grown on the main surface 10A of the single crystal substrate 10b. Thereafter, the light emitting layer 11b and the second semiconductor layer 11c are grown on the first semiconductor layer 11a.
  • a method for growing the optical semiconductor layer 11, that is, the first semiconductor layer 11a, the light emitting layer 11b, and the second semiconductor layer 11c a metal organic chemical vapor deposition method, a molecular beam epitaxy method, a hydride vapor deposition method, a pulsed laser deposition method, or the like Can be used.
  • the growth rate can be increased while controlling the number and position of the dislocations 13 extending to the light emitting layer 11b, so that the productivity of the optical semiconductor layer 11 can be increased. Can be improved.
  • the texture 12 on the outer surface of the protrusion 10b may be constituted by a columnar crystal 12 ′ whose tip is reduced in the upward direction.
  • the tip becomes smaller as it goes upward, so that the space between the adjacent projections 10b can be adhered to the semiconductor from the main surface 10A of the single crystal substrate 10a. Can grow well and fill.
  • a recess 16 surrounding the protrusion 10b may be formed on the main surface 10A of the single crystal substrate 10a.
  • the concave portion 16 is formed on the main surface 10A of the single crystal substrate 10a in this way, the surface of the single crystal substrate 10a between the two adjacent projections 10b does not become flat when viewed in cross section. It is possible to make it difficult for the first semiconductor layer 11a to grow on the surface. As a result, dislocations extending from the surface of the single crystal substrate 10 between two adjacent protrusions 10b can be reduced, and the crystal quality in the second region of the optical semiconductor layer 11 can be further improved.
  • a resist pattern 17 having an inverted mesa-shaped end face 17 ′ may be used.
  • a process of providing the protrusion 10b using the resist pattern 17 having the inverted mesa-shaped end face 17 ′ will be described with reference to FIG.
  • the end face 17 ′ is formed when the resist pattern 17 is formed by exposing the photosensitive material to solidification.
  • a reverse mesa shape may be used.
  • a method of making the end face 17 ′ into an inverted mesa shape a method of applying a photosensitive material on the upper surface 10A ′ of the single crystal substrate 10a and irradiating light from a direction perpendicular to the upper surface 10A ′ can be used. .
  • the irradiated light is refracted at the interface between the outside and the photosensitive material and enters the photosensitive material.
  • the inverted mesa-shaped end surface 17 ' can be set so that the inner angle between the end surface 17' of the resist pattern 17 and the main surface 10A of the single crystal substrate 10a is, for example, 95 ° to 150 °.
  • a metal material to be the mask pattern 20 is laminated on the upper surface 10A of the single crystal substrate 10a and the resist pattern 17 as a metal layer 20 '.
  • the metal material to be laminated can be cut off to form the mask 20 a on the upper surface 10 a of the single crystal substrate 10 a.
  • the cross-sectional shape in the vertical direction of the mask 20a is trapezoidal or semicircular.
  • Such a metal material can be set to be, for example, 10% or more and 70% or less with respect to the thickness of the resist pattern 17.
  • a method for laminating the metal material for example, an evaporation method or a sputtering method can be used. Thereafter, as shown in FIG. 9C, the resist pattern 17 is removed, and a mask pattern 20 is formed on the upper surface 10A of the single crystal substrate 10a.
  • a protrusion 10b is formed, and a texture 12 composed of a plurality of columnar crystals 12 'is formed on the outer surface of the protrusion 10b.
  • the mask pattern 20 made of a metal material can be etched in this way to form the texture 12 on the outer surface of the protrusion 10b.
  • the mask 20a has a trapezoidal cross-sectional shape in the vertical direction. This is because the etching rate varies because the material has crystal lumps.
  • the texture 12 composed of the plurality of columnar crystals 12 ' can be easily formed on the outer surface of the protrusion 10b.
  • An annular recess 16 may be formed on the main surface 10A of the single crystal substrate 10a so as to surround the raised protrusion 10b as shown in FIG.
  • Such a recess 16 can be formed, for example, by performing dry etching using a metal material as the mask pattern 20.
  • the mask pattern 20 When a metal material is used as the mask pattern 20 in this way, ions for etching the single crystal substrate 10a can easily travel in the side surface direction of the mask 20a. As a result, an annular recess 16 surrounding the projection 10b can be easily formed. Note that the depth of the recess 16 can be changed by, for example, a selection ratio between the amount of etching of the single crystal substrate 10a and the amount of etching of the mask.

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Abstract

Disclosed is a substrate for growing a semiconductor, wherein the main surface of the substrate is provided with a plurality of protruding portions, each of which has the upper surface and is formed by having a part of the main surface protruding upward. In each protruding portion, the upper surface is a crystal growing surface for growing a semiconductor crystal, the cross-section area thereof is reduced toward the upper portion from the lower portion, and the side surface thereof has a texture configured by having a plurality of columnar crystals with different heights overlap each other.

Description

半導体成長用基板および発光素子Semiconductor growth substrate and light emitting device
　この発明は、半導体成長用基板と、当該半導体成長用基板を用いた発光素子に関するものである。 The present invention relates to a semiconductor growth substrate and a light emitting device using the semiconductor growth substrate.
　現在、半導体成長用基板上に、紫外光、青色光、緑色光等を発光する光半導体層から構成される発光素子を形成する技術が提案されている。そのような発光素子としては、例えば特開2005－277374号公報に開示されている。 Currently, a technique for forming a light emitting element composed of an optical semiconductor layer that emits ultraviolet light, blue light, green light or the like on a semiconductor growth substrate has been proposed. Such a light emitting element is disclosed in, for example, Japanese Patent Application Laid-Open No. 2005-277374.
　発光素子の開発において、発光むらや発光効率を改善するために、半導体成長用基板上に光半導体層を成長させる際に、光半導体層の厚み方向に延在する転位を減らす必要があった。 In the development of a light emitting device, in order to improve light emission unevenness and light emission efficiency, it is necessary to reduce dislocations extending in the thickness direction of the optical semiconductor layer when growing the optical semiconductor layer on the semiconductor growth substrate.
　本発明の実施形態は、発光効率を向上させることができる半導体成長用基板、およびかかる半導体成長用基板上に光半導体層を成長させた発光素子を提供することを目的とする。 Embodiments of the present invention are intended to provide a semiconductor growth substrate capable of improving the light emission efficiency, and a light emitting device in which an optical semiconductor layer is grown on the semiconductor growth substrate.
　本発明の実施形態にかかる半導体成長用基板は、基板の主面に、該主面の一部が上方に***した、上面を持つ突起を複数備え、該突起は、前記上面が半導体結晶を成長させるための結晶成長面であり、下方から上方に向かうにつれて横断面積が小さくなっているとともに、側面が高さの異なる多数の柱状結晶が重なり合って構成されているテクスチャーを有している。 A substrate for semiconductor growth according to an embodiment of the present invention includes a plurality of protrusions having an upper surface with a part of the main surface protruding upward on the main surface of the substrate, and the protrusion grows a semiconductor crystal on the upper surface. The crystal growth surface is made to have a texture in which the cross-sectional area decreases from the lower side to the upper side, and the side surface has a texture formed by overlapping a large number of columnar crystals having different heights.
　また本発明の実施形態にかかる発光素子は、上述の半導体成長用基板上に、前記突起を被覆するように成長させた光半導体層を備える。 A light emitting device according to an embodiment of the present invention includes an optical semiconductor layer grown on the above-described semiconductor growth substrate so as to cover the protrusions.
本発明の実施形態にかかる発光素子を実装した発光装置を示す図であり、（ａ）は斜視図であり、（ｂ）は（ａ）のＡ－Ａ’線で切断したときの断面図である。BRIEF DESCRIPTION OF THE DRAWINGS It is a figure which shows the light-emitting device which mounted the light emitting element concerning embodiment of this invention, (a) is a perspective view, (b) is sectional drawing when cut | disconnecting by the AA 'line of (a). is there. 図１に示す発光素子の斜視図である。It is a perspective view of the light emitting element shown in FIG. 図２に示す発光素子の断面図であり、図２のＢ－Ｂ’線で切断したときの断面に相当する。FIG. 3 is a cross-sectional view of the light emitting element shown in FIG. 2 and corresponds to a cross section taken along line B-B ′ of FIG. 2. 本発明の実施形態にかかる半導体成長用基板の突起を走査型電子顕微鏡により観察した時の図面代用写真であり、（ａ）はかかる突起を斜視したとき、（ｂ）は突起を側面視したときに該当する。It is a drawing substitute photograph when the protrusion of the substrate for semiconductor growth according to the embodiment of the present invention is observed with a scanning electron microscope, where (a) is a perspective view of the protrusion and (b) is a side view of the protrusion. It corresponds to. 本発明の実施形態にかかる半導体成長用基板の製造工程の一工程を示す断面図であり、図２のＢ－Ｂ’線で切断したときの断面に相当する。FIG. 5 is a cross-sectional view showing a step of the manufacturing process of the semiconductor growth substrate according to the embodiment of the present invention, corresponding to a cross section taken along line B-B ′ of FIG. 2. 本発明の実施形態にかかる半導体成長用基板の製造工程の一工程を示す断面図である。It is sectional drawing which shows 1 process of the manufacturing process of the board | substrate for semiconductor growth concerning embodiment of this invention. 本発明の実施形態にかかる半導体成長用基板の製造工程の一工程を示す断面図である。It is sectional drawing which shows 1 process of the manufacturing process of the board | substrate for semiconductor growth concerning embodiment of this invention. 本発明の実施形態にかかる半導体成長用基板の製造工程の一工程を示す断面図である。It is sectional drawing which shows 1 process of the manufacturing process of the board | substrate for semiconductor growth concerning embodiment of this invention. 本発明の実施形態にかかる発光素子の製造工程の一工程を示す断面図である。It is sectional drawing which shows 1 process of the manufacturing process of the light emitting element concerning embodiment of this invention. 図５～８に示す半導体成長用基板の製造工程の変形例を示す断面図である。FIG. 9 is a cross-sectional view showing a modification of the manufacturing process of the semiconductor growth substrate shown in FIGS. 図８に示す半導体成長用基板の変形例を示す断面図である。It is sectional drawing which shows the modification of the board | substrate for semiconductor growth shown in FIG.
　本発明は以下の実施形態に限定されるものではなく、本発明の実施形態の要旨を逸脱しない範囲内で種々変更を施すことができる。 The present invention is not limited to the following embodiments, and various modifications can be made without departing from the scope of the embodiments of the present invention.
　＜発光装置＞
　図１（ａ）は本実施形態にかかる発光素子１を実装した発光装置２の斜視図であり、図１（ｂ）は図１（ａ）に示す発光装置２の断面図であり、図１（ａ）のＡ－Ａ’線で切断した時の断面に相当する。 <Light emitting device>
FIG. 1A is a perspective view of a light emitting device 2 on which the light emitting element 1 according to the present embodiment is mounted, and FIG. 1B is a cross-sectional view of the light emitting device 2 shown in FIG. This corresponds to a cross section taken along line AA ′ in FIG.
　発光装置２は、図１（ｂ）に示すように、引き出し電極３が設けられた実装基体４と、実装基体４上に実装された発光素子１と、を有している。 As shown in FIG. 1B, the light emitting device 2 includes a mounting substrate 4 provided with lead electrodes 3 and a light emitting element 1 mounted on the mounting substrate 4.
　実装基体４は、実装基体４の実装面４Ａから引き出し面４Ｂまで導通をとるための引き出し電極３を有している。このような実装基体４は、セラミック材料などを積層することにより形成することができる。 The mounting substrate 4 has an extraction electrode 3 for conducting from the mounting surface 4A of the mounting substrate 4 to the extraction surface 4B. Such a mounting substrate 4 can be formed by laminating ceramic materials or the like.
　第１接合電極５および第２接合電極６は、それぞれ後述する発光素子１の第１電極層７および第２電極層８と引き出し電極３との間に介在し、それぞれが電気的に接合するように設けられている。このような第１接合電極５および第２接合電極６は、例えば金－スズ等のはんだ、ペースト、金、ニッケル、アルミニウム、チタンまたはクロムなどの導電性材料などを用いることができる。 The first bonding electrode 5 and the second bonding electrode 6 are interposed between the first electrode layer 7 and the second electrode layer 8 of the light emitting element 1 described later and the extraction electrode 3, respectively, so that they are electrically bonded to each other. Is provided. For the first bonding electrode 5 and the second bonding electrode 6, for example, solder such as gold-tin, paste, conductive material such as gold, nickel, aluminum, titanium, or chromium can be used.
　発光素子１は、上述した第１接合電極５および第２接合電極６を介して電気的に引き出し電極３と接続されて、実装面４Ａ上に実装される。本実施形態において発光素子１は、後述する半導体成長用基板10から光半導体層11で発した光を取り出すようにフリップチップ接続による配置で実装されている。 The light emitting element 1 is electrically connected to the extraction electrode 3 via the first bonding electrode 5 and the second bonding electrode 6 described above, and mounted on the mounting surface 4A. In the present embodiment, the light emitting element 1 is mounted in a flip-chip connection so as to extract light emitted from the optical semiconductor layer 11 from a semiconductor growth substrate 10 to be described later.
　モールド樹脂９は、実装基体４に実装された発光素子１を被覆するように、実装基体４の開口部に充填されている。このように発光素子１をモールド樹脂９によって被覆することで、電気的に周囲と絶縁させることができ、信頼性を向上させることができる。 The mold resin 9 is filled in the opening of the mounting substrate 4 so as to cover the light emitting element 1 mounted on the mounting substrate 4. Thus, by covering the light emitting element 1 with the mold resin 9, it can be electrically insulated from the surroundings, and the reliability can be improved.
　［発光素子の構造］
　発光装置２に実装される発光素子１を、図面を参考にしつつ以下に詳細に説明する。 [Structure of light-emitting element]
The light emitting element 1 mounted on the light emitting device 2 will be described in detail below with reference to the drawings.
　図２は本実施形態にかかる発光素子１の斜視図、図３は図２に示す発光素子１の断面図であり、図２のＢ－Ｂ’線で切断したときの断面に相当する。 2 is a perspective view of the light-emitting element 1 according to the present embodiment, and FIG. 3 is a cross-sectional view of the light-emitting element 1 shown in FIG. 2, which corresponds to a cross section taken along line B-B ′ of FIG.
　発光素子１は、図２および３に示すように、半導体成長用基板10と、半導体成長用基板10上に成長させた光半導体層11とを有する。 As shown in FIGS. 2 and 3, the light-emitting element 1 includes a semiconductor growth substrate 10 and an optical semiconductor layer 11 grown on the semiconductor growth substrate 10.
　半導体成長用基板10は、主面10Ａから***した突起10ｂを持つ単結晶基板10ａから構成されている。半導体成長用基板10は、光半導体層11を成長させることが可能な材料を用いることができ、例えばサファイア、窒化ガリウム、窒化アルミニウムまたは酸化亜鉛などの結晶性材料を用いることができる。 The substrate 10 for semiconductor growth is composed of a single crystal substrate 10a having protrusions 10b raised from the main surface 10A. For the semiconductor growth substrate 10, a material capable of growing the optical semiconductor layer 11 can be used. For example, a crystalline material such as sapphire, gallium nitride, aluminum nitride, or zinc oxide can be used.
　半導体成長用基板10は、平面視形状が例えば長方形状などの多角形状や円形状などに設定される。半導体成長用基板10の厚みは、例えば２μｍ以上1000μｍ以下に設定される。ここで、半導体成長用基板10の厚みは、単結晶基板10ａの下面10Ｂから突起10ｂの上面10Ａ’までの厚みを指す。本実施形態のように、発光素子１をフリップチップ実装する場合、半導体成長用基板10として除去することが容易な材料や透光性の材料を用いてもよい。このような材料で半導体成長用基板10を形成することにより、発光層11ｂで発した光を、発光層11ｂの半導体成長用基板10側から効率よく取り出すことができる。 The semiconductor growth substrate 10 has a plan view shape set to a polygonal shape such as a rectangular shape or a circular shape. The thickness of the semiconductor growth substrate 10 is set to 2 μm or more and 1000 μm or less, for example. Here, the thickness of the semiconductor growth substrate 10 refers to the thickness from the lower surface 10B of the single crystal substrate 10a to the upper surface 10A 'of the protrusion 10b. When the light-emitting element 1 is flip-chip mounted as in this embodiment, a material that can be easily removed as the semiconductor growth substrate 10 or a light-transmitting material may be used. By forming the semiconductor growth substrate 10 with such a material, the light emitted from the light emitting layer 11b can be efficiently extracted from the semiconductor growth substrate 10 side of the light emitting layer 11b.
　突起10ｂは、単結晶基板10ａの主面10Ａから上方に***するよう単結晶基板10ａと一体的に設けられている。突起10ｂの上面10Ａ’は、結晶成長面となっている。結晶成長面とは半導体が成長しやすくなるように、結晶格子の結晶面を揃えた平面を指す。結晶成長面としては、例えばサファイアを用いた場合だと、結晶格子のＡ面、Ｃ面またはＲ面などの結晶面を用いることができる。 The protrusion 10b is provided integrally with the single crystal substrate 10a so as to protrude upward from the main surface 10A of the single crystal substrate 10a. The upper surface 10A 'of the protrusion 10b is a crystal growth surface. The crystal growth plane refers to a plane in which crystal planes of the crystal lattice are aligned so that a semiconductor can be easily grown. As the crystal growth surface, for example, when sapphire is used, a crystal plane such as an A plane, a C plane, or an R plane of the crystal lattice can be used.
　突起10ｂは、平面視形状が、例えば、六角形状もしくは長方形状などの多角形状または円形状などである。突起10ｂは、上面10Ａ’の面積が、例えば0.2μｍ２以上15μｍ２以下となるように設定することができる。また、突起10ｂの上面10Ａ’は、単結晶基板10ａの主面10Ａに対して占める面積が、例えば20％以上80％以下となるように設けることができる。 The projection 10b has a planar shape, for example, a polygonal shape such as a hexagonal shape or a rectangular shape, or a circular shape. The protrusion 10b can be set so that the area of the upper surface 10A ′ is, for example, 0.2 μm 2 or more and 15 μm 2 or less. Further, the upper surface 10A ′ of the protrusion 10b can be provided such that the area occupied by the main surface 10A of the single crystal substrate 10a is, for example, 20% or more and 80% or less.
　さらに突起10ａは、下方から上方に向かうにつれて、上下方向と垂直な方向の横断面の面積である横断面積が小さくなるように設けることができる。そのため、突起10ａは、上下方向の縦断面の形状が、例えば台形状または四角形状などの多角形状である。なお、突起10ｂは、単結晶基板10ａの主面10Ａから突起10ｂの上面10Ａ’までの高さが、例えば0.5μｍ以上200μｍ以下となるように設定することができる。 Furthermore, the protrusion 10a can be provided so that the cross-sectional area, which is the area of the cross section in the direction perpendicular to the vertical direction, decreases from the bottom to the top. Therefore, the protrusion 10a has a vertical cross-sectional shape that is a polygonal shape such as a trapezoidal shape or a quadrangular shape. The protrusion 10b can be set so that the height from the main surface 10A of the single crystal substrate 10a to the upper surface 10A 'of the protrusion 10b is, for example, not less than 0.5 μm and not more than 200 μm.
　突起10ｂの外側面は、図４に示すように、柱状結晶12’が重なり合って構成されたテクスチャー12を有している。図４（ａ）は突起10ｂを斜視したＳＥＭ写真を示し、図４（ｂ）は突起10ｂを側面視したＳＥＭ写真を示している。なお、当該ＳＥＭ写真は、サファイアからなる単結晶基板に突起を設けた後、表面全体に導電材料を10ｎｍ以下積層させた単結晶基板を観察したものである。かかるテクスチャー12は、図４（ｂ）に示すように、突起10ｂの下端から上端までの間に、下端から上方に向けて多数の柱状結晶12’が延在して重なり合うように設けられている。 As shown in FIG. 4, the outer surface of the protrusion 10b has a texture 12 formed by overlapping columnar crystals 12 '. FIG. 4A shows an SEM photograph in which the protrusion 10b is seen in perspective, and FIG. 4B shows an SEM photograph in which the protrusion 10b is viewed from the side. The SEM photograph was obtained by observing a single crystal substrate in which a conductive material was laminated on the entire surface by 10 nm or less after providing protrusions on the single crystal substrate made of sapphire. As shown in FIG. 4B, the texture 12 is provided so that a large number of columnar crystals 12 ′ extend and overlap from the lower end to the upper end between the lower end and the upper end of the protrusion 10 b. .
　テクスチャー12は、このように多数の柱状結晶12’が重なり合うようにして構成されていることにより、いわゆる鱗片状となっている。また、複数の柱状結晶12’は突起10ｂと一体的に設けられていることから、突起10ｂの外側面全体が柱状結晶12’によって段差を有する構造となっている。 The texture 12 has a so-called scaly shape by being configured such that a large number of columnar crystals 12 ′ overlap. Further, since the plurality of columnar crystals 12 'are provided integrally with the protrusion 10b, the entire outer surface of the protrusion 10b has a stepped structure due to the columnar crystal 12'.
　柱状結晶12’は、下端から上端までの長さが異なるように設けられている。これにより複数の柱状結晶12’は、その頂面が、単結晶基板10ａの主面10Ａからの高さ位置が異なるように配置されている。複数の柱状結晶12’は、その頂面が突起10ｂの上面10Ａと同じ高さ位置にまで延出されているもの、またはその頂面が突起10ｂの高さよりも低くなるように設けられているものを含んでいる。頂面が突起10ｂの高さよりも低く設けられた柱状結晶12’は、単結晶基板10ａの主面10Ａから頂面までの高さが、例えば0.5μｍ以上10μｍ以下となるように設定することができる。なお、柱状結晶12’の高さは、突起10ｂと単結晶基板10ａとの境界からの高さを用いればよい。 The columnar crystal 12 'is provided so that the length from the lower end to the upper end is different. Thereby, the plurality of columnar crystals 12 'are arranged such that the top surfaces thereof are different in height from the main surface 10A of the single crystal substrate 10a. The plurality of columnar crystals 12 'are provided such that the top surfaces thereof extend to the same height as the top surface 10A of the projections 10b, or the top surfaces thereof are lower than the heights of the projections 10b. Includes things. The columnar crystal 12 ′ having a top surface lower than the height of the protrusion 10b can be set such that the height from the main surface 10A to the top surface of the single crystal substrate 10a is, for example, 0.5 μm or more and 10 μm or less. it can. As the height of the columnar crystal 12 ', the height from the boundary between the protrusion 10b and the single crystal substrate 10a may be used.
　また柱状結晶12’は、柱状結晶12’の下方に位置する部分と、柱状結晶12’の上方に位置する部分とを比較した場合に、突起10ｂの下方にあるものほど、側面視したときの横幅が大きくなるように設定されている。柱状結晶12’は、側面視したときの横幅を、例えば50ｎｍ以上500ｎｍ以下に設定することができる。 In addition, when comparing the portion located below the columnar crystal 12 'with the portion located above the columnar crystal 12', the columnar crystal 12 'is located under the projection 10b when viewed from the side. The width is set to be large. The lateral width of the columnar crystal 12 'when viewed from the side can be set to, for example, 50 nm or more and 500 nm or less.
　柱状結晶12’は、突起10ｂの外側面に下方から上方にわたって様々な方向に向かって延びる複数の溝によって外側面の一部が突出するように、突起10ｂと一体的に設けられている。突起10ｂは、このような複数の柱状結晶12’が折り重なるように配置されることによるテクスチャー12を有している。 The columnar crystal 12 'is provided integrally with the protrusion 10b so that a part of the outer surface protrudes from the lower surface of the protrusion 10b in a variety of directions from the bottom to the top. The protrusion 10b has a texture 12 by arranging such a plurality of columnar crystals 12 'so as to be folded.
　突起10ｂの外側面に設けられる複数の溝は、例えば突起10ｂを横断面視したときに、Ｖ字状または四角形状など種々の形状で切り欠かれた形状からなる。突起10ｂの外側面から内部までの溝の深さは、例えば１ｎｍ以上１μｍ以下に設定することができる。また、複数の溝は、隣接する溝の間隔を、例えば10ｎｍ以上１μｍ以下に設定することができる。 The plurality of grooves provided on the outer surface of the protrusion 10b have shapes that are cut out in various shapes such as a V shape or a square shape when the protrusion 10b is viewed in cross section. The depth of the groove from the outer surface to the inside of the protrusion 10b can be set to 1 nm or more and 1 μm or less, for example. Moreover, the space | interval of an adjacent groove | channel can be set to 10 nm or more and 1 micrometer or less, for example.
　半導体成長用基板10上には、図３に示すように、光半導体層11が設けられている。光半導体層11は、第１半導体層11ａ、発光層11ｂおよび第２半導体層11ｃを順次積層することによって構成されている。なお、光半導体層11は、全体の厚みが例えば0.1μｍ以上20μｍ以下に形成されている。光半導体層11は、各層の屈折率が、窒化ガリウムを用いた場合には例えば1.80以上2.70以下に設定することができる。 An optical semiconductor layer 11 is provided on the semiconductor growth substrate 10 as shown in FIG. The optical semiconductor layer 11 is configured by sequentially laminating a first semiconductor layer 11a, a light emitting layer 11b, and a second semiconductor layer 11c. Note that the entire thickness of the optical semiconductor layer 11 is, for example, 0.1 μm or more and 20 μm or less. The refractive index of each layer of the optical semiconductor layer 11 can be set to, for example, 1.80 or more and 2.70 or less when gallium nitride is used.
　光半導体層11としては、III－Ｖ族半導体を用いることができる。III－Ｖ族半導体としては、III族窒化物半導体、ガリウム燐またはガリウムヒ素などを例示することができる。III族窒化物半導体としては、ボロン、アルミニウム、ガリウムまたはインジウムのうち少なくとも１つの窒化物からなる混晶を用いることができ、例えば窒化ガリウムを用いることができる。 As the optical semiconductor layer 11, a III-V semiconductor can be used. Examples of group III-V semiconductors include group III nitride semiconductors, gallium phosphide, gallium arsenide, and the like. As the group III nitride semiconductor, a mixed crystal made of at least one nitride of boron, aluminum, gallium, or indium can be used. For example, gallium nitride can be used.
　第１半導体層11ａは、突起10ｂを被覆するように単結晶基板10ａ上に設けられている。第１半導体層11ａは、単結晶基板10ａに結晶成長させて設けた場合には、厚み方向に転位13が延在するようになる。転位13は、半導体の結晶格子がずれることによって形成される。転位13には、例えば刃状転位またはらせん状転位などの種類がある。転位13すなわち結晶格子のずれは、第１半導体層11ａと単結晶基板10ａとが異なる格子定数を有することにより、起こりやすくなっている。なお、第１半導体層11ａは、厚みが１μｍ以上10μｍ以下に設定されている。 The first semiconductor layer 11a is provided on the single crystal substrate 10a so as to cover the protrusion 10b. When the first semiconductor layer 11a is provided by crystal growth on the single crystal substrate 10a, the dislocations 13 extend in the thickness direction. The dislocations 13 are formed by shifting the crystal lattice of the semiconductor. Examples of the dislocation 13 include edge dislocations and helical dislocations. Dislocations 13, that is, crystal lattice misalignment, are likely to occur because the first semiconductor layer 11a and the single crystal substrate 10a have different lattice constants. The first semiconductor layer 11a is set to have a thickness of 1 μm or more and 10 μm or less.
　発光層11ｂは、第１半導体層11ａ上に設けられている。発光層11ｂは、禁制帯幅の広い障壁層と禁制帯幅の狭い井戸層とからなる量子井戸構造が複数回繰り返し規則的に積層された多層量子井戸構造（ＭＱＷ）を用いることができる。障壁層と井戸層としては、インジウムとガリウムの窒化物からなる混晶においてインジウムとガリウムの組成比を調整したものを用いることができる。このように構成された発光層11ｂでは、例えば350ｎｍ以上600ｎｍ以下の波長の光を発光する。発光層11ｂは、第１半導体層11ａ上に設けられることから、第１半導体層11ａに転位13が延在する場合にはその転位13が発光層11ｂにも引き継がれやすくなる。 The light emitting layer 11b is provided on the first semiconductor layer 11a. As the light emitting layer 11b, a multilayer quantum well structure (MQW) in which a quantum well structure composed of a barrier layer with a wide forbidden band and a well layer with a narrow forbidden band is regularly stacked a plurality of times can be used. As the barrier layer and the well layer, a mixed crystal composed of nitride of indium and gallium with the composition ratio of indium and gallium adjusted can be used. The light emitting layer 11b configured as described above emits light having a wavelength of 350 nm to 600 nm, for example. Since the light emitting layer 11b is provided on the first semiconductor layer 11a, when the dislocation 13 extends in the first semiconductor layer 11a, the dislocation 13 is easily transferred to the light emitting layer 11b.
　第２半導体層11ｃは、発光層11ｂ上に設けられている。第２半導体層11ｃは、電子か正孔のどちらかを多数キャリアとすることにより、第１半導体層11ａとは逆導電型を呈するように設定されている。半導体層に導電型を付与する方法としては、例えばマグネシウムまたはシリコンを不純物として混ぜる方法を用いることができる。 The second semiconductor layer 11c is provided on the light emitting layer 11b. The second semiconductor layer 11c is set so as to exhibit an opposite conductivity type to the first semiconductor layer 11a by using either electrons or holes as majority carriers. As a method for imparting conductivity type to the semiconductor layer, for example, a method of mixing magnesium or silicon as an impurity can be used.
　第１電極層７は第１半導体層11ａ上に、第２電極層８は第２半導体層11ｃ上に、それぞれ設けられている。このような２つの電極層により、光半導体層11に電圧が印加される。電極層の材料としては、例えば、アルミニウム、チタン、ニッケル、クロム、インジウム、錫、モリブデン、銀、金、ニオブ、タンタル、バナジウム、白金、鉛またはベリリウムなどの金属、酸化錫、酸化インジウムもしくは酸化インジウム錫などの酸化物、または金－シリコン合金、金－ゲルマニウム合金、金－亜鉛合金もしくは金－ベリリウム合金などの合金膜を好適に用いることができる。また、このような電極層は、それぞれ上記材質の中から選択した層を多層積層しても構わない。 The first electrode layer 7 is provided on the first semiconductor layer 11a, and the second electrode layer 8 is provided on the second semiconductor layer 11c. A voltage is applied to the optical semiconductor layer 11 by such two electrode layers. Examples of the material for the electrode layer include aluminum, titanium, nickel, chromium, indium, tin, molybdenum, silver, gold, niobium, tantalum, vanadium, platinum, lead, and beryllium, tin oxide, indium oxide, and indium oxide. An oxide such as tin, or an alloy film such as a gold-silicon alloy, a gold-germanium alloy, a gold-zinc alloy, or a gold-beryllium alloy can be preferably used. In addition, such an electrode layer may be formed by laminating layers selected from the above materials.
　このように光半導体層11を、突起10ｂを有する単結晶基板10ａすなわち半導体成長用基板10上に結晶成長させた場合には、単結晶基板10ａから光半導体層11内に延在する転位13の数を制御することができる。 Thus, when the optical semiconductor layer 11 is crystal-grown on the single crystal substrate 10a having the protrusions 10b, that is, the semiconductor growth substrate 10, the dislocations 13 extending from the single crystal substrate 10a into the optical semiconductor layer 11 are formed. The number can be controlled.
　本実施形態においては、突起10ｂの外側面に、複数の柱状結晶12’から構成されているテクスチャー12を有している。そのため、突起10ｂの外側面の表面において、外側面の上下方向および外周方向に外側面を荒らして、単結晶基板10ａの結晶格子の結晶面を不揃いにすることができる。そのため、半導体成長用基板10上に光半導体層11を成長させた場合は、荒れた外側面には結晶を成長しにくくなることから、突起10ｂの外側面に結晶を成長させにくくすることができる。 In this embodiment, the outer surface of the protrusion 10b has a texture 12 composed of a plurality of columnar crystals 12 '. Therefore, on the surface of the outer surface of the protrusion 10b, the outer surface can be roughened in the vertical direction and the outer peripheral direction of the outer surface, and the crystal planes of the crystal lattice of the single crystal substrate 10a can be made uneven. Therefore, when the optical semiconductor layer 11 is grown on the semiconductor growth substrate 10, it is difficult to grow a crystal on the rough outer surface, so that it is difficult to grow a crystal on the outer surface of the protrusion 10b. .
　具体的には、光半導体層11内に位置する半導体成長用基板10から延びる転位13を複数有し、単結晶基板10ａの主面10Ａから延びる転位13の数よりも突起10ｂの外側面から延びる転位13の数が少なくなっている。 Specifically, there are a plurality of dislocations 13 extending from the semiconductor growth substrate 10 located in the optical semiconductor layer 11, and the number of dislocations 13 extending from the main surface 10A of the single crystal substrate 10a extends from the outer surface of the protrusion 10b. The number of dislocations 13 is decreasing.
　その結果、突起10ｂの上面10Ａ’すなわち結晶成長面で結晶成長させつつ、突起10ｂの外側面では結晶成長させにくくすることができる。そのため、突起10ｂの外側面から延びる転位13を少なくすることができ、光半導体層11の厚み方向に延在する転位13の数を減らすことができる。 As a result, it is possible to make the crystal growth difficult on the outer surface of the protrusion 10b while the crystal is grown on the upper surface 10A 'of the protrusion 10b, that is, the crystal growth surface. Therefore, the number of dislocations 13 extending from the outer surface of the protrusion 10b can be reduced, and the number of dislocations 13 extending in the thickness direction of the optical semiconductor layer 11 can be reduced.
　換言すると、光半導体層11および半導体成長用基板10を平面透視して、突起10ｂの上面10Ａ’と重ならない第１領域14における光半導体層11の厚み方向に延在する転位13の数を減らすことができる。その結果、第１領域14の光半導体層11の結晶品質を向上させることができ、発光素子１で発する光の発光効率を向上させることができる。なお、光半導体層11および半導体成長用基板10を平面透視して、突起10ｂの上面10Ａ’と重ならない領域は第１領域14を、突起10ｂの上面10Ａ’と重なる領域は第２領域15をそれぞれ示している。 In other words, the number of dislocations 13 extending in the thickness direction of the optical semiconductor layer 11 in the first region 14 that does not overlap the upper surface 10A ′ of the protrusion 10b is reduced when the optical semiconductor layer 11 and the semiconductor growth substrate 10 are seen through in plan. be able to. As a result, the crystal quality of the optical semiconductor layer 11 in the first region 14 can be improved, and the light emission efficiency of the light emitted from the light emitting element 1 can be improved. When the optical semiconductor layer 11 and the semiconductor growth substrate 10 are seen in a plan view, a region that does not overlap the upper surface 10A ′ of the protrusion 10b is a first region 14, and a region that overlaps the upper surface 10A ′ of the protrusion 10b is a second region 15. Each is shown.
　一方、突起の外側面にかかるテクスチャーを有しない構成では、突起の外側面の結晶面が揃いやすくなる。そのため、突起の外側面にも光半導体層が成長することによって突起の外側面から延びる転位が発生し、光半導体層の厚み方向に転位が延びることとなる。その結果、光半導体層内に転位が多数存在することとなり、発光素子の発光効率の低下を招きやすくなる。さらに、光半導体層の厚み方向に多くの転位が延在することにより、発光素子に電圧を印加した際に、かかる転位が光半導体層のバルク抵抗より小さい電気抵抗値を有するようになって短絡や静電破壊などを起こしやすくなり、信頼性の低下を招きやすくなる。 On the other hand, in the configuration having no texture on the outer surface of the protrusion, the crystal surface of the outer surface of the protrusion is easily aligned. For this reason, the optical semiconductor layer grows on the outer surface of the protrusion to generate dislocations extending from the outer surface of the protrusions, and the dislocations extend in the thickness direction of the optical semiconductor layer. As a result, a large number of dislocations exist in the optical semiconductor layer, and the light emission efficiency of the light emitting element is likely to be lowered. Furthermore, since many dislocations extend in the thickness direction of the optical semiconductor layer, when a voltage is applied to the light-emitting element, the dislocations have an electric resistance value smaller than the bulk resistance of the optical semiconductor layer and are short-circuited. And electrostatic breakdown are likely to occur, leading to a decrease in reliability.
　また、突起10ｂの外側面のテクスチャー12が、複数の柱状結晶12’によって構成されている。そのため、光半導体層11で発した光を単結晶基板10ａ側から取り出す際に、光半導体層11で発した光が半導体成長用基板10との界面で光半導体層11側に反射されにくくすることができる。そのため、発光素子１の光取り出し効率を向上させることができる。 Further, the texture 12 on the outer surface of the protrusion 10b is composed of a plurality of columnar crystals 12 '. Therefore, when the light emitted from the optical semiconductor layer 11 is extracted from the single crystal substrate 10a side, the light emitted from the optical semiconductor layer 11 is less likely to be reflected to the optical semiconductor layer 11 side at the interface with the semiconductor growth substrate 10. Can do. Therefore, the light extraction efficiency of the light emitting element 1 can be improved.
　さらに、第１領域14の光半導体層11で発した光が、突起10ｂの外側面から単結晶基板10ａに入射しやすくすることができる。このように光半導体層11から単結晶基板10ａに入射しやすくなることにより、入射角よりも屈折角が大きくなるように屈折させることができるため、光半導体層11の第１領域14で発した光を第２領域15方向に屈折させることができる。そのことから、第１領域14の光半導体層11の発光効率が向上された場合でも、発光素子１の発光むらを抑制することができる。 Furthermore, the light emitted from the optical semiconductor layer 11 in the first region 14 can be easily incident on the single crystal substrate 10a from the outer surface of the protrusion 10b. Since the light semiconductor layer 11 is easily incident on the single crystal substrate 10a in this manner, the light can be refracted so that the refraction angle is larger than the incident angle. Light can be refracted in the direction of the second region 15. Therefore, even when the light emission efficiency of the optical semiconductor layer 11 in the first region 14 is improved, the light emission unevenness of the light emitting element 1 can be suppressed.
　このように本発明の実施形態にかかる半導体成長用基板10を用いることにより、光半導体層11の結晶品質を向上させるとともに、光取り出し効率を向上させることが可能な発光素子１を提供することができる。 As described above, by using the semiconductor growth substrate 10 according to the embodiment of the present invention, it is possible to provide the light emitting element 1 capable of improving the crystal quality of the optical semiconductor layer 11 and improving the light extraction efficiency. it can.
　（発光素子の変形例１）
　多数の柱状結晶12’のうち、単結晶基板10ａの主面10Ａからの高さ位置が突起10ｂの側面の途中までのものは、上方へ向かうにつれて先端が部分的に小さくなっていてもよい。具体的に、柱状結晶12’は、平面透視して外郭断面積が上方へ向かうにつれて小さくなり、柱状結晶12’を側面視して、上方へ向かうにつれて柱状結晶12’の幅が小さくなるように設けられている。このように柱状結晶12’の先端が上方へ向かうにつれて小さくなっていることにより、柱状結晶12’の頂面が、単結晶基板10ａの主面10Ａに対して傾斜するようになっている。 (Modification 1 of light emitting element)
Among the many columnar crystals 12 ', the tip of the single crystal substrate 10a whose height position from the main surface 10A is partway along the side surface of the projection 10b may be partially reduced in the upward direction. Specifically, the columnar crystal 12 ′ is smaller as the outer cross-sectional area is upward when viewed in plan, and the width of the columnar crystal 12 ′ is smaller as viewed from the side when viewed from the side. Is provided. Thus, the top surface of the columnar crystal 12 'is inclined with respect to the main surface 10A of the single crystal substrate 10a by decreasing the tip of the columnar crystal 12' upward.
　柱状結晶12’は、上方へ向かうにつれて先端が小さくなっているときには、発光層11ｂで発した光が単結晶基板10ａとの界面で臨界角よりも小さい角度で入射しやすいものにすることができる。そのため、光半導体層11と単結晶基板10ａとの界面でさらに反射されにくくすることができる。その結果、光半導体層11で発した光を単結晶基板10ａ側から取り出す際に、発光素子１の光取出し効率を向上させることができる。 When the tip of the columnar crystal 12 ′ becomes smaller toward the upper side, the light emitted from the light emitting layer 11b can be easily incident at an angle smaller than the critical angle at the interface with the single crystal substrate 10a. . Therefore, it can be made more difficult to be reflected at the interface between the optical semiconductor layer 11 and the single crystal substrate 10a. As a result, when the light emitted from the optical semiconductor layer 11 is extracted from the single crystal substrate 10a side, the light extraction efficiency of the light emitting element 1 can be improved.
　また、光半導体層11の第１領域14で発した光を、かかるテクスチャー12によって、第２領域15に入射させることができるため、発光むらをさらに改善することができる。 Further, since the light emitted from the first region 14 of the optical semiconductor layer 11 can be made incident on the second region 15 by the texture 12, unevenness in light emission can be further improved.
　なお、柱状結晶12’の先端が上方へ向かうにつれて部分的に小さくなっている構造としては、柱状結晶12’は、横断面積が上方に向かうにつれて小さくなっている構造を用いればよい。そのような構造としては、例えば柱状結晶12’の先端（頂面）が上方に配置されたテーパー形状などを用いることができる。 As the structure in which the tip of the columnar crystal 12 ′ is partially reduced as it goes upward, the columnar crystal 12 ′ may have a structure that becomes smaller as the cross-sectional area goes upward. As such a structure, for example, a tapered shape in which the tip (top surface) of the columnar crystal 12 'is disposed above can be used.
　（発光素子の変形例２）
　単結晶基板10の主面10Ａに、図４（ａ）に示すように、***した突起10ｂを取り囲むように環状の凹部16が形成されている。このような凹部16は、単結晶基板10の主面10Ａから凹部16の下端部までの深さが、例えば0.1μｍ以上３μｍ以下となるように設けることができる。また、突起10ｂを取り囲むように形成された環状の凹部16は、突起10ｂの外側面と接するように配置されている。そのため、突起10ｂは、外側面の下端が凹部16の下端部となるように、上方に***するように設けられている。 (Modification 2 of light emitting element)
As shown in FIG. 4A, an annular recess 16 is formed on the main surface 10A of the single crystal substrate 10 so as to surround the raised protrusion 10b. Such a recess 16 can be provided such that the depth from the main surface 10A of the single crystal substrate 10 to the lower end of the recess 16 is, for example, not less than 0.1 μm and not more than 3 μm. An annular recess 16 formed so as to surround the protrusion 10b is disposed so as to be in contact with the outer surface of the protrusion 10b. Therefore, the protrusion 10b is provided so as to protrude upward so that the lower end of the outer surface becomes the lower end of the recess 16.
　このような凹部16を単結晶基板10ａの主面10Ａに形成することにより、発光層11ｂで発した光が凹部16で光半導体層11側に反射されにくいものにすることができるため、発光層11ｂで発した光を単結晶基板10ａ側から効率的に取り出すことができる。その結果、発光素子１の光取り出し効率を向上させることができる。 By forming such a recess 16 in the main surface 10A of the single crystal substrate 10a, the light emitted from the light emitting layer 11b can be made difficult to be reflected by the recess 16 toward the optical semiconductor layer 11 side. The light emitted from 11b can be efficiently extracted from the single crystal substrate 10a side. As a result, the light extraction efficiency of the light emitting element 1 can be improved.
　［発光素子の製造方法］
　次に、発光素子１の製造方法を説明する。図５から図10は、発光素子１の製造方法を説明するための断面図であり、図２に示す発光素子１のＡ―Ａ’線における断面に相当する部分を示している。 [Method for Manufacturing Light-Emitting Element]
Next, a method for manufacturing the light emitting element 1 will be described. 5 to 10 are cross-sectional views for explaining a method for manufacturing the light-emitting element 1, and show a portion corresponding to a cross section taken along line AA ′ of the light-emitting element 1 shown in FIG.
　（半導体成長用基板の製造工程）
　図５に示すように、単結晶基板10ａ上に、単結晶基板10ａの一部が露出した貫通孔17ａを有するレジストパターン17を形成する。レジストパターン17としては、後に容易に除去することができる材料を選択することができ、厚みは例えば0.1μｍ以上10μｍ以下に設定することができる。このようなレジストパターン17は、従来のフォトレジスト法などによって設けることができる。 (Manufacturing process of substrate for semiconductor growth)
As shown in FIG. 5, a resist pattern 17 having a through hole 17a in which a part of the single crystal substrate 10a is exposed is formed on the single crystal substrate 10a. As the resist pattern 17, a material that can be easily removed later can be selected, and the thickness can be set to 0.1 μm or more and 10 μm or less, for example. Such a resist pattern 17 can be provided by a conventional photoresist method or the like.
　このような貫通孔17を有するレジストパターン17を形成することにより、単結晶基板10ａの上面10Ａ’の一部を露出させることができる。なお、単結晶基板10ａの一部が露出した領域を、第１露出領域18ａとする。貫通孔17の平面形状は、突起10ｂの上面10Ａ’の形状に設定すればよい。 By forming the resist pattern 17 having such a through hole 17, a part of the upper surface 10A 'of the single crystal substrate 10a can be exposed. Note that a region where a part of the single crystal substrate 10a is exposed is defined as a first exposed region 18a. The planar shape of the through hole 17 may be set to the shape of the upper surface 10A 'of the protrusion 10b.
　次に、図６に示すように、単結晶基板10ａの第１露出領域18ａにマスク材料を埋めることによって積層膜19を形成する。積層膜19の厚みは、マスク材料とエッチングする深さとの選択比から設定すればよく、例えば400ｎｍ以上900ｎｍ以下に設定することができる。なお、単結晶基板10ａとしてサファイアを用いてドライエッチングを行なう場合は、サファイアと反応しやすい塩素系ガスを反応ガスとして好適に用いることができるが、この場合のマスク材料としては、チタン、ニッケルもしくはクロムなどの金属材料または酸化シリコンなどの耐塩素性の無機材料を用いることが望ましい。 Next, as shown in FIG. 6, a laminated film 19 is formed by filling a mask material in the first exposed region 18a of the single crystal substrate 10a. The thickness of the laminated film 19 may be set from the selection ratio between the mask material and the etching depth, and can be set to 400 nm or more and 900 nm or less, for example. In the case of performing dry etching using sapphire as the single crystal substrate 10a, a chlorine-based gas that easily reacts with sapphire can be suitably used as a reactive gas. In this case, as a mask material, titanium, nickel, or It is desirable to use a metal material such as chromium or a chlorine-resistant inorganic material such as silicon oxide.
　マスク材料を単結晶基板10ａ上に積層する方法としては、例えばスパッタリング法、蒸着法などを用いることができ、スパッタリング法を用いた場合には、貫通孔17ａに被覆性よくマスク材料を埋めることができる。 As a method of laminating the mask material on the single crystal substrate 10a, for example, a sputtering method, a vapor deposition method or the like can be used. When the sputtering method is used, the mask material can be buried in the through-hole 17a with good coverage. it can.
　また、異なるマスク材料を複数積層することによって積層膜19を形成してもよい。積層膜19を異なるマスク材料を積層することによって設けることにより、後述する単結晶基板10ａのエッチングの際に、エッチング速度をそれぞれのマスク材料の層によって変えることができる。このようにエッチング速度を変えて単結晶基板10ａをエッチングすることにより、単結晶基板10ａに突起10ｂを形成するとともに、突起10ｂに複数の柱状結晶12’から構成されているテクスチャー12を形成することができる。 Further, the laminated film 19 may be formed by laminating a plurality of different mask materials. By providing the laminated film 19 by laminating different mask materials, the etching rate can be changed depending on the layer of each mask material when the single crystal substrate 10a described later is etched. By thus etching the single crystal substrate 10a while changing the etching rate, the protrusion 10b is formed on the single crystal substrate 10a, and the texture 12 composed of a plurality of columnar crystals 12 'is formed on the protrusion 10b. Can do.
　その後、図７に示すように、レジストパターン17を除去することにより、単結晶基板10ａの一部を露出させた第２露出領域18ｂを有するマスクパターン20を形成する。本実施形態では、マスク材料として金属材料を用いてマスクパターン20を形成することにより、レジストパターン17を除去した際にマスクパターン20を構成するそれぞれのマスク20ａの外周面の一部も合わせて除去される。 Thereafter, as shown in FIG. 7, the resist pattern 17 is removed to form a mask pattern 20 having a second exposed region 18b in which a part of the single crystal substrate 10a is exposed. In this embodiment, by forming a mask pattern 20 using a metal material as a mask material, when the resist pattern 17 is removed, part of the outer peripheral surface of each mask 20a constituting the mask pattern 20 is also removed. Is done.
　そのため、マスクパターン20を構成するそれぞれのマスク20ａの外周面に複数の溝が形成される。このような複数の溝は、マスク20ａの下端から上端に沿って設けられている。溝の幅は、例えば10ｎｍ以上１μｍ以下となるように設定することができる。このようにマスク20ａの外周面に複数の溝が形成されやすいのは、金属材料を用いたマスクパターン20が結晶塊を有しているためである。 Therefore, a plurality of grooves are formed on the outer peripheral surface of each mask 20a constituting the mask pattern 20. Such a plurality of grooves are provided from the lower end to the upper end of the mask 20a. The width of the groove can be set to be 10 nm or more and 1 μm or less, for example. The reason why the plurality of grooves are easily formed on the outer peripheral surface of the mask 20a in this way is that the mask pattern 20 using a metal material has crystal lumps.
　次に、単結晶基板10ａの第２露出領域18ｂおよびマスクパターン20をエッチングによって厚み方向に単結晶基板10ａを一部除去する。これにより、単結晶基板10ａに突起10ｂを設けるとともに、突起10ｂの外側面に複数の柱状結晶12’によって構成されるテクスチャー12を形成する。 Next, the single crystal substrate 10a is partially removed in the thickness direction by etching the second exposed region 18b and the mask pattern 20 of the single crystal substrate 10a. Thereby, the protrusion 10b is provided on the single crystal substrate 10a, and the texture 12 composed of the plurality of columnar crystals 12 'is formed on the outer surface of the protrusion 10b.
　このようなエッチングとしては、ウエットエッチングやドライエッチングなどを用いることができる。単結晶基板10ａとしてサファイアを用いてドライエッチングを行なう場合には、サファイアと反応しやすい塩素系ガス雰囲気中でドライエッチングを行なうことによって生産性を向上させることができる。 As such etching, wet etching, dry etching, or the like can be used. When dry etching is performed using sapphire as the single crystal substrate 10a, productivity can be improved by performing dry etching in a chlorine-based gas atmosphere that easily reacts with sapphire.
　突起10ｂの外側面に設けるテクスチャー12は、例えば単結晶基板10ａに金属材料からなるマスクパターン20を形成した場合であれば、単結晶基板10ａの上方からドライエッチングをすることによって形成することができる。これは、マスク20ａの外周面に形成された溝および結晶塊で単結晶基板10ａのエッチング速度を部分的に変化させることができるためである。 For example, when the mask pattern 20 made of a metal material is formed on the single crystal substrate 10a, the texture 12 provided on the outer surface of the protrusion 10b can be formed by dry etching from above the single crystal substrate 10a. . This is because the etching rate of the single crystal substrate 10a can be partially changed by the grooves and crystal lumps formed on the outer peripheral surface of the mask 20a.
　この後、マスクパターン20をエッチングなどで除去することにより、図８に示すように、突起10ｂの外側面に複数の柱状結晶12’により構成されるテクスチャー12を形成した半導体成長用基板10を作製することができる。 Thereafter, by removing the mask pattern 20 by etching or the like, as shown in FIG. 8, a semiconductor growth substrate 10 is produced in which a texture 12 composed of a plurality of columnar crystals 12 'is formed on the outer surface of the protrusion 10b. can do.
　（発光素子の製造工程）
　次に、図９に示すように、光半導体層11を、半導体成長用基板10の突起10ｂ上に横方向成長を用いて形成する。光半導体層11を横方向成長させる方法としては、それぞれの層において組成比、成長温度および成長圧力などの成長条件を調整すればよい。このように成長条件を調整することにより、第１半導体層11ａの成長速度を単結晶基板10ａの主面10Ａに対する垂直方向と水平方向とで制御することができ、第１半導体層11ａを横方向成長させることができる。 (Manufacturing process of light emitting device)
Next, as shown in FIG. 9, the optical semiconductor layer 11 is formed on the protrusion 10b of the semiconductor growth substrate 10 by lateral growth. As a method for laterally growing the optical semiconductor layer 11, growth conditions such as a composition ratio, a growth temperature, and a growth pressure may be adjusted in each layer. By adjusting the growth conditions in this manner, the growth rate of the first semiconductor layer 11a can be controlled in the vertical direction and the horizontal direction with respect to the main surface 10A of the single crystal substrate 10a, and the first semiconductor layer 11a is controlled in the horizontal direction. Can be grown.
　突起10ｂの外側面には複数の柱状結晶12’によって構成されるテクスチャー12が設けられている。そのため、半導体成長用基板10上に第１半導体層11ａを成長させる場合に、突起10ｂの外側面には第１半導体層11ａが成長しにくくなっている。すなわち、突起10ｂの外側面から第１半導体層11ａの厚み方向に延びる転位13が発生することを抑制することができる。半導体成長用基板10上に第１半導体層11ａを横方向成長させた場合には、露出した単結晶基板10ａの主面10Ａに第１半導体層11ａが成長する。その結果、隣接する突起10ｂとの間の空間が、単結晶基板10ｂの主面10Ａ上に成長した第１半導体層11ａによって埋められる。その後、第１半導体層11ａ上に、発光層11ｂおよび第２半導体層11ｃを成長させる。 A texture 12 composed of a plurality of columnar crystals 12 'is provided on the outer surface of the protrusion 10b. Therefore, when the first semiconductor layer 11a is grown on the semiconductor growth substrate 10, the first semiconductor layer 11a is difficult to grow on the outer surface of the protrusion 10b. That is, it is possible to suppress the occurrence of dislocations 13 extending in the thickness direction of the first semiconductor layer 11a from the outer surface of the protrusion 10b. When the first semiconductor layer 11a is laterally grown on the semiconductor growth substrate 10, the first semiconductor layer 11a grows on the main surface 10A of the exposed single crystal substrate 10a. As a result, the space between the adjacent protrusions 10b is filled with the first semiconductor layer 11a grown on the main surface 10A of the single crystal substrate 10b. Thereafter, the light emitting layer 11b and the second semiconductor layer 11c are grown on the first semiconductor layer 11a.
　光半導体層11すなわち第１半導体層11ａ、発光層11ｂおよび第２半導体層11ｃを成長させる方法として、有機金属気相成長法、分子線エピタキシー法、ハイドライド気相成長法またはパルスレーザデポジション法などを用いることができる。 As a method for growing the optical semiconductor layer 11, that is, the first semiconductor layer 11a, the light emitting layer 11b, and the second semiconductor layer 11c, a metal organic chemical vapor deposition method, a molecular beam epitaxy method, a hydride vapor deposition method, a pulsed laser deposition method, or the like Can be used.
　このように第１半導体層11ａを横方向成長させることにより、発光層11ｂにまで延在する転位13の数および位置を制御しつつ成長速度を早めることができるため、光半導体層11の生産性を向上させることができる。 By growing the first semiconductor layer 11a in the lateral direction in this way, the growth rate can be increased while controlling the number and position of the dislocations 13 extending to the light emitting layer 11b, so that the productivity of the optical semiconductor layer 11 can be increased. Can be improved.
　（半導体成長用基板の製造方法の変形例１）
　突起10ｂの外側面のテクスチャー12が、上方へ向かうにつれて先端が小さくなった柱状結晶12’によって構成されていてもよい。このように柱状結晶12’を形成した場合は、先端が上方に向かうにつれて小さくなっていることから、隣接する突起10ｂ同士の間の空間を、単結晶基板10ａの主面10Ａから半導体を密着性よく成長させて埋めることができる。 (Variation 1 of manufacturing method of semiconductor growth substrate)
The texture 12 on the outer surface of the protrusion 10b may be constituted by a columnar crystal 12 ′ whose tip is reduced in the upward direction. When the columnar crystal 12 'is formed in this way, the tip becomes smaller as it goes upward, so that the space between the adjacent projections 10b can be adhered to the semiconductor from the main surface 10A of the single crystal substrate 10a. Can grow well and fill.
　その結果、光半導体層11と単結晶基板10ａとの間に、単結晶基板10ａよりも屈折率が小さい空隙が形成されるのを抑制することができるため、光半導体層11で発した光を、効率よく単結晶基板10ａ内に通過させることができる。そのため、発光素子１の光取り出し効率を向上させることができる。 As a result, it is possible to suppress the formation of a void having a refractive index smaller than that of the single crystal substrate 10a between the optical semiconductor layer 11 and the single crystal substrate 10a. Thus, it can be efficiently passed through the single crystal substrate 10a. Therefore, the light extraction efficiency of the light emitting element 1 can be improved.
　（半導体成長用基板の製造方法の変形例２）
　図４（ａ）に示すように、単結晶基板10ａの主面10Ａに、突起10ｂを取り囲むような凹部16を形成してもよい。このように単結晶基板10ａの主面10Ａに凹部16を形成した場合は、隣接する２つの突起10ｂの間の単結晶基板10ａ表面が断面視して平坦とならなくなるため、かかる単結晶基板10ａの表面で第１半導体層11ａを結晶成長させにくくすることができる。その結果、隣接する２つの突起10ｂの間の単結晶基板10表面から延びる転位を減らすことができ、光半導体層11の第２領域における結晶品質をさらに向上させることができる。 (Variation 2 of manufacturing method of substrate for semiconductor growth)
As shown in FIG. 4A, a recess 16 surrounding the protrusion 10b may be formed on the main surface 10A of the single crystal substrate 10a. When the concave portion 16 is formed on the main surface 10A of the single crystal substrate 10a in this way, the surface of the single crystal substrate 10a between the two adjacent projections 10b does not become flat when viewed in cross section. It is possible to make it difficult for the first semiconductor layer 11a to grow on the surface. As a result, dislocations extending from the surface of the single crystal substrate 10 between two adjacent protrusions 10b can be reduced, and the crystal quality in the second region of the optical semiconductor layer 11 can be further improved.
　（半導体成長用基板の製造方法の変形例３）
　金属材料からなるマスクパターン20を設ける際に、逆メサ形状の端面17’を持つレジストパターン17を用いてもよい。このように逆メサ形状の端面17’を持つレジストパターン17を用いて、突起10ｂを設ける工程について図９を用いて説明する。 (Modification 3 of manufacturing method of substrate for semiconductor growth)
When the mask pattern 20 made of a metal material is provided, a resist pattern 17 having an inverted mesa-shaped end face 17 ′ may be used. A process of providing the protrusion 10b using the resist pattern 17 having the inverted mesa-shaped end face 17 ′ will be described with reference to FIG.
　まず、図９（ａ）に示すように、レジストパターン17として感光性材料を用いた場合には、感光性材料を感光させて固化させることによってレジストパターン17を形成する際に、端面17’を逆メサ形状とすればよい。端面17’を逆メサ形状とする方法としては、感光性材料を単結晶基板10ａの上面10Ａ’上に塗布し、上面10Ａ’に対して垂直な方向から光を照射する方法を用いることができる。このように感光性材料に光を照射することにより、照射した光が外部と感光性材料との界面で屈折して感光性材料内に進入する。 First, as shown in FIG. 9A, when a photosensitive material is used as the resist pattern 17, the end face 17 ′ is formed when the resist pattern 17 is formed by exposing the photosensitive material to solidification. A reverse mesa shape may be used. As a method of making the end face 17 ′ into an inverted mesa shape, a method of applying a photosensitive material on the upper surface 10A ′ of the single crystal substrate 10a and irradiating light from a direction perpendicular to the upper surface 10A ′ can be used. . By irradiating light to the photosensitive material in this way, the irradiated light is refracted at the interface between the outside and the photosensitive material and enters the photosensitive material.
　そのため、感光性材料内に入った光は、単結晶基板10ａの上面10Ａ’に対して傾斜するようになる。逆メサ形状の端面17’としては、レジストパターン17の端面17’と単結晶基板10ａの主面10Ａとの内角を、例えば95°以上150°以下となるように設定することができる。逆メサ形状の端面17’は、感光性材料に照射する光の強度および感光性材料の屈折率を変化させることにより、単結晶基板10ａの主面10Ａとの内角を変化させることができる。 Therefore, light entering the photosensitive material is inclined with respect to the upper surface 10A 'of the single crystal substrate 10a. The inverted mesa-shaped end surface 17 'can be set so that the inner angle between the end surface 17' of the resist pattern 17 and the main surface 10A of the single crystal substrate 10a is, for example, 95 ° to 150 °. The inverted mesa-shaped end face 17 'can change the internal angle with the main surface 10A of the single crystal substrate 10a by changing the intensity of light applied to the photosensitive material and the refractive index of the photosensitive material.
　次に、図９（ｂ）に示すように、マスクパターン20となる金属材料を、単結晶基板10ａの上面10Ａおよびレジストパターン17上に金属層20’として積層する。この際に、レジストパターン17の端面17’が逆メサ形状であることから、積層する金属材料を段切れさせて、単結晶基板10ａの上面10ａにマスク20ａを形成することができる。また、段切れされたマスク20ａが設けられることにより、マスク20ａの上下方向の断面視形状が台形状または半円状となっている。 Next, as shown in FIG. 9B, a metal material to be the mask pattern 20 is laminated on the upper surface 10A of the single crystal substrate 10a and the resist pattern 17 as a metal layer 20 '. At this time, since the end face 17 ′ of the resist pattern 17 has an inverted mesa shape, the metal material to be laminated can be cut off to form the mask 20 a on the upper surface 10 a of the single crystal substrate 10 a. Further, by providing the stepped mask 20a, the cross-sectional shape in the vertical direction of the mask 20a is trapezoidal or semicircular.
　このような金属材料としては、レジストパターン17の厚みに対して、例えば10％以上70％以下となるように設定することができる。金属材料を積層する方法としては、例えば蒸着法またはスパッタリング法を用いることができる。その後、図９（ｃ）に示すように、レジストパターン17を除去して、単結晶基板10ａの上面10Ａにマスクパターン20を形成する。 Such a metal material can be set to be, for example, 10% or more and 70% or less with respect to the thickness of the resist pattern 17. As a method for laminating the metal material, for example, an evaporation method or a sputtering method can be used. Thereafter, as shown in FIG. 9C, the resist pattern 17 is removed, and a mask pattern 20 is formed on the upper surface 10A of the single crystal substrate 10a.
　さらにその後、単結晶基板10ａの上面10Ａ側からエッチングすることにより、図８に示すように、突起10ｂを形成するとともに、突起10ｂの外側面に複数の柱状結晶12’から構成されるテクスチャー12を形成することができる。このように金属材料からなるマスクパターン20をエッチングして、突起10ｂの外側面にテクスチャー12を形成することができるのは、マスク20ａの上下方向の断面視形状が台形状となっているとともに金属材料中に結晶塊を有しているため、エッチング速度にばらつきがでるためである。 Thereafter, by etching from the upper surface 10A side of the single crystal substrate 10a, as shown in FIG. 8, a protrusion 10b is formed, and a texture 12 composed of a plurality of columnar crystals 12 'is formed on the outer surface of the protrusion 10b. Can be formed. The mask pattern 20 made of a metal material can be etched in this way to form the texture 12 on the outer surface of the protrusion 10b. The mask 20a has a trapezoidal cross-sectional shape in the vertical direction. This is because the etching rate varies because the material has crystal lumps.
　このように、逆メサ形状のレジストパターン17を用いることにより、突起10ｂの外側面に複数の柱状結晶12’によって構成されるテクスチャー12を容易に形成することができる。 Thus, by using the resist pattern 17 having the inverted mesa shape, the texture 12 composed of the plurality of columnar crystals 12 'can be easily formed on the outer surface of the protrusion 10b.
　（半導体成長用基板の製造方法の変形例４）
　単結晶基板10ａの主面10Ａに、図１１に示すような***した突起10ｂを取り囲むように環状の凹部16を形成してもよい。このような凹部16は、例えばマスクパターン20として金属材料を用いてドライエッチングを行なうことによって形成することができる。 (Modification 4 of manufacturing method of substrate for semiconductor growth)
An annular recess 16 may be formed on the main surface 10A of the single crystal substrate 10a so as to surround the raised protrusion 10b as shown in FIG. Such a recess 16 can be formed, for example, by performing dry etching using a metal material as the mask pattern 20.
　このようにマスクパターン20として金属材料を用いると、単結晶基板10ａのエッチングを行なうイオンがマスク20ａの側面方向に進みやすくなる。その結果、突起10ｂの周りを取り囲む環状の凹部16が形成されやすくすることができる。なお、凹部16の深さは、例えば、単結晶基板10ａのエッチングされる量とマスクのエッチングされる量との選択比によって変化させることができる。 When a metal material is used as the mask pattern 20 in this way, ions for etching the single crystal substrate 10a can easily travel in the side surface direction of the mask 20a. As a result, an annular recess 16 surrounding the projection 10b can be easily formed. Note that the depth of the recess 16 can be changed by, for example, a selection ratio between the amount of etching of the single crystal substrate 10a and the amount of etching of the mask.

Claims (7)

  1. 　基板の主面に、該主面の一部が上方に***した、上面を持つ突起を複数備え、
    該突起は、前記上面が半導体結晶を成長させるための結晶成長面であり、下方から上方に向かうにつれて横断面積が小さくなっているとともに、側面が、高さの異なる多数の柱状結晶が重なり合って構成されているテクスチャーを有している半導体成長用基板。     Provided with a plurality of protrusions having an upper surface on the main surface of the substrate, a part of the main surface protruding upward,
    The protrusion is a crystal growth surface on which the upper surface grows a semiconductor crystal, and its cross-sectional area decreases as it goes from the bottom to the top, and the side surface is formed by overlapping a number of columnar crystals having different heights. A semiconductor growth substrate having a texture that is made.
  2. 　多数の前記柱状結晶のうち高さが前記側面の途中までのものは、上方へ向かうにつれて先端が小さくなっている請求項１に記載の半導体成長用基板。 The semiconductor growth substrate according to claim 1, wherein a tip of a plurality of the columnar crystals whose height is up to the middle of the side surface becomes smaller in the upward direction.
  3. 　多数の前記柱状結晶は、側面視して、上方に向かうにつれて幅が小さくなっている請求項１または２に記載の半導体成長用基板。 3. The semiconductor growth substrate according to claim 1, wherein the plurality of columnar crystals have a width that decreases in the upward direction when viewed from the side.
  4. 　多数の前記柱状結晶は、横断面積が上方に向かうにつれて小さくなっている請求項１～３のいずれかに記載の半導体成長用基板。 The semiconductor growth substrate according to any one of claims 1 to 3, wherein a large number of the columnar crystals become smaller in cross section.
  5. 　前記基板の前記主面に、***した前記突起を取り囲むように環状の凹部が形成されている請求項１～４のいずれかに記載の半導体成長用基板。 5. The semiconductor growth substrate according to claim 1, wherein an annular recess is formed on the main surface of the substrate so as to surround the raised protrusion.
  6. 　請求項１～５のいずれかに記載の半導体成長用基板と、該半導体成長用基板上に、前記突起を被覆するように成長させた光半導体層とを備えた発光素子。 6. A light emitting device comprising: the semiconductor growth substrate according to claim 1; and an optical semiconductor layer grown on the semiconductor growth substrate so as to cover the protrusions.
  7. 　前記光半導体層は、前記半導体成長用基板から延びる転位を複数有し、
    前記基板の前記主面から延びる前記転位の数よりも前記突起の前記側面から延びる前記転位の数が少ない請求項６に記載の発光素子。     The optical semiconductor layer has a plurality of dislocations extending from the semiconductor growth substrate,
    The light emitting device according to claim 6, wherein the number of dislocations extending from the side surface of the protrusion is smaller than the number of dislocations extending from the main surface of the substrate.
PCT/JP2011/054320 2010-02-26 2011-02-25 Substrate for growing semiconductor, and light emitting element WO2011105557A1 (en)

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