WO2011083667A1 - Procédé et dispositif de traitement de plaquette de composé semi-conducteur - Google Patents

Procédé et dispositif de traitement de plaquette de composé semi-conducteur Download PDF

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Publication number
WO2011083667A1
WO2011083667A1 PCT/JP2010/072602 JP2010072602W WO2011083667A1 WO 2011083667 A1 WO2011083667 A1 WO 2011083667A1 JP 2010072602 W JP2010072602 W JP 2010072602W WO 2011083667 A1 WO2011083667 A1 WO 2011083667A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor wafer
surface plate
compound semiconductor
wafer
soft material
Prior art date
Application number
PCT/JP2010/072602
Other languages
English (en)
Japanese (ja)
Inventor
義雄 目崎
哲弥 山崎
隆幸 西浦
Original Assignee
住友電気工業株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 住友電気工業株式会社 filed Critical 住友電気工業株式会社
Priority to JP2011548939A priority Critical patent/JPWO2011083667A1/ja
Priority to CN2010800606149A priority patent/CN102696096A/zh
Publication of WO2011083667A1 publication Critical patent/WO2011083667A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H01L21/0201—Specific process step
    • H01L21/02013—Grinding, lapping
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00—Lapping machines or devices; Accessories
    • B24B37/04—Lapping machines or devices; Accessories designed for working plane surfaces
    • B24B37/07—Lapping machines or devices; Accessories designed for working plane surfaces characterised by the movement of the work or lapping tool
    • B24B37/08—Lapping machines or devices; Accessories designed for working plane surfaces characterised by the movement of the work or lapping tool for double side lapping
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00—Lapping machines or devices; Accessories
    • B24B37/11—Lapping tools
    • B24B37/20—Lapping pads for working plane surfaces
    • B24B37/24—Lapping pads for working plane surfaces characterised by the composition or properties of the pad materials
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00—Lapping machines or devices; Accessories
    • B24B37/11—Lapping tools
    • B24B37/20—Lapping pads for working plane surfaces
    • B24B37/26—Lapping pads for working plane surfaces characterised by the shape of the lapping pad surface, e.g. grooved

Definitions

  • the present invention relates to a processing method and a processing apparatus for lapping both sides of a compound semiconductor wafer.
  • this compound semiconductor wafer was sandwiched between upper and lower surface plates and simultaneously lapped on both sides.
  • set the compound semiconductor wafer on the lower surface plate using a jig lower the upper surface plate and press it against the compound semiconductor wafer, and wrap using an abrasive while applying an appropriate load.
  • the cleaved surface portion is chamfered, the cleaved surface portion is not accurate in optical alignment using a microscope at the time of pattern exposure.
  • the surface plate hits an edge in an acute angle state, there is a problem that the corner is chipped with a considerable probability, and in some cases, the wafer is broken from the chipped portion.
  • Patent Document 2 discloses a method in which the upper surface plate is lowered to some extent and then the lower surface plate is finely raised to place the wafer. By this method, the incidence of cracking defects was reduced to about half that of the prior art, but the cracking defects were not completely eliminated.
  • Patent Document 3 discloses a technique for preventing the cracking of the wafer by providing a large number of grooves having a V-shaped cross section on the surface plate, but it still does not completely eliminate the cracking defect.
  • JP 2002-367940 A JP 04-258119 A Japanese Patent Application Laid-Open No. 06-015561
  • the present invention is to provide a processing method capable of eliminating wafer chipping and cracking defects during lapping of a compound semiconductor wafer.
  • An embodiment of the present invention is a method for lapping both surfaces of a compound semiconductor wafer, including a step of lapping by placing the semiconductor wafer between an upper surface plate and a lower surface plate,
  • the present invention relates to a compound semiconductor wafer processing method, characterized in that a soft material is attached to a wafer side surface.
  • the soft material has a thickness of 0.5 mm to 5 mm and an Asker C hardness of 40 to 90.
  • a groove is formed on the wafer-side surface of the soft material.
  • the groove has a width of 1 mm or more and 5 mm or less.
  • Another embodiment of the present invention is a processing apparatus that includes an upper surface plate and a lower surface plate, a semiconductor wafer is disposed between the upper surface plate and the lower surface plate, and the both surfaces thereof are lapped.
  • the present invention relates to a processing apparatus in which a soft material is attached to a surface of the surface plate on the wafer side.
  • the soft material has a thickness of 0.5 mm to 5 mm and an Asker C hardness of 40 to 90.
  • a groove is formed on the wafer-side surface of the soft material.
  • the groove has a width of 1 mm or more and 5 mm or less.
  • the compound semiconductor wafer processing method of the present invention is a method of lapping both surfaces of a compound semiconductor wafer, including a step of lapping the semiconductor wafer by placing the semiconductor wafer between an upper surface plate and a lower surface plate, A soft material is attached to the surface of the surface plate on the wafer side.
  • the compound semiconductor wafer processing apparatus of the present invention is used in the processing method of the present invention.
  • FIG. 1 is a processing apparatus for lapping both surfaces of a compound semiconductor wafer.
  • the semiconductor wafer 4 is placed between the upper surface plate 1 and the lower surface plate 2 and lapping is performed.
  • a soft material 3 is attached to the surface of the upper surface plate 1 on the wafer side.
  • the soft material 3 examples include a nonwoven fabric impregnated with a urethane resin, ultrahigh molecular weight polyethylene, urethane foam, and silicon rubber. These are preferably processed to the same size as the upper surface plate 1 and attached to the entire surface of the upper surface plate.
  • the method of attaching is not particularly limited, but may be attached with a double-sided tape or directly with an adhesive.
  • the thickness of the soft material 3 is preferably 0.5 mm or more and 5 mm or less. If it is less than 0.5 mm, the effect of the soft material may not be obtained and the wafer may be broken. If it exceeds 5 mm, the amount of sinking of the wafer into the soft material increases, and the sagging (roll-off) of the wafer edge portion becomes too large.
  • the Asker C hardness of the soft material 3 is preferably 40 or more and 90 or less. If the Asker C hardness is less than 40, roll-off occurs, which may cause a defect during pattern exposure due to surface fringing. If the Asker C hardness exceeds 90, the effect of reducing chipping at the edge portion is reduced. Is also not preferred.
  • a groove in the soft material 3 it is preferable to form a groove in the soft material 3 on the side that comes into contact with the wafer during lapping. It is preferable to provide a large number of grooves in a lattice shape.
  • the groove improves the flow of the polishing liquid and enables smooth polishing. Further, when the groove is formed, it is possible to prevent the wafer from being lifted together with the upper surface plate when the upper surface plate 1 is raised after the polishing process is completed. When there is no groove, the polishing liquid flows poorly, so that the polishing time becomes long but polishing is possible. Further, when there is no groove, the semiconductor wafer may be lifted together with the upper surface plate, so that it is necessary to carefully raise the upper surface plate after the polishing.
  • the width of the groove is preferably 1 mm or more and 5 mm or less. If the thickness is less than 1 mm, the wafer may be lifted together with the upper surface plate when the upper surface plate is raised after the polishing process is completed. If the thickness exceeds 5 mm, unevenness is exerted on the pressure applied to the wafer, so that wafer accuracy such as thickness variation (TTV: Totol Thickness Variation) and local flatness (LTV: Local Thickness Variation) deteriorates.
  • TTV Totol Thickness Variation
  • LTV Local Thickness Variation
  • the spacing (pitch) between the ridge grooves is preferably 10 mm or more and 50 mm or less. If it is less than 10 mm or exceeds 50 mm, the wafer is lifted together with the upper surface plate when the upper surface plate is raised after the polishing process is completed, which is not preferable.
  • the depth of the groove is preferably 0.1 to 1.0 mm. If it is less than 0.1 mm, the wafer is lifted together with the upper surface plate, and if it exceeds 1.0 mm, the polishing liquid that has entered the groove tends to solidify.
  • the upper surface plate 1 is not particularly limited, but is preferably manufactured from cast iron, SUS (stainless steel), or the like. Of these, SUS (stainless steel) is particularly desirable.
  • the lower surface plate 2 does not attach a soft material.
  • the surface of the compound semiconductor wafer is polished by the lower surface plate 2 so as to have a desired surface roughness to obtain a finished surface.
  • the lower surface plate 2 is preferably manufactured from glass, tin or the like, but is not particularly limited.
  • the upper limit of the hardness of the lower surface plate 2 is the hardness of the compound semiconductor wafer to be polished, for example, Vickers hardness Hv750 for GaAs and Hv450 for InP.
  • the lower limit is preferably Hv220. If the hardness of the lower surface plate is too hard, fine scratches are likely to enter the surface of the compound semiconductor wafer. On the other hand, if it is too soft, the lower surface plate is worn quickly during polishing, leading to deterioration in wafer accuracy.
  • the compound semiconductor wafer 4 is not particularly limited, but is, for example, GaAs, InP, or GaN.
  • a jig 5 is arranged on the lower surface plate 2 so as to sandwich or surround the compound semiconductor wafer 4.
  • This jig has a gear on the outer peripheral portion so that the compound semiconductor wafer 4 moves with respect to the surface plate.
  • the soft material 3 is attached to the upper surface plate 1.
  • the soft material 3 include a nonwoven fabric impregnated with a urethane resin, ultrahigh molecular weight polyethylene, urethane foam, and silicon rubber. These are preferably processed to the same size as the upper surface plate 1 and attached to the entire surface of the upper surface plate 1.
  • the method of attaching is not particularly limited, but may be attached with a double-sided tape or directly with an adhesive.
  • the lower surface plate 2 and the upper surface plate 1 to which the soft material 3 is attached are attached to a processing device (polishing device).
  • the lower surface plate 2 and the upper surface plate 1 (soft material 3) may be shaved and flattened using a flat jig (not shown) (correction work).
  • the semiconductor wafer 4 and the jig 5 are arranged on the lower surface plate 2.
  • the compound semiconductor wafer 4 for double-sided processing should just be prepared by this stage at least.
  • the compound semiconductor wafer 4 is not specifically limited, For example, compound semiconductors, such as GaAs, InP, and GaN, are mentioned.
  • the jig 5 is arranged on the lower surface plate 2 so as to sandwich or surround the compound semiconductor wafer 4.
  • the jig 5 is provided with a gear at the outer peripheral portion so that the compound semiconductor wafer 4 moves with respect to the surface plate.
  • the polishing condition may be, for example, a platen rotation speed of 10 to 50 rpm with a load of about 50 g / cm 2 per wafer unit area.
  • a soft material was affixed to the upper surface plate with double-sided tape.
  • the soft material was a non-woven fabric with Asker C hardness of 72, and the thickness was 1.5 mm.
  • this nonwoven fabric grooves having a pitch of 10 mm, a width of 3 mm, and a depth of 0.5 mm were provided in a lattice shape.
  • the upper surface plate was attached to an existing polishing machine, and the compound semiconductor wafer was polished.
  • a compound semiconductor is manufactured by a VB method, and contains a GaAs crystal containing 5 ⁇ 10 17 to 3 ⁇ 10 18 atoms / cc of Si as a dopant and having an in-plane average value of crystal defects EPD of 500 / cm 2 or less.
  • a wafer obtained by slicing at (100) 15 ° off ⁇ 111> ⁇ 0.1 ° and cleaving the (0-1-1) plane of the wafer and chamfering the outer periphery of the wafer other than the cleaved surface was used.
  • the lower surface plate was made of borosilicate glass having a hardness of Hv450 and slits of 10 cm square. 300 wafers were polished, but no chipping or cracking occurred.
  • a compound semiconductor wafer was polished using an upper surface plate to which no soft material was attached. After 300 sheets were polished, 2% chipping and cracking occurred.

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  • Engineering & Computer Science (AREA)
  • Mechanical Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)

Abstract

L'invention concerne un procédé de polissage permettant de diminuer des défauts tels que fissures ou éclats dans un plaquette de composé semi-conducteur. Ce procédé de polissage de plaquette de composé semi-conducteur est un procédé de rodage des deux faces d'une plaquette de composé semi-conducteur. Ce procédé comprend une étape de traitement de rodage dans laquelle la plaquette de composé semi-conducteur est placée entre un plateau supérieur et un plateau inférieur, un matériau doux étant fixé sur le plateau supérieur, sur la face côté plaquette. Le dispositif de traitement de cette invention est un dispositif pour traitement de rodage, lequel comprend un plateau supérieur et un plateau inférieur, et dans lequel la plaquette de composé semi-conducteur est placée entre le plateau supérieur et le plateau inférieur et les deux faces de cette plaquette sont rodées. Un matériau doux est fixé sur le plateau supérieur, sur la face côté plaquette.
PCT/JP2010/072602 2010-01-05 2010-12-16 Procédé et dispositif de traitement de plaquette de composé semi-conducteur WO2011083667A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2011548939A JPWO2011083667A1 (ja) 2010-01-05 2010-12-16 化合物半導体ウェハの加工方法及び加工装置
CN2010800606149A CN102696096A (zh) 2010-01-05 2010-12-16 化合物半导体晶片的加工方法以及加工装置

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2010-000395 2010-01-05
JP2010000395 2010-01-05

Publications (1)

Publication Number Publication Date
WO2011083667A1 true WO2011083667A1 (fr) 2011-07-14

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PCT/JP2010/072602 WO2011083667A1 (fr) 2010-01-05 2010-12-16 Procédé et dispositif de traitement de plaquette de composé semi-conducteur

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JP (1) JPWO2011083667A1 (fr)
CN (1) CN102696096A (fr)
TW (1) TW201135822A (fr)
WO (1) WO2011083667A1 (fr)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08216034A (ja) * 1995-02-14 1996-08-27 Furukawa Electric Co Ltd:The 研磨材とそれを用いた研磨方法
JP2001244221A (ja) * 2000-02-03 2001-09-07 Wacker Siltronic G Fuer Halbleitermaterialien Ag 半導体ウェハの製造方法およびこの種の半導体ウェハ
WO2001082354A1 (fr) * 2000-04-24 2001-11-01 Sumitomo Mitsubishi Silicon Corporation Procédé de fabrication d'une plaquette de semi-conducteur
JP2004343126A (ja) * 2003-05-15 2004-12-02 Siltronic Ag 半導体ウェハの前面および裏面を同時にポリッシングする方法
JP2005150216A (ja) * 2003-11-12 2005-06-09 Hitachi Cable Ltd 半導体ウェハの研磨装置

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3516203B2 (ja) * 1999-11-08 2004-04-05 株式会社日鉱マテリアルズ 化合物半導体ウェハ
JP4093793B2 (ja) * 2002-04-30 2008-06-04 信越半導体株式会社 半導体ウエーハの製造方法及びウエーハ

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08216034A (ja) * 1995-02-14 1996-08-27 Furukawa Electric Co Ltd:The 研磨材とそれを用いた研磨方法
JP2001244221A (ja) * 2000-02-03 2001-09-07 Wacker Siltronic G Fuer Halbleitermaterialien Ag 半導体ウェハの製造方法およびこの種の半導体ウェハ
WO2001082354A1 (fr) * 2000-04-24 2001-11-01 Sumitomo Mitsubishi Silicon Corporation Procédé de fabrication d'une plaquette de semi-conducteur
JP2004343126A (ja) * 2003-05-15 2004-12-02 Siltronic Ag 半導体ウェハの前面および裏面を同時にポリッシングする方法
JP2005150216A (ja) * 2003-11-12 2005-06-09 Hitachi Cable Ltd 半導体ウェハの研磨装置

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Publication number Publication date
CN102696096A (zh) 2012-09-26
JPWO2011083667A1 (ja) 2013-05-13
TW201135822A (en) 2011-10-16

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