WO2011078776A1

WO2011078776A1 - Memory element with magneto-thermo-electronic control

Info

Publication number: WO2011078776A1
Application number: PCT/SE2010/051444
Authority: WO
Inventors: Vladislav Korenivski
Original assignee: Vnk Innovation Ab
Priority date: 2009-12-22
Filing date: 2010-12-21
Publication date: 2011-06-30

Abstract

The present invention provides a device that improves the performance of MRAM by eliminating the requirement for external fields or STT during the write operation. This is accomplished by a special design of the magnetic storage tri-layer of the memory element, in which the three magnetic layers have different magnetic ordering temperatures, whereas the middle layer has lowest ordering temperature, whereas further the two outer layers have different ordering temperatures. The outer layers have different magnetic anisotropy such that one outer layer switches in a lower field than the other outer layer. Upon heating the sandwich from the base operating temperature, typically room temperature, the storage layer switches under a combined action of the intrinsic exchange and dipole fields controlled by the thermal effect of a two-step current pulse trough the device. The read out of the magnetization direction of the storage tri-layer is achieved by the conventional means of magneto-resistive sensing, which utilizes a nonmagnetic spacer and a magnetic reference layer in series with the storage layer.

Description

MEMORY ELEMENT

WITH MAGNETO-THERMO-ELECTRONIC CONTROL

FIELD OF THE INVENTION

The present invention relates to magnetic memory elements, in particular magnetic memory elements with spin-thermo-electronic control.

BACKGROUND OF THE INVENTION

Magnetic memory elements are known. Thus, a device illustrated in FIG. 1 and comprised of two ferromagnetic layers separated by an insulating tunnel barrier is known as a magnetic tunnel junction (MTJ). Such MTJ consists of a bottom terminal 18 placed on a substrate or underlayer, followed by the first magnetic layer 14, the oxide tunnel barrier 12, the second magnetic layer 10, and the top terminal 16. The resistance of such MTJ is a function of the relative orientation of the magnetizations of the two magnetic layers 10 and 14, being lowest for parallel (P) alignment and highest for anti-parallel (AP) alignment. The reference layer 14 is made magnetically hard and the second magnetic layer 10 is made magnetically soft such that the two layers switch at different magnetic fields. This is conventionally achieved by exchange biasing the reference layer using an adjacent antiferromagnetic layer. The P and AP states are realized by applying an external magnetic field sufficient to switch the soft layer but not the hard layer. Such MTJ's are used as storage elements in magnetic random access memory (MRAM) as described in [ 1] . Here the different resistance values for P and AP states of the junction obtained by switching the soft layer 10 correspond to the stored digital values "0" and "1", where the switching is controlled using magnetic fields produced by an array of word and bit lines (WL and BL) . A variation on this field-write MRAM design is Toggle MRAM [2] where the soft layer is replaced with a magnetic bi-layer and the write sequence is performed by sequentially toggling the WL and BL fields. The limitations of such field-write devices for MRAM applications are due to the high fields and therefore high on-chip write currents necessary for switching the soft layer as the memory cell sizes are scaled to below 100 nm, where the magnetic anisotropy of the soft layer must be significantly increased for achieving higher memory stability against thermal agitation. An additional disadvantage of the field-write MRAM designs are the significant inter- cell cross-talk and half-select fields during the write operation, which lead to unwanted disturbances and therefore limit the memory performance. The scaling of field-MRAM to higher densities is therefore severely limited by the nature of the write operation.

A variation of the above described MTJ memory device uses the spin- transfer-torque (STT) of the spin-polarized current through the device instead of the magnetic field of the WL and BL for switching the soft magnetic layer in the device [3] . The current must be of sufficient magnitude such that the amount of spin torque transferred from the reference to the soft layer is sufficient for switching the soft layer between the P and AP memory states of the device. STT- MRAM offers an advantage in density over field-MRAM in that it, in principle, does not require magnetic fields external to the storage element for the write operation, even though a number of STT-MRAM implementations use an assisting magnetic field applied simultaneously with the STT-current write pulse. STT- MRAM has significant limitations in terms of scaling the technology to 10-nm bit sizes due to such drawbacks as the non-deterministic STT switching and the resulting uncertainties in the write operation, as well as due to magnetic instability of soft magnetic elements to thermal agitation.

Implementations utilizing heat assisted field-MRAM and heat-assisted STT- MRAM designs, such as described in [4- 10], use heating applied simultaneously with the magnetic fields or STT currents during the write operation. These proposed heat-assisted designs therefore inherit the essential modes of operation and the limitations from the respective field-MRAM and STT-MRAM write schemes described above.

Phase change memory (PCM) uses heat pulses for changing the atomic order in a non-magnetic PCM alloy between its crystalline and amorphous states having significantly different resistance, which serve as the digital non-volatile memory states [ 1 1]. PCM is non-magnetic in nature and is therefore free from the limitations on the magnetic switching of MRAM described above. However, the need for very high temperatures of typically above 600°C, and local temperatures in the PCM stack of up to 900- 1000°C, during the write operation on the phase- change material is a significant drawback of PCM. The write operation involves melting the phase-change material at typically >600°C, which leads to unwanted atomic diffusion in the memory stack. A further drawback of PCM is that the need for such very high temperatures to be produced on chip leads to high power dissipation.

It is therefore highly desirable that a memory device is demonstrated incorporating the benefits of MRAM and PCM but free from the stated limitations of these technologies. This would greatly simplify the design and increase the density for non-volatile and dynamic memory applications, where FLASH and DRAM are the current market leaders.

In addition to memory, reprogrammable logic circuits can benefit from using an improved and easily scalable non-volatile memory element. Here, a circuit made of transistors can be re-configured to perform various tasks. These tasks can be low level logic operations such as addition or multiplication, as well as higher level processing tasks. Circuits with flexible, dynamically re- configurable architectures have been proposed based on magneto-resistive elements external to the transistors within the circuits [12]. The re-configuration is achieved by changing the resistance of one of the non-volatile memory elements incorporated in to the circuit, such as the memory element disclosed herein.

Thus, it is in the art demonstrated the envisaged potentials of memory devices utilizing magnetic elements and thermo-electronic control. However, the performance of such memory devices is presently impaired by the limitations of the available implementations for efficiently performing the write operation.

SUMMARY OF THE INVENTION

Obviously an improved device that makes it possible to fully take advantage of the possibilities of non-volatile memory and re-programmable logic applications is needed. The present invention provides a device that improves the performance of MRAM by eliminating the requirement for external fields or STT during the write operation in the prior art MRAM designs. This is accomplished by a special design of the magnetic storage tri-layer of the memory element, which switches under a combined action of the intrinsic exchange and dipole fields controlled by the thermal effect of the transport current trough the device.

In a preferred embodiment, the storage layer is a sandwich of three magnetic layers having different magnetic ordering temperatures, Tc, whereas the middle layer has lowest Tc, whereas further the two outer layers have different Tc. The outer layers have different magnetic anisotropy such that one switches in a lower field than the other. Upon heating the sandwich from the base operating temperature, typically room temperature, to above the Tc of the middle layer, the two outer layers exchange-decouple whereupon the magnetically soft outer layer switches its magnetization orientation under the effect of the reversing dipolar field from the magnetically hard outer layer. Upon a further increase of temperature to above the Tc of the hard outer layer, its magnetic moment vanishes while the magnetic moment of the soft outer layer is non-zero and remains in the switched state, opposite to the original magnetization direction of the tri-layer. Upon subsequent rapid cooling of the tri-layer to room temperature caused by an abrupt removal of the current through the device, the hard outer layer and the middle layer undergo a simultaneous magnetic ordering, whereas the direction of their magnetizations is set by the exchange interaction with the soft outer layer. Thus, the tri-layer switches and magnetically orders in the direction opposite to its original magnetization direction, which is achieved by the thermal effect of a two-step current pulse through the device. This switching sequence provides the write operation of the memory cell. The read out of the magnetization direction of the storage tri-layer is achieved by the conventional means of magneto-resistive sensing, which utilizes a spacer and a magnetic reference layer in series with the storage layer.

Other embodiment, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a cross-section of a conventional MRAM memory element, in which the reference and storage magnetic layers are separated by a non-magnetic spacer such as an oxide tunnel barrier or a thin normal metal layer.

FIG. 2 illustrates a cross-section of the device of the present invention having the storage layer made of three magnetic layers of different elemental compositions designed such as to achieve desired magneto-thermal properties of the tri-layer.

FIG. 3 illustrates the write method used to switch the magnetization of the storage layer.

FIG. 4 illustrates time traces of the write-current I(t) used to switch the memory element of the present invention.

FIG. 5 illustrates the arrangement in which the memory element of the present invention is used in a re-programmable logic circuit.

DESCRIPTION OF THE SPECIFIC EMBODIMENTS

The objective of the present invention is to provide a memory device that overcomes the drawbacks of the prior art techniques. This is achieved by the device illustrated in FIG 2, in which the storage layer 20 is a sandwich of three magnetically ordered materials, with all three undergoing magnetic ordering at different temperatures, known as Curie temperature (Tc), whereas the Tc for all three layers is greater than the base operating temperature typically room temperature (RT), whereas further the Tc of the middle layer 22 (Tc2) is lower than the Tc of both outer layers 21 and 23 (Tel and Tc3). It is further arranged that one of the outer layers, e.g. layer 21, has both a lower Tc and higher magnetic anisotropy than the second outer layer, layer 23. At the base operating temperature (T<Tcl ,Tc2,Tc3) all layers are magnetically ordered and therefore coupled by magnetic exchange throughout the volume of the tri-layer 20, thus effectively forming one magnetic element, as illustrated in FIG. 3a. The magnetization direction of the storage layer 20 representing the memory state of the device is read out using the conventional giant magnetoresistance or tunneling magnetoresistance effect across the non-magnetic layer 26 with respect to the magnetic reference layer 27. The device is electrically connected to a larger micro-electronic circuit such as a memory array using terminals 25 and 28. The read out additionally allows to pre-read the memory state of the cell, which is subsequently written only if a change of state is required.

In step 1 of the write sequence illustrated in FIG. 3b, heating the storage tri-layer 30 using the thermal effect of the current through the device from base temperature to a temperature above Tc2 (T>Tc2) but below Tel and Tc3 (T<Tcl ,Tc3) results in a magnetically disordered paramagnetic state of the middle layer 32, such that the magnetically ordered outer layers 31 and 33 are exchange-decoupled. In this configuration layer 33 having lower magnetic anisotropy switches its magnetization orientation under the effect of the reversing dipole field from layer 31 having higher magnetic anisotropy, such that layers 31 and 33 are aligned anti-parallel. The interlayer dipole force is due to the shape anisotropy of the magnetic layers in the memory stack lithographically patterned into a sub-micrometer pillar, and is one of the design parameters in conventional memory implementations [2].

In step 2 of the write sequence illustrated in FIG. 3c, the current-controlled temperature is increased to T>Tcl while still T<Tc3, such that layer 31 becomes paramagnetic and the magnetization of the tri-layer is given by layer 33 only, which is magnetically oriented in the direction obtained in step 1.

In step 3 of the write sequence illustrated in FIG. 3d, the temperature is abruptly reduced to the base temperature, such that layers 31 and 32 undergo a simultaneous transition into a magnetically ordered state, with the direction of the magnetization set by the exchange coupling to the magnetization of layer 33 during the rapid cooling process. Thus, upon cooling down to RT all three layers are magnetically ordered in the direction of layer 33 produced in step 1 , which is opposite to the original magnetization direction of the tri-layer shown in FIG. 3b.

This is the write sequence of the disclosed magnetic memory element, which achieves a magnetic reversal of the storage layer 30 by using the thermal effect of the write current, without using external magnetic fields or STT. The current-time trace of the write sequence of FIGS. 3a-3c is illustrated in FIG 4a. A straightforward variation on the write sequence described above is to reverse the action of steps 1-3, whereas step 1 is a rapid heating of the tri-layer to above Tel (Tc2,Tcl<T<Tc3) producing a paramagnetic state in both layer 32 and layer 31; step 2 is lowering the temperature to T<Tcl (Tc2<T<Tcl ,Tc3) producing magnetic ordering in layer 31 under the action of the dipole field from layer 33 acting in the direction opposite to the magnetization of layer 33; and step 3 is lowering the temperature to RT (T<Tc2,Tcl ,Tc3) producing magnetic ordering in layer 32 and thereby exchange coupling between layers 31 and 33 which aligns the soft outer magnetic layer 33 in the direction of the hard magnetic layer 31. Thus, upon cooling down to RT all three layers are magnetically ordered in the magnetization direction of layer 31 produced in step 2, which is opposite to the original magnetization direction of the storage layer 30. The current-time trace of this write sequence is illustrated in FIG 4b.

Another straightforward variation on the above write sequence is applying a current pulse of amplitude sufficient to heat the storage tri-layer to above Tel (Tc2,Tcl<T<Tc3) and of different rise and fall times, as illustrated in FIG 4c and FIG 4d. The action of the slow- rise /fast- fall sequence of FIG 4c is equivalent to the action of the 3-step sequence of FIG 4a, and the action of the fast-rise/ slow- fall sequence of FIG 4d is equivalent to the action of the 3-step sequence of FIG 4b. The thermal effect of the slow rise time current pulse of FIG 4c results in the paramagnetic transitions in layer 31 delayed in time with respect to the paramagnetic transition in layer 32. If this time delay is greater than the switching time of layer 33, typically or the order of 1 ns, then the action of the slow rise time pulse is analogous to that of the first step of the write sequence of FIG 4a. Similarly, the delay time between the paramagnetic transition in layer 32 with respect to the transition in layer 31 for the slow fall time current pulse of FIG 4d results in the action analogous to that of the last step of the write sequence of FIG 4b. Thus, the slow rise/fall times in the range Tc2<T<Tcl in the write sequences of FIGS. 4c, 4d or the current step duration at Tc2<T<Tcl in the write sequences of FIGS. 4a,4b are designed to exceed the switching time of layer 33 of typically 1 ns, e.g. be equal to 5 ns. Correspondingly, the fast rise/ fall times in the write sequences of FIGS 4a- 4d must be short compared to the typical magnetization switching time of layer 33. This is achieved by the conventional thermo-electronic design such as that of PCM [ 13] where typically 100 K/ns heating and cooling rates are used for controlling amorphous-to-crystalline transitions in nano-sized PCM elements. Selecting materials with Tcl -Tc2< 100 K allows sub-nanosecond transitions between Tc 1 and Tc2 and thereby avoids magnetic switching of layer 33 during the fast rise/ fall time. Thus, the transition between Tel and Tc2 driven by the fast pulse edge is designed to be shorter than approximately 1 ns, e.g. 0.3 ns for Tcl-Tc2=30 K and the heating/cooling rate of 100 K/ns.

The write operation of the disclosed magnetic memory element uses current driven transitions in the magnetic coupling between layers 31 and 33 of type exchange-dipole-exchange which are intrinsic to the storage layer and controlled by the thermal effect of the current through the stack. This is the preferred embodiment as it is free from the need for external fields or STT and therefore allows high memory density. A straightforward variation on this preferred design is to use assisting external fields produced by bit or word lines implemented in the memory array in the vicinity of the storage layer [ 1-2] or STT from the reference layer of the memory stack [3]. Since the magnetic switching is controlled either entirely or predominantly by the thermal effect of the current the requirements on the strength of the assisting magnetic field or STT are significantly reduced.

Various material compositions can be used with the disclosed storage layer design. The low-Tc middle layer 22 can be made of a variety of materials, such as alloys of Ni-Cu or Ni-Fe-Mo where the Tc is controlled by the Cu or Mo concentration. As an example, 30% of Cu in Ni or 10% of Mo in Ni-Fe reduces the Tc to approximately 100°C, which is in the desired range for the middle layer. The soft magnetic outer layer 23 can be made of a variety of magnetically soft alloys such as Ni-Fe and Co-Fe-B, with high Curie temperatures of above 400°C. The hard magnetic outer layer 21 is preferably a high anisotropy alloy such as Sm-Fe or Nd-Fe-B with Tc=200-400°C. The anisotropy fields in such magnetically hard alloys can be as high as 1- 10 T, which is desirable for achieving high stability of the memory element against thermal agitation and should ultimately allow scaling the bit size down to 10 nm and potentially to sub- 10 nm. It is of high utility that no high external fields, indeed no external fields at all are required for switching the disclosed memory element even if the switching field of the hard layer 21 at room temperature exceeds 1 T, since the switching relies on the intra- layer thermo-magnetic mechanism of the exchange-dipole-exchange magnetic coupling sequence disclosed herein. It will be understood by those skilled in the art that the material composition of the storage layer exemplified above can be selected from a variety of soft and hard magnetic materials without departing from the basic design and the operating principle of the memory element disclosed herein.

Various fabrication sequences can be used to produce the memory element disclosed herein. Thus, the metal alloy layers of the storage layer 20 as well as the reference layer 27 are deposited using such standard methods as DC sputtering. The tunnel barrier 26 is produced using such standard methods as DC sputtering of Al or Mg with post-deposition oxidation, reactive sputtering of Al or Mg in Ar-02 mixture, or RF sputtering of Al-O or MgO. The multi-layer of a desired composition is subsequently patterned into a nano-pillar using standard subtractive lithography processes. It will be understood by those skilled in the art that the fabrication process can be selected from a variety of film deposition and lithography techniques without departing from the basic design and the operating principle of the memory element disclosed herein.

The preferred read out configuration of the disclosed memory element is a non-magnetic spacer layer in the form of a tunnel barrier such as MgO or Al-O, separating the storage layer from the magnetic reference layer of conventional design [1 - 10]. The typical tunnel junction of 1 - 10 kOhm resistance can be biased with 0.1 - 1 V to achieve the current density through the stack of 0.1 - 1 mA, which is sufficient for heating nano-sized volumes to several hundred degrees [ 1 1]. It will be understood that for very small cell sizes, < 10 nm, it may be advantageous to use normal metal spacers in order to reduce the resistance of the stack and thereby enable sufficiently high write currents through the stack for performing the thermo-magnetic control. Re-programmable circuits can be realized based on magneto-resistive memory elements external to the transistors within the circuits [ 12]. The reconfiguration is achieved by changing the resistance of the non-volatile memory element incorporated in to the circuit, such as the memory element disclosed herein. As an example, FIG. 5 illustrates a conventional series connection of a field effect transistor 59 and the disclosed memory element, whereas the source- drain current of the transistor is high or low depending on the orientation of the storage layer 50 with respect to the reference layer 57, which can be dynamically re-configured from parallel to anti-parallel as illustrated in FIGS. 3-4.

It will be further understood that various changes in form and detail can be made to the above illustrative embodiment without departing from the spirit and scope of the present invention.

REFERENCES

1. Gallagher et al., US Patent #5,640,343

2. Savchenko et al., US Patent #6,545,906

3. Slonczewski, US Patent #5,695,864

4. Tang, US Patent #6,744,651

5. Dieny et al, US Patent #6,950,335

6. Huai et al., US Patent #7, 126,202

7. Daughton et al., US Patent #7,023,723

8. Nickel, US Patent #7,397,077

9. Nozieres et al., US Patent #7,41 1 ,817

10. Abraham et al., US Patent #7,477,567

l l . Ovshinsky et al., US Patent #5, 166,758

12. Ney et al. Nature 425, 485 (2003)

13. Kim et al., J. Appl. Phys. 101 , 064512 (2007)

Claims

1. A magnetic storage element comprising three magnetic layers exhibiting different Curie temperatures, wherein the middle layer has the lowest Curie temperature, the two outer layers have different Curie temperatures, and all three Curie temperatures are higher than the base operating temperature of the storage element, typically room temperature; the storage element further comprising a magnetically hard outer layer exhibiting a higher switching magnetic field and a lower Curie temperature than the other, magnetically soft outer layer.

2. The magnetic storage element of claim 1 , wherein the middle layer is a low- Curie temperature alloy, such as Ni-Cu, Ni-Fe, Ni-Fe-Mo, or a plurality of other magnetic metal alloys, wherein the Curie temperature can be tuned to the desired range, typically 100-200°C, by varying the relative concentrations of the elements comprising the alloy.

3. The magnetic storage element of claim 1 , wherein the soft outer layer is one of a variety of magnetically soft alloys of high Curie temperature, typically above 400°C, such as Ni-Fe and Co-Fe-B.

4. The magnetic storage element of claim 1 , wherein the hard outer layer is one of a variety of high anisotropy alloys, such as Sm-Fe and Nd-Fe-B, with the Curie temperature intermediate to that of the middle layer of claim 2 and the soft outer layer of claim 3, typically in the range 200- 400°C.

5. A method of magnetic switching the storage element of claim 1

characterized by the following steps:

(a) heating the storage element using the Joule-heating effect of the electrical current through the element from the base temperature to above the Curie temperature of the middle layer but below the Curie

temperatures of both the outer layers, having the effect of magnetically disordering the middle layer and switching the direction of the soft outer layer; (b) further heating the element to above the Curie temperature of the hard outer layer but below the Curie temperature of the soft outer layer, having the effect of magnetically disordering the hard outer layer;

(c) cooling the storage element to the base temperature by a one-step removal of the current through the element, having the effect of ordering the middle layer and the hard outer layer in the direction of the soft layer, opposite to the original magnetization direction of the soft layer prior to step (a).

6. An alternative method of magnetic switching the storage element of claim 1 characterized by the following steps:

(a) heating the storage element by applying one step of current through the element from the base temperature to above the Curie temperature of the hard outer layer but below the Curie temperature of the soft outer layer, having the effect of magnetically disordering the middle layer and hard outer layer;

(b) cooling the storage element by partially removing the current through the element to below the Curie temperature of the hard outer layer but above the Curie temperature of the middle layer, having the effect of magnetically ordering the hard outer layer in the direction opposite to that of the soft outer layer;

(c) cooling the storage element to the base temperature by fully removing the current through the element, having the effect of ordering the middle layer and switching the orientation of the soft outer layer in the direction of the hard layer, opposite to the original magnetization direction of the soft layer prior to step (a).

7. A magnetic junction comprising the storage element of claim 1 , a magnetic reference layer, and a non-magnetic spacer between the storage element and the reference layer, wherein the read out of the magnetization direction of the storage element is performed by means of measuring the resistance of the junction.

8. The magnetic junction of claim 7, wherein the spacer layer is a thin layer of such oxides as Al-O and MgO or a layer of metal such as Cu and the reference layer is a high anisotropy high Curie temperature magnetic layer, both layer conventionally used as readout elements in magnetic field sensors and memory elements.

9. A memory element comprising two electrical terminals connected to the magnetic junction device according to claim 7, fabricated on a suitable substrate or underlayer.