WO2011070745A1 - Solid-state imaging device and imaging device - Google Patents

Solid-state imaging device and imaging device Download PDF

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Publication number
WO2011070745A1
WO2011070745A1 PCT/JP2010/006974 JP2010006974W WO2011070745A1 WO 2011070745 A1 WO2011070745 A1 WO 2011070745A1 JP 2010006974 W JP2010006974 W JP 2010006974W WO 2011070745 A1 WO2011070745 A1 WO 2011070745A1
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Prior art keywords
transistor
pixel
imaging device
solid
state imaging
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PCT/JP2010/006974
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French (fr)
Japanese (ja)
Inventor
邦彦 原
誠之 松長
善久 南
洋之 林下
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パナソニック株式会社
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Publication of WO2011070745A1 publication Critical patent/WO2011070745A1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/40—Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled
    • H04N25/42—Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled by switching between different modes of operation using different resolutions or aspect ratios, e.g. switching between interlaced and non-interlaced mode
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/40—Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled
    • H04N25/46—Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled by combining or binning pixels
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14643—Photodiode arrays; MOS imagers

Definitions

  • the present invention relates to a solid-state imaging device and an imaging device in which pixels that photoelectrically convert incident light are two-dimensionally arranged on a semiconductor substrate.
  • MOS type image sensors solid-state imaging devices
  • DSLR digital single lens reflex cameras
  • MOS type image sensors solid-state imaging devices
  • DSLR digital single lens reflex cameras
  • the MOS type image sensor needs to have high image quality not only in the all-pixel readout mode for still image shooting but also in the pixel mixing mode for moving image recording.
  • Patent Document 1 there is one disclosed in Patent Document 1.
  • FIG. 20 is a diagram showing an overall configuration of the solid-state imaging device described in Patent Document 1.
  • This solid-state imaging device includes an imaging region 201 and a pixel readout circuit 100.
  • the imaging region 201 is arranged in a matrix and includes a plurality of unit cells 202 that photoelectrically convert incident light, and vertical signal lines 101 and 102 that are provided corresponding to the columns of the unit cells 202.
  • the unit cell 202 includes a photodiode 211, an amplification transistor 215, a reset switch 214, and a row selection switch 216.
  • the pixel readout circuit 100 includes a current source 103, a ground connection switch 104, a load transistor 105, and a power supply connection switch 106.
  • the ground connection switch 104 is turned off, the row selection switch 216 of the unit cell 202 in the selected row is turned on, and the power connection switch 106 is turned on.
  • the current source 103 is connected to either the source terminal or the drain terminal on the row selection switch 216 side of the amplification transistor 215 of the selected unit cell 202 via the vertical signal line 101, and the row selection switch 216 side A power source is connected to the other of the source terminal and the drain terminal on the opposite side via a vertical signal line 102.
  • the amplification transistor 215 of the unit cell 202 and the current source 103 form a source follower amplifier, and the signal of the selected unit cell 202 is read from the pixel output line 107.
  • the ground connection switch 104 is turned on, the row selection switch 216 of the unit cell 202 of the selected row is turned on, and the power connection switch 106 is turned off.
  • the ground is connected to either the source terminal or the drain terminal on the row selection switch 216 side of the amplification transistor 215 of the selected unit cell 202 via the vertical signal line 101, and opposite to the row selection switch 216 side.
  • a load transistor 105 is connected to one of the source terminal and the drain terminal on the side through a vertical signal line 102.
  • a common source amplifier is formed by the amplification transistor 215 and the load transistor 105 of the unit cell 202, and if the row selection switches 216 of two rows are simultaneously turned on, the signals of the upper and lower unit cells 202 arranged in the column direction are mixed.
  • the mixed signal is obtained from the pixel output line 108. If the mixed signal is read by sequentially turning on the row selection switch 216 two rows at a time, the mixed signal of the entire imaging region 201 is read.
  • the solid-state imaging device of FIG. 20 when the solid-state imaging device of FIG. 20 is driven in the pixel mixing mode, the operating current varies according to the signal level of the mixed signal. As a result, the power supply provided in common for all the pixel readout circuits 100 is shaken, and the captured image (pixel mixed image) obtained by the mixed signal is deteriorated.
  • an object of the present invention is to provide a solid-state imaging device and an imaging device capable of obtaining a high-quality image even when driven in a pixel mixing mode.
  • a solid-state imaging device includes a pixel that generates a signal corresponding to an amount of received light, a floating diffusion that accumulates the signal of the pixel, and a source that is the floating diffusion.
  • a plurality of unit cells arranged in a two-dimensional manner and corresponding to the column of pixels, and corresponding to the reset transistor connected to each other and amplifying transistors whose gates are connected to the floating diffusion A vertical signal line that is connected to a source of the amplification transistor of the unit cell including the pixel of the column and transmits a signal of the pixel of the corresponding column; and when the signal of the pixel is output to the vertical signal line
  • a pixel current source that supplies current to the signal line, a drain of the reset transistor, and a drain of the amplification transistor.
  • a pixel power supply line connected to IN and between the source of the amplification transistor and the vertical signal line, or between the drain of the amplification transistor and the pixel power supply line, and the pixel is connected to the vertical signal line. And an element that functions as a resistor when the above signal is output.
  • the element functioning as the resistor may be a transistor.
  • the on-resistance of the transistor functioning as the resistor may be larger than that of the reset transistor or the amplification transistor.
  • the solid-state imaging device of the present invention it is possible to obtain a high-quality image even when driven in the pixel mixing mode, and it is easy to realize a DSLR having a high-quality still image shooting function and a moving image recording function. The effect of becoming is obtained.
  • FIG. 1 is a diagram illustrating an overall configuration of a solid-state imaging device according to the first embodiment of the present invention.
  • FIG. 2 is a circuit diagram showing a detailed configuration of the imaging region of the solid-state imaging device according to the first embodiment of the present invention.
  • FIG. 3 is a diagram showing a detailed configuration of the column circuit of the solid-state imaging device according to the first embodiment of the present invention.
  • FIG. 4 is a diagram illustrating a detailed configuration of the multiplexer and its periphery in the solid-state imaging device according to the first embodiment of the present invention.
  • FIG. 5 is a diagram illustrating a detailed configuration of the row selection circuit of the solid-state imaging device according to the first embodiment of the present invention.
  • FIG. 1 is a diagram illustrating an overall configuration of a solid-state imaging device according to the first embodiment of the present invention.
  • FIG. 2 is a circuit diagram showing a detailed configuration of the imaging region of the solid-state imaging device according to the first embodiment of the present invention.
  • FIG. 3
  • FIG. 6 is a diagram illustrating the timing of each control signal supplied to the unit cell and the column circuit when the solid-state imaging device according to the first embodiment of the present invention is in the all-pixel readout mode.
  • FIG. 7 is a diagram illustrating the timing of each control signal supplied to the unit cell and the column circuit in the pixel mixing mode of two vertical pixels and two horizontal pixels of the solid-state imaging device according to the first embodiment of the present invention.
  • FIG. 8 is a diagram illustrating a relationship between the FD potential Vfd and the pixel SF output Vo when the solid-state imaging device according to the first embodiment of the present invention is in the all-pixel readout mode.
  • FIG. 9 is a diagram illustrating a relationship between the FD potential Vfd and the pixel SF output Vo when the solid-state imaging device according to the first embodiment of the present invention is in the pixel mixture mode.
  • FIG. 10 is a circuit diagram showing a detailed configuration of the imaging region of the solid-state imaging device according to the second embodiment of the present invention.
  • FIG. 11 is a diagram illustrating a detailed configuration of the row selection circuit of the solid-state imaging device according to the second embodiment of the present invention.
  • FIG. 12 is a diagram illustrating another detailed configuration of the row selection circuit of the solid-state imaging device according to the second embodiment of the present invention.
  • FIG. 13 is a circuit diagram illustrating a detailed configuration of the imaging region of the solid-state imaging device according to the third embodiment of the present invention.
  • FIG. 10 is a circuit diagram showing a detailed configuration of the imaging region of the solid-state imaging device according to the second embodiment of the present invention.
  • FIG. 11 is a diagram illustrating a detailed configuration of the row selection circuit
  • FIG. 14 is a diagram illustrating the timing of each control signal supplied to the unit cell and the column circuit in the all-pixel readout mode of the solid-state imaging device according to the third embodiment of the present invention.
  • FIG. 15 is a diagram illustrating timings of control signals supplied to the unit cell and the column circuit in the pixel mixing mode of two vertical pixels and two horizontal pixels of the solid-state imaging device according to the third embodiment of the present invention.
  • FIG. 16 is a circuit diagram illustrating a detailed configuration of the imaging region of the solid-state imaging device according to the fourth embodiment of the present invention.
  • FIG. 17 is a diagram illustrating an overall configuration of a solid-state imaging device according to the fifth embodiment of the present invention.
  • FIG. 18 is a diagram illustrating a detailed configuration of the column ADC of the solid-state imaging device according to the fifth embodiment of the present invention.
  • FIG. 19 is a timing chart for explaining the AD conversion operation of the column ADC of the solid-state imaging device according to the fifth embodiment of the present invention.
  • FIG. 20 is a diagram illustrating an overall configuration of the solid-state imaging device described in Patent Document 1.
  • FIG. 1 is a diagram illustrating an overall configuration of a solid-state imaging device according to the first embodiment of the present invention.
  • FIG. 2 is a circuit diagram illustrating a detailed configuration of the imaging region 1 of the solid-state imaging device.
  • This solid-state imaging device includes an imaging region 1, a row selection circuit 3, a pixel current source circuit 4, a clamp circuit 5, a sample hold (S / H) circuit 6, a multiplexer (MUX) 7, a column selection circuit 8, a control unit 9, and
  • the output amplifier 10 is configured.
  • the imaging region 1 is provided corresponding to a column of a plurality of unit cells 2 and pixels (light receiving units) 11 arranged in a two-dimensional shape (matrix) on a semiconductor substrate, and includes a unit 11 including pixels 11 of the corresponding column.
  • a vertical signal line 19 connected to the source terminal of the amplification transistor of the cell 2 and transmitting the output signal from the pixel 11 of the corresponding column in the column direction (vertical direction), and the drain terminal of the reset transistor 14 of the unit cell 2
  • a pixel power line 17 connected to the drain terminal of the amplifying transistor 15 and supplying an initial voltage to the unit cell 2.
  • FIG. 1 shows an example in which 6 ⁇ 4 unit cells 2 are two-dimensionally arranged, the actual number of unit cells 2 is several million or more.
  • the row selection circuit 3 is provided for each horizontal row of the unit cells 2 and is common to a plurality of unit cells 2 in the same row, that is, a row selection signal SEL [n], a reset signal RST [n], and a transfer signal. It is connected to three control lines for supplying TRAN [n] (n is a natural number of 1 or more).
  • the row selection circuit 3 resets (initializes), reads (reads), and selects a line (row selection) for each unit cell 2 in the imaging region 1 in units of rows of the unit cell 2 via these control lines.
  • the pixel 11 to be controlled and to output a signal to the vertical signal line 19 is selected in units of rows.
  • the pixel current source circuit 4 is configured such that basic units provided corresponding to each column of the pixels 11 are arranged in an array in the row direction (horizontal direction), and the signal of the pixel 11 is output to the vertical signal line 19. A current supplied to the vertical signal line 19 is sometimes generated and supplied.
  • the clamp circuit 5 is configured such that basic units provided corresponding to the respective columns of the pixels 11 are arranged in an array in the row direction, and the unit cell 2 is output from the output signal of the unit cell 2 in the row unit from the vertical signal line 19. The fixed pattern noise component generated in step 1 is removed.
  • the S / H circuit 6 includes basic units provided corresponding to the respective columns of the pixels 11 arranged in an array in the row direction, and holds the output signal of the unit cell 2 in units of rows from the clamp circuit 5. .
  • the MUX 7 is configured such that basic units provided corresponding to each column of the pixels 11 are arranged in an array in the row direction, and switches connection between each basic unit of the S / H circuit 6 and the output amplifier 10.
  • the column selection circuit 8 is connected to the MUX 7 via a control line and controls the operation of the MUX 7. In other words, the column selection circuit 8 sequentially selects the column of the pixels 11 that outputs the output signal from the clamp circuit 5 to the output amplifier 10, that is, the basic unit of the S / H circuit 6.
  • the output amplifier 10 receives the output signal from the S / H circuit 6 via the MUX 7, amplifies the received output signal, and outputs it to the outside of the chip.
  • the control unit 9 supplies a drive signal for driving the row selection circuit 3 to the row selection circuit 3 in accordance with the drive mode.
  • the unit cell 2 photoelectrically converts incident light to generate a signal charge corresponding to the amount of received light, accumulates and outputs the generated signal charge, and accumulates and accumulates the signal charge generated by the pixel 11.
  • a floating diffusion (FD) 13 for outputting a signal charge as a voltage signal, and a reset for initializing the FD 13 so that the source terminal is connected to the FD 13 and the voltage indicated by the FD 13 becomes an initial voltage (here, VDD).
  • the transistor 14, the transfer transistor 12 inserted between the pixel 11 and the FD 13 and supplying the signal charge output from the pixel 11 to the FD 13, and the gate terminal thereof are connected to the FD 13, and follow the voltage indicated by the FD 13.
  • an amplifying transistor 15 for outputting to the vertical signal line 19.
  • the unit cell 2 outputs a reset voltage obtained by amplifying the voltage of the FD 13 when the FD 13 is initialized and a read voltage obtained by amplifying the voltage of the FD 13 when the signal charge of the pixel 11 is read to the FD 13 to the vertical signal line 19. To do.
  • the unit cell 2 is further inserted between the source terminal of the amplification transistor 15 and the vertical signal line 19, and when the row selection signal SEL [n] is received at the gate terminal from the row selection circuit 3 via the control line.
  • the row selection transistor 16 that connects the output (source terminal) of the amplification transistor 15 to the vertical signal line 19, and the source terminal of the amplification transistor 15 and the row selection transistor 16 (vertical signal line 19) are serially connected to the amplification transistor 15.
  • a resistance element 61 that can ensure a desired operating range of the FD 13 in the pixel mixture mode.
  • the resistance element 61 is formed of a wiring composed of a diffusion region, a metal wiring, a polysilicon wiring, a contact, and the like.
  • An example of the pixel 11 is a photodiode having a buried structure.
  • the resistance element 61 functions as a resistance when the signal of the pixel 11 is output to the vertical signal line 19.
  • the unit cell 2 in FIG. 2 has a structure including a pixel, a transfer transistor, an FD, a reset transistor, and an amplification transistor, that is, a so-called one-pixel one-cell structure.
  • the unit cell 2 includes a plurality of pixels, and may have a structure in which any one or all of the FD, the reset transistor, and the amplification transistor are shared within the unit cell, that is, a so-called multi-pixel 1-cell structure. Absent.
  • the pixel 11 can have a structure formed on the surface of the semiconductor substrate, that is, on the same side as the surface on which the gate terminal and the wiring of the transistor are formed. Furthermore, the structure of a so-called back-side illumination type image sensor (back-side illumination type solid-state imaging device) in which the pixels 11 are formed on the back side of the semiconductor substrate, that is, the side on which the gate terminal and the wiring of the transistor are formed. It can also be used.
  • back-side illumination type image sensor back-side illumination type solid-state imaging device
  • FIG. 3 is a diagram showing a detailed configuration of the column circuit.
  • the column circuit processes signals output from the pixels 11 in the same column, and includes a basic unit 4 a of the pixel current source circuit 4, a basic unit 5 a of the clamp circuit 5, and a basic unit 6 a of the S / H circuit 6. Composed.
  • the column circuit temporarily holds a pixel signal indicating a difference between the reset voltage and the read voltage output to the vertical signal line 19 for each pixel 11 or for each unit cell 2, and then outputs a pixel signal indicating the difference to the MUX 7. .
  • the basic unit 4a of the pixel current source circuit 4 is supplied with a current source bias voltage 21 at its gate terminal, and from the current source transistor 20 that supplies current to the amplifying transistor 15 when a signal is read from the unit cell 2 to the vertical signal line 19. Become.
  • the basic unit 5a of the clamp circuit 5 includes a clamp capacitor 23 having a capacitance value Ccl for obtaining a pixel signal, a sampling transistor 22 to which a sampling signal is supplied to the gate terminal, and the S / H circuit 6 opposite to the clamp capacitor 23. It comprises a clamp voltage input terminal 25 for setting the terminal potential on the pixel current source circuit 4 side to the clamp potential (VCL) and a clamp transistor 24 to which a clamp signal is supplied to the gate terminal.
  • VCL clamp potential
  • the basic unit 6 a of the S / H circuit 6 includes an S / H capacitor 27 having a capacitance value Csh for temporarily holding a pixel signal, an S / H capacitor input signal supplied to the gate terminal, and a pixel in the S / H capacitor 27.
  • An S / H capacitor input transistor 26 for inputting a signal is included.
  • FIG. 4 is a diagram showing a detailed configuration of the MUX 7 and its surroundings.
  • the basic unit 7 a of the MUX 7 includes a column selection transistor 28 disposed between the basic unit 6 a of the S / H circuit 6 and the horizontal common signal line 29.
  • the column selection transistor 28 sequentially outputs the pixel signal held in each basic unit 6 a of the S / H circuit 6 to the horizontal common signal line 29 in response to the column selection signal H [n] supplied to the gate terminal.
  • the pixel signal supplied to the output amplifier 10 via the horizontal common signal line 29 is amplified and then output to the outside of the chip.
  • FIG. 5 is a diagram showing a detailed configuration of the row selection circuit 3.
  • the row selection circuit 3 includes an address decoder 31 and a plurality of row selection logic circuits 32 provided corresponding to each row of the unit cell 2.
  • a Hi voltage is output to a predetermined row selection logic circuit 32 according to the address signal ADR supplied from the control unit 9, and a write enable signal is output to the flip-flop 33 of the predetermined row selection logic circuit 32. Entered.
  • the Hi voltage is set in the flip-flop 33 to which the write enable signal is input, and the unit cell 2 in the row connected to the flip-flop 33 via the AND gate 34 is selected.
  • the control pulses SEL_s, TRAN_s, and RST_s are input in the selected state, the row selection signal SEL [n], the reset signal RST [n], and the transfer signal TRAN [ n].
  • the driving of the unit cell 2 is completed, the value of each flip-flop 33 is reset to the Lo voltage, and the row selection is released.
  • the solid-state imaging device of the present embodiment has an all-pixel readout mode that can be used for camera still photography and a pixel mixture mode that can be used for a moving image recording function. Next, the signal reading operation will be described for each mode.
  • FIG. 6 is a diagram showing the timing of each control signal supplied to the unit cell 2 and the column circuit in the all-pixel readout mode in the solid-state imaging device of the present embodiment.
  • Vfd the potential of the FD 13
  • the threshold voltage of the amplification transistor 15 is Vth
  • the resistance value of the resistance element 61 is R
  • the current value of the pixel current source circuit 4 Is Vfdrst-Vth-RI (precisely Vfdrst-Vth-RI- ⁇ , where ⁇ is omitted) is output to the vertical signal line 19 as a reset voltage.
  • the reset voltage Vfdrst ⁇ Vth ⁇ RI is output to one terminal of the clamp capacitor 23 because the sampling transistor 22 is in an on state.
  • both the clamp signal and the S / H capacitor input signal are Hi voltages, and the potential of the other terminal of the clamp capacitor 23 and the S / H capacitor 27 is set to VCL.
  • the transfer transistor 12 is off and the row selection transistor 16 is on, and Vfdrst-Vfdsig-Vth-RI is output to the vertical signal line 19 as a read voltage.
  • the input of the clamp capacitor 23 changes by Vfdsig.
  • the clamp transistor 24 is in the OFF state, the potential of the other terminal of the clamp capacitor 23, that is, the potential of the S / H capacitor 27 changes by Vfdsig ⁇ Ccl / (Ccl + Csh).
  • This potential change is a voltage corresponding to the difference between the reset voltage and the read voltage in the vertical signal line 19, that is, a voltage corresponding to the pixel signal, and at timing t5, the row selection signal SEL [1] and the S / H capacitor input signal. Becomes the Lo voltage, and this pixel signal is accumulated in the S / H capacitor 27.
  • the pixel signals for one row are held in the S / H circuit 6.
  • the column selection signal H [1] becomes the Hi voltage, and the column selection transistor 28 in the first column is turned on.
  • the pixel signal of the S / H capacitor 27 in the first column is output to the horizontal common signal line 29 and is output to the outside of the chip via the output amplifier 10.
  • the column selection signal H [2] becomes the Hi voltage, and the column selection transistor 28 in the second column is turned on.
  • the pixel signal of the S / H capacitor 27 in the second column is output to the horizontal common signal line 29 and output to the outside of the chip via the output amplifier 10.
  • pixel signals for one row are sequentially output to the outside of the chip.
  • FIG. 7 is a diagram showing the timing of each control signal supplied to the unit cell 2 and the column circuit in the pixel mixing mode of two vertical pixels and two horizontal pixels in the solid-state imaging device of the present embodiment.
  • the row selection signals SEL [1] and SEL [2] are both Hi voltage, and the unit cells 2 in the first and second rows are selected.
  • two address decoders 31 of the row selection circuit 3 This can be achieved by sequentially supplying the address signal ADR, sequentially inputting the write enable signal to the flip-flop 33 of the row selection logic circuit 32, and sequentially setting the Hi voltage (also for the transfer signals TRAN [1] and TRAN [2]). The same).
  • Vfdrst ⁇ Vth ⁇ RI / 2 is output to the vertical signal line 19 as a reset voltage (more precisely, Vfdrst -Vth-RI / 2- ⁇ , where ⁇ is omitted). Further, the reset voltage Vfdrst ⁇ Vth is output to one terminal of the clamp capacitor 23 because the sampling transistor 22 is in the ON state.
  • both the clamp signal and the S / H capacitor input signal are Hi voltages, and the potential of the other terminal of the clamp capacitor 23 and the S / H capacitor 27 is set to VCL.
  • the transfer transistors 12 are turned on for the unit cells 2 in the first and second rows, so that the signal charges accumulated in the pixels 11 of the unit cells 2 in the first and second rows are transferred to the FD 13.
  • the FD potentials Vfd1 and Vfd2 of the unit cells 2 in the first row and the second row are reduced by the voltages Vfdsig1 and Vfdsig2 corresponding to the signal charge amounts to Vfdrst ⁇ Vfdsig1 and Vfdrst ⁇ Vfdsig2.
  • Vfdrst ⁇ Vfdsig ⁇ Vth -RI / 2 is output to the vertical signal line 19 as a read voltage.
  • This read voltage corresponds to the mixed signal of the unit cells 2 in the first and second rows. Due to the potential change of the vertical signal line 19, the input of the clamp capacitor 23 also changes by Vfdsig.
  • the clamp transistor 24 since the clamp transistor 24 is in the OFF state, the potential of the other terminal of the clamp capacitor 23, that is, the potential of the S / H capacitor 27 changes by Vfdsig ⁇ Ccl / (Ccl + Csh).
  • This potential change is a voltage corresponding to the difference between the reset voltage and the read voltage in the vertical signal line 19, that is, an averaged pixel signal (vertical pixel mixed signal) of the unit cells 2 in the first and second rows.
  • the row selection signals SEL [1] and SEL [2] and the S / H capacitor input signal become Lo voltage and are stored in the S / H capacitor 27.
  • the S / H capacitor input signal and the column selection signals H [1] and H [2] are set to the Hi voltage, and the column selection transistors 28 in the first column and the second column are turned on.
  • the average signal of the S / H capacitor 27 in the first column and the S / H capacitor 27 in the second column is output to the horizontal common signal line 29 and output to the outside of the chip via the output amplifier 10.
  • the column selection signals H [3] and H [4] become Hi voltage, and the column selection transistors 28 in the third and fourth columns are turned on.
  • an average signal of the S / H capacitors 27 in the third column and the S / H capacitors 27 in the fourth column is output to the horizontal common signal line 29 and output to the outside of the chip via the output amplifier 10.
  • the average signal of the pixel signals of the S / H capacitors 27 in each column is sequentially output outside the chip.
  • FIG. 8 is a diagram showing the relationship between Vfd and pixel SF output Vo at timing t4 in the all-pixel readout mode (FIG. 6).
  • the relationship between Vfd and Vo is expressed by equations (1) and (2).
  • Vo Vfd ⁇ Vth ⁇ RI ⁇ (I / a) (1)
  • a (1/2) ⁇ (W / L) ⁇ ⁇ eff ⁇ Cox (2)
  • Vth, W, L, ⁇ eff, and Cox indicate the threshold voltage, gate width, gate length, carrier mobility, and gate oxide film thickness of the amplification transistor 15, and I indicates the current value of the pixel current source circuit 4. Show. Strictly speaking, when Vo changes, the source-substrate potential of the amplification transistor 15 changes and Vth also changes. Here, Vth is treated as a fixed value.
  • Vo shows a linear characteristic that becomes a value obtained by subtracting a fixed value from Vfd.
  • Vfd is at the initial value Vfdrst at the timing t2, and the signal charge of the pixel 11 is transferred at the timing t3 to reduce the potential.
  • a pixel signal is detected by detecting the difference in the output potential of the pixel SF with respect to the two values of Vfd by a column circuit.
  • FIG. 9 is a diagram showing the relationship between the FD potential Vfd1 of the unit cell 2 in the first row and the FD potential Vfd2 of the unit cell 2 in the second row and the pixel SF output Vo when mixing signals of two vertical pixels. is there.
  • ⁇ V RI + (2- ⁇ 2) ⁇ ⁇ (I / a) (4)
  • the resistance element 61 serially inserted into the amplification transistor 15 can ensure a desired operating range in the signal mixing of a plurality of pixels arranged vertically.
  • a desired operating range of the FD 13 can be secured by the resistance element 61 even when signals output from the unit cells 2 are mixed by the vertical signal line 19.
  • fluctuations in the operating current during signal readout can be suppressed in both the all-pixel readout mode and the pixel mixture mode, so that a high-quality image can be obtained.
  • the unit cell 2 in FIG. 2 has a configuration using four transistors, that is, an amplification transistor, a transfer transistor, a reset transistor, and a row selection transistor, but includes only three transistors, an amplification transistor, a transfer transistor, and a reset transistor. But it doesn't matter.
  • the row selection of the unit cell 2 is executed by setting a low potential to the Vfd of the unit cell 2 in the row where reading is not performed.
  • the overall configuration of the solid-state imaging device according to the second embodiment of the present invention is the same as the overall configuration of the solid-state imaging device according to the first embodiment shown in FIG.
  • FIG. 10 is a circuit diagram illustrating a detailed configuration of the imaging region 1 of the solid-state imaging device according to the second embodiment.
  • the difference between this circuit and the circuit of the imaging region 1 of the first embodiment shown in FIG. 2 is that there is no resistance that is serially connected to the amplification transistor 15, and the on-resistance of the row selection transistor 16 is different from that of the unit cell 2. It is larger than the transistor (reset transistor 14 or amplification transistor 15).
  • FIG. 11 is a diagram showing a detailed configuration of the row selection circuit 3.
  • VDDL is supplied as a power source of the AND gate 34 that generates the row selection signal SEL [n].
  • VDDL is set to a voltage lower than the power supply of other circuits. Either the Hi voltage or the Lo voltage lower than the Hi voltage is supplied to the gate terminals of the reset transistor 14 and the row selection transistor 16 by the row selection signal SEL.
  • the Hi voltage supplied to the gate terminal of the row selection transistor 16 is Since the voltage is lower than the Hi voltage supplied to the gate terminal of the reset transistor 14, the on-resistance of the row selection transistor 16 when the row selection transistor 16 is turned on becomes a relatively large value.
  • the solid-state imaging device of the present embodiment has an all-pixel readout mode that can be used for camera still photography and a pixel mixture mode that can be used for a moving image recording function. Next, the signal reading operation will be described for each mode.
  • the timing of each control signal supplied to the unit cell 2 and the column circuit in the all-pixel readout mode in the solid-state imaging device of the present embodiment is the same as the timing of the first embodiment shown in FIG.
  • Vfdrst-Vth-RI (exactly Vfdrst-Vth-RI- ⁇ , where ⁇ is omitted) Is output to the vertical signal line 19 as a reset voltage.
  • the reset voltage Vfdrst ⁇ Vth ⁇ RI is output to one terminal of the clamp capacitor 23 because the sampling transistor 22 is in an on state.
  • both the clamp signal and the S / H capacitor input signal are Hi voltages, and the potential of the other terminal of the clamp capacitor 23 and the S / H capacitor 27 is set to VCL.
  • the transfer transistor 12 is off and the row selection transistor 16 is on, and Vfdrst-Vfdsig-Vth-RI is output to the vertical signal line 19 as a read voltage.
  • the input of the clamp capacitor 23 changes by Vfdsig.
  • the clamp transistor 24 is in the OFF state, the potential of the other terminal of the clamp capacitor 23, that is, the potential of the S / H capacitor 27 changes by Vfdsig ⁇ Ccl / (Ccl + Csh).
  • This potential change is a voltage corresponding to the difference between the reset voltage and the read voltage in the vertical signal line 19, that is, a voltage corresponding to the pixel signal, and at timing t5, the row selection signal SEL [1] and the S / H capacitor input signal. Becomes the Lo voltage, and this pixel signal is accumulated in the S / H capacitor 27.
  • the pixel signals for one row are held in the S / H circuit 6.
  • the column selection signal H [1] becomes the Hi voltage, and the column selection transistor 28 in the first column is turned on.
  • the pixel signal of the S / H capacitor 27 in the first column is output to the horizontal common signal line 29 and is output to the outside of the chip via the output amplifier 10.
  • the column selection signal H [2] becomes the Hi voltage, and the column selection transistor 28 in the second column is turned on.
  • the pixel signal of the S / H capacitor 27 in the second column is output to the horizontal common signal line 29 and output to the outside of the chip via the output amplifier 10.
  • pixel signals for one row are sequentially output to the outside of the chip.
  • each control signal supplied to the unit cell 2 and the column circuit in the pixel mixing mode of two vertical pixels and two horizontal pixels in the solid-state imaging device of this embodiment is the same as the timing of the first embodiment shown in FIG. is there.
  • the row selection signals SEL [1] and SEL [2] are both Hi voltage, and the unit cells 2 in the first and second rows are selected.
  • two address decoders 31 of the row selection circuit 3 This can be achieved by sequentially supplying the address signal ADR, sequentially inputting the write enable signal to the flip-flop 33 of the row selection logic circuit 32, and sequentially setting the Hi voltage (also for the transfer signals TRAN [1] and TRAN [2]). The same).
  • the row selection transistor 16 is in the on state, but the on-resistance becomes a magnitude R that cannot be ignored because the gate potential is low, and Vfdrst ⁇ Vth ⁇ RI / 2. (To be precise, Vfdrst ⁇ Vth ⁇ RI / 2 ⁇ , where ⁇ is omitted) is output to the vertical signal line 19 as a reset voltage. Further, the reset voltage Vfdrst ⁇ Vth ⁇ RI / 2 is output to one terminal of the clamp capacitor 23 because the sampling transistor 22 is in the ON state. On the other hand, the clamp signal and the S / H capacitor input signal are Hi voltages, and the potential of the other terminal of the clamp capacitor 23 and the S / H capacitor 27 is set to VCL.
  • the transfer transistors 12 are turned on for the unit cells 2 in the first and second rows, so that the signal charges accumulated in the pixels 11 of the unit cells 2 in the first and second rows are transferred to the FD 13.
  • the FD potentials Vfd1 and Vfd2 of the unit cells 2 in the first row and the second row are reduced by the voltages Vfdsig1 and Vfdsig2 corresponding to the signal charge amounts to Vfdrst ⁇ Vfdsig1 and Vfdrst ⁇ Vfdsig2.
  • Vfdrst ⁇ Vfdsig ⁇ Vth -RI / 2 is output to the vertical signal line 19 as a read voltage.
  • This read voltage corresponds to the mixed signal of the unit cells 2 in the first and second rows. Due to the potential change of the vertical signal line 19, the input of the clamp capacitor 23 also changes by Vfdsig.
  • the clamp transistor 24 since the clamp transistor 24 is in the OFF state, the potential of the other terminal of the clamp capacitor 23, that is, the potential of the S / H capacitor 27 changes by Vfdsig ⁇ Ccl / (Ccl + Csh).
  • This potential change is a voltage corresponding to the difference between the reset voltage and the read voltage in the vertical signal line 19, that is, an averaged pixel signal (vertical pixel mixed signal) of the unit cells 2 in the first and second rows.
  • the row selection signals SEL [1] and SEL [2] and the S / H capacitor input signal become Lo voltage and are stored in the S / H capacitor 27.
  • the S / H capacitor input signal and the column selection signals H [1] and H [2] are set to the Hi voltage, and the column selection transistors 28 in the first column and the second column are turned on.
  • the average signal of the S / H capacitor 27 in the first column and the S / H capacitor 27 in the second column is output to the horizontal common signal line 29 and output to the outside of the chip via the output amplifier 10.
  • the column selection signals H [3] and H [4] become Hi voltage, and the column selection transistors 28 in the third and fourth columns are turned on.
  • an average signal of the S / H capacitors 27 in the third column and the S / H capacitors 27 in the fourth column is output to the horizontal common signal line 29 and output to the outside of the chip via the output amplifier 10.
  • the average signal of the pixel signals of the S / H capacitors 27 in each column is sequentially output outside the chip.
  • pixel signals in which signals of 2 vertical pixels and 2 horizontal pixels are mixed are sequentially output to the outside of the chip.
  • FD range ⁇ V in this pixel mixture mode is expressed by equation (4) as in the first embodiment. It can be seen that the operating range of the FD 13 can be secured by the on-resistance R generated by reducing the Hi voltage of the gate potential of the row selection transistor 16.
  • a resistance element is not provided separately, but the row selection transistor 16 functions as a resistor connected in series with the amplification transistor 15. Therefore, not only the signal mixing operation with the fluctuation of the operating current can be realized, but also the resistor element and the row selection transistor 16 can be realized by one device, and the circuit area of the unit cell 2 can be reduced and the sensitivity can be improved. There is also an advantage of being.
  • the gate width of the row selection transistor 16 is made smaller than the gate width of the amplification transistor 15, and the threshold voltage of the row selection transistor 16 is set to the threshold of the amplification transistor 15. There is also a method of adjusting larger than the value voltage. Further, the gate length of the row selection transistor 16 is made larger than the minimum value allowed in the process. For example, the gate length of the row selection transistor 16 is made larger than the minimum gate length of the transistors constituting the row selection circuit 3. The on-resistance of the selection transistor 16 can be increased.
  • FIG. 1 the configuration of another row selection circuit 3 for reducing the Hi voltage of the gate potential of the row selection transistor 16 is shown in FIG.
  • the output of the variable power source 62 having a variable output voltage is supplied as the power source of the AND gate 34 that generates the row selection signal SEL [n] for supplying the Hi voltage to the gate terminal of the row selection transistor 16.
  • the output of the variable power source 62 is a high voltage in the all-pixel reading mode and a low voltage in the pixel mixing mode.
  • the solid-state imaging device of the second embodiment is characterized in that the row selection transistor 16 functions as a resistance element, and the gate potential of the row selection transistor 16 is set low in order to clarify the effect of the feature.
  • the gate potential of the row selection transistor 16 is not adjusted, the on-resistance of the row selection transistor 16 exists, and in an application where the FD operation range ⁇ V may be relatively narrow, fluctuations in the operating current are suppressed even without this Hi voltage adjustment.
  • the pixel signal mixing operation in the state can be realized. In this case, a separate power source is unnecessary, and the configuration of the entire chip is simplified.
  • the gate width of the row selection transistor 16 is made smaller than that of the amplification transistor 15, and the gate length of the row selection transistor 16 is made larger than the minimum value allowed in the process.
  • the method of adjusting the threshold voltage of the row selection transistor 16 is also effective.
  • FIG. 13 is a circuit diagram showing a detailed configuration of the imaging region 1.
  • the resistance element 61 and the row selection transistor 16 function as an element that functions as a resistor connected in series with the amplification transistor 15.
  • a resistance transistor 63 whose gate terminal is connected to the pixel power supply line 17 and whose on-resistance is larger than the other transistors (reset transistor 14 or amplification transistor 15) constituting the unit cell 2 is serially connected to the amplification transistor 15.
  • the output VDDCEL of the pixel power supply generation circuit 73 is supplied to the pixel power supply line 17 connected to the drain terminals of the reset transistor 14 and the amplification transistor 15.
  • the row selection operation of the unit cell 2 is realized by turning on and off the row selection transistor 16, but here, the Vfd of all the rows of the unselected unit cell 2 is obtained.
  • the row selection operation of the unit cell 2 is realized by setting it low.
  • VDDCEL is switched between a low potential for non-selection and a high pixel potential (VDD) for signal readout.
  • the solid-state imaging device of the present embodiment has an all-pixel readout mode that can be used for camera still photography and a pixel mixture mode that can be used for a moving image recording function. Next, the signal reading operation will be described for each mode.
  • FIG. 14 is a diagram showing the timing of each control signal supplied to the unit cell 2 and the column circuit in the all-pixel readout mode in the solid-state imaging device of the present embodiment.
  • the transfer transistor 12 is in the OFF state
  • the VDDCEL is in the Hi voltage (VDD) state
  • the reset transistor 14 is in the ON state
  • the gate potential VDDCEL of the resistance transistor 63 is a Hi voltage. Accordingly, since the resistance transistor 63 is in the on state, assuming that the threshold voltage of the amplification transistor 15 is Vth, the on-resistance of the resistance transistor 63 is R, and the current value of the pixel current source circuit 4 is I, Vfdrst ⁇ Vth -RI (precisely Vfdrst-Vth-RI- ⁇ , where ⁇ is omitted) is output to the vertical signal line 19 as a reset voltage. Further, the reset voltage Vfdrst ⁇ Vth ⁇ RI is output to one terminal of the clamp capacitor 23 because the sampling transistor 22 is in an on state. On the other hand, both the clamp signal and the S / H capacitor input signal are Hi voltages, and the potential of the other terminal of the clamp capacitor 23 and the S / H capacitor 27 is set to VCL.
  • the transfer transistor 12 is off and the resistance transistor 63 is on, and Vfdrst-Vfdsig-Vth-RI is output to the vertical signal line 19 as a read voltage.
  • the input of the clamp capacitor 23 changes by Vfdsig.
  • the clamp transistor 24 is in the OFF state, the potential of the other terminal of the clamp capacitor 23, that is, the potential of the S / H capacitor 27 changes by Vfdsig ⁇ Ccl / (Ccl + Csh).
  • This potential change is a voltage corresponding to the difference between the reset voltage and the read voltage in the vertical signal line 19, that is, a voltage corresponding to the pixel signal.
  • the S / H capacitance input signal becomes the Lo voltage, and this pixel signal is Accumulated in the S / H capacity 27.
  • the pixel signals for one row are held in the S / H circuit 6.
  • VDDCEL is at the Lo voltage and the reset transistor 14 is in the ON state, so that Vfd is set to a low potential, and the unit cell 2 in the row where the signal reading is completed returns to the non-selected state.
  • the column selection signal H [1] becomes the Hi voltage, and the column selection transistor 28 in the first column is turned on.
  • the pixel signal of the S / H capacitor 27 in the first column is output to the horizontal common signal line 29 and is output to the outside of the chip via the output amplifier 10.
  • the column selection signal H [2] becomes the Hi voltage, and the column selection transistor 28 in the second column is turned on.
  • the pixel signal of the S / H capacitor 27 in the second column is output to the horizontal common signal line 29 and output to the outside of the chip via the output amplifier 10.
  • pixel signals for one row are sequentially output to the outside of the chip.
  • FIG. 15 is a diagram showing the timing of each control signal supplied to the unit cell 2 and the column circuit in the pixel mixing mode of two vertical pixels and two horizontal pixels in the solid-state imaging device of the present embodiment.
  • VDDCEL is in the Hi voltage state
  • the two address signals ADR are sequentially supplied to the address decoder 31 of the row selection circuit 3, and the row selection logic circuit. This can be achieved by sequentially setting the 32 flip-flops 33 to the selected state (the same applies to the transfer signals TRAN [1] and TRAN [2]).
  • the gate potential VDDCEL of the resistance transistor 63 is the Hi voltage for the unit cells 2 in the first row and the second row. Accordingly, since the resistance transistor 63 is in the ON state, Vfdrst ⁇ Vth ⁇ RI / 2 (precisely Vfdrst ⁇ Vth ⁇ RI / 2 ⁇ , where ⁇ is omitted) is used as the reset voltage as the vertical signal line 19. Is output. Further, the reset voltage Vfdrst ⁇ Vth ⁇ RI / 2 is output to one terminal of the clamp capacitor 23 because the sampling transistor 22 is in the ON state. On the other hand, the clamp signal and the S / H capacitor input signal are Hi voltages, and the potential of the other terminal of the clamp capacitor 23 and the S / H capacitor 27 is set to VCL.
  • the transfer transistors 12 are turned on for the unit cells 2 in the first and second rows, so that the signal charges accumulated in the pixels 11 of the unit cells 2 in the first and second rows are transferred to the FD 13.
  • the FD potentials Vfd1 and Vfd2 of the unit cells 2 in the first row and the second row are reduced by the voltages Vfdsig1 and Vfdsig2 corresponding to the signal charge amounts to Vfdrst ⁇ Vfdsig1 and Vfdrst ⁇ Vfdsig2.
  • Vfdrst ⁇ Vfdsig ⁇ Vth-RI / 2 is output to the vertical signal line 19 as a read voltage.
  • This read voltage corresponds to the mixed signal of the unit cells 2 in the first and second rows. Due to the potential change of the vertical signal line 19, the input of the clamp capacitor 23 also changes by Vfdsig.
  • the potential of the other terminal of the clamp capacitor 23, that is, the potential of the S / H capacitor 27 changes by Vfdsig ⁇ Ccl / (Ccl + Csh).
  • This potential change is a voltage corresponding to the difference between the reset voltage and the read voltage in the vertical signal line 19, that is, an averaged pixel signal (vertical pixel mixed signal) of the unit cells 2 in the first and second rows.
  • the S / H capacitor input signal becomes Lo voltage and is stored in the S / H capacitor 27.
  • VDDCEL is the Lo voltage and the reset transistors 14 of the unit cells 2 in the first row and the second row are in the ON state, Vfd is set to a low potential, Return to unselected state.
  • the S / H capacitor input signal and the column selection signals H [1] and H [2] are set to the Hi voltage, and the column selection transistors 28 in the first column and the second column are turned on.
  • the average signal of the S / H capacitor 27 in the first column and the S / H capacitor 27 in the second column is output to the horizontal common signal line 29 and output to the outside of the chip via the output amplifier 10.
  • the column selection signals H [3] and H [4] become Hi voltage, and the column selection transistors 28 in the third and fourth columns are turned on.
  • an average signal of the S / H capacitors 27 in the third column and the S / H capacitors 27 in the fourth column is output to the horizontal common signal line 29 and output to the outside of the chip via the output amplifier 10.
  • the average signal of the pixel signals of the S / H capacitors 27 in each column is sequentially output outside the chip.
  • FD range ⁇ V in this pixel mixture mode is expressed by equation (4) as in the first and second embodiments.
  • a transistor corresponding to the row selection transistor 16 of the first and second embodiments that is, as a transistor for selecting the unit cell 2
  • a resistance transistor 63 is provided, and the operating range of the FD 13 is increased by the on-resistance R of the resistance transistor 63. It can be seen that it can be secured.
  • the solid-state imaging device of the present embodiment not only can a signal mixing operation with suppressed fluctuations in operating current be realized, but also a transistor that functions as a resistor compared to the solid-state imaging device of the second embodiment. This eliminates the need for a signal line to be supplied to the gate terminal, and therefore has an advantage of being suitable for reducing the circuit area and the aperture ratio of the unit cell 2.
  • FIG. 16 is a circuit diagram showing a detailed configuration of the imaging region 1.
  • ⁇ V bRI + (2- ⁇ 2) ⁇ ⁇ (I / a) (5)
  • FIG. 17 is a diagram illustrating an overall configuration of a solid-state imaging device according to the fifth embodiment of the present invention.
  • This solid-state imaging device includes an imaging region 1, a row selection circuit 3, a pixel current source circuit 4, a clamp circuit 5, a sample hold (S / H) circuit 6, a column ADC 44, a digital mixer 45, and a control unit 9. .
  • the column ADC 44 is configured such that basic units provided corresponding to the respective columns of the pixels 11 are arranged in an array in the row direction, and converts the row-unit analog pixel signals held in the S / H circuit 6 into digital signals. To do.
  • the digital mixer 45 is configured such that basic units provided corresponding to each column of the pixels 11 are arranged in an array in the row direction, and mixes output data (digital signal) of the column ADC 44.
  • the detailed configuration of the unit cell 2, the pixel current source circuit 4, the clamp circuit 5, the S / H circuit 6, and the row selection circuit 3 is the same as that of the solid-state imaging device of the first embodiment.
  • FIG. 18 is a diagram showing a detailed configuration of the column ADC 44.
  • the column ADC 44 includes a plurality of basic units 44 a and a column ADC input terminal 46, a ramp waveform generation circuit 48, and a counter 50.
  • the basic unit 44 a of the column ADC 44 includes a comparator 47 and a latch 49.
  • the comparator 47 receives the pixel signal from the S / H circuit 6 input from the column ADC input terminal 46, compares the input pixel signal with the ramp waveform of the ramp waveform generation circuit 48, and the ramp waveform is When it is lower than the pixel signal, the Hi voltage is output.
  • the latch 49 receives the output (counter value) of the counter 50, and writes the output of the counter 50 when the latch signal from the counter 50 is switched from the Hi voltage to the Lo voltage.
  • the counter 50 counts up in synchronization with the ramp waveform generated by the ramp waveform generation circuit 48.
  • a pixel signal is input to the column ADC 44, the ramp waveform is set to the minimum value of the pixel signal, and the counter 50 is set to 0. At this time, since the ramp waveform is at a lower level than the pixel signal, the latch signal is at the Hi voltage.
  • the ramp waveform level starts to rise.
  • the rising slope is set to reach the maximum value of the pixel signal at timing t3.
  • the counter 50 also counts up in synchronization with the ramp waveform rise.
  • the latch signal is switched to the Lo voltage, and the counter value at that time is written in the latch 49.
  • the digital value written in the latch 49 is a value corresponding to the pixel signal.
  • the solid-state imaging device includes an all-pixel readout mode and a pixel mixture mode, similarly to the solid-state imaging device according to the first embodiment. Next, the signal reading operation in each mode will be described.
  • the unit cells 2 for one row are selected, and pixel signals for one row are read from the unit cells 2 and held in the S / H circuit 6.
  • the pixel signals for one row are read from the S / H circuit 6 to the column ADC 44 and are digitally converted by the column ADC 44.
  • the mixed pixel signal is read from the S / H circuit 6 to the column ADC 44 and is digitally converted by the column ADC 44.
  • digital signals are simultaneously read out from the basic units 44 a of the column ADCs 44 in a plurality of columns to the digital mixer 45 and mixed by the digital mixer 45.
  • the mixed digital signals are sequentially output to the outside of the chip via the output unit (not shown).
  • the solid-state imaging device As described above, according to the solid-state imaging device according to the present embodiment, a digital output solid-state imaging device having a pixel mixing function suitable for high image quality while suppressing fluctuations in operating current can be realized.
  • the MUX 7, the output amplifier 10, and the analog front end portion that performs AD conversion in the subsequent stage are wide-band circuits for a high data transfer rate. become. For this reason, there exists a subject that the noise from the outside tends to mix.
  • the solid-state imaging device has an advantage that the resistance to the disturbance noise is greatly improved since the signal is digitized by the column circuit. This also leads to easy creation of a camera substrate using a solid-state imaging device.
  • the present invention is not limited to this embodiment.
  • the present invention includes various modifications made by those skilled in the art without departing from the scope of the present invention. Moreover, you may combine each component in several embodiment arbitrarily in the range which does not deviate from the meaning of invention.
  • the solid-state imaging device of the above embodiment includes a lens that collects external light on the solid-state imaging device, an image signal processing device that processes a signal from the solid-state imaging device, and a signal processed by the image signal processing device. It can be used in an imaging apparatus that includes an image storage device for storing and has a still image shooting function and a moving image shooting function with a lower resolution and a higher frame rate than a still image.
  • each transistor constituting the solid-state imaging device is an n-channel type MOS transistor, but may be a p-channel type MOS transistor.
  • the present invention is useful as a solid-state imaging device and an imaging device, and particularly useful as an image sensor for an imaging device that requires high image quality and high functionality such as a digital single-lens reflex camera and a high-end compact camera.

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Abstract

In order to provide an imaging device and a solid-state imaging device that can obtain high-quality images when operating in pixel-blending mode, the devices are provided with: a plurality of unit cells (2) that are arrayed two-dimensionally and that each have a pixel (11), an FD (13), a reset transistor (14), and an amplifying transistor (15); a vertical signal line (19) that is provided corresponding to a column of pixels (11), connects with the sources of the amplifying transistors (15) of the unit cells (2) containing the corresponding column of pixels (11), and transmits the signals of the corresponding column of pixels (11); a pixel current-source circuit (4) that supplies current to the vertical signal line (19) when the signal of a pixel is output to the vertical signal line (19) ; a pixel power-source line (17) that is connected to the drains of the amplifying transistors (15) and the drains of the reset transistors (14); and a resistive element (61) inserted between the source of the amplifying transistor (15) and the vertical signal line (19).

Description

固体撮像装置及び撮像装置Solid-state imaging device and imaging device
　本発明は、入射された光を光電変換する画素が半導体基板上に２次元状に配置された固体撮像装置及び撮像装置に関する。 The present invention relates to a solid-state imaging device and an imaging device in which pixels that photoelectrically convert incident light are two-dimensionally arranged on a semiconductor substrate.
　ＭＯＳ型イメージセンサ（固体撮像装置）は高速及び高感度など優れた特徴があり、ＭＯＳ型イメージセンサを搭載したデジタル一眼レフカメラ（ＤＳＬＲ）の市場は近年急速に拡大している。また、最近は静止画撮影機能だけでなく、ハイビジョン動画記録機能を搭載したＤＳＬＲ（Digital Single Lens Reflex camera）も増えてきている。これは静止画撮影用の全画素読み出しモードだけでなく、動画記録用の画素混合モードも高画質であることがＭＯＳ型イメージセンサで必要になっていることを意味する。ＭＯＳ型イメージセンサとしては、例えば特許文献１に開示されているものがある。 MOS type image sensors (solid-state imaging devices) have excellent features such as high speed and high sensitivity, and the market for digital single lens reflex cameras (DSLR) equipped with MOS type image sensors has been rapidly expanding in recent years. Recently, not only the still image shooting function but also the DSLR (Digital Single Lens Reflex camera) equipped with a high-definition video recording function is increasing. This means that the MOS type image sensor needs to have high image quality not only in the all-pixel readout mode for still image shooting but also in the pixel mixing mode for moving image recording. As the MOS type image sensor, for example, there is one disclosed in Patent Document 1.
米国特許第７０９１４６６号明細書US Pat. No. 7,091,466
　図２０は、特許文献１に記載されている固体撮像装置の全体構成を示す図である。 FIG. 20 is a diagram showing an overall configuration of the solid-state imaging device described in Patent Document 1.
　この固体撮像装置は、撮像領域２０１及び画素読み出し回路１００から構成される。撮像領域２０１は、行列状に配置され、入射された光を光電変換する複数の単位セル２０２と、単位セル２０２の列に対応して設けられた垂直信号線１０１及び１０２とを含む。 This solid-state imaging device includes an imaging region 201 and a pixel readout circuit 100. The imaging region 201 is arranged in a matrix and includes a plurality of unit cells 202 that photoelectrically convert incident light, and vertical signal lines 101 and 102 that are provided corresponding to the columns of the unit cells 202.
　単位セル２０２は、フォトダイオード２１１、増幅トランジスタ２１５、リセットスイッチ２１４及び行選択スイッチ２１６を含む。画素読み出し回路１００は、電流源１０３、グランド接続スイッチ１０４、負荷トランジスタ１０５及び電源接続スイッチ１０６を含む。 The unit cell 202 includes a photodiode 211, an amplification transistor 215, a reset switch 214, and a row selection switch 216. The pixel readout circuit 100 includes a current source 103, a ground connection switch 104, a load transistor 105, and a power supply connection switch 106.
　次に、図２０の固体撮像装置の動作を説明する。 Next, the operation of the solid-state imaging device of FIG. 20 will be described.
　この固体撮像装置の駆動モードは、全画素読み出しモードと画素混合モードの２種類である。 There are two drive modes for this solid-state imaging device: an all-pixel readout mode and a pixel mixture mode.
　全画素読み出しモードでは、グランド接続スイッチ１０４がオフ、選択された行の単位セル２０２の行選択スイッチ２１６がオン、電源接続スイッチ１０６がオンに設定される。これにより、選択された単位セル２０２の増幅トランジスタ２１５の行選択スイッチ２１６側のソース端子及びドレイン端子のいずれか一方には垂直信号線１０１を介して電流源１０３が接続され、行選択スイッチ２１６側と反対側のソース端子及びドレイン端子のいずれか他方には垂直信号線１０２を介して電源が接続される。この構成では単位セル２０２の増幅トランジスタ２１５と電流源１０３とでソースフォロアアンプが形成され、画素出力線１０７から選択された単位セル２０２の信号が読み出される。１行ずつ順次行選択スイッチ２１６をオンにして単位セル２０２の信号を読み出せば、全ての単位セル２０２の信号が読み出される。 In the all-pixel readout mode, the ground connection switch 104 is turned off, the row selection switch 216 of the unit cell 202 in the selected row is turned on, and the power connection switch 106 is turned on. As a result, the current source 103 is connected to either the source terminal or the drain terminal on the row selection switch 216 side of the amplification transistor 215 of the selected unit cell 202 via the vertical signal line 101, and the row selection switch 216 side A power source is connected to the other of the source terminal and the drain terminal on the opposite side via a vertical signal line 102. In this configuration, the amplification transistor 215 of the unit cell 202 and the current source 103 form a source follower amplifier, and the signal of the selected unit cell 202 is read from the pixel output line 107. When the row selection switch 216 is sequentially turned on one row at a time and the signals of the unit cells 202 are read, the signals of all the unit cells 202 are read.
　一方、画素混合モードでは、グランド接続スイッチ１０４がオン、選択された行の単位セル２０２の行選択スイッチ２１６がオン、電源接続スイッチ１０６がオフに設定される。これにより、選択された単位セル２０２の増幅トランジスタ２１５の行選択スイッチ２１６側のソース端子及びドレイン端子のいずれか一方には垂直信号線１０１を介してグランドが接続され、行選択スイッチ２１６側と反対側のソース端子及びドレイン端子のいずれか他方には垂直信号線１０２を介して負荷トランジスタ１０５が接続される。この構成では単位セル２０２の増幅トランジスタ２１５と負荷トランジスタ１０５とでソース接地アンプが形成され、２行の行選択スイッチ２１６を同時にオンすれば、列方向に並ぶ上下２つの単位セル２０２の信号を混合した混合信号が画素出力線１０８から得られる。２行ずつ順次行選択スイッチ２１６をオンにして混合信号を読み出せば、撮像領域２０１全体の混合信号が読み出される。 On the other hand, in the pixel mixture mode, the ground connection switch 104 is turned on, the row selection switch 216 of the unit cell 202 of the selected row is turned on, and the power connection switch 106 is turned off. As a result, the ground is connected to either the source terminal or the drain terminal on the row selection switch 216 side of the amplification transistor 215 of the selected unit cell 202 via the vertical signal line 101, and opposite to the row selection switch 216 side. A load transistor 105 is connected to one of the source terminal and the drain terminal on the side through a vertical signal line 102. In this configuration, a common source amplifier is formed by the amplification transistor 215 and the load transistor 105 of the unit cell 202, and if the row selection switches 216 of two rows are simultaneously turned on, the signals of the upper and lower unit cells 202 arranged in the column direction are mixed. The mixed signal is obtained from the pixel output line 108. If the mixed signal is read by sequentially turning on the row selection switch 216 two rows at a time, the mixed signal of the entire imaging region 201 is read.
　しかしながら、図２０の固体撮像装置を画素混合モードで駆動させた場合、混合信号の信号レベルに応じて動作電流が変動する。その結果、全ての画素読み出し回路１００で共通して設けられた電源にゆれが発生し、混合信号により得られる撮像画像（画素混合画像）が劣化する。 However, when the solid-state imaging device of FIG. 20 is driven in the pixel mixing mode, the operating current varies according to the signal level of the mixed signal. As a result, the power supply provided in common for all the pixel readout circuits 100 is shaken, and the captured image (pixel mixed image) obtained by the mixed signal is deteriorated.
　そこで、本発明は、かかる問題点に鑑み、画素混合モードで駆動させたときでも高画質な画像を得ることができる固体撮像装置及び撮像装置を提供することを目的とする。 Therefore, in view of such a problem, an object of the present invention is to provide a solid-state imaging device and an imaging device capable of obtaining a high-quality image even when driven in a pixel mixing mode.
　上記目的を達成するために、本発明の一態様に係る固体撮像装置は、受光量に応じた信号を生成する画素と、前記画素の信号を蓄積するためのフローティングディフュージョンと、ソースが前記フローティングディフュージョンと接続されたリセットトランジスタと、ゲートが前記フローティングディフュージョンと接続された増幅トランジスタとを有し、２次元状に配列された複数の単位セルと、前記画素の列に対応して設けられ、対応する列の画素を含む前記単位セルの前記増幅トランジスタのソースと接続され、対応する列の画素の信号を伝達する垂直信号線と、前記垂直信号線に前記画素の信号が出力されるときに前記垂直信号線に電流を供給する画素電流源と、前記リセットトランジスタのドレインと前記増幅トランジスタのドレインとに接続された画素電源線と、前記増幅トランジスタのソースと前記垂直信号線との間、又は前記増幅トランジスタのドレインと前記画素電源線との間に挿入され、前記垂直信号線に前記画素の信号が出力されるときに抵抗として機能する素子とを備えることを特徴とする。 In order to achieve the above object, a solid-state imaging device according to an aspect of the present invention includes a pixel that generates a signal corresponding to an amount of received light, a floating diffusion that accumulates the signal of the pixel, and a source that is the floating diffusion. A plurality of unit cells arranged in a two-dimensional manner and corresponding to the column of pixels, and corresponding to the reset transistor connected to each other and amplifying transistors whose gates are connected to the floating diffusion A vertical signal line that is connected to a source of the amplification transistor of the unit cell including the pixel of the column and transmits a signal of the pixel of the corresponding column; and when the signal of the pixel is output to the vertical signal line A pixel current source that supplies current to the signal line, a drain of the reset transistor, and a drain of the amplification transistor. And a pixel power supply line connected to IN and between the source of the amplification transistor and the vertical signal line, or between the drain of the amplification transistor and the pixel power supply line, and the pixel is connected to the vertical signal line. And an element that functions as a resistor when the above signal is output.
　本態様によれば、複数の行を同時に選択して垂直信号線に複数の行の信号を同時に出力させ、信号を垂直信号線上で混合して信号の混合を行うときでも増幅トランジスタにシリアル接続された抵抗により所望のフローティングディフュージョンの動作レンジを確保することができる。その結果、画素混合モードにおける信号混合時の動作電流の変動を抑えることができ、高画質な画像を得ることができる。 According to this aspect, even when a plurality of rows are simultaneously selected and signals of a plurality of rows are simultaneously output to the vertical signal line, and the signals are mixed on the vertical signal line, they are serially connected to the amplification transistor. A desired floating diffusion operating range can be secured by the resistance. As a result, fluctuations in the operating current during signal mixing in the pixel mixing mode can be suppressed, and high-quality images can be obtained.
　ここで、本発明の一態様に係る固体撮像装置は、前記抵抗として機能する素子はトランジスタであってもよい。このとき、前記抵抗として機能するトランジスタのオン抵抗は前記リセットトランジスタ又は前記増幅トランジスタよりも大きくてもよい。 Here, in the solid-state imaging device according to one embodiment of the present invention, the element functioning as the resistor may be a transistor. At this time, the on-resistance of the transistor functioning as the resistor may be larger than that of the reset transistor or the amplification transistor.
　本態様によれば、信号出力を目的として単位セルに設けられているトランジスタを抵抗として用いることで、抵抗素子を別途単位セルに設ける必要がなくなるので、単位セルの回路面積の縮小及び感度の向上を実現することができる。 According to this aspect, by using a transistor provided in the unit cell for the purpose of signal output as a resistor, there is no need to separately provide a resistive element in the unit cell, so the circuit area of the unit cell is reduced and the sensitivity is improved. Can be realized.
　本発明に係る固体撮像装置によれば、画素混合モードで駆動させたときでも高画質な画像を得ることができ、高画質な静止画撮影機能と動画記録機能とを有するＤＳＬＲの実現が容易になるという効果が得られる。 According to the solid-state imaging device of the present invention, it is possible to obtain a high-quality image even when driven in the pixel mixing mode, and it is easy to realize a DSLR having a high-quality still image shooting function and a moving image recording function. The effect of becoming is obtained.
図１は、本発明の第１の実施形態における固体撮像装置の全体構成を示す図である。FIG. 1 is a diagram illustrating an overall configuration of a solid-state imaging device according to the first embodiment of the present invention. 図２は、本発明の第１の実施形態の形態における固体撮像装置の撮像領域の詳細な構成を示す回路図である。FIG. 2 is a circuit diagram showing a detailed configuration of the imaging region of the solid-state imaging device according to the first embodiment of the present invention. 図３は、本発明の第１の実施形態における固体撮像装置の列回路の詳細な構成を示す図である。FIG. 3 is a diagram showing a detailed configuration of the column circuit of the solid-state imaging device according to the first embodiment of the present invention. 図４は、本発明の第１の実施形態における固体撮像装置のマルチプレクサ及びその周辺の詳細な構成を示す図である。FIG. 4 is a diagram illustrating a detailed configuration of the multiplexer and its periphery in the solid-state imaging device according to the first embodiment of the present invention. 図５は、本発明の第１の実施形態における固体撮像装置の行選択回路の詳細な構成を示す図である。FIG. 5 is a diagram illustrating a detailed configuration of the row selection circuit of the solid-state imaging device according to the first embodiment of the present invention. 図６は、本発明の第１の実施形態における固体撮像装置の全画素読み出しモード時の単位セルと列回路に供給される各制御信号のタイミングを示す図である。FIG. 6 is a diagram illustrating the timing of each control signal supplied to the unit cell and the column circuit when the solid-state imaging device according to the first embodiment of the present invention is in the all-pixel readout mode. 図７は、本発明の第１の実施形態における固体撮像装置の垂直２画素水平２画素の画素混合モード時の単位セルと列回路に供給される各制御信号のタイミングを示す図である。FIG. 7 is a diagram illustrating the timing of each control signal supplied to the unit cell and the column circuit in the pixel mixing mode of two vertical pixels and two horizontal pixels of the solid-state imaging device according to the first embodiment of the present invention. 図８は、本発明の第１の実施形態における固体撮像装置の全画素読み出しモード時のＦＤの電位Ｖｆｄと画素ＳＦ出力Ｖｏとの関係を示す図である。FIG. 8 is a diagram illustrating a relationship between the FD potential Vfd and the pixel SF output Vo when the solid-state imaging device according to the first embodiment of the present invention is in the all-pixel readout mode. 図９は、本発明の第１の実施形態における固体撮像装置の画素混合モード時のＦＤの電位Ｖｆｄと画素ＳＦ出力Ｖｏとの関係を示す図である。FIG. 9 is a diagram illustrating a relationship between the FD potential Vfd and the pixel SF output Vo when the solid-state imaging device according to the first embodiment of the present invention is in the pixel mixture mode. 図１０は、本発明の第２の実施形態における固体撮像装置の撮像領域の詳細な構成を示す回路図である。FIG. 10 is a circuit diagram showing a detailed configuration of the imaging region of the solid-state imaging device according to the second embodiment of the present invention. 図１１は、本発明の第２の実施形態における固体撮像装置の行選択回路の詳細な構成を示す図である。FIG. 11 is a diagram illustrating a detailed configuration of the row selection circuit of the solid-state imaging device according to the second embodiment of the present invention. 図１２は、本発明の第２の実施形態における固体撮像装置の行選択回路の他の詳細な構成を示す図である。FIG. 12 is a diagram illustrating another detailed configuration of the row selection circuit of the solid-state imaging device according to the second embodiment of the present invention. 図１３は、本発明の第３の実施形態における固体撮像装置の撮像領域の詳細な構成を示す回路図である。FIG. 13 is a circuit diagram illustrating a detailed configuration of the imaging region of the solid-state imaging device according to the third embodiment of the present invention. 図１４は、本発明の第３の実施形態における固体撮像装置の全画素読み出しモード時の単位セルと列回路に供給される各制御信号のタイミングを示す図である。FIG. 14 is a diagram illustrating the timing of each control signal supplied to the unit cell and the column circuit in the all-pixel readout mode of the solid-state imaging device according to the third embodiment of the present invention. 図１５は、本発明の第３の実施形態における固体撮像装置の垂直２画素水平２画素の画素混合モード時の単位セルと列回路に供給される各制御信号のタイミングを示す図である。FIG. 15 is a diagram illustrating timings of control signals supplied to the unit cell and the column circuit in the pixel mixing mode of two vertical pixels and two horizontal pixels of the solid-state imaging device according to the third embodiment of the present invention. 図１６は、本発明の第４の実施形態における固体撮像装置の撮像領域の詳細な構成を示す回路図である。FIG. 16 is a circuit diagram illustrating a detailed configuration of the imaging region of the solid-state imaging device according to the fourth embodiment of the present invention. 図１７は、本発明の第５の実施形態における固体撮像装置の全体構成を示す図である。FIG. 17 is a diagram illustrating an overall configuration of a solid-state imaging device according to the fifth embodiment of the present invention. 図１８は、本発明の第５の実施形態における固体撮像装置のカラムＡＤＣの詳細な構成を示す図である。FIG. 18 is a diagram illustrating a detailed configuration of the column ADC of the solid-state imaging device according to the fifth embodiment of the present invention. 図１９は、本発明の第５の実施形態における固体撮像装置のカラムＡＤＣのＡＤ変換動作を説明するためのタイミングチャートを示す図である。FIG. 19 is a timing chart for explaining the AD conversion operation of the column ADC of the solid-state imaging device according to the fifth embodiment of the present invention. 図２０は、特許文献１に記載の固体撮像装置の全体構成を示す図である。FIG. 20 is a diagram illustrating an overall configuration of the solid-state imaging device described in Patent Document 1.
　以下、本発明の実施の形態における固体撮像装置及び撮像装置について、図面を参照しながら説明する。 Hereinafter, a solid-state imaging device and an imaging device according to an embodiment of the present invention will be described with reference to the drawings.
　（第１の実施形態）
　図１は、本発明の第１の実施形態における固体撮像装置の全体構成を示す図である。図２は、同固体撮像装置の撮像領域１の詳細な構成を示す回路図である。 (First embodiment)
FIG. 1 is a diagram illustrating an overall configuration of a solid-state imaging device according to the first embodiment of the present invention. FIG. 2 is a circuit diagram illustrating a detailed configuration of the imaging region 1 of the solid-state imaging device.
　この固体撮像装置は、撮像領域１、行選択回路３、画素電流源回路４、クランプ回路５、サンプルホールド（Ｓ／Ｈ）回路６、マルチプレクサ（ＭＵＸ）７、列選択回路８、制御部９及び出力アンプ１０から構成される。 This solid-state imaging device includes an imaging region 1, a row selection circuit 3, a pixel current source circuit 4, a clamp circuit 5, a sample hold (S / H) circuit 6, a multiplexer (MUX) 7, a column selection circuit 8, a control unit 9, and The output amplifier 10 is configured.
　撮像領域１は、半導体基板に２次元状（行列状）に配置された複数の単位セル２と、画素（受光部）１１の列に対応して設けられ、対応する列の画素１１を含む単位セル２の増幅トランジスタのソース端子と接続され、対応する列の画素１１からの出力信号を列方向（垂直方向）に伝達するための垂直信号線１９と、単位セル２のリセットトランジスタ１４のドレイン端子と増幅トランジスタ１５のドレイン端子とに接続され、単位セル２に初期電圧を供給するための画素電源線１７とを含む。なお、図１では６×４個の単位セル２が２次元状に配列された例が示されているが、実際の単位セル２の数は数百万個以上である。 The imaging region 1 is provided corresponding to a column of a plurality of unit cells 2 and pixels (light receiving units) 11 arranged in a two-dimensional shape (matrix) on a semiconductor substrate, and includes a unit 11 including pixels 11 of the corresponding column. A vertical signal line 19 connected to the source terminal of the amplification transistor of the cell 2 and transmitting the output signal from the pixel 11 of the corresponding column in the column direction (vertical direction), and the drain terminal of the reset transistor 14 of the unit cell 2 And a pixel power line 17 connected to the drain terminal of the amplifying transistor 15 and supplying an initial voltage to the unit cell 2. Although FIG. 1 shows an example in which 6 × 4 unit cells 2 are two-dimensionally arranged, the actual number of unit cells 2 is several million or more.
　行選択回路３は、単位セル２の横１行毎に設けられた、同一行の複数の単位セル２に共通の制御信号つまり行選択信号ＳＥＬ［ｎ］、リセット信号ＲＳＴ［ｎ］及び転送信号ＴＲＡＮ［ｎ］（ｎは１以上の自然数）を供給するための３本の制御線と接続されている。行選択回路３は、撮像領域１の各単位セル２に対して、これら制御線を介して単位セル２の行単位でリセット（初期化）、リード（読み出し）、及びラインセレクト（行選択）を制御し、垂直信号線１９に信号を出力させる画素１１を行単位で選択する。 The row selection circuit 3 is provided for each horizontal row of the unit cells 2 and is common to a plurality of unit cells 2 in the same row, that is, a row selection signal SEL [n], a reset signal RST [n], and a transfer signal. It is connected to three control lines for supplying TRAN [n] (n is a natural number of 1 or more). The row selection circuit 3 resets (initializes), reads (reads), and selects a line (row selection) for each unit cell 2 in the imaging region 1 in units of rows of the unit cell 2 via these control lines. The pixel 11 to be controlled and to output a signal to the vertical signal line 19 is selected in units of rows.
　画素電流源回路４は、画素１１の各列に対応して設けられた基本単位が行方向（水平方向）にアレイ状に並んで構成され、垂直信号線１９に画素１１の信号が出力されるときに垂直信号線１９に供給される電流を生成及び供給する。 The pixel current source circuit 4 is configured such that basic units provided corresponding to each column of the pixels 11 are arranged in an array in the row direction (horizontal direction), and the signal of the pixel 11 is output to the vertical signal line 19. A current supplied to the vertical signal line 19 is sometimes generated and supplied.
　クランプ回路５は、画素１１の各列に対応して設けられた基本単位が行方向にアレイ状に並んで構成され、垂直信号線１９からの行単位の単位セル２の出力信号から単位セル２で発生する固定パターンノイズ成分を除去する。 The clamp circuit 5 is configured such that basic units provided corresponding to the respective columns of the pixels 11 are arranged in an array in the row direction, and the unit cell 2 is output from the output signal of the unit cell 2 in the row unit from the vertical signal line 19. The fixed pattern noise component generated in step 1 is removed.
　Ｓ／Ｈ回路６は、画素１１の各列に対応して設けられた基本単位が行方向にアレイ状に並んで構成され、クランプ回路５からの行単位の単位セル２の出力信号を保持する。 The S / H circuit 6 includes basic units provided corresponding to the respective columns of the pixels 11 arranged in an array in the row direction, and holds the output signal of the unit cell 2 in units of rows from the clamp circuit 5. .
　ＭＵＸ７は、画素１１の各列に対応して設けられた基本単位が行方向にアレイ状に並んで構成され、Ｓ／Ｈ回路６の各基本単位と出力アンプ１０との接続を切り替える。 The MUX 7 is configured such that basic units provided corresponding to each column of the pixels 11 are arranged in an array in the row direction, and switches connection between each basic unit of the S / H circuit 6 and the output amplifier 10.
　列選択回路８は、制御線を介してＭＵＸ７と接続され、ＭＵＸ７の動作を制御する。言い換えると、列選択回路８は、クランプ回路５からの出力信号を出力アンプ１０に出力させる画素１１の列、つまりＳ／Ｈ回路６の基本単位を順次選択する。 The column selection circuit 8 is connected to the MUX 7 via a control line and controls the operation of the MUX 7. In other words, the column selection circuit 8 sequentially selects the column of the pixels 11 that outputs the output signal from the clamp circuit 5 to the output amplifier 10, that is, the basic unit of the S / H circuit 6.
　出力アンプ１０は、ＭＵＸ７を介してＳ／Ｈ回路６からの出力信号を受け取り、受け取った出力信号を増幅した後にチップ外部に出力する。 The output amplifier 10 receives the output signal from the S / H circuit 6 via the MUX 7, amplifies the received output signal, and outputs it to the outside of the chip.
　制御部９は、駆動モードに応じて、行選択回路３を駆動するための駆動信号を行選択回路３に供給する。 The control unit 9 supplies a drive signal for driving the row selection circuit 3 to the row selection circuit 3 in accordance with the drive mode.
　単位セル２は、入射した光を光電変換して受光量に応じた信号電荷を生成し、生成した信号電荷を蓄積及び出力する画素１１と、画素１１により発生した信号電荷を蓄積し、蓄積した信号電荷を電圧信号として出力するためのフローティングディフュージョン（ＦＤ）１３と、ソース端子がＦＤ１３と接続され、ＦＤ１３の示す電圧が初期電圧（ここではＶＤＤ）になるようにＦＤ１３を初期化するためのリセットトランジスタ１４と、画素１１とＦＤ１３との間に挿入され、画素１１により出力される信号電荷をＦＤ１３に供給するための転送トランジスタ１２と、ゲート端子がＦＤ１３と接続され、ＦＤ１３の示す電圧に追従して変化する電圧を垂直信号線１９に出力するための増幅トランジスタ１５とを備えている。 The unit cell 2 photoelectrically converts incident light to generate a signal charge corresponding to the amount of received light, accumulates and outputs the generated signal charge, and accumulates and accumulates the signal charge generated by the pixel 11. A floating diffusion (FD) 13 for outputting a signal charge as a voltage signal, and a reset for initializing the FD 13 so that the source terminal is connected to the FD 13 and the voltage indicated by the FD 13 becomes an initial voltage (here, VDD). The transistor 14, the transfer transistor 12 inserted between the pixel 11 and the FD 13 and supplying the signal charge output from the pixel 11 to the FD 13, and the gate terminal thereof are connected to the FD 13, and follow the voltage indicated by the FD 13. And an amplifying transistor 15 for outputting to the vertical signal line 19.
　単位セル２は、ＦＤ１３を初期化した時のＦＤ１３の電圧を増幅したリセット電圧と、画素１１の信号電荷をＦＤ１３に読み出した時のＦＤ１３の電圧を増幅したリード電圧とを垂直信号線１９に出力する。 The unit cell 2 outputs a reset voltage obtained by amplifying the voltage of the FD 13 when the FD 13 is initialized and a read voltage obtained by amplifying the voltage of the FD 13 when the signal charge of the pixel 11 is read to the FD 13 to the vertical signal line 19. To do.
　単位セル２は、さらに、増幅トランジスタ１５のソース端子と垂直信号線１９との間に挿入され、行選択回路３から制御線を介して行選択信号ＳＥＬ［ｎ］をゲート端子に受けたときに増幅トランジスタ１５の出力（ソース端子）を垂直信号線１９に接続する行選択トランジスタ１６と、増幅トランジスタ１５にシリアルに接続される形で増幅トランジスタ１５のソース端子と行選択トランジスタ１６（垂直信号線１９）との間に挿入され、画素混合モードでの所望のＦＤ１３の動作レンジの確保を可能にする抵抗素子６１とを備えている。 The unit cell 2 is further inserted between the source terminal of the amplification transistor 15 and the vertical signal line 19, and when the row selection signal SEL [n] is received at the gate terminal from the row selection circuit 3 via the control line. The row selection transistor 16 that connects the output (source terminal) of the amplification transistor 15 to the vertical signal line 19, and the source terminal of the amplification transistor 15 and the row selection transistor 16 (vertical signal line 19) are serially connected to the amplification transistor 15. ) And a resistance element 61 that can ensure a desired operating range of the FD 13 in the pixel mixture mode.
　抵抗素子６１は、拡散領域からなる配線、金属の配線、ポリシリコンの配線、及びコンタクトなどで形成される。画素１１の一例としては埋め込み構造のフォトダイオードがある。抵抗素子６１は、垂直信号線１９に画素１１の信号が出力されるときに抵抗として機能する。 The resistance element 61 is formed of a wiring composed of a diffusion region, a metal wiring, a polysilicon wiring, a contact, and the like. An example of the pixel 11 is a photodiode having a buried structure. The resistance element 61 functions as a resistance when the signal of the pixel 11 is output to the vertical signal line 19.
　なお、図２の単位セル２は、画素、転送トランジスタ、ＦＤ、リセットトランジスタ及び増幅トランジスタを有する構造、いわゆる１画素１セル構造を有するとした。しかし、単位セル２は、複数の画素を含み、さらに、ＦＤ、リセットトランジスタ及び増幅トランジスタのいずれか、あるいは、すべてを単位セル内で共有する構造、いわゆる多画素１セル構造を有しても構わない。 Note that the unit cell 2 in FIG. 2 has a structure including a pixel, a transfer transistor, an FD, a reset transistor, and an amplification transistor, that is, a so-called one-pixel one-cell structure. However, the unit cell 2 includes a plurality of pixels, and may have a structure in which any one or all of the FD, the reset transistor, and the amplification transistor are shared within the unit cell, that is, a so-called multi-pixel 1-cell structure. Absent.
　また、画素１１は半導体基板の表面、すなわち、トランジスタのゲート端子及び配線が形成された面と同じ面側に形成される構造を用いることが出来る。さらに、画素１１が半導体基板の裏面、すなわちトランジスタのゲート端子及び配線が形成された面に対して裏面側に形成される、いわゆる、裏面照射型イメージセンサ（裏面照射型固体撮像装置）の構造を用いることも出来る。 In addition, the pixel 11 can have a structure formed on the surface of the semiconductor substrate, that is, on the same side as the surface on which the gate terminal and the wiring of the transistor are formed. Furthermore, the structure of a so-called back-side illumination type image sensor (back-side illumination type solid-state imaging device) in which the pixels 11 are formed on the back side of the semiconductor substrate, that is, the side on which the gate terminal and the wiring of the transistor are formed. It can also be used.
　図３は、列回路の詳細な構成を示す図である。 FIG. 3 is a diagram showing a detailed configuration of the column circuit.
　この列回路は、同一列の画素１１から出力された信号を処理し、画素電流源回路４の基本単位４ａと、クランプ回路５の基本単位５ａと、Ｓ／Ｈ回路６の基本単位６ａとから構成される。同列回路は、画素１１毎または単位セル２毎に垂直信号線１９に出力されるリセット電圧とリード電圧との差分を示す画素信号を一時保持した後、その差分を示す画素信号をＭＵＸ７に出力する。 The column circuit processes signals output from the pixels 11 in the same column, and includes a basic unit 4 a of the pixel current source circuit 4, a basic unit 5 a of the clamp circuit 5, and a basic unit 6 a of the S / H circuit 6. Composed. The column circuit temporarily holds a pixel signal indicating a difference between the reset voltage and the read voltage output to the vertical signal line 19 for each pixel 11 or for each unit cell 2, and then outputs a pixel signal indicating the difference to the MUX 7. .
　画素電流源回路４の基本単位４ａは、ゲート端子に電流源バイアス電圧２１が供給され、単位セル２から垂直信号線１９への信号読み出し時に、増幅トランジスタ１５に電流を供給する電流源トランジスタ２０からなる。 The basic unit 4a of the pixel current source circuit 4 is supplied with a current source bias voltage 21 at its gate terminal, and from the current source transistor 20 that supplies current to the amplifying transistor 15 when a signal is read from the unit cell 2 to the vertical signal line 19. Become.
　クランプ回路５の基本単位５ａは、画素信号を求めるための容量値Ｃｃｌのクランプ容量２３と、ゲート端子にサンプリング信号が供給されるサンプリングトランジスタ２２と、クランプ容量２３のＳ／Ｈ回路６と反対側（画素電流源回路４側）の端子電位をクランプ電位（ＶＣＬ）に設定するためのクランプ電圧入力端子２５及びゲート端子にクランプ信号が供給されるクランプトランジスタ２４とからなる。 The basic unit 5a of the clamp circuit 5 includes a clamp capacitor 23 having a capacitance value Ccl for obtaining a pixel signal, a sampling transistor 22 to which a sampling signal is supplied to the gate terminal, and the S / H circuit 6 opposite to the clamp capacitor 23. It comprises a clamp voltage input terminal 25 for setting the terminal potential on the pixel current source circuit 4 side to the clamp potential (VCL) and a clamp transistor 24 to which a clamp signal is supplied to the gate terminal.
　Ｓ／Ｈ回路６の基本単位６ａは、画素信号を一時保持するための容量値ＣｓｈのＳ／Ｈ容量２７と、ゲート端子にＳ／Ｈ容量入力信号が供給され、Ｓ／Ｈ容量２７に画素信号を入力するためのＳ／Ｈ容量入力トランジスタ２６を含む。 The basic unit 6 a of the S / H circuit 6 includes an S / H capacitor 27 having a capacitance value Csh for temporarily holding a pixel signal, an S / H capacitor input signal supplied to the gate terminal, and a pixel in the S / H capacitor 27. An S / H capacitor input transistor 26 for inputting a signal is included.
　図４は、ＭＵＸ７及びその周辺の詳細な構成を示す図である。 FIG. 4 is a diagram showing a detailed configuration of the MUX 7 and its surroundings.
　ＭＵＸ７の基本単位７ａは、Ｓ／Ｈ回路６の基本単位６ａと水平共通信号線２９との間に配置された列選択トランジスタ２８から構成される。列選択トランジスタ２８は、ゲート端子に供給される列選択信号Ｈ［ｎ］に応じてＳ／Ｈ回路６の各基本単位６ａに保持された画素信号を水平共通信号線２９に順次出力する。水平共通信号線２９を介して出力アンプ１０に供給された画素信号は増幅された後にチップ外部に出力される。 The basic unit 7 a of the MUX 7 includes a column selection transistor 28 disposed between the basic unit 6 a of the S / H circuit 6 and the horizontal common signal line 29. The column selection transistor 28 sequentially outputs the pixel signal held in each basic unit 6 a of the S / H circuit 6 to the horizontal common signal line 29 in response to the column selection signal H [n] supplied to the gate terminal. The pixel signal supplied to the output amplifier 10 via the horizontal common signal line 29 is amplified and then output to the outside of the chip.
　図５は、行選択回路３の詳細な構成を示す図である。 FIG. 5 is a diagram showing a detailed configuration of the row selection circuit 3.
　行選択回路３は、アドレスデコーダ３１と、単位セル２の各行に対応して設けられた複数の行選択用論理回路３２とから構成される。 The row selection circuit 3 includes an address decoder 31 and a plurality of row selection logic circuits 32 provided corresponding to each row of the unit cell 2.
　アドレスデコーダ３１では、制御部９から供給されるアドレス信号ＡＤＲに応じて所定の行選択用論理回路３２にＨｉ電圧が出力され、所定の行選択用論理回路３２のフリップフロップ３３にライトイネーブル信号が入力される。ライトイネーブル信号が入力されたフリップフロップ３３にはＨｉ電圧が設定され、そのフリップフロップ３３とＡＮＤゲート３４を介して接続された行の単位セル２は選択状態になる。選択された状態で、各制御用のパルスＳＥＬ＿ｓ、ＴＲＡＮ＿ｓ及びＲＳＴ＿ｓが入力されると、選択された行の単位セル２に行選択信号ＳＥＬ［ｎ］、リセット信号ＲＳＴ［ｎ］及び転送信号ＴＲＡＮ［ｎ］が供給される。単位セル２の駆動が完了したら、各フリップフロップ３３の値がＬｏ電圧にリセットされ、行選択が解除される。 In the address decoder 31, a Hi voltage is output to a predetermined row selection logic circuit 32 according to the address signal ADR supplied from the control unit 9, and a write enable signal is output to the flip-flop 33 of the predetermined row selection logic circuit 32. Entered. The Hi voltage is set in the flip-flop 33 to which the write enable signal is input, and the unit cell 2 in the row connected to the flip-flop 33 via the AND gate 34 is selected. When the control pulses SEL_s, TRAN_s, and RST_s are input in the selected state, the row selection signal SEL [n], the reset signal RST [n], and the transfer signal TRAN [ n]. When the driving of the unit cell 2 is completed, the value of each flip-flop 33 is reset to the Lo voltage, and the row selection is released.
　本実施形態の固体撮像装置は、カメラスチル撮影に使える全画素読み出しモードと動画記録機能に使える画素混合モードとを備えている。次に、それぞれのモードに関し信号読み出し動作を説明する。 The solid-state imaging device of the present embodiment has an all-pixel readout mode that can be used for camera still photography and a pixel mixture mode that can be used for a moving image recording function. Next, the signal reading operation will be described for each mode.
　図６は、本実施形態の固体撮像装置における全画素読み出しモード時の単位セル２と列回路に供給される各制御信号のタイミングを示す図である。 FIG. 6 is a diagram showing the timing of each control signal supplied to the unit cell 2 and the column circuit in the all-pixel readout mode in the solid-state imaging device of the present embodiment.
　タイミングｔ１では、１行目の単位セル２について、転送トランジスタ１２がオフ状態でリセットトランジスタ１４はオン状態であり、ＦＤ１３の電位（以下ではＶｆｄ）はＦＤリセット電位Ｖｆｄｒｓｔ（＝ＶＤＤ）に初期化される。 At timing t1, for the unit cell 2 in the first row, the transfer transistor 12 is off and the reset transistor 14 is on, and the potential of the FD 13 (hereinafter Vfd) is initialized to the FD reset potential Vfdrst (= VDD). The
　タイミングｔ２では、１行目の単位セル２について、転送トランジスタ１２及びリセットトランジスタ１４がオフ状態なので、Ｖｆｄのリセット状態は保持され、ＶｆｄはＦＤリセット電位Ｖｆｄｒｓｔに維持される。 At timing t2, since the transfer transistor 12 and the reset transistor 14 are in the OFF state for the unit cell 2 in the first row, the reset state of Vfd is maintained and Vfd is maintained at the FD reset potential Vfdrst.
　このとき、１行目の単位セル２について、行選択トランジスタ１６はオン状態のため、増幅トランジスタ１５のしきい値電圧をＶｔｈ、抵抗素子６１の抵抗値をＲ、画素電流源回路４の電流値をＩとすると、Ｖｆｄｒｓｔ－Ｖｔｈ－ＲＩ（正確にはＶｆｄｒｓｔ－Ｖｔｈ－ＲＩ－αであるが、ここではαは省略）がリセット電圧として垂直信号線１９に出力される。さらに、このリセット電圧Ｖｆｄｒｓｔ－Ｖｔｈ－ＲＩは、サンプリングトランジスタ２２がオン状態のため、クランプ容量２３の一方の端子に出力される。一方、クランプ信号とＳ／Ｈ容量入力信号とは共にＨｉ電圧であり、クランプ容量２３の他方の端子及びＳ／Ｈ容量２７の電位はＶＣＬに設定される。 At this time, for the unit cell 2 in the first row, since the row selection transistor 16 is in the ON state, the threshold voltage of the amplification transistor 15 is Vth, the resistance value of the resistance element 61 is R, and the current value of the pixel current source circuit 4 Is Vfdrst-Vth-RI (precisely Vfdrst-Vth-RI-α, where α is omitted) is output to the vertical signal line 19 as a reset voltage. Further, the reset voltage Vfdrst−Vth−RI is output to one terminal of the clamp capacitor 23 because the sampling transistor 22 is in an on state. On the other hand, both the clamp signal and the S / H capacitor input signal are Hi voltages, and the potential of the other terminal of the clamp capacitor 23 and the S / H capacitor 27 is set to VCL.
　タイミングｔ３では、１行目の単位セル２について、転送トランジスタ１２がオン状態となるため、画素１１に蓄積された信号電荷がＦＤ１３に転送され、Ｖｆｄはこの信号電荷量に応じた電圧Ｖｆｄｓｉｇだけ低下しＶｆｄｒｓｔ－Ｖｆｄｓｉｇとなる。 At the timing t3, since the transfer transistor 12 is turned on for the unit cell 2 in the first row, the signal charge accumulated in the pixel 11 is transferred to the FD 13, and Vfd is decreased by a voltage Vfdsig corresponding to the signal charge amount. Vfdrst−Vfdsig.
　タイミングｔ４では、１行目の単位セル２について、転送トランジスタ１２がオフ状態で行選択トランジスタ１６がオン状態であり、Ｖｆｄｒｓｔ－Ｖｆｄｓｉｇ－Ｖｔｈ－ＲＩがリード電圧として垂直信号線１９に出力される。これによりクランプ容量２３の入力はＶｆｄｓｉｇだけ変化する。さらに、クランプトランジスタ２４はオフ状態なので、クランプ容量２３の他方の端子の電位、すなわちＳ／Ｈ容量２７の電位はＶｆｄｓｉｇ×Ｃｃｌ／（Ｃｃｌ＋Ｃｓｈ）だけ変化する。この電位変化は垂直信号線１９におけるリセット電圧とリード電圧との差分に対応した電圧、すなわち画素信号に対応する電圧であり、タイミングｔ５では、行選択信号ＳＥＬ［１］及びＳ／Ｈ容量入力信号がＬｏ電圧となりこの画素信号がＳ／Ｈ容量２７に蓄積される。 At timing t4, for the unit cell 2 in the first row, the transfer transistor 12 is off and the row selection transistor 16 is on, and Vfdrst-Vfdsig-Vth-RI is output to the vertical signal line 19 as a read voltage. As a result, the input of the clamp capacitor 23 changes by Vfdsig. Further, since the clamp transistor 24 is in the OFF state, the potential of the other terminal of the clamp capacitor 23, that is, the potential of the S / H capacitor 27 changes by Vfdsig × Ccl / (Ccl + Csh). This potential change is a voltage corresponding to the difference between the reset voltage and the read voltage in the vertical signal line 19, that is, a voltage corresponding to the pixel signal, and at timing t5, the row selection signal SEL [1] and the S / H capacitor input signal. Becomes the Lo voltage, and this pixel signal is accumulated in the S / H capacitor 27.
　以上により１行分の画素信号がＳ／Ｈ回路６に保持されることになる。 Thus, the pixel signals for one row are held in the S / H circuit 6.
　次に、タイミングｔ１１では、列選択信号Ｈ［１］がＨｉ電圧となり、１列目の列選択トランジスタ２８がオン状態となる。これにより１列目のＳ／Ｈ容量２７の画素信号が水平共通信号線２９に出力され、出力アンプ１０を介してチップ外部に出力される。 Next, at the timing t11, the column selection signal H [1] becomes the Hi voltage, and the column selection transistor 28 in the first column is turned on. As a result, the pixel signal of the S / H capacitor 27 in the first column is output to the horizontal common signal line 29 and is output to the outside of the chip via the output amplifier 10.
　タイミングｔ１２では、列選択信号Ｈ［２］がＨｉ電圧となり、２列目の列選択トランジスタ２８がオン状態となる。これにより２列目のＳ／Ｈ容量２７の画素信号が水平共通信号線２９に出力され、出力アンプ１０を介してチップ外部に出力される。 At timing t12, the column selection signal H [2] becomes the Hi voltage, and the column selection transistor 28 in the second column is turned on. As a result, the pixel signal of the S / H capacitor 27 in the second column is output to the horizontal common signal line 29 and output to the outside of the chip via the output amplifier 10.
　同様に順次列選択信号Ｈ［３］、Ｈ［４］・・・をＨｉ電圧にすれば各列のＳ／Ｈ容量２７の画素信号が順次チップ外部に出力される。 Similarly, if the column selection signals H [3], H [4],... Are sequentially set to the Hi voltage, the pixel signals of the S / H capacitors 27 in each column are sequentially output outside the chip.
　以上より、１行分の画素信号が順次チップ外部に出力される。 As described above, pixel signals for one row are sequentially output to the outside of the chip.
　図６の動作を撮像領域１の行数だけ繰り返せば、撮像領域１全体の画素信号が読み出されることになる。 If the operation of FIG. 6 is repeated for the number of rows in the imaging area 1, the pixel signals of the entire imaging area 1 are read out.
　図７は、本実施形態の固体撮像装置における垂直２画素水平２画素の画素混合モード時の単位セル２と列回路に供給される各制御信号のタイミングを示す図である。 FIG. 7 is a diagram showing the timing of each control signal supplied to the unit cell 2 and the column circuit in the pixel mixing mode of two vertical pixels and two horizontal pixels in the solid-state imaging device of the present embodiment.
　タイミングｔ１では、行選択信号ＳＥＬ［１］及びＳＥＬ［２］が共にＨｉ電圧で１行目及び２行目の単位セル２が選択されている。その選択された単位セル２では、転送トランジスタ１２がオフ状態でリセットトランジスタ１４はオン状態であり、ＶｆｄはＦＤリセット電位Ｖｆｄｒｓｔ（＝ＶＤＤ）に初期化される。２つの行の単位セル２に同時に行選択信号ＳＥＬ［１］及びＳＥＬ［２］並びにリセット信号ＲＳＴ［１］及びＲＳＴ［２］を入力するには、行選択回路３のアドレスデコーダ３１に２つのアドレス信号ＡＤＲを順次供給し、行選択用論理回路３２のフリップフロップ３３にライトイネーブル信号を順次入力しＨｉ電圧を順次設定すれば可能になる（転送信号ＴＲＡＮ［１］及びＴＲＡＮ［２］についても同様）。 At timing t1, the row selection signals SEL [1] and SEL [2] are both Hi voltage, and the unit cells 2 in the first and second rows are selected. In the selected unit cell 2, the transfer transistor 12 is off and the reset transistor 14 is on, and Vfd is initialized to the FD reset potential Vfdrst (= VDD). In order to simultaneously input the row selection signals SEL [1] and SEL [2] and the reset signals RST [1] and RST [2] to the unit cells 2 of two rows, two address decoders 31 of the row selection circuit 3 This can be achieved by sequentially supplying the address signal ADR, sequentially inputting the write enable signal to the flip-flop 33 of the row selection logic circuit 32, and sequentially setting the Hi voltage (also for the transfer signals TRAN [1] and TRAN [2]). The same).
　タイミングｔ２では、１行目及び２行目の単位セル２について、転送トランジスタ１２及びリセットトランジスタ１４がオフ状態なので、Ｖｆｄのリセット状態は保持される。 At timing t2, since the transfer transistor 12 and the reset transistor 14 are in the OFF state for the unit cells 2 in the first row and the second row, the reset state of Vfd is maintained.
　このとき、１行目及び２行目の単位セル２について、行選択トランジスタ１６はオン状態のため、Ｖｆｄｒｓｔ－Ｖｔｈ－ＲＩ／２がリセット電圧として垂直信号線１９に出力される（正確にはＶｆｄｒｓｔ－Ｖｔｈ－ＲＩ／２－αであるが、ここではαは省略）。さらに、このリセット電圧Ｖｆｄｒｓｔ－Ｖｔｈは、サンプリングトランジスタ２２がオン状態のため、クランプ容量２３の一方の端子に出力される。一方、クランプ信号とＳ／Ｈ容量入力信号とは共にＨｉ電圧であり、クランプ容量２３の他方の端子及びＳ／Ｈ容量２７の電位はＶＣＬに設定される。 At this time, for the unit cells 2 in the first and second rows, since the row selection transistor 16 is in an on state, Vfdrst−Vth−RI / 2 is output to the vertical signal line 19 as a reset voltage (more precisely, Vfdrst -Vth-RI / 2-α, where α is omitted). Further, the reset voltage Vfdrst−Vth is output to one terminal of the clamp capacitor 23 because the sampling transistor 22 is in the ON state. On the other hand, both the clamp signal and the S / H capacitor input signal are Hi voltages, and the potential of the other terminal of the clamp capacitor 23 and the S / H capacitor 27 is set to VCL.
　タイミングｔ３では、１行目及び２行目の単位セル２について、転送トランジスタ１２がオン状態となるため、１行目及び２行目の単位セル２の画素１１に蓄積された信号電荷がＦＤ１３に転送され、１行目及び２行目の単位セル２それぞれのＦＤ電位Ｖｆｄ１、Ｖｆｄ２はこの信号電荷量に応じた電圧Ｖｆｄｓｉｇ１、Ｖｆｄｓｉｇ２だけ低下しＶｆｄｒｓｔ－Ｖｆｄｓｉｇ１、Ｖｆｄｒｓｔ－Ｖｆｄｓｉｇ２となる。 At the timing t3, the transfer transistors 12 are turned on for the unit cells 2 in the first and second rows, so that the signal charges accumulated in the pixels 11 of the unit cells 2 in the first and second rows are transferred to the FD 13. The FD potentials Vfd1 and Vfd2 of the unit cells 2 in the first row and the second row are reduced by the voltages Vfdsig1 and Vfdsig2 corresponding to the signal charge amounts to Vfdrst−Vfdsig1 and Vfdrst−Vfdsig2.
　タイミングｔ４では、１行目及び２行目の単位セル２について転送トランジスタ１２がオフ状態で行選択トランジスタ１６がオン状態であり、Ｖｆｄｓｉｇ１とＶｆｄｓｉｇ２との平均をＶｆｄｓｉｇとしたとき、Ｖｆｄｒｓｔ－Ｖｆｄｓｉｇ－Ｖｔｈ－ＲＩ／２がリード電圧として垂直信号線１９に出力される。このリード電圧は１行目及び２行目の単位セル２の混合信号に相当する。この垂直信号線１９の電位変化によりクランプ容量２３の入力もＶｆｄｓｉｇだけ変化する。さらに、クランプトランジスタ２４はオフ状態なので、クランプ容量２３の他方の端子の電位、すなわちＳ／Ｈ容量２７の電位はＶｆｄｓｉｇ×Ｃｃｌ／（Ｃｃｌ＋Ｃｓｈ）だけ変化する。この電位変化は垂直信号線１９におけるリセット電圧とリード電圧との差分に対応した電圧、すなわち１行目及び２行目の単位セル２の平均化された画素信号（垂直画素混合信号）であり、タイミングｔ５で行選択信号ＳＥＬ［１］及びＳＥＬ［２］並びにＳ／Ｈ容量入力信号がＬｏ電圧となりＳ／Ｈ容量２７に蓄積される。 At timing t4, when the transfer transistor 12 is off and the row selection transistor 16 is on for the unit cells 2 in the first and second rows, and Vfdsig1 and Vfdsig2 are averaged to Vfdsig, Vfdrst−Vfdsig−Vth -RI / 2 is output to the vertical signal line 19 as a read voltage. This read voltage corresponds to the mixed signal of the unit cells 2 in the first and second rows. Due to the potential change of the vertical signal line 19, the input of the clamp capacitor 23 also changes by Vfdsig. Further, since the clamp transistor 24 is in the OFF state, the potential of the other terminal of the clamp capacitor 23, that is, the potential of the S / H capacitor 27 changes by Vfdsig × Ccl / (Ccl + Csh). This potential change is a voltage corresponding to the difference between the reset voltage and the read voltage in the vertical signal line 19, that is, an averaged pixel signal (vertical pixel mixed signal) of the unit cells 2 in the first and second rows. At timing t5, the row selection signals SEL [1] and SEL [2] and the S / H capacitor input signal become Lo voltage and are stored in the S / H capacitor 27.
　タイミングｔ１１では、Ｓ／Ｈ容量入力信号と列選択信号Ｈ［１］及びＨ［２］とがＨｉ電圧となり、１列目及び２列目の列選択トランジスタ２８がオン状態となる。これにより、１列目のＳ／Ｈ容量２７と２列目のＳ／Ｈ容量２７との平均信号が水平共通信号線２９に出力され、出力アンプ１０を介してチップ外部に出力される。 At timing t11, the S / H capacitor input signal and the column selection signals H [1] and H [2] are set to the Hi voltage, and the column selection transistors 28 in the first column and the second column are turned on. As a result, the average signal of the S / H capacitor 27 in the first column and the S / H capacitor 27 in the second column is output to the horizontal common signal line 29 and output to the outside of the chip via the output amplifier 10.
　タイミングｔ１２では、列選択信号Ｈ［３］及びＨ［４］がＨｉ電圧となり、３列目及び４列目の列選択トランジスタ２８がオン状態となる。これにより、３列目のＳ／Ｈ容量２７と４列目のＳ／Ｈ容量２７との平均信号が水平共通信号線２９に出力され、出力アンプ１０を介してチップ外部に出力される。 At timing t12, the column selection signals H [3] and H [4] become Hi voltage, and the column selection transistors 28 in the third and fourth columns are turned on. As a result, an average signal of the S / H capacitors 27 in the third column and the S / H capacitors 27 in the fourth column is output to the horizontal common signal line 29 and output to the outside of the chip via the output amplifier 10.
　同様に順次列選択信号Ｈ［５］、Ｈ［６］・・・をＨｉ電圧にすれば各列のＳ／Ｈ容量２７の画素信号の平均信号が順次チップ外部に出力される。 Similarly, if the column selection signals H [5], H [6],... Are sequentially set to the Hi voltage, the average signal of the pixel signals of the S / H capacitors 27 in each column is sequentially output outside the chip.
　以上より、垂直２画素水平２画素の画素信号が混合された信号が順次チップ外部に出力される。 From the above, a signal in which pixel signals of two vertical pixels and two horizontal pixels are mixed is sequentially output to the outside of the chip.
　図７の動作を撮像領域１の単位セル２の行数／２だけ繰り返せば、撮像領域１全体の信号が読み出されることになる。 7 is repeated by the number of rows of the unit cells 2 in the imaging region 1/2, the signal of the entire imaging region 1 is read out.
　次に、全画素読み出しモード時（図６）のタイミングｔ４における増幅トランジスタ１５と画素電流源回路４とで構成される画素ソースフォロア（ＳＦ）の動作の詳細を説明する。 Next, details of the operation of the pixel source follower (SF) composed of the amplification transistor 15 and the pixel current source circuit 4 at the timing t4 in the all-pixel readout mode (FIG. 6) will be described.
　図８は全画素読み出しモード時（図６）のタイミングｔ４におけるＶｆｄと画素ＳＦ出力Ｖｏとの関係を示す図である。ＶｆｄとＶｏとの関係は式（１）及び（２）で表される。 FIG. 8 is a diagram showing the relationship between Vfd and pixel SF output Vo at timing t4 in the all-pixel readout mode (FIG. 6). The relationship between Vfd and Vo is expressed by equations (1) and (2).
　　Ｖｏ＝Ｖｆｄ－Ｖｔｈ－ＲＩ－√（Ｉ／ａ）・・・・・（１）
　　ａ＝（１／２）×（Ｗ／Ｌ）×μｅｆｆ×Ｃｏｘ・・・・・（２） Vo = Vfd−Vth−RI−√ (I / a) (1)
a = (1/2) × (W / L) × μeff × Cox (2)
　ここで、Ｖｔｈ、Ｗ、Ｌ、μｅｆｆ及びＣｏｘは増幅トランジスタ１５のしきい値電圧、ゲート幅、ゲート長、キャリア移動度及びゲート酸化膜厚を示し、Ｉは画素電流源回路４の電流値を示す。厳密にはＶｏが変化すると増幅トランジスタ１５のソース－基板電位が変化しＶｔｈも変化するが、ここではＶｔｈは固定値として扱う。 Here, Vth, W, L, μeff, and Cox indicate the threshold voltage, gate width, gate length, carrier mobility, and gate oxide film thickness of the amplification transistor 15, and I indicates the current value of the pixel current source circuit 4. Show. Strictly speaking, when Vo changes, the source-substrate potential of the amplification transistor 15 changes and Vth also changes. Here, Vth is treated as a fixed value.
　ＶｏはＶｆｄから固定値を引いた値になるという線形な特性を示す。Ｖｆｄはタイミングｔ２では、その初期値Ｖｆｄｒｓｔにあり、タイミングｔ３で画素１１の信号電荷が転送され電位はさがる。この２つのＶｆｄの値に対する画素ＳＦの出力電位の差を列回路で検出することにより画素信号が検出される。 Vo shows a linear characteristic that becomes a value obtained by subtracting a fixed value from Vfd. Vfd is at the initial value Vfdrst at the timing t2, and the signal charge of the pixel 11 is transferred at the timing t3 to reduce the potential. A pixel signal is detected by detecting the difference in the output potential of the pixel SF with respect to the two values of Vfd by a column circuit.
　次に、垂直２画素水平２画素の画素混合モード時（図７）のタイミングｔ４における画素ＳＦの動作の詳細を説明する。 Next, the details of the operation of the pixel SF at the timing t4 in the pixel mixing mode of two vertical pixels and two horizontal pixels (FIG. 7) will be described.
　図９は、垂直２画素の信号の混合を行う場合の１行目の単位セル２のＦＤ電位Ｖｆｄ１及び２行目の単位セル２のＦＤ電位Ｖｆｄ２と画素ＳＦ出力Ｖｏとの関係を示す図である。 FIG. 9 is a diagram showing the relationship between the FD potential Vfd1 of the unit cell 2 in the first row and the FD potential Vfd2 of the unit cell 2 in the second row and the pixel SF output Vo when mixing signals of two vertical pixels. is there.
　曲線１はＶｆｄ１＝Ｖｆｄ２のときの特性であり、曲線２はＶｆｄ１をＶｆｄｒｓｔに固定し、Ｖｆｄ２＝ＶｆｄとしてＶｆｄ２のみを変化させたときの特性である。Ｖｆｄ１＝Ｖｆｄ２のときの特性は信号の混合を行わないときの特性と同様であり式（３）で表される。 Curve 1 is a characteristic when Vfd1 = Vfd2, and curve 2 is a characteristic when Vfd1 is fixed to Vfdrst and only Vfd2 is changed with Vfd2 = Vfd. The characteristic when Vfd1 = Vfd2 is the same as the characteristic when signal mixing is not performed, and is expressed by Expression (3).
　　Ｖｏ＝Ｖｆｄ－Ｖｔｈ－ＲＩ／２－√（Ｉ／２ａ）・・・・・（３） Vo = Vfd-Vth-RI / 2-√ (I / 2a) (3)
　Ｖｆｄ１＝Ｖｆｄ２のときには増幅トランジスタ１５と画素ＳＦ出力との間の抵抗が１／２になり、電圧低下量が小さくなっている。一方、曲線２ではＶｆｄがＶｆｄｒｓｔから低下したとき一定範囲は線形な特性を示し、２つのＶｆｄの平均に対応する出力が得られる。しかし、ＶｏがＶｆｄｒｓｔ－Ｖｔｈ－ＲＩ－√（Ｉ／ａ）に近づくと低下しなくなる。Ｖｏの低下が飽和したときには最初２つの増幅トランジスタ１５に分かれて流れていた電流がすべてＶｆｄの高い側の一方の増幅トランジスタ１５に流れることになる。これよりＦＤ１３の動作可能レンジΔＶが決まり式（４）で表される。 When Vfd1 = Vfd2, the resistance between the amplification transistor 15 and the pixel SF output is halved, and the amount of voltage drop is small. On the other hand, in the curve 2, when Vfd decreases from Vfdrst, the certain range shows a linear characteristic, and an output corresponding to the average of the two Vfd is obtained. However, when Vo approaches Vfdrst−Vth−RI−√ (I / a), it does not decrease. When the drop in Vo is saturated, all of the current that has flowed in the two amplification transistors 15 first flows to one amplification transistor 15 on the higher Vfd side. From this, the operable range ΔV of the FD 13 is determined and expressed by equation (4).
　　ΔＶ＝ＲＩ＋（２－√２）×√（Ｉ／ａ）・・・・・（４） ΔV = RI + (2-√2) × √ (I / a) (4)
　式（４）より増幅トランジスタ１５にシリアルに挿入した抵抗素子６１は垂直に並ぶ複数画素の信号混合における所望の動作レンジの確保を可能にすることがわかる。 From equation (4), it can be seen that the resistance element 61 serially inserted into the amplification transistor 15 can ensure a desired operating range in the signal mixing of a plurality of pixels arranged vertically.
　以上のように本実施形態の固体撮像装置では、垂直信号線１９で単位セル２から出力された信号を混合する場合においても、抵抗素子６１により所望のＦＤ１３の動作レンジを確保できる。その結果、全画素読み出しモード及び画素混合モードの両方で信号読み出し時の動作電流の変動を抑えることができるため、高画質な画像を得ることができる。 As described above, in the solid-state imaging device of the present embodiment, a desired operating range of the FD 13 can be secured by the resistance element 61 even when signals output from the unit cells 2 are mixed by the vertical signal line 19. As a result, fluctuations in the operating current during signal readout can be suppressed in both the all-pixel readout mode and the pixel mixture mode, so that a high-quality image can be obtained.
　なお、図２の単位セル２は、増幅トランジスタ、転送トランジスタ、リセットトランジスタ及び行選択トランジスタという４つのトランジスタを用いた構成であるが、増幅トランジスタ、転送トランジスタ及びリセットトランジスタという３つのトランジスタのみを含む構成でもかまわない。このときの単位セル２の行選択は読み出しを行わない行の単位セル２のＶｆｄに低い電位を設定することにより実行される。 The unit cell 2 in FIG. 2 has a configuration using four transistors, that is, an amplification transistor, a transfer transistor, a reset transistor, and a row selection transistor, but includes only three transistors, an amplification transistor, a transfer transistor, and a reset transistor. But it doesn't matter. At this time, the row selection of the unit cell 2 is executed by setting a low potential to the Vfd of the unit cell 2 in the row where reading is not performed.
　（第２の実施形態）
　本発明の第２の実施形態による固体撮像装置の全体構成は図１に示す第１の実施形態の固体撮像装置の全体構成と同じである。 (Second Embodiment)
The overall configuration of the solid-state imaging device according to the second embodiment of the present invention is the same as the overall configuration of the solid-state imaging device according to the first embodiment shown in FIG.
　図１０は、第２の実施形態の固体撮像装置の撮像領域１の詳細な構成を示す回路図である。 FIG. 10 is a circuit diagram illustrating a detailed configuration of the imaging region 1 of the solid-state imaging device according to the second embodiment.
　この回路と図２に示す第１の実施形態の撮像領域１の回路との違いは増幅トランジスタ１５にシリアルに接続する抵抗がなく、行選択トランジスタ１６のオン抵抗が単位セル２を構成する他のトランジスタ（リセットトランジスタ１４又は増幅トランジスタ１５）よりも大きいことである。 The difference between this circuit and the circuit of the imaging region 1 of the first embodiment shown in FIG. 2 is that there is no resistance that is serially connected to the amplification transistor 15, and the on-resistance of the row selection transistor 16 is different from that of the unit cell 2. It is larger than the transistor (reset transistor 14 or amplification transistor 15).
　図１１は行選択回路３の詳細な構成を示す図である。 FIG. 11 is a diagram showing a detailed configuration of the row selection circuit 3.
　この行選択回路３と図５に示す第１の実施形態の行選択回路３との違いは行選択信号ＳＥＬ［ｎ］を生成するＡＮＤゲート３４の電源として別電位ＶＤＤＬが供給されていることである。ＶＤＤＬは他の回路の電源よりも低い電圧に設定される。リセットトランジスタ１４及び行選択トランジスタ１６のゲート端子にはＨｉ電圧及びＨｉ電圧より低いＬｏ電圧のいずれかが行選択信号ＳＥＬにより供給されるが、行選択トランジスタ１６のゲート端子に供給されるＨｉ電圧はリセットトランジスタ１４のゲート端子に供給されるＨｉ電圧よりも低くなるため、行選択トランジスタ１６がオン状態になるときの行選択トランジスタ１６のオン抵抗が比較的大きな値になる。 The difference between the row selection circuit 3 and the row selection circuit 3 of the first embodiment shown in FIG. 5 is that another potential VDDL is supplied as a power source of the AND gate 34 that generates the row selection signal SEL [n]. is there. VDDL is set to a voltage lower than the power supply of other circuits. Either the Hi voltage or the Lo voltage lower than the Hi voltage is supplied to the gate terminals of the reset transistor 14 and the row selection transistor 16 by the row selection signal SEL. The Hi voltage supplied to the gate terminal of the row selection transistor 16 is Since the voltage is lower than the Hi voltage supplied to the gate terminal of the reset transistor 14, the on-resistance of the row selection transistor 16 when the row selection transistor 16 is turned on becomes a relatively large value.
　本実施形態の固体撮像装置は、カメラスチル撮影に使える全画素読み出しモードと動画記録機能に使える画素混合モードとを備えている。次に、それぞれのモードに関し信号読み出し動作を説明する。 The solid-state imaging device of the present embodiment has an all-pixel readout mode that can be used for camera still photography and a pixel mixture mode that can be used for a moving image recording function. Next, the signal reading operation will be described for each mode.
　本実施形態の固体撮像装置における全画素読み出しモード時の単位セル２と列回路に供給される各制御信号のタイミングは図６に示す第１の実施形態のタイミングと同じである。 The timing of each control signal supplied to the unit cell 2 and the column circuit in the all-pixel readout mode in the solid-state imaging device of the present embodiment is the same as the timing of the first embodiment shown in FIG.
　すなわち、タイミングｔ１では、１行目の単位セル２について、転送トランジスタ１２がオフ状態でリセットトランジスタ１４はオン状態であり、ＶｆｄはＦＤリセット電位Ｖｆｄｒｓｔ（＝ＶＤＤ）に初期化される。 That is, at the timing t1, for the unit cell 2 in the first row, the transfer transistor 12 is off and the reset transistor 14 is on, and Vfd is initialized to the FD reset potential Vfdrst (= VDD).
　タイミングｔ２では、１行目の単位セル２について、転送トランジスタ１２及びリセットトランジスタ１４がオフ状態なので、Ｖｆｄのリセット状態は保持され、ＶｆｄはＦＤリセット電位Ｖｆｄｒｓｔに維持される。 At timing t2, since the transfer transistor 12 and the reset transistor 14 are in the OFF state for the unit cell 2 in the first row, the reset state of Vfd is maintained and Vfd is maintained at the FD reset potential Vfdrst.
　このとき、１行目の単位セル２について、行選択トランジスタ１６はオン状態であるが、そのゲート電位が低いため、オン抵抗が無視できない大きさＲとなる。増幅トランジスタ１５のしきい値電圧をＶｔｈ、画素電流源回路４の電流値をＩとすると、Ｖｆｄｒｓｔ－Ｖｔｈ－ＲＩ（正確にはＶｆｄｒｓｔ－Ｖｔｈ－ＲＩ－αであるが、ここではαは省略）がリセット電圧として垂直信号線１９に出力される。さらに、このリセット電圧Ｖｆｄｒｓｔ－Ｖｔｈ－ＲＩは、サンプリングトランジスタ２２がオン状態のため、クランプ容量２３の一方の端子に出力される。一方、クランプ信号とＳ／Ｈ容量入力信号は共にＨｉ電圧であり、クランプ容量２３の他方の端子及びＳ／Ｈ容量２７の電位はＶＣＬに設定される。 At this time, for the unit cell 2 in the first row, the row selection transistor 16 is in the ON state, but since the gate potential is low, the ON resistance becomes a magnitude R that cannot be ignored. Assuming that the threshold voltage of the amplification transistor 15 is Vth and the current value of the pixel current source circuit 4 is I, Vfdrst-Vth-RI (exactly Vfdrst-Vth-RI-α, where α is omitted) Is output to the vertical signal line 19 as a reset voltage. Further, the reset voltage Vfdrst−Vth−RI is output to one terminal of the clamp capacitor 23 because the sampling transistor 22 is in an on state. On the other hand, both the clamp signal and the S / H capacitor input signal are Hi voltages, and the potential of the other terminal of the clamp capacitor 23 and the S / H capacitor 27 is set to VCL.
　タイミングｔ３では、１行目の単位セル２について、転送トランジスタ１２がオン状態となるため、画素１１に蓄積された信号電荷がＦＤ１３に転送され、Ｖｆｄはこの信号電荷量に応じた電圧Ｖｆｄｓｉｇだけ低下しＶｆｄｒｓｔ－Ｖｆｄｓｉｇとなる。 At the timing t3, since the transfer transistor 12 is turned on for the unit cell 2 in the first row, the signal charge accumulated in the pixel 11 is transferred to the FD 13, and Vfd is decreased by a voltage Vfdsig corresponding to the signal charge amount. Vfdrst−Vfdsig.
　タイミングｔ４では、１行目の単位セル２について、転送トランジスタ１２がオフ状態で行選択トランジスタ１６がオン状態であり、Ｖｆｄｒｓｔ－Ｖｆｄｓｉｇ－Ｖｔｈ－ＲＩがリード電圧として垂直信号線１９に出力される。これによりクランプ容量２３の入力はＶｆｄｓｉｇだけ変化する。さらに、クランプトランジスタ２４はオフ状態なので、クランプ容量２３の他方の端子の電位、すなわちＳ／Ｈ容量２７の電位はＶｆｄｓｉｇ×Ｃｃｌ／（Ｃｃｌ＋Ｃｓｈ）だけ変化する。この電位変化は垂直信号線１９におけるリセット電圧とリード電圧との差分に対応した電圧、すなわち画素信号に対応する電圧であり、タイミングｔ５では、行選択信号ＳＥＬ［１］及びＳ／Ｈ容量入力信号がＬｏ電圧となりこの画素信号がＳ／Ｈ容量２７に蓄積される。 At timing t4, for the unit cell 2 in the first row, the transfer transistor 12 is off and the row selection transistor 16 is on, and Vfdrst-Vfdsig-Vth-RI is output to the vertical signal line 19 as a read voltage. As a result, the input of the clamp capacitor 23 changes by Vfdsig. Further, since the clamp transistor 24 is in the OFF state, the potential of the other terminal of the clamp capacitor 23, that is, the potential of the S / H capacitor 27 changes by Vfdsig × Ccl / (Ccl + Csh). This potential change is a voltage corresponding to the difference between the reset voltage and the read voltage in the vertical signal line 19, that is, a voltage corresponding to the pixel signal, and at timing t5, the row selection signal SEL [1] and the S / H capacitor input signal. Becomes the Lo voltage, and this pixel signal is accumulated in the S / H capacitor 27.
　以上により１行分の画素信号がＳ／Ｈ回路６に保持されることになる。 Thus, the pixel signals for one row are held in the S / H circuit 6.
　次に、タイミングｔ１１では、列選択信号Ｈ［１］がＨｉ電圧となり、１列目の列選択トランジスタ２８がオン状態となる。これにより１列目のＳ／Ｈ容量２７の画素信号が水平共通信号線２９に出力され、出力アンプ１０を介してチップ外部に出力される。 Next, at the timing t11, the column selection signal H [1] becomes the Hi voltage, and the column selection transistor 28 in the first column is turned on. As a result, the pixel signal of the S / H capacitor 27 in the first column is output to the horizontal common signal line 29 and is output to the outside of the chip via the output amplifier 10.
　タイミングｔ１２では、列選択信号Ｈ［２］がＨｉ電圧となり、２列目の列選択トランジスタ２８がオン状態となる。これにより２列目のＳ／Ｈ容量２７の画素信号が水平共通信号線２９に出力され、出力アンプ１０を介してチップ外部に出力される。 At timing t12, the column selection signal H [2] becomes the Hi voltage, and the column selection transistor 28 in the second column is turned on. As a result, the pixel signal of the S / H capacitor 27 in the second column is output to the horizontal common signal line 29 and output to the outside of the chip via the output amplifier 10.
　同様に順次列選択信号Ｈ［３］、Ｈ［４］・・・をＨｉ電圧にすれば各列のＳ／Ｈ容量２７の画素信号が順次チップ外部に出力される。 Similarly, if the column selection signals H [3], H [4],... Are sequentially set to the Hi voltage, the pixel signals of the S / H capacitors 27 in each column are sequentially output outside the chip.
　以上より、１行分の画素信号が順次チップ外部に出力される。 As described above, pixel signals for one row are sequentially output to the outside of the chip.
　図６の動作を撮像領域１の行数だけ繰り返せば、撮像領域１全体の画素信号が読み出されることになる。 If the operation of FIG. 6 is repeated for the number of rows in the imaging area 1, the pixel signals of the entire imaging area 1 are read out.
　本実施形態の固体撮像装置における垂直２画素水平２画素の画素混合モード時の単位セル２と列回路に供給される各制御信号のタイミングは図７に示す第１の実施形態のタイミングと同じである。 The timing of each control signal supplied to the unit cell 2 and the column circuit in the pixel mixing mode of two vertical pixels and two horizontal pixels in the solid-state imaging device of this embodiment is the same as the timing of the first embodiment shown in FIG. is there.
　すなわち、タイミングｔ１では、行選択信号ＳＥＬ［１］及びＳＥＬ［２］が共にＨｉ電圧で１行目及び２行目の単位セル２が選択されている。その選択された単位セル２では、転送トランジスタ１２がオフ状態でリセットトランジスタ１４はオン状態であり、ＶｆｄはＦＤリセット電位Ｖｆｄｒｓｔ（＝ＶＤＤ）に初期化される。２つの行の単位セル２に同時に行選択信号ＳＥＬ［１］及びＳＥＬ［２］並びにリセット信号ＲＳＴ［１］及びＲＳＴ［２］を入力するには、行選択回路３のアドレスデコーダ３１に２つのアドレス信号ＡＤＲを順次供給し、行選択用論理回路３２のフリップフロップ３３にライトイネーブル信号を順次入力しＨｉ電圧を順次設定すれば可能になる（転送信号ＴＲＡＮ［１］及びＴＲＡＮ［２］についても同様）。 That is, at the timing t1, the row selection signals SEL [1] and SEL [2] are both Hi voltage, and the unit cells 2 in the first and second rows are selected. In the selected unit cell 2, the transfer transistor 12 is off and the reset transistor 14 is on, and Vfd is initialized to the FD reset potential Vfdrst (= VDD). In order to simultaneously input the row selection signals SEL [1] and SEL [2] and the reset signals RST [1] and RST [2] to the unit cells 2 of two rows, two address decoders 31 of the row selection circuit 3 This can be achieved by sequentially supplying the address signal ADR, sequentially inputting the write enable signal to the flip-flop 33 of the row selection logic circuit 32, and sequentially setting the Hi voltage (also for the transfer signals TRAN [1] and TRAN [2]). The same).
　タイミングｔ２では、１行目及び２行目の単位セル２について、転送トランジスタ１２及びリセットトランジスタ１４がオフ状態なので、Ｖｆｄのリセット状態は保持される。 At timing t2, since the transfer transistor 12 and the reset transistor 14 are in the OFF state for the unit cells 2 in the first row and the second row, the reset state of Vfd is maintained.
　このとき、１行目及び２行目の単位セル２について、行選択トランジスタ１６はオン状態であるが、そのゲート電位が低いためオン抵抗が無視できない大きさＲとなり、Ｖｆｄｒｓｔ－Ｖｔｈ－ＲＩ／２（正確にはＶｆｄｒｓｔ－Ｖｔｈ－ＲＩ／２－αであるが、ここではαは省略）がリセット電圧として垂直信号線１９に出力される。さらに、このリセット電圧Ｖｆｄｒｓｔ－Ｖｔｈ－ＲＩ／２は、サンプリングトランジスタ２２がオン状態のため、クランプ容量２３の一方の端子に出力される。一方、クランプ信号とＳ／Ｈ容量入力信号とはＨｉ電圧であり、クランプ容量２３の他方の端子及びＳ／Ｈ容量２７の電位はＶＣＬに設定される。 At this time, for the unit cells 2 in the first row and the second row, the row selection transistor 16 is in the on state, but the on-resistance becomes a magnitude R that cannot be ignored because the gate potential is low, and Vfdrst−Vth−RI / 2. (To be precise, Vfdrst−Vth−RI / 2−α, where α is omitted) is output to the vertical signal line 19 as a reset voltage. Further, the reset voltage Vfdrst−Vth−RI / 2 is output to one terminal of the clamp capacitor 23 because the sampling transistor 22 is in the ON state. On the other hand, the clamp signal and the S / H capacitor input signal are Hi voltages, and the potential of the other terminal of the clamp capacitor 23 and the S / H capacitor 27 is set to VCL.
　タイミングｔ３では、１行目及び２行目の単位セル２について、転送トランジスタ１２がオン状態となるため、１行目及び２行目の単位セル２の画素１１に蓄積された信号電荷がＦＤ１３に転送され、１行目及び２行目の単位セル２それぞれのＦＤ電位Ｖｆｄ１、Ｖｆｄ２はこの信号電荷量に応じた電圧Ｖｆｄｓｉｇ１、Ｖｆｄｓｉｇ２だけ低下しＶｆｄｒｓｔ－Ｖｆｄｓｉｇ１、Ｖｆｄｒｓｔ－Ｖｆｄｓｉｇ２となる。 At the timing t3, the transfer transistors 12 are turned on for the unit cells 2 in the first and second rows, so that the signal charges accumulated in the pixels 11 of the unit cells 2 in the first and second rows are transferred to the FD 13. The FD potentials Vfd1 and Vfd2 of the unit cells 2 in the first row and the second row are reduced by the voltages Vfdsig1 and Vfdsig2 corresponding to the signal charge amounts to Vfdrst−Vfdsig1 and Vfdrst−Vfdsig2.
　タイミングｔ４では、１行目及び２行目の単位セル２について転送トランジスタ１２がオフ状態で行選択トランジスタ１６がオン状態であり、Ｖｆｄｓｉｇ１とＶｆｄｓｉｇ２との平均をＶｆｄｓｉｇとしたとき、Ｖｆｄｒｓｔ－Ｖｆｄｓｉｇ－Ｖｔｈ－ＲＩ／２がリード電圧として垂直信号線１９に出力される。このリード電圧は１行目及び２行目の単位セル２の混合信号に相当する。この垂直信号線１９の電位変化によりクランプ容量２３の入力もＶｆｄｓｉｇだけ変化する。さらに、クランプトランジスタ２４はオフ状態なので、クランプ容量２３の他方の端子の電位、すなわちＳ／Ｈ容量２７の電位はＶｆｄｓｉｇ×Ｃｃｌ／（Ｃｃｌ＋Ｃｓｈ）だけ変化する。この電位変化は垂直信号線１９におけるリセット電圧とリード電圧との差分に対応した電圧、すなわち１行目及び２行目の単位セル２の平均化された画素信号（垂直画素混合信号）であり、タイミングｔ５で行選択信号ＳＥＬ［１］及びＳＥＬ［２］並びにＳ／Ｈ容量入力信号がＬｏ電圧となりＳ／Ｈ容量２７に蓄積される。 At timing t4, when the transfer transistor 12 is off and the row selection transistor 16 is on for the unit cells 2 in the first and second rows, and Vfdsig1 and Vfdsig2 are averaged to Vfdsig, Vfdrst−Vfdsig−Vth -RI / 2 is output to the vertical signal line 19 as a read voltage. This read voltage corresponds to the mixed signal of the unit cells 2 in the first and second rows. Due to the potential change of the vertical signal line 19, the input of the clamp capacitor 23 also changes by Vfdsig. Further, since the clamp transistor 24 is in the OFF state, the potential of the other terminal of the clamp capacitor 23, that is, the potential of the S / H capacitor 27 changes by Vfdsig × Ccl / (Ccl + Csh). This potential change is a voltage corresponding to the difference between the reset voltage and the read voltage in the vertical signal line 19, that is, an averaged pixel signal (vertical pixel mixed signal) of the unit cells 2 in the first and second rows. At timing t5, the row selection signals SEL [1] and SEL [2] and the S / H capacitor input signal become Lo voltage and are stored in the S / H capacitor 27.
　タイミングｔ１１では、Ｓ／Ｈ容量入力信号と列選択信号Ｈ［１］及びＨ［２］とがＨｉ電圧となり、１列目及び２列目の列選択トランジスタ２８がオン状態となる。これにより、１列目のＳ／Ｈ容量２７と２列目のＳ／Ｈ容量２７との平均信号が水平共通信号線２９に出力され、出力アンプ１０を介してチップ外部に出力される。 At timing t11, the S / H capacitor input signal and the column selection signals H [1] and H [2] are set to the Hi voltage, and the column selection transistors 28 in the first column and the second column are turned on. As a result, the average signal of the S / H capacitor 27 in the first column and the S / H capacitor 27 in the second column is output to the horizontal common signal line 29 and output to the outside of the chip via the output amplifier 10.
　タイミングｔ１２では、列選択信号Ｈ［３］及びＨ［４］がＨｉ電圧となり、３列目及び４列目の列選択トランジスタ２８がオン状態となる。これにより、３列目のＳ／Ｈ容量２７と４列目のＳ／Ｈ容量２７との平均信号が水平共通信号線２９に出力され、出力アンプ１０を介してチップ外部に出力される。 At timing t12, the column selection signals H [3] and H [4] become Hi voltage, and the column selection transistors 28 in the third and fourth columns are turned on. As a result, an average signal of the S / H capacitors 27 in the third column and the S / H capacitors 27 in the fourth column is output to the horizontal common signal line 29 and output to the outside of the chip via the output amplifier 10.
　同様に順次列選択信号Ｈ［５］、Ｈ［６］・・・をＨｉ電圧にすれば各列のＳ／Ｈ容量２７の画素信号の平均信号が順次チップ外部に出力される。 Similarly, if the column selection signals H [5], H [6],... Are sequentially set to the Hi voltage, the average signal of the pixel signals of the S / H capacitors 27 in each column is sequentially output outside the chip.
　以上より、垂直２画素水平２画素の信号が混合された画素信号が順次チップ外部に出力される。 From the above, pixel signals in which signals of 2 vertical pixels and 2 horizontal pixels are mixed are sequentially output to the outside of the chip.
　図７の動作を撮像領域１の単位セル２の行数／２だけ繰り返せば、撮像領域１全体の信号が読み出されることになる。 7 is repeated by the number of rows of the unit cells 2 in the imaging region 1/2, the signal of the entire imaging region 1 is read out.
　この画素混合モードでのＦＤレンジΔＶは第１の実施形態と同様に式（４）であらわされる。行選択トランジスタ１６のゲート電位のＨｉ電圧をさげることにより生成されたオン抵抗ＲによりＦＤ１３の動作レンジを確保できることがわかる。 FD range ΔV in this pixel mixture mode is expressed by equation (4) as in the first embodiment. It can be seen that the operating range of the FD 13 can be secured by the on-resistance R generated by reducing the Hi voltage of the gate potential of the row selection transistor 16.
　以上のように、本実施の形態の固体撮像装置によれば、抵抗素子が別途設けられるのではなく、行選択トランジスタ１６を増幅トランジスタ１５とシリアルに接続された抵抗として機能させる。よって、動作電流の変動を抑えた信号の混合動作が実現できるだけでなく、抵抗素子と行選択トランジスタ１６とを１つのデバイスで実現でき、単位セル２の回路面積の縮小及び感度の向上が可能であるという利点もある。 As described above, according to the solid-state imaging device of the present embodiment, a resistance element is not provided separately, but the row selection transistor 16 functions as a resistor connected in series with the amplification transistor 15. Therefore, not only the signal mixing operation with the fluctuation of the operating current can be realized, but also the resistor element and the row selection transistor 16 can be realized by one device, and the circuit area of the unit cell 2 can be reduced and the sensitivity can be improved. There is also an advantage of being.
　なお、行選択トランジスタ１６のオン抵抗をあげるために、行選択トランジスタ１６のゲート幅を増幅トランジスタ１５のゲート幅よりも小さくする、及び行選択トランジスタ１６のしきい値電圧を増幅トランジスタ１５のしきい値電圧より大きく調整するという方法もある。また、行選択トランジスタ１６のゲート長をプロセスで許容される最小値よりも大きくする、例えば行選択トランジスタ１６のゲート長を、行選択回路３を構成するトランジスタの最小ゲート長より大きくすることでも行選択トランジスタ１６のオン抵抗をあげることができる。 In order to increase the on-resistance of the row selection transistor 16, the gate width of the row selection transistor 16 is made smaller than the gate width of the amplification transistor 15, and the threshold voltage of the row selection transistor 16 is set to the threshold of the amplification transistor 15. There is also a method of adjusting larger than the value voltage. Further, the gate length of the row selection transistor 16 is made larger than the minimum value allowed in the process. For example, the gate length of the row selection transistor 16 is made larger than the minimum gate length of the transistors constituting the row selection circuit 3. The on-resistance of the selection transistor 16 can be increased.
　ここで、行選択トランジスタ１６のゲート電位のＨｉ電圧をさげるための他の行選択回路３の構成を図１２に示す。 Here, the configuration of another row selection circuit 3 for reducing the Hi voltage of the gate potential of the row selection transistor 16 is shown in FIG.
　行選択トランジスタ１６のゲート端子にＨｉ電圧を供給する行選択信号ＳＥＬ［ｎ］を生成するＡＮＤゲート３４の電源として出力電圧が可変な可変電源６２の出力が供給されている。可変電源６２の出力は全画素読み出しモード時には高い電圧、画素混合モード時には低い電圧になる。その結果、画素混合モード時には所望のＦＤレンジΔＶの確保に有効なオン抵抗が得られ、一方全画素読み出しモード時には不要なオン抵抗を小さくでき消費電力が低減できるというメリットがある。 The output of the variable power source 62 having a variable output voltage is supplied as the power source of the AND gate 34 that generates the row selection signal SEL [n] for supplying the Hi voltage to the gate terminal of the row selection transistor 16. The output of the variable power source 62 is a high voltage in the all-pixel reading mode and a low voltage in the pixel mixing mode. As a result, an on-resistance effective for securing a desired FD range ΔV can be obtained in the pixel mixture mode, and an unnecessary on-resistance can be reduced in the all-pixel readout mode, thereby reducing power consumption.
　なお、第２の実施形態の固体撮像装置は、行選択トランジスタ１６を抵抗素子として機能させることを特徴とし、その特徴による効果を明確にするために行選択トランジスタ１６のゲート電位を低く設定する構成を説明してきた。しかし、行選択トランジスタ１６のゲート電位の調整なしでも行選択トランジスタ１６のオン抵抗は存在し、ＦＤ動作レンジΔＶが比較的狭くてもよい用途ではこのＨｉ電圧調整なしでも動作電流の変動を抑えた状態での画素信号の混合動作は実現できる。この場合は別電源が不要でありチップ全体の構成が簡素になる。電圧によるオン抵抗増大の効果がないことを補うためには、行選択トランジスタ１６のゲート幅を増幅トランジスタ１５よりも小さくする、行選択トランジスタ１６のゲート長をプロセスで許容される最小値よりも大きくする、及び行選択トランジスタ１６のしきい値電圧を大きく調整するという方法が同じく有効である。 Note that the solid-state imaging device of the second embodiment is characterized in that the row selection transistor 16 functions as a resistance element, and the gate potential of the row selection transistor 16 is set low in order to clarify the effect of the feature. Have explained. However, even if the gate potential of the row selection transistor 16 is not adjusted, the on-resistance of the row selection transistor 16 exists, and in an application where the FD operation range ΔV may be relatively narrow, fluctuations in the operating current are suppressed even without this Hi voltage adjustment. The pixel signal mixing operation in the state can be realized. In this case, a separate power source is unnecessary, and the configuration of the entire chip is simplified. In order to compensate for the absence of the effect of increasing the on-resistance due to the voltage, the gate width of the row selection transistor 16 is made smaller than that of the amplification transistor 15, and the gate length of the row selection transistor 16 is made larger than the minimum value allowed in the process. The method of adjusting the threshold voltage of the row selection transistor 16 is also effective.
　（第３の実施形態）
　本発明の第３の実施形態による固体撮像装置の全体構成は図１に示す第１の実施形態の固体撮像装置の全体構成と同じである。 (Third embodiment)
The overall configuration of the solid-state imaging device according to the third embodiment of the present invention is the same as the overall configuration of the solid-state imaging device according to the first embodiment shown in FIG.
　図１３は、撮像領域１の詳細な構成を示す回路図である。 FIG. 13 is a circuit diagram showing a detailed configuration of the imaging region 1.
　この回路と図２に示す第１及び第２の実施形態の撮像領域１の回路との違いは、増幅トランジスタ１５とシリアルに接続された抵抗として機能する素子として抵抗素子６１及び行選択トランジスタ１６のかわりに、ゲート端子が画素電源線１７と接続され、オン抵抗が単位セル２を構成する他のトランジスタ（リセットトランジスタ１４又は増幅トランジスタ１５）よりも大きい抵抗用トランジスタ６３が増幅トランジスタ１５にシリアルに接続する形で配置されていること、並びにリセットトランジスタ１４及び増幅トランジスタ１５のドレイン端子に接続される画素電源線１７に画素電源生成回路７３の出力ＶＤＤＣＥＬが供給されることである。第１及び第２の実施形態の固体撮像装置では単位セル２の行の選択動作は行選択トランジスタ１６のオン及びオフで実現するとしたが、ここでは非選択の単位セル２の行すべてのＶｆｄを低く設定することにより単位セル２の行の選択動作を実現する。ＶＤＤＣＥＬはこの非選択のための低い電位と、信号読み出しのための高い画素電位（ＶＤＤ）とに切り替えられる。 The difference between this circuit and the circuit in the imaging region 1 of the first and second embodiments shown in FIG. 2 is that the resistance element 61 and the row selection transistor 16 function as an element that functions as a resistor connected in series with the amplification transistor 15. Instead, a resistance transistor 63 whose gate terminal is connected to the pixel power supply line 17 and whose on-resistance is larger than the other transistors (reset transistor 14 or amplification transistor 15) constituting the unit cell 2 is serially connected to the amplification transistor 15. And the output VDDCEL of the pixel power supply generation circuit 73 is supplied to the pixel power supply line 17 connected to the drain terminals of the reset transistor 14 and the amplification transistor 15. In the solid-state imaging devices of the first and second embodiments, the row selection operation of the unit cell 2 is realized by turning on and off the row selection transistor 16, but here, the Vfd of all the rows of the unselected unit cell 2 is obtained. The row selection operation of the unit cell 2 is realized by setting it low. VDDCEL is switched between a low potential for non-selection and a high pixel potential (VDD) for signal readout.
　本実施形態の固体撮像装置は、カメラスチル撮影に使える全画素読み出しモードと動画記録機能に使える画素混合モードとを備えている。次に、それぞれのモードに関し信号読み出し動作を説明する。 The solid-state imaging device of the present embodiment has an all-pixel readout mode that can be used for camera still photography and a pixel mixture mode that can be used for a moving image recording function. Next, the signal reading operation will be described for each mode.
　図１４は、本実施形態の固体撮像装置における全画素読み出しモード時の単位セル２と列回路に供給される各制御信号のタイミングを示す図である。 FIG. 14 is a diagram showing the timing of each control signal supplied to the unit cell 2 and the column circuit in the all-pixel readout mode in the solid-state imaging device of the present embodiment.
　タイミングｔ１では、１行目の単位セル２について、転送トランジスタ１２がオフ状態で、ＶＤＤＣＥＬがＨｉ電圧（ＶＤＤ）の状態で、さらにリセットトランジスタ１４がオン状態であり、ＶｆｄはＦＤリセット電位Ｖｆｄｒｓｔ（＝ＶＤＤ）に初期化される。これにより、Ｖｆｄが初期化された単位セル２の行は信号読み出しのために選択された状態になる（後で述べるように、選択される前ではＦＤ電位は非選択状態に対応する低い電位に設定されている）。 At the timing t1, for the unit cell 2 in the first row, the transfer transistor 12 is in the OFF state, the VDDCEL is in the Hi voltage (VDD) state, the reset transistor 14 is in the ON state, and Vfd is the FD reset potential Vfdrst (= VDD). As a result, the row of the unit cell 2 in which Vfd is initialized is selected for signal reading (as will be described later, the FD potential is set to a low potential corresponding to the non-selected state before selection). Is set).
　タイミングｔ２では、１行目の単位セル２について、転送トランジスタ１２及びリセットトランジスタ１４がオフ状態なので、Ｖｆｄのリセット状態は保持される。 At timing t2, since the transfer transistor 12 and the reset transistor 14 are in the OFF state for the unit cell 2 in the first row, the reset state of Vfd is maintained.
　このとき、抵抗用トランジスタ６３のゲート電位ＶＤＤＣＥＬはＨｉ電圧である。従って、抵抗用トランジスタ６３はオン状態であるため、増幅トランジスタ１５のしきい値電圧をＶｔｈ、抵抗用トランジスタ６３のオン抵抗をＲ、画素電流源回路４の電流値をＩとすると、Ｖｆｄｒｓｔ－Ｖｔｈ－ＲＩ（正確にはＶｆｄｒｓｔ－Ｖｔｈ－ＲＩ－αであるが、ここではαは省略）がリセット電圧として垂直信号線１９に出力される。さらに、このリセット電圧Ｖｆｄｒｓｔ－Ｖｔｈ－ＲＩは、サンプリングトランジスタ２２がオン状態のため、クランプ容量２３の一方の端子に出力される。一方、クランプ信号とＳ／Ｈ容量入力信号とは共にＨｉ電圧であり、クランプ容量２３の他方の端子及びＳ／Ｈ容量２７の電位はＶＣＬに設定される。 At this time, the gate potential VDDCEL of the resistance transistor 63 is a Hi voltage. Accordingly, since the resistance transistor 63 is in the on state, assuming that the threshold voltage of the amplification transistor 15 is Vth, the on-resistance of the resistance transistor 63 is R, and the current value of the pixel current source circuit 4 is I, Vfdrst−Vth -RI (precisely Vfdrst-Vth-RI-α, where α is omitted) is output to the vertical signal line 19 as a reset voltage. Further, the reset voltage Vfdrst−Vth−RI is output to one terminal of the clamp capacitor 23 because the sampling transistor 22 is in an on state. On the other hand, both the clamp signal and the S / H capacitor input signal are Hi voltages, and the potential of the other terminal of the clamp capacitor 23 and the S / H capacitor 27 is set to VCL.
　タイミングｔ３では、１行目の単位セル２について、転送トランジスタ１２がオン状態となるため、画素１１に蓄積された信号電荷がＦＤ１３に転送され、Ｖｆｄはこの信号電荷量に応じた電圧Ｖｆｄｓｉｇだけ低下しＶｆｄｒｓｔ－Ｖｆｄｓｉｇとなる。 At the timing t3, since the transfer transistor 12 is turned on for the unit cell 2 in the first row, the signal charge accumulated in the pixel 11 is transferred to the FD 13, and Vfd is decreased by a voltage Vfdsig corresponding to the signal charge amount. Vfdrst−Vfdsig.
　タイミングｔ４では、１行目の単位セル２について、転送トランジスタ１２がオフ状態で抵抗用トランジスタ６３がオン状態であり、Ｖｆｄｒｓｔ－Ｖｆｄｓｉｇ－Ｖｔｈ－ＲＩがリード電圧として垂直信号線１９に出力される。これによりクランプ容量２３の入力はＶｆｄｓｉｇだけ変化する。さらに、クランプトランジスタ２４はオフ状態なので、クランプ容量２３の他方の端子の電位、すなわちＳ／Ｈ容量２７の電位はＶｆｄｓｉｇ×Ｃｃｌ／（Ｃｃｌ＋Ｃｓｈ）だけ変化する。この電位変化は垂直信号線１９におけるリセット電圧とリード電圧との差分に対応した電圧、すなわち画素信号に対応する電圧であり、タイミングｔ５では、Ｓ／Ｈ容量入力信号がＬｏ電圧となりこの画素信号がＳ／Ｈ容量２７に蓄積される。 At timing t4, for the unit cell 2 in the first row, the transfer transistor 12 is off and the resistance transistor 63 is on, and Vfdrst-Vfdsig-Vth-RI is output to the vertical signal line 19 as a read voltage. As a result, the input of the clamp capacitor 23 changes by Vfdsig. Further, since the clamp transistor 24 is in the OFF state, the potential of the other terminal of the clamp capacitor 23, that is, the potential of the S / H capacitor 27 changes by Vfdsig × Ccl / (Ccl + Csh). This potential change is a voltage corresponding to the difference between the reset voltage and the read voltage in the vertical signal line 19, that is, a voltage corresponding to the pixel signal. At timing t5, the S / H capacitance input signal becomes the Lo voltage, and this pixel signal is Accumulated in the S / H capacity 27.
　以上により１行分の画素信号がＳ／Ｈ回路６に保持されることになる。 Thus, the pixel signals for one row are held in the S / H circuit 6.
　このとき、同じくタイミングｔ５ではＶＤＤＣＥＬがＬｏ電圧で、かつリセットトランジスタ１４がオン状態のため、Ｖｆｄが低い電位にセットされ、信号の読み出しが完了した行の単位セル２は非選択状態に戻ることになる。 At this time, similarly, at timing t5, VDDCEL is at the Lo voltage and the reset transistor 14 is in the ON state, so that Vfd is set to a low potential, and the unit cell 2 in the row where the signal reading is completed returns to the non-selected state. Become.
　次に、タイミングｔ１１では、列選択信号Ｈ［１］がＨｉ電圧となり、１列目の列選択トランジスタ２８がオン状態となる。これにより１列目のＳ／Ｈ容量２７の画素信号が水平共通信号線２９に出力され、出力アンプ１０を介してチップ外部に出力される。 Next, at the timing t11, the column selection signal H [1] becomes the Hi voltage, and the column selection transistor 28 in the first column is turned on. As a result, the pixel signal of the S / H capacitor 27 in the first column is output to the horizontal common signal line 29 and is output to the outside of the chip via the output amplifier 10.
　タイミングｔ１２では、列選択信号Ｈ［２］がＨｉ電圧となり、２列目の列選択トランジスタ２８がオン状態となる。これにより２列目のＳ／Ｈ容量２７の画素信号が水平共通信号線２９に出力され、出力アンプ１０を介してチップ外部に出力される。 At timing t12, the column selection signal H [2] becomes the Hi voltage, and the column selection transistor 28 in the second column is turned on. As a result, the pixel signal of the S / H capacitor 27 in the second column is output to the horizontal common signal line 29 and output to the outside of the chip via the output amplifier 10.
　同様に順次列選択信号Ｈ［３］、Ｈ［４］・・・をＨｉ電圧にすれば各列のＳ／Ｈ容量２７の画素信号が順次出力される。 Similarly, if the column selection signals H [3], H [4]... Are set to the Hi voltage, the pixel signals of the S / H capacitors 27 in each column are sequentially output.
　以上より、１行分の画素信号が順次チップ外部に出力される。 As described above, pixel signals for one row are sequentially output to the outside of the chip.
　図１４の動作を撮像領域１の行数だけ繰り返せば、撮像領域１全体の画素信号が読み出されることになる。 If the operation in FIG. 14 is repeated for the number of rows in the imaging area 1, the pixel signals of the entire imaging area 1 are read out.
　図１５は、本実施形態の固体撮像装置における垂直２画素水平２画素の画素混合モード時の単位セル２と列回路に供給される各制御信号のタイミングを示す図である。 FIG. 15 is a diagram showing the timing of each control signal supplied to the unit cell 2 and the column circuit in the pixel mixing mode of two vertical pixels and two horizontal pixels in the solid-state imaging device of the present embodiment.
　タイミングｔ１では、ＶＤＤＣＥＬがＨｉ電圧の状態で、２つのリセット信号ＲＳＴ［１］及びＲＳＴ［２］が共にＨｉ電圧であるため、１行目及び２行目の単位セル２では、ＶｆｄがＦＤリセット電位Ｖｆｄｒｓｔ（＝ＶＤＤ）に初期化される。これにより、１行目及び２行目の単位セル２は、読み出しのための選択状態になる。２つの単位セル２の行に同時にリセット信号ＲＳＴ［１］及びＲＳＴ［２］を入力するには、行選択回路３のアドレスデコーダ３１に２つのアドレス信号ＡＤＲを順次供給し、行選択用論理回路３２のフリップフロップ３３を選択状態に順次設定すれば可能になる（転送信号ＴＲＡＮ［１］及びＴＲＡＮ［２］についても同様）。 At timing t1, VDDCEL is in the Hi voltage state, and the two reset signals RST [1] and RST [2] are both in the Hi voltage. Therefore, Vfd is FD reset in the unit cells 2 in the first and second rows. Initialized to potential Vfdrst (= VDD). As a result, the unit cells 2 in the first and second rows are selected for reading. In order to simultaneously input the reset signals RST [1] and RST [2] to the rows of the two unit cells 2, the two address signals ADR are sequentially supplied to the address decoder 31 of the row selection circuit 3, and the row selection logic circuit. This can be achieved by sequentially setting the 32 flip-flops 33 to the selected state (the same applies to the transfer signals TRAN [1] and TRAN [2]).
　タイミングｔ２では、１行目及び２行目の単位セル２について、転送トランジスタ１２及びリセットトランジスタ１４がオフ状態なので、Ｖｆｄのリセット状態は保持される。 At timing t2, since the transfer transistor 12 and the reset transistor 14 are in the OFF state for the unit cells 2 in the first row and the second row, the reset state of Vfd is maintained.
　このとき、１行目及び２行目の単位セル２について、抵抗用トランジスタ６３のゲート電位ＶＤＤＣＥＬはＨｉ電圧である。従って、抵抗用トランジスタ６３はオン状態のため、Ｖｆｄｒｓｔ－Ｖｔｈ－ＲＩ／２（正確にはＶｆｄｒｓｔ－Ｖｔｈ－ＲＩ／２－αであるが、ここではαは省略）がリセット電圧として垂直信号線１９に出力される。さらに、このリセット電圧Ｖｆｄｒｓｔ－Ｖｔｈ－ＲＩ／２は、サンプリングトランジスタ２２がオン状態のため、クランプ容量２３の一方の端子に出力される。一方、クランプ信号とＳ／Ｈ容量入力信号とはＨｉ電圧であり、クランプ容量２３の他方の端子及びＳ／Ｈ容量２７の電位はＶＣＬに設定される。 At this time, the gate potential VDDCEL of the resistance transistor 63 is the Hi voltage for the unit cells 2 in the first row and the second row. Accordingly, since the resistance transistor 63 is in the ON state, Vfdrst−Vth−RI / 2 (precisely Vfdrst−Vth−RI / 2−α, where α is omitted) is used as the reset voltage as the vertical signal line 19. Is output. Further, the reset voltage Vfdrst−Vth−RI / 2 is output to one terminal of the clamp capacitor 23 because the sampling transistor 22 is in the ON state. On the other hand, the clamp signal and the S / H capacitor input signal are Hi voltages, and the potential of the other terminal of the clamp capacitor 23 and the S / H capacitor 27 is set to VCL.
　タイミングｔ３では、１行目及び２行目の単位セル２について、転送トランジスタ１２がオン状態となるため、１行目及び２行目の単位セル２の画素１１に蓄積された信号電荷がＦＤ１３に転送され、１行目及び２行目の単位セル２それぞれのＦＤ電位Ｖｆｄ１、Ｖｆｄ２はこの信号電荷量に応じた電圧Ｖｆｄｓｉｇ１、Ｖｆｄｓｉｇ２だけ低下しＶｆｄｒｓｔ－Ｖｆｄｓｉｇ１、Ｖｆｄｒｓｔ－Ｖｆｄｓｉｇ２となる。 At the timing t3, the transfer transistors 12 are turned on for the unit cells 2 in the first and second rows, so that the signal charges accumulated in the pixels 11 of the unit cells 2 in the first and second rows are transferred to the FD 13. The FD potentials Vfd1 and Vfd2 of the unit cells 2 in the first row and the second row are reduced by the voltages Vfdsig1 and Vfdsig2 corresponding to the signal charge amounts to Vfdrst−Vfdsig1 and Vfdrst−Vfdsig2.
　タイミングｔ４では、１行目及び２行目の単位セル２について、転送トランジスタ１２がオフ状態で抵抗用トランジスタ６３がオン状態であり、Ｖｆｄｓｉｇ１とＶｆｄｓｉｇ２との平均をＶｆｄｓｉｇとしたとき、Ｖｆｄｒｓｔ－Ｖｆｄｓｉｇ－Ｖｔｈ－ＲＩ／２がリード電圧として垂直信号線１９に出力される。このリード電圧は１行目及び２行目の単位セル２の混合信号に相当する。この垂直信号線１９の電位変化によりクランプ容量２３の入力もＶｆｄｓｉｇだけ変化する。さらに、クランプトランジスタ２４はオフ状態なので、クランプ容量２３の他方の端子の電位、すなわちＳ／Ｈ容量２７の電位はＶｆｄｓｉｇ×Ｃｃｌ／（Ｃｃｌ＋Ｃｓｈ）だけ変化する。この電位変化は垂直信号線１９におけるリセット電圧とリード電圧との差分に対応した電圧、すなわち１行目及び２行目の単位セル２の平均化された画素信号（垂直画素混合信号）であり、タイミングｔ５でＳ／Ｈ容量入力信号がＬｏ電圧となりＳ／Ｈ容量２７に蓄積される。 At timing t4, for the unit cells 2 in the first and second rows, when the transfer transistor 12 is in the off state and the resistance transistor 63 is in the on state, and Vfdsig1 and Vfdsig2 are averaged to Vfdsig, Vfdrst−Vfdsig− Vth-RI / 2 is output to the vertical signal line 19 as a read voltage. This read voltage corresponds to the mixed signal of the unit cells 2 in the first and second rows. Due to the potential change of the vertical signal line 19, the input of the clamp capacitor 23 also changes by Vfdsig. Further, since the clamp transistor 24 is in the OFF state, the potential of the other terminal of the clamp capacitor 23, that is, the potential of the S / H capacitor 27 changes by Vfdsig × Ccl / (Ccl + Csh). This potential change is a voltage corresponding to the difference between the reset voltage and the read voltage in the vertical signal line 19, that is, an averaged pixel signal (vertical pixel mixed signal) of the unit cells 2 in the first and second rows. At timing t5, the S / H capacitor input signal becomes Lo voltage and is stored in the S / H capacitor 27.
　このとき、ＶＤＤＣＥＬがＬｏ電圧であり、かつ１行目及び２行目の単位セル２のリセットトランジスタ１４がオン状態のため、Ｖｆｄは低い電位にセットされ、読み出しが完了した行の単位セル２は非選択の状態に戻る。 At this time, since VDDCEL is the Lo voltage and the reset transistors 14 of the unit cells 2 in the first row and the second row are in the ON state, Vfd is set to a low potential, Return to unselected state.
　タイミングｔ１１では、Ｓ／Ｈ容量入力信号と列選択信号Ｈ［１］及びＨ［２］とがＨｉ電圧となり、１列目及び２列目の列選択トランジスタ２８がオン状態となる。これにより、１列目のＳ／Ｈ容量２７と２列目のＳ／Ｈ容量２７との平均信号が水平共通信号線２９に出力され、出力アンプ１０を介してチップ外部に出力される。 At timing t11, the S / H capacitor input signal and the column selection signals H [1] and H [2] are set to the Hi voltage, and the column selection transistors 28 in the first column and the second column are turned on. As a result, the average signal of the S / H capacitor 27 in the first column and the S / H capacitor 27 in the second column is output to the horizontal common signal line 29 and output to the outside of the chip via the output amplifier 10.
　タイミングｔ１２では、列選択信号Ｈ［３］及びＨ［４］がＨｉ電圧となり、３列目及び４列目の列選択トランジスタ２８がオン状態となる。これにより、３列目のＳ／Ｈ容量２７と４列目のＳ／Ｈ容量２７との平均信号が水平共通信号線２９に出力され、出力アンプ１０を介してチップ外部に出力される。 At timing t12, the column selection signals H [3] and H [4] become Hi voltage, and the column selection transistors 28 in the third and fourth columns are turned on. As a result, an average signal of the S / H capacitors 27 in the third column and the S / H capacitors 27 in the fourth column is output to the horizontal common signal line 29 and output to the outside of the chip via the output amplifier 10.
　同様に順次列選択信号Ｈ［５］、Ｈ［６］・・・をＨｉ電圧にすれば各列のＳ／Ｈ容量２７の画素信号の平均信号が順次チップ外部に出力される。 Similarly, if the column selection signals H [5], H [6],... Are sequentially set to the Hi voltage, the average signal of the pixel signals of the S / H capacitors 27 in each column is sequentially output outside the chip.
　以上より、垂直２画素水平２画素の画素信号が混合された信号が順次チップ外部に出力される。 From the above, a signal in which pixel signals of two vertical pixels and two horizontal pixels are mixed is sequentially output to the outside of the chip.
　図１５の動作を撮像領域１の単位セル２の行数／２だけ繰り返せば、撮像領域１全体の信号が読み出されることになる。 When the operation of FIG. 15 is repeated by the number of rows of the unit cell 2 in the imaging region 1/2, the signal of the entire imaging region 1 is read out.
　この画素混合モードでのＦＤレンジΔＶは第１及び第２の実施形態と同様に式（４）であらわされる。第１及び第２の実施形態の行選択トランジスタ１６に対応するものとして、つまり単位セル２を選択するトランジスタとして抵抗用トランジスタ６３が設けられ、抵抗用トランジスタ６３のオン抵抗ＲによりＦＤ１３の動作レンジを確保できることがわかる。 FD range ΔV in this pixel mixture mode is expressed by equation (4) as in the first and second embodiments. As a transistor corresponding to the row selection transistor 16 of the first and second embodiments, that is, as a transistor for selecting the unit cell 2, a resistance transistor 63 is provided, and the operating range of the FD 13 is increased by the on-resistance R of the resistance transistor 63. It can be seen that it can be secured.
　以上のように、本実施の形態の固体撮像装置によれば、動作電流の変動を抑えた信号の混合動作が実現できるだけでなく、第２の実施形態の固体撮像装置に比べ抵抗として機能するトランジスタのゲート端子に供給する信号線が不要のため、単位セル２の回路面積の縮小及び開口率拡大に適するという利点がある。 As described above, according to the solid-state imaging device of the present embodiment, not only can a signal mixing operation with suppressed fluctuations in operating current be realized, but also a transistor that functions as a resistor compared to the solid-state imaging device of the second embodiment. This eliminates the need for a signal line to be supplied to the gate terminal, and therefore has an advantage of being suitable for reducing the circuit area and the aperture ratio of the unit cell 2.
　（第４の実施形態）
　本発明の第４の実施形態による固体撮像装置の全体構成は図１に示す第１の実施形態の固体撮像装置の構成と同じである。 (Fourth embodiment)
The overall configuration of the solid-state imaging device according to the fourth embodiment of the present invention is the same as the configuration of the solid-state imaging device according to the first embodiment shown in FIG.
　図１６は、撮像領域１の詳細な構成を示す回路図である。 FIG. 16 is a circuit diagram showing a detailed configuration of the imaging region 1.
　この回路と図２に示す第１の実施形態の撮像領域１の回路との違いは増幅トランジスタ１５にシリアルに接続される抵抗素子６１が増幅トランジスタ１５のドレイン端子と画素電源線１７との間に挿入されていることである。このとき、画素混合モードでのＦＤレンジΔＶは式（５）で表される。 The difference between this circuit and the circuit of the imaging region 1 of the first embodiment shown in FIG. 2 is that a resistance element 61 serially connected to the amplification transistor 15 is between the drain terminal of the amplification transistor 15 and the pixel power line 17. It is inserted. At this time, the FD range ΔV in the pixel mixture mode is expressed by Expression (5).
　　ΔＶ＝ｂＲＩ＋（２－√２）×√（Ｉ／ａ）・・・・・（５） ΔV = bRI + (2-√2) × √ (I / a) (5)
　なお、ｂは１より小さい係数である。式（５）と、抵抗素子６１を増幅トランジスタ１５のソース端子側に配置したときのＦＤレンジを示す式（４）との違いは抵抗の効果（抵抗素子６１によるＦＤレンジの広がり）が係数ｂだけ低減していることである。これは増幅トランジスタ１５のドレイン端子側の電位変化は部分的にソースフォロア回路の出力に伝わることを反映している。一方、抵抗素子６１が増幅トランジスタ１５のドレイン端子側に配置されると、増幅トランジスタ１５が駆動する負荷が低減し、高速読み出しがしやすくなるという利点がある。 Note that b is a coefficient smaller than 1. The difference between Expression (5) and Expression (4) showing the FD range when the resistance element 61 is arranged on the source terminal side of the amplification transistor 15 is that the effect of resistance (expansion of the FD range by the resistance element 61) is a coefficient b. It is only reduced. This reflects that the potential change on the drain terminal side of the amplification transistor 15 is partially transmitted to the output of the source follower circuit. On the other hand, when the resistance element 61 is arranged on the drain terminal side of the amplification transistor 15, there is an advantage that the load driven by the amplification transistor 15 is reduced and high-speed reading is facilitated.
　（第５の実施形態）
　図１７は、本発明の第５の実施形態における固体撮像装置の全体構成を示す図である。 (Fifth embodiment)
FIG. 17 is a diagram illustrating an overall configuration of a solid-state imaging device according to the fifth embodiment of the present invention.
　この固体撮像装置は、撮像領域１、行選択回路３、画素電流源回路４、クランプ回路５、サンプルホールド（Ｓ／Ｈ）回路６、カラムＡＤＣ４４、デジタル混合器４５及び制御部９から構成される。 This solid-state imaging device includes an imaging region 1, a row selection circuit 3, a pixel current source circuit 4, a clamp circuit 5, a sample hold (S / H) circuit 6, a column ADC 44, a digital mixer 45, and a control unit 9. .
　カラムＡＤＣ４４は、画素１１の各列に対応して設けられた基本単位が行方向にアレイ状にならんで構成され、Ｓ／Ｈ回路６に保持された行単位のアナログ画素信号をデジタル信号に変換する。 The column ADC 44 is configured such that basic units provided corresponding to the respective columns of the pixels 11 are arranged in an array in the row direction, and converts the row-unit analog pixel signals held in the S / H circuit 6 into digital signals. To do.
　デジタル混合器４５は、画素１１の各列に対応して設けられた基本単位が行方向にアレイ状にならんで構成され、カラムＡＤＣ４４の出力データ（デジタル信号）の混合を行う。 The digital mixer 45 is configured such that basic units provided corresponding to each column of the pixels 11 are arranged in an array in the row direction, and mixes output data (digital signal) of the column ADC 44.
　単位セル２、画素電流源回路４、クランプ回路５、Ｓ／Ｈ回路６及び行選択回路３の詳細な構成は第１の実施の形態の固体撮像装置と同様である。 The detailed configuration of the unit cell 2, the pixel current source circuit 4, the clamp circuit 5, the S / H circuit 6, and the row selection circuit 3 is the same as that of the solid-state imaging device of the first embodiment.
　図１８は、カラムＡＤＣ４４の詳細な構成を示す図である。 FIG. 18 is a diagram showing a detailed configuration of the column ADC 44.
　カラムＡＤＣ４４は、複数の基本単位４４ａ及びカラムＡＤＣ入力端子４６と、ランプ波形生成回路４８と、カウンタ５０とから構成される。カラムＡＤＣ４４の基本単位４４ａは、コンパレータ４７及びラッチ４９から構成される。 The column ADC 44 includes a plurality of basic units 44 a and a column ADC input terminal 46, a ramp waveform generation circuit 48, and a counter 50. The basic unit 44 a of the column ADC 44 includes a comparator 47 and a latch 49.
　コンパレータ４７は、カラムＡＤＣ入力端子４６から入力されるＳ／Ｈ回路６からの画素信号の入力をうけ、入力された画素信号とランプ波形生成回路４８のランプ波形との比較を行い、ランプ波形が画素信号よりも低いときにＨｉ電圧を出力する。 The comparator 47 receives the pixel signal from the S / H circuit 6 input from the column ADC input terminal 46, compares the input pixel signal with the ramp waveform of the ramp waveform generation circuit 48, and the ramp waveform is When it is lower than the pixel signal, the Hi voltage is output.
　ラッチ４９は、カウンタ５０の出力（カウンタ値）をうけ、カウンタ５０からのラッチ信号がＨｉ電圧からＬｏ電圧に切り替わったときにカウンタ５０の出力を書き込む。 The latch 49 receives the output (counter value) of the counter 50, and writes the output of the counter 50 when the latch signal from the counter 50 is switched from the Hi voltage to the Lo voltage.
　カウンタ５０は、ランプ波形生成回路４８により生成されたランプ波形に同期してカウントアップを行う。 The counter 50 counts up in synchronization with the ramp waveform generated by the ramp waveform generation circuit 48.
　次に、カラムＡＤＣ４４のＡＤ変換動作について図１９のタイミングチャートを参照して説明する。 Next, the AD conversion operation of the column ADC 44 will be described with reference to the timing chart of FIG.
　まず、タイミングｔ０で画素信号がカラムＡＤＣ４４に入力され、ランプ波形は画素信号の最小値に、カウンタ５０は０に設定される。このとき、ランプ波形は画素信号より低いレベルなのでラッチ信号はＨｉ電圧である。 First, at timing t0, a pixel signal is input to the column ADC 44, the ramp waveform is set to the minimum value of the pixel signal, and the counter 50 is set to 0. At this time, since the ramp waveform is at a lower level than the pixel signal, the latch signal is at the Hi voltage.
　次に、タイミングｔ１で、ランプ波形のレベルは上昇し始める。上昇の傾きはタイミングｔ３で画素信号の最大値に達するように設定される。カウンタ５０もランプ波形の上昇に同期してカウントアップする。 Next, at the timing t1, the ramp waveform level starts to rise. The rising slope is set to reach the maximum value of the pixel signal at timing t3. The counter 50 also counts up in synchronization with the ramp waveform rise.
　次に、タイミングｔ２でランプ波形が画素信号より大きくなるので、ラッチ信号がＬｏ電圧に切り替わり、そのときのカウンタ値がラッチ４９に書き込まれる。先に述べたように、ランプ波形の上昇とカウントアップは同期しているので、ラッチ４９に書き込まれたデジタル値は画素信号に対応した値になっている。 Next, since the ramp waveform becomes larger than the pixel signal at the timing t2, the latch signal is switched to the Lo voltage, and the counter value at that time is written in the latch 49. As described above, since the ramp waveform rises and counts up, the digital value written in the latch 49 is a value corresponding to the pixel signal.
　以上のＡＤ変換動作は各列で並列に行われており、１行分のアナログ画素信号が並列にＡＤ変換され、デジタル信号として各列のラッチ４９に保持される。 The above AD conversion operations are performed in parallel in each column, and analog pixel signals for one row are AD converted in parallel and held in the latch 49 of each column as a digital signal.
　本実施形態の固体撮像装置は、第１の実施形態に係る固体撮像装置と同様に、全画素読み出しモードと画素混合モードとを備えている。次に、それぞれのモードでの信号読み出し動作を説明する。 The solid-state imaging device according to the present embodiment includes an all-pixel readout mode and a pixel mixture mode, similarly to the solid-state imaging device according to the first embodiment. Next, the signal reading operation in each mode will be described.
　まず、全画素読み出しモードでは、１行分の単位セル２が選択され、単位セル２から１行分の画素信号が読み出されＳ／Ｈ回路６に保持される。 First, in the all-pixel reading mode, the unit cells 2 for one row are selected, and pixel signals for one row are read from the unit cells 2 and held in the S / H circuit 6.
　次に、１行分の画素信号がＳ／Ｈ回路６からカラムＡＤＣ４４に読み出され、カラムＡＤＣ４４でデジタル変換される。 Next, the pixel signals for one row are read from the S / H circuit 6 to the column ADC 44 and are digitally converted by the column ADC 44.
　最後に、出力部（図外）を介してカラムＡＤＣ４４からのデジタル信号が順次チップ外部に出力される。 Finally, digital signals from the column ADC 44 are sequentially output to the outside of the chip via the output unit (not shown).
　以上の動作を撮像領域１の単位セル２の行数だけ繰り返せば撮像領域１全体の信号が出力される。 If the above operation is repeated for the number of rows of the unit cell 2 in the imaging area 1, a signal of the entire imaging area 1 is output.
　一方、画素混合モードでも、まず２行の単位セル２が同時に選択され、単位セル２から２行分の画素信号が読み出され、垂直信号線１９で混合された後、Ｓ／Ｈ回路６に保持される。 On the other hand, also in the pixel mixing mode, first, two rows of unit cells 2 are simultaneously selected, and pixel signals for two rows are read from the unit cells 2 and mixed by the vertical signal line 19 before being sent to the S / H circuit 6. Retained.
　次に、混合された画素信号がＳ／Ｈ回路６からカラムＡＤＣ４４に読み出され、カラムＡＤＣ４４でデジタル変換される。 Next, the mixed pixel signal is read from the S / H circuit 6 to the column ADC 44 and is digitally converted by the column ADC 44.
　次に、デジタル信号が複数列のカラムＡＤＣ４４の基本単位４４ａから同時にデジタル混合器４５に読み出され、デジタル混合器４５で混合される。 Next, digital signals are simultaneously read out from the basic units 44 a of the column ADCs 44 in a plurality of columns to the digital mixer 45 and mixed by the digital mixer 45.
　最後に、出力部（図外）を介して混合されたデジタル信号が順次チップ外部に出力される。 Finally, the mixed digital signals are sequentially output to the outside of the chip via the output unit (not shown).
　以上の動作を撮像領域１の単位セル２の行数／２だけ繰り返せば撮像領域１全体の信号が出力される。 If the above operation is repeated by the number of rows of the unit cell 2 in the imaging region 1/2, the signal of the entire imaging region 1 is output.
　以上のように、本実施形態に係る固体撮像装置によれば、動作電流の変動を抑えた高画質化に適した画素混合機能を有するデジタル出力の固体撮像装置を実現できる。第１の実施形態から第４の実施形態に係る固体撮像装置では、図４に示すＭＵＸ７、出力アンプ１０及び後段でＡＤ変換を行うアナログフロントエンドの部分は高いデータ転送レートのために広帯域の回路になる。このため、外部からのノイズが混入しやすいという課題がある。これに対し、本実施形態に係る固体撮像装置では列回路で信号のデジタル化を行うためにこの外乱ノイズへの耐性が大幅に向上するという利点がある。これは固体撮像装置を用いたカメラ基板の作成が容易になることにもつながる。 As described above, according to the solid-state imaging device according to the present embodiment, a digital output solid-state imaging device having a pixel mixing function suitable for high image quality while suppressing fluctuations in operating current can be realized. In the solid-state imaging device according to the first to fourth embodiments, the MUX 7, the output amplifier 10, and the analog front end portion that performs AD conversion in the subsequent stage are wide-band circuits for a high data transfer rate. become. For this reason, there exists a subject that the noise from the outside tends to mix. On the other hand, the solid-state imaging device according to the present embodiment has an advantage that the resistance to the disturbance noise is greatly improved since the signal is digitized by the column circuit. This also leads to easy creation of a camera substrate using a solid-state imaging device.
　以上、本発明の固体撮像装置について、実施の形態に基づいて説明したが、本発明は、この実施の形態に限定されるものではない。本発明の要旨を逸脱しない範囲内で当業者が思いつく各種変形を施したものも本発明の範囲内に含まれる。また、発明の趣旨を逸脱しない範囲で、複数の実施の形態における各構成要素を任意に組み合わせてもよい。 As mentioned above, although the solid-state imaging device of the present invention has been described based on the embodiment, the present invention is not limited to this embodiment. The present invention includes various modifications made by those skilled in the art without departing from the scope of the present invention. Moreover, you may combine each component in several embodiment arbitrarily in the range which does not deviate from the meaning of invention.
　例えば、上記実施形態の固体撮像装置は、外部からの光を固体撮像装置に集光するレンズ、固体撮像装置からの信号を処理する画像信号処理装置、及び画像信号処理装置で処理された信号を記憶する画像記憶装置を備え、スチル画像撮影機能とスチル画像よりも低解像度で高フレームレートな動画撮影機能を有する撮像装置に用いることができる。 For example, the solid-state imaging device of the above embodiment includes a lens that collects external light on the solid-state imaging device, an image signal processing device that processes a signal from the solid-state imaging device, and a signal processed by the image signal processing device. It can be used in an imaging apparatus that includes an image storage device for storing and has a still image shooting function and a moving image shooting function with a lower resolution and a higher frame rate than a still image.
　また、上記実施形態の固体撮像装置では、固体撮像装置を構成する各トランジスタは、ｎチャネル型のＭＯＳトランジスタであるとしたが、ｐチャネル型のＭＯＳトランジスタであってもよい。 In the solid-state imaging device of the above embodiment, each transistor constituting the solid-state imaging device is an n-channel type MOS transistor, but may be a p-channel type MOS transistor.
　本発明は、固体撮像装置及び撮像装置として有用であり、特にデジタル一眼レフカメラ及び高級コンパクトカメラなど高画質及び高機能が求められる撮像機器向けイメージセンサとして有用である。 The present invention is useful as a solid-state imaging device and an imaging device, and particularly useful as an image sensor for an imaging device that requires high image quality and high functionality such as a digital single-lens reflex camera and a high-end compact camera.
　　１、２０１　　撮像領域
　　２、２０２　　単位セル
　　３　　行選択回路
　　４　　画素電流源回路
　　４ａ、５ａ、６ａ、７ａ、４４ａ　　基本単位
　　５　　クランプ回路
　　６　　Ｓ／Ｈ回路
　　７　　マルチプレクサ
　　８　　列選択回路
　　９　　制御部
　　１０　　出力アンプ
　　１１　　画素
　　１２　　転送トランジスタ
　　１３　　フローティングディフュージョン
　　１４　　リセットトランジスタ
　　１５、２１５　　増幅トランジスタ
　　１６　　行選択トランジスタ
　　１７　　画素電源線
　　１９、１０１、１０２　　垂直信号線
　　２０　　電流源トランジスタ
　　２１　　電流源バイアス電圧
　　２２　　サンプリングトランジスタ
　　２３　　クランプ容量
　　２４　　クランプトランジスタ
　　２５　　クランプ電圧入力端子
　　２６　　Ｓ／Ｈ容量入力トランジスタ
　　２７　　Ｓ／Ｈ容量
　　２８　　列選択トランジスタ
　　２９　　水平共通信号線
　　３１　　アドレスデコーダ
　　３２　　行選択用論理回路
　　３３　　フリップフロップ
　　３４　　ＡＮＤゲート
　　４４　　カラムＡＤＣ
　　４５　　デジタル混合器
　　４６　　カラムＡＤＣ入力端子
　　４７　　コンパレータ
　　４８　　ランプ波形生成回路
　　４９　　ラッチ
　　５０　　カウンタ
　　６１　　抵抗素子
　　６３　　抵抗用トランジスタ
　　７３　　画素電源生成回路
　　１００　　画素読み出し回路
　　１０３　　電流源
　　１０４　　グランド接続スイッチ
　　１０５　　負荷トランジスタ
　　１０６　　電源接続スイッチ
　　１０７、１０８　　画素出力線
　　２１１　　フォトダイオード
　　２１４　　リセットスイッチ
　　２１６　　行選択スイッチ
  DESCRIPTION OF SYMBOLS 1,201 Imaging region 2,202 Unit cell 3 Row selection circuit 4 Pixel current source circuit 4a, 5a, 6a, 7a, 44a Basic unit 5 Clamp circuit 6 S / H circuit 7 Multiplexer 8 Column selection circuit 9 Control part 10 Output amplifier DESCRIPTION OF SYMBOLS 11 Pixel 12 Transfer transistor 13 Floating diffusion 14 Reset transistor 15, 215 Amplification transistor 16 Row selection transistor 17 Pixel power supply line 19, 101, 102 Vertical signal line 20 Current source transistor 21 Current source bias voltage 22 Sampling transistor 23 Clamp capacity 24 Clamp transistor 25 Clamp voltage input terminal 26 S / H capacity input transistor 27 S / H capacity 28 Column selection transistor 29 Horizontal common signal line 31 Address 32 decoder logic circuit for row selection 33 flip-flop 34 AND gate 44 column ADC
45 Digital mixer 46 Column ADC input terminal 47 Comparator 48 Ramp waveform generation circuit 49 Latch 50 Counter 61 Resistive element 63 Resistor transistor 73 Pixel power supply circuit 100 Pixel readout circuit 103 Current source 104 Ground connection switch 105 Load transistor 106 Power connection switch 107, 108 Pixel output line 211 Photodiode 214 Reset switch 216 Row selection switch

Claims (14)

  1. 　受光量に応じた信号を生成する画素と、前記画素の信号を蓄積するためのフローティングディフュージョンと、ソースが前記フローティングディフュージョンと接続されたリセットトランジスタと、ゲートが前記フローティングディフュージョンと接続された増幅トランジスタとを有し、２次元状に配列された複数の単位セルと、
    　前記画素の列に対応して設けられ、対応する列の画素を含む前記単位セルの前記増幅トランジスタのソースと接続され、対応する列の画素の信号を伝達する垂直信号線と、
    　前記垂直信号線に前記画素の信号が出力されるときに前記垂直信号線に電流を供給する画素電流源と、
    　前記リセットトランジスタのドレインと前記増幅トランジスタのドレインとに接続された画素電源線と、
    　前記増幅トランジスタのソースと前記垂直信号線との間、又は前記増幅トランジスタのドレインと前記画素電源線との間に挿入され、前記垂直信号線に前記画素の信号が出力されるときに抵抗として機能する素子とを備える
    　固体撮像装置。     A pixel that generates a signal corresponding to the amount of received light; a floating diffusion for storing the signal of the pixel; a reset transistor having a source connected to the floating diffusion; and an amplifying transistor having a gate connected to the floating diffusion; A plurality of unit cells arranged two-dimensionally,
    A vertical signal line provided corresponding to the column of pixels, connected to the source of the amplification transistor of the unit cell including the pixel of the corresponding column, and transmitting a signal of the pixel of the corresponding column;
    A pixel current source for supplying a current to the vertical signal line when a signal of the pixel is output to the vertical signal line;
    A pixel power line connected to the drain of the reset transistor and the drain of the amplification transistor;
    Inserted between the source of the amplification transistor and the vertical signal line, or between the drain of the amplification transistor and the pixel power supply line, and functions as a resistor when the pixel signal is output to the vertical signal line A solid-state imaging device.
  2. 　前記画素は、埋め込み構造のフォトダイオードであり、
    　前記単位セルは、さらに、前記フォトダイオードと前記フローティングディフュージョンとの間に挿入された転送トランジスタを有する
    　請求項１記載の固体撮像装置。     The pixel is an embedded photodiode.
    The solid-state imaging device according to claim 1, wherein the unit cell further includes a transfer transistor inserted between the photodiode and the floating diffusion.
  3. 　前記抵抗として機能する素子は、抵抗素子である
    　請求項１又は２に記載の固体撮像装置。     The solid-state imaging device according to claim 1, wherein the element functioning as the resistor is a resistance element.
  4. 　前記単位セルは、さらに、前記増幅トランジスタのソースと前記垂直信号線との間に、前記抵抗素子と直列に挿入された選択トランジスタを有する
    　請求項３記載の固体撮像装置。     The solid-state imaging device according to claim 3, wherein the unit cell further includes a selection transistor inserted in series with the resistance element between a source of the amplification transistor and the vertical signal line.
  5. 　前記抵抗として機能する素子はトランジスタである
    　請求項１又は２に記載の固体撮像装置。     The solid-state imaging device according to claim 1, wherein the element functioning as the resistor is a transistor.
  6. 　前記抵抗として機能するトランジスタのオン抵抗は前記リセットトランジスタ又は前記増幅トランジスタよりも大きい
    　請求項５に記載の固体撮像装置。     The solid-state imaging device according to claim 5, wherein an on-resistance of the transistor functioning as the resistor is larger than that of the reset transistor or the amplification transistor.
  7. 　前記抵抗として機能する素子としてのトランジスタのゲートは、前記画素電源線と接続されている
    　請求項５記載の固体撮像装置。     The solid-state imaging device according to claim 5, wherein a gate of a transistor as an element functioning as the resistor is connected to the pixel power supply line.
  8. 　前記固体撮像装置は、さらに、同一行の複数の前記単位セルにおける前記抵抗として機能する素子としてのトランジスタのゲートに共通の制御信号を供給する制御線を備える
    　請求項５記載の固体撮像装置。     The solid-state imaging device according to claim 5, further comprising a control line that supplies a common control signal to a gate of a transistor as an element functioning as the resistor in the plurality of unit cells in the same row.
  9. 　前記リセットトランジスタ及び前記抵抗として機能する素子としてのトランジスタのゲートには、Ｈｉ電圧及び前記Ｈｉ電圧より低いＬｏ電圧のいずれかが供給され、
    　前記抵抗として機能する素子としてのトランジスタのゲートに供給されるＨｉ電圧は、前記リセットトランジスタのゲートに供給されるＨｉ電圧よりも低い
    　請求項８記載の固体撮像装置。     Either the Hi voltage or the Lo voltage lower than the Hi voltage is supplied to the gate of the reset transistor and the transistor serving as the resistor.
    The solid-state imaging device according to claim 8, wherein a Hi voltage supplied to a gate of a transistor as an element functioning as the resistor is lower than a Hi voltage supplied to a gate of the reset transistor.
  10. 　前記固体撮像装置は、さらに、前記抵抗として機能するトランジスタのゲートにハイレベル電圧を供給する可変電源を備える
    　請求項８記載の固体撮像装置。     The solid-state imaging device according to claim 8, further comprising a variable power supply that supplies a high level voltage to a gate of the transistor that functions as the resistor.
  11. 　前記抵抗として機能するトランジスタのゲート幅は、前記増幅トランジスタのゲート幅より小さい
    　請求項５～１０のいずれか１項に記載の固体撮像装置。     The solid-state imaging device according to any one of claims 5 to 10, wherein a gate width of the transistor functioning as the resistor is smaller than a gate width of the amplification transistor.
  12. 　前記固体撮像装置は、さらに、前記垂直信号線に信号を出力させる画素を行単位で選択する行選択回路を備え、
    　前記抵抗として機能するトランジスタのゲート長は、前記行選択回路を構成するトランジスタの最小ゲート長より大きい
    　請求項５～１０のいずれか１項に記載の固体撮像装置。     The solid-state imaging device further includes a row selection circuit that selects pixels for outputting signals to the vertical signal lines in units of rows,
    The solid-state imaging device according to any one of claims 5 to 10, wherein a gate length of the transistor functioning as the resistor is larger than a minimum gate length of the transistors constituting the row selection circuit.
  13. 　前記抵抗として機能するトランジスタのしきい値電圧は、前記増幅トランジスタのしきい値電圧より大きい
    　請求項５～１０のいずれか１項に記載の固体撮像装置。     The solid-state imaging device according to any one of claims 5 to 10, wherein a threshold voltage of the transistor functioning as the resistor is larger than a threshold voltage of the amplification transistor.
  14. 　請求項１～１３のいずれか１項に記載の固体撮像装置、レンズ、画像信号処理装置及び画像記憶装置を備え、
    　スチル画像撮影機能と前記スチル画像よりも低解像度で高フレームレートな動画撮影機能を有する
    　撮像装置。     A solid-state imaging device, a lens, an image signal processing device, and an image storage device according to any one of claims 1 to 13,
    An imaging apparatus having a still image shooting function and a moving image shooting function having a lower resolution and a higher frame rate than the still image.
PCT/JP2010/006974 2009-12-09 2010-11-30 Solid-state imaging device and imaging device WO2011070745A1 (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005218139A (en) * 2005-04-04 2005-08-11 Canon Inc Solid-state image pickup device, solid-state image pickup system using it, and signal transferring device
JP2008271159A (en) * 2007-04-19 2008-11-06 Matsushita Electric Ind Co Ltd Solid-state imaging apparatus
JP2009010787A (en) * 2007-06-28 2009-01-15 Panasonic Corp Solid-state imaging device and its driving method, imaging device
JP2010136110A (en) * 2008-12-04 2010-06-17 Canon Inc Solid-state imaging device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005218139A (en) * 2005-04-04 2005-08-11 Canon Inc Solid-state image pickup device, solid-state image pickup system using it, and signal transferring device
JP2008271159A (en) * 2007-04-19 2008-11-06 Matsushita Electric Ind Co Ltd Solid-state imaging apparatus
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