WO2011065687A2 - Crystallized solar cell using microcrystalline semiconductor layer and production method for same - Google Patents

Crystallized solar cell using microcrystalline semiconductor layer and production method for same Download PDF

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WO2011065687A2
WO2011065687A2 PCT/KR2010/007868 KR2010007868W WO2011065687A2 WO 2011065687 A2 WO2011065687 A2 WO 2011065687A2 KR 2010007868 W KR2010007868 W KR 2010007868W WO 2011065687 A2 WO2011065687 A2 WO 2011065687A2
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semiconductor layer
solar cell
layer
silicon layer
amorphous silicon
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PCT/KR2010/007868
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French (fr)
Korean (ko)
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WO2011065687A3 (en
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이시우
이유진
김동제
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주식회사 티지솔라
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Priority claimed from KR1020090113758A external-priority patent/KR101084650B1/en
Priority claimed from KR1020090116094A external-priority patent/KR101084652B1/en
Application filed by 주식회사 티지솔라 filed Critical 주식회사 티지솔라
Publication of WO2011065687A2 publication Critical patent/WO2011065687A2/en
Publication of WO2011065687A3 publication Critical patent/WO2011065687A3/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/036—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes
    • H01L31/0368—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including polycrystalline semiconductors
    • H01L31/03682—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including polycrystalline semiconductors including only elements of Group IV of the Periodic Table
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/036—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/036—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes
    • H01L31/0368—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including polycrystalline semiconductors
    • H01L31/03682—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including polycrystalline semiconductors including only elements of Group IV of the Periodic Table
    • H01L31/03685—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including polycrystalline semiconductors including only elements of Group IV of the Periodic Table including microcrystalline silicon, uc-Si
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/075—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PIN type, e.g. amorphous silicon PIN solar cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/545—Microcrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/546—Polycrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/548—Amorphous silicon PV cells

Definitions

  • the present invention relates to a solar cell crystallized using a microcrystalline semiconductor layer and a method of manufacturing the same. More specifically, the present invention relates to a polycrystalline solar cell capable of crystallizing an amorphous semiconductor layer at low temperature (for example, 600 degrees or less) using a microcrystalline semiconductor layer, and a method of manufacturing the same.
  • a solar cell using amorphous silicon has a very low diffusion length of a carrier compared to monocrystalline silicon or polycrystalline silicon (p-si) due to the characteristics of the amorphous silicon material itself. Therefore, when the amorphous silicon (a-Si) solar cell is manufactured with a pn junction structure, the collection efficiency of electron-hole pairs generated by light is very low, and deterioration occurs after prolonged exposure to light. As time goes by, the photoelectric conversion efficiency is lowered.
  • an amorphous silicon pin structure formed between p-type and n-type having a high impurity doping concentration by using an intrinsic semiconductor layer containing no impurity as a light absorbing layer, and heat treatment at high temperature For example, a solar cell having a polycrystalline silicon pin structure which crystallizes to polycrystalline silicon (p-si) at 600 degrees or more has been proposed.
  • a depletion region is formed at the junction between the i-layer, which is a light absorbing layer, and the p-layer and the n-layer, which have a high impurity doping concentration, to generate an electric field therein. Therefore, the electron-hole pair generated by the incident light in the i layer is a drift in which electrons (-) move to the n-type silicon layer and holes (+) move to the p-type silicon layer according to the internal electric field, not diffusion. Current can flow.
  • the heat treatment temperature is required to be higher than 600 degrees at the time of crystallization of the amorphous silicon, the substrate is deformed (for example, the warpage of the substrate) during the heat treatment process and impurities are formed in the silicon layer (especially, optical Diffused into the absorption layer), thereby lowering the photoelectric conversion efficiency.
  • ⁇ c-Si microcrystalline Si
  • PECVD Plasma Enhanced Chemical Vapor Deposition
  • the present invention has been made to solve the above problems of the prior art, and provides a solar cell and a method of manufacturing the same that can easily crystallize the amorphous semiconductor even at low temperatures by using the characteristics of the microcrystalline semiconductor. have.
  • Another object of the present invention is to provide a solar cell and a method of manufacturing the same, which may have grain boundaries grown in the same direction as the direction of movement of electrons and holes generated in the light absorption layer.
  • Another object of the present invention is to provide a solar cell and a method of manufacturing the same, which can improve the photoelectric conversion efficiency by efficiently controlling the crystallization of the amorphous semiconductor layer.
  • Another object of the present invention is to provide a solar cell and a method of manufacturing the same, which can crystallize only the upper optoelectronic device by using characteristics of a microcrystalline semiconductor among multiple photoelectric devices.
  • the photoelectric conversion efficiency of the solar cell can be improved by forming grain boundaries in the same direction as the direction of movement of electrons and holes generated in the light absorbing layer to improve the mobility of electrons and holes.
  • only the upper photoelectric device of the multi-junction photoelectric device can be crystallized to polycrystalline silicon having excellent characteristics even at low temperature by using fine crystalline silicon.
  • FIG. 1 to 5 are views illustrating a manufacturing process of a solar cell crystallized using the microcrystalline semiconductor layer according to the first embodiment of the present invention.
  • FIGS. 6 to 10 are views illustrating a manufacturing process of a stacked solar cell crystallized using the microcrystalline semiconductor layer according to the second embodiment of the present invention.
  • 300, 300P Optoelectronic device (lower optoelectronic device)
  • first amorphous silicon layer (lower first amorphous silicon layer)
  • third amorphous silicon layer (lower third amorphous silicon layer)
  • the object of the present invention is a substrate; A lower electrode formed on the substrate; An optoelectronic device formed on the lower electrode and including a polycrystalline semiconductor layer having a grain boundary grown in the same direction as the movement direction of electrons or holes; And it is achieved by a solar cell comprising an upper electrode formed on the optoelectronic device.
  • the above object of the present invention (a) forming a microcrystalline semiconductor layer between the stacked amorphous semiconductor layer; And (b) forming a photovoltaic device comprising a polycrystalline semiconductor layer formed by crystallizing at least a portion of the microcrystalline semiconductor layer and the amorphous semiconductor layer by performing a heat treatment process. It is also achieved by the method.
  • the step (a) (a1) forming a first amorphous semiconductor layer on the lower electrode on the substrate; (a2) forming a lower second amorphous semiconductor layer on the first amorphous semiconductor layer; (a3) forming the microcrystalline semiconductor layer on the lower second amorphous semiconductor layer; (a4) forming an upper second amorphous semiconductor layer on the microcrystalline semiconductor layer; And (a5) forming a third amorphous semiconductor layer on the upper second amorphous semiconductor layer.
  • silicon (Si) most commonly used as a material of a semiconductor layer is described as an example, but the present invention is not limited thereto, and known materials having semiconductor characteristics may be used without limitation.
  • FIG. 1 to 5 are views illustrating a manufacturing process of a solar cell crystallized using the microcrystalline semiconductor layer according to the first embodiment of the present invention.
  • a substrate 100 may be provided.
  • the material of the substrate 100 may be a transparent glass substrate, but is not necessarily limited thereto.
  • the substrate 100 may be formed of a transparent material such as glass or plastic, silicon, or metal [eg, SUS (Stainless) according to a direction in which a solar cell receives light. Steel)] can be used for all opaque materials.
  • roughness may be formed by performing a texturing process on the surface of the substrate 100.
  • the texturing is to prevent the phenomenon that the characteristic is degraded by the optical reflection of light incident on the substrate surface of the solar cell is reflected. That is, forming a roughness pattern on the substrate surface by making the surface of the substrate rough.
  • the surface of the substrate is roughened by texturing, the light reflected once from the surface may be reflected back toward the solar cell, thereby reducing the loss of light and increasing the amount of light trapping, thereby improving the photoelectric conversion efficiency of the solar cell. You can.
  • the texturing process may be performed by using a sand blasting method, which includes both dry blasting for spraying etching particles with compressed air and wet blasting for spraying etching particles with liquid.
  • Etching particles used in sand blasting can be used without limitation, such as sand, small metals, particles that can form irregularities on the substrate by physical impact.
  • the texturing process may be omitted if necessary.
  • an antireflection layer (not shown) may be formed on the substrate 100.
  • the anti-reflection layer may serve to prevent a phenomenon in which solar light incident through the substrate 100 is not absorbed by the silicon layer and is directly reflected to the outside, thereby lowering the efficiency of the solar cell.
  • the material of the anti-reflection layer may be silicon oxide (SiO x ) or silicon nitride (SiN x ), which are transparent insulating layers, but are not limited thereto.
  • the method of forming the reflective ring layer may include chemical vapor deposition (CVD), such as Low Pressure Chemical Vapor Deposition (LPCVD) and Plasma Enhanced Chemical Vapor Deposition (PECVD). Can be.
  • CVD chemical vapor deposition
  • LPCVD Low Pressure Chemical Vapor Deposition
  • PECVD Plasma Enhanced Chemical Vapor Deposition
  • a lower electrode 200 of a conductive material may be formed on the substrate 100.
  • the material of the lower electrode 200 may use a transparent conductive oxide (TCO) having low contact resistance and transparent properties.
  • TCO transparent conductive oxide
  • the transparent electrode TCO may be any one of AZO (ZnO: Al), ITO (Indium-Tin-Oxide), GZO (ZnO: Ga), BZO (ZnO: B), and FTO (SnO 2 : F). have.
  • the lower electrode 200 may be formed using physical vapor deposition (PVD), LPCVD, PECVD, metal organic chemistry such as thermal evaporation, e-beam evaporation, and sputtering.
  • PVD physical vapor deposition
  • PECVD PECVD
  • metal organic chemistry such as thermal evaporation, e-beam evaporation, and sputtering.
  • MOCVD Metal Organic Chemical Vapor Deposition
  • p-type, i-type, n-type (particularly, p + type, i-type, n + type), n-type, i-type, p-type (particularly, n + type, type i, p +), p, n, n (especially p +, p-, n +) or n, n, p (especially n +, n-, p +)
  • a silicon layer having a conductivity type of can be formed in this order.
  • n + is higher doped than n-. If there is no indication of + or-, there is no particular restriction on the doping concentration.
  • An i-type silicon layer located between p-type and n-type functions as a light absorbing layer.
  • p-type, i-type, and n-type silicon layers 310, 320, and 330 are sequentially formed on the lower electrode 200.
  • the p-type first amorphous silicon layer 310 is formed on the lower electrode 200, and then the i-type second amorphous silicon layer 320 is formed on the first amorphous silicon layer 310.
  • an n-type third amorphous silicon layer 330 may be formed on the second amorphous silicon layer 320 to form one optoelectronic device 300.
  • a fine crystalline silicon layer 322 is further formed between the 2-1 amorphous silicon layer 321 and the 2-2 amorphous silicon layer 323.
  • the 2-1 amorphous silicon layer 321 is formed on the first amorphous silicon layer 310, and then the fine crystalline silicon layer 322 is formed on the 2-1 amorphous silicon layer 321.
  • the second-2 amorphous silicon layer 323 may be formed on the microcrystalline silicon layer 322.
  • the microcrystalline silicon layer 322 may function to induce crystallization of adjacent amorphous silicon layers 321 and 323.
  • the fine crystalline silicon layer 322 is not limited to the above-described arrangement, and between the first amorphous silicon layer 310 and the second amorphous silicon layer 320, or the second amorphous silicon layer 320 and the first It may be formed between the three amorphous silicon layer 330.
  • the first 310, the second 320 (321, 323) and the third amorphous silicon layer 330 and the microcrystalline silicon layer 322 may be preferably formed using PECVD.
  • SiH 4 (or Si 2 H 6 ) which is a source gas, is formed. It can be formed by adjusting the mixing ratio of H 2 as an auxiliary gas. That is, the ratio of H 2 to SiH 4 (or Si 2 H 6 ) may be decreased (H 2 may be 0) to form the 2-1 and 2-2 amorphous silicon layers 321 and 323.
  • the ratio of H 2 to SiH 4 may be increased to form the microcrystalline silicon layer 322.
  • the technique for controlling the crystallinity of the silicon layer formed by adjusting the mixing ratio of the source gas and the auxiliary gas in PECVD is a known method, detailed description thereof will be omitted.
  • the first, second and third amorphous silicon layer (310, 320, 330) when forming the first, second and third amorphous silicon layer (310, 320, 330) by PECVD, it is preferable to use an in situ method that proceeds sequentially in a single process in a single chamber.
  • the first, second and third amorphous silicon layers 310, 320, and 330, which constitute the optoelectronic device 300 are formed without being exposed to the external environment, the reliability of the solar cell is improved.
  • the manufacturing process is simplified and the manufacturing time is shortened to increase the productivity of the solar cell.
  • the microcrystalline silicon layer 322 may be crystallized into the polycrystalline silicon layer 322P by performing a heat treatment process at a predetermined temperature.
  • the microcrystalline silicon has a microstructure in the middle of the amorphous silicon and polycrystalline silicon.
  • fine crystalline silicon can be crystallized into polycrystalline silicon at a lower temperature than amorphous silicon.
  • the temperature for crystallizing amorphous silicon is 600 ° C. or more
  • the fine crystalline silicon may be crystallized to polycrystalline silicon even at a low temperature of 600 ° C. or less (eg, 550 ° C.).
  • the 2-1 and 2-2 amorphous silicon layers 321 and 323 and the microcrystalline silicon layer 322 may be formed.
  • the 2-1 and 2-2 amorphous silicon layers 321 and 323 may also be sequentially crystallized around the interface to become the 2-1 and 2-2 polycrystalline silicon layers 321P and 323P.
  • the second amorphous silicon layer 320 is grown in the direction perpendicular to the interface.
  • the process may be the first polycrystalline silicon layer 310P and the third polycrystalline silicon layer 330P. That is, the first, second, and third amorphous silicon layers 310, 320, and 330 may be formed into the first, second, and third polycrystalline silicon layers 310P, even by a low temperature heat treatment of 600 ° C. or lower, using fine crystalline silicon as a seed. 320P, 330P) layer can be crystallized. Therefore, deformation of the substrate 100 due to high temperature heat treatment (for example, warpage of the substrate) can be prevented.
  • high temperature heat treatment for example, warpage of the substrate
  • the first amorphous silicon layer 310 and the third amorphous silicon layer 330 are separately provided.
  • the metal layer (not shown) may be formed so that the first amorphous silicon layer 310 and the third amorphous silicon layer 330 may be crystallized by a metal induced crystallization (MIC) method.
  • MIC metal induced crystallization
  • the component of the metal layer may include any one of Ni, Al, Ti, Ag, Au, Co, Sb, Pd, Cu, or a combination of two or more thereof.
  • the metal layer may be formed by a low pressure chemical vapor deposition method, a plasma chemical vapor deposition method, an atomic unit layer deposition method, a sputtering method, or the like. Since the method of crystallizing amorphous silicon by the metal-induced crystallization method is a known technique, a detailed description thereof will be omitted herein.
  • the upper electrode 500 of the conductive material may be formed on the photoelectric device 300P including the first, second, and third polycrystalline silicon layers 310P, 320P, and 330P. have.
  • the material of the upper electrode 500 may be a transparent electrode (TCO), or may include copper (Cu), aluminum (Al), titanium (Ti), silver (Ag), and alloys thereof, which are conventional conductive materials. It is not limited to this.
  • the method of forming the upper electrode 500 may include a physical vapor deposition method such as sputtering and a chemical vapor deposition method such as LPCVD, PECVD, and MOCVD.
  • the polycrystalline silicon solar cell 10 having excellent photoelectric conversion efficiency, reliability, and productivity using the microcrystalline silicon layer may be implemented.
  • a tandem solar cell refers to a structure in which photovoltaic devices are stacked in a multi junction, and in the following description, a tandem solar cell stacked in a double junction is described. Although the description will be made in the center, the present invention is not limited thereto, and the concept may include a solar cell having a laminated structure of triple junction or more.
  • the present embodiment is different from the first embodiment in that it is a double-junction stacked solar cell, and the description of this embodiment will be omitted.
  • FIGS. 6 to 10 are views illustrating a manufacturing process of a stacked solar cell crystallized using the microcrystalline semiconductor layer according to the second embodiment of the present invention.
  • a substrate 100 is provided, and a lower electrode 200 is formed on the substrate 100.
  • p-type, i-type, and n-type silicon layers 310, 320, and 330 are sequentially formed on the lower electrode 200.
  • the p-type lower first amorphous silicon layer 310 is formed on the lower electrode 200
  • the i-type lower second amorphous silicon layer is formed on the lower first amorphous silicon layer 310.
  • a lower photovoltaic device in which the lower silicon layers 310, 320, and 330 are stacked by forming an n-type lower third amorphous silicon layer 330 on the lower second amorphous silicon layer 320. 300 can be configured.
  • p-type, i-type, and n-type silicon layers 410, 420, and 430 are sequentially formed on the lower photoelectric device 300.
  • the p-type upper first amorphous silicon layer 410 is formed on the lower photoelectric device 300, and then the i-type upper second amorphous silicon is formed on the upper first amorphous silicon layer 410.
  • the device 400 may be configured.
  • a fine crystalline silicon layer 422 is further added between the upper 2-1 amorphous silicon layer 421 and the upper 2-2 amorphous silicon layer 423.
  • the upper 2-1 amorphous silicon layer 421 is formed on the lower third amorphous silicon layer 330, and then the fine crystalline silicon layer is formed on the upper 2-1 amorphous silicon layer 421.
  • 422 may be formed, and then an upper second-second amorphous silicon layer 423 may be formed on the microcrystalline silicon layer 422.
  • the microcrystalline silicon layer 422 may function to induce crystallization of adjacent amorphous silicon layers 421 and 423.
  • the microcrystalline silicon layer 422 is not limited to the above-described arrangement, and is disposed between the upper first amorphous silicon layer 410 and the upper second amorphous silicon layer 420 or the upper second amorphous silicon layer 420. ) And the upper third amorphous silicon layer 430 may be formed.
  • the microcrystalline silicon layer 422 may be crystallized into the polycrystalline silicon layer 422P by performing a heat treatment process at a predetermined temperature.
  • the microcrystalline silicon may be crystallized into polycrystalline silicon at a low temperature (for example, 550 ° C) of 600 ° C. or less as in the first embodiment, and in this process, the microcrystalline silicon may be seeded for crystallization of amorphous silicon. seed) to act on the interface between the upper 2-1 and upper 2-2 amorphous silicon layers 421 and 423 and the microcrystalline silicon layer 422, and the upper 2-1 and upper 2-2 amorphous layers.
  • the silicon layers 421 and 423 may also be sequentially crystallized to become the 2-1 and 2-2 polycrystalline silicon layers 421P and 423P.
  • the upper first amorphous silicon layer 410 and the upper third amorphous silicon layer 430 may be continuously formed according to the degree of performance (eg, the heat treatment time) of the heat treatment process of FIG. 8. Crystallization may proceed to form the upper first polycrystalline silicon layer 410P and the upper third polycrystalline silicon layer 430P. That is, the upper first, upper second, and upper third amorphous silicon layers 410, 420, and 430 may be formed of the upper first, upper second, and upper third layers even at a low temperature heat treatment of 600 ° C. or lower using fine crystalline silicon as a seed. Crystallization may be performed using the polycrystalline silicon layers 410P, 420P, and 430P.
  • a transparent conductor is formed between the lower optoelectronic device 300 and the upper optoelectronic device 400, and more specifically, between the lower third amorphous silicon layer 330 and the upper first amorphous silicon layer 410.
  • a blocking layer (not shown) may be further formed. In the blocking layer, crystallization using the fine crystalline silicon layer 422 as a seed proceeds only to the upper first amorphous silicon layer 410, and the layer below the lower third amorphous silicon layer 330, that is, the lower photoelectric device 300.
  • Amorphous silicon layers 310, 320, and 330 constituting the block serves to block the progress of crystallization.
  • the blocking layer may make an ohmic contact between the lower third amorphous silicon layer 330 and the upper first polycrystalline silicon layer 410P, and as a result, improve the photoelectric conversion efficiency of the solar cell. It may be.
  • the blocking layer is preferably AZO (ZnO: Al) in which a small amount of Al is added to ZnO, but is not necessarily limited thereto, and transparent conductive materials such as conventional ITO, ZnO, IZO, FTO (SnO 2 : F), and BZO. Can be used without any special restrictions.
  • an upper electrode 500 of a conductive material is formed on the upper photoelectric device 400P.
  • a tandem polycrystalline silicon solar cell 20 having a double junction structure having excellent photoelectric conversion efficiency, reliability, and productivity may be implemented using the microcrystalline silicon layer as in the first embodiment.

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Abstract

Disclosed are a crystallized solar cell which uses a microcrystalline semiconductor layer and a production method for said solar cell. The disclosed solar cell which uses a microcrystalline semiconductor layer is provided with: a substrate (100); a lower electrode (200) which is formed on the substrate (100); a photoelectric element (300) which comprises a polycrystalline semiconductor layer (320) which is formed on the lower electrode (200) and which has crystalline particles (30) extending in the same direction as the movement direction of the electrons or electron holes; and an upper electrode (500) which is formed on the photoelectric element (300).

Description

미세 결정질 반도체층을 이용하여 결정화된 태양전지 및 그 제조방법Solar cell crystallized using microcrystalline semiconductor layer and method for manufacturing same
본 발명은 미세 결정질 반도체층을 이용하여 결정화된 태양전지 및 그 제조방법에 관한 것이다. 보다 상세하게는, 미세 결정질 반도체층 (microcrystalline semiconductor layer)을 이용하여 저온(예를 들면, 600도 이하)에서 비정질 반도체층을 결정화할 수 있는 다결정 태양전지 및 그 제조방법에 관한 것이다.The present invention relates to a solar cell crystallized using a microcrystalline semiconductor layer and a method of manufacturing the same. More specifically, the present invention relates to a polycrystalline solar cell capable of crystallizing an amorphous semiconductor layer at low temperature (for example, 600 degrees or less) using a microcrystalline semiconductor layer, and a method of manufacturing the same.
일반적으로 비정질 실리콘(a-Si)을 이용한 태양전지는 비정질 실리콘 물질 자체의 특성으로 인해 캐리어(carrier)의 확산 거리(diffusion length)가 단결정 실리콘 또는 다결정 실리콘(p-si)에 비해 매우 낮다. 따라서, 비정질 실리콘(a-Si) 태양전지는 p-n 접합 구조로 제조될 경우 빛에 의해 생성된 전자-정공 쌍(electron-hole pairs)의 수집 효율은 매우 낮고, 빛에 장시간 노출되면 열화 현상이 나타나서 시간이 갈수록 광전 변환 효율이 저하되는 문제점을 가지고 있다.In general, a solar cell using amorphous silicon (a-Si) has a very low diffusion length of a carrier compared to monocrystalline silicon or polycrystalline silicon (p-si) due to the characteristics of the amorphous silicon material itself. Therefore, when the amorphous silicon (a-Si) solar cell is manufactured with a pn junction structure, the collection efficiency of electron-hole pairs generated by light is very low, and deterioration occurs after prolonged exposure to light. As time goes by, the photoelectric conversion efficiency is lowered.
이러한 문제점을 해결하기 위해, 불순물이 첨가되지 않은 진성(intrinsic) 반도체층을 광 흡수층으로 사용하여 높은 불순물 도핑 농도를 갖는 p 형과 n 형 사이에 형성하는 비정질 실리콘 p-i-n 구조와, 이를 고온에서 열처리(예를 들면, 600도 이상)하여 다결정 실리콘(p-si)으로 결정화하는 다결정 실리콘 p-i-n 구조의 태양전지가 제안되었다.In order to solve this problem, an amorphous silicon pin structure formed between p-type and n-type having a high impurity doping concentration by using an intrinsic semiconductor layer containing no impurity as a light absorbing layer, and heat treatment at high temperature ( For example, a solar cell having a polycrystalline silicon pin structure which crystallizes to polycrystalline silicon (p-si) at 600 degrees or more) has been proposed.
이와 같은 p-i-n 구조에서 광 흡수층인 i층과 높은 불순물 도핑 농도를 갖는 p층과 n층의 접합면에는 공핍(depletion) 영역이 형성되어 내부에 전계(electric field)가 발생하게 된다. 따라서, i층에서 입사광에 의해 생성된 전자-정공 쌍은 확산이 아닌 내부의 전계에 따라 전자(-)는 n 형 실리콘층으로, 정공(+)은 p 형 실리콘층으로 이동하는 표동(drift) 전류가 흐를 수 있다.In such a p-i-n structure, a depletion region is formed at the junction between the i-layer, which is a light absorbing layer, and the p-layer and the n-layer, which have a high impurity doping concentration, to generate an electric field therein. Therefore, the electron-hole pair generated by the incident light in the i layer is a drift in which electrons (-) move to the n-type silicon layer and holes (+) move to the p-type silicon layer according to the internal electric field, not diffusion. Current can flow.
그러나, 종래의 다결정 실리콘 p-i-n 구조에서는 비정질 실리콘의 결정화시 열처리 온도가 600도 이상의 고온이 요구되기 때문에, 열처리 과정에서 기판이 변형(예를 들면, 기판의 휨)되고 불순물이 실리콘층(특히, 광 흡수층)으로 불필요하게 확산되어 광전 변환 효율을 저하시키는 문제점이 있다.However, in the conventional polycrystalline silicon pin structure, since the heat treatment temperature is required to be higher than 600 degrees at the time of crystallization of the amorphous silicon, the substrate is deformed (for example, the warpage of the substrate) during the heat treatment process and impurities are formed in the silicon layer (especially, optical Diffused into the absorption layer), thereby lowering the photoelectric conversion efficiency.
이러한 문제점을 해결하기 위해, 플라즈마 화학기상 증착법(Plasma Enhanced Chemical Vapor Deposition: PECVD)을 사용하여 비정질 실리콘과 다결정 실리콘의 경계 물질인 미세 결정질 실리콘(microcrystalline Si: μc-Si)을 이용하는 태양전지가 제안되었다. 하지만, PECVD를 이용하여 미세 결정질 실리콘을 형성할 경우 낮은 증착 압력과 높은 증착 파워 조건이 요구되어 공정 조건 제어가 까다롭고, 미세 결정질 실리콘이 다결정 실리콘에 비해 재료 특성이 떨어지는 등 태양전지의 생산성 및 광전 변환 효율 향상에 한계가 있다.In order to solve this problem, a solar cell using microcrystalline Si (μc-Si), which is a boundary material between amorphous silicon and polycrystalline silicon, has been proposed by using Plasma Enhanced Chemical Vapor Deposition (PECVD). . However, when forming microcrystalline silicon using PECVD, low deposition pressure and high deposition power conditions are required, which makes it difficult to control process conditions. There is a limit to improving conversion efficiency.
본 발명은 상기와 같은 종래기술의 제반 문제점을 해결하기 위하여 안출된 것으로서, 미세 결정질 반도체의 특성을 이용하여 저온에서도 용이하게 비정질 반도체를 결정화할 수 있는 태양전지 및 그 제조방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the above problems of the prior art, and provides a solar cell and a method of manufacturing the same that can easily crystallize the amorphous semiconductor even at low temperatures by using the characteristics of the microcrystalline semiconductor. have.
또한, 본 발명은 광 흡수층에서 생성된 전자와 전공의 이동 방향과 동일한 방향으로 성장된 결정립계를 가질 수 있는 태양전지 및 그 제조방법을 제공하는데 다른 목적이 있다.Another object of the present invention is to provide a solar cell and a method of manufacturing the same, which may have grain boundaries grown in the same direction as the direction of movement of electrons and holes generated in the light absorption layer.
또한, 본 발명은 비정질 반도체층의 결정화를 효율적으로 제어하여 광전 변환 효율을 향상시킬 수 있는 태양전지 및 그 제조방법을 제공하는데 다른 목적이 있다.Another object of the present invention is to provide a solar cell and a method of manufacturing the same, which can improve the photoelectric conversion efficiency by efficiently controlling the crystallization of the amorphous semiconductor layer.
또한, 본 발명은 다중 접합의 광전소자 중 미세 결정질 반도체의 특성을 이용하여 상부 광전소자만을 결정화할 수 있는 태양전지 및 그 제조방법을 제공하는데 다른 목적이 있다.Another object of the present invention is to provide a solar cell and a method of manufacturing the same, which can crystallize only the upper optoelectronic device by using characteristics of a microcrystalline semiconductor among multiple photoelectric devices.
본 발명에 의하면, 미세 결정질 실리콘을 이용하여 저온에서도 특성이 우수한 다결정 실리콘 태양전지를 제조할 수 있다.According to the present invention, it is possible to produce a polycrystalline silicon solar cell having excellent properties even at low temperatures using fine crystalline silicon.
또한, 본 발명에 의하면, 광 흡수층에서 생성된 전자와 전공의 이동 방향과 동일한 방향으로 결정립계를 형성하여 전자와 정공의 이동도를 향상시킴으로써 태양전지의 광전 변환 효율을 향상시킬 수 있다.Further, according to the present invention, the photoelectric conversion efficiency of the solar cell can be improved by forming grain boundaries in the same direction as the direction of movement of electrons and holes generated in the light absorbing layer to improve the mobility of electrons and holes.
또한, 본 발명에 의하면, 인시츄(in situ) 방식으로 비정질 실리콘과 미세 결정질 실리콘을 순차적으로 형성하고 이를 결정화할 수 있어서 태양전지의 신뢰성 및 생산성을 향상시킬 수 있다.In addition, according to the present invention, it is possible to sequentially form and crystallize amorphous silicon and fine crystalline silicon in an in situ manner to improve the reliability and productivity of the solar cell.
또한, 본 발명에 의하면, 다중 접합의 광전소자 중 상부 광전소자만을 미세 결정질 실리콘을 이용하여 저온에서도 특성이 우수한 다결정 실리콘으로 결정화할 수 있다.According to the present invention, only the upper photoelectric device of the multi-junction photoelectric device can be crystallized to polycrystalline silicon having excellent characteristics even at low temperature by using fine crystalline silicon.
도 1 내지 도 5는 본 발명의 제1 실시예에 따른 미세 결정질 반도체층을 이용하여 결정화된 태양전지의 제조 과정을 나타내는 도면이다.1 to 5 are views illustrating a manufacturing process of a solar cell crystallized using the microcrystalline semiconductor layer according to the first embodiment of the present invention.
도 6 내지 도 10은 본 발명의 제2 실시예에 따른 미세 결정질 반도체층을 이용하여 결정화된 적층형 태양전지의 제조 과정을 나타내는 도면이다.6 to 10 are views illustrating a manufacturing process of a stacked solar cell crystallized using the microcrystalline semiconductor layer according to the second embodiment of the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
10, 20: 태양전지10, 20: solar cell
100: 기판100: substrate
200: 하부전극200: lower electrode
300, 300P: 광전소자(하부 광전소자)300, 300P: Optoelectronic device (lower optoelectronic device)
310: 제1 비정질 실리콘층(하부 제1 비정질 실리콘층)310: first amorphous silicon layer (lower first amorphous silicon layer)
310P: 제1 다결정 실리콘층310P: first polycrystalline silicon layer
320: 제2 비정질 실리콘층(하부 제2 비정질실리콘층)320: second amorphous silicon layer (lower second amorphous silicon layer)
320P: 제2 다결정 실리콘층320P: second polycrystalline silicon layer
322, 422: 미세 결정질 실리콘층322 and 422: microcrystalline silicon layer
330: 제3 비정질 실리콘층 (하부 제3 비정질 실리콘층)330: third amorphous silicon layer (lower third amorphous silicon layer)
330p: 제3 다결정 실리콘층330p: third polycrystalline silicon layer
400, 400P: 상부 광전소자400, 400P: upper optoelectronic device
410: 상부 제1 비정질 실리콘층410: Upper first amorphous silicon layer
410P: 상부 제1 다결정 실리콘층410P: top first polycrystalline silicon layer
420: 상부 제2 비정질 실리콘층420: upper second amorphous silicon layer
420P: 상부 제2 다결정 실리콘층420P: top second polycrystalline silicon layer
430: 상부 제3 비정질 실리콘층430: upper third amorphous silicon layer
430P: 상부 제3 다결정 실리콘층430P: top third polycrystalline silicon layer
500: 상부전극500: upper electrode
본 발명의 상기 목적은 기판; 상기 기판 상에 형성되는 하부전극; 상기 하부전극 상에 형성되고 전자 또는 정공의 이동 방향과 동일한 방향으로 성장된 결정립계를 갖는 다결정 반도체층을 포함하는 광전소자; 및 상기 광전소자 상에 형성되는 상부전극을 포함하는 것을 특징으로 하는 태양전지에 의해 달성된다.The object of the present invention is a substrate; A lower electrode formed on the substrate; An optoelectronic device formed on the lower electrode and including a polycrystalline semiconductor layer having a grain boundary grown in the same direction as the movement direction of electrons or holes; And it is achieved by a solar cell comprising an upper electrode formed on the optoelectronic device.
또한, 본 발명의 상기 목적은 기판; 상기 기판 상에 형성되는 하부전극; 상기 하부전극 상에 형성되고 비정질 반도체층을 포함하는 하부 광전소자; 상기 하부 광전소자 상에 형성되고 전자 또는 정공의 이동 방향과 동일한 방향으로 성장된 결정립계를 갖는 다결정 반도체층을 포함하는 상부 광전소자; 및 상기 상부 광전소자 상에 형성되는 상부전극을 포함하는 것을 특징으로 하는 태양전지에 의해서도 달성된다.In addition, the above object of the present invention; A lower electrode formed on the substrate; A lower optoelectronic device formed on the lower electrode and including an amorphous semiconductor layer; An upper optoelectronic device formed on the lower optoelectronic device and including a polycrystalline semiconductor layer having grain boundaries grown in the same direction as the movement direction of electrons or holes; And an upper electrode formed on the upper optoelectronic device.
또한, 본 발명의 상기 목적은 (a) 적층된 비정질 반도체층 사이에 미세 결정질 반도체층을 형성하는 단계; 및 (b) 열처리 공정을 수행하여 상기 미세 결정질 반도체층과 상기 비정질 반도체층의 적어도 일부를 결정화시켜 형성되는 다결정 반도체층을 포함하는 광전소자를 형성하는 단계를 포함하는 것을 특징으로 하는 태양전지의 제조방법에 의해서도 달성된다.In addition, the above object of the present invention (a) forming a microcrystalline semiconductor layer between the stacked amorphous semiconductor layer; And (b) forming a photovoltaic device comprising a polycrystalline semiconductor layer formed by crystallizing at least a portion of the microcrystalline semiconductor layer and the amorphous semiconductor layer by performing a heat treatment process. It is also achieved by the method.
이때, 상기 (a) 단계는, (a1) 기판 상의 하부전극 상에 제1 비정질 반도체층을 형성하는 단계; (a2) 상기 제1 비정질 반도체층 상에 하부 제2 비정질 반도체층을 형성하는 단계; (a3) 상기 하부 제2 비정질 반도체층 상에 상기 미세 결정질 반도체층을 형성하는 단계; (a4) 상기 미세 결정질 반도체층 상에 상부 제2 비정질 반도체층을 형성하는 단계; 및 (a5) 상기 상부 제2 비정질 반도체층 상에 제3 비정질 반도체층을 형성하는 단계를 포함할 수 있다.At this time, the step (a), (a1) forming a first amorphous semiconductor layer on the lower electrode on the substrate; (a2) forming a lower second amorphous semiconductor layer on the first amorphous semiconductor layer; (a3) forming the microcrystalline semiconductor layer on the lower second amorphous semiconductor layer; (a4) forming an upper second amorphous semiconductor layer on the microcrystalline semiconductor layer; And (a5) forming a third amorphous semiconductor layer on the upper second amorphous semiconductor layer.
본 발명의 상기 목적과 기술적 구성 및 그에 따른 작용 효과에 관한 자세한 사항은 본 발명의 바람직한 실시예를 도시하고 있는 도면을 참조한 이하 상세한 설명에 의해보다 명확하게 이해될 것이다.Details of the above object and technical configuration of the present invention and the effects thereof according to the present invention will be more clearly understood by the following detailed description with reference to the drawings showing preferred embodiments of the present invention.
본 명세서에 있어서, 반도체층의 소재로서 가장 일반적으로 사용되는 실리콘(Si)을 일례로 설명하지만, 본 발명이 이에 한정되는 것은 아니며, 반도체 특성을 가지는 공지된 물질들을 제한없이 사용할 수 있다.In the present specification, silicon (Si) most commonly used as a material of a semiconductor layer is described as an example, but the present invention is not limited thereto, and known materials having semiconductor characteristics may be used without limitation.
[제1 실시예][First Embodiment]
이하의 상세한 설명에는 편의를 위하여 태양전지의 기판(100)의 단위셀 영역(태양전지 중 광전 변환이 일어나는 영역)을 중심으로 설명한다.In the following detailed description, for convenience, a unit cell region (a region where photoelectric conversion occurs in the solar cell) of the substrate 100 of the solar cell will be described.
도 1 내지 도 5는 본 발명의 제1 실시예에 따른 미세 결정질 반도체층을 이용하여 결정화된 태양전지의 제조 과정을 나타내는 도면이다.1 to 5 are views illustrating a manufacturing process of a solar cell crystallized using the microcrystalline semiconductor layer according to the first embodiment of the present invention.
먼저, 도 1을 참조하면, 기판(100)을 제공할 수 있다. 기판(100)의 재질은 투명한 유리 기판을 사용할 수 있으나 반드시 이에 한정되는 것은 아니며, 태양전지가 빛을 수광하는 방향에 따라 유리, 플라스틱과 같은 투명 재질 또는 실리콘, 금속[예를 들면, SUS(Stainless Steel)]과 같은 불투명 재질을 모두 사용할 수 있다.First, referring to FIG. 1, a substrate 100 may be provided. The material of the substrate 100 may be a transparent glass substrate, but is not necessarily limited thereto. The substrate 100 may be formed of a transparent material such as glass or plastic, silicon, or metal [eg, SUS (Stainless) according to a direction in which a solar cell receives light. Steel)] can be used for all opaque materials.
이어서, 도시되지는 않았지만, 기판(100)의 표면에 텍스쳐링(texturing) 공정을 수행하여 거칠기를 형성할 수 있다. 본 발명에서, 텍스쳐링이란 태양전지의 기판 표면에 입사되는 빛이 반사되어 광학적으로 손실됨으로써 그 특성이 저하되는 현상을 방지하지 위한 것이다. 즉, 기판의 표면을 거칠게 만드는 것으로서 기판 표면에 요철 패턴을 형성하는 것을 말한다. 이와 같이, 텍스쳐링으로 기판의 표면이 거칠어지면 표면에서 한번 반사된 빛이 태양전지 방향으로 재반사될 수 있으므로 빛이 손실되는 것을 감소시킬 수 있고, 광 포획량이 증가되어 태양전지의 광전 변환 효율을 향상시킬 수 있다.Subsequently, although not shown, roughness may be formed by performing a texturing process on the surface of the substrate 100. In the present invention, the texturing is to prevent the phenomenon that the characteristic is degraded by the optical reflection of light incident on the substrate surface of the solar cell is reflected. That is, forming a roughness pattern on the substrate surface by making the surface of the substrate rough. As such, when the surface of the substrate is roughened by texturing, the light reflected once from the surface may be reflected back toward the solar cell, thereby reducing the loss of light and increasing the amount of light trapping, thereby improving the photoelectric conversion efficiency of the solar cell. You can.
이때, 텍스쳐링 공정은 샌드 블래스팅 방법을 이용하여 수행할 수 있는데, 식각 입자를 압축 공기로 분사하여 식각하는 건식 블래스팅과 액체와 함께 식각 입자를 분사하여 식각하는 습식 블래스팅을 모두 포함하는 것이다. 샌드 블래스팅에 사용되는 식각 입자는 모래, 작은 금속과 같이 물리적 충격으로 기판에 요철을 형성시킬 수 있는 입자를 제한 없이 사용할 수 있다. 물론, 필요에 따라 텍스쳐링 공정을 생략할 수도 있다.In this case, the texturing process may be performed by using a sand blasting method, which includes both dry blasting for spraying etching particles with compressed air and wet blasting for spraying etching particles with liquid. Etching particles used in sand blasting can be used without limitation, such as sand, small metals, particles that can form irregularities on the substrate by physical impact. Of course, the texturing process may be omitted if necessary.
이어서, 기판(100) 상에는 반사 방지층(미도시함)을 형성할 수 있다. 반사 방지층은 기판(100)을 통하여 입사된 태양광이 실리콘층에 흡수되지 못하고 바로 외부로 반사됨으로써, 태양전지의 효율을 저하시키는 현상을 방지하는 역할을 할 수 있다. 반사 방지층의 소재는 투명 절연층인 실리콘 산화물(SiOx), 실리콘 질화물(SiNx)일 수 있으나 반드시 이에 한정되지 않는다.Subsequently, an antireflection layer (not shown) may be formed on the substrate 100. The anti-reflection layer may serve to prevent a phenomenon in which solar light incident through the substrate 100 is not absorbed by the silicon layer and is directly reflected to the outside, thereby lowering the efficiency of the solar cell. The material of the anti-reflection layer may be silicon oxide (SiO x ) or silicon nitride (SiN x ), which are transparent insulating layers, but are not limited thereto.
반사 반지층의 형성 방법으로는 저압 화학기상 증착법(Low Pressure Chemical Vapor Deposition: LPCVD) 및 플라즈마 화학기상 증착법(Plasma Enhanced Chemical Vapor Deposition: PECVD) 등과 같은 화학기상 증착법(Chemical Vapor Deposition: CVD)을 포함할 수 있다.The method of forming the reflective ring layer may include chemical vapor deposition (CVD), such as Low Pressure Chemical Vapor Deposition (LPCVD) and Plasma Enhanced Chemical Vapor Deposition (PECVD). Can be.
이어서, 기판(100) 상에는 전도성 재질의 하부전극(200)을 형성할 수 있다. 하부전극(200)의 소재는 접촉 저항이 낮으면서 투명한 성질을 갖는 투명전극(transparent conductive oxide; TCO)을 사용할 수 있다. 투명전극(TCO)은 일례로 AZO(ZnO:Al), ITO(Indium-Tin-Oxide), GZO(ZnO:Ga), BZO(ZnO:B) 및 FTO(SnO2:F) 중 어느 하나일 수 있다.Subsequently, a lower electrode 200 of a conductive material may be formed on the substrate 100. The material of the lower electrode 200 may use a transparent conductive oxide (TCO) having low contact resistance and transparent properties. For example, the transparent electrode TCO may be any one of AZO (ZnO: Al), ITO (Indium-Tin-Oxide), GZO (ZnO: Ga), BZO (ZnO: B), and FTO (SnO 2 : F). have.
하부전극(200)의 형성 방법으로는 열 증착법(Thermal Evaporation), 전자빔 증착법(E-beam Evaporation), 스퍼터링(sputtering)과 같은 물리기상 증착법(Physical Vapor Deposition: PVD) 및 LPCVD, PECVD, 금속유기 화학기상 증착법(Metal Organic Chemical Vapor Deposition: MOCVD)과 같은 화학기상 증착법(Chemical Vapor Deposition: CVD)을 포함할 수 있다.The lower electrode 200 may be formed using physical vapor deposition (PVD), LPCVD, PECVD, metal organic chemistry such as thermal evaporation, e-beam evaporation, and sputtering. Chemical Vapor Deposition (CVD), such as Metal Organic Chemical Vapor Deposition (MOCVD).
다음으로, 도 2를 참조하면, 하부전극(200) 상에는 p 형, i 형, n 형(특히, p+ 형, i 형, n+ 형), n 형, i 형, p 형(특히, n+ 형, i 형, p+ 형), p 형, n 형, n 형(특히, p+ 형, p- 형, n+ 형) 또는 n 형, n 형, p형(특히, n+ 형, n- 형, p+ 형)의 도전형을 갖는 실리콘층을 순서대로 형성할 수 있다. 여기서, +와 -의 의미는 도핑 농도의 상대적인 차이를 나타내며 +가 -보다 도핑 농도가 높음을 의미한다. 예를 들어, n+가 n-보다 하이 도핑되어 있음을 의미한다. + 또는 -의 표시가 없는 경우에는 도핑 농도의 특별한 제한이 없음을 의미한다. p 형과 n 형 사이에 위치하는 i 형의 실리콘층은 광 흡수층의 기능을 한다.Next, referring to FIG. 2, on the lower electrode 200, p-type, i-type, n-type (particularly, p + type, i-type, n + type), n-type, i-type, p-type (particularly, n + type, type i, p +), p, n, n (especially p +, p-, n +) or n, n, p (especially n +, n-, p +) A silicon layer having a conductivity type of can be formed in this order. Here, + and-means a relative difference between the doping concentrations and means that the + doping concentration is higher than the-. For example, n + is higher doped than n-. If there is no indication of + or-, there is no particular restriction on the doping concentration. An i-type silicon layer located between p-type and n-type functions as a light absorbing layer.
본 실시예에서는, 하부전극(200) 상에 p 형, i 형, n 형의 실리콘층(310, 320, 330)을 순서대로 형성한다. 보다 상세하게 설명하면, 하부전극(200) 상에 p 형의 제1 비정질 실리콘층(310)을 형성하고, 이어서 제1 비정질 실리콘층(310) 상에 i 형의 제2 비정질 실리콘층(320)을 형성하고, 이어서 제2 비정질 실리콘층(320) 상에 n 형의 제3 비정질 실리콘층(330)을 형성하여 하나의 광전소자(300)를 구성할 수 있다. In the present exemplary embodiment, p-type, i-type, and n-type silicon layers 310, 320, and 330 are sequentially formed on the lower electrode 200. In more detail, the p-type first amorphous silicon layer 310 is formed on the lower electrode 200, and then the i-type second amorphous silicon layer 320 is formed on the first amorphous silicon layer 310. Next, an n-type third amorphous silicon layer 330 may be formed on the second amorphous silicon layer 320 to form one optoelectronic device 300.
또한, 본 실시예에서는, 제2 비정질 실리콘층(320) 형성시 제2-1 비정질 실리콘층(321)과 제2-2 비정질 실리콘층(323) 사이에 미세 결정질 실리콘층(322)을 더 형성할 수 있다. 보다 상세하게 설명하면, 제1 비정질 실리콘층(310) 상에 제2-1 비정질 실리콘층(321)을 형성하고, 이어서 제2-1 비정질 실리콘층(321) 상에 미세 결정질 실리콘층(322)을 형성하고, 이어서 미세 결정질 실리콘층(322) 상에 제2-2 비정질 실리콘층(323)을 형성할 수 있다. 이러한 미세 결정질 실리콘은 이후 열처리 공정에 의해 비정질 실리콘보다 저온에서 결정화되기 때문에, 미세 결정질 실리콘층(322)은 인접하는 비정질 실리콘층(321, 323)의 결정화를 유도하는 기능을 수행할 수 있다. 한편, 미세 결정질 실리콘층(322)은 상술한 바에 한정되어 배치되는 것은 아니고, 제1 비정질 실리콘층(310)과 제2 비정질 실리콘층(320) 사이, 또는 제2 비정질 실리콘층(320)과 제3 비정질 실리콘층(330) 사이에 형성될 수도 있다.In addition, in the present embodiment, when the second amorphous silicon layer 320 is formed, a fine crystalline silicon layer 322 is further formed between the 2-1 amorphous silicon layer 321 and the 2-2 amorphous silicon layer 323. can do. In more detail, the 2-1 amorphous silicon layer 321 is formed on the first amorphous silicon layer 310, and then the fine crystalline silicon layer 322 is formed on the 2-1 amorphous silicon layer 321. Next, the second-2 amorphous silicon layer 323 may be formed on the microcrystalline silicon layer 322. Since the microcrystalline silicon is later crystallized at a lower temperature than the amorphous silicon by a heat treatment process, the microcrystalline silicon layer 322 may function to induce crystallization of adjacent amorphous silicon layers 321 and 323. On the other hand, the fine crystalline silicon layer 322 is not limited to the above-described arrangement, and between the first amorphous silicon layer 310 and the second amorphous silicon layer 320, or the second amorphous silicon layer 320 and the first It may be formed between the three amorphous silicon layer 330.
제1(310), 제2(320: 321, 323) 및 제3 비정질 실리콘층(330) 및 미세 결정질 실리콘층(322)은 바람직하게는 PECVD를 이용하여 형성할 수 있다. PECVD 로 제2-1 비정질 실리콘층(321), 미세 결정질 실리콘층(322) 및 제2-2 비정질 실리콘층(323)을 순차적으로 형성할 때 소스가스인SiH4(또는 Si2H6)와 보조가스인 H2의 혼합비를 조절하여 형성할 수 있다. 즉, SiH4(또는 Si2H6)에 대한 H2의 비율을 감소(H2가 0일 수도 있음)시켜 제2-1 및 제2-2 비정질 실리콘층(321, 323)을 형성할 수 있고, SiH4(또는 Si2H6)에 대한 H2의 비율이 증가시켜 미세 결정질 실리콘층(322)을 형성할 수 있다. 이와 같이, PECVD에서 소스가스와 보조가스의 혼합 비율을 조정하여 형성되는 실리콘층의 결정화도를 제어하는 기술은 공지의 방법이므로 본 발명에서는 상세한 설명은 생략하기로 한다.The first 310, the second 320 (321, 323) and the third amorphous silicon layer 330 and the microcrystalline silicon layer 322 may be preferably formed using PECVD. When the 2-1 amorphous silicon layer 321, the microcrystalline silicon layer 322, and the 2-2 amorphous silicon layer 323 are sequentially formed by PECVD, SiH 4 (or Si 2 H 6 ), which is a source gas, is formed. It can be formed by adjusting the mixing ratio of H 2 as an auxiliary gas. That is, the ratio of H 2 to SiH 4 (or Si 2 H 6 ) may be decreased (H 2 may be 0) to form the 2-1 and 2-2 amorphous silicon layers 321 and 323. In addition, the ratio of H 2 to SiH 4 (or Si 2 H 6 ) may be increased to form the microcrystalline silicon layer 322. As described above, since the technique for controlling the crystallinity of the silicon layer formed by adjusting the mixing ratio of the source gas and the auxiliary gas in PECVD is a known method, detailed description thereof will be omitted.
한편, PECVD로 제1, 제2 및 제3 비정질 실리콘층(310, 320, 330)을 형성할 때는 단일 챔버 내에서 단일 공정으로 순차적으로 진행되는 인시츄(in situ) 방식을 이용하는 것이 바람직하다. 이렇게 되면, 향후 광전소자(300)를 구성하게 되는 제1, 제2 및 제3 비정질 실리콘층(310, 320, 330)이 외부 환경에 노출되지 않으면서 형성되기 때문에 태양전지의 신뢰성이 향상되며, 제조 공정이 간단해지고 제조 시간이 단축되어 태양전지의 생산성이 향상된다.On the other hand, when forming the first, second and third amorphous silicon layer (310, 320, 330) by PECVD, it is preferable to use an in situ method that proceeds sequentially in a single process in a single chamber. In this case, since the first, second and third amorphous silicon layers 310, 320, and 330, which constitute the optoelectronic device 300, are formed without being exposed to the external environment, the reliability of the solar cell is improved. The manufacturing process is simplified and the manufacturing time is shortened to increase the productivity of the solar cell.
다음으로, 도 3을 참조하면, 소정의 온도로 열처리 공정을 수행하여 미세 결정질 실리콘층(322)을 다결정 실리콘층(322P)으로 결정화시킬 수 있다. 이때, 미세 결정질 실리콘은 비정질 실리콘과 다결정 실리콘의 중간 정도의 미세 구조(microstructure)를 갖는다고 볼 수 있다. 따라서, 미세 결정질 실리콘은 비정질 실리콘보다 낮은 온도에서 다결정 실리콘으로 결정화될 수 있다. 예를 들어 비정질 실리콘을 결정화하는 온도가 600℃ 이상이라면, 미세 결정질 실리콘은 600℃ 이하의 저온(예를 들면, 550℃)에서도 다결정 실리콘으로 결정화될 수 있다. 이어서, 미세 결정질 실리콘이 비정질 실리콘의 결정화에 필요한 시드(seed) 역할을 수행할 수 있기 때문에, 제2-1 및 제2-2 비정질 실리콘층(321, 323)과 미세 결정질 실리콘층(322)의 경계면을 중심으로 제2-1 및 제2-2 비정질 실리콘층(321, 323)도 순차적으로 결정화가 진행되어 제2-1 및 제2-2 다결정 실리콘층(321P, 323P)이 될 수 있다. 이 과정에서, 시드 역할을 하는 미세 결정질 실리콘이 상기 경계면을 중심으로 상기 경계면에 수직이면서 위 또는 아래 방향으로 확산하기 때문에, 제2 비정질 실리콘층(320)은 상기 경계면에 수직한 방향으로 성장된 결정립계(grain boundary) 및 상기 결정립계와 수직한 방향으로 배열된 다결정 실리콘의 그레인(grain)을 포함하는 다결정 실리콘층(광 흡수층)으로 결정화될 수 있다. 따라서, 광흡수층의 결정립계의 성장 방향은 광 흡수층에서 생성되는 전자 또는 정공의 이동 방향과 동일하기 때문에, 태양전지 내에서 전자 또는 정공의 이동도가 증가하여 태양전지의 광전 변환 효율을 향상시킬 수 있다.Next, referring to FIG. 3, the microcrystalline silicon layer 322 may be crystallized into the polycrystalline silicon layer 322P by performing a heat treatment process at a predetermined temperature. In this case, it can be seen that the microcrystalline silicon has a microstructure in the middle of the amorphous silicon and polycrystalline silicon. Thus, fine crystalline silicon can be crystallized into polycrystalline silicon at a lower temperature than amorphous silicon. For example, when the temperature for crystallizing amorphous silicon is 600 ° C. or more, the fine crystalline silicon may be crystallized to polycrystalline silicon even at a low temperature of 600 ° C. or less (eg, 550 ° C.). Subsequently, since the microcrystalline silicon may serve as a seed required for crystallization of the amorphous silicon, the 2-1 and 2-2 amorphous silicon layers 321 and 323 and the microcrystalline silicon layer 322 may be formed. The 2-1 and 2-2 amorphous silicon layers 321 and 323 may also be sequentially crystallized around the interface to become the 2-1 and 2-2 polycrystalline silicon layers 321P and 323P. In this process, since the crystalline silicon serving as the seed diffuses in the up or down direction perpendicular to the interface with respect to the interface, the second amorphous silicon layer 320 is grown in the direction perpendicular to the interface. It can be crystallized into a polycrystalline silicon layer (light absorbing layer) comprising grain boundaries and grains of polycrystalline silicon arranged in a direction perpendicular to the grain boundaries. Therefore, since the growth direction of the grain boundary of the light absorption layer is the same as the direction of movement of electrons or holes generated in the light absorption layer, the mobility of electrons or holes in the solar cell may be increased to improve the photoelectric conversion efficiency of the solar cell. .
다음으로, 도 4를 참조하면, 도 3의 열처리 공정의 수행 정도(예를 들면, 열처리 시간)에 따라, 제1 비정질 실리콘층(310)과 제3 비정질 실리콘층(330) 까지도 연속적으로 결정화가 진행되어 제1 다결정 실리콘층(310P)과 제3 다결정 실리콘층(330P)이 될 수 있다. 즉, 미세 결정질 실리콘을 시드로 하여 600℃ 이하의 저온 열처리로도 제1, 제2 및 제3 비정질 실리콘층(310, 320, 330)을 제1, 제2 및 제3 다결정 실리콘층(310P, 320P, 330P)층으로 결정화시킬 수 있다. 따라서, 고온 열처리에 따른 기판(100)의 변형(예를 들면, 기판 휨)을 방지할 수 있다.Next, referring to FIG. 4, crystallization is continuously performed even to the first amorphous silicon layer 310 and the third amorphous silicon layer 330 according to the degree of performance (eg, heat treatment time) of the heat treatment process of FIG. 3. The process may be the first polycrystalline silicon layer 310P and the third polycrystalline silicon layer 330P. That is, the first, second, and third amorphous silicon layers 310, 320, and 330 may be formed into the first, second, and third polycrystalline silicon layers 310P, even by a low temperature heat treatment of 600 ° C. or lower, using fine crystalline silicon as a seed. 320P, 330P) layer can be crystallized. Therefore, deformation of the substrate 100 due to high temperature heat treatment (for example, warpage of the substrate) can be prevented.
한편, 제1 비정질 실리콘층(310)과 제3 비정질 실리콘층(330)을 보다 효율적으로 결정화를 촉진하기 위하여, 제1 비정질 실리콘층(310) 및/또는 제3 비정질 실리콘층(330) 상에는 별도의 금속층(미도시함)을 형성하여 제1 비정질 실리콘층(310)과 제3 비정질 실리콘층(330)은 금속유도 결정화(Metal Induced Crystallization: MIC) 방식에 의해서도 결정화가 진행되게 할 수 있다. 물론, 이 과정에서 제2-1, 제2-2 비정질 실리콘층(321, 323)의 결정화도 촉진시킬 수 있다. 상기 금속층의 성분은 Ni, Al, Ti, Ag, Au, Co, Sb, Pd, Cu 중 어느 하나 또는 이들 중 둘 이상의 조합을 포함할 수 있다. 상기 금속층의 형성 방법으로는 저압 화학 기상 증착법, 플라즈마 화학 기상 증착법, 원자 단위층 증착법, 스퍼터링법 등을 포함할 수 있다. 금속유도 결정화 방식에 의한 비정질 실리콘의 결정화 방법은 공지의 기술이므로, 이에 대한 상세한 설명은 본 명세서에서는 생략하기로 한다.Meanwhile, in order to promote crystallization of the first amorphous silicon layer 310 and the third amorphous silicon layer 330 more efficiently, the first amorphous silicon layer 310 and / or the third amorphous silicon layer 330 are separately provided. The metal layer (not shown) may be formed so that the first amorphous silicon layer 310 and the third amorphous silicon layer 330 may be crystallized by a metal induced crystallization (MIC) method. Of course, the crystallization of the 2-1 and 2-2 amorphous silicon layers 321 and 323 may be promoted in this process. The component of the metal layer may include any one of Ni, Al, Ti, Ag, Au, Co, Sb, Pd, Cu, or a combination of two or more thereof. The metal layer may be formed by a low pressure chemical vapor deposition method, a plasma chemical vapor deposition method, an atomic unit layer deposition method, a sputtering method, or the like. Since the method of crystallizing amorphous silicon by the metal-induced crystallization method is a known technique, a detailed description thereof will be omitted herein.
다음으로, 도 5를 참조하면, 제1, 제2 및 제3 다결정 실리콘층(310P, 320P, 330P)층으로 구성되는 광전소자(300P) 상에 전도성 재질의 상부전극(500)을 형성할 수 있다. 상부전극(500)의 재질은 투명전극(TCO)이거나, 통상적인 전도성 소재인 구리(Cu), 알루미늄(Al), 티타늄(Ti), 은(Ag) 등 및 이들의 합금 등을 포함할 수 있으나, 이에 한정되는 것은 아니다. 상부전극(500)의 형성 방법으로는 스퍼터링과 같은 물리기상 증착법 및 LPCVD, PECVD, MOCVD와 같은 화학기상 증착법 등을 포함할 수 있다.Next, referring to FIG. 5, the upper electrode 500 of the conductive material may be formed on the photoelectric device 300P including the first, second, and third polycrystalline silicon layers 310P, 320P, and 330P. have. The material of the upper electrode 500 may be a transparent electrode (TCO), or may include copper (Cu), aluminum (Al), titanium (Ti), silver (Ag), and alloys thereof, which are conventional conductive materials. It is not limited to this. The method of forming the upper electrode 500 may include a physical vapor deposition method such as sputtering and a chemical vapor deposition method such as LPCVD, PECVD, and MOCVD.
이로써 본 실시예에서는 미세 결정질 실리콘층을 이용한 우수한 광전 변환 효율, 신뢰성 및 생산성을 갖는 다결정 실리콘 태양전지(10)를 구현할 수 있다.As a result, in the present exemplary embodiment, the polycrystalline silicon solar cell 10 having excellent photoelectric conversion efficiency, reliability, and productivity using the microcrystalline silicon layer may be implemented.
[제2 실시예]Second Embodiment
본 실시예는 제1 실시예의 다결정 실리콘 에서, 탠덤형 태양전지는 광전소자가 다중 접합(multi junction)으로 적층된 구조를 의미하는 것으로서, 이하의 상세한 설명에서는 이중 접합으로 적층된 탠덤형 태양전지를 중심으로 설명하지만 이에 한정되는 것은 아니며, 삼중 접합 이상의 적층 구조를 갖는 태양전지를 포괄하는 개념일 수 있다.In the present embodiment, in the polycrystalline silicon of the first embodiment, a tandem solar cell refers to a structure in which photovoltaic devices are stacked in a multi junction, and in the following description, a tandem solar cell stacked in a double junction is described. Although the description will be made in the center, the present invention is not limited thereto, and the concept may include a solar cell having a laminated structure of triple junction or more.
또한, 본 실시예는 이중 접합의 적층형 태양전지라는 점에서 제1 실시예와 차이가 있으며, 이하의 본 실시예의 설명에서 제1 실시예와 중복되는 내용은 생략하였다.In addition, the present embodiment is different from the first embodiment in that it is a double-junction stacked solar cell, and the description of this embodiment will be omitted.
도 6 내지 도 10은 본 발명의 제2 실시예에 따른 미세 결정질 반도체층을 이용하여 결정화된 적층형 태양전지의 제조 과정을 나타내는 도면이다.6 to 10 are views illustrating a manufacturing process of a stacked solar cell crystallized using the microcrystalline semiconductor layer according to the second embodiment of the present invention.
먼저, 도 6을 참조하면, 기판(100)이 제공되고, 기판(100) 상에 하부전극(200)이 형성된다.First, referring to FIG. 6, a substrate 100 is provided, and a lower electrode 200 is formed on the substrate 100.
이어서, 하부전극(200) 상에 p 형, i 형, n 형의 실리콘층(310, 320, 330)을 순서대로 형성한다. 보다 상세하게 설명하면, 하부전극(200) 상에 p 형의 하부 제1 비정질 실리콘층(310)을 형성하고, 이어서 하부 제1 비정질 실리콘층(310) 상에 i 형의 하부 제2 비정질 실리콘층(320)을 형성하고, 이어서 하부 제2 비정질 실리콘층(320) 상에 n 형의 하부 제3 비정질 실리콘층(330)을 형성하여 하부 실리콘층(310, 320, 330)이 적층된 하부 광전소자(300)를 구성할 수 있다.Subsequently, p-type, i-type, and n-type silicon layers 310, 320, and 330 are sequentially formed on the lower electrode 200. In more detail, the p-type lower first amorphous silicon layer 310 is formed on the lower electrode 200, and then the i-type lower second amorphous silicon layer is formed on the lower first amorphous silicon layer 310. A lower photovoltaic device in which the lower silicon layers 310, 320, and 330 are stacked by forming an n-type lower third amorphous silicon layer 330 on the lower second amorphous silicon layer 320. 300 can be configured.
다음으로, 도 7을 참조하면, 하부 광전소자(300) 상에 p 형, i 형, n 형의 실리콘층(410, 420, 430)을 순서대로 형성한다. 보다 상세하게 설명하면, 하부 광전소자(300) 상에p 형의 상부 제1 비정질 실리콘층(410)을 형성하고, 이어서 상부 제1 비정질 실리콘층(410) 상에 i 형의 상부 제2 비정질 실리콘층(420)을 형성하고, 이어서 상부 제2 비정질 실리콘층(420) 상에 n 형의 상부 제3 비정질 실리콘층(430)을 형성하여 상부 실리콘층(410, 420, 430)이 적층된 상부 광전소자(400)를 구성할 수 있다.Next, referring to FIG. 7, p-type, i-type, and n-type silicon layers 410, 420, and 430 are sequentially formed on the lower photoelectric device 300. In more detail, the p-type upper first amorphous silicon layer 410 is formed on the lower photoelectric device 300, and then the i-type upper second amorphous silicon is formed on the upper first amorphous silicon layer 410. An upper photoelectric layer in which the upper silicon layers 410, 420, and 430 are stacked by forming a layer 420, and then forming an n-type upper third amorphous silicon layer 430 on the upper second amorphous silicon layer 420. The device 400 may be configured.
본 실시예에서는, 상부 제2 비정질 실리콘층(420) 형성시 상부 제2-1 비정질 실리콘층(421)과 상부 제2-2 비정질 실리콘층(423) 사이에 미세 결정질 실리콘층(422)을 더 형성할 수 있다. 보다 상세하게 설명하면, 하부 제3 비정질 실리콘층(330) 상에 상부 제2-1 비정질 실리콘층(421)을 형성하고, 이어서 상부 제2-1 비정질 실리콘층(421) 상에 미세 결정질 실리콘층(422)을 형성하고, 이어서 미세 결정질 실리콘층(422) 상에 상부 제2-2 비정질 실리콘층(423)을 형성할 수 있다. 이러한 미세 결정질 실리콘은 이후 열처리 공정에 의해 비정질 실리콘보다 저온에서 결정화되기 때문에, 미세 결정질 실리콘층(422)은 인접하는 비정질 실리콘층(421, 423)의 결정화를 유도하는 기능을 수행할 수 있다. 한편, 미세 결정질 실리콘층(422)은 상술한 바에 한정되어 배치되는 것은 아니고, 상부 제1 비정질 실리콘층(410)과 상부 제2 비정질 실리콘층(420) 사이, 또는 상부 제2 비정질 실리콘층(420)과 상부 제3 비정질 실리콘층(430) 사이에 형성될 수도 있다.In the present embodiment, when the upper second amorphous silicon layer 420 is formed, a fine crystalline silicon layer 422 is further added between the upper 2-1 amorphous silicon layer 421 and the upper 2-2 amorphous silicon layer 423. Can be formed. In more detail, the upper 2-1 amorphous silicon layer 421 is formed on the lower third amorphous silicon layer 330, and then the fine crystalline silicon layer is formed on the upper 2-1 amorphous silicon layer 421. 422 may be formed, and then an upper second-second amorphous silicon layer 423 may be formed on the microcrystalline silicon layer 422. Since the microcrystalline silicon is crystallized at a lower temperature than amorphous silicon by a heat treatment process, the microcrystalline silicon layer 422 may function to induce crystallization of adjacent amorphous silicon layers 421 and 423. On the other hand, the microcrystalline silicon layer 422 is not limited to the above-described arrangement, and is disposed between the upper first amorphous silicon layer 410 and the upper second amorphous silicon layer 420 or the upper second amorphous silicon layer 420. ) And the upper third amorphous silicon layer 430 may be formed.
다음으로, 도 8을 참조하면, 소정의 온도로 열처리 공정을 수행하여 미세 결정질 실리콘층(422)을 다결정 실리콘층(422P)으로 결정화시킬 수 있다. 이때, 미세 결정질 실리콘은 제1 실시예와 동일하게 600℃ 이하의 저온(예를 들면, 550℃)에서도 다결정 실리콘으로 결정화될 수 있으며, 이 과정에서 미세 결정질 실리콘이 비정질 실리콘의 결정화에 필요한 시드(seed) 역할을 수행하여 상부 제2-1 및 상부 제2-2 비정질 실리콘층(421, 423)과 미세 결정질 실리콘층(422)의 경계면을 중심으로 상부 제2-1 및 상부 제2-2 비정질 실리콘층(421, 423)도 순차적으로 결정화가 진행되어 제2-1 및 제2-2 다결정 실리콘층(421P, 423P)이 될 수 있다.Next, referring to FIG. 8, the microcrystalline silicon layer 422 may be crystallized into the polycrystalline silicon layer 422P by performing a heat treatment process at a predetermined temperature. In this case, the microcrystalline silicon may be crystallized into polycrystalline silicon at a low temperature (for example, 550 ° C) of 600 ° C. or less as in the first embodiment, and in this process, the microcrystalline silicon may be seeded for crystallization of amorphous silicon. seed) to act on the interface between the upper 2-1 and upper 2-2 amorphous silicon layers 421 and 423 and the microcrystalline silicon layer 422, and the upper 2-1 and upper 2-2 amorphous layers. The silicon layers 421 and 423 may also be sequentially crystallized to become the 2-1 and 2-2 polycrystalline silicon layers 421P and 423P.
다음으로, 도 9를 참조하면, 도 8의 열처리 공정의 수행 정도(예를 들면, 열처리 시간)에 따라, 상부 제1 비정질 실리콘층(410)과 상부 제3 비정질 실리콘층(430) 까지도 연속적으로 결정화가 진행되어 상부 제1 다결정 실리콘층(410P)과 상부 제3 다결정 실리콘층(430P)될 수 있다. 즉, 미세 결정질 실리콘을 시드로 하여 600℃ 이하의 저온 열처리로도 상부 제1, 상부 제2 및 상부 제3 비정질 실리콘층(410, 420, 430)을 상부 제1, 상부 제2 및 상부 제3 다결정 실리콘층(410P, 420P, 430P)으로 결정화시킬 수 있다.Next, referring to FIG. 9, even the upper first amorphous silicon layer 410 and the upper third amorphous silicon layer 430 may be continuously formed according to the degree of performance (eg, the heat treatment time) of the heat treatment process of FIG. 8. Crystallization may proceed to form the upper first polycrystalline silicon layer 410P and the upper third polycrystalline silicon layer 430P. That is, the upper first, upper second, and upper third amorphous silicon layers 410, 420, and 430 may be formed of the upper first, upper second, and upper third layers even at a low temperature heat treatment of 600 ° C. or lower using fine crystalline silicon as a seed. Crystallization may be performed using the polycrystalline silicon layers 410P, 420P, and 430P.
한편, 도시되어 있지 않지만, 하부 광전소자(300)와 상부 광전소자(400) 사이, 더 구체적으로는 하부 제3 비정질 실리콘층(330)과 상부 제1 비정질 실리콘층(410) 사이에는 투명 전도체인 차단층(미도시)이 추가로 형성될 수 있다. 상기 차단층은 미세 결정질 실리콘층(422)을 시드로 하는 결정화가 상부 제1 비정질 실리콘층(410)까지만 진행되고, 하부 제3 비정질 실리콘층(330) 이하의 층, 즉 하부 광전소자(300)를 구성하는 비정질 실리콘층(310, 320, 330)은 결정화가 진행되는 것을 차단하는 역할을 한다. 또한, 상기 차단층은 하부 제3 비정질 실리콘층(330)과 상부 제1 다결정 실리콘층(410P)간에 오믹 접촉(ohmic contact)이 이루어지게 하여서 그 결과 태양전지의 광전 변환 효율을 향상시키는 역할을 할 수도 있다. 이때, 상기 차단층은 ZnO에 Al이 소량 첨가된 AZO(ZnO:Al)인 것이 바람직하나 반드시 이에 한정되지 않으며 통상적인 ITO, ZnO, IZO, FTO(SnO2:F), BZO 등과 같은 투명 전도성 소재를 특별한 제한 없이 사용할 수 있다.Although not shown, a transparent conductor is formed between the lower optoelectronic device 300 and the upper optoelectronic device 400, and more specifically, between the lower third amorphous silicon layer 330 and the upper first amorphous silicon layer 410. A blocking layer (not shown) may be further formed. In the blocking layer, crystallization using the fine crystalline silicon layer 422 as a seed proceeds only to the upper first amorphous silicon layer 410, and the layer below the lower third amorphous silicon layer 330, that is, the lower photoelectric device 300. Amorphous silicon layers 310, 320, and 330 constituting the block serves to block the progress of crystallization. In addition, the blocking layer may make an ohmic contact between the lower third amorphous silicon layer 330 and the upper first polycrystalline silicon layer 410P, and as a result, improve the photoelectric conversion efficiency of the solar cell. It may be. In this case, the blocking layer is preferably AZO (ZnO: Al) in which a small amount of Al is added to ZnO, but is not necessarily limited thereto, and transparent conductive materials such as conventional ITO, ZnO, IZO, FTO (SnO 2 : F), and BZO. Can be used without any special restrictions.
다음으로, 도 10을 참조하면, 상부 광전소자(400P) 상에 전도성 재질의 상부전극(500)을 형성한다.Next, referring to FIG. 10, an upper electrode 500 of a conductive material is formed on the upper photoelectric device 400P.
이로써 본 실시예에서는 제1 실시예와 동일하게 미세 결정질 실리콘층을 이용하여 우수한 광전 변환 효율, 신뢰성 및 생산성을 갖는 이중 접합 구조를 갖는 탠덤형 다결정 실리콘 태양전지(20)를 구현할 수 있다.As a result, in the present embodiment, a tandem polycrystalline silicon solar cell 20 having a double junction structure having excellent photoelectric conversion efficiency, reliability, and productivity may be implemented using the microcrystalline silicon layer as in the first embodiment.

Claims (14)

  1. 기판;Board;
    상기 기판 상에 형성되는 하부전극;A lower electrode formed on the substrate;
    상기 하부전극 상에 형성되고 전자 또는 정공의 이동 방향과 동일한 방향으로 성장된 결정립계를 갖는 다결정 반도체층을 포함하는 광전소자; 및An optoelectronic device formed on the lower electrode and including a polycrystalline semiconductor layer having a grain boundary grown in the same direction as the movement direction of electrons or holes; And
    상기 광전소자 상에 형성되는 상부전극An upper electrode formed on the optoelectronic device
    을 포함하는 것을 특징으로 하는 태양전지.Solar cell comprising a.
  2. 기판;Board;
    상기 기판 상에 형성되는 하부전극;A lower electrode formed on the substrate;
    상기 하부전극 상에 형성되고 비정질 반도체층을 포함하는 하부 광전소자;A lower optoelectronic device formed on the lower electrode and including an amorphous semiconductor layer;
    상기 하부 광전소자 상에 형성되고 전자 또는 정공의 이동 방향과 동일한 방향으로 성장된 결정립계를 갖는 다결정 반도체층을 포함하는 상부 광전소자; 및An upper optoelectronic device formed on the lower optoelectronic device and including a polycrystalline semiconductor layer having grain boundaries grown in the same direction as the movement direction of electrons or holes; And
    상기 상부 광전소자 상에 형성되는 상부전극An upper electrode formed on the upper optoelectronic device
    을 포함하는 것을 특징으로 하는 태양전지.Solar cell comprising a.
  3. 제1항 또는 제2항에 있어서,The method according to claim 1 or 2,
    상기 다결정 반도체층은 상기 결정립계와 수직하는 방향으로 배열된 그레인을 포함하는 것을 특징으로 하는 태양전지.And said polycrystalline semiconductor layer comprises grains arranged in a direction perpendicular to said grain boundaries.
  4. 제1항 또는 제2항에 있어서,The method according to claim 1 or 2,
    상기 다결정 반도체층은 광 흡수층인 것을 특징으로 하는 태양전지.The polycrystalline semiconductor layer is a solar cell, characterized in that the light absorbing layer.
  5. 제1항 또는 제2항에 있어서,The method according to claim 1 or 2,
    상기 다결정 반도체층은 다결정 실리콘층인 것을 특징으로 하는 태양전지.The polycrystalline semiconductor layer is a solar cell, characterized in that the polycrystalline silicon layer.
  6. 제1항 또는 제2항에 있어서,The method according to claim 1 or 2,
    상기 기판과 상기 하부전극 사이에는 투명 절연체인 반사 방지층을 더 형성하는 것을 특징으로 하는 태양전지.A solar cell, characterized in that further formed between the substrate and the lower electrode an anti-reflection layer which is a transparent insulator.
  7. 제2항에 있어서,The method of claim 2,
    상기 하부 광전소자와 상기 상부 광전소자 사이에는 투명 전도체인 차단층을 더 형성하는 것을 특징으로 하는 태양전지.And a blocking layer, which is a transparent conductor, between the lower optoelectronic device and the upper optoelectronic device.
  8. (a) 적층된 비정질 반도체층 사이에 미세 결정질 반도체층을 형성하는 단계; 및(a) forming a microcrystalline semiconductor layer between the stacked amorphous semiconductor layers; And
    (b) 열처리 공정을 수행하여 상기 미세 결정질 반도체층과 상기 비정질 반도체층의 적어도 일부를 결정화시켜 형성되는 다결정 반도체층을 포함하는 광전소자를 형성하는 단계(b) forming an optoelectronic device including a polycrystalline semiconductor layer formed by performing a heat treatment to crystallize the microcrystalline semiconductor layer and at least a portion of the amorphous semiconductor layer
    를 포함하는 것을 특징으로 하는 태양전지의 제조방법.Method for manufacturing a solar cell comprising a.
  9. 제8항에 있어서,The method of claim 8,
    상기 (a) 단계는,In step (a),
    (a1) 기판 상의 하부전극 상에 제1 비정질 반도체층을 형성하는 단계;(a1) forming a first amorphous semiconductor layer on the lower electrode on the substrate;
    (a2) 상기 제1 비정질 반도체층 상에 하부 제2 비정질 반도체층을 형성하(a2) forming a lower second amorphous semiconductor layer on the first amorphous semiconductor layer
    는 단계;The step;
    (a3) 상기 하부 제2 비정질 반도체층 상에 상기 미세 결정질 반도체층을 형성하는 단계;(a3) forming the microcrystalline semiconductor layer on the lower second amorphous semiconductor layer;
    (a4) 상기 미세 결정질 반도체층 상에 상부 제2 비정질 반도체층을 형성하는 단계; 및(a4) forming an upper second amorphous semiconductor layer on the microcrystalline semiconductor layer; And
    (a5) 상기 상부 제2 비정질 반도체층 상에 제3 비정질 반도체층을 형성하는 단계(a5) forming a third amorphous semiconductor layer on the upper second amorphous semiconductor layer
    를 포함하는 것을 특징으로 하는 태양전지의 제조방법.Method for manufacturing a solar cell comprising a.
  10. 제8항에 있어서,The method of claim 8,
    상기 다결정 반도체층은 전자 또는 정공의 이동 방향과 동일한 방향으로 성장된 결정립계를 포함하는 것을 특징으로 하는 태양전지의 제조방법.The polycrystalline semiconductor layer is a manufacturing method of a solar cell, characterized in that it comprises a grain boundary grown in the same direction as the movement direction of electrons or holes.
  11. 제8항에 있어서,The method of claim 8,
    상기 다결정 반도체층은 상기 결정립계와 수직하는 방향으로 배열된 그레인을 포함하는 것을 특징으로 하는 태양전지의 제조방법.And said polycrystalline semiconductor layer comprises grains arranged in a direction perpendicular to said grain boundaries.
  12. 제8항에 있어서,The method of claim 8,
    상기 비정질 반도체층과 상기 미세 결정질 반도체층은 화학기상 증착법을 이용하여 형성되는 것을 특징으로 하는 태양전지의 제조방법.The amorphous semiconductor layer and the fine crystalline semiconductor layer is a method of manufacturing a solar cell, characterized in that formed by chemical vapor deposition.
  13. 제8항에 있어서,The method of claim 8,
    상기 비정질 반도체층과 상기 미세 결정질 반도체층은 인시츄(in situ) 방식으로 형성되는 것을 특징으로 하는 태양전지의 제조방법.The amorphous semiconductor layer and the fine crystalline semiconductor layer is a method of manufacturing a solar cell, characterized in that formed in situ (in situ) method.
  14. 제9항에 있어서,The method of claim 9,
    상기 비정질 반도체층 중 적어도 한 층 상에 금속층을 형성하는 것을 특징으로 하는 태양전지의 제조방법.Forming a metal layer on at least one of the amorphous semiconductor layers.
PCT/KR2010/007868 2009-11-24 2010-11-09 Crystallized solar cell using microcrystalline semiconductor layer and production method for same WO2011065687A2 (en)

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KR19980071510A (en) * 1997-02-19 1998-10-26 미따라이 후지오 Photovoltaic device, photoelectric converter and manufacturing method thereof
US20040231590A1 (en) * 2003-05-19 2004-11-25 Ovshinsky Stanford R. Deposition apparatus for the formation of polycrystalline materials on mobile substrates
KR20090078958A (en) * 2008-01-16 2009-07-21 서울대학교산학협력단 Polycrystalline silicon solar cell having high efficiency and method for fabricating the same

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