WO2011046012A1 - Procédé de fabrication d'un dispositif d'évaluation de transistors et dispositif d'évaluation de transistors - Google Patents

Procédé de fabrication d'un dispositif d'évaluation de transistors et dispositif d'évaluation de transistors Download PDF

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Publication number
WO2011046012A1
WO2011046012A1 PCT/JP2010/066687 JP2010066687W WO2011046012A1 WO 2011046012 A1 WO2011046012 A1 WO 2011046012A1 JP 2010066687 W JP2010066687 W JP 2010066687W WO 2011046012 A1 WO2011046012 A1 WO 2011046012A1
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Prior art keywords
pad
source
gate
electrode
inspection
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PCT/JP2010/066687
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English (en)
Japanese (ja)
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敦史 庄司
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シャープ株式会社
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Priority to JP2011536087A priority Critical patent/JP5335929B2/ja
Publication of WO2011046012A1 publication Critical patent/WO2011046012A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133351—Manufacturing of individual cells out of a plurality of cells, e.g. by dicing
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells

Definitions

  • the present invention relates to a method for manufacturing a transistor evaluation device and a transistor evaluation device, and more particularly to a TFT transistor evaluation device for a liquid crystal display device and a method for manufacturing the same.
  • the TFT evaluation structure described in Japanese Patent Application Laid-Open No. 2003-110115 corresponds to a source electrode and a drain electrode provided on both sides of an intrinsic semiconductor formed on an insulating substrate, and the intrinsic semiconductor.
  • a TFT evaluation structure for evaluating a thin film transistor including a gate electrode provided via a gate insulating film.
  • a channel region formed in the intrinsic semiconductor when a voltage is applied to the gate electrode while the N-type semiconductor and the P-type semiconductor constitute a diode composed of an N-type semiconductor-intrinsic semiconductor-P-type semiconductor with respect to the thin film transistor. It is provided so that the substrate potential can be fixed.
  • Patent Document 2 In the thin film transistor described in Japanese Unexamined Patent Publication No. 2007-173488 (Patent Document 2), n-type semiconductor layers and p-type semiconductor layers are alternately provided on both sides of the intrinsic semiconductor layer.
  • the TFT evaluation structure described in Japanese Patent Application Laid-Open No. 2003-110115 and the thin film transistor described in Japanese Patent Application Laid-Open No. 2007-173488 are mounted on an actual liquid crystal display device in order to improve specific evaluation characteristics.
  • the structure of the TFT transistor is greatly different.
  • the TFT evaluation structure and the transistor evaluation device such as the thin film transistor need to be formed on a substrate different from the mother glass of the TFT transistor to be mounted.
  • the transistor evaluation device is manufactured on a manufacturing line different from the TFT transistor manufacturing line mounted on the actual liquid crystal display device, it is necessary to prepare a new manufacturing line, which increases the cost.
  • a plurality of active matrix circuits are formed on the mother glass at intervals.
  • a circuit forming region where the active matrix circuit is formed, and a blank region where the active matrix circuit is not formed is stipulated.
  • the transistor evaluation device when the transistor evaluation device is to be manufactured in the blank area, the transistor evaluation device circuit and the active matrix circuit are adjacent to each other, and the transistor evaluation device circuit and the active matrix circuit are not adjacent to each other. Wiring density is different.
  • the drain electrode is covered with an interlayer insulating film or the like.
  • the inspection needle cannot be pressed against the drain electrode. Therefore, it is conceivable to employ a TFT transistor in which an ITO pad connected to the drain electrode is formed on the interlayer insulating film. It is conceivable that the ITO pad is formed at the same time as the pixel electrode is formed. However, it is necessary to form a protective film on the pixel electrode, and the protective film is also formed on the ITO pad. For this reason, it is difficult to bring the inspection needle into contact with the ITO pad.
  • the area of the ITO pad is small and it is very difficult to accurately apply the inspection needle.
  • the present invention has been made in view of the above problems, and a first object of the present invention is to provide a method for manufacturing a transistor evaluation device in which the manufacturing cost is kept low and the decrease in the yield of the transistor evaluation device is suppressed. Is to provide.
  • the second object of the present invention is to propose a transistor evaluation apparatus that can easily bring an inspection needle into contact with a pad or the like connected to a drain electrode, and to manufacture the transistor evaluation apparatus. Is to provide a method.
  • the transistor evaluation apparatus manufacturing method includes a first circuit formation region in which a first matrix circuit for liquid crystal display can be formed, and a second matrix circuit for liquid crystal display, which has a lower yield than the first circuit formation region.
  • the first matrix circuit is formed in the first circuit formation region, and the transistor evaluation circuit is formed in the second circuit formation region.
  • the step of forming the transistor evaluation circuit includes a step of forming a gate electrode, a step of forming a gate pad connected to the gate electrode, a step of forming a gate insulating film on the gate electrode, and a gate insulating film Forming a semiconductor layer thereon; forming a drain electrode and a source electrode formed on the semiconductor layer and spaced apart from each other; and forming an inspection drain pad connected to the drain electrode And forming a test source pad connected to the source electrode.
  • the step of forming the gate electrode includes a step of forming the first gate electrode and the second gate electrode.
  • the step of forming the drain electrode and the source electrode includes a first drain electrode and a first source electrode located above the first gate electrode, a second drain electrode and a second source electrode located above the second gate electrode, Forming a step.
  • the inspection drain pad is connected to the first drain electrode.
  • the step of forming the transistor evaluation circuit includes a step of forming a dummy source pad spaced from the inspection source pad, a first source wiring connecting the first source electrode and the inspection source pad, and a second source wiring.
  • the step of forming the first matrix circuit and the transistor evaluation circuit includes a step of disposing a mother substrate in the plasma device, wherein the second circuit formation region is more plasma than the first circuit formation region in the plasma device. It is arranged away from the insertion port of the device.
  • a transistor evaluation apparatus includes a substrate having a main surface including a test element forming region and a test peripheral region located around the test element forming region, and being positioned in the test element forming region and on the main surface of the substrate.
  • a first gate electrode and a second gate electrode are formed and spaced apart from each other.
  • the transistor evaluation apparatus includes a first gate wiring connected to the first gate electrode, a first gate pad formed in the inspection peripheral region and connected to the first gate wiring, and the first gate electrode and the second gate electrode. And a gate insulating film formed on the substrate.
  • the transistor evaluation apparatus includes a first semiconductor layer located above the first gate electrode and above the first gate electrode, and a second semiconductor located above the gate insulating film and above the second gate electrode.
  • a drain electrode and a second source electrode are provided.
  • the transistor evaluation device includes a first drain wiring connected to the first drain electrode and formed on the gate insulating film, a test drain pad formed in the test peripheral region and connected to the first drain wiring, A first source line connected to the source electrode and formed on the gate insulating film, and an inspection source pad connected to the first source line are provided.
  • a dummy source pad formed in the inspection peripheral region and spaced from the inspection source pad, and a second source disposed between the dummy source pad and the second source electrode and partially disconnected. And a wiring.
  • the first drain wiring is formed so as to reach the inspection drain pad from the first drain electrode through the disconnected portion of the second source wiring.
  • the transistor evaluation device is formed over the second gate wiring connected to the second gate electrode, the second gate pad connected to the second gate wiring, and the first gate pad and the second gate pad. And a conductive gate terminal connecting the first gate pad and the second gate pad.
  • the transistor evaluation device is formed in the inspection peripheral region, is formed over the dummy source pad and the inspection source pad, and is formed over the dummy source pad and the inspection source pad. A conductive source terminal to which the source pad is connected.
  • the inspection needle can be easily brought into contact with a pad or the like connected to the drain electrode.
  • FIG. 4 is a circuit diagram schematically showing a part of a circuit of a transistor evaluation device 500.
  • FIG. FIG. 2 is a plan view showing in detail a configuration around a test transistor 215A and a dummy transistor 215B shown in FIG. 5 is a cross-sectional view of an inspection element formation region 230 and an inspection peripheral region 205.
  • FIG. It is sectional drawing in the test
  • FIG. 8 is a plan view showing a part of the active matrix circuit shown in FIG. 7 in detail. It is sectional drawing which shows sectional drawing in the pixel arrangement
  • FIG. It is sectional drawing of the test
  • FIG. 16 is a cross-sectional view of an inspection peripheral region 205 during the manufacturing process shown in FIG. 15.
  • FIG. 16 is a cross-sectional view of an inspection peripheral region 205 during the manufacturing process shown in FIG. 15.
  • FIG. 18 is a plan view of a circuit formation region 301B during the manufacturing process shown in FIGS. 15 to 17. It is a top view in the circuit formation area 301A at the time of the manufacturing process of FIG.
  • FIG. 21 is a cross-sectional view of an inspection peripheral region 205 during the manufacturing process shown in FIG. 20.
  • FIG. 21 is a cross-sectional view of an inspection peripheral region 205 during the manufacturing process shown in FIG. 20. It is a top view at the time of the manufacturing process shown in FIG.
  • FIG. 24 is a plan view of a circuit formation region 301A during the manufacturing process shown in FIG. 23. It is sectional drawing which shows the manufacturing process after the manufacturing process shown in FIG.
  • FIG. 26 is a cross-sectional view of an inspection peripheral region 205 during the manufacturing process shown in FIG. 25.
  • FIG. 26 is a cross-sectional view of an inspection peripheral region 205 during the manufacturing process shown in FIG. 25.
  • FIG. 28 is a plan view of the circuit formation region 301B during the manufacturing process shown in FIGS. 25 to 27.
  • FIG. 28 is a plan view of the circuit formation region 301A during the manufacturing process shown in FIGS. 25 to 27;
  • a transistor evaluation apparatus 500 according to the present invention will be described with reference to FIGS.
  • FIG. 1 is a circuit diagram schematically showing a part of the circuit of the transistor evaluation apparatus 500.
  • the transistor evaluation apparatus 500 includes a transparent substrate 223 having a main surface and an evaluation circuit 501 formed on the main surface of the transparent substrate 223.
  • an inspection element forming region 230 in which a plurality of inspection transistors (thin film transistors) 215A and dummy transistors 215B are formed, and an inspection periphery in which terminals 228, source terminals 227, drain pads 226 and the like are formed
  • An area 205 is defined.
  • the terminal 228, the source terminal 227, and the drain pad 226 are connected to the inspection transistor 215A and the dummy transistor 215B.
  • the source terminal 227 is made of a conductive material such as silver.
  • a conductive source terminal 227 is formed over the plurality of source pads 214A and 214B, and each source pad 214A and the source pad 214B are electrically connected by the source terminal 227.
  • the inspection needle can be easily brought into contact with the source terminal 227.
  • the source pad 214A is connected to the source wiring 213A connected to the source electrode of the inspection transistor 215A.
  • the source pad (dummy source pad) 214B is connected to the source wiring 213B connected to the source electrode of the dummy transistor 215B.
  • the gate terminal 228 is made of a conductive metal material such as silver.
  • a plurality of gate pads 212 are formed on the lower surface of the gate terminal 228, and conductive gate terminals 228 are formed over the plurality of gate pads 212. Each gate pad 212 is electrically connected by a gate terminal 228.
  • the gate pad 212 is connected to the inspection transistor 215A and the dummy transistor 215B by a gate line 211.
  • the pixel electrode 216 is connected to the drain electrode of the inspection transistor 215A. Note that the wiring disposed between the drain electrode of the dummy transistor 215B and the pixel electrode 216 is disconnected. For this reason, the drain electrode of the dummy transistor 215B and the pixel electrode 216 are not electrically connected.
  • the drain pad (inspection drain pad) 226 is connected to the drain electrode of the inspection transistor 215A.
  • FIG. 2 is a plan view showing in detail the configuration around the inspection transistor 215A and the dummy transistor 215B shown in FIG.
  • FIG. 3 is a cross-sectional view of the inspection element formation region 230 and the inspection peripheral region 205.
  • the transistor evaluation apparatus 500 is formed in a transparent substrate, gate electrodes 232A and 232B formed in a portion where a test element forming region is located on a main surface of the transparent substrate, and a test peripheral region.
  • the inspection transistor 215A includes a gate electrode 232A formed on the main surface of the transparent substrate 223, a gate insulating film 233 formed so as to cover the gate electrode 232A, and an upper surface of the gate insulating film 233A.
  • a semiconductor layer 234A formed in a portion located above the gate electrode 232A, and a source electrode 235A and a drain electrode 236A formed on the semiconductor layer 234A are provided.
  • the source electrode 235A and the source pad 214A are electrically connected by a source wiring 213.
  • the drain electrode 236A and the drain pad 226 are electrically connected by drain wirings 219 and 217A.
  • the gate electrode 232 ⁇ / b> A and the gate pad 212 are connected by the gate line 211.
  • the performance of the inspection transistor 215A can be evaluated by bringing the inspection needle into contact with the source terminal 227, the gate terminal 228, and the drain pad 226.
  • the inspection transistor 215A has the same configuration as a TFT transistor mounted on a liquid crystal display device, as will be described later, accurate evaluation can be performed.
  • the drain pad 226, the source pad 214A and the gate pad 212 are drawn out to the inspection peripheral area 205, the needle for evaluation can be easily brought into contact with each pad. For this reason, repeated evaluation can be satisfactorily performed even in a test in which the transistor evaluation apparatus 500 is exposed to a predetermined environment for a long period of time and the evaluation of the inspection transistor 215A is repeated. Specifically, in the above repeated test, it is necessary to bring the inspection needle into contact with each pad many times, but since the inspection needle is easily brought into contact with each pad, The transistor evaluation device 500 can be prevented from being damaged by the needle.
  • the transistor evaluation device 500 includes a plurality of thin film transistors arranged around the inspection transistor 215A for evaluating performance, and has the same configuration as an active matrix circuit of an actual liquid crystal display device. For this reason, accurate performance evaluation can be performed.
  • a dummy transistor 215B is disposed around the inspection transistor 215A.
  • the wiring density can be approximated to an actual active matrix circuit, and the inspection transistor 215A can be formed accurately.
  • the dummy transistor 215B includes a gate electrode 232B formed on the main surface of the transparent substrate 223, a gate insulating film 233 formed so as to cover the gate electrode 232B, and the gate insulating film 233.
  • the drain wiring 217B connected to the drain electrode 236 is disconnected, and the drain wiring 217B is not connected to the drain pad 226 and the contact pad portion 218. Further, the source wiring 213B connected to the source electrode 235B is also disconnected.
  • the drain wiring 219 is formed so as to reach the drain pad 226 from the drain electrode 236A through the disconnected portion of the drain wiring 217B and the disconnected portion of the source wiring 213.
  • FIG. 3 is a cross-sectional view in the inspection element formation region 230, and the right side is a cross-sectional view in the inspection peripheral region 205 in which the gate pad 212 is formed.
  • gate electrodes 232A and 232B, the gate line 211, the gate pad 212, the source pad 214, and the drain pad 226 are all formed by laminating an aluminum alloy film or a plurality of metal films.
  • gate electrode 232A, 232B etc. are the 1st metal film formed from titanium, and the 2nd metal film formed on the 1st metal film and formed from aluminum And a third metal film located on the second metal film and made of titanium.
  • the aluminum alloy material film includes aluminum as a base material, cobalt (Co), rhodium (Rh), nickel (Ni), palladium (Pd), carbon (C), silicon (Si), germanium (Ge). ), And an alloy component (first alloy component) containing at least one element selected from the group consisting of tin (Sn), and another component (first component) containing aluminum and an element different from the elements listed above In other words, an aluminum alloy material film having a total of three or more elements of the alloy component and the other component is employed.
  • the gate insulating film 233 is formed so as to cover the gate electrodes 232A and 232B, the gate pad 212, the source pad 214, and the drain pad 226, and the gate insulating film 233 is formed of, for example, a silicon nitride film or the like. Yes.
  • a semiconductor layer (first semiconductor layer) 234A is formed on the upper surface of the gate insulating film 233 above the gate electrode (first gate electrode) 232A.
  • a semiconductor layer (second semiconductor layer) 234B is formed in a portion located above the gate electrode (second gate electrode) 232B.
  • Each of the semiconductor layers 234A and 234B includes an amorphous silicon film (i layer) 234a and an amorphous silicon film (n + layer) 234b formed on the amorphous silicon film (i layer) 234a.
  • a source electrode (first source electrode) 235A and a drain electrode (first drain electrode) 236A are formed spaced apart from each other.
  • a source electrode (second source electrode) 235B and a drain electrode (second drain electrode) 236B are formed on the semiconductor layer 234B.
  • Each of the source electrodes 235A and 235B includes a metal film 235a formed of a metal material such as molybdenum and a metal film 234b located on the upper surface of the metal film 235a and formed of an aluminum alloy material film.
  • the drain electrodes 236A and 236B include a metal film 236a formed of a metal material such as molybdenum and a metal film 236b located on the upper surface of the metal film 236a and formed of an aluminum alloy material film.
  • the metal film 236b and the metal film 235b employ an aluminum alloy material film constituting the gate electrode 232.
  • An interlayer insulating film 240 is formed on the source electrodes 235A and 235B and the drain electrodes 236A and 236B.
  • the interlayer insulating film 240 includes a passivation film 237 and a planarization film 238 formed on the passivation film 237.
  • the passivation film 237 is formed of, for example, a silicon nitride film, and the planarization film 238 is formed of an organic material such as an acrylic-based synthetic resin.
  • a pixel electrode 216 made of an ITO film is formed on the upper surface of the planarizing film 238. Note that a protective film (not shown) is formed on the upper surface of the pixel electrode 216.
  • a gate insulating film 233 and an amorphous silicon film (i layer) 234a are formed on the upper surface of the gate pad 212, and the upper surface of the gate pad 212 is formed on the gate insulating film 233 and the amorphous silicon film (i layer) 234a.
  • a contact hole 270 is formed so as to reach.
  • the ITO film 241 is formed so as to reach the gate pad 212 through the inner peripheral surface of the contact hole 270.
  • FIG. 4 is a cross-sectional view in the inspection peripheral region 205 in which the source pad 214 is formed
  • FIG. 5 is a cross-sectional view in the inspection peripheral region 205 in which the drain pad 226 is formed.
  • the source pad 214 is formed on the main surface of the transparent substrate 223, and the gate insulating film 233 and the amorphous silicon film (i layer) 234a are formed on the upper surface of the source pad 214.
  • a contact hole 276 reaching the source pad 214 is formed in the gate insulating film 233 and the amorphous silicon film (i layer) 234a.
  • the ITO film 242 is formed so as to reach the upper surface of the source pad 214 from the upper surface of the amorphous silicon film (i layer) 234a through the inner peripheral surface of the contact hole 276.
  • the drain pad 226 is formed on the main surface of the transparent substrate 223, and a gate insulating film 233 and an amorphous silicon film (i layer) 234a are formed on the upper surface of the drain pad 226.
  • a contact hole reaching the drain pad 226 is formed in the gate insulating film 233 and the amorphous silicon film (i layer) 234a.
  • the ITO film 242 is formed so as to reach the upper surface of the drain pad 226 from the upper surface of the amorphous silicon film (i layer) 234a through the inner peripheral surface of the contact hole.
  • FIG. 6 is a plan view of a mother glass 300 on which an evaluation circuit of the transistor evaluation apparatus 500 is formed.
  • a plurality of circuit forming regions 301 capable of forming an active matrix circuit for liquid crystal display are defined.
  • circuit formation region 301 an active matrix circuit mounted on the liquid crystal display device is formed in the circuit formation region 301A, and an evaluation circuit of the transistor evaluation device 500 is formed in the circuit formation region 301B. Yes.
  • the evaluation circuit and the active matrix circuit are formed by repeatedly depositing and patterning an insulating film and a metal film. Then, an evaluation circuit or an active matrix circuit can be formed in the circuit formation region 301B by changing a mask used for patterning.
  • the mother glass 300 is formed in a rectangular shape, and the circuit formation region 301B is located on one side of the sides arranged in the longitudinal direction.
  • FIG. 7 is a circuit diagram showing an active matrix circuit formed in the circuit formation region 301A.
  • a pixel array region 107 and a peripheral region 105 located around the pixel array region 107 are defined.
  • the pixel array area 107 includes a non-display area 104 and a display area 103.
  • a plurality of thin film transistors (switching elements) 115 are arranged in a portion of the main surface of the mother glass 300 where the display area 103 of the pixel arrangement area 107 is located.
  • a plurality of gate lines 111 connected to the gate electrode of the thin film transistor 115 and source wirings 113 connected to the source electrode of the thin film transistor 115 are formed on the active matrix substrate 130.
  • a pixel electrode 116 is connected to the drain electrode of the thin film transistor 115.
  • the circuit formation region 301 ⁇ / b> A has a rectangular shape, and the gate line 111 extends in the longitudinal direction of the circuit formation region 301.
  • a plurality of gate lines 111 are formed at intervals in the lateral direction of the circuit formation region 301.
  • the source wiring 113 extends in the lateral direction, and a plurality of source wirings 113 are formed at intervals in the longitudinal direction.
  • One pixel electrode 116 is disposed in a region surrounded by the gate line 111 and the source wiring 113.
  • the gate line 111 is drawn from the thin film transistor 115 and extends from the pixel array region 107 to the peripheral region 105.
  • a gate pad 112 is formed in a portion of the gate line 111 located on the peripheral region 105.
  • the source wiring 113 is drawn from the thin film transistor 115 and extends from the pixel array region 107 to the peripheral region 105.
  • a source pad 114 is formed in a portion of the source wiring 113 located on the peripheral region 105.
  • the evaluation circuit of the transistor evaluation device 500 and the active matrix circuit mounted on the liquid crystal display device are substantially the same circuit.
  • FIG. 8 is a plan view showing in detail a part of the active matrix circuit shown in FIG. 7, and FIG. 9 is a cross-sectional view of the pixel array region 107 and a cross-sectional view of the peripheral region 105 where the gate pad 112 is formed. It shows.
  • the inspection transistor 215A and the thin film transistor 115 have substantially the same structure, and the gate pad 212 of the transistor evaluation device 500 and the gate pad 112 of the active matrix circuit are the same. It becomes the composition of.
  • the active matrix circuit is formed on the gate electrode 132 formed on the main surface of the mother glass 300, the gate insulating film 133 formed to cover the gate electrode 132, and the gate insulating film 133.
  • a semiconductor layer 134 is formed in a portion located above the gate electrode 132.
  • a source electrode 135 and a drain electrode 136 are formed on the upper surface of the semiconductor layer 134 so as to be spaced from each other.
  • An interlayer insulating film 140 is formed so as to cover the drain electrode 136 and the source electrode 135.
  • the interlayer insulating film 140 includes a planarization film 138 and a passivation film 137 formed on the planarization film 138.
  • a pixel electrode 116 is formed on the upper surface of the planarizing film 138.
  • a contact hole 175 is formed in the interlayer insulating film 140, and the pixel electrode 116 is formed so as to reach the contact pad portion 118 from the upper surface of the interlayer insulating film 140 through the inner peripheral surface of the contact hole 175. ing.
  • the gate electrode 132 shown in FIG. 9 and the gate electrodes 232A and 232B shown in FIG. 3 are formed of the same aluminum alloy material film.
  • the source electrode 135 shown in FIG. 9 and the source electrodes 235A and 235B shown in FIG. 3 are formed of the same metal film, and the drain electrode 136 and the drain electrodes 236A and 236B are formed of the same metal film. .
  • the metal films 135a and 136a are made of molybdenum, and the metal films 135b and 136b are made of an aluminum alloy material film.
  • the gate pad 112 is also formed of the same aluminum alloy material film as the gate pad 212.
  • a gate insulating film 133 and an amorphous silicon film (i layer) 134 a are formed on the upper surface of the gate pad 112.
  • a contact hole 170 formed so as to reach the gate pad 112 is formed in the gate insulating film 133 and the amorphous silicon film (i layer) 134a.
  • the ITO film 141 is formed so as to reach the gate pad 112 from the upper surface of the amorphous silicon film (i layer) 134 a through the inner peripheral surface of the contact hole 170.
  • FIG. 10 is a cross-sectional view of the peripheral region 105 where the source pad 114 is formed. As shown in FIG. 10, the source pad 114 and the source pad 214 shown in FIG. 4 are formed. Note that a gate insulating film 133 and an amorphous silicon film (i layer) 134a are formed on the source pad 114, and reach the source pad 114 on the gate insulating film 133 and the amorphous silicon film (i layer) 134a. A contact hole 176 is formed.
  • the ITO film 142 is formed so as to reach the source pad 114 from the upper surface of the amorphous silicon film (i layer) 134a through the inner peripheral surface of the contact hole 176.
  • the evaluation circuit of the transistor evaluation apparatus 500 and the active matrix circuit have substantially the same structure. Therefore, the transistor evaluation apparatus 500 can be used to accurately evaluate the active matrix substrate.
  • FIG. 11 is a cross-sectional view showing a method for manufacturing an evaluation circuit of the transistor evaluation apparatus 500 configured as described above.
  • FIG. 11 is a cross-sectional view of the mother glass 300 in the circuit formation region 301B.
  • an aluminum alloy material film is formed on the main surface of mother glass 300 and patterned to form gate electrode 232A and gate pad 212.
  • a source wiring 213 and a drain pad 226 are formed.
  • the gate electrode 132, the gate pad 112, and the source pad 114 shown in FIGS. 9 and 10 are formed in the circuit formation region 301A.
  • FIG. 14 is a cross-sectional view showing a manufacturing process after the manufacturing process shown in FIGS.
  • the mother glass 300 on which the gate electrode 232 and the like are formed is housed in a plasma CVD (chemical vapor deposition) apparatus 600, and a silicon nitride film is formed on the main surface of the mother glass 300.
  • a plasma CVD chemical vapor deposition
  • the plasma CVD apparatus 600 includes a housing 602 that can accommodate the mother glass 300, and an upper electrode 603 and a lower electrode 601 that are disposed in the housing 602.
  • An insertion port 604 is formed in the housing 602, and the housing 602 includes a door that opens and closes the insertion port 604.
  • the upper electrode 603 is provided with a supply port for supplying a reaction gas to the housing 602, and a heater is provided in the lower electrode 601.
  • the reactive gas supplied into the housing 602 is brought into a plasma state, and active radicals or ions Is generated.
  • the distribution of radicals and ions varies.
  • the region away from the insertion port 604 has a lower concentration of radicals and ions than the region in the vicinity of the insertion port 604.
  • the yield of the active matrix circuit in the circuit formation region 301B is lower than the yield of the active matrix circuit in the circuit formation region 301A.
  • an evaluation circuit of the transistor evaluation device 500 is formed in the circuit formation region 301B, while an active matrix circuit is formed in the circuit formation region 301A.
  • the evaluation circuit when the evaluation circuit is formed in a region located between the circuit formation regions 301, the wiring density of the circuit formed in the circuit formation region 301 adjacent to the evaluation circuit and the circuit formation region 301 not adjacent to the evaluation circuit are formed. There is a difference in the wiring density of the circuit to be used. When a difference occurs in the wiring density, it becomes difficult to form a wiring pattern accurately.
  • an evaluation circuit is formed in circuit formation region 301 ⁇ / b> B and located between circuit formation regions 301 on the main surface of mother glass 300. The portion is not used as an evaluation circuit formation region.
  • FIG. 15 is a cross-sectional view showing a manufacturing process after the manufacturing process shown in FIG.
  • a gate insulating film 233 is formed on the main surface of the mother glass 300 by the plasma CVD apparatus 600 shown in FIG. At this time, the gate insulating film 133 shown in FIG. 9 is formed in the circuit formation region 301A.
  • an amorphous silicon film (i layer) 234a and an amorphous silicon film (n + layer) 234b are deposited, and the amorphous silicon film (i layer) 234a and the amorphous silicon film (n + layer) 234b are patterned. Thereby, the semiconductor layer 234A is formed. At this time, the semiconductor layer 134 shown in FIG. 9 is formed in the circuit formation region 301A.
  • a gate insulating film 233 is deposited on the gate pad 112, and an amorphous silicon film (i layer) 234a and an amorphous silicon film (n + layer) 234b are formed on the upper surface of the gate insulating film 233.
  • an amorphous silicon film (i layer) 234a and an amorphous silicon film (n + layer) 234b are formed on the upper surface of the gate insulating film 233.
  • holes 234f and 234e formed so as to reach the upper surface of the gate insulating film 233 are formed.
  • a gate insulating film 233 is formed on the upper surfaces of the source pad 214 and the drain pad 226, and an amorphous silicon film (i layer) 234 a and 234 a are formed on the upper surface of the gate insulating film 233.
  • An amorphous silicon film (n + layer) 234b is formed. Holes 234h and 234g are formed in the amorphous silicon film (i layer) 234a and the amorphous silicon film (n + layer) 234b.
  • the end of the drain pad 226 on the test element formation region 230 side is exposed from the amorphous silicon film (i layer) 234a and the amorphous silicon film (n + layer) 234b.
  • the end of the source pad 214 on the test element formation region 230 side is exposed from the amorphous silicon film (i layer) 234a and the amorphous silicon film (n + layer) 234b.
  • FIG. 18 is a plan view of the circuit formation region 301B during the manufacturing process shown in FIGS.
  • a plurality of source pads 214 are formed on the main surface of the mother glass 300 at intervals, and the gate pad 212 and the drain pad 226 are also formed on the main surface of the mother glass 300. Further, gate line 211 and gate electrode 232 are formed on the main surface of mother glass 300.
  • FIG. 19 is a plan view of the circuit formation region 301A during the manufacturing process of FIG. As shown in FIG. 19, also in circuit formation region 301 ⁇ / b> A, source pad 114, gate pad 112, gate line 111, and gate electrode 132 are formed on the main surface of mother glass 300.
  • metal films 235a and 236a and metal films 235b and 236b are sequentially deposited, and the metal films 235a and 236a and the metal films 235b and 236b are patterned.
  • the source electrode 235A and the drain electrode 236A are formed. As shown in FIG. 9, the source electrode 135 and the drain electrode 136 are also formed in the circuit formation region 301A.
  • the metal films 235a and 236a and the metal films 235b and 236b are formed by patterning the metal films 235a and 236a and the metal films 235b and 236b. It is removed from 205.
  • the amorphous silicon film (n + layer) 234b located above the gate pad 212, the source pad 214, and the pixel electrode 216 is also removed, and the amorphous silicon film (i layer) 234a is exposed.
  • FIG. 23 is a plan view of the manufacturing process shown in FIG. As shown in FIG. 23, disconnection portions are formed in the drain wiring 217B and the source wiring 213B of the dummy transistor 215B. A drain wiring 219 connected to the inspection transistor 215A is formed.
  • the drain wiring 219 is formed so as to reach the drain pad 226 through the disconnection portion formed in the source wiring 213B and the drain wiring 217B.
  • the end of the source pad 214 on the test element formation region 230 side is exposed from the amorphous silicon film (i layer) 234a, and the end of the source wiring 213 is located above this end.
  • a contact hole 225 a is formed at the end of the source wiring 213.
  • the end of the drain pad 226 is exposed from the amorphous silicon film (i layer) 234a, and the end of the drain wiring 219 is located above this end.
  • a contact hole 227 a is formed at the end of the drain wiring 219 so as to reach the end of the drain pad 226.
  • FIG. 24 is a plan view of the circuit formation region 301A during the manufacturing process shown in FIG.
  • the end of the source pad 114 on the display region 103 side is formed so as to be exposed from the amorphous silicon film (i layer) 134a.
  • the source wiring 113 is formed above the end of the source pad 114 so that the end of the source wiring 113 is located.
  • a contact hole 125 a is formed at the end of the source wiring 113 so as to reach the end of the source pad 114.
  • a passivation film 237 and a planarizing film 238 are sequentially deposited.
  • the passivation film 137 and the planarization film 138 are also formed in the circuit formation region 301A.
  • planarization films 238 and 138 are patterned, and the passivation films 237 and 137 and the gate insulating films 233 and 133 are patterned.
  • holes 270 and 234f reaching the gate pad 212 are formed in the gate insulating film 233 and the amorphous silicon film (i layer) 234a located on the gate pad 212. .
  • holes 276 and 234h are also formed in the gate insulating film 233 and the amorphous silicon film (i layer) 234a formed on the upper surfaces of the source pad 214 and the drain pad 226.
  • FIG. 28 is a plan view of the circuit formation region 301B during the manufacturing process shown in FIGS. As shown in FIG. 28, a contact hole 275 reaching the contact pad portion 218 is formed in the planarization film 238 and the passivation film 237.
  • a contact hole 175 reaching the contact pad portion 118 is also formed in the planarization film 138 and the passivation film 137.
  • an ITO film is formed, and the ITO film 242, 241, 243 is formed on the source pad 214, the gate pad 212, and the drain pad 226 by patterning the ITO film.
  • a pixel electrode 216 is also formed.
  • an ITO film is formed on the source pad 214 and the gate pad 212, and a pixel electrode is formed.
  • an active matrix circuit is formed in the circuit formation region 301A of the mother glass 300, and an evaluation circuit of the transistor evaluation device 500 is formed in the circuit formation region 301B.
  • the active glass substrate and the transistor evaluation apparatus 500 can be manufactured by cutting the mother glass 300 into the circuit forming regions 301A and 301B.
  • the present invention can be applied to a method for manufacturing a transistor evaluation apparatus and a transistor evaluation apparatus, and is particularly suitable for a TFT transistor evaluation apparatus for a liquid crystal display device and a method for manufacturing the same.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Automation & Control Theory (AREA)
  • Thin Film Transistor (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Liquid Crystal (AREA)

Abstract

L'invention concerne un procédé de fabrication d'un dispositif d'évaluation de transistors, comprenant : une étape de préparation d'une carte-mère (300) comprenant une première région de formation de circuit (301A) dans laquelle on peut former un premier circuit matriciel pour afficheur à cristaux liquides et une seconde région de formation de circuit (301B) dans laquelle on peut former un second circuit matriciel pour afficheur à cristaux liquides, la seconde région de formation de circuit ayant un rendement inférieur à celui de la première région de formation de circuit (301A), une étape de formation du premier circuit matriciel dans la première région de formation de circuit (301A), une étape de formation d'un circuit d'évaluation de transistors dans la seconde région de formation de circuit (301B), et une étape de découpage du circuit d'évaluation de transistors par découpe de la carte-mère (300).
PCT/JP2010/066687 2009-10-13 2010-09-27 Procédé de fabrication d'un dispositif d'évaluation de transistors et dispositif d'évaluation de transistors WO2011046012A1 (fr)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0815722A (ja) * 1994-06-28 1996-01-19 Kyocera Corp 液晶表示装置
JP2000075319A (ja) * 1998-08-26 2000-03-14 Sharp Corp アクティブマトリクス基板の欠陥修正方法、製造方法及び欠陥修正装置
JP2000221542A (ja) * 1999-01-29 2000-08-11 Fujitsu Ltd 薄膜トランジスタ基板
JP2005249939A (ja) * 2004-03-02 2005-09-15 Seiko Epson Corp 電気光学装置用大型パネル構造体、電気光学装置、電気光学装置用基板、電気光学装置の製造方法、及び電気光学装置の検査方法
WO2008096483A1 (fr) * 2007-02-09 2008-08-14 Sharp Kabushiki Kaisha Substrat à matrice active, panneau à cristaux liquides, unité d'affichage à cristaux liquides, dispositif d'affichage à cristaux liquides, récepteur de télévision, procédé de fabrication du substrat à matrice active et procédé de fabrication d'un panneau à cristaux liq

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0815722A (ja) * 1994-06-28 1996-01-19 Kyocera Corp 液晶表示装置
JP2000075319A (ja) * 1998-08-26 2000-03-14 Sharp Corp アクティブマトリクス基板の欠陥修正方法、製造方法及び欠陥修正装置
JP2000221542A (ja) * 1999-01-29 2000-08-11 Fujitsu Ltd 薄膜トランジスタ基板
JP2005249939A (ja) * 2004-03-02 2005-09-15 Seiko Epson Corp 電気光学装置用大型パネル構造体、電気光学装置、電気光学装置用基板、電気光学装置の製造方法、及び電気光学装置の検査方法
WO2008096483A1 (fr) * 2007-02-09 2008-08-14 Sharp Kabushiki Kaisha Substrat à matrice active, panneau à cristaux liquides, unité d'affichage à cristaux liquides, dispositif d'affichage à cristaux liquides, récepteur de télévision, procédé de fabrication du substrat à matrice active et procédé de fabrication d'un panneau à cristaux liq

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