WO2011027387A1 - Amplifier - Google Patents

Amplifier Download PDF

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Publication number
WO2011027387A1
WO2011027387A1 PCT/JP2009/004309 JP2009004309W WO2011027387A1 WO 2011027387 A1 WO2011027387 A1 WO 2011027387A1 JP 2009004309 W JP2009004309 W JP 2009004309W WO 2011027387 A1 WO2011027387 A1 WO 2011027387A1
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WO
WIPO (PCT)
Prior art keywords
amplifier
amplification
terminal
signal
amplification stage
Prior art date
Application number
PCT/JP2009/004309
Other languages
French (fr)
Japanese (ja)
Inventor
王トウ
三友敏也
Original Assignee
株式会社 東芝
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Publication date
Application filed by 株式会社 東芝 filed Critical 株式会社 東芝
Priority to PCT/JP2009/004309 priority Critical patent/WO2011027387A1/en
Publication of WO2011027387A1 publication Critical patent/WO2011027387A1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
    • H03F3/245—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages with semiconductor devices only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High frequency amplifiers, e.g. radio frequency amplifiers
    • H03F3/19—High frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
    • H03F3/193—High frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only with field-effect devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H03F3/45183—Long tailed pairs
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/408—Indexing scheme relating to amplifiers the output amplifying stage of an amplifier comprising three power stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/78—A comparator being used in a controlling circuit of an amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45594—Indexing scheme relating to differential amplifiers the IC comprising one or more resistors, which are not biasing resistor
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45596—Indexing scheme relating to differential amplifiers the IC comprising one or more biasing resistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45604—Indexing scheme relating to differential amplifiers the IC comprising a input shunting resistor
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45631—Indexing scheme relating to differential amplifiers the LC comprising one or more capacitors, e.g. coupling capacitors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45638—Indexing scheme relating to differential amplifiers the LC comprising one or more coils
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45652—Indexing scheme relating to differential amplifiers the LC comprising one or more further dif amp stages, either identical to the dif amp or not, in cascade

Definitions

  • the present invention relates to an amplifier.
  • a method having a plurality of amplification stages is known as a method for realizing a high output amplifier capable of obtaining a large output signal with respect to an input signal.
  • the current flowing through the current adjustment circuit is adjusted so that the amplification operation of the transistor that is the amplification stage is not saturated.
  • the above-described amplifier has a problem that a part of the current flowing through the amplification stage flows through the current adjustment circuit, so that the current for signal amplification is wasted. Furthermore, since the total amount of current flowing through each amplification stage increases as the number of amplification stages increases, the amplifier disclosed in Patent Document 1 has a problem that it is difficult to increase the number of amplification stages to three or more.
  • the present invention has been made to solve this problem, and an object of the present invention is to provide an amplifier that suppresses an increase in power consumption even when the number of amplification stages is increased.
  • an amplifier according to the present invention includes a transistor having source terminals connected to each other and a drain terminal connected to a first power supply potential, and amplifies an AC signal to obtain an amplified signal.
  • M amplifier stages and transistors having drain terminals connected to the source terminals of the M amplifier stages and connected to each other, the source terminals connected to the second power supply potential, and an AC signal NM amplification stages that amplify and obtain an amplified signal, wherein the source terminals of the M amplification stages and the drain terminals of the NM amplification stages are connected in common To do.
  • FIG. 1 is a diagram showing an amplifier 1 according to a first embodiment.
  • the figure which shows the amplifier 2 which concerns on 1st Example. 1 is a diagram showing an amplifier 3 according to a first embodiment.
  • FIG. 1 is a diagram showing an amplifier 4 according to a first embodiment.
  • FIG. 5 which concerns on the modification 2 of 1st Example.
  • the figure which shows the amplifier 6 which concerns on 2nd Example.
  • the figure which shows the amplifier 7 which concerns on 3rd Example.
  • the amplifier according to the first embodiment of the present invention includes M amplification stages that amplify an AC signal to obtain an amplification signal, and NM amplification stages that amplify the AC signal to obtain an amplification signal.
  • the M amplification stages have transistors whose source terminals are connected to each other and whose drain terminals are connected to the first power supply potential.
  • the NM amplifier stages have transistors having drain terminals connected to the source terminals of the M amplifier stages and connected to each other, and the source terminals connected to the second power supply potential.
  • the source terminals of the M amplification stages and the drain terminals of the NM amplification stages are connected in common.
  • the sum total of direct currents flowing through the M amplification stages is equal to the sum of direct currents flowing through the NM amplification stages.
  • the drain terminal of the kth amplification stage (k is an integer of 0 ⁇ k ⁇ N) is connected to the gate terminal of the (k + 1) th amplification stage, and The k + 1th amplification stage amplifies the amplified signal amplified by the k amplification stage.
  • amplification stage when simply referred to as an amplification stage, it refers to all M and NM amplification stages.
  • the amplifier 1 of FIG. 1 has first to third amplification stages 100-1 to 100-3.
  • the first and second amplification stages 100-1 and 2 correspond to M (2) amplification stages
  • the amplification stage has an input terminal A to which an AC signal is input, first and second terminals B and C connected to either the first or second power supply potential, and an output terminal D for outputting the amplified signal. Yes.
  • the input terminal A of the first amplification stage 100-1 becomes the input terminal of the amplifier 1.
  • the first terminal B of the first amplification stage 100-1 is connected to a first terminal B of the second amplification stage 100-2 and a second terminal C of the third amplification stage 100-3 which will be described later.
  • the second terminal C of the first amplification stage 100-1 is connected to the first power supply potential.
  • the first power supply potential is Vdd and the second power supply potential is ground.
  • the input terminal A of the second amplification stage 100-2 is connected to the output terminal D of the first amplification stage 100-1.
  • the first terminal B of the second amplification stage 100-2 is connected to the first terminal B of the first amplification stage 100-1 and the second terminal C of the third amplification stage 100-3.
  • the second terminal C of the second amplification stage 100-2 is connected to Vdd.
  • the input terminal A of the third amplification stage 100-3 is connected to the output terminal D of the second amplification stage 100-2.
  • the first terminal B of the third amplification stage 100-3 is connected to the ground.
  • the second terminal C of the third amplification stage 100-3 is connected to the first terminal B of the first and second amplification stages 100-1, 2.
  • the output terminal D of the third amplification stage 100-3 becomes the output terminal of the amplifier 1.
  • the first and second amplification stages 100-1 and 2 are connected in parallel (in terms of DC) in terms of DC current.
  • the first and second amplification stages are collectively referred to as a first amplification group 10.
  • the third amplification stage 100-3 is connected in series with the first amplification group 10 in terms of direct current (in terms of direct current).
  • the third amplification stage 100-3 is referred to as a second amplification group 20.
  • the second and third amplification stages 100-2 and 3 have the same configuration.
  • the first amplification stage 100-1 includes a first transistor having a gate terminal connected to the input terminal A, a drain terminal connected to the second terminal C via the inductor element L, and a source terminal connected to the first terminal B.
  • An amplifier circuit 110 having M1 is provided.
  • the output terminal D is connected between the inductor element L and the drain terminal of the first transistor M1 via the capacitor element C1.
  • the first amplification stage 100-1 has one end connected to the input terminal A and the gate terminal of the first transistor M1, and the other end having a resistor R to which a bias voltage Vbias is applied.
  • the first amplification stage 100-1 has a capacitor element C2 having one end connected to the first terminal B and the source terminal of the first transistor M1, and the other end grounded.
  • the first terminals B of the first and second amplification stages 100-1 and 2 are short-circuited in a direct current and are grounded in an alternating current by being connected to the ground via the capacitor element C2.
  • the second terminal C of the third amplifying stage 100-3 is connected to the first terminal B of the first and second amplifying stages 100-1 and 2 to be grounded in an AC manner.
  • the first amplification stage 100-1 in FIG. 2B is a pseudo-differential amplification stage that includes the second transistor M2 in addition to the first transistor M1, and amplifies an AC signal that is a differential signal.
  • the second and third amplification stages 100-2 and 3 have the same configuration.
  • the first amplification stage 100-1 includes a first transistor having a gate terminal connected to the input terminal A1, a drain terminal connected to the second terminal C via the inductor element L1, and a source terminal connected to the first terminal B.
  • a circuit 111 is provided.
  • the output terminal D1 is connected between the inductor element L1 and the drain terminal of the first transistor M1 via the capacitor C11.
  • the output terminal D2 is connected via the capacitor C12 between the inductor element L2 and the drain terminal of the second transistor M2.
  • the first amplification stage 100-1 has one end connected to the input terminal A1 and the gate terminal of the first transistor M1, the other end connected to the resistor R1 to which the bias voltage Vbias is applied, and one end connected to the input terminal A2 and the second transistor M2. And a resistor R2 to which the bias voltage Vbias is applied at the other end.
  • the input terminals A1 and A2 constitute the input terminal A in FIG. 1
  • the output terminals D1 and D2 constitute the output terminal D in FIG.
  • the first terminals B of the first and second amplification stages 100-1 and 2 are grounded in an AC manner by connecting the source terminals of the first and second transistors M1 and M2.
  • the second terminal C of the third amplifying stage 100-3 is connected to the first terminal B of the first and second amplifying stages 100-1 and 2 to be grounded in an AC manner.
  • the magnitude of the direct current flowing through the amplification stage is the size of the first transistor M1 of the amplification stage and the potential difference between the input terminal A and the first terminal B of the amplification stage, that is, between the gate and source of the first transistor M1. It depends on the voltage.
  • the magnitude of the direct current flowing in the first and second amplification stages 100-1 and 1002, and the third amplification stage 100-3 The magnitude of the flowing direct current can be adjusted.
  • amplifier 1 The operation of amplifier 1 will be described with reference to FIG. First, the flow of an AC signal will be described.
  • the input signal is input to the input terminal A of the first amplification stage 100-1.
  • the input signal is amplified by the first amplification stage 100-1 and converted into a first amplified signal.
  • the first amplified signal is output from the output terminal D of the first amplification stage 100-1 and input to the input terminal A of the second amplification stage 100-2.
  • the first amplification stage is amplified by the second amplification stage 100-2 and converted into a second amplified signal.
  • the second amplified signal is output from the output terminal D of the second amplification stage 100-2 and input to the input terminal A of the third amplification stage 100-3.
  • the second amplified signal is amplified by the third amplification stage 100-3 and converted into a third amplified signal.
  • the third amplified signal is output as the output signal of the amplifier 1 from the output terminal D of the third amplification stage 100-3.
  • the input signal and the first to third amplified signals are AC signals having signal information in amplitude or phase, for example. Since the first terminals B of the first and second amplification stages 100-1 and 2 are grounded in an AC manner, no AC signal is output from the first terminal B.
  • a direct current flows from Vdd that is the first power supply potential to the ground that is the second power supply potential.
  • This DC current is a current necessary for the amplification stage to amplify the AC signal.
  • DC current is input from Vdd to the second terminals C of the first and second amplification stages 100-1 and 2, respectively.
  • the direct currents input to the first and second amplification stages 100-1 and 2 are output from the first terminals B of the first and second amplification stages 100-1 and 2, and are combined to form the third amplification stage 100- Entered in 3. That is, a direct current equal to the sum of direct currents flowing through the first and second amplification stages 100-1 and 2 flows through the third amplification stage 100-3.
  • the direct current input to the third amplification stage 100-3 is output from the first terminal B of the third amplification stage to the ground.
  • the first terminal B of the first amplification stage 100-1 of the amplifier 2 is connected to the second terminal C of the second amplification stage 100-2 and the first terminal B of the third amplification stage 100-3.
  • the first terminal B of the second amplification stage 100-2 is connected to the ground, and the second terminal C is connected to the first terminals B of the first and third amplification stages 100-1 and 3.
  • the first terminal B of the third amplification stage 100-3 is connected to the first terminal B of the first amplification stage 100-1 and the second terminal C of the second amplification stage 100-2, and the second terminal C is connected to Vdd. Yes.
  • the first and third amplification stages 100-1 and 100-3 are connected in parallel in a direct current, and the first and third amplification stages 100-1, 3 and the second amplification stage 100-2 are connected in a direct current.
  • the configuration is the same as that of the amplifier 1 in FIG. 1 except that the amplifiers are connected in series.
  • the first and third amplification stages 100-1 and 3 are collectively referred to as a first amplification group 10, and the second amplification stage 100-2 is defined as a second amplification group 20.
  • the flow of the AC signal of the amplifier 2 is the same as that of the amplifier 1, and flows in the order of the first amplification stage 100-1, the second amplification stage 100-2, and the third amplification stage 100-3.
  • the direct current is input from Vdd to the second terminals C of the first and third amplification stages 100-1 and 3, respectively.
  • the direct currents input to the first and third amplification stages 100-1 and 3 are output from the first terminals B of the first and third amplification stages 100-1 and 3, and then combined, and then the second amplification stage. Input to 100-2. That is, a direct current equal to the sum of the currents flowing through the first and third amplification stages 100-1 and 3 flows through the second amplification stage 100-2.
  • the direct current input to the second amplification stage 100-2 is output from the first terminal B of the second amplification stage to the ground.
  • each amplification group is connected in parallel with each other in DC, and each amplification group is connected in series with DC, the sum of the direct current flowing through the first amplification group 10 and the second amplification group 20 The sum of the flowing DC currents is equal.
  • the first power supply potential is ground
  • the second power supply potential is Vdd.
  • the first terminals B of the first and second amplification stages 100-1 and 2 of the amplifier 3 shown in FIG. 3B are connected to the second terminals C of the third amplification stages 100-2 and 3.
  • the second terminals C of the first and second amplification stages 100-1 and 2 are connected to the ground.
  • the second terminal C of the third amplification stage 100-3 is connected to the first terminal B of the first and second amplification stages 100-1, 2.
  • the first terminal B of the third amplification stage 100-3 is connected to Vdd.
  • the first and second amplification stages 100-1 and 2 are connected in parallel in a direct current manner, and the first and second amplification stages 100-1 and 100-3 are connected in a direct current manner. Connected in series.
  • the first and second amplification stages 100-1 and 100-2 are defined as the first amplification group 10
  • the third amplification stage 100-3 is defined as the second amplification group 20.
  • the flow of the AC signal of the amplifier 3 is the same as that of the amplifier 1, and flows in the order of the first amplification stage 100-1, the second amplification stage 100-2, and the third amplification stage 100-3.
  • the direct current flows to the third amplification stage 100-3 and then to the first and second amplification stages 100-1 and 2.
  • the direct current flowing through the first and second amplification stages 100-1 and 2 is equal to the sum of the direct current flowing through the third amplification stage 100-3.
  • the first terminal B of the first and second amplification stages 100-1 and 2 of the amplifier 4 shown in FIG. 3 (c) is the second terminal C of the third and fourth amplification stages 100-3,4 and the second terminal C. Is connected to Vdd.
  • the first terminals B of the third and fourth amplification stages 100-3,4 are connected to the ground.
  • the fourth amplification stage 100-4 has the same configuration as the first to third amplification stages 100-1 to 100-3, for example, the stage configuration shown in FIG.
  • the first and second amplification stages 100-1 and 2 are connected in parallel in a direct current manner.
  • the first and second amplification stages 100-1 and 2 are defined as a first amplification group 10.
  • the third and fourth amplification stages 100-3,4 are connected in parallel in a direct current manner.
  • the third and fourth amplification stages 100-3 and 4 are defined as a second amplification group 20.
  • the first and second amplification groups 10 and 20 are connected in series in a direct current manner.
  • the flow of the AC signal input to the amplifier 4 will be described.
  • the AC signal input to the input terminal A of the first amplification stage 100-1 flows in the order of the second amplification stage 100-2, the third amplification stage 100-3, and the fourth amplification stage 100-4. Amplified and output from the output terminal D of the fourth amplification stage 100-4.
  • the direct current flowing through the amplifier 4 will be described.
  • the direct current flowing from Vdd to the first and second amplification stages 100-1 and 2 flows into the third and fourth amplification stages 100-3,4 and flows to the ground.
  • the sum of direct currents flowing through the first and second amplification stages 100-1 and 2 is equal to the sum of direct currents flowing through the third and third amplification stages 100-3,4.
  • M M amplifier stages included in the first amplification group
  • M 2
  • Modification 1 When the input AC signal is amplified by the plurality of amplification stages 100-1 to 100-n as in this embodiment, the power of the AC signal that can be output increases as the direct current flowing through the first transistor of the amplification stage increases. Therefore, in order to increase the output power of the amplifier, it is only necessary to increase the current flowing through the first transistor in the subsequent amplification stage than in the previous amplification stage. That is, the k amplification stage 100-k (k is 1 ⁇ k ⁇ integer n) and DC current I k + 1 flowing through the direct current Ik and the k + 1 amplifier stage 100-k + 1 flowing to the I k ⁇ I k + 1 is sufficient.
  • the direct current I k is determined by the size W k of the first transistor and the potential difference between the input terminal A and the first terminal B, that is, the gate-source voltage V gs-k of the first transistor M1. Therefore, in order to increase the output power of the amplifier, W k and V gs-k may be designed so that I k ⁇ I k + 1 .
  • M> NM M amplification stages are composed of the first to M amplification stages
  • NM amplification stages are composed of the M + 1 to N amplification stages.
  • Each size W1s of the first transistors of the NM amplification stages (s is an integer of 1 ⁇ s ⁇ NM) is each size W2t of the first transistors of the M amplification stages (t is an integer of 1 ⁇ t ⁇ M) ) Larger than (W1s> W2t).
  • the sum of the DC currents flowing through the M amplification stages included in the first amplification group 10 is equal to the sum of the DC currents flowing through the NM amplification stages included in the second amplification group 20. can do.
  • the size of the first transistor in the amplification stage is W1s> W2t (s is an integer of 1 ⁇ s ⁇ N ⁇ M, and t is an integer of 1 ⁇ t ⁇ M). Further, the voltage difference Vgk between the gate terminal and the source terminal of the first transistor of the k-th amplification stage 100-k is set to satisfy Vgk ⁇ Vgk + 1. Thereby, the output power of the amplifier can be increased.
  • the AC signal is input in the order of the first amplification stage 100-1, the second amplification stage 100-2, and the third amplification stage 100-3. The AC signal increases in order as it is input to the amplification stage.
  • the amplifier 5 according to the modified example 2 further includes a comparison amplifier 120 in addition to the configuration of the amplifier 1 of FIG.
  • the comparison amplifier 120 compares the voltage at the first terminal B of the first and second amplification stages 100-1 and 2 and the second terminal C of the third amplification stage 100-3 with the reference voltage Vref, and based on the comparison result Thus, a voltage is applied to the input terminal A of the third amplification stage 100-3 via the resistor R3.
  • the comparison amplifier 120 is used to suppress fluctuations in the voltage at the first terminal B of the first and second amplification stages 100-1 and 2 and the second terminal C of the third amplification stage 100-3. Thus, distortion of the output signal of the amplifier 5 is suppressed.
  • the amplifiers 2 to 4 shown in FIG. 3 also use a comparison amplifier to compare the voltage of the short-circuited terminal of the amplification stage with the reference voltage Vref, and to compare the voltage based on the comparison result to the second terminal. It is also possible to suppress fluctuations in the DC current flowing through the amplifiers 2 to 4 by performing feedback to one of the amplification stages where C is connected to the ground.
  • FIG. 5 A second embodiment of the present invention will be described with reference to FIG.
  • the circuit shown in FIG. 5 is a circuit having both a frequency conversion function and an amplification function. In this embodiment, it is referred to as an amplifier 6 having a frequency conversion function.
  • the amplifier 6 includes an adding circuit 131 in addition to the amplifier 1 shown in FIG.
  • the adding circuit 131 and the first amplification stage 100-1 are collectively referred to as a frequency conversion circuit 130.
  • the frequency conversion circuit 130 converts the frequency of the input signal using the LO signal (local signal), and outputs the signal Sout to the second amplification stage 100-2.
  • the input signal input to the frequency conversion circuit 130 is first added to the LO signal by the adder circuit 131.
  • the addition signal Sadd is input to the gate terminal of the first transistor M1 included in the first amplification stage 100-1.
  • the first transistor M1 has a function of amplifying the addition signal Sadd and simultaneously converting the square of the input voltage into a current.
  • the output signal of the first amplifier stage 100-1 i.e., the frequency fout of the signal S out output from the frequency conversion stage 130 has a frequency of the sum or difference of f in and f LO. Since the operation of the amplifier 6 after the second amplification stage 100-2 is the same as that of the amplifier 1, the description thereof is omitted.
  • the frequency conversion function can be added to the amplifier 6 by providing the adder circuit 131 in front of the first amplification stage 100-1.
  • the first transistor M1 included in the frequency conversion circuit 130 can share the direct current with the first transistor M1 included in the second and third amplification stages 100-2 and 3 to suppress the power consumption of the amplifier 6.
  • any frequency conversion circuit having a transistor may be used instead of the frequency conversion circuit 130 shown in this embodiment.
  • the power consumption of the amplifier 6 having the frequency conversion function can be suppressed.
  • FIG. 6 A third embodiment of the present invention will be described with reference to FIG.
  • the circuit shown in FIG. 6 is a circuit having both an oscillation function and an amplification function. In this embodiment, it is referred to as an amplifier 7 having an oscillation function.
  • the amplifier 7 has an oscillation circuit 140 instead of the first amplification stage 100-1 of the amplifier 1 of FIG.
  • the oscillation circuit 140 includes transistors M3 and M4 that are cross-coupled to each other, and variable capacitor elements C3 and C3 that are connected to the drain terminals of the transistors M3 and 4 and that are connected in series to each other. ing.
  • the gate terminal of the transistor M3 is connected to the drain terminal of the transistor M4, the drain terminal is connected to one end of the variable capacitor element C3 and one end of the inductor element L3, and the source terminal is connected to the ground.
  • the gate terminal of the transistor M4 is connected to the drain terminal of the transistor M3, the drain terminal is connected to one end of the variable capacitor element C4 and one end of the inductor element L4, and the source terminal is connected to the ground.
  • variable capacitor element C3 has one end connected to the drain terminal of the transistor M3 and the other end connected to the other end of the variable capacitor element C4.
  • the inductor element L3 has one end connected to the drain terminal of the transistor M3 and the other end connected to the other end of the inductor element L4 and Vdd.
  • the oscillation signal that is the output signal of the oscillation circuit 140 is output from the drain terminals of the transistors M3 and M4, and is input to the second amplification stage 100-2 via the capacitor elements C31 and C32. Since the oscillation circuit 140 shown in FIG. 6 outputs an oscillation signal that is a differential signal, the second and third amplification stages 100-2 and 3 of the amplifier 7 have pseudo differential amplification stages shown in FIG. Use.
  • the sum of the direct current flowing through the transistors M3 and M4 and the direct current flowing through the second amplification stage 100-2 is made equal to the direct current flowing through the third amplification stage 100-3.
  • the amplifier 7 having an oscillation function can be provided by providing the oscillation circuit 140 instead of the first amplification stage 100-1.
  • the sum of the direct current flowing through the transistors M3 and 4 and the direct current flowing through the second amplification stage 100-2 is made equal to the direct current flowing through the third amplification stage 100-3, so that the direct current flowing through the oscillation circuit 140 is reached. Since the current and the direct current flowing through the second and third amplification stages 100-2 and 3 can be shared, the power consumption of the amplifier 7 can be suppressed.
  • the oscillation circuit 140 shown in this embodiment may be used instead.
  • the power consumption of the amplifier 7 having the oscillation function can be suppressed.
  • FIG. 7 shows a transmitter 1000 that uses the amplifier 1 as a PA (Power Amplifier).
  • PA Power Amplifier
  • the transmitter 1000 includes a low-pass filter 1001, a mixer 1002, an amplifier 1, a band-pass filter 1003, and an antenna 1004.
  • Transmission data to be transmitted to the transmission partner of the transmitter 1000 is subjected to signal processing such as modulation and DA conversion in a signal processing unit (not shown) and converted to an IF signal.
  • signal processing such as modulation and DA conversion in a signal processing unit (not shown) and converted to an IF signal.
  • the low pass filter 1001 extracts a signal in a desired band from the IF signal, and outputs the extracted IF signal to the mixer 1002 at the subsequent stage.
  • the mixer 1002 multiplies the IF signal and the LO signal to generate an RF signal.
  • the amplifier 1 is the amplifier shown in FIG. 1 and amplifies an RF signal and outputs an amplified signal.
  • the bandpass filter 1003 extracts a signal in a desired band from the amplified signal and transmits a radio signal via the antenna 1004.
  • the power consumption of the transmitter 1000 can be suppressed by using it as the PA of the transmitter 1000.
  • amplifiers 2 to 6 may be used.
  • the amplifier 6 has a frequency conversion function, so that the mixer 1002 of the wireless device 1000 can be omitted, and the circuit area of the wireless device can be reduced.
  • the power consumption of the transmitter can be reduced by using the amplifiers 1 to 6 shown in the first to third embodiments.
  • the amplifiers 1 to 6 shown in the first to third embodiments may be used as the amplification means of the receiver.
  • the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying constituent elements without departing from the scope of the invention in the implementation stage.
  • various inventions can be formed by appropriately combining a plurality of components disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment.
  • constituent elements over different embodiments may be appropriately combined.

Abstract

Provided is an amplifier including: M amplification circuits which are equipped with transistors having source terminals mutually connected and drain terminals connected to a first power potential and amplify an AC signal to obtain an amplified signal; and N-M amplification circuits which are equipped with transistors having drain terminals mutually connected and also connected to the source terminals of the M amplification circuits and source terminals connected to a second power potential and amplify an AC signal to obtain an amplified signal.  The source terminals of the M amplification stages and the drain terminals of the N-M amplification stages are commonly connected.

Description

増幅器amplifier
　本発明は、増幅器に関する。 The present invention relates to an amplifier.
　入力信号に対して大きな出力信号が得られる高出力な増幅器を実現する方法として、増幅段を複数持つものが知られている。例えば、特許文献1に示す増幅器では、電流調整回路に流れる電流を調整することで、増幅段であるトランジスタの増幅動作が飽和しないようにしている。 A method having a plurality of amplification stages is known as a method for realizing a high output amplifier capable of obtaining a large output signal with respect to an input signal. For example, in the amplifier shown in Patent Document 1, the current flowing through the current adjustment circuit is adjusted so that the amplification operation of the transistor that is the amplification stage is not saturated.
特開2003-332864号公報(第1-7頁、第1図）JP 2003-332864 A (page 1-7, Fig. 1)
　上述した増幅器では、増幅段に流れる電流の一部が電流調整回路に流れるため、信号増幅のための電流が無駄になるという問題がある。さらに、増幅段の段数が増えると各増幅段に流れる電流の総量が増えるため、特許文献１に示す増幅器は、増幅段を３つ以上に増やすことが難しいという問題がある。 The above-described amplifier has a problem that a part of the current flowing through the amplification stage flows through the current adjustment circuit, so that the current for signal amplification is wasted. Furthermore, since the total amount of current flowing through each amplification stage increases as the number of amplification stages increases, the amplifier disclosed in Patent Document 1 has a problem that it is difficult to increase the number of amplification stages to three or more.
　本発明は、この問題を解決するためになされたものであり、増幅段数を増やしても消費電力の増加を抑制した増幅器を提供することを目的とする。 The present invention has been made to solve this problem, and an object of the present invention is to provide an amplifier that suppresses an increase in power consumption even when the number of amplification stages is increased.
　上記目的を達成するために、本発明の増幅器は、ソース端子が互いに接続しており、ドレイン端子が第1電源電位に接続しているトランジスタを有し、交流信号を増幅して増幅信号を得るM個の増幅段と、ドレイン端子が前記M個の増幅段のソース端子に接続され、かつ互いに接続しており、ソース端子が第2電源電位に接続しているトランジスタを有し、交流信号を増幅して増幅信号を得るN-M個の増幅段と、を備え、前記M個の増幅段の前記ソース端子と、前記N-M個の増幅段の前記ドレイン端子とは共通接続されていることを特徴とする。 In order to achieve the above object, an amplifier according to the present invention includes a transistor having source terminals connected to each other and a drain terminal connected to a first power supply potential, and amplifies an AC signal to obtain an amplified signal. M amplifier stages and transistors having drain terminals connected to the source terminals of the M amplifier stages and connected to each other, the source terminals connected to the second power supply potential, and an AC signal NM amplification stages that amplify and obtain an amplified signal, wherein the source terminals of the M amplification stages and the drain terminals of the NM amplification stages are connected in common To do.
　本発明によれば、消費電力の増加を抑制した増幅器を提供することができる。 According to the present invention, it is possible to provide an amplifier that suppresses an increase in power consumption.
第1実施形態に係る増幅器1を示す図。1 is a diagram showing an amplifier 1 according to a first embodiment. 増幅段の一例を示す図。The figure which shows an example of an amplification stage. 増幅段の一例を示す図。The figure which shows an example of an amplification stage. 第1実施例に係る増幅器2を示す図。The figure which shows the amplifier 2 which concerns on 1st Example. 第1実施例に係る増幅器3を示す図。1 is a diagram showing an amplifier 3 according to a first embodiment. FIG. 第1実施例に係る増幅器4を示す図。1 is a diagram showing an amplifier 4 according to a first embodiment. FIG. 第1実施例の変形例2に係る増幅器5を示す図。The figure which shows the amplifier 5 which concerns on the modification 2 of 1st Example. 第2実施例に係る増幅器6を示す図。The figure which shows the amplifier 6 which concerns on 2nd Example. 第3実施例に係る増幅器7を示す図。The figure which shows the amplifier 7 which concerns on 3rd Example. 第4実施例に係る送信機1000を示す図。The figure which shows the transmitter 1000 which concerns on 4th Example.
　以下、図面を参照し本発明の実施の形態を説明する。なお、以下の実施形態中では、同一の番号を付した部分については同様の動作を行うものとし、重ねての説明を省略する。 Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that, in the following embodiments, the same numbered parts are assumed to perform the same operation, and repeated description is omitted.
　(第1実施例)
　本発明の第1実施例に係る増幅器は、交流信号を増幅して増幅信号を得るM個の増幅段と、交流信号を増幅して増幅信号を得るN-M個の増幅段と、を備える。M個の増幅段は、ソース端子が互いに接続しており、ドレイン端子が第1電源電位に接続しているトランジスタを有する。N-M個の増幅段は、ドレイン端子が該M個の増幅段のソース端子に接続され、かつ互いに接続しており、ソース端子が第2電源電位に接続しているトランジスタを有する。かつ、M個の増幅段のソース端子と、N-M個の増幅段のドレイン端子とは共通接続されている。このため、M個の増幅段に流れる直流電流の総和は、N-M個の増幅段に流れる直流電流の総和に等しい。また、M個及びN-M個の増幅段のうち、第k(kは、0<k<Nの整数)増幅段のドレイン端子は、第k+1増幅段のゲート端子に接続されており、第k増幅段で増幅した増幅信号を第k+1増幅段が増幅する。 (First Example)
The amplifier according to the first embodiment of the present invention includes M amplification stages that amplify an AC signal to obtain an amplification signal, and NM amplification stages that amplify the AC signal to obtain an amplification signal. The M amplification stages have transistors whose source terminals are connected to each other and whose drain terminals are connected to the first power supply potential. The NM amplifier stages have transistors having drain terminals connected to the source terminals of the M amplifier stages and connected to each other, and the source terminals connected to the second power supply potential. The source terminals of the M amplification stages and the drain terminals of the NM amplification stages are connected in common. For this reason, the sum total of direct currents flowing through the M amplification stages is equal to the sum of direct currents flowing through the NM amplification stages. Further, of the M and NM amplification stages, the drain terminal of the kth amplification stage (k is an integer of 0 <k <N) is connected to the gate terminal of the (k + 1) th amplification stage, and The k + 1th amplification stage amplifies the amplified signal amplified by the k amplification stage.
　以下、単に増幅段と称する場合は、M個及びN-M個の増幅段全てを指す。 Hereinafter, when simply referred to as an amplification stage, it refers to all M and NM amplification stages.
(N=3,M=2の例1)
　図1はN=3,M=2の場合における本発明の第1実施例に係る増幅器1を示す図である。図1の増幅器1は、第1～3増幅段100-1～100-3を有している。本例では、第1,2増幅段100-1,2がM(2)個の増幅段に相当し、第3増幅段100-3がN-M(3-2=1)個の増幅段に相当する。 (Example 1 where N = 3, M = 2)
FIG. 1 is a diagram showing an amplifier 1 according to a first embodiment of the present invention when N = 3 and M = 2. The amplifier 1 of FIG. 1 has first to third amplification stages 100-1 to 100-3. In this example, the first and second amplification stages 100-1 and 2 correspond to M (2) amplification stages, and the third amplification stage 100-3 corresponds to NM (3-2 = 1) amplification stages. To do.
　増幅段は、交流信号が入力される入力端子Aと、第1又は第2電源電位の何れかに接続する第1,2端子B,Cと、増幅信号を出力する出力端子Dを有している。 The amplification stage has an input terminal A to which an AC signal is input, first and second terminals B and C connected to either the first or second power supply potential, and an output terminal D for outputting the amplified signal. Yes.
　第1増幅段100-1の入力端子Aは、増幅器1の入力端子となる。第1増幅段100-1の第1端子Bは、後述する第2増幅段100-2の第1端子B及び第3増幅段100-3の第2端子Cに接続している。第1増幅段100-1の第2端子Cは、第1電源電位に接続している。以下、第1電源電位はVddであり、第2電源電位はグランドであるものとする。 The input terminal A of the first amplification stage 100-1 becomes the input terminal of the amplifier 1. The first terminal B of the first amplification stage 100-1 is connected to a first terminal B of the second amplification stage 100-2 and a second terminal C of the third amplification stage 100-3 which will be described later. The second terminal C of the first amplification stage 100-1 is connected to the first power supply potential. Hereinafter, it is assumed that the first power supply potential is Vdd and the second power supply potential is ground.
　第2増幅段100-2の入力端子Aは、第1増幅段100-1の出力端子Dに接続されている。第2増幅段100-2の第1端子Bは、第1増幅段100-1の第1端子B及び第3増幅段100-3の第2端子Cに接続している。第2増幅段100-2の第2端子Cは、Vddに接続している。 The input terminal A of the second amplification stage 100-2 is connected to the output terminal D of the first amplification stage 100-1. The first terminal B of the second amplification stage 100-2 is connected to the first terminal B of the first amplification stage 100-1 and the second terminal C of the third amplification stage 100-3. The second terminal C of the second amplification stage 100-2 is connected to Vdd.
　第3増幅段100-3の入力端子Aは、第2増幅段100-2の出力端子Dに接続されている。第3増幅段100-3の第1端子Bは、グランドに接続している。第3増幅段100-3の第2端子Cは、第1,2増幅段100-1,2の第1端子Bに接続している。第3増幅段100-3の出力端子Dは、増幅器1の出力端子となる。 The input terminal A of the third amplification stage 100-3 is connected to the output terminal D of the second amplification stage 100-2. The first terminal B of the third amplification stage 100-3 is connected to the ground. The second terminal C of the third amplification stage 100-3 is connected to the first terminal B of the first and second amplification stages 100-1, 2. The output terminal D of the third amplification stage 100-3 becomes the output terminal of the amplifier 1.
　第1,2増幅段100-1,2は、直流電流で考えると(直流的に)並列に接続している。第1,2増幅段をまとめて第1増幅群10と称する。また、第3増幅段100-3は、第1増幅群10と直流電流で考えると(直流的に)直列に接続している。第3増幅段100-3を第2増幅群20と称する。第1増幅群10と第2増幅群20とを直列に接続することで、第1増幅群10の各増幅段に流れる直流電流の総和が、第2増幅群20の各増幅段に流れる直流電流の総和に等しくなる。 The first and second amplification stages 100-1 and 2 are connected in parallel (in terms of DC) in terms of DC current. The first and second amplification stages are collectively referred to as a first amplification group 10. The third amplification stage 100-3 is connected in series with the first amplification group 10 in terms of direct current (in terms of direct current). The third amplification stage 100-3 is referred to as a second amplification group 20. By connecting the first amplification group 10 and the second amplification group 20 in series, the sum of the direct currents flowing through each amplification stage of the first amplification group 10 becomes the direct current flowing through each amplification stage of the second amplification group 20. Is equal to the sum of
　次に、図2(a)を用いて第1増幅段100-1の一例を説明する。なお、第2,3増幅段100-2,3も同様の構成である。 Next, an example of the first amplification stage 100-1 will be described with reference to FIG. The second and third amplification stages 100-2 and 3 have the same configuration.
　第1増幅段100-1は、ゲート端子が入力端子Aに接続され、ドレイン端子がインダクタ素子Lを介して第2端子Cに接続され、ソース端子が第1端子Bに接続された第1トランジスタM1を有する増幅回路110を備えている。出力端子Dは、インダクタ素子Lと第1トランジスタM1のドレイン端子との間に、キャパシタ素子C1を介して接続される。第1増幅段100-1は一端が入力端子A及び第1トランジスタM1のゲート端子に接続され、他端にバイアス電圧Vbiasが印加された抵抗Rを有している。第1増幅段100-1は、一端が第1端子B及び第1トランジスタM1のソース端子に接続され、他端が接地されたキャパシタ素子C2を有している。 The first amplification stage 100-1 includes a first transistor having a gate terminal connected to the input terminal A, a drain terminal connected to the second terminal C via the inductor element L, and a source terminal connected to the first terminal B. An amplifier circuit 110 having M1 is provided. The output terminal D is connected between the inductor element L and the drain terminal of the first transistor M1 via the capacitor element C1. The first amplification stage 100-1 has one end connected to the input terminal A and the gate terminal of the first transistor M1, and the other end having a resistor R to which a bias voltage Vbias is applied. The first amplification stage 100-1 has a capacitor element C2 having one end connected to the first terminal B and the source terminal of the first transistor M1, and the other end grounded.
　第1,2増幅段100-1,2の第1端子Bは、直流的に短絡しており、かつキャパシタ素子C2を介してグランドに接続することで交流的に接地している。第3増幅段100-3の第2端子Cは、第1,2増幅段100-1,2の第1端子Bと接続することで交流的に接地している。 The first terminals B of the first and second amplification stages 100-1 and 2 are short-circuited in a direct current and are grounded in an alternating current by being connected to the ground via the capacitor element C2. The second terminal C of the third amplifying stage 100-3 is connected to the first terminal B of the first and second amplifying stages 100-1 and 2 to be grounded in an AC manner.
　続いて、図2(b)を用いて第1増幅段100-1の別の例を説明する。図2(b)の第1増幅段100-1は、第1トランジスタM1の他に第2トランジスタM2を有し、差動信号である交流信号を増幅する擬似差動増幅段である。なお、第2,3増幅段100-2,3も同様の構成である。 Subsequently, another example of the first amplification stage 100-1 will be described with reference to FIG. The first amplification stage 100-1 in FIG. 2B is a pseudo-differential amplification stage that includes the second transistor M2 in addition to the first transistor M1, and amplifies an AC signal that is a differential signal. The second and third amplification stages 100-2 and 3 have the same configuration.
　第1増幅段100-1は、ゲート端子が入力端子A1に接続され、ドレイン端子がインダクタ素子L1を介して第2端子Cに接続され、ソース端子が第1端子Bに接続された第1トランジスタM1と、ゲート端子が入力端子A2に接続され、ドレイン端子がインダクタ素子L2を介して第2端子Cに接続され、ソース端子が第1端子Bに接続された第2トランジスタM2と、を有する増幅回路111を備えている。出力端子D1は、インダクタ素子L1と第1トランジスタM1のドレイン端子との間に、キャパシタC11を介して接続される。出力端子D2は、インダクタ素子L2と第2トランジスタM2のドレイン端子との間に、キャパシタC12を介して接続される。第1増幅段100-1は、一端が入力端子A1及び第1トランジスタM1のゲート端子に接続され、他端にバイアス電圧Vbiasが印加された抵抗R1と、一端が入力端子A2及び第2トランジスタM2のゲート端子に接続され、他端にバイアス電圧Vbiasが印加された抵抗R2と、を有している。 The first amplification stage 100-1 includes a first transistor having a gate terminal connected to the input terminal A1, a drain terminal connected to the second terminal C via the inductor element L1, and a source terminal connected to the first terminal B. An amplification having M1, a second transistor M2 having a gate terminal connected to the input terminal A2, a drain terminal connected to the second terminal C via the inductor element L2, and a source terminal connected to the first terminal B. A circuit 111 is provided. The output terminal D1 is connected between the inductor element L1 and the drain terminal of the first transistor M1 via the capacitor C11. The output terminal D2 is connected via the capacitor C12 between the inductor element L2 and the drain terminal of the second transistor M2. The first amplification stage 100-1 has one end connected to the input terminal A1 and the gate terminal of the first transistor M1, the other end connected to the resistor R1 to which the bias voltage Vbias is applied, and one end connected to the input terminal A2 and the second transistor M2. And a resistor R2 to which the bias voltage Vbias is applied at the other end.
　第1増幅段100-1は、擬似差動増幅段であるため、入力端子A1,A2で図1の入力端子Aを、出力端子D1,D2で図1の出力端子Dを構成している。 Since the first amplification stage 100-1 is a pseudo differential amplification stage, the input terminals A1 and A2 constitute the input terminal A in FIG. 1, and the output terminals D1 and D2 constitute the output terminal D in FIG.
　第1,2増幅段100-1,2の第1端子Bは、第1,2トランジスタM1,2の各ソース端子を接続することで交流的に接地している。第3増幅段100-3の第2端子Cは、第1,2増幅段100-1,2の第1端子Bと接続することで交流的に接地している。 The first terminals B of the first and second amplification stages 100-1 and 2 are grounded in an AC manner by connecting the source terminals of the first and second transistors M1 and M2. The second terminal C of the third amplifying stage 100-3 is connected to the first terminal B of the first and second amplifying stages 100-1 and 2 to be grounded in an AC manner.
　図1に戻る。増幅段に流れる直流電流の大きさは、増幅段が有する第1トランジスタM1のサイズと、増幅段の入力端子Aと第1端子Bとの間の電位差、即ち第1トランジスタM1のゲート‐ソース間電圧によって決まる。増幅段が有する第1トランジスタM1のサイズとゲート‐ソース間電圧を調整することで、第1,2増幅段100-1,2に流れる直流電流の大きさ、及び第3増幅段100-3に流れる直流電流の大きさを調整することができる。 Return to Figure 1. The magnitude of the direct current flowing through the amplification stage is the size of the first transistor M1 of the amplification stage and the potential difference between the input terminal A and the first terminal B of the amplification stage, that is, between the gate and source of the first transistor M1. It depends on the voltage. By adjusting the size of the first transistor M1 and the gate-source voltage of the amplification stage, the magnitude of the direct current flowing in the first and second amplification stages 100-1 and 1002, and the third amplification stage 100-3 The magnitude of the flowing direct current can be adjusted.
　図1を用いて増幅器1の動作について説明する。まず交流信号の流れについて説明する。 The operation of amplifier 1 will be described with reference to FIG. First, the flow of an AC signal will be described.
　入力信号は、第1増幅段100-1の入力端子Aに入力される。入力信号は、第1増幅段100-1で増幅され第1増幅信号に変換される。第1増幅信号は、第1増幅段100-1の出力端子Dから出力され、第2増幅段100-2の入力端子Aに入力される。第1増幅段は、第2増幅段100-2で増幅され第2増幅信号に変換される。第2増幅信号は、第2増幅段100-2の出力端子Dから出力され、第3増幅段100-3の入力端子Aに入力される。第2増幅信号は、第3増幅段100-3で増幅され第3増幅信号に変換される。第3増幅信号は、第3増幅段100-3の出力端子Dから増幅器1の出力信号として出力される。本実施例では、入力信号、第1～3増幅信号は、例えば振幅又は位相に信号情報を有する交流信号とする。第1,2増幅段100-1,2の第1端子Bは交流的に接地しているため、第1端子Bから交流信号が出力されることはない。 The input signal is input to the input terminal A of the first amplification stage 100-1. The input signal is amplified by the first amplification stage 100-1 and converted into a first amplified signal. The first amplified signal is output from the output terminal D of the first amplification stage 100-1 and input to the input terminal A of the second amplification stage 100-2. The first amplification stage is amplified by the second amplification stage 100-2 and converted into a second amplified signal. The second amplified signal is output from the output terminal D of the second amplification stage 100-2 and input to the input terminal A of the third amplification stage 100-3. The second amplified signal is amplified by the third amplification stage 100-3 and converted into a third amplified signal. The third amplified signal is output as the output signal of the amplifier 1 from the output terminal D of the third amplification stage 100-3. In this embodiment, the input signal and the first to third amplified signals are AC signals having signal information in amplitude or phase, for example. Since the first terminals B of the first and second amplification stages 100-1 and 2 are grounded in an AC manner, no AC signal is output from the first terminal B.
　次に直流電流の流れについて説明する。増幅器1の場合、第1電源電位であるVddから第2電源電位であるグランドに直流電流が流れる。この直流電流は、増幅段が交流信号を増幅するために必要な電流である。 Next, the flow of direct current will be described. In the case of the amplifier 1, a direct current flows from Vdd that is the first power supply potential to the ground that is the second power supply potential. This DC current is a current necessary for the amplification stage to amplify the AC signal.
　直流電流は、Vddから第1,2増幅段100-1,2の第2端子Cにそれぞれ入力される。第1,2増幅段100-1,2に入力された各直流電流は、第1,2増幅段100-1,2の各第1端子Bから出力され合成されて、第3増幅段100-3に入力される。即ち第1,2増幅段100-1,2に流れる直流電流の総和に等しい直流電流が第3増幅段100-3に流れる。第3増幅段100-3に入力された直流電流は、第3増幅段の第1端子Bからグランドに出力される。 DC current is input from Vdd to the second terminals C of the first and second amplification stages 100-1 and 2, respectively. The direct currents input to the first and second amplification stages 100-1 and 2 are output from the first terminals B of the first and second amplification stages 100-1 and 2, and are combined to form the third amplification stage 100- Entered in 3. That is, a direct current equal to the sum of direct currents flowing through the first and second amplification stages 100-1 and 2 flows through the third amplification stage 100-3. The direct current input to the third amplification stage 100-3 is output from the first terminal B of the third amplification stage to the ground.
(N=3,M=2の例2)
　図3(a)に、N=3,M=2の場合における本実施例に係る別の増幅器2を示す。 (Example 2 where N = 3, M = 2)
FIG. 3 (a) shows another amplifier 2 according to the present embodiment when N = 3 and M = 2.
増幅器2の第1増幅段100-1の第1端子Bは、第2増幅段100-2の第2端子C及び第3増幅段100-3の第1端子Bに接続している。第2増幅段100-2の第1端子Bはグランドに、第2端子Cは第1,3増幅段100-1,3の各第1端子Bに接続している。第3増幅段100-3の第1端子Bは第1増幅段100-1の第1端子B及び第2増幅段100-2の第2端子Cに、第2端子CはVddに接続している。 The first terminal B of the first amplification stage 100-1 of the amplifier 2 is connected to the second terminal C of the second amplification stage 100-2 and the first terminal B of the third amplification stage 100-3. The first terminal B of the second amplification stage 100-2 is connected to the ground, and the second terminal C is connected to the first terminals B of the first and third amplification stages 100-1 and 3. The first terminal B of the third amplification stage 100-3 is connected to the first terminal B of the first amplification stage 100-1 and the second terminal C of the second amplification stage 100-2, and the second terminal C is connected to Vdd. Yes.
増幅器2は、第1,3増幅段100-1,3が直流的に並列に接続しており、第1,3増幅段100-1,3と第2増幅段100-2とが直流的に直列に接続している点を除き図1の増幅器1と同じ構成となっている。図3(a)の増幅器2の場合、第1,3増幅段100-1,3をまとめて第1増幅群10と、第2増幅段100-2を第2増幅群20とする。 In the amplifier 2, the first and third amplification stages 100-1 and 100-3 are connected in parallel in a direct current, and the first and third amplification stages 100-1, 3 and the second amplification stage 100-2 are connected in a direct current. The configuration is the same as that of the amplifier 1 in FIG. 1 except that the amplifiers are connected in series. In the case of the amplifier 2 in FIG. 3A, the first and third amplification stages 100-1 and 3 are collectively referred to as a first amplification group 10, and the second amplification stage 100-2 is defined as a second amplification group 20.
　増幅器2の交流信号の流れは増幅器1と同じであり、第1増幅段100-1、第2増幅段100-2、第3増幅段100-3の順に流れる。直流電流は、Vddから第1,3増幅段100-1,3の第2端子Cにそれぞれ入力される。第1,3増幅段100-1,3に入力された各直流電流は、第1,3増幅段100-1,3の各第1端子Bから出力されて合成された後、第2増幅段100-2に入力される。すなわち、第1,3増幅段100-1,3に流れる電流の総和に等しい直流電流が第2増幅段100-2に流れる。第2増幅段100-2に入力された直流電流は、第2増幅段の第1端子Bからグランドに出力される。 The flow of the AC signal of the amplifier 2 is the same as that of the amplifier 1, and flows in the order of the first amplification stage 100-1, the second amplification stage 100-2, and the third amplification stage 100-3. The direct current is input from Vdd to the second terminals C of the first and third amplification stages 100-1 and 3, respectively. The direct currents input to the first and third amplification stages 100-1 and 3 are output from the first terminals B of the first and third amplification stages 100-1 and 3, and then combined, and then the second amplification stage. Input to 100-2. That is, a direct current equal to the sum of the currents flowing through the first and third amplification stages 100-1 and 3 flows through the second amplification stage 100-2. The direct current input to the second amplification stage 100-2 is output from the first terminal B of the second amplification stage to the ground.
　各増幅群に含まれる増幅段を互いに直流的に並列に接続し、各増幅群を直流的に直列に接続すれば、第1増幅群10に流れる直流電流の総和と、第2増幅群20に流れる直流電流の総和とが等しくなる。 If the amplification stages included in each amplification group are connected in parallel with each other in DC, and each amplification group is connected in series with DC, the sum of the direct current flowing through the first amplification group 10 and the second amplification group 20 The sum of the flowing DC currents is equal.
(N=3,M=1の例)
　 次に、図3(b)にN=3,M=1の場合の例を示す。本例では、第1電源電位はグランドであり、第2電源電位はVddである。図3(b)に示す増幅器3の第1,2増幅段100-1,2の第1端子Bは、第3増幅段100-2,3の第2端子Cに接続している。第1,2増幅段100-1,2の第2端子Cは、グランドに接続している。第3増幅段100-3の第2端子Cは第1,2増幅段100-1,2の第1端子Bに接続している。第3増幅段100-3の第1端子BはVddに接続している。 (Example of N = 3, M = 1)
Next, FIG. 3 (b) shows an example in the case of N = 3 and M = 1. In this example, the first power supply potential is ground, and the second power supply potential is Vdd. The first terminals B of the first and second amplification stages 100-1 and 2 of the amplifier 3 shown in FIG. 3B are connected to the second terminals C of the third amplification stages 100-2 and 3. The second terminals C of the first and second amplification stages 100-1 and 2 are connected to the ground. The second terminal C of the third amplification stage 100-3 is connected to the first terminal B of the first and second amplification stages 100-1, 2. The first terminal B of the third amplification stage 100-3 is connected to Vdd.
　増幅器3は、第1,2増幅段100-1,2が直流的に並列に接続しており、第1,2増幅段100-1,2と第3増幅段100-3とが直流的に直列に接続している。図3(b)の増幅器3の場合、第1,2増幅段100-1,2を第1増幅群10、第3増幅段100-3を第2増幅群20とする。 In the amplifier 3, the first and second amplification stages 100-1 and 2 are connected in parallel in a direct current manner, and the first and second amplification stages 100-1 and 100-3 are connected in a direct current manner. Connected in series. In the case of the amplifier 3 in FIG. 3B, the first and second amplification stages 100-1 and 100-2 are defined as the first amplification group 10, and the third amplification stage 100-3 is defined as the second amplification group 20.
　増幅器3の交流信号の流れは増幅器1と同じであり、第1増幅段100-1、第2増幅段100-2、第3増幅段100-3の順に流れる。直流電流は、第3増幅段100-3に流れ、その後第1,2増幅段100-1,2に流れる。第1,2増幅段100-1,2に流れる直流電流と、第3増幅段100-3に流れる直流電流の総和とが等しくなる。 The flow of the AC signal of the amplifier 3 is the same as that of the amplifier 1, and flows in the order of the first amplification stage 100-1, the second amplification stage 100-2, and the third amplification stage 100-3. The direct current flows to the third amplification stage 100-3 and then to the first and second amplification stages 100-1 and 2. The direct current flowing through the first and second amplification stages 100-1 and 2 is equal to the sum of the direct current flowing through the third amplification stage 100-3.
(N=4,M=2の例)
　図3(c)にN=4,M=2の場合の例を示す。図3(c)に示す増幅器4の第1,2増幅段100-1,2の第1端子Bは、第3,4増幅段100-3,4の第2端子Cと、第2端子CはVddと接続している。第3,4増幅段100-3,4の第1端子Bはグランドと接続している。第4増幅段100-4は、第1～3増幅段100-1～3と同様の構成であり、例えば図2に示す段構成である。 (Example of N = 4, M = 2)
FIG. 3 (c) shows an example when N = 4 and M = 2. The first terminal B of the first and second amplification stages 100-1 and 2 of the amplifier 4 shown in FIG. 3 (c) is the second terminal C of the third and fourth amplification stages 100-3,4 and the second terminal C. Is connected to Vdd. The first terminals B of the third and fourth amplification stages 100-3,4 are connected to the ground. The fourth amplification stage 100-4 has the same configuration as the first to third amplification stages 100-1 to 100-3, for example, the stage configuration shown in FIG.
　増幅器4は、第1,2増幅段100-1,2が直流的に並列に接続している。第1,2増幅段100-1,2を第1増幅群10とする。第3,4増幅段100-3,4が直流的に並列に接続している。第3,4増幅段100-3,4を第2増幅群20とする。第1,2増幅群10,20が直流的に直列に接続している。 In the amplifier 4, the first and second amplification stages 100-1 and 2 are connected in parallel in a direct current manner. The first and second amplification stages 100-1 and 2 are defined as a first amplification group 10. The third and fourth amplification stages 100-3,4 are connected in parallel in a direct current manner. The third and fourth amplification stages 100-3 and 4 are defined as a second amplification group 20. The first and second amplification groups 10 and 20 are connected in series in a direct current manner.
　増幅器4に入力される交流信号の流れについて説明する。第1増幅段100-1の入力端子Aに入力された交流信号は、第2増幅段100-2、第3増幅段100-3、第4増幅段100-4の順に流れ、各増幅段で増幅され、第4増幅段100-4の出力端子Dから出力される。 The flow of the AC signal input to the amplifier 4 will be described. The AC signal input to the input terminal A of the first amplification stage 100-1 flows in the order of the second amplification stage 100-2, the third amplification stage 100-3, and the fourth amplification stage 100-4. Amplified and output from the output terminal D of the fourth amplification stage 100-4.
　次に、増幅器4に流れる直流電流について説明する。Vddから第1,2増幅段100-1,2に流れる直流電流は、第3,4増幅段100-3,4に流れこみ、グランドへと流れる。第1,2増幅段100-1,2に流れる直流電流の総和は、第3,4増幅段100-3,4に流れる直流電流の総和と等しい。 Next, the direct current flowing through the amplifier 4 will be described. The direct current flowing from Vdd to the first and second amplification stages 100-1 and 2 flows into the third and fourth amplification stages 100-3,4 and flows to the ground. The sum of direct currents flowing through the first and second amplification stages 100-1 and 2 is equal to the sum of direct currents flowing through the third and third amplification stages 100-3,4.
　以上のように、第1実施形態に係る増幅器では、第1増幅群に含まれるM個の増幅段(Mは、0<M<Nの整数。図1の場合はM=2。) に流れる直流電流をN-M個の増幅段 (Nは3以上の整数。図1の場合はN=3。) に流すことで、増幅段に流れる直流電流を効率よく利用することができる。また、増幅段を3つ以上に増やすことが可能であり、高利得かつ高効率の増幅器を提供することができる。 As described above, in the amplifier according to the first embodiment, M amplifier stages included in the first amplification group (M is an integer satisfying 0 <M <N. In the case of FIG. 1, M = 2). Direct current flowing through the amplification stage can be efficiently utilized by flowing direct current through NM amplification stages (N is an integer of 3 or more. In the case of FIG. 1, N = 3). Further, the number of amplification stages can be increased to three or more, and a high gain and high efficiency amplifier can be provided.
(変形例1)
　本実施例のように入力された交流信号を複数の増幅段100-1～nで増幅する場合、増幅段が有する第1トランジスタに流れる直流電流が大きくなるほど出力できる交流信号の電力が大きくなる。従って、増幅器の出力電力を大きくするためには、前段の増幅段より後段の増幅段の第1トランジスタに流れる電流を大きくすればよい。すなわち、第k増幅段100-k(kは1≦k<nの整数)に流れる直流電流Ikと第k+1増幅段100-k+1に流れる直流電流Ik+1とがIk≦Ik+1となればよい。 (Modification 1)
When the input AC signal is amplified by the plurality of amplification stages 100-1 to 100-n as in this embodiment, the power of the AC signal that can be output increases as the direct current flowing through the first transistor of the amplification stage increases. Therefore, in order to increase the output power of the amplifier, it is only necessary to increase the current flowing through the first transistor in the subsequent amplification stage than in the previous amplification stage. That is, the k amplification stage 100-k (k is 1 ≦ k <integer n) and DC current I k + 1 flowing through the direct current Ik and the k + 1 amplifier stage 100-k + 1 flowing to the I k ≦ I k + 1 is sufficient.
　直流電流Ikは、第1トランジスタのサイズW kと入力端子Aと第1端子Bとの間の電位差、即ち第1トランジスタM1のゲート‐ソース間電圧Vgs-kによって決まる。従って、増幅器の出力電力を大きくするためには、Ik≦Ik+1となるようにW kとVgs-kを設計すればいい。 The direct current I k is determined by the size W k of the first transistor and the potential difference between the input terminal A and the first terminal B, that is, the gate-source voltage V gs-k of the first transistor M1. Therefore, in order to increase the output power of the amplifier, W k and V gs-k may be designed so that I k ≦ I k + 1 .
　また、図1に示す増幅器1のように、M>N-Mであり、かつM個の増幅段が第1～M増幅段からなり、N-M個の増幅段が第M+1～N増幅段からなる場合、N-M個の増幅段の第1トランジスタの各サイズW1s(sは1≦s≦N-Mの整数)がM個の増幅段の第1トランジスタの各サイズW2t(tは1≦t≦Mの整数)より大きく(W1s>W2t)する。これにより、M>N-Mであるため第1増幅群10に含まれるM個の増幅段に流れる直流電流の総和と第2増幅群20に含まれるN-M個の増幅段に流れる直流電流の総和を等しくすることができる。 Further, as in the amplifier 1 shown in FIG. 1, M> NM, M amplification stages are composed of the first to M amplification stages, and NM amplification stages are composed of the M + 1 to N amplification stages. Each size W1s of the first transistors of the NM amplification stages (s is an integer of 1 ≦ s ≦ NM) is each size W2t of the first transistors of the M amplification stages (t is an integer of 1 ≦ t ≦ M) ) Larger than (W1s> W2t). Thus, since M> NM, the sum of the DC currents flowing through the M amplification stages included in the first amplification group 10 is equal to the sum of the DC currents flowing through the NM amplification stages included in the second amplification group 20. can do.
　逆に、W1s<W2tだった場合、M個の増幅段にそれぞれ流れる直流電流itがN-M個の増幅段にそれぞれ流れる直流電流isより大きくなる。このときM個の増幅段に流れる直流電流の総和Σt=1MitがN-M個の増幅段に流れる直流電流の総和Σs=1 N-Misより大きくなってしまうことは、it>is,M>N-Mから明らかである。 Conversely, if it was W1s <W2T, DC current i t flowing respectively to the M of the amplification stage is larger than the DC current i s flows respectively NM number of amplification stages. At this time, the sum Σt = 1Mit of the DC currents flowing in the M amplification stages becomes larger than the sum Σ s = 1 NM i s of the DC currents flowing in the NM amplification stages, i t > i s , M > It is clear from NM.
　上述したように、本変形例の増幅器1は、増幅段の第1トランジスタのサイズをW1s>W2t(sは1≦s≦N-M整数、tは1≦t≦Mの整数)とする。また第k増幅段100-kの第1トランジスタのゲート端子とソース端子との間の電圧差Vgkを、Vgk<Vgk+1を満たすようにする。これにより、増幅器の出力電力を大きくすることができる。 As described above, in the amplifier 1 of the present modification, the size of the first transistor in the amplification stage is W1s> W2t (s is an integer of 1 ≦ s ≦ N−M, and t is an integer of 1 ≦ t ≦ M). Further, the voltage difference Vgk between the gate terminal and the source terminal of the first transistor of the k-th amplification stage 100-k is set to satisfy Vgk <Vgk + 1. Thereby, the output power of the amplifier can be increased.
　図1に示す増幅器1が有する第1～3増幅段100-1～3の第1トランジスタM1に流れる直流電流は、I1<I2<I3かつI1+I2=I3を満たす。そのため、第1～3増幅段100-1～3から出力される交流信号の電力P1～P3もP1<P2<P3を満たす。交流信号は、第1増幅段100-1、第2増幅段100-2、第3増幅段100-3の順に入力される。交流信号は、増幅段に入力されるに従って順に大きくなっていく。 The direct current flowing through the first transistors M1 of the first to third amplification stages 100-1 to 100-3 included in the amplifier 1 shown in FIG. 1 satisfies I 1 <I 2 <I 3 and I 1 + I 2 = I 3 . Therefore, the powers P 1 to P 3 of the AC signals output from the first to third amplification stages 100-1 to 100-3 also satisfy P 1 <P 2 <P 3 . The AC signal is input in the order of the first amplification stage 100-1, the second amplification stage 100-2, and the third amplification stage 100-3. The AC signal increases in order as it is input to the amplification stage.
(変形例2)
　図4を用いて第1実施例の変形例2を説明する。変形例2に係る増幅器5は、図1の増幅器1の構成に加え比較アンプ120をさらに有している。 (Modification 2)
A second modification of the first embodiment will be described with reference to FIG. The amplifier 5 according to the modified example 2 further includes a comparison amplifier 120 in addition to the configuration of the amplifier 1 of FIG.
　比較アンプ120は、第1,2増幅段100-1,2の第1端子B及び第3増幅段100-3の第2端子Cの電圧と、参照電圧Vrefとを比較し、比較結果に基づいて、第3増幅段100-3の入力端子Aに抵抗R3を介して電圧を印加する。 The comparison amplifier 120 compares the voltage at the first terminal B of the first and second amplification stages 100-1 and 2 and the second terminal C of the third amplification stage 100-3 with the reference voltage Vref, and based on the comparison result Thus, a voltage is applied to the input terminal A of the third amplification stage 100-3 via the resistor R3.
　増幅器5に入力される交流信号の電力が変動すると、第1,2増幅段100-1,2の第1端子B及び第3増幅段100-3の第2端子Cの電圧も変動してしまう。この変動により増幅器5から出力される信号が歪んでしまう。そこで、本変形例では、比較アンプ120を用い、第1,2増幅段100-1,2の第1端子B及び第3増幅段100-3の第2端子Cの電圧の変動を抑制することで、増幅器5の出力信号の歪みを抑制している。 When the power of the AC signal input to the amplifier 5 fluctuates, the voltages at the first terminal B of the first and second amplification stages 100-1 and 2 and the second terminal C of the third amplification stage 100-3 also fluctuate. . Due to this fluctuation, the signal output from the amplifier 5 is distorted. Therefore, in this modification, the comparison amplifier 120 is used to suppress fluctuations in the voltage at the first terminal B of the first and second amplification stages 100-1 and 2 and the second terminal C of the third amplification stage 100-3. Thus, distortion of the output signal of the amplifier 5 is suppressed.
　なお、図3に示す増幅器2～4も同様に比較アンプを用いて増幅段の交流的に短絡している端子の電圧と参照電圧Vrefとを比較し、比較結果に基づいた電圧を第2端子Cがグランドに接続される増幅段のいずれかにフィードバックを行うことで、増幅器2～4に流れる直流電流の変動を抑制することも可能である。 Similarly, the amplifiers 2 to 4 shown in FIG. 3 also use a comparison amplifier to compare the voltage of the short-circuited terminal of the amplification stage with the reference voltage Vref, and to compare the voltage based on the comparison result to the second terminal. It is also possible to suppress fluctuations in the DC current flowing through the amplifiers 2 to 4 by performing feedback to one of the amplification stages where C is connected to the ground.
(第2実施例)
　図5を用いて本発明の第2実施例を説明する。図5に示す回路は、周波数変換機能と増幅機能を併せ持つ回路である。本実施例では、周波数変換機能を有する増幅器6と称する。 (Second embodiment)
A second embodiment of the present invention will be described with reference to FIG. The circuit shown in FIG. 5 is a circuit having both a frequency conversion function and an amplification function. In this embodiment, it is referred to as an amplifier 6 having a frequency conversion function.
　増幅器6は、図1に示す増幅器1に加え、加算回路131有している。加算回路131と第1増幅段100-1をあわせて周波数変換回路130と呼ぶ。周波数変換回路130は、入力信号の周波数を、LO信号(ローカル信号)を用いて変換し、信号Soutを第2増幅段100-2へ出力する。 The amplifier 6 includes an adding circuit 131 in addition to the amplifier 1 shown in FIG. The adding circuit 131 and the first amplification stage 100-1 are collectively referred to as a frequency conversion circuit 130. The frequency conversion circuit 130 converts the frequency of the input signal using the LO signal (local signal), and outputs the signal Sout to the second amplification stage 100-2.
　周波数変換回路130に入力された入力信号は、まず加算回路131にてLO信号と足しあわされる。入力信号とLO信号とを加算した加算信号Saddの周波数faddは、入力信号の周波数をfin、LO信号の周波数をfloとすると、fadd=fin±floを満たす。加算信号Saddは、第1増幅段100-1が有する第1トランジスタM1のゲート端子に入力される。第1トランジスタM1は、加算信号Saddを増幅するのと同時に、入力電圧の二乗を電流に変換する機能を持っている。第1増幅段100-1の出力信号、即ち周波数変換段130から出力される信号Soutの周波数foutは、finとfLOの和又は差の周波数を有する。第2増幅段100-2以降の増幅器6の動作は、増幅器1と同じであるため説明を省略する。 The input signal input to the frequency conversion circuit 130 is first added to the LO signal by the adder circuit 131. Frequency f the add of the sum of the input signal and the LO signal addition signal S the add is the frequency of the input signal f in, and the frequency of the LO signal and f lo, satisfy f add = f in ± f lo . The addition signal Sadd is input to the gate terminal of the first transistor M1 included in the first amplification stage 100-1. The first transistor M1 has a function of amplifying the addition signal Sadd and simultaneously converting the square of the input voltage into a current. The output signal of the first amplifier stage 100-1, i.e., the frequency fout of the signal S out output from the frequency conversion stage 130 has a frequency of the sum or difference of f in and f LO. Since the operation of the amplifier 6 after the second amplification stage 100-2 is the same as that of the amplifier 1, the description thereof is omitted.
　以上のように、第2実施例では、第1増幅段100-1の前段に加算回路131を設けることで、増幅器6に周波数変換機能を追加することができる。周波数変換回路130が有する第1トランジスタM1は、第2,3増幅段100-2,3が有する第1トランジスタM1と直流電流を共有することで、増幅器6の消費電力を抑制できる。 As described above, in the second embodiment, the frequency conversion function can be added to the amplifier 6 by providing the adder circuit 131 in front of the first amplification stage 100-1. The first transistor M1 included in the frequency conversion circuit 130 can share the direct current with the first transistor M1 included in the second and third amplification stages 100-2 and 3 to suppress the power consumption of the amplifier 6.
　なお、図3に示す増幅器2～3の第1増幅段100-1の前段に加算回路131を設けることで増幅器2～3にも周波数変換機能を備えることが可能である。 In addition, it is possible to provide the amplifiers 2 to 3 with a frequency conversion function by providing the adder circuit 131 before the first amplification stage 100-1 of the amplifiers 2 to 3 shown in FIG.
　また、トランジスタを有する周波数変換回路であれば、本実施例で示した周波数変換回路130に代えて用いてもよい。周波数変換回路が有するトランジスタに流れる直流電流と増幅段に流れる直流電流を共有することで、周波数変換機能を有する増幅器6の消費電力を抑制できる。 Further, any frequency conversion circuit having a transistor may be used instead of the frequency conversion circuit 130 shown in this embodiment. By sharing the direct current flowing through the transistor included in the frequency conversion circuit and the direct current flowing through the amplification stage, the power consumption of the amplifier 6 having the frequency conversion function can be suppressed.
(第3実施例)
　図6を用いて本発明の第3実施例を説明する。図6に示す回路は、発振機能と増幅機能を併せ持つ回路である。本実施例では発振機能を有する増幅器7と称する。 (Third embodiment)
A third embodiment of the present invention will be described with reference to FIG. The circuit shown in FIG. 6 is a circuit having both an oscillation function and an amplification function. In this embodiment, it is referred to as an amplifier 7 having an oscillation function.
　増幅器7は、図1の増幅器1の第1増幅段100-1に代えて発振回路140を有している。発振回路140は、互いにクロスカップル接続されたトランジスタM3,M4と、トランジスタM3,4のドレイン端子に接続され、かつ互いに直列に接続された可変キャパシタ素子C3,4及びインダクタ素子L3.4を有している。 The amplifier 7 has an oscillation circuit 140 instead of the first amplification stage 100-1 of the amplifier 1 of FIG. The oscillation circuit 140 includes transistors M3 and M4 that are cross-coupled to each other, and variable capacitor elements C3 and C3 that are connected to the drain terminals of the transistors M3 and 4 and that are connected in series to each other. ing.
　トランジスタM3のゲート端子はトランジスタM4のドレイン端子に接続し、ドレイン端子は可変キャパシタ素子C3の一端及びインダクタ素子L3の一端に接続し、ソース端子はグランドに接続している。 The gate terminal of the transistor M3 is connected to the drain terminal of the transistor M4, the drain terminal is connected to one end of the variable capacitor element C3 and one end of the inductor element L3, and the source terminal is connected to the ground.
　トランジスタM4のゲート端子はトランジスタM3のドレイン端子に接続し、ドレイン端子は可変キャパシタ素子C4の一端及びインダクタ素子L４の一端に接続し、ソース端子はグランドに接続している。 The gate terminal of the transistor M4 is connected to the drain terminal of the transistor M3, the drain terminal is connected to one end of the variable capacitor element C4 and one end of the inductor element L4, and the source terminal is connected to the ground.
　可変キャパシタ素子C3は、一端がトランジスタM3のドレイン端子に、他端が可変キャパシタ素子C4の他端に接続している。インダクタ素子L3は、一端がトランジスタM3のドレイン端子に、他端がインダクタ素子L4の他端及びVddに接続している。 The variable capacitor element C3 has one end connected to the drain terminal of the transistor M3 and the other end connected to the other end of the variable capacitor element C4. The inductor element L3 has one end connected to the drain terminal of the transistor M3 and the other end connected to the other end of the inductor element L4 and Vdd.
　発振回路140の出力信号である発振信号は、トランジスタM3,4のドレイン端子からそれぞれ出力され、キャパシタ素子C31,C32を介して第2増幅段100-2へ入力される。図6に示す発振回路140は差動信号である発振信号を出力するため、増幅器7の第2,3増幅段100-2,3には、図2(b)に示す擬似差動増幅段を用いる。 The oscillation signal that is the output signal of the oscillation circuit 140 is output from the drain terminals of the transistors M3 and M4, and is input to the second amplification stage 100-2 via the capacitor elements C31 and C32. Since the oscillation circuit 140 shown in FIG. 6 outputs an oscillation signal that is a differential signal, the second and third amplification stages 100-2 and 3 of the amplifier 7 have pseudo differential amplification stages shown in FIG. Use.
　トランジスタM3,4に流れる直流電流及び第2増幅段100-2に流れる直流電流の総和は、第3増幅段100-3に流れる直流電流と等しくなるようにする。 The sum of the direct current flowing through the transistors M3 and M4 and the direct current flowing through the second amplification stage 100-2 is made equal to the direct current flowing through the third amplification stage 100-3.
　以上のように、第3実施例では、第1増幅段100-1の代わりに発振回路140を設けることで、発振機能を有する増幅器7を提供することができる。トランジスタM3,4に流れる直流電流及び第2増幅段100-2に流れる直流電流の総和は、第3増幅段100-3に流れる直流電流と等しくなるようにすることで、発振回路140に流れる直流電流と第2,3増幅段100-2,3に流れる直流電流とを共有することができるため、増幅器7の消費電力を抑制することが可能となる。 As described above, in the third embodiment, the amplifier 7 having an oscillation function can be provided by providing the oscillation circuit 140 instead of the first amplification stage 100-1. The sum of the direct current flowing through the transistors M3 and 4 and the direct current flowing through the second amplification stage 100-2 is made equal to the direct current flowing through the third amplification stage 100-3, so that the direct current flowing through the oscillation circuit 140 is reached. Since the current and the direct current flowing through the second and third amplification stages 100-2 and 3 can be shared, the power consumption of the amplifier 7 can be suppressed.
　なお、図3に示す増幅器2～3の第1増幅段100-1の代わりに発振回路140を設けても、本実施例と同様の効果が得られることは明らかである。 It is obvious that the same effect as in this embodiment can be obtained even if the oscillation circuit 140 is provided instead of the first amplification stage 100-1 of the amplifiers 2 to 3 shown in FIG.
　また、トランジスタを有する発振回路であれば、本実施例に示した発振回路140に代えて用いてもよい。発振回路が有するトランジスタに流れる直流電流と増幅段に流れる直流電流を共有することで、発振機能を有する増幅器7の消費電力を抑制することができる。 Further, if the oscillation circuit has a transistor, the oscillation circuit 140 shown in this embodiment may be used instead. By sharing the direct current flowing through the transistor included in the oscillation circuit and the direct current flowing through the amplification stage, the power consumption of the amplifier 7 having the oscillation function can be suppressed.
(第4実施例)
　図7を用いて、本発明の第4の実施例を説明する。図7には、増幅器1をPA(Power Amplifier)として使用した送信機1000を示している。 (Fourth embodiment)
A fourth embodiment of the present invention will be described with reference to FIG. FIG. 7 shows a transmitter 1000 that uses the amplifier 1 as a PA (Power Amplifier).
　送信機1000は、ローパスフィルタ1001、ミキサ1002、増幅器1、バンドパスフィルタ1003、アンテナ1004を有している。 The transmitter 1000 includes a low-pass filter 1001, a mixer 1002, an amplifier 1, a band-pass filter 1003, and an antenna 1004.
　送信機1000の送信相手に送信する送信データは、図示しない信号処理部で変調、DA変換等の信号処理が行われ、IF信号に変換される。 Transmission data to be transmitted to the transmission partner of the transmitter 1000 is subjected to signal processing such as modulation and DA conversion in a signal processing unit (not shown) and converted to an IF signal.
　ローパスフィルタ1001は、IF信号から所望帯域の信号を抽出し、後段のミキサ1002に抽出したIF信号を出力する。ミキサ1002は、該IF信号とLO信号とを乗算し、RF信号を生成する。増幅器1は、図1に示す増幅器であって、RF信号のを増幅し、増幅信号を出力する。バンドパスフィルタ1003は、増幅信号から所望の帯域の信号を抽出し、無線信号をアンテナ1004を介して送信する。 The low pass filter 1001 extracts a signal in a desired band from the IF signal, and outputs the extracted IF signal to the mixer 1002 at the subsequent stage. The mixer 1002 multiplies the IF signal and the LO signal to generate an RF signal. The amplifier 1 is the amplifier shown in FIG. 1 and amplifies an RF signal and outputs an amplified signal. The bandpass filter 1003 extracts a signal in a desired band from the amplified signal and transmits a radio signal via the antenna 1004.
　以上のように第4実施例によれば、送信機1000のPAとして用いることで送信機1000の消費電力を抑制することができる。 As described above, according to the fourth embodiment, the power consumption of the transmitter 1000 can be suppressed by using it as the PA of the transmitter 1000.
　なお、図1に示す増幅器1以外にも増幅器2～6を用いてもよい。特に増幅器6は周波数変換機能を有しており、無線機1000のミキサ1002を省略することができ、無線機の回路面積を削減できる。 In addition to the amplifier 1 shown in FIG. 1, amplifiers 2 to 6 may be used. In particular, the amplifier 6 has a frequency conversion function, so that the mixer 1002 of the wireless device 1000 can be omitted, and the circuit area of the wireless device can be reduced.
　なお、図7に示す送信機以外の構成であってもPAを用いる送信機であれば、第1～第3実施例に示す増幅器1～6を用いることで送信機の消費電力を削減できる。また、送信機のPA以外にも、受信機の増幅手段として、第1～第3実施例に示す増幅器1～6を用いてもよい。 Note that even if the configuration is other than the transmitter shown in FIG. 7, if the transmitter uses a PA, the power consumption of the transmitter can be reduced by using the amplifiers 1 to 6 shown in the first to third embodiments. In addition to the PA of the transmitter, the amplifiers 1 to 6 shown in the first to third embodiments may be used as the amplification means of the receiver.
　なお、本発明は上記実施形態そのままに限定されるものではなく、実施段階ではその要旨を逸脱しない範囲で構成要素を変形して具体化できる。また、上記実施形態に開示されている複数の構成要素の適宜な組み合わせにより、種々の発明を形成できる。例えば、実施形態に示される全構成要素から幾つかの構成要素を削除してもよい。さらに、異なる実施形態にわたる構成要素を適宜組み合わせてもよい。 Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying constituent elements without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of components disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, constituent elements over different embodiments may be appropriately combined.
1～7　増幅器、100　増幅段、110,111　増幅回路、130　周波数変換回路、131　加算回路、140　発振回路 1-7 amplifier, 100 amplifier stage, 110,111 amplifier circuit, 130 frequency converter circuit, 131 adder circuit, 140 oscillator circuit

Claims (5)

  1. 　ソース端子が互いに接続しており、ドレイン端子が第1電源電位に接続しているトランジスタを有し、交流信号を増幅して増幅信号を得るM(Mは2以上の整数)個の増幅回路と、
    　ドレイン端子が前記M個の増幅回路のソース端子に接続され、かつ互いに接続しており、ソース端子が第2電源電位に接続しているトランジスタを有し、交流信号を増幅して増幅信号を得るN-M(Nは3以上の整数)個の増幅回路と、を備え、
    　前記M個の増幅段の前記ソース端子と、前記N-M個の増幅段の前記ドレイン端子とは共通接続されていることを特徴とする増幅器。     M (M is an integer of 2 or more) amplifier circuits that have transistors whose source terminals are connected to each other and whose drain terminals are connected to the first power supply potential, and that amplify an AC signal and obtain an amplified signal; ,
    A drain terminal is connected to the source terminals of the M amplifier circuits and connected to each other, and the source terminal has a transistor connected to the second power supply potential, and an AC signal is amplified to obtain an amplified signal. NM (N is an integer of 3 or more) amplifier circuits,
    The amplifier, wherein the source terminals of the M amplification stages and the drain terminals of the NM amplification stages are connected in common.
  2. 　前記M個及びN-M個の増幅回路のうち、第k(kは、0<k<Nの整数)増幅回路のドレイン端子は、第k+1増幅回路のゲート端子に接続されており、第k増幅回路で増幅した増幅信号を第k+1増幅回路が増幅することを特徴とする請求項1の増幅器。 Of the M and NM amplifier circuits, the drain terminal of the kth amplifier circuit (k is an integer of 0 <k <N) is connected to the gate terminal of the (k + 1) th amplifier circuit, and the kth amplifier circuit. 2. The amplifier according to claim 1, wherein the k + 1-th amplifier circuit amplifies the amplified signal amplified by the amplifier circuit.
  3. 　M>N-Mであり、かつ前記M個の増幅回路は、第1～M増幅回路からなり、前記N-M個の増幅回路は、第M+1～N増幅回路からなることを特徴とする請求項2記載の増幅器。 3. M> NM, and the M amplifier circuits include first to M amplifier circuits, and the NM amplifier circuits include M + 1 to N amplifier circuits. The described amplifier.
  4. 　前記N-M個の増幅回路の前記トランジスタの各サイズW1s(sは1≦s≦N-Mの整数)は、前記M個の増幅回路の前記トランジスタの各サイズW2t(tは1≦t≦Mの整数)より大きい(W1s>W2t)ことを特徴とする請求項３記載の増幅器。 Each size W1s (s is an integer of 1 ≦ s ≦ NM) of the transistors of the NM amplifier circuits is each size W2t of the transistors of the M amplifier circuits (t is an integer of 1 ≦ t ≦ M). 4. The amplifier according to claim 3, wherein the amplifier is larger (W1s> W2t).
  5. 　前記第k増幅回路の前記トランジスタのゲート端子とソース端子との間の電圧差VgkはVgk<Vgk+1を満たすことを特徴とする請求項４に記載の増幅器。 The amplifier according to claim 4, wherein the voltage difference Vgk between the gate terminal and the source terminal of the transistor of the kth amplifier circuit satisfies Vgk <Vgk + 1.
PCT/JP2009/004309 2009-09-02 2009-09-02 Amplifier WO2011027387A1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016051906A (en) * 2014-08-28 2016-04-11 ラピスセミコンダクタ株式会社 High frequency amplifier circuit

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0247820U (en) * 1988-09-29 1990-04-03
JPH11340748A (en) * 1998-05-29 1999-12-10 Hochiki Corp High frequency amplifier circuit
JP2001007657A (en) * 1999-04-21 2001-01-12 Hitachi Ltd High-frequency power amplifier and radio communications equipment
JP2002171147A (en) * 2000-11-30 2002-06-14 Nec Corp Wide band preamplifier
JP2004056162A (en) * 2002-07-16 2004-02-19 Oki Electric Ind Co Ltd Amplifier circuit

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0247820U (en) * 1988-09-29 1990-04-03
JPH11340748A (en) * 1998-05-29 1999-12-10 Hochiki Corp High frequency amplifier circuit
JP2001007657A (en) * 1999-04-21 2001-01-12 Hitachi Ltd High-frequency power amplifier and radio communications equipment
JP2002171147A (en) * 2000-11-30 2002-06-14 Nec Corp Wide band preamplifier
JP2004056162A (en) * 2002-07-16 2004-02-19 Oki Electric Ind Co Ltd Amplifier circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016051906A (en) * 2014-08-28 2016-04-11 ラピスセミコンダクタ株式会社 High frequency amplifier circuit

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