WO2011007642A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
WO2011007642A1
WO2011007642A1 PCT/JP2010/060388 JP2010060388W WO2011007642A1 WO 2011007642 A1 WO2011007642 A1 WO 2011007642A1 JP 2010060388 W JP2010060388 W JP 2010060388W WO 2011007642 A1 WO2011007642 A1 WO 2011007642A1
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Prior art keywords
voltage
signal
semiconductor device
clock
power supply
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PCT/JP2010/060388
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French (fr)
Japanese (ja)
Inventor
古田　太
長田　健一
晋也 宮崎
一成 藤木
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株式会社日立製作所
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Priority to JP2011522766A priority Critical patent/JP5319773B2/en
Publication of WO2011007642A1 publication Critical patent/WO2011007642A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
    • H01L2224/05009—Bonding area integrally formed with a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16146—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Definitions

  • the present invention relates to a semiconductor device in which a microprocessor, a memory, and the like are integrated, and more particularly, to a signal transmission method via through vias between a plurality of stacked semiconductor chips.
  • CMOS Complementary Metal Oxide Semiconductor
  • CMOS Complementary Metal Oxide Semiconductor
  • the miniaturization of elements has realized improvement in speed per chip and reduction in power consumption.
  • a tendency to slow down in improving chip performance has appeared. This is because the limit of miniaturization itself, the wiring delay between elements that cannot be improved by miniaturization, and the increase in power consumption accompanying the increase in the leakage current of the element have become apparent.
  • an information processing system of a certain scale is constructed, since there is a limit to the functions that can be integrated on one chip, it is essential to arrange a plurality of chips and connect the chips.
  • the arrangement direction of the chips has been horizontal so far, and the transmission distance of signals between the chips is at least one side of the chip. Therefore, even if the operation speed per chip is improved, since the transmission distance between the chips is long, it is difficult to improve the speed of the entire system.
  • Non-Patent Document 1 A multilayer chip system represented by Non-Patent Document 1 has been proposed in order to cope with the slowdown of chip performance improvement and the performance improvement of the entire system.
  • the outline is shown in FIG. This is because another semiconductor chip is three-dimensionally stacked above and below the semiconductor chip 100, and the chips are connected via through vias (conductor 101, pad 102, solder bump 104) to transmit information and power.
  • Technology Long-distance wiring of signals within a chip and signal wiring between chips are transmitted by through vias directly above the chip, greatly reducing wiring delay between elements in the chip and inter-chip transmission delay that becomes a bottleneck in the entire system It can be expected to be reduced.
  • Patent Document 1 in the stacked chip system as shown in FIG. 1, by providing a latch circuit on a through via path in each chip, data transfer between the chips is performed via a pipeline via the latch circuit.
  • the technique to be performed by the method is shown.
  • the influence of delay due to the floating capacitance of the through via can be reduced, and high-speed data transfer can be realized.
  • Patent Document 2 in data transfer between a driver circuit and a receiver circuit via a wiring, a MISFET having a gate as a fixed voltage is inserted into a driving path on the high level side of the driver circuit, so that the high level side is inserted.
  • a technique for limiting the amplitude is shown.
  • each gate of pMOSFET and nMOSFET is driven by a logic gate having a predetermined logic threshold value, and the output voltage of the output driver circuit is fed back to the input of each logic gate.
  • a technique for controlling the amplitude on the high level side and the low level side is shown. Thereby, for example, speeding up and noise reduction can be achieved.
  • the semiconductor device (laminated chip system) using through vias as shown in FIG. 1 has the following problems.
  • the through via literally includes a conductor 101 penetrating the front and back of the silicon substrate, and this conductor is in contact with the silicon substrate through the insulating film 103, and thus a stray capacitance is generated therebetween.
  • FIG. 2 is an equivalent circuit diagram showing a configuration example of the peripheral portion of the through via per chip in FIG.
  • the transmitter 107 included in a certain semiconductor chip 100 outputs a signal to the through via, and this signal is transmitted through the through via of each semiconductor chip 100.
  • the receiving unit 108 included in the semiconductor chip 100 receives.
  • the through via floating capacitance 106 for each chip is added, so the influence of the floating capacitance cannot be ignored as the layers are stacked.
  • the via diameter is 10 ⁇ m
  • the via length is 50 ⁇ m
  • the thickness of the insulating film (SiO 2 ) is 100 nm
  • the stray capacitance per via is 0.53 pF.
  • the stray capacitance of the via becomes 6.5 pF, which is equivalent to a normal PAD wiring.
  • the increase in through-via stray capacitance has a large effect on the operating frequency of the circuit.
  • a rise time and a fall time are required when the signal voltage is switched. These times are proportional to the CR time constant determined by the load capacitance C of the transmission line and the resistance of the output FET, that is, the output resistance R.
  • An increase in through via stray capacitance leads to an increase in these times, leading to a limitation on the upper limit frequency in the transmission signal on the through via and an increase in the delay time in the transmission signal from the chip to another chip.
  • the number of stacked layers increases, it becomes difficult to increase the speed of the entire system, which is an inherent advantage of the stacked chip. For this reason, to improve the operating frequency, it is necessary to reduce the CR time constant, that is, to reduce the stray capacitance and the output resistance.
  • the channel width of the FET is widened to reduce the output resistance and the CR time constant.
  • the stray capacitance of the FET itself increases as the channel width increases, not only can the CR time constant be reduced efficiently, but the power consumption may increase by the amount of stray capacitance of the FET.
  • Patent Document 1 there is a method of improving the operating frequency by inserting a latch circuit into a through via. By dividing the through via capacitance for each chip, the CR time constant does not depend on the number of stacked layers, and is always equal to the number of stacked layers, so that high speed can be expected. However, since the through-via stray capacitance in the entire multilayer chip does not change, power consumption does not decrease.
  • the load capacitance can be charged using a single-stage configuration (pMOSFET) instead of the two-stage configuration as in Patent Document 2, and the speed is increased by limiting the amplitude.
  • the substantial operating voltage when charging the load capacitance is the low voltage V1. That is, when the power supply voltage is Vd and the low level voltage is VL, the source-drain voltage V1 when the pMISFET is turned on is a voltage (Vd ⁇ VL) lower than Vd. This delays the rise time.
  • the margin for manufacturing variations may be reduced.
  • the determination level of the signal is normally set between the high level and the low level, but both the high level and the low level may vary due to manufacturing variations, so there is a possibility that a sufficient margin for the determination level cannot be secured.
  • the present invention has been made in view of the above, and one of its purposes is to reduce power consumption and increase the speed of signal transmission in a semiconductor device that performs signal transmission via a bus such as a through via. Is to realize.
  • a bus such as a through via.
  • the semiconductor device includes a transmission buffer circuit including a pMOSFET connected between the through via and the power supply voltage VDD, and an nMOSFET connected between the through via and the reference power supply voltage VSS in the stacked chip system using the through via. And a control circuit for controlling the on / off time of each FET so that the low level is VSS and the high level is VDD ⁇ K (0.0 ⁇ K ⁇ 1.0).
  • control circuit There are two types of control methods using this control circuit. One is a method of limiting the amplitude by turning on / off each FET for a certain period using a delay circuit according to the load of the through via. The other is that the reference signal (for example, clock signal) and data signal through-vias have the same structure, and the voltage state of the reference signal is detected, so that the data transmission buffer is reflected while reflecting the load capacity of the through-via. This is a method of controlling and limiting the amplitude.
  • reference signal for example, clock signal
  • data signal through-vias have the same structure, and the voltage state of the reference signal is detected, so that the data transmission buffer is reflected while reflecting the load capacity of the through-via.
  • FIG. 3 shows an outline of the transmission unit of the through via transmission circuit according to this embodiment.
  • the data signal is input in synchronization with the clock signal.
  • the clock transmission buffer (inverter composed of pMOSFET 202 and nMOSFET 203 in FIG. 3) receives the clock input signal and drives the through via to transmit the clock signal, and the amplitude voltage of the clock signal is transmitted to the power supply voltage.
  • a conventional driving method that swings from VDD to the reference power supply voltage VSS is used.
  • the data transmission buffer pMOSFET 204 and nMOSFET 205 in FIG. 3
  • the gates of the pMOSFET 204 and the nMOSFET 205 are independently controlled so that a data signal whose amplitude is limited to the through via can be transmitted. Limited in the range of VDD to VSS.
  • the control circuit 201 When the first control method is used, the control circuit 201 first drives the nMOSFET 205 on and the pMOSFET 204 off when the clock signal is at a low level. As a result, the through via voltage becomes VSS. Thereafter, when the clock signal rises from the low level to the high level, the control circuit 201 maintains the state of each FET described above when the data input signal is at the low level. On the other hand, when the data input signal is at a high level, the control circuit 201 turns off the nMOSFET 205 in response to the rising edge of the clock signal, and is necessary for the through via voltage to reach K ⁇ VDD by the delay circuit provided therein. The pMOSFET 204 is turned on for a short period and then turned off. Next, when the clock signal falls to the low level, as described above, the control circuit 201 turns on the nMOSFET 205 and returns the through via voltage to VSS.
  • the control circuit 201 monitors the transition of the clock input signal (251) as an input of the clock transmission buffer and the voltage of the clock output signal (252) on the via as an output. First, when the clock input signal is at a low level, the control circuit 201 drives the nMOSFET 205 on and the pMOSFET 204 off. As a result, the through via voltage becomes VSS. Thereafter, when the clock input signal rises from the low level to the high level, the control circuit 201 maintains the state of each FET described above when the data input signal is at the low level.
  • the control circuit 201 turns off the nMOSFET 205 in response to the rising edge of the clock input signal, and turns off the pMOSFET 204 after turning it on for a certain period.
  • the timing at which the pMOSFET 204 is switched from on to off is the timing at which the voltage of the data signal through via reaches K ⁇ VDD based on the result of monitoring the voltage of the clock output signal (252) on the via. is there.
  • the control circuit 201 turns on the nMOSFET 205 and returns the through via voltage to VSS.
  • FIG. 4 shows an outline of the receiving unit of the through via transmission circuit according to this embodiment.
  • the clock input signal input through the through via is used as a start signal (determination timing) 253 of the comparator circuit (reception buffer) 211 on the data signal side. In some cases, it is also used as the start signal 253 of the reference voltage source 212. Used.
  • the data signal input via the through via is compared with the reference voltage by the comparator circuit 211 at the determination timing, and is output via the latch circuit 213.
  • the receiving unit determines the truth value by comparing the amplitude-limited data signal with the reference voltage.
  • FIG. 2 is an equivalent circuit diagram illustrating a configuration example of a peripheral portion of a through via per chip in FIG. 1.
  • FIG. 3 is a block diagram illustrating a configuration example of a transmission unit in the semiconductor device according to the first embodiment of the present invention.
  • FIG. 3 is a block diagram illustrating a configuration example of a receiving unit in the semiconductor device according to the first embodiment of the present invention.
  • FIG. 7 is a circuit diagram illustrating a configuration example of the comparator circuit in the receiving unit of FIG. 6.
  • FIG. 6 is a waveform diagram illustrating an operation example of the transmission unit in FIG. 5.
  • FIG. 7 is a waveform diagram illustrating an operation example of the reception unit in FIG. 6. It is a circuit diagram equivalently showing a transmission buffer and a penetration via. It is explanatory drawing which shows prescription
  • 5 is a graph showing a result of verifying a power consumption value with respect to an operating frequency in the semiconductor device according to the first embodiment of the present invention.
  • 5 is a graph showing a result of verifying an FET width necessary to satisfy an operating frequency in the semiconductor device according to the first embodiment of the present invention.
  • the semiconductor device by Embodiment 2 of this invention it is a block diagram which shows the structural example of the transmission part.
  • it is a block diagram which shows the structural example of the receiving part.
  • It is a wave form diagram which shows the operation example of the transmission part of FIG.
  • It is a wave form diagram which shows the operation example of the receiving part of FIG.
  • it shows the reference voltage source of the receiving part,
  • (a) is a circuit diagram which shows the example of a structure
  • (b) is a capacitance pair with a switch in (a). It is a circuit diagram which shows a structural example.
  • FIG. 21 is a circuit diagram illustrating a configuration example of a differential amplifier circuit in FIG. 20. It is a wave form diagram which shows the operation example of the transmission part of FIG. It is a wave form diagram which shows the operation example of the receiving part of FIG. It is a conceptual diagram explaining an example of the effect in the semiconductor device by one embodiment of the present invention.
  • each functional block of the embodiment are not particularly limited, but are formed on a semiconductor substrate such as single crystal silicon by a known integrated circuit technology such as a CMOS (complementary MOS transistor).
  • CMOS complementary MOS transistor
  • a MOSFET Metal / Oxide / Semiconductor / Field / Effect / Transistor
  • MISFET Metal / Insulator / Semiconductor / Field / Effect / Transistor
  • pMOSFET P-channel MOSFET
  • nMOSFET N-channel MOSFET
  • FIG. 5 is a block diagram showing a configuration example of the transmitting unit in the semiconductor device according to the first embodiment of the present invention.
  • FIG. 6 shows a configuration of the receiving unit in the semiconductor device according to the first embodiment of the present invention. It is a block diagram which shows an example. 5 and 6 correspond to the transmitting unit 107 and the receiving unit 108 shown in FIG. 2, respectively.
  • the FET in the data signal transmission buffer circuit is controlled by the delay circuit will be described.
  • data signals for one channel are shown for one clock signal, but the actual number of data signal channels may be plural.
  • the transmission unit shown in FIG. 5 includes a clock transmission buffer composed of a pMOSFET 320 and an nMOSFET 321, a data transmission buffer composed of a pMOSFET 318 and an nMOSFET 319, a control circuit 301 for the data transmission buffer, and the like.
  • the clock transmission buffer transmits a clock output signal 337 to the through via
  • the data transmission buffer transmits a data output signal 336 to the through via.
  • the control circuit 301 includes a latch circuit 311, a rising edge detection circuit 312, a delay circuit 313, a delay circuit 314, a state control register 315, a state control register 316, and a NAND circuit 317.
  • the rise detection circuit 312 and the delay circuits 313 and 314 can be shared between the channels.
  • the MOSFETs 318 and 319 constituting the data transmission buffer may be configured to have a smaller channel width than the MOSFETs 320 and 321 of the clock transmission buffer.
  • FIG. 8 is a waveform diagram showing an operation example of the transmission unit of FIG. While the clock input signal is at the low level, the nMOSFET 319 of the data transmission buffer is in the ON state, and the through via voltage is fixed to the reference power supply voltage VSS. In this case, the register 316 is also initialized so that the nMOSFET 319 is turned on.
  • the detection circuit 312 may be anything as long as it can detect the rising edge of the clock signal, and examples thereof include an inverter.
  • the latch circuit 311 takes in the data input signal and outputs it to the NAND circuit 317 in response to the start signal 331 that is output from the detection circuit 312. At the same time, the activation signal 331 sets the control register 315 and outputs a signal “1” from the register to the NAND circuit 317.
  • the pMOSFET 318 is turned on by the control signal 334 from the NAND circuit 317.
  • the state control register 316 is reset by the activation signal 331, and the nMOSFET 319 is turned off.
  • the activation signal 331 is delayed for a certain time by the delay circuit 313, whereby the inhibition signal 332 is generated.
  • the inhibit signal 332 resets the register 315.
  • the output of the register becomes “0”, and the pMOSFET 318 of the data transmission buffer is turned OFF via the NAND circuit 317.
  • charging of the data signal through via (data output signal 336) is stopped and the voltage is maintained.
  • the inhibition signal 332 is input to the second delay circuit 314, and the register 316 is set by the delayed precharge signal 333. Therefore, the nMOSFET 319 is turned on, and the data signal through via is forcibly precharged to VSS.
  • the precharge signal 333 is generated using the two delay circuits 313 and 314. However, a system in which the precharge signal 333 is generated by simply detecting the low level of the clock signal may be used.
  • the reception unit shown in FIG. 6 includes a rise detection circuit 341, a reference voltage source 342, a comparator circuit 343, a truth value determination circuit (latch circuit) 344, a delay circuit 345, and the like, similar to the control circuit 301 of the transmission unit.
  • the rising edge detection circuit 341 detects the rising edge of the clock input signal 355 received from the through via, and is not particularly limited.
  • the rising edge detection circuit 341 includes an inverter circuit.
  • FIG. 9 is a waveform diagram illustrating an operation example of the receiving unit in FIG. First, the reference voltage source 342 is activated by the activation signal 351 that is the output of the rise detection circuit 341.
  • the comparator circuit 343 is activated by the determination enable signal 352 delayed through the delay circuit 345.
  • the data input signal 354 input through the through via is compared with the reference voltage from the reference voltage source 342 by the latch type comparator circuit 343, and the determination data signal 353 as a result is input to the truth value determination circuit 344.
  • FIG. 7 is a circuit diagram showing a configuration example of the comparator circuit 343 in the receiving unit of FIG.
  • the comparator circuit shown in FIG. 7 includes a so-called CMOS cross-coupled sense amplifier circuit, an input switch for connecting an input signal thereto, a power switch for connecting a power supply (power supply voltage VDD, reference power supply voltage VSS) to the switch, It is constituted by a flip-flop that latches an output signal. While the determination enable signal (SENSE) 352 in FIG. 6 is low, the input signal is connected to the sense amplifier circuit, but is separated from the power supply. On the other hand, when SENCE goes high, the input signal is separated and the power supply is connected. At this moment, a slight voltage difference between the input signals is amplified to the level between VDD and VSS, and the truth value is determined. Then, the truth value is latched by a subsequent flip-flop.
  • CMOS cross-coupled sense amplifier circuit an input switch for connecting an input signal thereto
  • a power switch for connecting
  • the power consumption reduction effect when amplitude limitation is performed using the semiconductor device according to the present embodiment will be described.
  • the power consumption of the transmission buffer (inverter circuit) for driving a load capacitance C L is caused by the charging and discharging current to the load capacitance.
  • the power consumption P in the case where the power supply voltage VDD, the frequency f, and the load volume to C L is expressed by the formula (1) described above.
  • the power consumption P is expressed by Equation (2), and the power consumption can be reduced by the ratio of the limit width to VDD.
  • the transmission buffer and the through via connected thereto can be approximated to the RC circuit shown in FIG.
  • R PMOS is the effective output resistance of the pMOSFET.
  • the operating frequency f MAX is expressed by Equation (5). For this reason, it is essential to reduce each time in order to improve the operating frequency. Limiting the amplitude reduces these times, resulting in an increase in operating frequency.
  • the VSS side and the VDD side can be considered.
  • the amplitude limit on the VSS side is used, and the output voltage is basically in a state of VSS, and when outputting a high level, the output voltage is adjusted by the ON time of the pMOSFET, and then the nMOSFET again. The voltage is returned to the VSS potential by turning on (VSS precharge).
  • the rise time (t R ) and fall time (t F ) when through vias are connected are expressed by equations (6) and (7) in the same manner as in the derivation of equation (4).
  • VDD precharge Each time in this case is expressed by Expression (8) and Expression (9) as in the case of VSS precharge.
  • Both precharge methods can reduce the rise time and fall time, respectively.
  • the VSS precharge system of the present embodiment due to the asymmetry of carrier mobility between the pMOSFET and the nMOSFET, it is actually more advantageous to use the VSS precharge system of the present embodiment.
  • the electron mobility is higher than the hole mobility, and the effective resistance R PMOS is more than twice as high as the R NMOS in the FET having the same channel width.
  • the ratio of the FET channel width is determined by the VDD precharge method based on the comparison between Equation (6) and Equation (7), and Equation (8) and Equation (9) Becomes larger.
  • the VSS side restriction can reduce the time more effectively.
  • the required FET width for the target operating frequency can be minimized, the mounting area and stray capacitance can be reduced, and the power consumption can be close to the theoretical value.
  • the nMOSFET is turned on from the state where the potential difference between the source and the drain is VDD, and until the drain voltage reaches the predetermined intermediate voltage Vmid, the discharge operation is mainly performed using the saturation region. Then, the pMOSFET is turned on from the state where the source-drain voltage is VDD-Vmid and the charge operation is performed mainly using the non-saturated region until the drain voltage reaches VDD.
  • the pMOSFET is turned on from the state in which the potential difference between the source and the drain is VDD and the drain voltage reaches Vmid.
  • the nMOSFET is turned on from the state in which the potential difference between the source and the drain is VDD ⁇ Vmid and the discharge operation is performed mainly using the non-saturated region until the drain voltage reaches VSS.
  • the switching time greatly affects the delay time in this non-saturation region, and the delay time is larger in the pMOSFET than in the nMOSFET.
  • the switching time between VDD and Vmid is Tvd
  • the switching time between VSS and Vmid is shorter by ⁇ t than Tvd. Tvs. This makes it possible to increase the speed.
  • the VSS precharge method according to the present embodiment is also beneficial from the viewpoint of margin for manufacturing process variations. That is, in the method of Patent Document 3, there is a risk that the voltage value on both the high level side and the low level side may vary, but in the VSS precharge method, there is a risk that only the voltage value on the high level side may vary. Therefore, it becomes possible to give a certain margin to the reference voltage value from the reference voltage source 342 of the receiving unit in FIG.
  • FIG. 12 shows the power consumption value with respect to the operating frequency. Further, for comparison of the effect of reducing power consumption, the theoretical values obtained in the case of full amplitude and the above-described equation (1) are also plotted in FIG. First, it can be seen that the power consumption can be reduced for the same operating frequency in both precharge methods as compared with the full amplitude. The reduction ratio is 60% as long as it is on the theoretical value straight line. Furthermore, a comparison between the VSS precharge method and the VDD precharge method shows that the former can substantially achieve the theoretical value even if the operating frequency is improved. This indicates that power consumption is consumed with almost via capacity. This is because the channel width of the FET in the VSS precharge method can be narrower than that in the VDD precharge method, so that the stray capacitance is at a level that can be ignored with respect to the via load capacitance.
  • FIG. 13 shows the FET width required in the transmission buffer to satisfy the operating frequency.
  • This width value represents the total value of the nMOSFET and the pMOSFET.
  • the reason why the full-amplitude FET width is three times or more wider than the two precharge methods is that it is necessary to lower the output resistance in order to achieve the same operating frequency.
  • the reason why the VDD precharge method is 1.5 times wider than the VSS precharge method is that the ratio of pMOSFET to nMOSFET is unbalanced. It can also be seen from the figure that the VSS precharge method can improve the operating frequency with the narrowest FET width. Only the same method is consistent with the theoretical value.
  • the semiconductor device typically, when signal transmission is performed via a bus such as a through via, power consumption can be reduced and signal transmission speed can be increased. .
  • FIG. 14 is a block diagram illustrating a configuration example of the transmission unit in the semiconductor device according to the second embodiment of the present invention.
  • FIG. 15 illustrates a configuration of the reception unit in the semiconductor device according to the second embodiment of the present invention. It is a block diagram which shows an example. In FIG. 14 and FIG. 15, data signals for one channel are shown for one clock signal, but the actual number of data signal channels may be plural.
  • the 14 includes a clock transmission buffer composed of a pMOSFET 719 and an nMOSFET 720, a data transmission buffer composed of a pMOSFET 717 and an nMOSFET 718, a control circuit 701 for the data transmission buffer, and the like.
  • the clock transmission buffer transmits a clock output signal 736 to the through via
  • the data transmission buffer transmits a data output signal 735 to the through via.
  • the control circuit 701 includes a latch circuit 711, a rising edge detection circuit 712, a voltage detection circuit 713, a state control register 714, a NAND circuit 715, and an inverter circuit 716. When there are a plurality of data channels, the rise detection circuit 712 and the voltage detection circuit 713 can be shared between the channels.
  • the transistor size (gate width) of the MOSFETs 717 and 718 constituting the data transmission buffer is the same as the transistor size (gate width) of the MOSFETs 719 and 720 constituting the clock transmission buffer.
  • the clock transmission buffer may be designed larger than the data transmission buffer.
  • the rising edge detection circuit 712 may be anything as long as it can compare specific voltages. Although a simple inverter is possible, the threshold value may vary. It is desirable to use a reference voltage source in combination with a comparator circuit that performs a constant comparison operation represented by a differential amplifier.
  • FIG. 16 is a waveform diagram showing an operation example of the transmission unit in FIG. While the clock input signal is at the low level, the nMOSFET 718 of the data transmission buffer is in the ON state, and the via voltage is fixed to the reference power supply voltage VSS.
  • the rise detection circuit 712 outputs the start signal 731 as in the case of the first embodiment, and the latch circuit 711 receives the data input signal and outputs it to the NAND circuit 715.
  • the control register 714 is set by the activation signal 731, and a signal “1” from the register is output to the NAND circuit 715.
  • the pMOSFET 717 is turned on by the signal (733) from the NAND circuit 715.
  • the nMOSFET 718 is turned off via the inverter circuit 716.
  • the pMOSFET 719 of the clock transmission buffer is turned on to raise the potential on the through via.
  • the voltage detection circuit 713 detects it, and the control register 714 is reset by the inhibition signal 732 that is the output.
  • the output of the register becomes “0”
  • the output (733) of the NAND circuit 715 connected thereto becomes “0”
  • the pMOSFET 717 of the data transmission buffer is turned OFF.
  • the voltage increase of the data signal through via is stopped and the voltage (for example, 0.6 VDD) is maintained.
  • the nMOSFET 718 is turned on by the precharge signal 734 from the inverter circuit 716, and the voltage of the data signal through via is forcibly precharged to VSS.
  • the truth value of the data signal from the latch circuit 711 is “0”
  • the pMOSFET 717 is always OFF, and the via voltage remains fixed at VSS.
  • the voltage value detected by the voltage detection circuit 713 is assumed to be equal to the high-level voltage value of the data output signal 735. Strictly speaking, however, the pMOSFET 717 is detected after the voltage detection circuit 713 detects. Since there is a delay time until it is driven to OFF, voltage value adjustment for that is required. Therefore, as described above, for example, the clock transmission buffer is designed to be larger than the data transmission buffer, so that the voltage rise on the clock signal through via is made faster than the data signal through via. It is also possible to compensate for the delay time.
  • the VSS precharge is performed by using the inverter circuit 716 to forcibly turn on the nMOSFET 718 during the period when the clock signal is low, as shown in the first embodiment. Alternatively, the VSS precharge may be performed using a signal obtained by delaying the inhibition signal 732.
  • the receiving unit shown in FIG. 15 includes a voltage detection circuit 721, a reference voltage source 722, a comparator circuit 723, a truth value determination circuit 724, and a delay circuit 725 similar to the control circuit 701 of the transmission unit.
  • FIG. 17 is a waveform diagram showing an operation example of the receiving unit in FIG.
  • the voltage detection circuit 721 detects the voltage of the clock input signal 745 input through the through via
  • the comparator circuit 723 is a signal (determination enable signal 724) obtained by adding a delay by the delay circuit 725 to the output (start signal 741). Start up.
  • the data input signal 744 input through the through via is compared with the reference voltage from the reference voltage source 722 by the comparator circuit 723, and the determination data signal 743 obtained as a result is input to the truth value determination circuit 724. If the delay circuit 725 is not provided, the activation of the comparator circuit 723 and the OFF operation of the pMOSFET 717 of the transmission unit are performed at substantially the same time. Further, FIG. 15 shows a case where a circuit that always outputs a reference voltage is used. However, as shown in the first embodiment, a reference voltage source that is activated only when a comparison operation is performed using an appropriate delay circuit. It may be used.
  • the semiconductor device of the second embodiment typically, when signal transmission is performed via a bus such as a through via, power consumption is reduced. High-speed signal transmission can be realized.
  • the amplitude is limited not by the delay circuit method but by the method of monitoring the voltage of the clock signal, even when the number of stacked semiconductor chips is not fixed, the number of stacked layers is reduced. Accordingly, it is not necessary to adjust the on-time of the pMOSFET 717.
  • the rise time of the data signal changes due to the change in the stray capacitance with the number of stacks
  • the rise time of the clock signal also changes in the same manner, so that the charging time can be determined reflecting the effect of the number of stacks.
  • FIG. 18A is a circuit diagram showing a configuration example thereof
  • FIG. 18B is a switch in FIG. It is a circuit diagram which shows the structural example of an attached capacitance pair.
  • 18A includes a charge pMOSFET 911, a discharge amount nMOSFET 912, a charge distribution nMOSFET 913, a control circuit for controlling on / off thereof, and one end and the other end of the nMOSFET 913.
  • a plurality of capacitance circuits 901a to 901c, 901d, and 901e connected to each other are provided.
  • each of the capacitor circuits includes a capacitor pair formed by a pMOSFET 902 and an nMOSFET 903, and a CMOS switch 904 that connects the capacitor pair to a predetermined voltage node according to a setting signal.
  • the pMOSFET 902 has a gate as an input, the source and drain are connected to the power supply voltage VDD, and the nMOSFET 903 has a gate as an input, and the source and drain are connected to the reference power supply voltage VSS.
  • the capacitance value of each capacitance circuit is set as an integer multiple of the minimum capacitance of the FETs that are configured.
  • 901b and 901c are capacitance values that are twice and four times, respectively, with the capacitance circuit 901a as a reference.
  • 901d and 901e are four times the capacitance value.
  • the operation will be described below.
  • the permission signal is always high.
  • the activation signal for example, the activation signal 351 in FIG. 6
  • the charge / discharge MOSFETs 911 and 912 are both turned on.
  • VDD is charged to the capacitor pair selected by the setting signal VSEL1 from among the capacitor pairs in the capacitor circuits 901a to 901c
  • the capacitor pair in the capacitor circuit 901e is set to VSS according to the selection by the setting signal VSEL2. Is charged.
  • the capacity pair in the capacity circuit 901d is always selected and charged to VSS.
  • the charge / discharge MOSFETs 911 and 912 are turned off, and the charge distribution nMOSFET 913 is turned on instead.
  • the charges charged in the upper capacitor pair move to the lower capacitor pair through the nMOSFET 913, and the voltages of all the capacitor pairs become the same.
  • the voltage in this state is taken out as the reference voltage VREFOUT .
  • the reference voltage V REFOUT is expressed by Expression (10).
  • ⁇ (VSEL1) is “4” when only the capacitor circuit 901c is selected, “2” when only the capacitor circuit 901b is selected, and “6” when both are selected.
  • an arbitrary voltage can be generated by switching the setting signals (VSEL1, VSEL2), and a low reference voltage can be generated on the VSS side as in this embodiment.
  • V REFOUT VDD ⁇ ( ⁇ (VSEL1) / ( ⁇ (VSEL1) + VSEL2 + 4)) (10)
  • a storage capacitor in which a pMOSFET 902 and an nMOSFET 903 are connected in series is used as a capacitor pair.
  • a single element for example, an nMOSFET grounded on the VSS side
  • the capacity rapidly decreases when the charging voltage is near VSS. Therefore, by connecting the nMOSFET to the VSS side and the pMOSFET to the VDD side, a sufficient capacity can be secured over the charging voltage between VDD and VSS.
  • FIG. 19 is a block diagram illustrating a configuration example of the transmission unit in the semiconductor device according to the fourth embodiment of the present invention.
  • FIG. 20 illustrates a configuration of the reception unit in the semiconductor device according to the fourth embodiment of the present invention. It is a block diagram which shows an example. In this example, one channel of data signal is shown for one clock signal, but the actual number of data signal channels is preferably plural.
  • the transmission unit shown in FIG. 19 includes a clock transmission buffer composed of pMOSFET 1005 and nMOSFET 1006, a data transmission buffer composed of pMOSFET 1003 and nMOSFET 1004, a control circuit 1002 for clock transmission buffer, and a control circuit 1001 for data transmission buffer. Composed.
  • the clock transmission buffer transmits a clock output signal 1050 to the through via
  • the data transmission buffer transmits a data output signal 1049 to the through via.
  • the clock transmission buffer control circuit 1002 includes a rise detection circuit 1011, a comparator circuit 1012, a reference voltage source 1013, a state control register 1014, a NAND circuit 1015, and an inverter circuit 1016.
  • the data transmission buffer control circuit 1001 includes a latch circuit 1021, a state control register 1022, a NAND circuit 1023, and an inverter circuit 1024.
  • FIG. 22 is a waveform diagram showing an operation example of the transmission unit of FIG. While the clock input signal is at the low level, the nMOSFETs 1006 and 1004 of the clock and data transmission buffers are in the ON state, and the voltage of each through via is fixed to VSS.
  • the clock input signal changes to a high level, the rising edge is detected by the detection circuit 1011, and the circuit outputs an activation signal 1041.
  • the latch circuit 1021 latches the data input signal, and when it is “1”, outputs a high level to the NAND circuit 1023.
  • control registers 1014 and 1022 are set by the activation signal 1041, and the register outputs a signal “1” to the NAND circuits 1015 and 1023.
  • the signal from the NAND circuit 1015 turns on the pMOSFET 1005 and increases the voltage on the clock signal through via, and the signal from the NAND circuit 1023 turns on the pMOSFET 1003 and raises the voltage on the data signal through via.
  • the comparator circuit 1012 detects the excess in comparison with the reference voltage, outputs the inhibition signal 1042, and resets the control register 1014. .
  • the output of the control register 1014 becomes “0”
  • the output of the NAND circuit 1015 connected thereto becomes “0”
  • the pMOSFET 1005 of the clock transmission buffer is turned off.
  • the voltage increase stops and the voltage is maintained.
  • the output of the control register 1014 does not change.
  • the control register 1022 in the data control circuit 1001 is also reset by the inhibition signal 1042, the pMOSFET 1003 is turned off via the NAND circuit 1023, and the voltage at that time is passed through the data signal. Maintained by via (data output signal 1049). Thereafter, when the clock input signal changes to the low level, the nMOSFETs 1006 and 1004 are turned on through the inverters 1016 and 1024, and the voltages of the clock output signal 1050 and the data output signal 1049 are forcibly precharged to the VSS side.
  • a differential amplifier circuit 1031 includes a differential amplifier circuit 1031, a reference voltage source 1032, and a two-stage inverter (buffer) as a part that processes an amplitude-limited clock signal, and processes a data signal.
  • a comparator circuit 1035 As parts, a comparator circuit 1035, a reference voltage source 1034, a truth value determination circuit 1036, and delay circuits 1037 and 1038 are provided.
  • FIG. 23 is a waveform diagram showing an operation example of the receiving unit of FIG.
  • the clock input signal 1052 input through the through via is differentially amplified by the differential amplifier circuit 1031 using the reference voltage from the reference voltage source 1032 as a reference.
  • the reference voltage source 1032 always maintains the activated state.
  • the clock input signal 1052 is converted into a digital signal (start signal) 1053 saturated by the differential amplifier circuit 1031 and the two stages of inverters. Based on the rising edge of the activation signal 1053, the reference voltage source 1034 on the data signal side is activated.
  • the activation signal 1053 becomes a determination enable signal 1054 via the delay circuit 1037, and the comparator circuit 1035 receives the determination enable signal 1054 and uses the data input signal 1051 input through the through via as a reference voltage source 1034. And the comparison result is input to the truth value determination circuit 1036.
  • FIG. 21 is a circuit diagram showing a configuration example of the differential amplifier circuit 1031 in FIG.
  • the differential amplifier circuit 1031 shown in FIG. 21 has a widely known configuration, depending on the MOSFET serving as the differential pair, the MOSFET serving as the load element for amplification, and the fixed voltage value (BIAS) of the gate. It is composed of a MOSFET that supplies an operating current for amplification. Since the differential amplifier circuit 1031 always performs a comparison operation, a current determined by BIAS continues to flow through the differential pair.
  • the comparator circuit 1035 to which the data signal is input and the reference voltage source 1034 consume power only at the time of startup, while the differential amplifier circuit 1031 and the reference voltage source 1032 to which the clock signal is input are always in an operating state. For this reason, the receiving circuit on the clock signal side consumes more power than the data signal side. Therefore, in order to reduce power consumption in the entire transmission circuit, it is desirable to increase the number of data signal channels with respect to one clock signal.
  • the semiconductor device of the fourth embodiment typically, when signal transmission is performed via a bus such as a through via, power consumption is reduced. High-speed signal transmission can be realized. Further, since the clock signal is monitored, it is possible to flexibly cope with a change in the number of stacked layers. Furthermore, since the amplitude of the clock signal is also limited as compared with the first and second embodiments, the power consumption accompanying charging / discharging of the clock bus can be reduced, and for the same reason as in the case of the data bus. The clock bus speed can also be increased.
  • the clock signal is transmitted with the same through via structure as the data signal, and the change in the total via load capacity caused by the change in the number of stacked layers is reflected by detecting the change in the output voltage and using it as the amplitude control signal. it can.
  • the semiconductor device according to the present embodiment is a technique that is particularly useful when applied to a stacked chip system in which a plurality of semiconductor chips are stacked and transmitted / received data through through vias.
  • the present invention is also applicable to a general bus system that transmits and receives data via bus wiring.

Abstract

Provided is a semiconductor device in which signals are transmitted via a bus such as a through-via, the semiconductor device achieving a reduction in power consumption and an increase in signal transmission speed. Specifically, when a data signal is transmitted to a through-via, the through-via is precharged to reference power supply voltage (VSS) by driving an nMOSFET (205) on, and when a data input signal is high, the high-level voltage of the through-via is limited to predetermined voltage between power supply voltage (VDD) and VSS by driving a pMOSFET (204) on only for a given period. The power consumption is reduced by limiting the amplitude of the voltage of the through-via, and the signal transmission speed is increased by limiting the amplitude during the on period of the pMOSFET (204).

Description

半導体装置Semiconductor device
　本発明は、マイクロプロセッサやメモリ等が集積された半導体装置に関わり、特に、積層搭載された複数の半導体チップ間での貫通ビアを介した信号伝送方法に関するものである。 The present invention relates to a semiconductor device in which a microprocessor, a memory, and the like are integrated, and more particularly, to a signal transmission method via through vias between a plurality of stacked semiconductor chips.
　ＣＭＯＳ（Complementary Metal Oxide Semiconductor）プロセスの大きな特徴は、素子サイズの微細化により動作速度の向上や消費電力の削減が可能となるスケーリング則にある。これまで素子の微細化により、チップあたりの速度向上や消費電力の低減を実現してきた。しかし、微細化が進むにつれてチップ性能の向上に鈍化傾向が現れてきた。その理由は、微細化そのものの限界、微細化で改善しない素子間の配線遅延および素子のリーク電流増大に伴う消費電力の増大が顕在化してきたためである。また一定規模の情報処理システムを構築する場合、１つのチップに集積できる機能に限界があるため、複数のチップを配置すると共にチップ間を接続することが必須となる。チップの配置方向はこれまで水平であり、チップ間の信号の伝送距離は最短でもチップ一辺以上の長さとなる。よって、チップあたりの動作速度が向上してもチップ間の伝送距離が長いため、システム全体での速度向上が困難であった。 A major feature of the CMOS (Complementary Metal Oxide Semiconductor) process is the scaling law that can improve the operation speed and reduce the power consumption by miniaturizing the element size. Up to now, the miniaturization of elements has realized improvement in speed per chip and reduction in power consumption. However, as miniaturization progresses, a tendency to slow down in improving chip performance has appeared. This is because the limit of miniaturization itself, the wiring delay between elements that cannot be improved by miniaturization, and the increase in power consumption accompanying the increase in the leakage current of the element have become apparent. When an information processing system of a certain scale is constructed, since there is a limit to the functions that can be integrated on one chip, it is essential to arrange a plurality of chips and connect the chips. The arrangement direction of the chips has been horizontal so far, and the transmission distance of signals between the chips is at least one side of the chip. Therefore, even if the operation speed per chip is improved, since the transmission distance between the chips is long, it is difficult to improve the speed of the entire system.
　チップ性能向上の鈍化やシステム全体の性能向上に対応するため、非特許文献１に代表される積層チップシステムが提案されている。その概要を図１に示す。これは、半導体チップ１００の上下に別の半導体チップを３次元的に積層し、チップ間を貫通ビア（導体１０１、パッド１０２、半田バンプ１０４）を介して接続することで、情報や電力を伝送する技術である。チップ内での信号の長距離配線やチップ間での信号配線をチップ直上の貫通ビアで伝送することで、チップ内の素子間の配線遅延やシステム全体でネックとなるチップ間伝送遅延を大幅に低減されることが期待できる。 A multilayer chip system represented by Non-Patent Document 1 has been proposed in order to cope with the slowdown of chip performance improvement and the performance improvement of the entire system. The outline is shown in FIG. This is because another semiconductor chip is three-dimensionally stacked above and below the semiconductor chip 100, and the chips are connected via through vias (conductor 101, pad 102, solder bump 104) to transmit information and power. Technology. Long-distance wiring of signals within a chip and signal wiring between chips are transmitted by through vias directly above the chip, greatly reducing wiring delay between elements in the chip and inter-chip transmission delay that becomes a bottleneck in the entire system It can be expected to be reduced.
　特許文献１には、図１に示したような積層チップシステムにおいて、各チップ内の貫通ビア経路上にラッチ回路を設けることで、各チップ間のデータ転送を、このラッチ回路を介したパイプライン方式で行わせる技術が示されている。この技術を用いると、例えば、貫通ビアの浮遊容量に伴う遅延の影響等が低減でき、高速なデータ転送が実現可能になる。また、特許文献２には、配線を介したドライバ回路とレシーバ回路間のデータ転送において、ドライバ回路のハイレベル側の駆動経路にゲートを固定電圧とするＭＩＳＦＥＴを挿入することで、ハイレベル側の振幅を制限する技術が示されている。これによって、例えば、配線容量の充放電に伴う消費電力を低減可能になる。さらに、特許文献３には、ＣＭＯＳ型の出力ドライバ回路において、ｐＭＯＳＦＥＴおよびｎＭＯＳＦＥＴの各ゲートを所定の論理閾値を持つ論理ゲートで駆動し、各論理ゲートの入力に出力ドライバ回路の出力電圧を帰還することで、ハイレベル側とロウレベル側の振幅を制御する技術が示されている。これによって、例えば、高速化やノイズの低減等が図れる。 In Patent Document 1, in the stacked chip system as shown in FIG. 1, by providing a latch circuit on a through via path in each chip, data transfer between the chips is performed via a pipeline via the latch circuit. The technique to be performed by the method is shown. By using this technique, for example, the influence of delay due to the floating capacitance of the through via can be reduced, and high-speed data transfer can be realized. Further, in Patent Document 2, in data transfer between a driver circuit and a receiver circuit via a wiring, a MISFET having a gate as a fixed voltage is inserted into a driving path on the high level side of the driver circuit, so that the high level side is inserted. A technique for limiting the amplitude is shown. As a result, for example, it is possible to reduce power consumption associated with charging / discharging of the wiring capacity. Further, in Patent Document 3, in a CMOS type output driver circuit, each gate of pMOSFET and nMOSFET is driven by a logic gate having a predetermined logic threshold value, and the output voltage of the output driver circuit is fed back to the input of each logic gate. Thus, a technique for controlling the amplitude on the high level side and the low level side is shown. Thereby, for example, speeding up and noise reduction can be achieved.
特開２００６－３３０９７４号公報JP 2006-330974 A 特開２００１－３３２９６８号公報JP 2001-332968 A 特開平５－５５８９３号公報Japanese Unexamined Patent Publication No. 5-55893
　図１に示したような貫通ビアを用いた半導体装置（積層チップシステム）においては、次のような問題点がある。貫通ビアは、文字通りシリコン基板の表裏を貫通する導体１０１を含み、この導体は絶縁膜１０３を介してシリコン基板と接触するため、その間に浮遊容量が生じる。図２は、図１における１チップあたりの貫通ビア周辺部の構成例を示す等価回路図である。図２に示す半導体装置では、ある半導体チップ１００に含まれる送信部１０７が貫通ビアに対して信号を出力し、この信号が各半導体チップ１００の貫通ビアを介して伝送され、その伝送信号を別の半導体チップ１００に含まれる受信部１０８が受信する。貫通ビアを用いて多層の積層チップに高速信号を伝送する場合、チップごとの貫通ビア浮遊容量１０６が加算されるため、積層するにつれてこの浮遊容量の影響が無視できなくなる。たとえば、ビア径が１０μｍ、ビア長が５０μｍ、絶縁膜（ＳｉＯ２）の厚さが１００ｎｍの場合、ビアあたりの浮遊容量は０．５３ｐＦとなる。このチップを１６層積層した場合、ビアの浮遊容量は６．５ｐＦとなり、通常のＰＡＤ配線と同等となる。 The semiconductor device (laminated chip system) using through vias as shown in FIG. 1 has the following problems. The through via literally includes a conductor 101 penetrating the front and back of the silicon substrate, and this conductor is in contact with the silicon substrate through the insulating film 103, and thus a stray capacitance is generated therebetween. FIG. 2 is an equivalent circuit diagram showing a configuration example of the peripheral portion of the through via per chip in FIG. In the semiconductor device shown in FIG. 2, the transmitter 107 included in a certain semiconductor chip 100 outputs a signal to the through via, and this signal is transmitted through the through via of each semiconductor chip 100. The receiving unit 108 included in the semiconductor chip 100 receives. When a high-speed signal is transmitted to a multilayer stacked chip using through vias, the through via floating capacitance 106 for each chip is added, so the influence of the floating capacitance cannot be ignored as the layers are stacked. For example, when the via diameter is 10 μm, the via length is 50 μm, and the thickness of the insulating film (SiO 2 ) is 100 nm, the stray capacitance per via is 0.53 pF. When 16 layers of this chip are laminated, the stray capacitance of the via becomes 6.5 pF, which is equivalent to a normal PAD wiring.
　貫通ビア浮遊容量の増加は回路の動作周波数に大きな影響を及ぼす。一般に、貫通ビア上を矩形波信号が伝送する際、信号電圧の切り替わりで立ち上がり時間と立ち下がり時間が必要となる。これらの時間は伝送路の負荷容量Ｃと出力ＦＥＴの抵抗すなわち出力抵抗Ｒで決定されるＣＲ時定数に比例する。貫通ビア浮遊容量の増加はこれらの時間の増大につながり、貫通ビア上の伝送信号における上限周波数の制限とチップから他チップに向けた伝送信号における遅延時間の増大につながる。結果として、積層数が増加するにつれて積層チップ本来の利点であったシステム全体での高速化が困難となってくる。このため、動作周波数の向上には、ＣＲ時定数の低減すなわち浮遊容量および出力抵抗の削減が必要となる。 The increase in through-via stray capacitance has a large effect on the operating frequency of the circuit. In general, when a rectangular wave signal is transmitted over a through via, a rise time and a fall time are required when the signal voltage is switched. These times are proportional to the CR time constant determined by the load capacitance C of the transmission line and the resistance of the output FET, that is, the output resistance R. An increase in through via stray capacitance leads to an increase in these times, leading to a limitation on the upper limit frequency in the transmission signal on the through via and an increase in the delay time in the transmission signal from the chip to another chip. As a result, as the number of stacked layers increases, it becomes difficult to increase the speed of the entire system, which is an inherent advantage of the stacked chip. For this reason, to improve the operating frequency, it is necessary to reduce the CR time constant, that is, to reduce the stray capacitance and the output resistance.
　また、浮遊容量増加の問題は消費電力にも大きな影響を及ぼす。一般に負荷容量ＣＬを駆動するバッファ出力段（インバータ回路）の消費電力の大部分は、負荷容量へ充放電で生じる。振幅電圧幅Ｖ、周波数ｆ、負荷容量をＣＬとした場合の、出力段の消費電力Ｐは式（１）で表される。積層数が増加すると貫通ビア浮遊容量が増大し、積層システム全体での消費電力が増大する。このため、動作周波数を維持して消費電力を低減するためには、負荷容量である貫通ビア浮遊容量ＣＬの低減と信号の振幅電圧幅の低減が必要となる。 In addition, the problem of increased stray capacitance greatly affects power consumption. Most of the power consumption of the general buffer output stage for driving a load capacitance C L (inverter circuit) occurs in the charge and discharge the load capacitor. The power consumption P of the output stage when the amplitude voltage width V, the frequency f, and the load capacitance are C L is expressed by Expression (1). As the number of stacked layers increases, the through via stray capacitance increases, and the power consumption of the entire stacked system increases. Therefore, in order to reduce power consumption while maintaining the operating frequency, it is necessary to reduce the amplitude voltage width reduction and signal a load capacitance through via stray capacitance C L.
　Ｐ＝ＣＬ×ｆ×Ｖ２　　　（１） P = C L × f × V 2 (1)
　上記の問題を解決するために、回路上の改善技術がいくつか挙げられる。まず高速化では、一般にＦＥＴのチャネル幅を広げて出力抵抗を低減しＣＲ時定数を削減する。しかし、チャネル幅の拡大に伴いＦＥＴ自体の浮遊容量の増大するため、ＣＲ時定数を効率的に削減できないばかりか、ＦＥＴの浮遊容量分だけ消費電力が増大する恐れがある。また、特許文献１に示すように、貫通ビアにラッチ回路を挿入して動作周波数を向上させる方法がある。チップごとに貫通ビア容量を分割することで、ＣＲ時定数は積層数に依存せず常に積層数1枚分となり高速化が見込める。しかし、積層チップ全体での貫通ビア浮遊容量は変わらないため消費電力は低下しない。 In order to solve the above problems, there are several circuit improvement techniques. First, in order to increase the speed, generally, the channel width of the FET is widened to reduce the output resistance and the CR time constant. However, since the stray capacitance of the FET itself increases as the channel width increases, not only can the CR time constant be reduced efficiently, but the power consumption may increase by the amount of stray capacitance of the FET. Further, as shown in Patent Document 1, there is a method of improving the operating frequency by inserting a latch circuit into a through via. By dividing the through via capacitance for each chip, the CR time constant does not depend on the number of stacked layers, and is always equal to the number of stacked layers, so that high speed can be expected. However, since the through-via stray capacitance in the entire multilayer chip does not change, power consumption does not decrease.
　一方、低消費電力化の回路技術として、振幅電圧を制限する方法がある。一般には、例えばＣＭＯＳインバータ回路の電源電圧ＶｄをＶ１に下げる方法が挙げられる。また、特許文献２のように、電源電圧Ｖｄはそのままで、制限電圧源に接続されたｎＭＩＳＦＥＴを用いて振幅をＶ１に抑制する方法が挙げられる。特許文献２では、ｐＭＩＳＦＥＴおよびｎＭＩＳＦＥＴからなるインバータにおけるｐＭＩＳＦＥＴと出力ノードの間に、電源電圧Ｖｄより低い制御電圧をゲートに印加したｎＭIＳＦＥＴを挿入することで、その制御電圧以下となるＶ１に振幅を制限している。これらの方法の場合、振幅の制限に伴い消費電力は低下する。 On the other hand, there is a method of limiting the amplitude voltage as a circuit technology for reducing power consumption. In general, for example, there is a method of reducing the power supply voltage Vd of the CMOS inverter circuit to V1. Further, as in Patent Document 2, there is a method of suppressing the amplitude to V1 using an nMISFET connected to a limiting voltage source while keeping the power supply voltage Vd as it is. In Patent Document 2, by inserting an nMISFET having a control voltage lower than the power supply voltage Vd applied to the gate between the pMISFET and the output node in the inverter composed of pMISFET and nMISFET, the amplitude is limited to V1 which is lower than the control voltage. is doing. In these methods, the power consumption decreases as the amplitude is limited.
　しかしながら、電源電圧を下げる方法では、負荷容量を充電する際の動作電圧自体が低い電圧Ｖ１となる（すなわちｐＭＩＳＦＥＴがオンした時点の当該ソース・ドレイン間電圧がＶ１となる）ため、ＣＲ時定数で決定される信号の立ち上がり時間を改善することはできない。また、特許文献２では、ｐＭＩＳＦＥＴと挿入されたｎＭＩＳＦＥＴの直列２段接続を介して充電が行われるため、その抵抗が高くなり、ＣＲ時定数が大きくなると共に立ち上がり時間が遅延することになる。 However, in the method of reducing the power supply voltage, the operating voltage itself when charging the load capacitance becomes a low voltage V1 (that is, the source-drain voltage when the pMISFET is turned on becomes V1). The rise time of the determined signal cannot be improved. In Patent Document 2, since charging is performed through a two-stage connection in series of a pMISFET and an inserted nMISFET, the resistance increases, the CR time constant increases, and the rise time is delayed.
　一方、特許文献３では、特許文献２のような２段構成ではなく、１段構成（ｐＭＯＳＦＥＴ）を用いて負荷容量を充電でき、振幅の制限によって高速化を図っている。しかしながら、ハイレベルとロウレベルの両方で振幅制限を行っているため、負荷容量を充電する際の実質的な動作電圧は低い電圧Ｖ１となる。すなわち、電源電圧をＶｄ、ロウレベルの電圧をＶＬとするとｐＭＩＳＦＥＴがオンした時点の当該ソース・ドレイン間電圧Ｖ１は、Ｖｄよりも低い電圧（Ｖｄ－ＶＬ）となる。これにより、立ち上がり時間が遅延する。さらに、特許文献３では、製造ばらつきに対するマージンが低下する恐れがある。すなわち、通常、信号の判定レベルはハイレベルとロウレベルの中間に設定されるが、ハイレベルおよびロウレベル共に製造ばらつきによってばらつく恐れがあるため、判定レベルのマージンが十分に確保できない恐れがある。 On the other hand, in Patent Document 3, the load capacitance can be charged using a single-stage configuration (pMOSFET) instead of the two-stage configuration as in Patent Document 2, and the speed is increased by limiting the amplitude. However, since the amplitude is limited at both the high level and the low level, the substantial operating voltage when charging the load capacitance is the low voltage V1. That is, when the power supply voltage is Vd and the low level voltage is VL, the source-drain voltage V1 when the pMISFET is turned on is a voltage (Vd−VL) lower than Vd. This delays the rise time. Furthermore, in Patent Document 3, there is a risk that the margin for manufacturing variations may be reduced. In other words, the determination level of the signal is normally set between the high level and the low level, but both the high level and the low level may vary due to manufacturing variations, so there is a possibility that a sufficient margin for the determination level cannot be secured.
　本発明は、このようなことを鑑みてなされたものであり、その目的の一つは、貫通ビア等のバスを介して信号伝送を行う半導体装置において、消費電力の低減と共に信号伝送の高速化を実現することにある。本発明の前記並びにその他の目的と新規な特徴は、本明細書の記述及び添付図面から明らかになるであろう。 The present invention has been made in view of the above, and one of its purposes is to reduce power consumption and increase the speed of signal transmission in a semiconductor device that performs signal transmission via a bus such as a through via. Is to realize. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
　本願において開示される発明のうち、代表的な実施の形態の概要を簡単に説明すれば、次のとおりである。 Among the inventions disclosed in the present application, the outline of a typical embodiment will be briefly described as follows.
　本実施の形態による半導体装置は、貫通ビアによる積層チップシステムにおいて、貫通ビアと電源電圧ＶＤＤ間に接続されたｐＭＯＳＦＥＴ、及び貫通ビアと基準電源電圧ＶＳＳ間に接続されたｎＭＯＳＦＥＴからなる送信バッファ回路と、ロウレベルがＶＳＳ、ハイレベルがＶＤＤ×Ｋ（０．０＜Ｋ＜１．０）となるように各ＦＥＴのオン・オフ時間を制御する制御回路とを備えたものとなっている。 The semiconductor device according to the present embodiment includes a transmission buffer circuit including a pMOSFET connected between the through via and the power supply voltage VDD, and an nMOSFET connected between the through via and the reference power supply voltage VSS in the stacked chip system using the through via. And a control circuit for controlling the on / off time of each FET so that the low level is VSS and the high level is VDD × K (0.0 <K <1.0).
　この制御回路による制御方法は２種類ある。１つは貫通ビアの負荷に応じた遅延回路を用いて各ＦＥＴを一定期間ＯＮ／ＯＦＦし、振幅を制限する方法である。もう１つは、参照信号（例えばクロック信号）とデータ信号の貫通ビアを同一の構造とし、その参照信号の電圧状態を検出することで、貫通ビアの負荷容量を反映しながらデータ用送信バッファを制御して振幅制限する方法である。 There are two types of control methods using this control circuit. One is a method of limiting the amplitude by turning on / off each FET for a certain period using a delay circuit according to the load of the through via. The other is that the reference signal (for example, clock signal) and data signal through-vias have the same structure, and the voltage state of the reference signal is detected, so that the data transmission buffer is reflected while reflecting the load capacity of the through-via. This is a method of controlling and limiting the amplitude.
　本実施の形態による貫通ビア伝送回路の送信部の概要を図３に示す。通信方式の前提として、データ信号はクロック信号に同期して入力される。クロック用送信バッファ（図３ではｐＭＯＳＦＥＴ２０２およびｎＭＯＳＦＥＴ２０３で構成したインバータ）は、クロック入力信号を受けて貫通ビアを駆動することでクロック信号を伝送し、このクロック信号の伝送にはその振幅電圧が電源電圧ＶＤＤ～基準電源電圧ＶＳＳまで振れる従来の駆動方式が用いられる。一方、データ用送信バッファ（図３ではｐＭＯＳＦＥＴ２０４およびｎＭＯＳＦＥＴ２０５）は、貫通ビアに対して振幅が制限されたデータ信号を送信できるようにｐＭＯＳＦＥＴ２０４およびｎＭＯＳＦＥＴ２０５のゲートが独立に制御され、その振幅電圧はＫ×ＶＤＤ～ＶＳＳの範囲で制限される。 FIG. 3 shows an outline of the transmission unit of the through via transmission circuit according to this embodiment. As a premise of the communication system, the data signal is input in synchronization with the clock signal. The clock transmission buffer (inverter composed of pMOSFET 202 and nMOSFET 203 in FIG. 3) receives the clock input signal and drives the through via to transmit the clock signal, and the amplitude voltage of the clock signal is transmitted to the power supply voltage. A conventional driving method that swings from VDD to the reference power supply voltage VSS is used. On the other hand, in the data transmission buffer (pMOSFET 204 and nMOSFET 205 in FIG. 3), the gates of the pMOSFET 204 and the nMOSFET 205 are independently controlled so that a data signal whose amplitude is limited to the through via can be transmitted. Limited in the range of VDD to VSS.
　第１の制御方法を用いる場合、制御回路２０１は、まず、クロック信号がロウレベルの場合は、ｎＭＯＳＦＥＴ２０５をオン、ｐＭＯＳＦＥＴ２０４をオフに駆動する。これによって貫通ビア電圧はＶＳＳとなる。その後、クロック信号がロウレベルからハイレベルに立ち上がると、制御回路２０１は、データ入力信号がロウレベルの場合には、前述した各ＦＥＴの状態を維持する。一方、データ入力信号がハイレベルの場合、制御回路２０１は、クロック信号の立ち上がりを受けてｎＭＯＳＦＥＴ２０５をオフにすると共に、その内部に設けた遅延回路によって貫通ビア電圧がＫ×ＶＤＤに達するのに必要な期間ｐＭＯＳＦＥＴ２０４をオンにし、その後オフにする。次いで、クロック信号がロウレベルに立ち下がると、前述したように、制御回路２０１は、ｎＭＯＳＦＥＴ２０５をオンにして貫通ビア電圧をＶＳＳに戻す。 When the first control method is used, the control circuit 201 first drives the nMOSFET 205 on and the pMOSFET 204 off when the clock signal is at a low level. As a result, the through via voltage becomes VSS. Thereafter, when the clock signal rises from the low level to the high level, the control circuit 201 maintains the state of each FET described above when the data input signal is at the low level. On the other hand, when the data input signal is at a high level, the control circuit 201 turns off the nMOSFET 205 in response to the rising edge of the clock signal, and is necessary for the through via voltage to reach K × VDD by the delay circuit provided therein. The pMOSFET 204 is turned on for a short period and then turned off. Next, when the clock signal falls to the low level, as described above, the control circuit 201 turns on the nMOSFET 205 and returns the through via voltage to VSS.
　第２の制御方法を用いる場合は、前提として、クロック信号とデータ信号を伝送する貫通ビアを同一の構造とする。制御回路２０１は、クロック用送信バッファの入力となるクロック入力信号（２５１）の遷移と、出力となるビア上のクロック出力信号（２５２）の電圧をモニタする。制御回路２０１は、まず、クロック入力信号がロウレベルの場合は、ｎＭＯＳＦＥＴ２０５をオン、ｐＭＯＳＦＥＴ２０４をオフに駆動する。これによって貫通ビア電圧はＶＳＳとなる。その後、クロック入力信号がロウレベルからハイレベルに立ち上がると、制御回路２０１は、データ入力信号がロウレベルの場合には、前述した各ＦＥＴの状態を維持する。一方、データ入力信号がハイレベルの場合、制御回路２０１は、クロック入力信号の立ち上がりを受けてｎＭＯＳＦＥＴ２０５をオフにすると共に、ｐＭＯＳＦＥＴ２０４を一定期間オンにした後オフにする。このｐＭＯＳＦＥＴ２０４をオンからオフに切り替えるタイミングは、ビア上のクロック出力信号（２５２）の電圧をモニタした結果に基づいて、データ信号用貫通ビアの電圧がＫ×ＶＤＤに達したと推定されるタイミングである。次いで、クロック入力信号がロウレベルに立ち下がると、前述したように、制御回路２０１は、ｎＭＯＳＦＥＴ２０５をオンにして貫通ビア電圧をＶＳＳに戻す。 When using the second control method, it is assumed that the through vias for transmitting the clock signal and the data signal have the same structure. The control circuit 201 monitors the transition of the clock input signal (251) as an input of the clock transmission buffer and the voltage of the clock output signal (252) on the via as an output. First, when the clock input signal is at a low level, the control circuit 201 drives the nMOSFET 205 on and the pMOSFET 204 off. As a result, the through via voltage becomes VSS. Thereafter, when the clock input signal rises from the low level to the high level, the control circuit 201 maintains the state of each FET described above when the data input signal is at the low level. On the other hand, when the data input signal is at a high level, the control circuit 201 turns off the nMOSFET 205 in response to the rising edge of the clock input signal, and turns off the pMOSFET 204 after turning it on for a certain period. The timing at which the pMOSFET 204 is switched from on to off is the timing at which the voltage of the data signal through via reaches K × VDD based on the result of monitoring the voltage of the clock output signal (252) on the via. is there. Next, when the clock input signal falls to the low level, as described above, the control circuit 201 turns on the nMOSFET 205 and returns the through via voltage to VSS.
　本実施の形態による貫通ビア伝送回路の受信部の概要を図４に示す。貫通ビアを経由して入力されたクロック入力信号は、データ信号側のコンパレータ回路（受信バッファ）２１１の起動信号（判定タイミング）２５３として用いられ、場合によっては基準電圧源２１２の起動信号２５３としても用いられる。貫通ビアを経由して入力されたデータ信号は、判定タイミングにおいてコンパレータ回路２１１により基準電圧と比較され、ラッチ回路２１３を経て出力される。受信部では、振幅制限されたデータ信号を基準電圧と比較して真理値を決定する。 FIG. 4 shows an outline of the receiving unit of the through via transmission circuit according to this embodiment. The clock input signal input through the through via is used as a start signal (determination timing) 253 of the comparator circuit (reception buffer) 211 on the data signal side. In some cases, it is also used as the start signal 253 of the reference voltage source 212. Used. The data signal input via the through via is compared with the reference voltage by the comparator circuit 211 at the determination timing, and is output via the latch circuit 213. The receiving unit determines the truth value by comparing the amplitude-limited data signal with the reference voltage.
　本願において開示される発明のうち、代表的な実施の形態によって得られる効果を簡単に説明すると、貫通ビア等のバスを介して信号伝送を行う半導体装置において、消費電力の低減と共に信号伝送の高速化が実現可能になる。 Of the inventions disclosed in this application, the effects obtained by the representative embodiments will be briefly described. In a semiconductor device that performs signal transmission through a bus such as a through via, power consumption is reduced and signal transmission is performed at high speed. Can be realized.
本発明の前提として検討した半導体装置において、その断面構造の一例を示す概略図である。In the semiconductor device examined as a premise of the present invention, it is the schematic diagram showing an example of the section structure. 図１における１チップあたりの貫通ビア周辺部の構成例を示す等価回路図である。FIG. 2 is an equivalent circuit diagram illustrating a configuration example of a peripheral portion of a through via per chip in FIG. 1. 本発明の一実施の形態による半導体装置において、その送信部の概略構成例を示すブロック図である。In the semiconductor device by one embodiment of this invention, it is a block diagram which shows the schematic structural example of the transmission part. 本発明の一実施の形態による半導体装置において、その受信部の概略構成例を示すブロック図である。In the semiconductor device by one embodiment of this invention, it is a block diagram which shows the schematic structural example of the receiving part. 本発明の実施の形態１による半導体装置において、その送信部の構成例を示すブロック図である。FIG. 3 is a block diagram illustrating a configuration example of a transmission unit in the semiconductor device according to the first embodiment of the present invention. 本発明の実施の形態１による半導体装置において、その受信部の構成例を示すブロック図である。FIG. 3 is a block diagram illustrating a configuration example of a receiving unit in the semiconductor device according to the first embodiment of the present invention. 図６の受信部において、そのコンパレータ回路の構成例を示す回路図である。FIG. 7 is a circuit diagram illustrating a configuration example of the comparator circuit in the receiving unit of FIG. 6. 図５の送信部の動作例を示す波形図である。FIG. 6 is a waveform diagram illustrating an operation example of the transmission unit in FIG. 5. 図６の受信部の動作例を示す波形図である。FIG. 7 is a waveform diagram illustrating an operation example of the reception unit in FIG. 6. 送信バッファと貫通ビアを等価的に表す回路図である。It is a circuit diagram equivalently showing a transmission buffer and a penetration via. 信号の立ち上がり時間と立ち下り時間の規定を示す説明図である。It is explanatory drawing which shows prescription | regulation of the rise time and fall time of a signal. 本発明の実施の形態１による半導体装置において、動作周波数に対する消費電力値を検証した結果を示すグラフである。5 is a graph showing a result of verifying a power consumption value with respect to an operating frequency in the semiconductor device according to the first embodiment of the present invention. 本発明の実施の形態１による半導体装置において、動作周波数を満たすのに必要なＦＥＴ幅を検証した結果を示すグラフである。5 is a graph showing a result of verifying an FET width necessary to satisfy an operating frequency in the semiconductor device according to the first embodiment of the present invention. 本発明の実施の形態２による半導体装置において、その送信部の構成例を示すブロック図である。In the semiconductor device by Embodiment 2 of this invention, it is a block diagram which shows the structural example of the transmission part. 本発明の実施の形態２による半導体装置において、その受信部の構成例を示すブロック図である。In the semiconductor device by Embodiment 2 of this invention, it is a block diagram which shows the structural example of the receiving part. 図１４の送信部の動作例を示す波形図である。It is a wave form diagram which shows the operation example of the transmission part of FIG. 図１５の受信部の動作例を示す波形図である。It is a wave form diagram which shows the operation example of the receiving part of FIG. 本発明の実施の形態３による半導体装置において、その受信部の基準電圧源を示すものであり、（ａ）はその構成例を示す回路図、（ｂ）は（ａ）におけるスイッチ付き容量対の構成例を示す回路図である。In the semiconductor device by Embodiment 3 of this invention, it shows the reference voltage source of the receiving part, (a) is a circuit diagram which shows the example of a structure, (b) is a capacitance pair with a switch in (a). It is a circuit diagram which shows a structural example. 本発明の実施の形態４による半導体装置において、その送信部の構成例を示すブロック図である。In the semiconductor device by Embodiment 4 of this invention, it is a block diagram which shows the structural example of the transmission part. 本発明の実施の形態４による半導体装置において、その受信部の構成例を示すブロック図である。In the semiconductor device by Embodiment 4 of this invention, it is a block diagram which shows the structural example of the receiving part. 図２０における差動増幅回路の構成例を示す回路図である。FIG. 21 is a circuit diagram illustrating a configuration example of a differential amplifier circuit in FIG. 20. 図１９の送信部の動作例を示す波形図である。It is a wave form diagram which shows the operation example of the transmission part of FIG. 図２０の受信部の動作例を示す波形図である。It is a wave form diagram which shows the operation example of the receiving part of FIG. 本発明の一実施の形態による半導体装置において、その効果の一例を説明する概念図である。It is a conceptual diagram explaining an example of the effect in the semiconductor device by one embodiment of the present invention.
　以下の実施の形態においては便宜上その必要があるときは、複数のセクションまたは実施の形態に分割して説明するが、特に明示した場合を除き、それらは互いに無関係なものではなく、一方は他方の一部または全部の変形例、詳細、補足説明等の関係にある。また、以下の実施の形態において、要素の数等（個数、数値、量、範囲等を含む）に言及する場合、特に明示した場合および原理的に明らかに特定の数に限定される場合等を除き、その特定の数に限定されるものではなく、特定の数以上でも以下でも良い。同様に、以下の実施の形態において、構成要素等の形状、位置関係等に言及するときは、特に明示した場合および原理的に明らかにそうでないと考えられる場合等を除き、実質的にその形状等に近似または類似するもの等を含むものとする。このことは、上記数値および範囲についても同様である。 In the following embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant, and one is the other. Some or all of the modifications, details, supplementary explanations, and the like are related. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.
　また、実施の形態の各機能ブロックを構成する回路素子は、特に制限されないが、公知のＣＭＯＳ（相補型ＭＯＳトランジスタ）等の集積回路技術によって、単結晶シリコンのような半導体基板上に形成される。なお、実施の形態では、ＭＩＳＦＥＴ（Metal Insulator Semiconductor Field Effect Transistor）の一例としてＭＯＳＦＥＴ（Metal Oxide Semiconductor Field Effect Transistor）を用いる。図面において、Ｐチャネル型ＭＯＳＦＥＴ（ｐＭＯＳＦＥＴ）にはゲートに丸印の記号を付すことで、Ｎチャネル型ＭＯＳＦＥＴ（ｎＭＯＳＦＥＴ）と区別することとする。図面にはＭＯＳＦＥＴの基板電位の接続は特に明記していないが、ＭＯＳＦＥＴが正常動作可能な範囲であれば、その接続方法は特に限定しない。 The circuit elements constituting each functional block of the embodiment are not particularly limited, but are formed on a semiconductor substrate such as single crystal silicon by a known integrated circuit technology such as a CMOS (complementary MOS transistor). . In the embodiment, a MOSFET (Metal / Oxide / Semiconductor / Field / Effect / Transistor) is used as an example of a MISFET (Metal / Insulator / Semiconductor / Field / Effect / Transistor). In the drawing, a P-channel MOSFET (pMOSFET) is distinguished from an N-channel MOSFET (nMOSFET) by adding a circle symbol to the gate. The connection of the substrate potential of the MOSFET is not particularly specified in the drawing, but the connection method is not particularly limited as long as the MOSFET can operate normally.
　以下、本発明の実施の形態を図面に基づいて詳細に説明する。なお、実施の形態を説明するための全図において、同一の部材には原則として同一の符号を付し、その繰り返しの説明は省略する。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.
　（実施の形態１）
　図５は、本発明の実施の形態１による半導体装置において、その送信部の構成例を示すブロック図であり、図６は、本発明の実施の形態１による半導体装置において、その受信部の構成例を示すブロック図である。図５、図６は、それぞれ、図２に示した送信部１０７、受信部１０８に対応するものである。本実施の形態１では、データ信号の送信バッファ回路内のＦＥＴを遅延回路で制御する場合について説明する。図５、図６では、１本のクロック信号に対して１チャネル分のデータ信号を示しているが、実際のデータ信号チャネル数は複数でもかまわない。 (Embodiment 1)
FIG. 5 is a block diagram showing a configuration example of the transmitting unit in the semiconductor device according to the first embodiment of the present invention. FIG. 6 shows a configuration of the receiving unit in the semiconductor device according to the first embodiment of the present invention. It is a block diagram which shows an example. 5 and 6 correspond to the transmitting unit 107 and the receiving unit 108 shown in FIG. 2, respectively. In the first embodiment, a case where the FET in the data signal transmission buffer circuit is controlled by the delay circuit will be described. In FIGS. 5 and 6, data signals for one channel are shown for one clock signal, but the actual number of data signal channels may be plural.
　図５に示す送信部は、ｐＭＯＳＦＥＴ３２０とｎＭＯＳＦＥＴ３２１で構成したクロック用送信バッファと、ｐＭＯＳＦＥＴ３１８とｎＭＯＳＦＥＴ３１９で構成したデータ用送信バッファと、データ用送信バッファの制御回路３０１等で構成される。クロック用送信バッファは、貫通ビアに対してクロック出力信号３３７を送信し、データ用送信バッファは、貫通ビアに対してデータ出力信号３３６を送信する。制御回路３０１は、ラッチ回路３１１、立ち上がり検出回路３１２、遅延回路３１３、遅延回路３１４、状態制御レジスタ３１５、状態制御レジスタ３１６、ＮＡＮＤ回路３１７で構成される。データチャネルが複数ある場合は、立ち上がり検出回路３１２、遅延回路３１３，３１４はチャネル間で共有できる。データ用送信バッファを構成するＭＯＳＦＥＴ３１８、３１９は、クロック用送信バッファのＭＯＳＦＥＴ３２０，３２１よりチャネル幅を小さく構成してもよい。 The transmission unit shown in FIG. 5 includes a clock transmission buffer composed of a pMOSFET 320 and an nMOSFET 321, a data transmission buffer composed of a pMOSFET 318 and an nMOSFET 319, a control circuit 301 for the data transmission buffer, and the like. The clock transmission buffer transmits a clock output signal 337 to the through via, and the data transmission buffer transmits a data output signal 336 to the through via. The control circuit 301 includes a latch circuit 311, a rising edge detection circuit 312, a delay circuit 313, a delay circuit 314, a state control register 315, a state control register 316, and a NAND circuit 317. When there are a plurality of data channels, the rise detection circuit 312 and the delay circuits 313 and 314 can be shared between the channels. The MOSFETs 318 and 319 constituting the data transmission buffer may be configured to have a smaller channel width than the MOSFETs 320 and 321 of the clock transmission buffer.
　図８は、図５の送信部の動作例を示す波形図である。クロック入力信号がロウレベルの間は、データ用送信バッファのｎＭＯＳＦＥＴ３１９がＯＮ状態であり、貫通ビア電圧は基準電源電圧ＶＳＳに固定されている。またレジスタ３１６も、この場合、ｎＭＯＳＦＥＴ３１９がＯＮ状態になるよう初期化されている。クロック入力信号がハイレベルに変化した場合、その立ち上がりは検出回路３１２で検出される。検出回路３１２は、クロック信号の立ち上がりを検出できるものであれば何でもよく、例えばインバータ等が挙げられる。 FIG. 8 is a waveform diagram showing an operation example of the transmission unit of FIG. While the clock input signal is at the low level, the nMOSFET 319 of the data transmission buffer is in the ON state, and the through via voltage is fixed to the reference power supply voltage VSS. In this case, the register 316 is also initialized so that the nMOSFET 319 is turned on. When the clock input signal changes to a high level, the rising edge is detected by the detection circuit 312. The detection circuit 312 may be anything as long as it can detect the rising edge of the clock signal, and examples thereof include an inverter.
　検出回路３１２の出力となる起動信号３３１により、ラッチ回路３１１はデータ入力信号を取り込みＮＡＮＤ回路３１７に向けて出力する。同時に起動信号３３１は制御レジスタ３１５をＳＥＴして同レジスタより信号“１”をＮＡＮＤ回路３１７に出力する。ラッチ回路３１１で取り込んだデータ信号の真理値が“１”である場合、ＮＡＮＤ回路３１７からの制御信号３３４でｐＭＯＳＦＥＴ３１８がＯＮになる。さらに起動信号３３１により状態制御レジスタ３１６はＲＥＳＥＴされ、ｎＭＯＳＦＥＴ３１９はＯＦＦ状態となる。 The latch circuit 311 takes in the data input signal and outputs it to the NAND circuit 317 in response to the start signal 331 that is output from the detection circuit 312. At the same time, the activation signal 331 sets the control register 315 and outputs a signal “1” from the register to the NAND circuit 317. When the truth value of the data signal fetched by the latch circuit 311 is “1”, the pMOSFET 318 is turned on by the control signal 334 from the NAND circuit 317. Furthermore, the state control register 316 is reset by the activation signal 331, and the nMOSFET 319 is turned off.
　起動信号３３１は、遅延回路３１３によって一定時間遅延され、これによって、抑止信号３３２が生成される。抑止信号３３２はレジスタ３１５をＲＥＳＥＴする。その結果、レジスタの出力は“０”となり、ＮＡＮＤ回路３１７を経てデータ用送信バッファのｐＭＯＳＦＥＴ３１８はＯＦＦとなる。この時点でデータ信号用貫通ビア（データ出力信号３３６）の充電はストップし、その電圧を維持する。つぎに抑止信号３３２は、２番目の遅延回路３１４に入力され、さらに遅れたプリチャージ信号３３３により、レジスタ３１６をＳＥＴする。このためｎＭＯＳＦＥＴ３１９がＯＮ状態となり、データ信号用貫通ビアは強制的にＶＳＳにプリチャージされる。また、ラッチ回路３１１からのデータ信号の真理値が“０”であった場合、常にｐＭＯＳＦＥＴ３１８はＯＦＦになっておりデータ信号用貫通ビアの電圧はＶＳＳに固定されたままである。なお、図５では、２つの遅延回路３１３，３１４を用いてプリチャージ信号３３３を生成したが、単にクロック信号のロウレベルを検出してプリチャージ信号３３３を生成する方式であってもよい。 The activation signal 331 is delayed for a certain time by the delay circuit 313, whereby the inhibition signal 332 is generated. The inhibit signal 332 resets the register 315. As a result, the output of the register becomes “0”, and the pMOSFET 318 of the data transmission buffer is turned OFF via the NAND circuit 317. At this time, charging of the data signal through via (data output signal 336) is stopped and the voltage is maintained. Next, the inhibition signal 332 is input to the second delay circuit 314, and the register 316 is set by the delayed precharge signal 333. Therefore, the nMOSFET 319 is turned on, and the data signal through via is forcibly precharged to VSS. When the truth value of the data signal from the latch circuit 311 is “0”, the pMOSFET 318 is always OFF and the voltage of the data signal through via remains fixed at VSS. In FIG. 5, the precharge signal 333 is generated using the two delay circuits 313 and 314. However, a system in which the precharge signal 333 is generated by simply detecting the low level of the clock signal may be used.
　一方、図６に示す受信部は、送信部の制御回路３０１と同様の立ち上がり検出回路３４１、基準電圧源３４２、コンパレータ回路３４３、真理値確定回路（ラッチ回路）３４４および遅延回路３４５等で構成される。立ち上がり検出回路３４１は、貫通ビアから受信したクロック入力信号３５５の立ち上がりを検出し、特に限定はされないが、例えばインバータ回路等で構成される。図９は、図６の受信部の動作例を示す波形図である。立ち上がり検出回路３４１の出力となる起動信号３５１により、まず基準電圧源３４２が起動する。その後、遅延回路３４５を経て遅れた判定イネーブル信号３５２によりコンパレータ回路３４３が起動する。貫通ビア経由で入力されたデータ入力信号３５４は、ラッチ型のコンパレータ回路３４３にて基準電圧源３４２からの基準電圧と比較され、その結果である判定データ信号３５３が真理値確定回路３４４に入力される。 On the other hand, the reception unit shown in FIG. 6 includes a rise detection circuit 341, a reference voltage source 342, a comparator circuit 343, a truth value determination circuit (latch circuit) 344, a delay circuit 345, and the like, similar to the control circuit 301 of the transmission unit. The The rising edge detection circuit 341 detects the rising edge of the clock input signal 355 received from the through via, and is not particularly limited. For example, the rising edge detection circuit 341 includes an inverter circuit. FIG. 9 is a waveform diagram illustrating an operation example of the receiving unit in FIG. First, the reference voltage source 342 is activated by the activation signal 351 that is the output of the rise detection circuit 341. Thereafter, the comparator circuit 343 is activated by the determination enable signal 352 delayed through the delay circuit 345. The data input signal 354 input through the through via is compared with the reference voltage from the reference voltage source 342 by the latch type comparator circuit 343, and the determination data signal 353 as a result is input to the truth value determination circuit 344. The
　図５および図６の構成例は、回路規模が小さいので、特に、半導体チップの積層数が固定されており、積層数の変化が起きない半導体装置に対して有効である。これは、積層数に応じて、貫通ビアの浮遊容量が変化するため、図５におけるｐＭＯＳトランジスタ３１８のＯＮ時間を規定する遅延回路３１３等に必要な遅延時間が積層数に応じて変化するためである。ただし、この遅延時間を可変遅延回路を用いて定めることで、積層数の変化に対応することもできる。 5 and 6 are effective particularly for a semiconductor device in which the number of stacked semiconductor chips is fixed and the number of stacked layers does not change because the circuit scale is small. This is because the stray capacitance of the through via changes according to the number of stacked layers, and therefore the delay time required for the delay circuit 313 and the like that defines the ON time of the pMOS transistor 318 in FIG. 5 changes according to the number of stacked layers. is there. However, this delay time can be determined by using a variable delay circuit to cope with a change in the number of stacked layers.
　図７は、図６の受信部において、そのコンパレータ回路３４３の構成例を示す回路図である。図７に示すコンパレータ回路は、所謂、ＣＭＯＳクロスカップル型のセンスアンプ回路と、それに入力信号を接続する入力スイッチと、それに電源（電源電圧ＶＤＤ、基準電源電圧ＶＳＳ）を接続する電源スイッチと、その出力信号をラッチするフリップフロップによって構成される。図６の判定イネーブル信号（ＳＥＮＳＥ）３５２がロウの間、入力信号はセンスアンプ回路に接続されるが、電源からは分離されている。一方、ＳＥＮＣＥがハイになると、入力信号は分離され、電源が接続される。この瞬間、入力信号間のわずかな電圧差がＶＤＤ－ＶＳＳ間レベルまで増幅され、真理値が確定する。そして、その真理値は、後段のフリップフロップによってラッチされる。 FIG. 7 is a circuit diagram showing a configuration example of the comparator circuit 343 in the receiving unit of FIG. The comparator circuit shown in FIG. 7 includes a so-called CMOS cross-coupled sense amplifier circuit, an input switch for connecting an input signal thereto, a power switch for connecting a power supply (power supply voltage VDD, reference power supply voltage VSS) to the switch, It is constituted by a flip-flop that latches an output signal. While the determination enable signal (SENSE) 352 in FIG. 6 is low, the input signal is connected to the sense amplifier circuit, but is separated from the power supply. On the other hand, when SENCE goes high, the input signal is separated and the power supply is connected. At this moment, a slight voltage difference between the input signals is amplified to the level between VDD and VSS, and the truth value is determined. Then, the truth value is latched by a subsequent flip-flop.
　次に、本実施の形態による半導体装置を用いて、振幅制限を行った場合の消費電力低減効果について説明する。通常、負荷容量ＣＬを駆動する送信バッファ（インバータ回路）の消費電力の大部分は、負荷容量へ充放電電流で生じる。よって電源電圧ＶＤＤ、周波数f、負荷容量をＣＬとした場合の消費電力Ｐは、前述した式（１）で表される。ここで、振幅を制限し、出力振幅をＶ’（＜ＶＤＤ）とした場合、その消費電力Ｐは式（２）で表され、ＶＤＤに対する制限幅の割合で消費電力が低減できる。 Next, the power consumption reduction effect when amplitude limitation is performed using the semiconductor device according to the present embodiment will be described. Usually, most of the power consumption of the transmission buffer (inverter circuit) for driving a load capacitance C L is caused by the charging and discharging current to the load capacitance. Thus the power consumption P in the case where the power supply voltage VDD, the frequency f, and the load volume to C L is expressed by the formula (1) described above. Here, when the amplitude is limited and the output amplitude is V ′ (<VDD), the power consumption P is expressed by Equation (2), and the power consumption can be reduced by the ratio of the limit width to VDD.
　Ｐ＝ＣＬ×ｆ×Ｖ’×ＶＤＤ　　　（２） P = C L × f × V ′ × VDD (2)
　次に、本実施の形態による半導体装置を用いて、振幅制限を行った場合の動作周波数の向上効果について説明する。送信バッファとそれに接続された貫通ビアは、図１０に示すＲＣ回路に近似できる。送信バッファの出力信号の論理状態が時間ｔ＝０でステップ状に変化する、すなわちｐＭＯＳＦＥＴを介して負荷容量に電流が流れる場合には、ＣＬ上の電圧ｖ（ｔ）は、式（３）に示すようにＲＣ時定数を持つ指数曲線で表される。ここで、ＲＰＭＯＳはｐＭＯＳＦＥＴの実効出力抵抗である。 Next, the effect of improving the operating frequency when the amplitude is limited using the semiconductor device according to the present embodiment will be described. The transmission buffer and the through via connected thereto can be approximated to the RC circuit shown in FIG. Logic state of the output signal of the transmission buffer is changed stepwise at time t = 0, that is, when the current flows to the load capacitance through the pMOSFET, the voltage on C L v (t) has the formula (3) As shown by an exponential curve having an RC time constant. Here, R PMOS is the effective output resistance of the pMOSFET.
　ｖ（ｔ）＝ＶＤＤ（1－ｅｘｐ（－ｔ／ＲＰＭＯＳＣＬ））　　　（３） v (t) = VDD (1−exp (−t / R PMOS C L )) (3)
　図１１に示すようにその電圧変化において、フルスケールの１０％から９０％に遷移する時間を立ち上がり時間（ｔＲ）とすると、式（３）の逆関数より式（４）となる。同様にして、ＣＬに充電された電荷がｎＭＯＳＦＥＴを介して放電された場合、フルスケールの９０％から１０％に遷移する時間を立ち下がり時間（ｔＦ）とすると、ＲＰＭＯＳがＲＮＭＯＳに変わることを除いて式（４）と同様になる。 As shown in FIG. 11, in the voltage change, when the transition time from 10% to 90% of the full scale is the rise time (t R ), Expression (4) is obtained from the inverse function of Expression (3). Similarly, if the charge accumulated in the C L is discharged through the nMOSFET, when the fall time of the transition time from 90% to 10% of full scale (t F), R PMOS within R NMOS It becomes the same as Formula (4) except changing.
　ｔＲ＝（－ｌｏｇ（１－０．９）＋ｌｏｇ（１－０．１））ＲＰＭＯＳＣＬ≒２．２ＲＰＭＯＳＣＬ　　　（４） t R = (− log (1−0.9) + log (1−0.1)) R PMOS C L ≈2.2R PMOS C L (4)
　ここから動作周波数ｆＭＡＸは、式（５）で表される。このため、動作周波数の向上には各時間の低減が必須となる。振幅を制限することで、これらの時間を低減し、結果として動作周波数の向上につながる。 From here, the operating frequency f MAX is expressed by Equation (5). For this reason, it is essential to reduce each time in order to improve the operating frequency. Limiting the amplitude reduces these times, resulting in an increase in operating frequency.
　ｆＭＡＸ＝１／（ｔＦ＋ｔＲ）　　　（５） f MAX = 1 / (t F + t R) (5)
　振幅制限を行う方式としては、ＶＳＳ側とＶＤＤ側が考えられる。本実施の形態ではＶＳＳ側での振幅制限を用いており、出力電圧は、ＶＳＳである状態が基本となり、ハイレベルを出力する際にはｐＭＯＳＦＥＴのＯＮ時間で出力電圧を調節し、その後再びｎＭＯＳＦＥＴのＯＮによりＶＳＳ電位に復帰することになる（ＶＳＳプリチャージ）。ここで、貫通ビアを接続した場合の立ち上がり時間（ｔＲ）、立ち下がり時間（ｔＦ）は、式（４）の導出と同様の方法により式（６）、式（７）であらわされる。 As a method for limiting the amplitude, the VSS side and the VDD side can be considered. In this embodiment, the amplitude limit on the VSS side is used, and the output voltage is basically in a state of VSS, and when outputting a high level, the output voltage is adjusted by the ON time of the pMOSFET, and then the nMOSFET again. The voltage is returned to the VSS potential by turning on (VSS precharge). Here, the rise time (t R ) and fall time (t F ) when through vias are connected are expressed by equations (6) and (7) in the same manner as in the derivation of equation (4).
　ｔＲ＝（－ｌｏｇ（１―Ｖ’／ＶＤＤ）＋ｌｏｇ（１－Ｖ’／ＶＤＤ×０．１））×ＲＰＭＯＳＣＬ　　　（６） t R = (− log (1−V ′ / VDD) + log (1−V ′ / VDD × 0.1)) × R PMOS C L (6)
　ｔＦ＝（－ｌｏｇ（１―０．９）＋ｌｏｇ（１－０．１））×ＲＮＭＯＳＣＬ＝２．２×ＲＮＭＯＳＣＬ　　　（７） t F = (− log (1−0.9) + log (1−0.1)) × R NMOS C L = 2.2 × R NMOS C L (7)
　一方、ＶＤＤ側での振幅制限を用いた場合、出力電圧は、ＶＤＤである状態が基本となり、ｎＭＯＳＦＥＴのＯＮ時間で出力電圧を調節し、その後再びｐＭＯＳＦＥＴのＯＮによりＶＤＤ電位まで復帰することになる（ＶＤＤプリチャージ）。この場合の各時間は、ＶＳＳプリチャージの場合と同様に式（８）、式（９）であらわされる。 On the other hand, when the amplitude limit on the VDD side is used, the output voltage is basically in the state of VDD, and the output voltage is adjusted by the ON time of the nMOSFET, and then returned to the VDD potential by turning on the pMOSFET again. (VDD precharge). Each time in this case is expressed by Expression (8) and Expression (9) as in the case of VSS precharge.
　ｔＲ＝（－ｌｏｇ（１―０．９）＋ｌｏｇ（１－０．１））×ＲＰＭＯＳＣＬ＝２．２×ＲＰＭＯＳＣＬ　　　（８） t R = (− log (1−0.9) + log (1−0.1)) × R PMOS C L = 2.2 × R PMOS C L (8)
　ｔＦ＝（－ｌｏｇ（１―Ｖ’／ＶＤＤ）＋ｌｏｇ（１－Ｖ’／ＶＤＤ×０．１））×ＲＮＭＯＳＣＬ　　　（９） t F = (− log (1−V ′ / VDD) + log (1−V ′ / VDD × 0.1)) × R NMOS C L (9)
　たとえば、ＶＳＳプリチャージ方式で、Ｖ’＝０．４×ＶＤＤの場合、立ち上がり時間は式（６）より０．５×ＲＰＭＯＳＣＬとなり、フル振幅と比較して約１／４に改善することがわかる。 For example, the VSS precharge method, when the V '= 0.4 × VDD, the rise time is improved to about 1/4 as compared 0.5 × R PMOS C L next to the equation (6), and full amplitude I understand that.
　なお、両プリチャージ方式は、それぞれ立ち上がり時間や立ち下がり時間を低減できる。しかし、ｐＭＯＳＦＥＴとｎＭＯＳＦＥＴのキャリア移動度の非対称性により、実際には本実施の形態のＶＳＳプリチャージ方式を用いた方が有利である。電子移動度はホール移動度より高く、同じチャネル幅のＦＥＴにおいて実効抵抗ＲＰＭＯＳの方がＲＮＭＯＳと比較して２倍以上高い。各方式において立ち上がり時間と立ち下がり時間を同一にする場合、ＦＥＴチャネル幅の比は、式（６）と式（７）および式（８）と式（９）の比較からＶＤＤプリチャージ方式の方が大きくなる。結果として、ＶＳＳ側制限の方がより効果的に時間を低減することができる。これにより、目的の動作周波数に対して必要なＦＥＴ幅を最小限にでき、実装面積、浮遊容量も低減され、消費電力も理論値に近い値が得られる。 Both precharge methods can reduce the rise time and fall time, respectively. However, due to the asymmetry of carrier mobility between the pMOSFET and the nMOSFET, it is actually more advantageous to use the VSS precharge system of the present embodiment. The electron mobility is higher than the hole mobility, and the effective resistance R PMOS is more than twice as high as the R NMOS in the FET having the same channel width. When the rise time and the fall time are made the same in each method, the ratio of the FET channel width is determined by the VDD precharge method based on the comparison between Equation (6) and Equation (7), and Equation (8) and Equation (9) Becomes larger. As a result, the VSS side restriction can reduce the time more effectively. As a result, the required FET width for the target operating frequency can be minimized, the mounting area and stray capacitance can be reduced, and the power consumption can be close to the theoretical value.
　また、両方プリチャージ方式の比較について概念的に説明すると、図２４のようになる。すなわち、ＶＤＤプリチャージ方式の場合、ｎＭＯＳＦＥＴは、ソース・ドレイン間電位差がＶＤＤの状態からオンとなり、ドレイン電圧が所定の中間電圧Ｖｍｉｄに到達するまでの間、主に飽和領域を用いて放電動作を行い、次いで、ｐＭＯＳＦＥＴは、ソース・ドレイン間電圧がＶＤＤ－Ｖｍｉｄの状態からオンとなり、ドレイン電圧がＶＤＤに到達するまでの間、主に非飽和領域を用いて充電動作を行う。 Also, a conceptual description of the comparison of both precharge methods is as shown in FIG. That is, in the case of the VDD precharge method, the nMOSFET is turned on from the state where the potential difference between the source and the drain is VDD, and until the drain voltage reaches the predetermined intermediate voltage Vmid, the discharge operation is mainly performed using the saturation region. Then, the pMOSFET is turned on from the state where the source-drain voltage is VDD-Vmid and the charge operation is performed mainly using the non-saturated region until the drain voltage reaches VDD.
　一方、ＶＳＳプリチャージ方式の場合、ｐＭＯＳＦＥＴは、ソース・ドレイン間電位差がＶＤＤの状態からオンとなり、ドレイン電圧がＶｍｉｄに到達するまでの間、主に飽和領域を用いて充電動作を行い、次いで、ｎＭＯＳＦＥＴは、ソース・ドレイン間電位差がＶＤＤ－Ｖｍｉｄの状態からオンとなり、ドレイン電圧がＶＳＳに到達するまでの間、主に非飽和領域を用いて放電動作を行う。一般的に、スイッチング時間は、この非飽和領域での遅延時間が大きく影響し、その遅延時間は、ｎＭＯＳＦＥＴに比べてｐＭＯＳＦＥＴの方がより大きくなる。したがって、ＶＤＤプリチャージ方式の場合は、ＶＤＤ－Ｖｍｉｄ間のスイッチ時間がＴｖｄとなるのに対して、ＶＳＳプリチャージ方式を用いた場合は、ＶＳＳ－Ｖｍｉｄ間のスイッチ時間をＴｖｄよりもΔｔだけ短いＴｖｓとすることができる。これによって高速化を実現することが可能となる。 On the other hand, in the case of the VSS precharge method, the pMOSFET is turned on from the state in which the potential difference between the source and the drain is VDD and the drain voltage reaches Vmid. The nMOSFET is turned on from the state in which the potential difference between the source and the drain is VDD−Vmid and the discharge operation is performed mainly using the non-saturated region until the drain voltage reaches VSS. In general, the switching time greatly affects the delay time in this non-saturation region, and the delay time is larger in the pMOSFET than in the nMOSFET. Therefore, in the case of the VDD precharge method, the switching time between VDD and Vmid is Tvd, whereas in the case of using the VSS precharge method, the switching time between VSS and Vmid is shorter by Δt than Tvd. Tvs. This makes it possible to increase the speed.
　なお、前述した特許文献２や特許文献３の方式と比較すると、特許文献２の場合には、充電時の直列２段接続に伴いｐＭＯＳＦＥＴ側の実効抵抗ＲＰＭＯＳが大きくなる。特許文献３の場合には、充電開始時のソース・ドレイン間電位差が小さいためｐＭＯＳＦＥＴ側の実効抵抗ＲＰＭＯＳが大きくなる。したがって、これらの場合には、図２４におけるｐＭＯＳＦＥＴの立ち上がり特性の傾きが更に鈍化することになり、本実施の形態の場合と比較して高速化が図れないことになる。 As compared with the method of Patent Document 2 and Patent Document 3 described above, in the case of Patent Document 2, the effective resistance R PMOS of the pMOSFET side with the series two-stage connection during charging increases. In the case of Patent Document 3, since the potential difference between the source and the drain at the start of charging is small, the effective resistance R PMOS on the pMOSFET side becomes large. Therefore, in these cases, the slope of the rising characteristic of the pMOSFET in FIG. 24 is further slowed down, and the speed cannot be increased as compared with the case of the present embodiment.
　また、特許文献３の方式と比較すると、本実施の形態によるＶＳＳプリチャージ方式は、製造プロセスばらつきに対するマージンの点からも有益となる。すなわち、特許文献３の方式では、ハイレベル側とロウレベル側の両方の電圧値にばらつきが生じる恐れがあったが、ＶＳＳプリチャージ方式では、ハイレベル側の電圧値のみにばらつきが生じる恐れがあるため、図６の受信部の基準電圧源３４２からの基準電圧値にある程度のマージンを持たせることが可能になる。 In addition, compared with the method of Patent Document 3, the VSS precharge method according to the present embodiment is also beneficial from the viewpoint of margin for manufacturing process variations. That is, in the method of Patent Document 3, there is a risk that the voltage value on both the high level side and the low level side may vary, but in the VSS precharge method, there is a risk that only the voltage value on the high level side may vary. Therefore, it becomes possible to give a certain margin to the reference voltage value from the reference voltage source 342 of the receiving unit in FIG.
　図１２に、動作周波数に対する消費電力値を示す。また、消費電力低減の効果の比較のためにフル振幅の場合および前述した式（１）で得られる理論値も同図にプロットした。まずフル振幅と比較して、両プリチャージ方式ともに同じ動作周波数に対して消費電力が低減できることがわかる。理論値直線に乗る限りその低減率は６０％である。さらにＶＳＳプリチャージ方式とＶＤＤプリチャージ方式の比較では、前者は動作周波数を向上させても理論値をほぼ実現できていることがわかる。これは、消費電力がほぼビア容量で消費されていることを示す。ＶＳＳプリチャージ方式でのＦＥＴのチャネル幅がＶＤＤプリチャージ方式と比較して狭くできるため、浮遊容量がビア負荷容量に対して無視できるレベルであるためである。 FIG. 12 shows the power consumption value with respect to the operating frequency. Further, for comparison of the effect of reducing power consumption, the theoretical values obtained in the case of full amplitude and the above-described equation (1) are also plotted in FIG. First, it can be seen that the power consumption can be reduced for the same operating frequency in both precharge methods as compared with the full amplitude. The reduction ratio is 60% as long as it is on the theoretical value straight line. Furthermore, a comparison between the VSS precharge method and the VDD precharge method shows that the former can substantially achieve the theoretical value even if the operating frequency is improved. This indicates that power consumption is consumed with almost via capacity. This is because the channel width of the FET in the VSS precharge method can be narrower than that in the VDD precharge method, so that the stray capacitance is at a level that can be ignored with respect to the via load capacitance.
　図１３に、動作周波数を満たすために送信バッファにおいて必要なＦＥＴ幅を示す。この幅値はｎＭＯＳＦＥＴとｐＭＯＳＦＥＴの合計値を示す。両プリチャージ方式と比較してフル振幅方式のＦＥＴ幅が３倍以上広いのは、同じ動作周波数を実現するために出力抵抗を下げる必要があるためである。また、ＶＳＳプリチャージ方式と比較してＶＤＤプリチャージ方式の幅が１．５倍広いのは、ｐＭＯＳＦＥＴとｎＭＯＳＦＥＴの比がアンバランスなためである。同図からもＶＳＳプリチャージ方式の方がもっとも狭いＦＥＴ幅で動作周波数の向上を実現できることがわかる。また、同方式のみ理論値と一致している。これらの結果は、ＶＳＳプリチャージ方式を用いると、ＶＤＤプリチャージ方式よりも消費電力をほぼ理論値に近づけることができ、かつ、必要なＦＥＴ幅も小さいためＦＥＴの浮遊容量の影響を受けにくいため、動作周波数の向上が図れることを示す。 FIG. 13 shows the FET width required in the transmission buffer to satisfy the operating frequency. This width value represents the total value of the nMOSFET and the pMOSFET. The reason why the full-amplitude FET width is three times or more wider than the two precharge methods is that it is necessary to lower the output resistance in order to achieve the same operating frequency. The reason why the VDD precharge method is 1.5 times wider than the VSS precharge method is that the ratio of pMOSFET to nMOSFET is unbalanced. It can also be seen from the figure that the VSS precharge method can improve the operating frequency with the narrowest FET width. Only the same method is consistent with the theoretical value. These results show that when the VSS precharge method is used, the power consumption can be brought closer to the theoretical value than the VDD precharge method, and the required FET width is small, so that it is less susceptible to the stray capacitance of the FET. This shows that the operating frequency can be improved.
　以上、本実施の形態１の半導体装置を用いることで、代表的には、貫通ビア等のバスを介して信号伝送を行う際に、消費電力の低減と共に信号伝送の高速化が実現可能になる。 As described above, by using the semiconductor device according to the first embodiment, typically, when signal transmission is performed via a bus such as a through via, power consumption can be reduced and signal transmission speed can be increased. .
　（実施の形態２）
　本実施の形態２では、前述したＶＳＳプリチャージ方式を用い、実施の形態１とは異なる方法で振幅制御を行う半導体装置について説明する。図１４は、本発明の実施の形態２による半導体装置において、その送信部の構成例を示すブロック図であり、図１５は、本発明の実施の形態２による半導体装置において、その受信部の構成例を示すブロック図である。図１４および図１５では、１本のクロック信号に対して１チャネル分のデータ信号を示しているが、実際のデータ信号チャネル数は複数でもかまわない。 (Embodiment 2)
In the second embodiment, a semiconductor device that uses the above-described VSS precharge method and performs amplitude control by a method different from that of the first embodiment will be described. FIG. 14 is a block diagram illustrating a configuration example of the transmission unit in the semiconductor device according to the second embodiment of the present invention. FIG. 15 illustrates a configuration of the reception unit in the semiconductor device according to the second embodiment of the present invention. It is a block diagram which shows an example. In FIG. 14 and FIG. 15, data signals for one channel are shown for one clock signal, but the actual number of data signal channels may be plural.
　図１４に示す送信部は、ｐＭＯＳＦＥＴ７１９とｎＭＯＳＦＥＴ７２０で構成したクロック用送信バッファと、ｐＭＯＳＦＥＴ７１７とｎＭＯＳＦＥＴ７１８で構成したデータ用送信バッファと、データ用送信バッファの制御回路７０１等で構成される。クロック用送信バッファは、貫通ビアに対してクロック出力信号７３６を送信し、データ用送信バッファは、貫通ビアに対してデータ出力信号７３５を送信する。制御回路７０１は、ラッチ回路７１１、立ち上がり検出回路７１２、電圧検出回路７１３、状態制御レジスタ７１４、ＮＡＮＤ回路７１５およびインバータ回路７１６で構成される。データチャネルが複数ある場合は、立ち上がり検出回路７１２および電圧検出回路７１３はチャネル間で共有できる。 14 includes a clock transmission buffer composed of a pMOSFET 719 and an nMOSFET 720, a data transmission buffer composed of a pMOSFET 717 and an nMOSFET 718, a control circuit 701 for the data transmission buffer, and the like. The clock transmission buffer transmits a clock output signal 736 to the through via, and the data transmission buffer transmits a data output signal 735 to the through via. The control circuit 701 includes a latch circuit 711, a rising edge detection circuit 712, a voltage detection circuit 713, a state control register 714, a NAND circuit 715, and an inverter circuit 716. When there are a plurality of data channels, the rise detection circuit 712 and the voltage detection circuit 713 can be shared between the channels.
　また、ここでは、データ用送信バッファを構成するＭＯＳＦＥＴ７１７，７１８のトランジスタサイズ（ゲート幅）は、クロック用送信バッファを構成するＭＯＳＦＥＴ７１９，７２０のトランジスタサイズ（ゲート幅）と同一とするが、場合によっては、クロック用送信バッファをデータ用送信バッファよりも大きく設計してもよい。立ち上がり検出回路７１２は、特定の電圧を比較できるものであれば何でもよい。単なるインバータでも可能であるが閾値がばらつく可能性がある。差動増幅器に代表される常時比較動作を行うコンパレータ回路と基準電圧源の併用が望ましい。 Here, the transistor size (gate width) of the MOSFETs 717 and 718 constituting the data transmission buffer is the same as the transistor size (gate width) of the MOSFETs 719 and 720 constituting the clock transmission buffer. The clock transmission buffer may be designed larger than the data transmission buffer. The rising edge detection circuit 712 may be anything as long as it can compare specific voltages. Although a simple inverter is possible, the threshold value may vary. It is desirable to use a reference voltage source in combination with a comparator circuit that performs a constant comparison operation represented by a differential amplifier.
　図１６は、図１４の送信部の動作例を示す波形図である。クロック入力信号がロウレベルの間は、データ用送信バッファのｎＭＯＳＦＥＴ７１８がＯＮ状態であり、ビア電圧は基準電源電圧ＶＳＳに固定されている。クロック入力信号がハイレベルに変化した場合、実施の形態１の場合と同様に立ち上がり検出回路７１２が起動信号７３１を出力し、ラッチ回路７１１はデータ入力信号を取り込んでＮＡＮＤ回路７１５に向けて出力する。同時に起動信号７３１によって制御レジスタ７１４がＳＥＴされ、同レジスタによる信号“１”がＮＡＮＤ回路７１５に出力される。ラッチ回路７１１で取り込んだデータ信号の真理値が“１”である場合、ＮＡＮＤ回路７１５からの信号（７３３）でｐＭＯＳＦＥＴ７１７がＯＮになる。また、クロック入力信号がハイレベルの場合は、インバータ回路７１６を介してｎＭＯＳＦＥＴ７１８はＯＦＦとなる。 FIG. 16 is a waveform diagram showing an operation example of the transmission unit in FIG. While the clock input signal is at the low level, the nMOSFET 718 of the data transmission buffer is in the ON state, and the via voltage is fixed to the reference power supply voltage VSS. When the clock input signal changes to a high level, the rise detection circuit 712 outputs the start signal 731 as in the case of the first embodiment, and the latch circuit 711 receives the data input signal and outputs it to the NAND circuit 715. . At the same time, the control register 714 is set by the activation signal 731, and a signal “1” from the register is output to the NAND circuit 715. When the truth value of the data signal fetched by the latch circuit 711 is “1”, the pMOSFET 717 is turned on by the signal (733) from the NAND circuit 715. When the clock input signal is at a high level, the nMOSFET 718 is turned off via the inverter circuit 716.
　一方、クロック入力信号のハイレベルを受けて、クロック用送信バッファのｐＭＯＳＦＥＴ７１９がＯＮになり、貫通ビア上の電位を上昇させる。このクロック信号用貫通ビア上の電圧がある値（例えば０．６ＶＤＤ）に達すると、電圧検出回路７１３がそれを検出し、その出力である抑止信号７３２によって制御レジスタ７１４がＲＥＳＥＴされる。その結果、レジスタの出力は“０”となり、それにつながるＮＡＮＤ回路７１５の出力（７３３）も“０”となってデータ用送信バッファのｐＭＯＳＦＥＴ７１７がＯＦＦとなる。この時点でデータ信号用貫通ビアの電圧増加はストップし、その電圧（例えば０．６ＶＤＤ）が維持される。次にクロック入力信号がロウレベルに変化すると、インバータ回路７１６からのプリチャージ信号７３４によってｎＭＯＳＦＥＴ７１８がＯＮとなり、データ信号用貫通ビアの電圧はＶＳＳに強制的にプリチャージされる。また、ラッチ回路７１１からのデータ信号の真理値が“０”であった場合、常にｐＭＯＳＦＥＴ７１７はＯＦＦになっており、ビア上電圧はＶＳＳに固定されたままである。 On the other hand, in response to the high level of the clock input signal, the pMOSFET 719 of the clock transmission buffer is turned on to raise the potential on the through via. When the voltage on the clock signal through via reaches a certain value (for example, 0.6 VDD), the voltage detection circuit 713 detects it, and the control register 714 is reset by the inhibition signal 732 that is the output. As a result, the output of the register becomes “0”, the output (733) of the NAND circuit 715 connected thereto becomes “0”, and the pMOSFET 717 of the data transmission buffer is turned OFF. At this time, the voltage increase of the data signal through via is stopped and the voltage (for example, 0.6 VDD) is maintained. Next, when the clock input signal changes to the low level, the nMOSFET 718 is turned on by the precharge signal 734 from the inverter circuit 716, and the voltage of the data signal through via is forcibly precharged to VSS. When the truth value of the data signal from the latch circuit 711 is “0”, the pMOSFET 717 is always OFF, and the via voltage remains fixed at VSS.
　なお、ここでは、電圧検出回路７１３で検出した電圧値と、データ出力信号７３５のハイレベル側電圧値とが等しいものとしたが、厳密には、電圧検出回路７１３が検出を行ってからｐＭＯＳＦＥＴ７１７がＯＦＦに駆動されるまでに遅延時間があるため、その分の電圧値調整が必要となる。そこで、前述したように、例えば、クロック用送信バッファをデータ用送信バッファよりも大きく設計する等で、クロック信号用貫通ビア上の電圧上昇をデータ信号用貫通ビアよりも速くし、これによって前述した遅延時間を補償することも可能である。また、本実施の形態２では、インバータ回路７１６を用いて、クロック信号がロウである期間は強制的にｎＭＯＳＦＥＴ７１８をＯＮにすることでＶＳＳプリチャージを行ったが、実施の形態１で示したように抑止信号７３２を遅延させた信号でＶＳＳプリチャージを行ってもよい。 Here, the voltage value detected by the voltage detection circuit 713 is assumed to be equal to the high-level voltage value of the data output signal 735. Strictly speaking, however, the pMOSFET 717 is detected after the voltage detection circuit 713 detects. Since there is a delay time until it is driven to OFF, voltage value adjustment for that is required. Therefore, as described above, for example, the clock transmission buffer is designed to be larger than the data transmission buffer, so that the voltage rise on the clock signal through via is made faster than the data signal through via. It is also possible to compensate for the delay time. In the second embodiment, the VSS precharge is performed by using the inverter circuit 716 to forcibly turn on the nMOSFET 718 during the period when the clock signal is low, as shown in the first embodiment. Alternatively, the VSS precharge may be performed using a signal obtained by delaying the inhibition signal 732.
　一方、図１５に示す受信部は、送信部の制御回路７０１と同様の電圧検出回路７２１、基準電圧源７２２、コンパレータ回路７２３、真理値確定回路７２４、および遅延回路７２５で構成される。図１７は、図１５の受信部の動作例を示す波形図である。貫通ビアを介して入力されたクロック入力信号７４５の電圧を電圧検出回路７２１で検出し、その出力（起動信号７４１）に遅延回路７２５による遅延を加えた信号（判定イネーブル信号７２４）でコンパレータ回路７２３を起動する。貫通ビア経由で入力されたデータ入力信号７４４は、コンパレータ回路７２３にて基準電圧源７２２からの基準電圧と比較され、その結果によって得られる判定データ信号７４３が真理値確定回路７２４に入力される。なお、遅延回路７２５がない場合は、このコンパレータ回路７２３の起動と送信部のｐＭＯＳＦＥＴ７１７のＯＦＦ動作はほぼ同一時刻に行われる。また、図１５では、常に基準電圧を出力する回路を用いた場合を示したが、実施の形態１で示したように、適当な遅延回路を用いて比較動作するときのみ起動する基準電圧源を用いてもよい。 On the other hand, the receiving unit shown in FIG. 15 includes a voltage detection circuit 721, a reference voltage source 722, a comparator circuit 723, a truth value determination circuit 724, and a delay circuit 725 similar to the control circuit 701 of the transmission unit. FIG. 17 is a waveform diagram showing an operation example of the receiving unit in FIG. The voltage detection circuit 721 detects the voltage of the clock input signal 745 input through the through via, and the comparator circuit 723 is a signal (determination enable signal 724) obtained by adding a delay by the delay circuit 725 to the output (start signal 741). Start up. The data input signal 744 input through the through via is compared with the reference voltage from the reference voltage source 722 by the comparator circuit 723, and the determination data signal 743 obtained as a result is input to the truth value determination circuit 724. If the delay circuit 725 is not provided, the activation of the comparator circuit 723 and the OFF operation of the pMOSFET 717 of the transmission unit are performed at substantially the same time. Further, FIG. 15 shows a case where a circuit that always outputs a reference voltage is used. However, as shown in the first embodiment, a reference voltage source that is activated only when a comparison operation is performed using an appropriate delay circuit. It may be used.
　以上、本実施の形態２の半導体装置を用いることで、実施の形態１の場合と同様に、代表的には、貫通ビア等のバスを介して信号伝送を行う際に、消費電力の低減と共に信号伝送の高速化が実現可能になる。また、実施の形態１の場合と比較して、遅延回路方式ではなくクロック信号の電圧をモニタする方式で振幅制限を行っているため、半導体チップの積層数が固定でない場合においても、積層数に応じてｐＭＯＳＦＥＴ７１７のオン時間を調整する必要がない。すなわち、積層数に伴う浮遊容量の変化によってデータ信号の立ち上がり時間が変わった場合には、同様にクロック信号の立ち上がり時間も変わるため、積層数の影響を反映した上で充電時間を定めることができる。 As described above, by using the semiconductor device of the second embodiment, as in the case of the first embodiment, typically, when signal transmission is performed via a bus such as a through via, power consumption is reduced. High-speed signal transmission can be realized. Compared to the case of the first embodiment, since the amplitude is limited not by the delay circuit method but by the method of monitoring the voltage of the clock signal, even when the number of stacked semiconductor chips is not fixed, the number of stacked layers is reduced. Accordingly, it is not necessary to adjust the on-time of the pMOSFET 717. That is, when the rise time of the data signal changes due to the change in the stray capacitance with the number of stacks, the rise time of the clock signal also changes in the same manner, so that the charging time can be determined reflecting the effect of the number of stacks. .
　（実施の形態３）
　本実施の形態３では、実施の形態１，２の受信部で用いられる基準電圧源（例えば図６の基準電圧源３４２等）の構成例について説明する。図１８は、本発明の実施の形態３による半導体装置において、その受信部の基準電圧源を示すものであり、（ａ）はその構成例を示す回路図、（ｂ）は（ａ）におけるスイッチ付き容量対の構成例を示す回路図である。図１８（ａ）に示す基準電圧源は、充電用のｐＭＯＳＦＥＴ９１１と、放電量のｎＭＯＳＦＥＴ９１２と、電荷配分用のｎＭＯＳＦＥＴ９１３と、これらのオン・オフを制御する制御回路と、ｎＭＯＳＦＥＴ９１３の一端および他端にそれぞれ接続された複数の容量回路９０１ａ～９０１ｃおよび９０１ｄ，９０１ｅを備えている。 (Embodiment 3)
In the third embodiment, a configuration example of a reference voltage source (for example, the reference voltage source 342 in FIG. 6) used in the receiving units of the first and second embodiments will be described. 18A and 18B show a reference voltage source of the receiving unit in the semiconductor device according to the third embodiment of the present invention. FIG. 18A is a circuit diagram showing a configuration example thereof, and FIG. 18B is a switch in FIG. It is a circuit diagram which shows the structural example of an attached capacitance pair. 18A includes a charge pMOSFET 911, a discharge amount nMOSFET 912, a charge distribution nMOSFET 913, a control circuit for controlling on / off thereof, and one end and the other end of the nMOSFET 913. A plurality of capacitance circuits 901a to 901c, 901d, and 901e connected to each other are provided.
　容量回路のそれぞれは、図１８（ｂ）に示すように、ｐＭＯＳＦＥＴ９０２とｎＭＯＳＦＥＴ９０３で構成した容量対と、当該容量対を設定信号に応じて所定の電圧ノードに接続するＣＭＯＳスイッチ９０４によって構成される。ｐＭＯＳＦＥＴ９０２は、ゲートを入力とし、ソースおよびドレインが電源電圧ＶＤＤに接続され、ｎＭＯＳＦＥＴ９０３は、ゲートを入力とし、ソースおよびドレインが基準電源電圧ＶＳＳに接続される。各容量回路の容量値は、構成するＦＥＴの最小容量の整数倍で設定され、ここでは、容量回路９０１ａを基準として、例えば、９０１ｂ、９０１ｃが、それぞれ２倍、４倍の容量値であり、９０１ｄ、９０１ｅが共に４倍の容量値である例を示している。 As shown in FIG. 18B, each of the capacitor circuits includes a capacitor pair formed by a pMOSFET 902 and an nMOSFET 903, and a CMOS switch 904 that connects the capacitor pair to a predetermined voltage node according to a setting signal. The pMOSFET 902 has a gate as an input, the source and drain are connected to the power supply voltage VDD, and the nMOSFET 903 has a gate as an input, and the source and drain are connected to the reference power supply voltage VSS. The capacitance value of each capacitance circuit is set as an integer multiple of the minimum capacitance of the FETs that are configured. Here, for example, 901b and 901c are capacitance values that are twice and four times, respectively, with the capacitance circuit 901a as a reference. In the example, 901d and 901e are four times the capacitance value.
　以下に、動作を説明する。許可信号は常にハイレベルとする。起動信号（例えば図６の起動信号３５１）がロウレベルの場合、充放電用のＭＯＳＦＥＴ９１１，９１２が共にＯＮ状態となる。これにより、容量回路９０１ａ～９０１ｃ内の各容量対の中から設定信号ＶＳＥＬ１によって選択された容量対にＶＤＤが充電され、また、設定信号ＶＳＥＬ２による選択に応じて容量回路９０１ｅ内の容量対がＶＳＳに充電される。ただし、容量回路９０１ｄ内の容量対は常に選択され、ＶＳＳに充電される。ここで起動信号がハイレベルに変わると、充放電用のＭＯＳＦＥＴ９１１，９１２はＯＦＦ状態となり、代わりに電荷配分用のｎＭＯＳＦＥＴ９１３がＯＮ状態となる。ここで上側容量対に充電されていた電荷は、ｎＭＯＳＦＥＴ９１３を通じて下側容量対に移動して全容量対の電圧が同じになる。この状態の電圧を基準電圧ＶＲＥＦＯＵＴとして取り出す。 The operation will be described below. The permission signal is always high. When the activation signal (for example, the activation signal 351 in FIG. 6) is at a low level, the charge / discharge MOSFETs 911 and 912 are both turned on. As a result, VDD is charged to the capacitor pair selected by the setting signal VSEL1 from among the capacitor pairs in the capacitor circuits 901a to 901c, and the capacitor pair in the capacitor circuit 901e is set to VSS according to the selection by the setting signal VSEL2. Is charged. However, the capacity pair in the capacity circuit 901d is always selected and charged to VSS. When the activation signal changes to a high level, the charge / discharge MOSFETs 911 and 912 are turned off, and the charge distribution nMOSFET 913 is turned on instead. Here, the charges charged in the upper capacitor pair move to the lower capacitor pair through the nMOSFET 913, and the voltages of all the capacitor pairs become the same. The voltage in this state is taken out as the reference voltage VREFOUT .
　負荷容量を無視できる場合、基準電圧ＶＲＥＦＯＵＴは式（１０）で表される。なお、例えば、Σ（ＶＳＥＬ１）は、容量回路９０１ｃのみを選択する場合は「４」、容量回路９０１ｂのみを選択する場合は「２」、この両方を選択する場合は「６」となる。式（１０）に示すように、設定信号（ＶＳＥＬ１，ＶＳＥＬ２）を切り替えることで任意の電圧を生成することができ、本実施の形態のようなＶＳＳ側に低い基準電圧の生成が可能となる。 When the load capacitance can be ignored, the reference voltage V REFOUT is expressed by Expression (10). For example, Σ (VSEL1) is “4” when only the capacitor circuit 901c is selected, “2” when only the capacitor circuit 901b is selected, and “6” when both are selected. As shown in Expression (10), an arbitrary voltage can be generated by switching the setting signals (VSEL1, VSEL2), and a low reference voltage can be generated on the VSS side as in this embodiment.
　ＶＲＥＦＯＵＴ＝ＶＤＤ×（Σ（ＶＳＥＬ１）／（Σ（ＶＳＥＬ１）＋ＶＳＥＬ２＋４））　　　（１０） V REFOUT = VDD × (Σ (VSEL1) / (Σ (VSEL1) + VSEL2 + 4)) (10)
　なお、本実施の形態３では、容量対としてｐＭＯＳＦＥＴ９０２とｎＭＯＳＦＥＴ９０３の直列接続した蓄積容量を用いた。単体（たとえばＶＳＳ側に接地したｎＭＯＳＦＥＴ）で構成した場合、充電電圧がＶＳＳ付近であると容量が急激に低下する。そこで、ｎＭＯＳＦＥＴをＶＳＳ側にｐＭＯＳＦＥＴをＶＤＤ側に接続することで、ＶＤＤ－ＶＳＳ間の充電電圧にわたり十分な容量を確保することできる。 In the third embodiment, a storage capacitor in which a pMOSFET 902 and an nMOSFET 903 are connected in series is used as a capacitor pair. In the case of a single element (for example, an nMOSFET grounded on the VSS side), the capacity rapidly decreases when the charging voltage is near VSS. Therefore, by connecting the nMOSFET to the VSS side and the pMOSFET to the VDD side, a sufficient capacity can be secured over the charging voltage between VDD and VSS.
　（実施の形態４）
　本実施の形態４では、前述したＶＳＳプリチャージ方式を用い、実施の形態１，２で説明したデータ信号の振幅制御に加えて、クロック信号の振幅制限も行う半導体装置について説明する。図１９は、本発明の実施の形態４による半導体装置において、その送信部の構成例を示すブロック図であり、図２０は、本発明の実施の形態４による半導体装置において、その受信部の構成例を示すブロック図である。この例では１本のクロック信号に対して１チャネル分のデータ信号を示しているが、実際のデータ信号チャネル数は複数のほうが好ましい。 (Embodiment 4)
In the fourth embodiment, a semiconductor device that uses the above-described VSS precharge method and performs amplitude limitation of a clock signal in addition to the amplitude control of the data signal described in the first and second embodiments will be described. FIG. 19 is a block diagram illustrating a configuration example of the transmission unit in the semiconductor device according to the fourth embodiment of the present invention. FIG. 20 illustrates a configuration of the reception unit in the semiconductor device according to the fourth embodiment of the present invention. It is a block diagram which shows an example. In this example, one channel of data signal is shown for one clock signal, but the actual number of data signal channels is preferably plural.
　図１９に示す送信部は、ｐＭＯＳＦＥＴ１００５とｎＭＯＳＦＥＴ１００６で構成したクロック用送信バッファと、ｐＭＯＳＦＥＴ１００３とｎＭＯＳＦＥＴ１００４で構成したデータ用送信バッファと、クロック用送信バッファの制御回路１００２およびデータ用送信バッファの制御回路１００１で構成される。クロック用送信バッファは、貫通ビアに対してクロック出力信号１０５０を送信し、データ用送信バッファは、貫通ビアに対してデータ出力信号１０４９を送信する。 The transmission unit shown in FIG. 19 includes a clock transmission buffer composed of pMOSFET 1005 and nMOSFET 1006, a data transmission buffer composed of pMOSFET 1003 and nMOSFET 1004, a control circuit 1002 for clock transmission buffer, and a control circuit 1001 for data transmission buffer. Composed. The clock transmission buffer transmits a clock output signal 1050 to the through via, and the data transmission buffer transmits a data output signal 1049 to the through via.
　クロック用送信バッファの制御回路１００２は、立ち上がり検出回路１０１１、コンパレータ回路１０１２、基準電圧源１０１３、状態制御レジスタ１０１４、ＮＡＮＤ回路１０１５およびインバータ回路１０１６で構成される。データ用送信バッファの制御回路１００１は、ラッチ回路１０２１、状態制御レジスタ１０２２、ＮＡＮＤ回路１０２３およびインバータ回路１０２４で構成される。 The clock transmission buffer control circuit 1002 includes a rise detection circuit 1011, a comparator circuit 1012, a reference voltage source 1013, a state control register 1014, a NAND circuit 1015, and an inverter circuit 1016. The data transmission buffer control circuit 1001 includes a latch circuit 1021, a state control register 1022, a NAND circuit 1023, and an inverter circuit 1024.
　図２２は、図１９の送信部の動作例を示す波形図である。クロック入力信号がロウレベルの間は、クロック用およびデータ用の送信バッファのｎＭＯＳＦＥＴ１００６，１００４がＯＮ状態であり、各貫通ビアの電圧はＶＳＳに固定されている。クロック入力信号がハイレベルに変化した場合、その立ち上がりが検出回路１０１１で検出され、同回路は起動信号１０４１を出力する。この信号によりラッチ回路１０２１は、データ入力信号をラッチし、それが“１”の場合にはＮＡＮＤ回路１０２３に向けてハイレベルを出力する。同時に起動信号１０４１により制御レジスタ１０１４，１０２２がＳＥＴされ、同レジスタが信号“１”をＮＡＮＤ回路１０１５，１０２３に出力する。ＮＡＮＤ回路１０１５からの信号でｐＭＯＳＦＥＴ１００５がＯＮになりクロック信号用貫通ビア上の電圧が上昇し、ＮＡＮＤ回路１０２３からの信号でｐＭＯＳＦＥＴ１００３がＯＮになりデータ信号用貫通ビア上の電圧が上昇する。 FIG. 22 is a waveform diagram showing an operation example of the transmission unit of FIG. While the clock input signal is at the low level, the nMOSFETs 1006 and 1004 of the clock and data transmission buffers are in the ON state, and the voltage of each through via is fixed to VSS. When the clock input signal changes to a high level, the rising edge is detected by the detection circuit 1011, and the circuit outputs an activation signal 1041. In response to this signal, the latch circuit 1021 latches the data input signal, and when it is “1”, outputs a high level to the NAND circuit 1023. At the same time, the control registers 1014 and 1022 are set by the activation signal 1041, and the register outputs a signal “1” to the NAND circuits 1015 and 1023. The signal from the NAND circuit 1015 turns on the pMOSFET 1005 and increases the voltage on the clock signal through via, and the signal from the NAND circuit 1023 turns on the pMOSFET 1003 and raises the voltage on the data signal through via.
　クロック用貫通ビア上の電圧（クロック出力信号１０５０）が制限振幅に達すると、コンパレータ回路１０１２が、基準電圧との比較でその超過を検出して抑止信号１０４２を出力し、制御レジスタ１０１４をＲＥＳＥＴする。その結果、制御レジスタ１０１４の出力は“０”となり、それにつながるＮＡＮＤ回路１０１５の出力も“０”となりクロック用送信バッファのｐＭＯＳＦＥＴ１００５はＯＦＦとなる。この時点で電圧増加はストップし、その電圧が維持される。ここで、万が一クロック電圧が基準電圧より低下してコンパレータ回路の出力が“０”になっても、制御レジスタ１０１４の出力は変化しない。一方、クロック用の制御回路１００２と同様に、データ用の制御回路１００１における制御レジスタ１０２２も抑止信号１０４２によってＲＥＳＥＴされ、ＮＡＮＤ回路１０２３を介してｐＭＯＳＦＥＴ１００３がＯＦＦとなり、その時点の電圧がデータ信号用貫通ビア（データ出力信号１０４９）で維持される。その後、クロック入力信号がロウレベルに変化すると、インバータ１０１６，１０２４を通じてｎＭＯＳＦＥＴ１００６，１００４がＯＮ状態となりクロック出力信号１０５０およびデータ出力信号１０４９の電圧は、ＶＳＳ側に強制的にプリチャージされる。 When the voltage on the clock through via (clock output signal 1050) reaches the limit amplitude, the comparator circuit 1012 detects the excess in comparison with the reference voltage, outputs the inhibition signal 1042, and resets the control register 1014. . As a result, the output of the control register 1014 becomes “0”, the output of the NAND circuit 1015 connected thereto becomes “0”, and the pMOSFET 1005 of the clock transmission buffer is turned off. At this point, the voltage increase stops and the voltage is maintained. Here, even if the clock voltage drops below the reference voltage and the output of the comparator circuit becomes “0”, the output of the control register 1014 does not change. On the other hand, similarly to the clock control circuit 1002, the control register 1022 in the data control circuit 1001 is also reset by the inhibition signal 1042, the pMOSFET 1003 is turned off via the NAND circuit 1023, and the voltage at that time is passed through the data signal. Maintained by via (data output signal 1049). Thereafter, when the clock input signal changes to the low level, the nMOSFETs 1006 and 1004 are turned on through the inverters 1016 and 1024, and the voltages of the clock output signal 1050 and the data output signal 1049 are forcibly precharged to the VSS side.
　また、図２０に示す受信部は、振幅制限されたクロック信号を処理する部分として、差動増幅回路１０３１と、基準電圧源１０３２と、２段のインバータ（バッファ）を備え、データ信号を処理する部分として、コンパレータ回路１０３５、基準電圧源１０３４、真理値確定回路１０３６、および遅延回路１０３７、１０３８を備える。 20 includes a differential amplifier circuit 1031, a reference voltage source 1032, and a two-stage inverter (buffer) as a part that processes an amplitude-limited clock signal, and processes a data signal. As parts, a comparator circuit 1035, a reference voltage source 1034, a truth value determination circuit 1036, and delay circuits 1037 and 1038 are provided.
　図２３は、図２０の受信部の動作例を示す波形図である。貫通ビアを介して入力されたクロック入力信号１０５２は、差動増幅回路１０３１によって、基準電圧源１０３２からの基準電圧を基準として差動増幅される。基準電圧源１０３２は常に起動状態を維持している。クロック入力信号１０５２は、差動増幅回路１０３１とインバータ２段によって飽和したデジタル信号（起動信号）１０５３に変換される。この起動信号１０５３の立ち上がりを元に、データ信号側の基準電圧源１０３４が起動する。また、この起動信号１０５３は、遅延回路１０３７を介して判定イネーブル信号１０５４となり、コンパレータ回路１０３５は、この判定イネーブル信号１０５４を受けて、貫通ビア経由で入力されたデータ入力信号１０５１を基準電圧源１０３４からの基準電圧１０３４と比較し、その比較結果が真理値確定回路１０３６に入力される。 FIG. 23 is a waveform diagram showing an operation example of the receiving unit of FIG. The clock input signal 1052 input through the through via is differentially amplified by the differential amplifier circuit 1031 using the reference voltage from the reference voltage source 1032 as a reference. The reference voltage source 1032 always maintains the activated state. The clock input signal 1052 is converted into a digital signal (start signal) 1053 saturated by the differential amplifier circuit 1031 and the two stages of inverters. Based on the rising edge of the activation signal 1053, the reference voltage source 1034 on the data signal side is activated. The activation signal 1053 becomes a determination enable signal 1054 via the delay circuit 1037, and the comparator circuit 1035 receives the determination enable signal 1054 and uses the data input signal 1051 input through the through via as a reference voltage source 1034. And the comparison result is input to the truth value determination circuit 1036.
　図２１は、図２０における差動増幅回路１０３１の構成例を示す回路図である。図２１に示す差動増幅回路１０３１は、広く知られている構成であり、差動対となるＭＯＳＦＥＴと、その増幅用の負荷素子となるＭＯＳＦＥＴと、ゲートの固定電圧値（ＢＩＡＳ）に応じて増幅用の動作電流を供給するＭＯＳＦＥＴから構成される。差動増幅回路１０３１は、常に比較動作を行うため、差動対にはＢＩＡＳで決定される電流が流れ続ける。データ信号が入力されるコンパレータ回路１０３５および基準電圧源１０３４は起動時のみ電力を消費する一方で、クロック信号が入力される差動増幅回路１０３１および基準電圧源１０３２は常に動作状態である。このため、クロック信号側の受信回路は、データ信号側と比較して消費電力が大きい。よって伝送回路全体で低消費電力化を図るためには、クロック信号１本に対してデータ信号チャネル数を多く取ることが望ましい。 FIG. 21 is a circuit diagram showing a configuration example of the differential amplifier circuit 1031 in FIG. The differential amplifier circuit 1031 shown in FIG. 21 has a widely known configuration, depending on the MOSFET serving as the differential pair, the MOSFET serving as the load element for amplification, and the fixed voltage value (BIAS) of the gate. It is composed of a MOSFET that supplies an operating current for amplification. Since the differential amplifier circuit 1031 always performs a comparison operation, a current determined by BIAS continues to flow through the differential pair. The comparator circuit 1035 to which the data signal is input and the reference voltage source 1034 consume power only at the time of startup, while the differential amplifier circuit 1031 and the reference voltage source 1032 to which the clock signal is input are always in an operating state. For this reason, the receiving circuit on the clock signal side consumes more power than the data signal side. Therefore, in order to reduce power consumption in the entire transmission circuit, it is desirable to increase the number of data signal channels with respect to one clock signal.
　以上、本実施の形態４の半導体装置を用いることで、実施の形態２の場合と同様に、代表的には、貫通ビア等のバスを介して信号伝送を行う際に、消費電力の低減と共に信号伝送の高速化が実現可能になる。また、クロック信号をモニタしているため、積層数の変化にも柔軟に対応可能となる。さらに、実施の形態１，２と比較して、クロック信号の振幅も制限しているため、クロックバスの充放電に伴う消費電力が低減可能となり、これと共に、データバスの場合と同様の理由でクロックバスの高速化も図れる。 As described above, by using the semiconductor device of the fourth embodiment, as in the case of the second embodiment, typically, when signal transmission is performed via a bus such as a through via, power consumption is reduced. High-speed signal transmission can be realized. Further, since the clock signal is monitored, it is possible to flexibly cope with a change in the number of stacked layers. Furthermore, since the amplitude of the clock signal is also limited as compared with the first and second embodiments, the power consumption accompanying charging / discharging of the clock bus can be reduced, and for the same reason as in the case of the data bus. The clock bus speed can also be increased.
　また、これまでに説明した各実施の形態による代表的な効果を纏めると次のようになる。まず、貫通ビアの浮遊容量を低振幅信号で駆動することで電力消費を低減する。同時にバッファ回路を通した浮遊容量への充電は電源電圧で行うため、伝送路上の立ち上がり時間を低減し伝送系全体の動作周波数向上に貢献する。また、出力振幅をＶＳＳ側で制限することでバッファ回路のｐＭＯＳＦＥＴの広幅化が不要となり、ＦＥＴ浮遊容量の低減になる。バッファ回路の制御では、データ信号と同一の貫通ビア構造でクロック信号を伝送し、その出力電圧変化を検出して振幅制御信号とすることで積層数の変更で生じる総ビア負荷容量の変化を反映できる。 Also, the typical effects of each embodiment described so far are summarized as follows. First, power consumption is reduced by driving the stray capacitance of the through via with a low amplitude signal. At the same time, since the stray capacitance through the buffer circuit is charged with the power supply voltage, the rise time on the transmission path is reduced and the operating frequency of the entire transmission system is improved. Further, by limiting the output amplitude on the VSS side, it becomes unnecessary to widen the pMOSFET of the buffer circuit, and the FET stray capacitance is reduced. In the control of the buffer circuit, the clock signal is transmitted with the same through via structure as the data signal, and the change in the total via load capacity caused by the change in the number of stacked layers is reflected by detecting the change in the output voltage and using it as the amplitude control signal. it can.
　以上、本発明者によってなされた発明を実施の形態に基づき具体的に説明したが、本発明は前記実施の形態に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能である。 As described above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention.
　本実施の形態による半導体装置は、複数の半導体チップが積層搭載され、貫通ビアを介してデータ送受信を行う積層チップシステムに適用して特に有益な技術であり、これに限らず、複数の半導体チップ間でバス配線を介してデータ送受信を行う一般的なバスシステム等に対しても適用可能である。 The semiconductor device according to the present embodiment is a technique that is particularly useful when applied to a stacked chip system in which a plurality of semiconductor chips are stacked and transmitted / received data through through vias. The present invention is also applicable to a general bus system that transmits and receives data via bus wiring.
　１００：半導体チップ、１０１：導体、１０２：パッド、１０３：絶縁膜、１０４：半田バンプ、１０６：浮遊容量、１０７：送信部、１０８：受信部、２０１：制御回路、２０２：ｐＭＯＳＦＥＴ、２０３：ｎＭＯＳＦＥＴ、２０４：ｐＭＯＳＦＥＴ、２０５：ｎＭＯＳＦＥＴ、２１１：コンパレータ回路、２１２：基準電圧源、２１３：ラッチ回路、３０１：制御回路、３１１：ラッチ回路、３１２：立ち上がり検出回路、３１３：遅延回路、３１４：遅延回路、３１５：制御レジスタ、３１６：制御レジスタ、３１７：ＮＡＮＤ回路、３１８：ｐＭＯＳＦＥＴ、３１９：ｎＭＯＳＦＥＴ、３２０：ｐＭＯＳＦＥＴ、３２１：ｎＭＯＳＦＥＴ、３３１：起動信号、３３２：抑止信号、３３３：プリチャージ信号、３３４：ゲート制御信号、３３５：ゲート制御信号、３３６：データ出力信号、３３７：クロック出力信号、３４１：立ち上がり検出回路、３４２：基準電圧源、３４３：コンパレータ回路、３４４：真理値確定回路、３４５：遅延回路、３５１：起動信号、３５２：判定イネーブル信号、３５３：判定データ信号、７０１：制御回路、７１１：ラッチ回路、７１２：立ち上がり検出回路、７１３：電圧検出回路、７１４：制御レジスタ、７１５：ＮＡＮＤ回路、７１６：インバータ回路、７１７：ｐＭＯＳＦＥＴ、７１８：ｎＭＯＳＦＥＴ、７１９：ｐＭＯＳＦＥＴ、７２０：ｎＭＯＳＦＥＴ、７２１：電圧検出回路、７２２：基準電圧源、７２３：コンパレータ回路、７２４：真理値確定回路、７２５：遅延回路、７３１：起動信号、７３２：抑止信号、７３３：ゲート制御信号、７３４：プリチャージ信号、７３５：データ出力信号、７３６：クロック出力信号、７４１：起動信号、７４２：判定イネーブル信号、７４３：判定データ信号、７４４：データ入力信号、７４５：クロック入力信号、９０１：容量回路、９０２：ｐＭＯＳＦＥＴ、９０３：ｎＭＯＳＦＥＴ、９０４：ＣＭＯＳスイッチ、９２０：制御回路、９１１：ｐＭＯＳＦＥＴ、９１２：ｎＭＯＳＦＥＴ、９１３：ｎＭＯＳＦＥＴ、１００１：制御回路、１００２：制御回路、１００３：ｐＭＯＳＦＥＴ、１００４：ｎＭＯＳＦＥＴ、１００５：ｐＭＯＳＦＥＴ、１００６：ｎＭＯＳＦＥＴ、１０１１：立ち上がり検出回路、１０１２：コンパレータ回路、１０１３：基準電圧源、１０１４：制御レジスタ、１０１５：ＮＡＮＤ回路、１０１６：インバータ回路、１０２１：ラッチ回路、１０２２：制御レジスタ、１０２３：ＮＡＮＤ回路、１０２４：インバータ回路、１０３１：差動増幅回路、１０３２：基準電圧源、１０３４：基準電圧源、１０３５：コンパレータ回路、１０３６：真理値確定回路、１０３７：遅延回路、１０３８：遅延回路、１０４１：起動信号、１０４２：抑止信号、１０４３：ゲート制御信号、１０４４：ゲート制御信号、１０４５：ゲート制御信号、１０４６：ゲート制御信号、１０４９：データ出力信号、１０５０：クロック出力信号、１０５１：データ入力信号、１０５２：クロック入力信号、１０５３：起動信号、１０５４：判定イネーブル信号、１０５５：判定データ信号。 100: Semiconductor chip, 101: Conductor, 102: Pad, 103: Insulating film, 104: Solder bump, 106: Floating capacitance, 107: Transmitter, 108: Receiver, 201: Control circuit, 202: pMOSFET, 203: nMOSFET 204: pMOSFET, 205: nMOSFET, 211: comparator circuit, 212: reference voltage source, 213: latch circuit, 301: control circuit, 311: latch circuit, 312: rise detection circuit, 313: delay circuit, 314: delay circuit 315: Control register, 316: Control register, 317: NAND circuit, 318: pMOSFET, 319: nMOSFET, 320: pMOSFET, 321: nMOSFET, 331: Start signal, 332: Suppression signal, 333: Precharge signal, 334: Gate control signal 335: Gate control signal, 336: Data output signal, 337: Clock output signal, 341: Rise detection circuit, 342: Reference voltage source, 343: Comparator circuit, 344: Truth value determination circuit, 345: Delay circuit, 351: Activation signal, 352: determination enable signal, 353: determination data signal, 701: control circuit, 711: latch circuit, 712: rise detection circuit, 713: voltage detection circuit, 714: control register, 715: NAND circuit, 716: inverter Circuit, 717: pMOSFET, 718: nMOSFET, 719: pMOSFET, 720: nMOSFET, 721: voltage detection circuit, 722: reference voltage source, 723: comparator circuit, 724: truth value determination circuit, 725: delay circuit, 731: start-up Signal, 732: inhibition signal, 73 : Gate control signal, 734: precharge signal, 735: data output signal, 736: clock output signal, 741: start signal, 742: determination enable signal, 743: determination data signal, 744: data input signal, 745: clock input Signal, 901: Capacitance circuit, 902: pMOSFET, 903: nMOSFET, 904: CMOS switch, 920: Control circuit, 911: pMOSFET, 912: nMOSFET, 913: nMOSFET, 1001: Control circuit, 1002: Control circuit, 1003: pMOSFET , 1004: nMOSFET, 1005: pMOSFET, 1006: nMOSFET, 1011: rise detection circuit, 1012: comparator circuit, 1013: reference voltage source, 1014: control register, 1015: NAND circuit 1016: Inverter circuit, 1021: Latch circuit, 1022: Control register, 1023: NAND circuit, 1024: Inverter circuit, 1031: Differential amplifier circuit, 1032: Reference voltage source, 1034: Reference voltage source, 1035: Comparator circuit, 1036: Truth value determination circuit, 1037: Delay circuit, 1038: Delay circuit, 1041: Start signal, 1042: Inhibition signal, 1043: Gate control signal, 1044: Gate control signal, 1045: Gate control signal, 1046: Gate control signal 1049: Data output signal, 1050: Clock output signal, 1051: Data input signal, 1052: Clock input signal, 1053: Start signal, 1054: Determination enable signal, 1055: Determination data signal.

Claims (19)

  1. 　送信端子と、
    　前記送信端子を介して情報信号を送信する送信バッファとを備え、
    　前記送信バッファは、
    　ソースが電源電圧に、ドレインが前記送信端子に接続された第１導電型の第１ＭＩＳＦＥＴと、
    　ソースが前記電源電圧よりも小さい基準電源電圧に、ドレインが前記送信端子に接続された第２導電型の第２ＭＩＳＦＥＴと、
    　前記第１および第２ＭＩＳＦＥＴのゲートを制御する第１制御回路とを備え、
    　前記第１制御回路は、まず、前記第２ＭＩＳＦＥＴをオンに駆動すると共に、前記第１ＭＩＳＦＥＴをオフに駆動することで前記送信端子を前記基準電源電圧に放電する第１処理を実行し、次いで、前記情報信号としてハイレベルを送信する際には、前記第２ＭＩＳＦＥＴをオフに駆動すると共に、前記第１ＭＩＳＦＥＴを第１期間だけオンに駆動した後オフに駆動する第２処理を実行し、
    　前記第１期間は、前記送信端子を前記基準電源電圧よりも大きく前記電源電圧よりも小さい第１電圧に充電するのに必要な期間に設定されていることを特徴とする半導体装置。     A transmission terminal;
    A transmission buffer for transmitting an information signal via the transmission terminal,
    The transmission buffer is
    A first conductivity type first MISFET having a source connected to a power supply voltage and a drain connected to the transmission terminal;
    A second conductivity type second MISFET having a source connected to a reference power supply voltage lower than the power supply voltage and a drain connected to the transmission terminal;
    A first control circuit for controlling the gates of the first and second MISFETs,
    The first control circuit first performs a first process for driving the second MISFET on and discharging the transmission terminal to the reference power supply voltage by driving the first MISFET off, and then When transmitting a high level as an information signal, the second MISFET is driven off and a second process is performed in which the first MISFET is driven on for a first period and then turned off.
    The semiconductor device according to claim 1, wherein the first period is set to a period necessary for charging the transmission terminal to a first voltage that is larger than the reference power supply voltage and smaller than the power supply voltage.
  2. 　請求項１記載の半導体装置において、さらに、
    　クロック送信端子と、
    　第１クロック信号が入力され、前記クロック送信端子を介して第２クロック信号を送信するクロック出力バッファとを備え、
    　前記第１処理は、前記第１クロック信号が第１論理レベルの際に実行され、
    　前記第２処理は、前記第１クロック信号の前記第１論理レベルから第２論理レベルへの遷移を受けて実行されることを特徴とする半導体装置。     The semiconductor device according to claim 1, further comprising:
    A clock transmission terminal;
    A clock output buffer that receives a first clock signal and transmits a second clock signal via the clock transmission terminal;
    The first process is performed when the first clock signal is at a first logic level;
    The semiconductor device is characterized in that the second process is executed in response to a transition of the first clock signal from the first logic level to a second logic level.
  3. 　請求項２記載の半導体装置において、
    　前記第１論理レベル、前記第２論理レベルは、それぞれ、ロウレベル、ハイレベルであり、
    　前記クロック出力バッファは、
    　ソースが前記電源電圧に、ドレインが前記クロック送信端子に接続された前記第１導電型の第３ＭＩＳＦＥＴと、
    　ソースが前記基準電源電圧に、ドレインが前記クロック送信端子に接続された前記第２導電型の第４ＭＩＳＦＥＴとを備え、
    　前記第１制御回路は、前記第２クロック信号の電圧が所定の電圧に到達したことを検出する第１電圧検出回路を備え、
    　前記第１期間は、前記第１クロック信号がロウレベルからハイレベルへ遷移してから、前記第１電圧検出回路が検出信号を出力するまでの期間に基づいて定められることを特徴とする半導体装置。     The semiconductor device according to claim 2,
    The first logic level and the second logic level are a low level and a high level, respectively.
    The clock output buffer is
    A third MISFET of the first conductivity type having a source connected to the power supply voltage and a drain connected to the clock transmission terminal;
    A second MISFET of the second conductivity type having a source connected to the reference power supply voltage and a drain connected to the clock transmission terminal;
    The first control circuit includes a first voltage detection circuit that detects that the voltage of the second clock signal has reached a predetermined voltage,
    The semiconductor device according to claim 1, wherein the first period is determined based on a period from when the first clock signal transits from a low level to a high level until the first voltage detection circuit outputs a detection signal.
  4. 　請求項３記載の半導体装置において、
    　前記第３ＭＩＳＦＥＴは、前記第１ＭＩＳＦＥＴよりも駆動能力が大きく設計されていることを特徴とする半導体装置。     The semiconductor device according to claim 3.
    The third MISFET is designed to have a driving capability larger than that of the first MISFET.
  5. 　請求項２記載の半導体装置において、
    　前記第１制御回路は、遅延回路を備え、
    　前記第１期間は、前記第１クロック信号が前記第１論理レベルから前記第２論理レベルへ遷移してから、前記遅延回路による所定の遅延時間が経過するまでの期間に基づいて定められることを特徴とする半導体装置。     The semiconductor device according to claim 2,
    The first control circuit includes a delay circuit;
    The first period is determined based on a period from when the first clock signal transitions from the first logic level to the second logic level until a predetermined delay time by the delay circuit elapses. A featured semiconductor device.
  6. 　請求項２記載の半導体装置において、
    　前記第１論理レベル、前記第２論理レベルは、それぞれ、ロウレベル、ハイレベルであり、
    　前記クロック出力バッファは、
    　ソースが前記電源電圧に、ドレインが前記クロック送信端子に接続され、前記第１ＭＩＳＦＥＴと等しい駆動能力に設計された前記第１導電型の第５ＭＩＳＦＥＴと、
    　ソースが前記基準電源電圧に、ドレインが前記クロック送信端子に接続され、前記第２ＭＩＳＦＥＴと等しい駆動能力に設計された前記第２導電型の第６ＭＩＳＦＥＴとを備え、
    　前記半導体装置は、さらに、前記第５および第６ＭＩＳＦＥＴのゲートを制御する第２制御回路を備え、
    　前記第２制御回路は、まず、前記第２クロック信号としてロウレベルを送信する際には、前記第６ＭＩＳＦＥＴをオンに駆動すると共に、前記第５ＭＩＳＦＥＴをオフに駆動することで前記クロック送信端子を前記基準電源電圧に放電する第３処理を実行し、次いで、前記第２クロック信号としてハイレベルを送信する際には、前記第６ＭＩＳＦＥＴをオフに駆動すると共に、前記第５ＭＩＳＦＥＴを第２期間だけオンに駆動した後オフに駆動する第４処理を実行し、
    　前記第２期間は、前記クロック送信端子を前記第１電圧に充電するのに必要な期間に設定されていることを特徴とする半導体装置。     The semiconductor device according to claim 2,
    The first logic level and the second logic level are a low level and a high level, respectively.
    The clock output buffer is
    A fifth MISFET of the first conductivity type, the source of which is connected to the power supply voltage, the drain of which is connected to the clock transmission terminal, and which is designed to have a driving capability equal to that of the first MISFET;
    A sixth MISFET of the second conductivity type having a source connected to the reference power supply voltage, a drain connected to the clock transmission terminal, and a drive capability equal to that of the second MISFET;
    The semiconductor device further includes a second control circuit that controls gates of the fifth and sixth MISFETs,
    When transmitting a low level as the second clock signal, the second control circuit first drives the sixth MISFET on and drives the fifth MISFET off to set the clock transmission terminal to the reference. When the third process of discharging to the power supply voltage is performed and then a high level is transmitted as the second clock signal, the sixth MISFET is driven off and the fifth MISFET is driven on only for the second period. And then execute a fourth process of driving off,
    The semiconductor device according to claim 2, wherein the second period is set to a period necessary for charging the clock transmission terminal to the first voltage.
  7. 　請求項６記載の半導体装置において、
    　前記第２制御回路は、前記第２クロック信号の電圧が、所定の電圧に到達したことを検出する第２電圧検出回路を備え、
    　前記第１および第２期間は、共に、前記第１クロック信号がロウレベルからハイレベルへ遷移してから、前記第２電圧検出回路が検出信号を出力するまでの期間に基づいて定められることを特徴とする半導体装置。     The semiconductor device according to claim 6.
    The second control circuit includes a second voltage detection circuit that detects that the voltage of the second clock signal has reached a predetermined voltage,
    The first and second periods are both determined based on a period from when the first clock signal transitions from a low level to a high level until the second voltage detection circuit outputs a detection signal. A semiconductor device.
  8. 　順に積層され、第１および第２半導体チップを含んだ複数の半導体チップを備え、
    　前記第１半導体チップは、
    　第１貫通ビアと、
    　前記第１貫通ビアを介して情報信号を送信する送信バッファとを備え、
    　前記送信バッファは、
    　ソースが電源電圧に、ドレインが前記第１貫通ビアに接続された第１導電型の第１ＭＩＳＦＥＴと、
    　ソースが前記電源電圧よりも小さい基準電源電圧に、ドレインが前記第１貫通ビアに接続された第２導電型の第２ＭＩＳＦＥＴと、
    　前記第１および第２ＭＩＳＦＥＴのゲートを制御する第１制御回路とを含み、
    　前記第１制御回路は、まず、前記第２ＭＩＳＦＥＴをオンに駆動すると共に、前記第１ＭＩＳＦＥＴをオフに駆動することで前記第１貫通ビアを前記基準電源電圧に放電する第１処理を実行し、次いで、前記情報信号としてハイレベルを送信する際には、前記第２ＭＩＳＦＥＴをオフに駆動すると共に、前記第１ＭＩＳＦＥＴを第１期間だけオンに駆動した後オフに駆動する第２処理を実行し、
    　前記第１期間は、前記第１貫通ビアを前記基準電源電圧よりも大きく前記電源電圧よりも小さい第１電圧に充電するのに必要な期間に設定され、
    　前記第２半導体チップは、
    　前記第１貫通ビアを介して送信された情報信号を受信する第２貫通ビアと、
    　前記第２貫通ビアが受信した情報信号を、前記基準電源電圧よりも大きく前記第１電圧よりも小さい第１判定電圧を基準として比較判定する受信バッファとを有することを特徴とする半導体装置。     A plurality of semiconductor chips that are sequentially stacked and include first and second semiconductor chips;
    The first semiconductor chip is
    A first through via;
    A transmission buffer for transmitting an information signal through the first through via,
    The transmission buffer is
    A first conductivity type first MISFET having a source connected to a power supply voltage and a drain connected to the first through via;
    A second MISFET of a second conductivity type having a source connected to a reference power supply voltage smaller than the power supply voltage and a drain connected to the first through via;
    A first control circuit for controlling the gates of the first and second MISFETs,
    The first control circuit first performs a first process for driving the second MISFET on and discharging the first through via to the reference power supply voltage by driving the first MISFET off, and then When transmitting a high level as the information signal, the second MISFET is driven off, and the second process of driving the first MISFET on for a first period and then driving off is executed.
    The first period is set to a period required to charge the first through via to a first voltage that is larger than the reference power supply voltage and smaller than the power supply voltage,
    The second semiconductor chip is
    A second through via for receiving an information signal transmitted through the first through via;
    A semiconductor device comprising: a reception buffer for comparing and determining an information signal received by the second through via with reference to a first determination voltage that is larger than the reference power supply voltage and smaller than the first voltage.
  9. 　請求項８記載の半導体装置において、
    　前記第１半導体チップは、さらに、
    　第３貫通ビアと、
    　第１クロック信号が入力され、前記第３貫通ビアを介して第２クロック信号を送信するクロック出力バッファとを備え、
    　前記第２半導体チップは、さらに、前記第２クロック信号を受信する第４貫通ビアを備え、
    　前記第１処理は、前記第１クロック信号が第１論理レベルの際に実行され、
    　前記第２処理は、前記第１クロック信号の前記第１論理レベルから第２論理レベルへの遷移を受けて実行されることを特徴とする半導体装置。     The semiconductor device according to claim 8.
    The first semiconductor chip further includes:
    A third through via;
    A clock output buffer that receives a first clock signal and transmits the second clock signal through the third through via;
    The second semiconductor chip further includes a fourth through via that receives the second clock signal,
    The first process is performed when the first clock signal is at a first logic level;
    The semiconductor device is characterized in that the second process is executed in response to a transition of the first clock signal from the first logic level to a second logic level.
  10. 　請求項９記載の半導体装置において、
    　前記第１論理レベル、前記第２論理レベルは、それぞれ、ロウレベル、ハイレベルであり、
    　前記第１半導体チップの前記クロック出力バッファは、
    　ソースが前記電源電圧に、ドレインが前記第３貫通ビアに接続された前記第１導電型の第３ＭＩＳＦＥＴと、
    　ソースが前記基準電源電圧に、ドレインが前記第３貫通ビアに接続された前記第２導電型の第４ＭＩＳＦＥＴとを備え、
    　前記第１半導体チップの前記第１制御回路は、前記第２クロック信号の電圧が所定の第２電圧に到達したことを検出する第１電圧検出回路を備え、
    　前記第１期間は、前記第１クロック信号がロウレベルからハイレベルへ遷移してから、前記第１電圧検出回路が検出信号を出力するまでの期間に基づいて定められ、
    　前記第２半導体チップは、さらに、前記第４貫通ビアで受信した前記第２クロック信号の電圧が前記第２電圧に到達したことを検出する第２電圧検出回路を備え、
    　前記第２半導体チップの前記受信バッファは、前記第２電圧検出回路の検出信号に基づいたタイミングで比較判定動作を行うことを特徴とする半導体装置。     The semiconductor device according to claim 9.
    The first logic level and the second logic level are a low level and a high level, respectively.
    The clock output buffer of the first semiconductor chip is
    A third MISFET of the first conductivity type having a source connected to the power supply voltage and a drain connected to the third through via;
    A second MISFET of the second conductivity type having a source connected to the reference power supply voltage and a drain connected to the third through via;
    The first control circuit of the first semiconductor chip includes a first voltage detection circuit that detects that the voltage of the second clock signal has reached a predetermined second voltage,
    The first period is determined based on a period from when the first clock signal transitions from a low level to a high level until the first voltage detection circuit outputs a detection signal,
    The second semiconductor chip further includes a second voltage detection circuit that detects that the voltage of the second clock signal received by the fourth through via has reached the second voltage,
    The semiconductor device according to claim 1, wherein the reception buffer of the second semiconductor chip performs a comparison determination operation at a timing based on a detection signal of the second voltage detection circuit.
  11. 　請求項１０記載の半導体装置において、
    　前記第３ＭＩＳＦＥＴは、前記第１ＭＩＳＦＥＴよりも駆動能力が大きく設計されていることを特徴とする半導体装置。     The semiconductor device according to claim 10.
    The third MISFET is designed to have a driving capability larger than that of the first MISFET.
  12. 　請求項９記載の半導体装置において、
    　前記第１半導体チップの前記第１制御回路は、
    　前記第１クロック信号の前記第１論理レベルから前記第２論理レベルへの遷移を検出する第１エッジ検出回路と、
    　前記第１エッジ検出回路の検出信号を遅延させる第１遅延回路とを備え、
    　前記第１期間は、前記第１エッジ検出回路が検出信号を出力してから前記第１遅延回路が出力信号を出力するまでの期間に基づいて定められ、
    　前記第２半導体チップは、さらに、
    　前記第４貫通ビアで受信した前記第２クロック信号の前記第１論理レベルから前記第２論理レベルへの遷移を検出する第２エッジ検出回路と、
    　前記第２エッジ検出回路の検出信号を遅延させる第２遅延回路とを備え、
    　前記第２半導体チップの前記受信バッファは、前記第２遅延回路の出力信号に基づいたタイミングで比較判定動作を行うことを特徴とする半導体装置。     The semiconductor device according to claim 9.
    The first control circuit of the first semiconductor chip is
    A first edge detection circuit for detecting a transition of the first clock signal from the first logic level to the second logic level;
    A first delay circuit for delaying a detection signal of the first edge detection circuit,
    The first period is determined based on a period from when the first edge detection circuit outputs a detection signal to when the first delay circuit outputs an output signal,
    The second semiconductor chip further includes:
    A second edge detection circuit for detecting a transition from the first logic level to the second logic level of the second clock signal received by the fourth through via;
    A second delay circuit for delaying the detection signal of the second edge detection circuit,
    The semiconductor device, wherein the reception buffer of the second semiconductor chip performs a comparison / determination operation at a timing based on an output signal of the second delay circuit.
  13. 　請求項９記載の半導体装置において、
    　前記第１論理レベル、前記第２論理レベルは、それぞれ、ロウレベル、ハイレベルであり、
    　前記第１半導体チップの前記クロック出力バッファは、
    　ソースが前記電源電圧に、ドレインが前記第３貫通ビアに接続され、前記第１ＭＩＳＦＥＴと等しい駆動能力に設計された前記第１導電型の第５ＭＩＳＦＥＴと、
    　ソースが前記基準電源電圧に、ドレインが前記第３貫通ビアに接続され、前記第２ＭＩＳＦＥＴと等しい駆動能力に設計された前記第２導電型の第６ＭＩＳＦＥＴとを備え、
    　前記第１半導体チップは、さらに、前記第５および第６ＭＩＳＦＥＴのゲートを制御する第２制御回路を備え、
    　前記第２制御回路は、まず、前記第２クロック信号としてロウレベルを送信する際には、前記第６ＭＩＳＦＥＴをオンに駆動すると共に、前記第５ＭＩＳＦＥＴをオフに駆動することで前記第３貫通ビアを前記基準電源電圧に放電する第３処理を実行し、次いで、前記第２クロック信号としてハイレベルを送信する際には、前記第６ＭＩＳＦＥＴをオフに駆動すると共に、前記第５ＭＩＳＦＥＴを第２期間だけオンに駆動した後オフに駆動する第４処理を実行し、
    　前記第２期間は、前記第３貫通ビアを前記第１電圧に充電するのに必要な期間に設定され、
    　前記第２半導体チップは、さらに、
    　前記第４貫通ビアで受信した前記第２クロック信号を前記基準電源電圧よりも大きく前記第１電圧よりも小さい第２判定電圧を基準として比較判定するクロック入力バッファと、
    　前記クロック入力バッファの出力信号の振幅を前記電源電圧－前記基準電源電圧間のレベルに増幅するクロック増幅回路とを備え、
    　前記第２半導体チップの前記受信バッファは、前記クロック増幅回路の出力信号の立ち上がりエッジに基づいたタイミングで比較判定動作を行うことを特徴とする半導体装置。     The semiconductor device according to claim 9.
    The first logic level and the second logic level are a low level and a high level, respectively.
    The clock output buffer of the first semiconductor chip is
    A fifth MISFET of the first conductivity type having a source connected to the power supply voltage, a drain connected to the third through via, and designed to have a driving capability equal to that of the first MISFET;
    A second conductivity type sixth MISFET having a source connected to the reference power supply voltage, a drain connected to the third through via, and a drive capability equal to that of the second MISFET;
    The first semiconductor chip further includes a second control circuit for controlling gates of the fifth and sixth MISFETs,
    First, when transmitting a low level as the second clock signal, the second control circuit drives the sixth MISFET on, and drives the fifth MISFET off to thereby turn off the third through via. When the third process of discharging to the reference power supply voltage is performed and then a high level is transmitted as the second clock signal, the sixth MISFET is driven off and the fifth MISFET is turned on only for the second period. The fourth process of driving off after driving is executed,
    The second period is set to a period necessary for charging the third through via to the first voltage,
    The second semiconductor chip further includes:
    A clock input buffer for comparing and determining the second clock signal received by the fourth through via with reference to a second determination voltage larger than the reference power supply voltage and smaller than the first voltage;
    A clock amplification circuit that amplifies the amplitude of the output signal of the clock input buffer to a level between the power supply voltage and the reference power supply voltage;
    The semiconductor device according to claim 1, wherein the reception buffer of the second semiconductor chip performs a comparison / determination operation at a timing based on a rising edge of an output signal of the clock amplifier circuit.
  14. 　請求項８記載の半導体装置において、
    　前記第２半導体チップは、さらに、前記受信バッファの前記第１判定電圧を生成する電圧生成回路を備え、
    　前記電圧生成回路は、
    　一端が前記電源電圧に接続された第１スイッチと、
    　それぞれ、異なった容量値を持ち、前記第１スイッチの他端への接続有無が第１設定信号によって制御される第１容量群と、
    　一端が前記基準電源電圧に接続された第２スイッチと、
    　それぞれ、異なった容量値を持ち、前記第２スイッチの他端への接続有無が第２設定信号によって制御される第２容量群と、
    　オンの際に前記第１スイッチの他端と前記第２スイッチの他端を接続する第３スイッチとを備え、
    　前記第１判定電圧は、前記第１設定信号および前記第２設定信号によって所望の前記第１容量群および前記第２容量群を選択すると共に、前記第１～第３スイッチを適宜制御し、この選択された第１容量群と第２容量群の電荷を配分することによって生成されることを特徴とする半導体装置。     The semiconductor device according to claim 8.
    The second semiconductor chip further includes a voltage generation circuit that generates the first determination voltage of the reception buffer,
    The voltage generation circuit includes:
    A first switch having one end connected to the power supply voltage;
    A first capacitance group having a different capacitance value and having a connection to the other end of the first switch controlled by a first setting signal;
    A second switch having one end connected to the reference power supply voltage;
    A second capacitance group having different capacitance values, each having a connection with the other end of the second switch controlled by a second setting signal;
    A third switch that connects the other end of the first switch and the other end of the second switch when turned on;
    The first determination voltage selects a desired first capacitance group and the second capacitance group by the first setting signal and the second setting signal, and appropriately controls the first to third switches. A semiconductor device generated by distributing charges of a selected first capacitor group and second capacitor group.
  15. 　外部から伝送された情報信号を受信する受信端子と、
    　外部から伝送されたクロック信号を受信するクロック受信端子と、
    　電源電圧（ＶＤ）と前記電源電圧よりも小さい基準電源電圧（ＶＳ）によって動作し、前記受信端子で受信した情報信号を判定電圧を基準として比較判定する受信バッファとを有し、
    　前記判定電圧は、（（ＶＤ＋ＶＳ）／２）よりも小さい値であることを特徴とする半導体装置。     A receiving terminal for receiving an information signal transmitted from the outside;
    A clock receiving terminal for receiving a clock signal transmitted from the outside;
    A reception buffer that operates with a power supply voltage (VD) and a reference power supply voltage (VS) smaller than the power supply voltage, and compares and determines an information signal received at the reception terminal with reference to a determination voltage;
    The semiconductor device according to claim 1, wherein the determination voltage is a value smaller than ((VD + VS) / 2).
  16. 　請求項１５記載の半導体装置において、
    　前記半導体装置は、さらに、前記クロック受信端子で受信した前記クロック信号の立ち上がり電圧が所定の電圧に到達したことを検出する電圧検出回路を備え、
    　前記受信バッファは、前記電圧検出回路の検出信号に基づいたタイミングで比較判定動作を行うことを特徴とする半導体装置。     The semiconductor device according to claim 15, wherein
    The semiconductor device further includes a voltage detection circuit that detects that a rising voltage of the clock signal received at the clock receiving terminal has reached a predetermined voltage.
    The semiconductor device according to claim 1, wherein the reception buffer performs a comparison determination operation at a timing based on a detection signal of the voltage detection circuit.
  17. 　請求項１５記載の半導体装置において、
    　前記クロック受信端子で受信した前記クロック信号のエッジを検出するエッジ検出回路と、
    　前記エッジ検出回路の検出信号を遅延させる遅延回路とを備え、
    　前記受信バッファは、前記遅延回路の出力信号に基づいたタイミングで比較判定動作を行うことを特徴とする半導体装置。     The semiconductor device according to claim 15, wherein
    An edge detection circuit for detecting an edge of the clock signal received at the clock reception terminal;
    A delay circuit for delaying the detection signal of the edge detection circuit,
    The semiconductor device according to claim 1, wherein the reception buffer performs a comparison determination operation at a timing based on an output signal of the delay circuit.
  18. 　請求項１５記載の半導体装置において、さらに、
    　前記クロック受信端子で受信した前記クロック信号を前記判定電圧を基準として比較判定するクロック入力バッファと、
    　前記クロック入力バッファの出力信号の振幅を前記電源電圧－前記基準電源電圧間のレベルに増幅する増幅回路とを備え、
    　前記受信バッファは、前記増幅回路の出力信号のエッジに基づいたタイミングで比較判定動作を行うことを特徴とする半導体装置。     16. The semiconductor device according to claim 15, further comprising:
    A clock input buffer for comparing and determining the clock signal received at the clock receiving terminal with reference to the determination voltage;
    An amplification circuit that amplifies the amplitude of the output signal of the clock input buffer to a level between the power supply voltage and the reference power supply voltage;
    The semiconductor device according to claim 1, wherein the reception buffer performs a comparison determination operation at a timing based on an edge of an output signal of the amplifier circuit.
  19. 　請求項１５記載の半導体装置において、さらに、
    　前記判定電圧を生成する電圧生成回路を備え、
    　前記電圧生成回路は、
    　一端が前記電源電圧に接続された第１スイッチと、
    　それぞれ、異なった容量値を持ち、前記第１スイッチの他端への接続有無が第１設定信号によって制御される第１容量群と、
    　一端が前記基準電源電圧に接続された第２スイッチと、
    　それぞれ、異なった容量値を持ち、前記第２スイッチの他端への接続有無が第２設定信号によって制御される第２容量群と、
    　オンの際に前記第１スイッチの他端と前記第２スイッチの他端を接続する第３スイッチとを備え、
    　前記判定電圧は、前記第１設定信号および前記第２設定信号によって所望の前記第１容量群および前記第２容量群を選択すると共に、前記第１～第３スイッチを適宜制御し、この選択された第１容量群と第２容量群の電荷を配分することによって生成されることを特徴とする半導体装置。     16. The semiconductor device according to claim 15, further comprising:
    A voltage generation circuit for generating the determination voltage;
    The voltage generation circuit includes:
    A first switch having one end connected to the power supply voltage;
    A first capacitance group having a different capacitance value and having a connection to the other end of the first switch controlled by a first setting signal;
    A second switch having one end connected to the reference power supply voltage;
    A second capacitance group having different capacitance values, each having a connection with the other end of the second switch controlled by a second setting signal;
    A third switch that connects the other end of the first switch and the other end of the second switch when turned on;
    The determination voltage is selected by selecting the desired first capacitance group and the second capacitance group according to the first setting signal and the second setting signal, and appropriately controlling the first to third switches. Further, the semiconductor device is generated by distributing charges of the first capacitor group and the second capacitor group.
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US9627340B2 (en) 2015-05-28 2017-04-18 Kabushiki Kaisha Toshiba Semiconductor device
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