WO2011007483A1 - Vertical transistor, manufacturing method therefor, and semiconductor device - Google Patents

Vertical transistor, manufacturing method therefor, and semiconductor device Download PDF

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WO2011007483A1
WO2011007483A1 PCT/JP2010/002777 JP2010002777W WO2011007483A1 WO 2011007483 A1 WO2011007483 A1 WO 2011007483A1 JP 2010002777 W JP2010002777 W JP 2010002777W WO 2011007483 A1 WO2011007483 A1 WO 2011007483A1
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nitride
vertical transistor
oxide film
conductive
electrode
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PCT/JP2010/002777
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French (fr)
Japanese (ja)
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大田一樹
安藤裕二
井上隆
岡本康宏
中山達峰
遠藤一臣
宮本広信
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日本電気株式会社
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Priority to JP2011522688A priority Critical patent/JP5468609B2/en
Publication of WO2011007483A1 publication Critical patent/WO2011007483A1/en

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Definitions

  • the present invention relates to a vertical transistor, a manufacturing method thereof, and a semiconductor device. More specifically, the present invention relates to a vertical transistor using a nitride-based semiconductor and a manufacturing method thereof. The present invention also relates to a semiconductor device on which the vertical transistor is mounted.
  • Nitride-based semiconductors such as GaN, AlGaN, InGaN, InAlN, and InAlGaN have the characteristics of having high dielectric breakdown strength, high thermal conductivity, and high electron saturation speed. For this reason, nitride-based semiconductors are promising as semiconductor materials for use in the production of power devices for power control such as high-frequency devices and switching elements. In recent years, field-effect transistors using nitride-based semiconductor materials have been actively developed and developed.
  • nitride-based semiconductors In the application of nitride-based semiconductors to high-frequency devices and power devices for power control, nitride semiconductors are epitaxially grown on inexpensive dissimilar substrates such as sapphire, silicon carbide (SiC), and silicon (Si) to produce devices. It has become common to do. Compared to the case of using a GaN substrate with extremely high manufacturing cost, the manufacturing cost can be reduced.
  • lateral transistors using two-dimensional electron gas (2DEG: 2 Dimensional Electron Gas) accumulated by polarization at the epitaxially grown AlGaN / GaN heterojunction interface have been developed. It is ahead.
  • 2DEG 2 Dimensional Electron Gas
  • both the source electrode and the drain electrode must be formed on the wafer surface, and (2) a long drift region for obtaining a high breakdown voltage must be formed along the surface.
  • the device area tends to increase. Therefore, from the viewpoint of reducing the on-resistance per unit area, it is desired to develop a vertical transistor in which the drain electrode is formed on the back surface and the drift region is formed in the thickness direction of the substrate.
  • a vertical transistor is manufactured using a wafer obtained by epitaxially growing a nitride-based semiconductor on a substrate such as sapphire, silicon carbide (SiC), or silicon (Si).
  • a substrate such as sapphire, silicon carbide (SiC), or silicon (Si).
  • SiC silicon carbide
  • Si silicon
  • a nitride semiconductor epitaxial layer such as GaN or AlGaN is grown on the buffer layer.
  • a vertical transistor is manufactured by forming a source electrode on the front surface of the wafer and a drain electrode on the back surface of the substrate.
  • an AlN layer having a large band gap between the substrate and the nitride semiconductor epitaxial layer serves as a barrier.
  • a large resistance exists between the substrate and the nitride semiconductor epitaxial layer.
  • Patent Document 1 discloses a vertical transistor manufactured by bonding a GaN thin film to a different substrate.
  • FIG. 7 is a schematic cross-sectional view of a GaN-based vertical transistor disclosed in Patent Document 1.
  • a GaN-based vertical transistor described in Patent Document 1 has a conductive (carrier concentration: 4 ⁇ 10 18 cm ⁇ 3) and specific resistance: 0.01 ⁇ cm on a conductive Si substrate (heterogeneous substrate) 150A as a substrate.
  • GaN thin film bonded substrate 150 to which single crystal GaN thin film 150B is bonded is used.
  • n ⁇ -type GaN layer 113 (electron concentration: 1 ⁇ 10 16 cm ⁇ ) formed as a GaN-based semiconductor layer 120 by MOCVD (Metal Organic Chemical Vapor Deposition) method. 3 ), a p-type layer 114 into which Mg ions are implanted is formed in a partial region of the n ⁇ -type GaN layer 113, and n + into which a partial region of the p-type layer 114 is implanted with Si ions.
  • a mold layer 115 is formed.
  • An insulating film 116 made of SiO 2 having a thickness of 50 nm formed by p-CVD (Chemical Vapor Deposition) is formed on the GaN-based semiconductor layer 120, and the insulating film 116 is partially opened.
  • a source electrode 152 made of Ti / Al / Ti / Au is formed in the region.
  • a gate electrode 151 made of Al is formed on a part of the insulating film 116 to form a MIS (metal-insulator-semiconductor) structure.
  • a drain electrode 153 made of Ti / Al / Ti / Au is formed on the back surface of the conductive Si substrate (different substrate) 150A.
  • Patent Document 1 since there is no AlN layer having a large band gap between the Si substrate (heterogeneous substrate) 150A and the GaN thin film 150B, a method of epitaxially growing a nitride-based semiconductor layer on the Si substrate described above is used. In comparison, the on-resistance can be reduced.
  • the present invention has been made in view of the above-described problems, and an object of the present invention is to provide a vertical transistor capable of effectively reducing on-resistance, a manufacturing method thereof, and a semiconductor device.
  • the vertical transistor according to the present invention includes a conductive semiconductor substrate, a conductive oxide film formed on the surface of the conductive semiconductor substrate and having a specific resistance of 3 ⁇ 10 ⁇ 4 ⁇ cm or less, and is attached on the conductive oxide film. And an n + -type or p + -type nitride semiconductor thin film having an impurity concentration of 5 ⁇ 10 17 cm ⁇ 3 or more, and a nitride semiconductor epitaxially grown on the nitride semiconductor thin film.
  • a stack a source electrode or emitter electrode formed on the surface of the stack, a drain electrode or collector electrode formed on the back surface of the conductive semiconductor substrate, and between the source electrode and the drain electrode, or And a gate electrode having a function of controlling a magnitude of a current flowing between the emitter electrode and the collector electrode.
  • a conductive oxide film is formed on a conductive semiconductor substrate, a nitride semiconductor thin film is formed on the conductive oxide film, and the nitride semiconductor thin film is formed.
  • a layered body made of a nitride semiconductor is epitaxially grown on the upper layer, a source electrode or an emitter electrode is formed on the surface of the layered body, and a drain electrode or a collector electrode is formed on the back surface of the conductive semiconductor substrate.
  • FIG. 2 is a schematic cross-sectional view schematically illustrating an example of a configuration of a vertical transistor according to the first embodiment.
  • FIG. 4 is a manufacturing process cross-sectional view of the vertical transistor according to the first embodiment.
  • FIG. 4 is a manufacturing process cross-sectional view of the vertical transistor according to the first embodiment.
  • FIG. 4 is a manufacturing process cross-sectional view of the vertical transistor according to the first embodiment.
  • FIG. 4 is a manufacturing process cross-sectional view of the vertical transistor according to the first embodiment.
  • FIG. 4 is a manufacturing process cross-sectional view of the vertical transistor according to the first embodiment.
  • FIG. 5 is a schematic cross-sectional view schematically illustrating an example of a configuration of a vertical transistor according to a second embodiment.
  • FIG. 10 is a manufacturing process cross-sectional view of a vertical transistor according to the second embodiment.
  • FIG. 10 is a manufacturing process cross-sectional view of a vertical transistor according to the second embodiment.
  • FIG. 10 is a manufacturing process cross-sectional view of a vertical transistor according to the second embodiment.
  • FIG. 5 is a schematic cross-sectional view schematically illustrating an example of a configuration of a vertical transistor according to a third embodiment.
  • FIG. 10 is a manufacturing process cross-sectional view of a vertical transistor according to the second embodiment.
  • FIG. 10 is a manufacturing process cross-sectional view of a vertical transistor according to the second embodiment.
  • FIG. 10 is a manufacturing process cross-sectional view of a vertical transistor according to the second embodiment.
  • FIG. 10 is a schematic cross-sectional view of a vertical transistor described in Patent Document 1.
  • a conductive oxide film having a specific resistance of 3 ⁇ 10 ⁇ 4 ⁇ cm or less is formed on the surface of the conductive semiconductor substrate.
  • An n + type or p + type nitride-based semiconductor thin film formed by bonding is disposed on the conductive oxide film.
  • the impurity concentration of this nitride-based semiconductor thin film is 5 ⁇ 10 17 cm ⁇ 3 or more.
  • a laminated body made of the nitride semiconductor epitaxially grown is formed on the nitride semiconductor thin film.
  • the source electrode or emitter electrode of the vertical transistor is formed on the surface of the stacked body.
  • the drain electrode or the collector electrode is formed on the back side of the conductive semiconductor substrate.
  • the gate electrode has a function of controlling the magnitude of a current flowing between the source electrode and the drain electrode or between the emitter electrode and the collector electrode.
  • FIG. 1 is a cross-sectional view schematically showing the structure of the vertical transistor according to the first embodiment.
  • the vertical transistor 1 according to the first embodiment includes a conductive semiconductor substrate 50, a gate electrode 51, a source electrode 52, a drain electrode 53, a conductive oxide film 11, a nitride semiconductor thin film 12, and a stacked semiconductor film.
  • the body 20 and the insulating film 16 are provided.
  • the conductive semiconductor substrate 50 can be applied without particular limitation as long as it does not depart from the spirit of the present invention. From the viewpoint of reducing the manufacturing cost, it is preferable to select a material that can obtain a large-diameter substrate of 6 inches or more at a low cost. Suitable examples of such a conductive semiconductor substrate material include Si, poly-Si, poly-SiC and the like. By applying these, a low on-resistance vertical transistor can be manufactured at low cost. In the first embodiment, n-type Si having a specific resistance of 0.02 ⁇ cm is applied.
  • the conductive oxide film 11 is formed on the conductive semiconductor substrate 50.
  • the specific resistance of the conductive oxide film 11 is at least 3 ⁇ 10 ⁇ 4 ⁇ cm or less. By setting it to 3 ⁇ 10 ⁇ 4 ⁇ cm or less, it is possible to obtain an effect that the on-resistance can be lowered as compared with the case where the nitride-based semiconductor thin film 12 is directly bonded to the conductive semiconductor substrate 50 as in the prior art.
  • a more preferable range is 2 ⁇ 10 ⁇ 4 ⁇ cm or less, and a particularly preferable range is 1 ⁇ 10 ⁇ 4 ⁇ cm or less.
  • the lower limit value of the specific resistance of the conductive oxide film 11 is not particularly limited, but is preferably 2 ⁇ 10 ⁇ 6 ⁇ cm or more in order to realize a high-quality film quality that does not deteriorate strength or resistance due to long-term conduction.
  • the material of the conductive oxide film 11 can be applied without particular limitation as long as it does not depart from the spirit of the present invention. From the viewpoint of obtaining a stable and strong bonded substrate, the conductive oxide film 11 preferably has a melting point of 1300 ° C. or higher. By using a material having a high melting point in this way, even for manufacturing processes that require high temperatures of about 1000 ° C., such as crystal growth of nitride-based semiconductors by metal organic vapor phase epitaxy (MOVPE).
  • MOVPE metal organic vapor phase epitaxy
  • a stable and strong bonded substrate can be obtained.
  • the upper limit of the melting point of the conductive oxide film 11 is not particularly limited.
  • Al-doped ZnO (ZAO) having a specific resistance of 2 ⁇ 10 ⁇ 4 ⁇ cm is used as the conductive oxide film 11.
  • the film thickness of the conductive oxide film 11 is not particularly limited, but can be, for example, 5 nm or more and 1000 nm or less. A more preferable range is 10 nm or more and 500 nm or less, and a particularly preferable range is 20 nm or more and 300 nm or less.
  • the nitride-based semiconductor thin film 12 can be formed by bonding a nitride-based semiconductor bulk crystal on the conductive oxide film 11 and dividing it in the thickness direction.
  • the impurity concentration of the nitride-based semiconductor thin film 12 is 5 ⁇ 10 17 cm ⁇ 3 or more. By setting it to 5 ⁇ 10 17 cm ⁇ 3 or more, it is possible to obtain an effect that the nitride-based semiconductor thin film 12 and the conductive oxide film 11 can be connected with a sufficiently low resistance.
  • a more preferable range is 1 ⁇ 10 18 cm ⁇ 3 or more.
  • the upper limit of the impurity concentration of the nitride-based semiconductor thin film 12 is preferably 5 ⁇ 10 20 cm ⁇ 3 or less.
  • n + -GaN having an impurity concentration of 5 ⁇ 10 18 cm ⁇ 3 and a film thickness of 0.1 ⁇ m is formed.
  • the stacked body 20 made of a nitride-based semiconductor is formed on the nitride-based semiconductor thin film 12.
  • the stacked body 20 is obtained by epitaxial growth.
  • the drift layer 13, the channel layer 14, and the contact layer 15 are formed in this order from the nitride-based semiconductor thin film 12 side.
  • n ⁇ -GaN having an impurity concentration of 1 ⁇ 10 16 cm ⁇ 3 and a film thickness of 3 ⁇ m is used as the drift layer 13, and a film having an impurity concentration of 1 ⁇ 10 18 cm ⁇ 3 is used as the channel layer 14.
  • P-GaN having a thickness of 0.6 ⁇ m was used as the contact layer 15 and n + -GaN having an impurity concentration of 3 ⁇ 10 18 cm ⁇ 3 and a thickness of 0.5 ⁇ m was applied.
  • the source electrode 52 is formed on the surface of the contact layer 15, and the drain electrode 53 is formed on the back surface of the conductive semiconductor substrate 50.
  • an electrode made of Ti / Al Ti is a lower layer side and Al is an upper layer side (hereinafter the same)) is applied.
  • a part of the stacked body 20 is formed with an upper surface side trench 21 reaching the drift layer 13 from the surface thereof, and contacts extending from the inner and bottom surfaces of the upper surface side trench 21 and the inner wall of the upper surface side trench 21.
  • a part of the surface of the layer 15 is covered with a gate insulating film 16 made of SiO 2 . Furthermore, a gate electrode 51 made of Ni / Au is formed on the inner wall and bottom surface of the upper surface side trench 21.
  • the first embodiment is a so-called trench gate type field effect transistor in which a channel is formed by the channel layer 14 in contact with the side surface of the upper side trench 21 being an inversion region.
  • the conductive oxide film 11 is formed on the conductive semiconductor substrate 50, and the nitride-based semiconductor thin film 12 is formed on the conductive oxide film 11.
  • the stacked body 20 made of the nitride-based semiconductor is epitaxially grown on the nitride-based semiconductor thin film 12 to form the source electrode 52 on the surface of the stacked body 20.
  • the drain electrode 53 is formed on the back surface of the conductive semiconductor substrate 50.
  • FIGS. 2A to 2E are cross-sectional views schematically showing the manufacturing process of the vertical transistor according to the first embodiment.
  • a nitride-based semiconductor bulk crystal 30 in which the bonding surface with the conductive semiconductor substrate 50 is mirror-polished is prepared.
  • a GaN bulk crystal is prepared as the nitride-based semiconductor bulk crystal 30.
  • hydrogen ions are implanted, for example, to a depth of 0.1 ⁇ m from the bonding surface (hereinafter also referred to as “N surface (nitrogen atom surface)”) (FIG. 2A).
  • N surface (nitrogen atom surface) hydrogen ions
  • helium ions or nitrogen ions may be used instead of hydrogen ions.
  • mirror polishing of a nitride semiconductor bulk crystal is not always essential. However, the surface roughness should be at a level that does not cause a problem in bonding the nitride semiconductor bulk crystal 30 and the conductive oxide film 11.
  • a conductive oxide film 11 made of Al-doped ZnO (ZAO) is formed on the conductive semiconductor substrate 50 by sputtering (FIG. 2B).
  • the N surface of the nitride-based semiconductor bulk crystal 30 and the surface of the conductive oxide film 11 are bonded together by a fusion bonding method or the like.
  • the nitride semiconductor bulk crystal 30 is divided in the thickness direction at the hydrogen ion implantation surface by performing a heat treatment at 450 ° C.
  • the nitride-based semiconductor thin film 12 is formed (FIG. 2C).
  • the nitride semiconductor bulk crystal 30 is separated from the conductive semiconductor substrate 50 side at a depth of, for example, 0.1 ⁇ m.
  • the bonding of the nitride-based semiconductor bulk crystal 30 and the conductive semiconductor substrate 50 is not limited to the fusion bonding method, and a known method can be applied without limitation.
  • the N surface may be bonded by a surface activation method in which the surface is activated by exposing it to plasma and then bonded.
  • the method for obtaining the nitride-based semiconductor thin film 12 is not limited to the method using the nitride-based semiconductor bulk crystal described above, and various methods can be adopted without departing from the spirit of the present invention. it can.
  • a nitride-based semiconductor thin film may be obtained by epitaxially growing a nitride-based semiconductor on a heterogeneous substrate, and bonding the growth surface side onto a conductive oxide film, and then peeling the heterogeneous substrate.
  • the drift layer 13 made of n ⁇ -GaN having an impurity concentration of 1 ⁇ 10 16 cm ⁇ 3 and a film thickness of 3 ⁇ m is formed on the nitride semiconductor thin film 12 by metal organic vapor phase epitaxy, and the impurity concentration is 1 ⁇ 10 18 cm ⁇ 3 channel layer 14 made of p-GaN having a film thickness of 0.6 ⁇ m, and n + -GaN contact layer having an impurity concentration of 3 ⁇ 10 18 cm ⁇ 3 and a film thickness of 0.5 ⁇ m. Layer 15 is grown in this order (FIG. 2D).
  • the source electrode 52 is formed. Specifically, a Ti / Al (30 nm / 180 nm) electrode pattern is formed by vapor deposition / lift-off using a photoresist mask in which an opening pattern is formed in a region where the source electrode 52 is formed. Then, the source electrode 52 is obtained by performing RTA (Rapid Thermal Thermal) at 700 ° C. for 60 seconds.
  • RTA Rapid Thermal Thermal
  • an upper surface side trench 21 reaching the drift layer 13 from the surface of the contact layer 15 is formed. Specifically, it is formed by an ICP (Inductively Coupled Plasma) dry etching method using a photoresist mask in which an opening pattern is formed in a predetermined region. Then, in order to remove damage on the inner wall of the upper surface side trench 21, a wet etching process using NH 4 OH (ammonia water) is performed. Thereafter, the gate insulating film 16 that covers the inner wall surface and the edge of the upper-side trench 21 is formed by using an ECR (Electron Cyclotron Resonance) sputtering method (FIG. 2E).
  • ICP Inductively Coupled Plasma
  • the gate electrode 51 is formed. Specifically, a Ni / Au (30 nm / 300 nm) electrode pattern is formed at a predetermined position by using a vapor deposition / lift-off method using a photoresist mask in which an opening pattern is formed in a region where the gate electrode 51 is formed. To do.
  • the drain electrode 53 is formed. Specifically, first, the back surface of the conductive semiconductor substrate 50 is polished and thinned. Thereafter, a drain electrode 53 made of Ti / Al is formed on the back surface of the conductive semiconductor substrate 50 using a vacuum deposition method. Through the above steps, a vertical transistor made of a nitride-based semiconductor having the configuration shown in FIG. 1 is manufactured.
  • the first cause of difficulty in sufficiently reducing the resistance at the bonding interface is a large difference between the Si band gap (1.1 eV) and the GaN band gap (3.4 eV).
  • a band gap difference (2.3 eV)
  • a very large band discontinuity of about 1 eV exists in the conduction band and valence band of the bonding interface.
  • this band discontinuity becomes a large potential barrier, a large resistance is generated at the Si / GaN interface. That is, in the configuration in which the conductive Si substrate 150A and the conductive GaN thin film 150B are bonded together, it is difficult to sufficiently reduce the on-resistance of the vertical transistor.
  • the second cause that it is difficult to sufficiently reduce the resistance at the bonding interface is due to bonding of semiconductor materials such as the Si substrate 150A and the GaN thin film 150B.
  • semiconductor materials such as the Si substrate 150A and the GaN thin film 150B.
  • a large amount of dangling bonds (dangling bonds) exist at the bonding interface.
  • this unbonded hand functions as a carrier trap.
  • the occurrence of interface resistance due to carrier traps at the interface is inevitable at the bonding interface.
  • the materials to be bonded are Si and GaN, both of which are semiconductors.
  • the semiconductor material can be made conductive by adding impurities, but the specific resistance obtained in a state of maintaining good crystallinity is at most about 1 ⁇ 10 ⁇ 2 ⁇ cm. That is, both layers to be bonded are made of a material having a high specific resistance, and it is difficult to sufficiently reduce the interface resistance. This problem cannot be solved even when another semiconductor substrate such as a single crystal SiC substrate is used instead of the Si substrate. As a result, with the configuration shown in FIG. 7, it was difficult to manufacture a vertical transistor with sufficiently reduced on-resistance.
  • the specific resistance is 3 ⁇ 10 ⁇ 4 ⁇ cm or less (in the specific example, 2 ⁇ 10 ⁇ 4 ⁇ cm) between the conductive semiconductor substrate 50 and the nitride-based semiconductor thin film 12.
  • a conductive oxide film 11 is provided. Thereby, a junction can be formed without generating a large interface resistance at the interface between the conductive oxide film 11 and the conductive semiconductor substrate 50. For the same reason, a junction can be formed without generating a large interface resistance at the interface between the conductive oxide film 11 and the nitride-based semiconductor thin film 12.
  • the conductive oxide film 11 is made of a material having a band gap of Al-doped ZnO (ZAO) close to GaN (ZnO: 3.3 eV, GaN: 3.4 eV).
  • ZnO Al-doped ZnO
  • the interfacial resistance at the interface between the conductive oxide film 11 and the nitride-based semiconductor thin film 12 can be particularly reduced.
  • the Si substrate is used as the conductive semiconductor substrate, there is an advantage that it is inexpensive.
  • the vertical transistor 1 according to the first embodiment has an on-resistance of about several tens of percent to about half that of a gate-type field effect transistor manufactured using a conventional low-cost bonding technique. Can be reduced.
  • the conductive oxide film 11 having a low specific resistance of 3 ⁇ 10 ⁇ 4 ⁇ cm or less is disposed between the conductive semiconductor substrate 50 and the nitride-based semiconductor thin film 12.
  • the interface resistance can be greatly reduced at any of the interfaces of the conductive semiconductor substrate 50 / conductive oxide film 11 and conductive oxide film 11 / nitride-based semiconductor thin film 12.
  • a low on-resistance vertical transistor can be realized.
  • the vertical transistor 2 according to the second embodiment is a so-called insulated gate bipolar transistor (IGBT: Insulated Gate Gate Bipolar Transistor) in which a P collector is added to the drain side of the N-channel vertical MOSFET.
  • IGBT Insulated Gate Gate Bipolar Transistor
  • the basic structure of the vertical transistor according to the second embodiment is the same as that of the first embodiment except for the following points.
  • the upper surface side trench 21 is formed in the stacked body 20 in the first embodiment, but the second embodiment is different in that the upper surface side trench 21 is not formed in the stacked body. Therefore, the structure of the laminate is different from that of the first embodiment. Accordingly, the shapes of the insulating film and the gate electrode arranged on the upper layer of the stacked body are different.
  • the source electrode is disposed in the upper layer of the stacked body 20
  • the emitter electrode is formed in the upper layer of the stacked body 20 instead of the source electrode. Is different.
  • the drain electrode is formed on the back side of the conductive semiconductor substrate 50, whereas in the second embodiment, the drain electrode is changed to the collector electrode on the back side of the conductive semiconductor substrate. The difference is that an electrode is formed.
  • FIG. 3 is a cross-sectional view schematically showing the structure of the vertical transistor according to the second embodiment.
  • the vertical transistor 2 according to the second embodiment includes a conductive semiconductor substrate 50a, a gate electrode 51a, an emitter electrode 55, a collector electrode 56, a conductive oxide film 11a, a nitride-based semiconductor thin film 12a, and a stacked layer including a nitride-based semiconductor.
  • the vertical transistor 2 has at least the following structure. That is, the conductive oxide film 11a having a specific resistance of 3 ⁇ 10 ⁇ 4 ⁇ cm or less is formed on the conductive semiconductor substrate 50a. On the conductive oxide film 11a, a p + -type nitride-based semiconductor thin film 12a having an impurity concentration of 5 ⁇ 10 17 cm ⁇ 3 or more is formed. On the nitride semiconductor thin film 12a, a stacked body 20a made of a nitride semiconductor obtained by epitaxial growth is formed. An emitter electrode 55 is formed on the surface of the stacked body 20a, and a collector electrode 56 is formed on the back surface of the conductive semiconductor substrate 50a. A gate electrode 51a having a function of controlling the magnitude of the current flowing between the emitter electrode 55 and the collector electrode 56 is formed.
  • the second embodiment will be described.
  • the configuration, preferable materials, and the like of the conductive semiconductor substrate 50a are as described in the first embodiment.
  • p-type poly SiC having a specific resistance of 0.04 ⁇ cm is used.
  • the specific resistance range and preferred materials of the conductive oxide film 11a are the same as those in the first embodiment.
  • ITO having a specific resistance of 1.5 ⁇ 10 ⁇ 4 ⁇ cm is used as the conductive oxide film 11a.
  • p + -GaN having an impurity concentration of 1 ⁇ 10 18 cm ⁇ 3 and a film thickness of 0.3 ⁇ m was used as the nitride-based semiconductor thin film 12a.
  • the band gap of the conductive oxide film is 2.8 eV to 4.0 eV.
  • a conductive material having a band gap in this range it is possible to more effectively reduce the interface resistance with the nitride-based semiconductor thin film formed immediately above the conductive material. This is because the band gap difference from the nitride semiconductor thin film can be reduced (when GaN is applied as the nitride semiconductor thin film, the band gap is 3.4 eV).
  • Suitable materials for the conductive oxide film having a band gap of 2.8 eV to 4.0 eV include ITO, ZnO, TiO 2 , SnO 2 , CdO, and the like. Further, in order to effectively reduce the specific resistance, a material obtained by adding a metal impurity to the above-described material can be suitably applied.
  • the stacked body 20a includes a drift layer 13a, a channel layer 14a, and a contact layer 15a.
  • the drift layer 13a is made of n ⁇ -GaN having an impurity concentration of 1 ⁇ 10 16 cm ⁇ 3 and a film thickness of 5 ⁇ m
  • the channel layer 14a is made of p-GaN having an impurity concentration of 1 ⁇ 10 18 cm ⁇ 3. Applied. Further, n + -GaN having an impurity concentration of 5 ⁇ 10 18 cm ⁇ 3 was applied to the contact layer 15a.
  • the shape of the drift layer 13a has a structure having convex portions as shown in FIG.
  • the channel layer 14a and the contact layer 15a are formed in this order on both sides of the protruding portion of the drift layer 13a (see FIG. 3).
  • the emitter electrode 55 is formed at a predetermined position on the surface of the contact layer 15a. As described above, the collector electrode 56 is formed on the back side of the conductive semiconductor substrate 50a.
  • the emitter electrode 55 and the collector electrode 56 are both made of Ti / Al. Of course, the composition ratio and the like of the emitter electrode 55 and the collector electrode 56 can be changed as appropriate and do not need to match. Different materials may be used.
  • a gate insulating film 16a is formed so as to cover a part of the surface of the contact layer 15a, the entire surface of the channel layer 14a, and at least a part of the surface of the drift layer 13a.
  • the gate electrode 51a is formed on the gate insulating film 16a so as to be opposed to the drift layer 13a, the channel layer 14a disposed outside the gate insulating film 16a, and the contact layer 15a.
  • Ni / Au is applied as the gate electrode 51a.
  • the vertical transistor 2 according to the second embodiment is configured as described above.
  • the conductive oxide film 11a is formed on the conductive semiconductor substrate 50a, and the nitride-based semiconductor thin film 12a is formed on the conductive oxide film 11a. Then, a stacked body 20a made of a nitride-based semiconductor is epitaxially grown on the nitride-based semiconductor thin film 12a, and an emitter electrode 55 is formed on the surface of the stacked body 20a. Then, a collector electrode 56 is formed on the back surface of the conductive semiconductor substrate 50a.
  • FIGS. 4A to 4C are cross-sectional views schematically showing the manufacturing process of the vertical transistor according to the second embodiment.
  • a substrate in which the conductive oxide film 11a and the nitride semiconductor thin film 12a are bonded to the conductive semiconductor substrate 50a is manufactured (FIG. 4A).
  • the only difference from Embodiment 1 is that the materials are different as described above.
  • a bonded substrate can be produced in exactly the same way as in FIGS. 2A to 2C.
  • a drift layer 13a made of n ⁇ -GaN having an impurity concentration of 1 ⁇ 10 16 cm ⁇ 3 and a thickness of 5 ⁇ m is grown on the nitride-based semiconductor thin film 12a by metal organic vapor phase epitaxy.
  • Mg ions are implanted into a partial region of the drift layer 13a by selective ion implantation to form the channel layer 14a.
  • Si ions are implanted into part of the channel layer 14a to form the contact layer 15a, thereby obtaining a stacked body 20a made of a nitride-based semiconductor.
  • a gate insulating film 16a made of Al 2 O 3 is formed on the stacked body 20a by using an ALD (Atomic Layer Deposition) method.
  • a portion of the gate insulating film 16a is etched with buffered hydrofluoric acid using a photoresist mask in which an opening pattern is formed in the region where the emitter electrode 55 is to be formed.
  • 30 nm / 180 nm) electrodes are formed at predetermined positions.
  • RTA is performed at 700 ° C. for 60 seconds to obtain the emitter electrode 55 (FIG. 4C).
  • a Ni / Au (30 nm / 300 nm) electrode is formed at a predetermined position in a region where the gate electrode 51a is to be formed by using a photoresist mask having an opening pattern and using a vapor deposition / lift-off method.
  • a drain electrode 53a made of Ti / Al is formed on the back surface of the conductive semiconductor substrate 50a by using a vacuum deposition method, so that the configuration of FIG. 3 is obtained.
  • a vertical transistor is manufactured.
  • the conductive oxide film 11a having a specific resistance of 3 ⁇ 10 ⁇ 4 ⁇ cm or less (in the specific example, 1.5 ⁇ 10 ⁇ 4 ⁇ cm) is used.
  • a junction can be formed without generating large interface resistance at the interface with the semiconductor substrate 50a.
  • a junction can be formed without generating a large interface resistance at any of the interfaces between the conductive oxide film 11a and the nitride-based semiconductor thin film 12a.
  • the conductive oxide film 11a is made of a material having a band gap of ITO close to that of GaN (ITO: 3 eV, GaN: 3.4 eV), the interface between the conductive oxide film 11a and the nitride-based semiconductor thin film 12a.
  • the interfacial resistance can be made particularly low.
  • the band gap of ITO is close to the band gap (2.3 eV to 3.2 eV) of poly-SiC used for the conductive semiconductor substrate 50a, the interface between the conductive oxide film 11a and the conductive semiconductor substrate 50a. The interface resistance can be lowered.
  • the vertical transistor 2 according to the second embodiment has an on-resistance approximately several times that of an insulated gate bipolar transistor using a nitride-based semiconductor manufactured using a conventional low-cost bonding technique. It can be reduced from 10% to about half.
  • the vertical transistor according to the third embodiment is a so-called high electron mobility transistor (HEMT: High Electron Mobility Transistor).
  • HEMT High Electron Mobility Transistor
  • Embodiment 3 The basic structure of the vertical transistor according to Embodiment 3 is the same as that of Embodiment 1 except for the following points. That is, in Embodiment 1 above, no trench was formed in the conductive semiconductor substrate 50, whereas in Embodiment 3, a trench reaching the conductive oxide film was formed in the conductive semiconductor substrate. Is different. Moreover, the structure of a laminated body differs from the said Embodiment 1. FIG.
  • FIG. 5 is a cross-sectional view schematically showing the structure of the vertical transistor according to the third embodiment.
  • the vertical transistor 3 according to the third embodiment includes a conductive semiconductor substrate 50b, a gate electrode 51b, a source electrode 52b, a drain electrode 53b, a conductive oxide film 11b, a nitride-based semiconductor thin film 12b, and a stacked layer composed of a nitride-based semiconductor.
  • a body 20b and the like are provided.
  • the vertical transistor 3 has at least the following structure. That is, the conductive oxide film 11b having a specific resistance of 3 ⁇ 10 ⁇ 4 ⁇ cm or less is formed on the conductive semiconductor substrate 50b. On the conductive oxide film 11b, an n + -type or p + -type nitride-based semiconductor thin film 12b having an impurity concentration of 5 ⁇ 10 17 cm ⁇ 3 or more is formed. On the nitride semiconductor thin film 12b, a stacked body 20b made of a nitride semiconductor obtained by epitaxial growth is formed. A source electrode 52b is formed on the surface of the stacked body 20b.
  • a part of the conductive semiconductor substrate 50b is formed with a back side trench 23 that reaches the conductive oxide film 11b from the back side.
  • a drain electrode 53b is formed on the back surface of the conductive semiconductor substrate 50b and the inner wall of the back surface side trench 23 to cover them.
  • a gate electrode 51b having a function of controlling the magnitude of current flowing between the source electrode 52b and the drain electrode 53b is formed on the stacked body 20b.
  • the third embodiment will be described.
  • the configuration, preferable materials, and the like of the conductive semiconductor substrate 50b are as described in the first embodiment.
  • n-type Si having a specific resistance of 0.02 ⁇ cm is used as the conductive semiconductor substrate 50b.
  • the range of the specific resistance of the conductive oxide film 11b and preferred materials are the same as those in the first embodiment.
  • the preferable impurity concentration and the like of the nitride-based semiconductor thin film 12b are also as described in the first embodiment.
  • Nb-added TiO 2 having a specific resistance of 3 ⁇ 10 ⁇ 4 ⁇ cm is used as the conductive oxide film 11b.
  • n + -GaN having an impurity concentration of 5 ⁇ 10 18 cm ⁇ 3 and a film thickness of 0.1 ⁇ m was used as the nitride-based semiconductor thin film 12b.
  • a drift layer 13b In the stacked body 20b, a drift layer 13b, a barrier layer 17, a channel layer 14b, and an electron supply layer 18 heterojunction with the channel layer 14b are stacked in this order.
  • the drift layer 13b is made of n ⁇ -GaN with an impurity concentration of 1 ⁇ 10 16 cm ⁇ 3 and a film thickness of 4 ⁇ m
  • the barrier layer 17 is made with an impurity concentration of 1 ⁇ 10 18 cm ⁇ 3 and a film thickness of 0 .5 ⁇ m p-GaN was used.
  • the channel layer 14b was made of non-doped GaN having a thickness of 50 nm
  • the electron supply layer 18 was made of non-doped Al 0.2 Ga 0.8 N having a thickness of 30 nm.
  • a source electrode 52b made of Ti / Al and a gate electrode 51b made of Ni / Au are formed on the surface of the electron supply layer 18. Further, an n + type region 19 having an impurity concentration of 3 ⁇ 10 18 cm ⁇ 3 that functions as an electron conduction region is formed on the side where the source electrode 52b is not disposed opposite to the gate electrode 51b.
  • the n + -type region 19 functioning as an electron conducting region is formed in a region extending from at least a substantial surface of the channel layer 14b to a region closer to the nitride-based semiconductor thin film 12b side than the barrier layer 17. ing.
  • the n + -type region 19 is formed in a region that reaches a partial region of the drift layer 13b from the surface of the channel layer 14b.
  • the n + -type region 19 may be formed in a region extending from the surface of the electron supply layer 18 to a region closer to the nitride-based semiconductor thin film 12b side than the barrier layer 17.
  • a part of the conductive semiconductor substrate 50b is formed with a back side trench 23 that reaches the conductive oxide film 11b from the back side, and covers the back side of the conductive semiconductor substrate 50b and the inner wall of the back side trench 23.
  • a drain electrode 53b made of Al is formed.
  • the vertical transistor according to the third embodiment is a so-called high electron mobility transistor (HEMT: High) that uses a two-dimensional electron gas 25 accumulated by a polarization effect as a channel near the interface between the channel layer 14b and the electron supply layer 18. Electron Mobility Transistor).
  • HEMT high electron mobility transistor
  • FIGS. 6A to 6C are cross-sectional views schematically showing the manufacturing process of the vertical transistor according to the third exemplary embodiment.
  • a substrate in which the conductive oxide film 11b and the nitride semiconductor thin film 12b are bonded to the conductive semiconductor substrate 50b is manufactured (FIG. 6A).
  • the only difference from the first embodiment is the difference in material in which Nb-added TiO 2 is used for the conductive oxide film 11b.
  • a bonded substrate can be manufactured in exactly the same manner as in FIGS. 2A to 2C. .
  • a stacked body 20b is obtained on the nitride-based semiconductor thin film 12b by using a metal organic chemical vapor deposition method.
  • a drift layer 13b made of n ⁇ -GaN having an impurity concentration of 1 ⁇ 10 16 cm ⁇ 3 and a film thickness of 4 ⁇ m, and an impurity concentration of 1 ⁇ 10 18 cm ⁇ 3 and a film thickness of 0.5 ⁇ m.
  • a barrier layer 17 made of p-GaN, a channel layer 14b made of non-doped GaN having a thickness of 50 nm, and an electron supply layer 18 made of non-doped Al 0.2 Ga 0.8 N having a thickness of 30 nm are grown.
  • Si ions are implanted into a part of the stacked body 20 b to form the n + -type region layer 19. Thereafter, a 300 nm SiO 2 film is formed as a protective film (not shown) on the surface of the stacked body 20b, and then heat treatment is performed at 1250 ° C. for 60 seconds. Thereby, the implanted ions are activated. Thereafter, the protective film is removed with buffered hydrofluoric acid (FIG. 6B).
  • the source electrode 52 b is formed on the electron supply layer 18.
  • a Ti / Al (30 nm / 180 nm) electrode pattern is formed on the electron supply layer by using a photoresist mask having an opening pattern in a region where the source electrode 52b is formed, and using an evaporation / lift-off method. 18 is formed at a predetermined position on the surface. Thereafter, RTA is performed at 700 ° C. for 60 seconds to obtain the source electrode 52b.
  • a gate electrode 51b is formed on the electron supply layer 18 at a position spaced from the source electrode 52b. Specifically, using a photoresist mask in which an opening pattern is formed in a region where the gate electrode 51b is to be formed, a Ni / Al (30 nm / 300 nm) electrode pattern is formed on the electron supply layer by vapor deposition / lift-off method. 18 is formed at a predetermined position on the surface (FIG. 6C).
  • a drain electrode is formed on the back side of the conductive semiconductor substrate 50b. Specifically, after polishing and thinning the back surface of the conductive semiconductor substrate 50b, a RIE (Reactive ⁇ ⁇ ⁇ ⁇ Ion Etching) method is used using a photoresist mask in which an opening pattern is formed at a predetermined position. A back side trench 23 reaching the conductive oxide film 11b from the back side of the conductive semiconductor substrate 50b is formed.
  • a vertical electrode having the configuration of FIG. 5 is formed by forming a drain electrode 53b made of Ti / Al so as to cover the back surface of the conductive semiconductor substrate 50b and the inner wall of the back surface side trench 23 by using a vacuum evaporation method. Complete 3
  • a so-called high electron mobility transistor using a two-dimensional electron gas 25 accumulated by polarization charge as a channel at the interface between the channel layer 14b and the electron supply layer 18 is manufactured.
  • the conductive oxide film 11b having a specific resistance of 3 ⁇ 10 ⁇ 4 ⁇ cm or less (specific example: 3 ⁇ 10 ⁇ 4 ⁇ cm)
  • the conductive oxide film 11b and the conductive semiconductor substrate are used. Bonding can be performed without generating large interface resistance at the interface with 50b. For the same reason, a junction can be formed without generating a large interface resistance at the interface between the conductive oxide film 11b and the nitride-based semiconductor thin film 12b.
  • the conductive oxide film 11b is made of a material having a band gap of Nb-added TiO 2 close to that of GaN (TiO 2 : 3.2 eV, GaN: 3.4 eV), the conductive oxide film 11b and the nitride system are used.
  • the interface resistance at the interface with the semiconductor thin film 12b can be particularly lowered.
  • the back side trench 23 reaching the conductive oxide film 11b from the back side is formed in a part of the conductive semiconductor substrate 50b, and the drain electrode 53b is in direct contact with the conductive oxide film 11b. Is formed.
  • the vertical transistor according to the third embodiment has an on-resistance that is approximately several times higher than that of a high electron mobility transistor using a nitride-based semiconductor manufactured using a conventional low-cost bonding technique. It can be reduced from 10% to about half.
  • the back-side trench 23 reaching the conductive oxide film 11b is formed in a part of the conductive semiconductor substrate 50b.
  • the drain electrode 53b or the collector electrode is preferably formed so as to contact not only the back surface of the conductive semiconductor substrate 50b but also the side surface and the bottom surface of the back surface side trench 23.
  • the first to third embodiments have been described as specific examples of the present invention.
  • the materials and manufacturing processes described in the first to third embodiments are only examples and are not limited thereto. is not.
  • a GaN-based example has been described as the nitride-based semiconductor
  • the present invention can also be applied to nitride-based semiconductors such as AlGaN, InGaN, InAlN, and InAlGaN.
  • the gate insulating films 16 and 16a not only SiO 2 and Al 2 O 3 but also SiN, SiON, AlN, MgO, Sc 2 O 3 , ZrO 2 , HfO 2 , or a stacked structure thereof can be used.
  • a MIS gate structure can be formed by providing a gate insulating film between the electron supply layer 18 and the gate electrode 51b.
  • each of the channel structures shown in the first to third embodiments is not limited to this, and each channel structure can be applied to other embodiments.
  • a trench gate type IGBT can be manufactured by applying the trench gate type channel described in the first embodiment to the second embodiment.
  • the HEMT type channel shown in the third embodiment can be applied to the first embodiment.
  • the configuration in which the back-side trench 23 reaching the conductive oxide film 11b from the back surface is formed in a part of the conductive semiconductor substrate 50b shown in the third embodiment is applicable to the first and second embodiments.
  • the number of layers, the thickness, the composition, and the like of the laminate obtained by epitaxially growing the nitride-based semiconductor are not limited to the structures described in the first to third embodiments.
  • the example in which the drift layer 13a made of n ⁇ -GaN is grown on the nitride semiconductor thin film 12a made of p + -GaN obtained by bonding has been described.
  • the epitaxial growth start interface and the pn junction interface coincide with each other, the p + -GaN layer is epitaxially grown before the growth of the drift layer 13a, and then the drift layer made of n ⁇ -GaN 13a may be grown. Thereby, the epitaxial growth start interface and the pn junction interface can be located at different positions.
  • the laminated body obtained by epitaxial growth can be used by freely combining the number of layers, thickness, composition, etc., as long as nitride semiconductors are laminated.
  • Additional remark 3 The vertical transistor of Additional remark 1 or 2 characterized by the band gap of the said conductive oxide film being 2.8 eV or more and 4.0 eV or less.
  • Supplementary note 4 Any one of Supplementary notes 1 to 3, wherein the conductive oxide film is any one of ITO, ZnO, TiO 2 , SnO 2 , CdO, or a metal impurity added thereto.
  • the vertical transistor as described.
  • the back surface side trench which reaches the said conductive oxide film from the back surface is formed in a part of said conductive semiconductor substrate,
  • the said drain electrode or the said collector electrode is a back surface of the said conductive semiconductor substrate.
  • the laminated body which consists of the said nitride-type semiconductor was formed on the said drift layer formed on the said nitride-type semiconductor thin film, the barrier layer formed on the said drift layer, and the said barrier layer A channel layer; and an electron supply layer heterojunctioned on the channel layer, wherein the gate electrode is formed on the stacked body so as to be opposed to the source electrode with a gap, and the gate The electrode extends to the side where the source electrode is not opposed to the electrode, at least from the substantial surface of the channel layer to a region closer to the nitride-based semiconductor thin film side than the barrier layer.
  • the vertical transistor according to any one of appendices 1 to 6, further comprising an electron conduction region.
  • Appendix 11 The nitride semiconductor thin film according to any one of appendices 1 to 10, wherein the impurity concentration is 1 ⁇ 10 18 cm ⁇ 3 or more and 5 ⁇ 10 20 cm ⁇ 3 or less. Vertical transistor.
  • a conductive oxide film is formed on a conductive semiconductor substrate, a nitride semiconductor thin film is formed on the conductive oxide film, and a nitride semiconductor is formed on the nitride semiconductor thin film.
  • a method of manufacturing a vertical transistor comprising: epitaxially growing a laminate comprising: forming a source electrode or an emitter electrode on a surface of the laminate; and forming a drain electrode or a collector electrode on a back surface of the conductive semiconductor substrate.
  • the nitride semiconductor thin film is obtained by bonding a nitride semiconductor bulk crystal on the conductive oxide film and dividing the nitride semiconductor bulk crystal in the thickness direction.
  • Appendix 14 A semiconductor device including a vertical transistor, the semiconductor device including the vertical transistor according to any one of Appendixes 1 to 11 as the vertical transistor.
  • the vertical transistor using the nitride semiconductor according to the present invention has a structure that can realize low on-resistance at low cost and reduce power consumption. Utilizing these advantages, it can be applied to a transistor used in a power control device such as a PC power supply or an automobile power steering.

Abstract

Disclosed are a vertical transistor, the on-resistance of which can be effectively reduced, and a manufacturing method therefor. Said vertical transistor is formed on the surface of a conductive semiconductor substrate (50) and comprises a conductive oxide film (11) having a resistivity no greater than 3 × 10−4 Ωcm and an n+ or p+ nitride semiconductor thin film (12) that is bonded to the conductive oxide film and has an impurity concentration of at least 5 × 1017 cm−3. The vertical transistor is also provided with: a layered body (20) that comprises a nitride semiconductor and is epitaxially formed on the nitride semiconductor thin film (12); a source electrode (52) or emitter electrode (55) formed on the surface of the layered body (20); a drain electrode (53) or collector electrode (56) formed on the reverse side of the conductive semiconductor substrate (50); and a gate electrode (51) that controls the magnitude of the current that flows between the source electrode (52) and drain electrode (53) or between the emitter electrode (55) and collector electrode (56).

Description

縦型トランジスタ及びその製造方法、並びに半導体装置Vertical transistor, method for manufacturing the same, and semiconductor device
　本発明は、縦型トランジスタ、及びその製造方法、並びに半導体装置に関する。より詳細には、窒化物系半導体を用いた縦型トランジスタ、及びその製造方法に関する。また、前記縦型トランジスタを搭載した半導体装置に関する。 The present invention relates to a vertical transistor, a manufacturing method thereof, and a semiconductor device. More specifically, the present invention relates to a vertical transistor using a nitride-based semiconductor and a manufacturing method thereof. The present invention also relates to a semiconductor device on which the vertical transistor is mounted.
　ＧａＮ、ＡｌＧａＮ、ＩｎＧａＮ、ＩｎＡｌＮ、ＩｎＡｌＧａＮなどの窒化物系半導体は、高い絶縁破壊強度、高い熱伝導率、高い電子飽和速度を有しているという特長を有する。このため、窒化物系半導体は、高周波デバイスやスイッチング素子などの電力制御用パワーデバイスの作製に利用する半導体材料として有望視されている。近年においては、窒化物系半導体材料を用いた電界効果トランジスタの実用化開発が盛んに行われている。 Nitride-based semiconductors such as GaN, AlGaN, InGaN, InAlN, and InAlGaN have the characteristics of having high dielectric breakdown strength, high thermal conductivity, and high electron saturation speed. For this reason, nitride-based semiconductors are promising as semiconductor materials for use in the production of power devices for power control such as high-frequency devices and switching elements. In recent years, field-effect transistors using nitride-based semiconductor materials have been actively developed and developed.
　窒化物系半導体の高周波デバイス、電力制御用パワーデバイスへの応用においては、サファイア、シリコンカーバイド（ＳｉＣ）、シリコン（Ｓｉ）などの安価な異種基板上に、窒化物半導体をエピタキシャル成長させ、デバイスを作製するのが一般的となっている。製造コストが極めて高いＧａＮ基板を用いる場合に比して、製造コストを抑えることができるというメリットを有する。 In the application of nitride-based semiconductors to high-frequency devices and power devices for power control, nitride semiconductors are epitaxially grown on inexpensive dissimilar substrates such as sapphire, silicon carbide (SiC), and silicon (Si) to produce devices. It has become common to do. Compared to the case of using a GaN substrate with extremely high manufacturing cost, the manufacturing cost can be reduced.
　窒化物系半導体を用いたパワーデバイス開発においては、エピタキシャル成長したＡｌＧａＮ／ＧａＮヘテロ接合界面に、分極により蓄積される２次元電子ガス（２ＤＥＧ：2 Dimensional Electron Gas）をキャリアとして利用する横型トランジスタの開発が先行している。しかしながら、横型トランジスタでは、（１）ソース電極とドレイン電極の両方をウェハ表面に形成しなければならない点、（２）高耐圧を得るための長いドリフト領域を表面に沿って形成しなければならない点などから、デバイス面積が大きくなりやすい。従って、単位面積当たりのオン抵抗を低減するという観点からは、ドレイン電極を裏面に形成し、ドリフト領域を基板の厚み方向に形成する縦型トランジスタの開発が望まれている。 In the development of power devices using nitride-based semiconductors, lateral transistors using two-dimensional electron gas (2DEG: 2 Dimensional Electron Gas) accumulated by polarization at the epitaxially grown AlGaN / GaN heterojunction interface have been developed. It is ahead. However, in the lateral transistor, (1) both the source electrode and the drain electrode must be formed on the wafer surface, and (2) a long drift region for obtaining a high breakdown voltage must be formed along the surface. As a result, the device area tends to increase. Therefore, from the viewpoint of reducing the on-resistance per unit area, it is desired to develop a vertical transistor in which the drain electrode is formed on the back surface and the drift region is formed in the thickness direction of the substrate.
　ここで、サファイア、シリコンカーバイド（ＳｉＣ）、シリコン（Ｓｉ）などの基板上に窒化物系半導体をエピタキシャル成長したウェハを用いて縦型トランジスタを製造する場合を考える。これらの基板上に、高品質のエピタキシャル層を得るためには、通常、基板上にＡｌＮ層を含むバッファ層を成長させることが必要であることが知られている。このバッファ層上にＧａＮ、ＡｌＧａＮなどの窒化物系半導体エピタキシャル層を成長させる。そして、このウェハの表面にソース電極を、基板裏面にドレイン電極を形成することにより、縦型トランジスタが製造される。 Here, consider a case where a vertical transistor is manufactured using a wafer obtained by epitaxially growing a nitride-based semiconductor on a substrate such as sapphire, silicon carbide (SiC), or silicon (Si). In order to obtain a high-quality epitaxial layer on these substrates, it is generally known that it is necessary to grow a buffer layer including an AlN layer on the substrate. A nitride semiconductor epitaxial layer such as GaN or AlGaN is grown on the buffer layer. A vertical transistor is manufactured by forming a source electrode on the front surface of the wafer and a drain electrode on the back surface of the substrate.
　しかしながら、上記構成の縦型トランジスタは、基板と窒化物系半導体エピタキシャル層との間にあるバンドギャップの大きいＡｌＮ層が障壁となる。換言すると、基板と窒化物系半導体エピタキシャル層との間に大きな抵抗が存在することになる。その結果、トランジスタのオン抵抗を低減することが困難であった。 However, in the vertical transistor having the above structure, an AlN layer having a large band gap between the substrate and the nitride semiconductor epitaxial layer serves as a barrier. In other words, a large resistance exists between the substrate and the nitride semiconductor epitaxial layer. As a result, it has been difficult to reduce the on-resistance of the transistor.
　この問題を解決する手段として、特許文献１には、異種基板にＧａＮ薄膜を貼り合わせて製造した縦型トランジスタが開示されている。図７に、特許文献１に開示されているＧａＮ系の縦型トランジスタの模式的な断面図を示す。特許文献１に記載のＧａＮ系の縦型トランジスタは、基板として、導電性のＳｉ基板（異種基板）１５０Ａ上に、導電性（キャリア濃度：４×１０１８ｃｍ－３、比抵抗：０．０１Ωｃｍ）の単結晶ＧａＮ薄膜１５０Ｂが貼り合せられたＧａＮ薄膜貼り合わせ基板１５０が用いられている。 As means for solving this problem, Patent Document 1 discloses a vertical transistor manufactured by bonding a GaN thin film to a different substrate. FIG. 7 is a schematic cross-sectional view of a GaN-based vertical transistor disclosed in Patent Document 1. A GaN-based vertical transistor described in Patent Document 1 has a conductive (carrier concentration: 4 × 10 18 cm −3) and specific resistance: 0.01 Ωcm on a conductive Si substrate (heterogeneous substrate) 150A as a substrate. GaN thin film bonded substrate 150 to which single crystal GaN thin film 150B is bonded is used.
　ＧａＮ薄膜貼り合わせ基板１５０上には、ＧａＮ系半導体層１２０として、ＭＯＣＶＤ（Metal Organic Chemical Vapor Deposition）法で形成された厚さ１０μｍのｎ－型ＧａＮ層１１３（電子濃度：１×１０１６ｃｍ－３）が形成され、ｎ－型ＧａＮ層１１３の一部領域には、Ｍｇイオンを注入したｐ型層１１４が形成され、ｐ型層１１４の一部領域には、Ｓｉイオンを注入したｎ＋型層１１５が形成されている。 On the GaN thin film bonded substrate 150, a 10 μm thick n − -type GaN layer 113 (electron concentration: 1 × 10 16 cm − ) formed as a GaN-based semiconductor layer 120 by MOCVD (Metal Organic Chemical Vapor Deposition) method. 3 ), a p-type layer 114 into which Mg ions are implanted is formed in a partial region of the n − -type GaN layer 113, and n + into which a partial region of the p-type layer 114 is implanted with Si ions. A mold layer 115 is formed.
　ＧａＮ系半導体層１２０上にはｐ－ＣＶＤ（Chemical Vapor Deposition）（プラズマ化学気相堆積）法で形成された厚さ５０ｎｍのＳｉＯ２からなる絶縁膜１１６が形成され、絶縁膜１１６を一部開口した領域にＴｉ／Ａｌ／Ｔｉ／Ａｕからなるソース電極１５２が形成されている。また、絶縁膜１１６上の一部にはＡｌからなるゲート電極１５１が形成され、ＭＩＳ（金属－絶縁体－半導体）構造を構成している。導電性Ｓｉ基板（異種基板）１５０Ａ裏面には、Ｔｉ／Ａｌ／Ｔｉ／Ａｕからなるドレイン電極１５３が形成されている。 An insulating film 116 made of SiO 2 having a thickness of 50 nm formed by p-CVD (Chemical Vapor Deposition) is formed on the GaN-based semiconductor layer 120, and the insulating film 116 is partially opened. A source electrode 152 made of Ti / Al / Ti / Au is formed in the region. In addition, a gate electrode 151 made of Al is formed on a part of the insulating film 116 to form a MIS (metal-insulator-semiconductor) structure. A drain electrode 153 made of Ti / Al / Ti / Au is formed on the back surface of the conductive Si substrate (different substrate) 150A.
　特許文献１によれば、Ｓｉ基板（異種基板）１５０ＡとＧａＮ薄膜１５０Ｂとの間には、バンドギャップの大きいＡｌＮ層が無いため、上述のＳｉ基板上に窒化物系半導体層をエピタキシャル成長する手法に比べて、オン抵抗を低減することができる。 According to Patent Document 1, since there is no AlN layer having a large band gap between the Si substrate (heterogeneous substrate) 150A and the GaN thin film 150B, a method of epitaxially growing a nitride-based semiconductor layer on the Si substrate described above is used. In comparison, the on-resistance can be reduced.
特開２００８－１０７６６号公報JP 2008-10766 A
　しかしながら、図７に示す構成の縦型トランジスタでは、導電性のＳｉ基板１５０Ａと、導電性のＧａＮ薄膜１５０Ｂの貼り合わせ界面の抵抗を十分に低くすることが困難であり、縦型トランジスタのオン抵抗の低減効果が十分とは言えなかった。 However, in the vertical transistor having the configuration shown in FIG. 7, it is difficult to sufficiently reduce the resistance at the bonding interface between the conductive Si substrate 150A and the conductive GaN thin film 150B. The reduction effect was not sufficient.
　本発明は、上述した課題に鑑みてなされたものであり、その目的とするところは、オン抵抗を効果的に低減可能な縦型トランジスタ及びその製造方法、並びに半導体装置を提供することである。 The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a vertical transistor capable of effectively reducing on-resistance, a manufacturing method thereof, and a semiconductor device.
　本発明に係る縦型トランジスタは、導電性半導体基板と、前記導電性半導体基板表面に形成され、比抵抗が３×１０－４Ωｃｍ以下の導電性酸化膜と、前記導電性酸化膜上に貼り合せてなる、不純物濃度が５×１０１７ｃｍ－３以上のｎ＋型、又はｐ＋型の窒化物系半導体薄膜と、前記窒化物系半導体薄膜上にエピタキシャル成長された、窒化物系半導体からなる積層体と、前記積層体表面に形成されたソース電極、又はエミッタ電極と、前記導電性半導体基板裏面に形成されたドレイン電極、又はコレクタ電極と、前記ソース電極と前記ドレイン電極との間、若しくは前記エミッタ電極と前記コレクタ電極との間を流れる電流の大きさを制御する機能を有するゲート電極とを備えるものである。 The vertical transistor according to the present invention includes a conductive semiconductor substrate, a conductive oxide film formed on the surface of the conductive semiconductor substrate and having a specific resistance of 3 × 10 −4 Ωcm or less, and is attached on the conductive oxide film. And an n + -type or p + -type nitride semiconductor thin film having an impurity concentration of 5 × 10 17 cm −3 or more, and a nitride semiconductor epitaxially grown on the nitride semiconductor thin film. A stack, a source electrode or emitter electrode formed on the surface of the stack, a drain electrode or collector electrode formed on the back surface of the conductive semiconductor substrate, and between the source electrode and the drain electrode, or And a gate electrode having a function of controlling a magnitude of a current flowing between the emitter electrode and the collector electrode.
　本発明に係る縦型トランジスタの製造方法は、導電性半導体基板上に、導電性酸化膜を形成し、前記導電性酸化膜上に、窒化物系半導体薄膜を形成し、前記窒化物系半導体薄膜の上層に、窒化物系半導体からなる積層体をエピタキシャル成長させ、前記積層体表面にソース電極、又はエミッタ電極を形成し、前記導電性半導体基板裏面にドレイン電極、又はコレクタ電極を形成するものである。 In the method for manufacturing a vertical transistor according to the present invention, a conductive oxide film is formed on a conductive semiconductor substrate, a nitride semiconductor thin film is formed on the conductive oxide film, and the nitride semiconductor thin film is formed. A layered body made of a nitride semiconductor is epitaxially grown on the upper layer, a source electrode or an emitter electrode is formed on the surface of the layered body, and a drain electrode or a collector electrode is formed on the back surface of the conductive semiconductor substrate. .
　本発明によれば、オン抵抗を十分に低減可能な縦型トランジスタ及びその製造方法、並びに半導体装置を提供することができるという優れた効果を有する。 According to the present invention, there is an excellent effect that it is possible to provide a vertical transistor capable of sufficiently reducing on-resistance, a manufacturing method thereof, and a semiconductor device.
実施形態１に係る縦型トランジスタの構成の一例を模式的に示す模式的断面図。FIG. 2 is a schematic cross-sectional view schematically illustrating an example of a configuration of a vertical transistor according to the first embodiment. 実施形態１に係る縦型トランジスタの製造工程断面図。FIG. 4 is a manufacturing process cross-sectional view of the vertical transistor according to the first embodiment. 実施形態１に係る縦型トランジスタの製造工程断面図。FIG. 4 is a manufacturing process cross-sectional view of the vertical transistor according to the first embodiment. 実施形態１に係る縦型トランジスタの製造工程断面図。FIG. 4 is a manufacturing process cross-sectional view of the vertical transistor according to the first embodiment. 実施形態１に係る縦型トランジスタの製造工程断面図。FIG. 4 is a manufacturing process cross-sectional view of the vertical transistor according to the first embodiment. 実施形態１に係る縦型トランジスタの製造工程断面図。FIG. 4 is a manufacturing process cross-sectional view of the vertical transistor according to the first embodiment. 実施形態２に係る縦型トランジスタの構成の一例を模式的に示す模式的断面図。FIG. 5 is a schematic cross-sectional view schematically illustrating an example of a configuration of a vertical transistor according to a second embodiment. 実施形態２に係る縦型トランジスタの製造工程断面図。FIG. 10 is a manufacturing process cross-sectional view of a vertical transistor according to the second embodiment. 実施形態２に係る縦型トランジスタの製造工程断面図。FIG. 10 is a manufacturing process cross-sectional view of a vertical transistor according to the second embodiment. 実施形態２に係る縦型トランジスタの製造工程断面図。FIG. 10 is a manufacturing process cross-sectional view of a vertical transistor according to the second embodiment. 実施形態３に係る縦型トランジスタの構成の一例を模式的に示す模式的断面図。FIG. 5 is a schematic cross-sectional view schematically illustrating an example of a configuration of a vertical transistor according to a third embodiment. 実施形態２に係る縦型トランジスタの製造工程断面図。FIG. 10 is a manufacturing process cross-sectional view of a vertical transistor according to the second embodiment. 実施形態２に係る縦型トランジスタの製造工程断面図。FIG. 10 is a manufacturing process cross-sectional view of a vertical transistor according to the second embodiment. 実施形態２に係る縦型トランジスタの製造工程断面図。FIG. 10 is a manufacturing process cross-sectional view of a vertical transistor according to the second embodiment. 特許文献１に記載の縦型トランジスタの模式的断面図。FIG. 10 is a schematic cross-sectional view of a vertical transistor described in Patent Document 1.
　本発明に係る縦型トランジスタは、導電性半導体基板表面に、比抵抗が３×１０－４Ωｃｍ以下の導電性酸化膜が形成されている。そして、導電性酸化膜上には、貼り合わせることにより形成されるｎ＋型、又はｐ＋型の窒化物系半導体薄膜が配設されている。この窒化物系半導体薄膜の不純物濃度は、５×１０１７ｃｍ－３以上とする。また、窒化物系半導体薄膜上には、エピタキシャル成長させた窒化物系半導体からなる積層体が形成されている。縦型トランジスタのソース電極、又はエミッタ電極は、積層体表面に形成されている。一方、ドレイン電極、又はコレクタ電極は、導電性半導体基板の裏面側に形成されている。ゲート電極は、ソース電極とドレイン電極との間、若しくはエミッタ電極とコレクタ電極との間を流れる電流の大きさを制御する機能を有する。 In the vertical transistor according to the present invention, a conductive oxide film having a specific resistance of 3 × 10 −4 Ωcm or less is formed on the surface of the conductive semiconductor substrate. An n + type or p + type nitride-based semiconductor thin film formed by bonding is disposed on the conductive oxide film. The impurity concentration of this nitride-based semiconductor thin film is 5 × 10 17 cm −3 or more. Further, on the nitride semiconductor thin film, a laminated body made of the nitride semiconductor epitaxially grown is formed. The source electrode or emitter electrode of the vertical transistor is formed on the surface of the stacked body. On the other hand, the drain electrode or the collector electrode is formed on the back side of the conductive semiconductor substrate. The gate electrode has a function of controlling the magnitude of a current flowing between the source electrode and the drain electrode or between the emitter electrode and the collector electrode.
　本発明者らは、オン抵抗を効果的に低減可能な縦型トランジスタ及びその製造方法を得るべく、鋭意検討を重ねた結果、上記構成において、本発明の目的を達成し得ることを突き止め、本発明を完成するに至った。以下、本発明を適用した実施形態の一例について、具体例を示して説明する。なお、下記の具体例は、本発明の最良の実施形態の一例であるが、本発明は、これらの実施形態に限定されるものではない。また、以降の図における各部材のサイズや比率は、説明の便宜上のものであり、実際のものとは異なる。 As a result of intensive studies to obtain a vertical transistor capable of effectively reducing on-resistance and a method for manufacturing the same, the present inventors have found that the object of the present invention can be achieved in the above-described configuration. The invention has been completed. Hereinafter, an example of an embodiment to which the present invention is applied will be described with a specific example. The following specific examples are examples of the best embodiment of the present invention, but the present invention is not limited to these embodiments. Moreover, the size and ratio of each member in the following drawings are for convenience of explanation, and are different from actual ones.
［実施形態１］
　図１は、本実施形態１に係る縦型トランジスタの構造を模式的に示す断面図である。本実施形態１に係る縦型トランジスタ１は、導電性半導体基板５０、ゲート電極５１、ソース電極５２、ドレイン電極５３、導電性酸化膜１１、窒化物系半導体薄膜１２、窒化物系半導体からなる積層体２０、絶縁膜１６等を備える。 [Embodiment 1]
FIG. 1 is a cross-sectional view schematically showing the structure of the vertical transistor according to the first embodiment. The vertical transistor 1 according to the first embodiment includes a conductive semiconductor substrate 50, a gate electrode 51, a source electrode 52, a drain electrode 53, a conductive oxide film 11, a nitride semiconductor thin film 12, and a stacked semiconductor film. The body 20 and the insulating film 16 are provided.
　導電性半導体基板５０は、本発明の趣旨を逸脱しない範囲において、特に限定されずに適用することができる。製造コストを低減する観点からは、６インチ以上の大口径基板を安価に入手できる材料を選択することが好ましい。このような導電性半導体基板材料の好適な例として、Ｓｉ、ポリＳｉ、ポリＳｉＣ等を挙げることができる。これらを適用することにより、低オン抵抗の縦型トランジスタを低コストで製造することができる。本実施形態１においては、比抵抗が０．０２Ωｃｍのｎ型Ｓｉを適用した。 The conductive semiconductor substrate 50 can be applied without particular limitation as long as it does not depart from the spirit of the present invention. From the viewpoint of reducing the manufacturing cost, it is preferable to select a material that can obtain a large-diameter substrate of 6 inches or more at a low cost. Suitable examples of such a conductive semiconductor substrate material include Si, poly-Si, poly-SiC and the like. By applying these, a low on-resistance vertical transistor can be manufactured at low cost. In the first embodiment, n-type Si having a specific resistance of 0.02 Ωcm is applied.
　導電性酸化膜１１は、導電性半導体基板５０上に形成されている。導電性酸化膜１１の比抵抗は、少なくとも３×１０－４Ωｃｍ以下とする。３×１０－４Ωｃｍ以下とすることにより、従来のように導電性半導体基板５０に直接窒化物系半導体薄膜１２を貼り合せた場合に比べ、オン抵抗を低くできるという効果が得られる。より好ましい範囲は、２×１０－４Ωｃｍ以下であり、特に好ましい範囲は、１×１０－４Ωｃｍ以下である。導電性酸化膜１１の比抵抗の下限値は、特に限定されないが、長期通電による強度や抵抗の劣化がない良質な膜質を実現するため、２×１０－６Ωｃｍ以上とすることが好ましい。導電性酸化膜１１の材料としては、本発明の趣旨を逸脱しない範囲において、特に限定されずに適用することができる。安定した強固な貼り合わせ基板を得る観点からは、導電性酸化膜１１の融点が１３００℃以上であることが好ましい。このように融点の高い材料を用いることにより、有機金属気相成長法（ＭＯＶＰＥ：Metal Organic Vapor Phase Epitaxy）による窒化物系半導体の結晶成長など、１０００℃程度の高温を要する製造工程に対しても、安定した強固な貼り合わせ基板を得ることができる。導電性酸化膜１１の融点の上限は、特に限定されない。本実施形態１においては、導電性酸化膜１１として、比抵抗が２×１０－４ΩｃｍのＡｌ添加ＺｎＯ（ＺＡＯ）を用いた。 The conductive oxide film 11 is formed on the conductive semiconductor substrate 50. The specific resistance of the conductive oxide film 11 is at least 3 × 10 −4 Ωcm or less. By setting it to 3 × 10 −4 Ωcm or less, it is possible to obtain an effect that the on-resistance can be lowered as compared with the case where the nitride-based semiconductor thin film 12 is directly bonded to the conductive semiconductor substrate 50 as in the prior art. A more preferable range is 2 × 10 −4 Ωcm or less, and a particularly preferable range is 1 × 10 −4 Ωcm or less. The lower limit value of the specific resistance of the conductive oxide film 11 is not particularly limited, but is preferably 2 × 10 −6 Ωcm or more in order to realize a high-quality film quality that does not deteriorate strength or resistance due to long-term conduction. The material of the conductive oxide film 11 can be applied without particular limitation as long as it does not depart from the spirit of the present invention. From the viewpoint of obtaining a stable and strong bonded substrate, the conductive oxide film 11 preferably has a melting point of 1300 ° C. or higher. By using a material having a high melting point in this way, even for manufacturing processes that require high temperatures of about 1000 ° C., such as crystal growth of nitride-based semiconductors by metal organic vapor phase epitaxy (MOVPE). A stable and strong bonded substrate can be obtained. The upper limit of the melting point of the conductive oxide film 11 is not particularly limited. In Embodiment 1, Al-doped ZnO (ZAO) having a specific resistance of 2 × 10 −4 Ωcm is used as the conductive oxide film 11.
　導電性酸化膜１１の膜厚は、特に限定されないが、例えば、５ｎｍ以上、１０００ｎｍ以下とすることができる。より好ましい範囲は、１０ｎｍ以上、５００ｎｍ以下であり、特に好ましい範囲は、２０ｎｍ以上、３００ｎｍ以下である。 The film thickness of the conductive oxide film 11 is not particularly limited, but can be, for example, 5 nm or more and 1000 nm or less. A more preferable range is 10 nm or more and 500 nm or less, and a particularly preferable range is 20 nm or more and 300 nm or less.
　窒化物系半導体薄膜１２は、窒化物系半導体バルク結晶を導電性酸化膜１１上に貼り合せ、これを厚み方向に分割することにより形成することができる。窒化物系半導体薄膜１２の不純物濃度は、５×１０１７ｃｍ－３以上とする。５×１０１７ｃｍ－３以上とすることにより、窒化物系半導体薄膜１２と導電性酸化膜１１とが十分低い抵抗で接続できるという効果が得られる。より好ましい範囲は、１×１０１８ｃｍ－３以上である。また、窒化物系半導体薄膜１２の不純物濃度の上限値は、５×１０２０ｃｍ－３以下とすることが好ましい。５×１０２０ｃｍ－３を超えると、窒化物系半導体薄膜１２上に形成する積層体２０の結晶性が低下し、デバイスの信頼性を損なう恐れがある。不純物導入により、Ｐ＋型、若しくはｎ＋型となるようにする。本実施形態１においては、不純物濃度が５×１０１８ｃｍ－３で、膜厚が０．１μｍのｎ＋-ＧａＮを形成した。 The nitride-based semiconductor thin film 12 can be formed by bonding a nitride-based semiconductor bulk crystal on the conductive oxide film 11 and dividing it in the thickness direction. The impurity concentration of the nitride-based semiconductor thin film 12 is 5 × 10 17 cm −3 or more. By setting it to 5 × 10 17 cm −3 or more, it is possible to obtain an effect that the nitride-based semiconductor thin film 12 and the conductive oxide film 11 can be connected with a sufficiently low resistance. A more preferable range is 1 × 10 18 cm −3 or more. The upper limit of the impurity concentration of the nitride-based semiconductor thin film 12 is preferably 5 × 10 20 cm −3 or less. If it exceeds 5 × 10 20 cm −3 , the crystallinity of the laminate 20 formed on the nitride-based semiconductor thin film 12 is lowered, and the reliability of the device may be impaired. By introducing impurities, it becomes a P + type or an n + type. In Embodiment 1, n + -GaN having an impurity concentration of 5 × 10 18 cm −3 and a film thickness of 0.1 μm is formed.
　窒化物系半導体からなる積層体２０は、窒化物系半導体薄膜１２上に形成されている。積層体２０は、エピタキシャル成長により得られる。積層体２０は、ドリフト層１３、チャネル層１４、コンタクト層１５が、窒化物系半導体薄膜１２側からこの順に形成されている。実施形態１においては、ドリフト層１３として、不純物濃度が１×１０１６ｃｍ－３で膜厚が３μｍのｎ－-ＧａＮを、チャネル層１４として、不純物濃度が１×１０１８ｃｍ－３で膜厚が０．６μｍのｐ‐ＧａＮを、コンタクト層１５として、不純物濃度が３×１０１８ｃｍ－３で膜厚が０．５μｍのｎ＋‐ＧａＮを適用した。 The stacked body 20 made of a nitride-based semiconductor is formed on the nitride-based semiconductor thin film 12. The stacked body 20 is obtained by epitaxial growth. In the stacked body 20, the drift layer 13, the channel layer 14, and the contact layer 15 are formed in this order from the nitride-based semiconductor thin film 12 side. In the first embodiment, n − -GaN having an impurity concentration of 1 × 10 16 cm −3 and a film thickness of 3 μm is used as the drift layer 13, and a film having an impurity concentration of 1 × 10 18 cm −3 is used as the channel layer 14. P-GaN having a thickness of 0.6 μm was used as the contact layer 15 and n + -GaN having an impurity concentration of 3 × 10 18 cm −3 and a thickness of 0.5 μm was applied.
　ソース電極５２は、コンタクト層１５の表面に、ドレイン電極５３は、導電性半導体基板５０の裏面に形成されている。ソース電極５２及びドレイン電極５３ともに、実施形態１においては、Ｔｉ／Ａｌ（Ｔｉが下層側、Ａｌが上層側（以下、同様とする））からなる電極を適用した。 The source electrode 52 is formed on the surface of the contact layer 15, and the drain electrode 53 is formed on the back surface of the conductive semiconductor substrate 50. For the source electrode 52 and the drain electrode 53, in the first embodiment, an electrode made of Ti / Al (Ti is a lower layer side and Al is an upper layer side (hereinafter the same)) is applied.
　積層体２０の一部には、その表面から、ドリフト層１３に達する上面側トレンチ２１が形成されており、この上面側トレンチ２１の内壁及び底面、上面側トレンチ２１の内壁から延在されるコンタクト層１５の表面の一部に亘って、ＳｉＯ２からなるゲート絶縁膜１６が被覆されている。さらには、上面側トレンチ２１の内壁及び底面には、Ｎｉ／Ａｕからなるゲート電極５１が形成されている。 A part of the stacked body 20 is formed with an upper surface side trench 21 reaching the drift layer 13 from the surface thereof, and contacts extending from the inner and bottom surfaces of the upper surface side trench 21 and the inner wall of the upper surface side trench 21. A part of the surface of the layer 15 is covered with a gate insulating film 16 made of SiO 2 . Furthermore, a gate electrode 51 made of Ni / Au is formed on the inner wall and bottom surface of the upper surface side trench 21.
　本実施形態１は、上面側トレンチ２１の側面に接触するチャネル層１４が反転領域となることによってチャネルが形成される、いわゆるトレンチゲート型の電界効果トランジスタとなっている。 The first embodiment is a so-called trench gate type field effect transistor in which a channel is formed by the channel layer 14 in contact with the side surface of the upper side trench 21 being an inversion region.
　次に、本実施形態１に係る縦型トランジスタの製造方法について説明する。まず、導電性半導体基板５０上に導電性酸化膜１１を形成し、導電性酸化膜１１上に窒化物系半導体薄膜１２を形成する。そして、窒化物系半導体薄膜１２の上層に、窒化物系半導体からなる積層体２０をエピタキシャル成長させ、積層体２０表面にソース電極５２を形成する。そして、導電性半導体基板５０裏面にドレイン電極５３を形成する。以下、本実施形態１に係る縦型トランジスタの製造方法の具体的な一例を、図２Ａ～図２Ｅを参照して説明する。図２Ａ～図２Ｅは、本実施形態１に係る縦型トランジスタの製造工程を模式的に示す断面図である。 Next, a method for manufacturing the vertical transistor according to the first embodiment will be described. First, the conductive oxide film 11 is formed on the conductive semiconductor substrate 50, and the nitride-based semiconductor thin film 12 is formed on the conductive oxide film 11. Then, the stacked body 20 made of the nitride-based semiconductor is epitaxially grown on the nitride-based semiconductor thin film 12 to form the source electrode 52 on the surface of the stacked body 20. Then, the drain electrode 53 is formed on the back surface of the conductive semiconductor substrate 50. Hereinafter, a specific example of the method for manufacturing the vertical transistor according to the first embodiment will be described with reference to FIGS. 2A to 2E. 2A to 2E are cross-sectional views schematically showing the manufacturing process of the vertical transistor according to the first embodiment.
　はじめに、導電性半導体基板５０との貼り合わせ面が鏡面研磨された窒化物系半導体バルク結晶３０を用意する。本実施形態１においては、窒化物系半導体バルク結晶３０として、ＧａＮバルク結晶を用意した。そして、貼り合わせ面（以下、「Ｎ面（窒素原子面）」とも称する）から、例えば０．１μｍの深さに水素イオンを注入する（図２Ａ）。なお、水素イオンに変えて、ヘリウムイオンや窒素イオンなどを用いてもよい。また、窒化物系半導体バルク結晶の鏡面研磨は、必ずしも必須ではない。但し、窒化物系半導体バルク結晶３０と導電性酸化膜１１の貼り合わせに問題が生じないレベルの表面粗さとなっている必要がある。 First, a nitride-based semiconductor bulk crystal 30 in which the bonding surface with the conductive semiconductor substrate 50 is mirror-polished is prepared. In the first embodiment, a GaN bulk crystal is prepared as the nitride-based semiconductor bulk crystal 30. Then, hydrogen ions are implanted, for example, to a depth of 0.1 μm from the bonding surface (hereinafter also referred to as “N surface (nitrogen atom surface)”) (FIG. 2A). Note that helium ions or nitrogen ions may be used instead of hydrogen ions. Further, mirror polishing of a nitride semiconductor bulk crystal is not always essential. However, the surface roughness should be at a level that does not cause a problem in bonding the nitride semiconductor bulk crystal 30 and the conductive oxide film 11.
　次に、導電性半導体基板５０上に、スパッタ法により、Ａｌ添加ＺｎＯ（ＺＡＯ）からなる導電性酸化膜１１を形成する（図２Ｂ）。次いで、窒化物系半導体バルク結晶３０のＮ面と、導電性酸化膜１１表面とを、フュージョンボンディング法等により貼り合せる。その後、４５０℃の熱処理を行うことによって、水素イオン注入面で窒化物系半導体バルク結晶３０を厚み方向で分割する。これにより、窒化物系半導体薄膜１２が形成される（図２Ｃ）。窒化物系半導体バルク結晶３０の分割は、導電性半導体基板５０側から、例えば０．１μｍの深さで剥離する。 Next, a conductive oxide film 11 made of Al-doped ZnO (ZAO) is formed on the conductive semiconductor substrate 50 by sputtering (FIG. 2B). Next, the N surface of the nitride-based semiconductor bulk crystal 30 and the surface of the conductive oxide film 11 are bonded together by a fusion bonding method or the like. Thereafter, the nitride semiconductor bulk crystal 30 is divided in the thickness direction at the hydrogen ion implantation surface by performing a heat treatment at 450 ° C. Thereby, the nitride-based semiconductor thin film 12 is formed (FIG. 2C). The nitride semiconductor bulk crystal 30 is separated from the conductive semiconductor substrate 50 side at a depth of, for example, 0.1 μm.
　なお、窒化物系半導体バルク結晶３０と導電性半導体基板５０の貼り合わせは、フュージョンボンディング法に限定されるものではなく、公知の方法を制限なく適用することができる。例えば、Ｎ面をプラズマに曝すことによりその表面を活性化させた後に貼り合わせる、表面活性化法により貼り合わせてもよい。また、窒化物系半導体薄膜１２を得る方法としては、上述した窒化物系半導体バルク結晶を用いる方法に限定されるものではなく、本発明の趣旨を逸脱しない範囲において種々の方法を採用することができる。例えば、異種基板上に、窒化物系半導体をエピタキシャル成長させ、成長面側を導電性酸化膜上に貼り合わせた後に、異種基板を剥離することにより窒化物系半導体薄膜を得るようにしてもよい。 The bonding of the nitride-based semiconductor bulk crystal 30 and the conductive semiconductor substrate 50 is not limited to the fusion bonding method, and a known method can be applied without limitation. For example, the N surface may be bonded by a surface activation method in which the surface is activated by exposing it to plasma and then bonded. The method for obtaining the nitride-based semiconductor thin film 12 is not limited to the method using the nitride-based semiconductor bulk crystal described above, and various methods can be adopted without departing from the spirit of the present invention. it can. For example, a nitride-based semiconductor thin film may be obtained by epitaxially growing a nitride-based semiconductor on a heterogeneous substrate, and bonding the growth surface side onto a conductive oxide film, and then peeling the heterogeneous substrate.
　続いて、窒化物系半導体薄膜１２上に、有機金属気相成長法により、不純物濃度が１×１０１６ｃｍ－３で膜厚が３μｍのｎ－-ＧａＮからなるドリフト層１３と、不純物濃度が１×１０１８ｃｍ－３で膜厚が０．６μｍのｐ‐ＧａＮからなるチャネル層１４と、不純物濃度が３×１０１８ｃｍ－３で膜厚が０．５μｍのｎ＋‐ＧａＮからなるコンタクト層１５とを、この順に成長させる（図２Ｄ）。 Subsequently, the drift layer 13 made of n − -GaN having an impurity concentration of 1 × 10 16 cm −3 and a film thickness of 3 μm is formed on the nitride semiconductor thin film 12 by metal organic vapor phase epitaxy, and the impurity concentration is 1 × 10 18 cm −3 channel layer 14 made of p-GaN having a film thickness of 0.6 μm, and n + -GaN contact layer having an impurity concentration of 3 × 10 18 cm −3 and a film thickness of 0.5 μm. Layer 15 is grown in this order (FIG. 2D).
　その後、ソース電極５２を形成する。具体的には、ソース電極５２が形成される領域に開口パターンを形成したフォトレジスト・マスクを利用し、蒸着・リフトオフ法を用いて、Ｔｉ／Ａｌ（３０ｎｍ／１８０ｎｍ）電極パターンを形成する。そして、７００℃、６０秒のＲＴＡ（Rapid Thermal Anneal）を行うことにより、ソース電極５２を得る。 Thereafter, the source electrode 52 is formed. Specifically, a Ti / Al (30 nm / 180 nm) electrode pattern is formed by vapor deposition / lift-off using a photoresist mask in which an opening pattern is formed in a region where the source electrode 52 is formed. Then, the source electrode 52 is obtained by performing RTA (Rapid Thermal Thermal) at 700 ° C. for 60 seconds.
　次に、コンタクト層１５の表面からドリフト層１３に達する上面側トレンチ２１を形成する。具体的には、所定の領域に開口パターンを形成したフォトレジスト・マスクを利用して、ＩＣＰ（Inductively Coupled Plasma）ドライエッチ法により形成する。そして、上面側トレンチ２１内壁のダメージを除去するため、ＮＨ４ＯＨ（アンモニア水）によるウェットエッチング処理を行う。その後、ＥＣＲ（Electron Cyclotron Resonance：電子サイクロトロン共鳴）スパッタ法を用いて、上面側トレンチ２１の内壁面と縁部を覆うゲート絶縁膜１６を形成する（図２Ｅ）。 Next, an upper surface side trench 21 reaching the drift layer 13 from the surface of the contact layer 15 is formed. Specifically, it is formed by an ICP (Inductively Coupled Plasma) dry etching method using a photoresist mask in which an opening pattern is formed in a predetermined region. Then, in order to remove damage on the inner wall of the upper surface side trench 21, a wet etching process using NH 4 OH (ammonia water) is performed. Thereafter, the gate insulating film 16 that covers the inner wall surface and the edge of the upper-side trench 21 is formed by using an ECR (Electron Cyclotron Resonance) sputtering method (FIG. 2E).
　次いで、ゲート電極５１を形成する。具体的には、ゲート電極５１が形成される領域に開口パターンを形成したフォトレジスト・マスクを利用し、蒸着・リフトオフ法を用いて、Ｎｉ／Ａｕ（３０ｎｍ／３００ｎｍ）電極パターンを所定位置に形成する。 Next, the gate electrode 51 is formed. Specifically, a Ni / Au (30 nm / 300 nm) electrode pattern is formed at a predetermined position by using a vapor deposition / lift-off method using a photoresist mask in which an opening pattern is formed in a region where the gate electrode 51 is formed. To do.
　続いて、ドレイン電極５３を形成する。具体的には、まず、導電性半導体基板５０の裏面を研磨して薄層化する。その後、真空蒸着法を用いて、導電性半導体基板５０裏面にＴｉ／Ａｌからなるドレイン電極５３を形成する。以上の工程等を経て、図１に示す構成の窒化物系半導体からなる縦型トランジスタが製造される。 Subsequently, the drain electrode 53 is formed. Specifically, first, the back surface of the conductive semiconductor substrate 50 is polished and thinned. Thereafter, a drain electrode 53 made of Ti / Al is formed on the back surface of the conductive semiconductor substrate 50 using a vacuum deposition method. Through the above steps, a vertical transistor made of a nitride-based semiconductor having the configuration shown in FIG. 1 is manufactured.
　次に、本実施形態１に係る縦型トランジスタが、オン抵抗を十分に低くすることができる理由について説明する。まず、図７（特許文献１）の縦型トランジスタにおいて、オン抵抗を十分に低くすることが困難であった理由について説明する。 Next, the reason why the vertical transistor according to the first embodiment can sufficiently reduce the on-resistance will be described. First, the reason why it is difficult to sufficiently reduce the on-resistance in the vertical transistor of FIG. 7 (Patent Document 1) will be described.
　図７の構成において、貼り合わせ界面での抵抗を十分に低くするのが困難な第１の原因は、Ｓｉのバンドギャップ（１．１ｅＶ）とＧａＮのバンドギャップ（３．４ｅＶ）の差が大きいことにある。このようなバンドギャップの差（２．３ｅＶ）のものを直接貼り合せると、貼り合わせ界面の伝導帯、価電子帯にはそれぞれ１ｅＶ程度の非常に大きなバンド不連続が存在することになる。このバンド不連続が大きなポテンシャル障壁となることにより、Ｓｉ／ＧａＮ界面には大きな抵抗が発生する。すなわち、導電性のＳｉ基板１５０Ａと導電性のＧａＮ薄膜１５０Ｂを貼り合せる構成では、縦型トランジスタのオン抵抗を十分に低くすることが困難となる。 In the configuration of FIG. 7, the first cause of difficulty in sufficiently reducing the resistance at the bonding interface is a large difference between the Si band gap (1.1 eV) and the GaN band gap (3.4 eV). There is. When such a band gap difference (2.3 eV) is directly bonded, a very large band discontinuity of about 1 eV exists in the conduction band and valence band of the bonding interface. When this band discontinuity becomes a large potential barrier, a large resistance is generated at the Si / GaN interface. That is, in the configuration in which the conductive Si substrate 150A and the conductive GaN thin film 150B are bonded together, it is difficult to sufficiently reduce the on-resistance of the vertical transistor.
　この問題を解決する方法として、バンドギャップがＧａＮに近い単結晶ＳｉＣ（バンドギャップ：３．２ｅＶ）を基板として用いる方法が考えられる。しかしながら、単結晶ＳｉＣ基板は、著しく高価である。また、大口径ウェハが存在しない。このため、Ｓｉ基板を用いたデバイス製造に比して、著しくコストが増加してしまう。すなわち、図７に示す構成では、十分にオン抵抗を低減した縦型トランジスタを低コストに製造することは困難である。 As a method for solving this problem, a method using a single crystal SiC (band gap: 3.2 eV) having a band gap close to that of GaN as a substrate can be considered. However, single crystal SiC substrates are significantly expensive. Also, there is no large diameter wafer. For this reason, compared with device manufacture using a Si substrate, cost will increase remarkably. That is, with the configuration shown in FIG. 7, it is difficult to manufacture a vertical transistor with a sufficiently reduced on-resistance at a low cost.
　貼り合わせ界面での抵抗を十分に低くするのが困難な第２の原因は、Ｓｉ基板１５０Ａ及びＧａＮ薄膜１５０Ｂという半導体材料同士を貼り合わせていることに起因する。貼り合せ基板を用いた半導体素子の場合、貼り合わせの界面には多量の未結合手（ダングリングボンド）が存在する。そして、この未結合手がキャリアトラップとして機能する。このため、貼り合わせ界面には、界面のキャリアトラップに起因する界面抵抗の発生が避けられない。この界面抵抗を十分に低減するには、貼り合せる材料の一方を、比抵抗の低い導体（例えば３×１０－４Ωｃｍ以下）で構成することが有効である。 The second cause that it is difficult to sufficiently reduce the resistance at the bonding interface is due to bonding of semiconductor materials such as the Si substrate 150A and the GaN thin film 150B. In the case of a semiconductor element using a bonded substrate, a large amount of dangling bonds (dangling bonds) exist at the bonding interface. And this unbonded hand functions as a carrier trap. For this reason, the occurrence of interface resistance due to carrier traps at the interface is inevitable at the bonding interface. In order to sufficiently reduce the interface resistance, it is effective to configure one of the materials to be bonded with a conductor having a low specific resistance (for example, 3 × 10 −4 Ωcm or less).
　しかしながら、図７に示した縦型トランジスタでは、貼り合せている材料は、ＳｉとＧａＮであり、いずれも半導体である。半導体材料は、不純物を添加することで導電性が得られるが、良好な結晶性を保った状態で得られる比抵抗はせいぜい１×１０－２Ωｃｍ程度である。すなわち、貼り合わされる層の両方が比抵抗の高い材料で構成されていることになり、界面抵抗を十分に低減することが困難となる。この問題は、Ｓｉ基板の代わりに単結晶ＳｉＣ基板など、他の半導体基板を用いた場合においても解消することはできなかった。結果として、図７に示す構成では、十分にオン抵抗を低減した縦型トランジスタを製造することは困難であった。 However, in the vertical transistor shown in FIG. 7, the materials to be bonded are Si and GaN, both of which are semiconductors. The semiconductor material can be made conductive by adding impurities, but the specific resistance obtained in a state of maintaining good crystallinity is at most about 1 × 10 −2 Ωcm. That is, both layers to be bonded are made of a material having a high specific resistance, and it is difficult to sufficiently reduce the interface resistance. This problem cannot be solved even when another semiconductor substrate such as a single crystal SiC substrate is used instead of the Si substrate. As a result, with the configuration shown in FIG. 7, it was difficult to manufacture a vertical transistor with sufficiently reduced on-resistance.
　一方、本実施形態１においては、導電性半導体基板５０と窒化物系半導体薄膜１２との間に、比抵抗が３×１０－４Ωｃｍ以下（具体例においては、２×１０－４Ωｃｍ）の導電性酸化膜１１を配設している。これにより、導電性酸化膜１１と導電性半導体基板５０との界面に大きな界面抵抗が生じることなく、接合を形成することができる。同様の理由により、導電性酸化膜１１と窒化物系半導体薄膜１２との界面に大きな界面抵抗を生じることなく、接合を形成することができる。 On the other hand, in the first embodiment, the specific resistance is 3 × 10 −4 Ωcm or less (in the specific example, 2 × 10 −4 Ωcm) between the conductive semiconductor substrate 50 and the nitride-based semiconductor thin film 12. A conductive oxide film 11 is provided. Thereby, a junction can be formed without generating a large interface resistance at the interface between the conductive oxide film 11 and the conductive semiconductor substrate 50. For the same reason, a junction can be formed without generating a large interface resistance at the interface between the conductive oxide film 11 and the nitride-based semiconductor thin film 12.
　しかも、本実施形態１においては、導電性酸化膜１１として、Ａｌ添加ＺｎＯ（ＺＡＯ）というバンドギャップがＧａＮに近い（ＺｎＯ：３．３ｅＶ、ＧａＮ：３．４ｅＶ）材料を用いているため、導電性酸化膜１１と窒化物系半導体薄膜１２との界面の界面抵抗を特に低くすることができる。また、導電性半導体基板として、Ｓｉ基板を用いているので安価であるというメリットも有する。 In the first embodiment, the conductive oxide film 11 is made of a material having a band gap of Al-doped ZnO (ZAO) close to GaN (ZnO: 3.3 eV, GaN: 3.4 eV). The interfacial resistance at the interface between the conductive oxide film 11 and the nitride-based semiconductor thin film 12 can be particularly reduced. Moreover, since the Si substrate is used as the conductive semiconductor substrate, there is an advantage that it is inexpensive.
　以上の効果により、本実施形態１に係る縦型トランジスタ１は、従来の低コスト貼り合わせ技術を用いて作製されたゲート型電界効果トランジスタに比べて、オン抵抗を凡そ数１０％から、半分程度まで低減することができる。 Due to the above effects, the vertical transistor 1 according to the first embodiment has an on-resistance of about several tens of percent to about half that of a gate-type field effect transistor manufactured using a conventional low-cost bonding technique. Can be reduced.
　本実施形態１によれば、導電性半導体基板５０と、窒化物系半導体薄膜１２との間に、３×１０－４Ωｃｍ以下の比抵抗の低い導電性酸化膜１１を配設している。これにより、導電性半導体基板５０／導電性酸化膜１１、導電性酸化膜１１／窒化物系半導体薄膜１２いずれの界面においても、界面抵抗を大幅に低減することができる。その結果、低オン抵抗の縦型トランジスタを実現することができる。
［実施形態２］　　 According to the first embodiment, the conductive oxide film 11 having a low specific resistance of 3 × 10 −4 Ωcm or less is disposed between the conductive semiconductor substrate 50 and the nitride-based semiconductor thin film 12. As a result, the interface resistance can be greatly reduced at any of the interfaces of the conductive semiconductor substrate 50 / conductive oxide film 11 and conductive oxide film 11 / nitride-based semiconductor thin film 12. As a result, a low on-resistance vertical transistor can be realized.
[Embodiment 2]
　次に、上記実施形態とは異なる縦型トランジスタの一例について説明する。本実施形態２に係る縦型トランジスタ２は、Ｎチャネル縦型ＭＯＳＦＥＴのドレイン側にＰコレクタを追加した、いわゆる絶縁ゲートバイポーラトランジスタ（ＩＧＢＴ：Insulated Gate Bipolar Transistor）である。 Next, an example of a vertical transistor different from the above embodiment will be described. The vertical transistor 2 according to the second embodiment is a so-called insulated gate bipolar transistor (IGBT: Insulated Gate Gate Bipolar Transistor) in which a P collector is added to the drain side of the N-channel vertical MOSFET.
　本実施形態２に係る縦型トランジスタは、以下の点を除く基本的な構造は、上記実施形態１と同様である。すなわち、上記実施形態１においては、積層体２０に上面側トレンチ２１を形成していたのに対し、本実施形態２においては、積層体に上面側トレンチ２１が形成されていない点において相違する。従って、積層体の構造が上記実施形態１とは異なる。これに伴って、積層体の上層に配置される絶縁膜やゲート電極の形状が異なる。また、上記実施形態１においては、積層体２０の上層にソース電極が配設されていたのに対し、本実施形態２においては、積層体２０の上層にソース電極に代えてエミッタ電極が形成されている点が相違する。さらに、上記実施形態１においては、導電性半導体基板５０の裏面側にドレイン電極が形成されていたのに対し、本実施形態２においては、導電性半導体基板の裏面側にドレイン電極に変えてコレクタ電極が形成されている点において相違する。 The basic structure of the vertical transistor according to the second embodiment is the same as that of the first embodiment except for the following points. In other words, the upper surface side trench 21 is formed in the stacked body 20 in the first embodiment, but the second embodiment is different in that the upper surface side trench 21 is not formed in the stacked body. Therefore, the structure of the laminate is different from that of the first embodiment. Accordingly, the shapes of the insulating film and the gate electrode arranged on the upper layer of the stacked body are different. In the first embodiment, the source electrode is disposed in the upper layer of the stacked body 20, whereas in the second embodiment, the emitter electrode is formed in the upper layer of the stacked body 20 instead of the source electrode. Is different. Further, in the first embodiment, the drain electrode is formed on the back side of the conductive semiconductor substrate 50, whereas in the second embodiment, the drain electrode is changed to the collector electrode on the back side of the conductive semiconductor substrate. The difference is that an electrode is formed.
　図３に、実施形態２に係る縦型トランジスタの構造を模式的に示す断面図を示す。本実施形態２に係る縦型トランジスタ２は、導電性半導体基板５０ａ、ゲート電極５１ａ、エミッタ電極５５、コレクタ電極５６、導電性酸化膜１１ａ、窒化物系半導体薄膜１２ａ、窒化物系半導体からなる積層体２０ａ、絶縁膜１６ａ等を備える。 FIG. 3 is a cross-sectional view schematically showing the structure of the vertical transistor according to the second embodiment. The vertical transistor 2 according to the second embodiment includes a conductive semiconductor substrate 50a, a gate electrode 51a, an emitter electrode 55, a collector electrode 56, a conductive oxide film 11a, a nitride-based semiconductor thin film 12a, and a stacked layer including a nitride-based semiconductor. A body 20a, an insulating film 16a, and the like.
　縦型トランジスタ２は、少なくとも以下の構造を備える。すなわち、導電性半導体基板５０ａ上に、比抵抗が３×１０－４Ωｃｍ以下の導電性酸化膜１１ａが形成されている。導電性酸化膜１１ａ上には、これと貼り合せてなる、不純物濃度が５×１０１７ｃｍ－３以上のｐ＋型の窒化物系半導体薄膜１２ａが形成されている。窒化物系半導体薄膜１２ａ上には、エピタキシャル成長させることにより得た窒化物系半導体からなる積層体２０ａが形成されている。積層体２０ａ表面には、エミッタ電極５５が形成され、導電性半導体基板５０ａ裏面にはコレクタ電極５６が形成されている。そして、エミッタ電極５５とコレクタ電極５６との間を流れる電流の大きさを制御する機能を有するゲート電極５１ａが形成されている。 The vertical transistor 2 has at least the following structure. That is, the conductive oxide film 11a having a specific resistance of 3 × 10 −4 Ωcm or less is formed on the conductive semiconductor substrate 50a. On the conductive oxide film 11a, a p + -type nitride-based semiconductor thin film 12a having an impurity concentration of 5 × 10 17 cm −3 or more is formed. On the nitride semiconductor thin film 12a, a stacked body 20a made of a nitride semiconductor obtained by epitaxial growth is formed. An emitter electrode 55 is formed on the surface of the stacked body 20a, and a collector electrode 56 is formed on the back surface of the conductive semiconductor substrate 50a. A gate electrode 51a having a function of controlling the magnitude of the current flowing between the emitter electrode 55 and the collector electrode 56 is formed.
　以下、本実施形態２の具体的な一例について説明する。導電性半導体基板５０ａの構成、好ましい材料等については、上記実施形態１で述べたとおりである。本実施形態２においては、比抵抗が０．０４Ωｃｍのｐ型ポリＳｉＣを用いた。 Hereinafter, a specific example of the second embodiment will be described. The configuration, preferable materials, and the like of the conductive semiconductor substrate 50a are as described in the first embodiment. In the second embodiment, p-type poly SiC having a specific resistance of 0.04 Ωcm is used.
　導電性酸化膜１１ａの比抵抗の範囲や、好ましい材料等は、上記実施形態１と同様である。本実施形態２においては、導電性酸化膜１１aとして、比抵抗が１．５×１０－４ΩｃｍのＩＴＯを用いた。また、窒化物系半導体薄膜１２ａとして、不純物濃度が１×１０１８ｃｍ－３で、膜厚が０．３μｍのｐ＋-ＧａＮを用いた。 The specific resistance range and preferred materials of the conductive oxide film 11a are the same as those in the first embodiment. In the second embodiment, ITO having a specific resistance of 1.5 × 10 −4 Ωcm is used as the conductive oxide film 11a. Further, p + -GaN having an impurity concentration of 1 × 10 18 cm −3 and a film thickness of 0.3 μm was used as the nitride-based semiconductor thin film 12a.
　縦型トランジスタの低オン抵抗をより効果的に実現するためには、導電性酸化膜のバンドギャップが２．８ｅＶ～４．０ｅＶである材料を選択することが好ましい。この範囲のバンドギャップの導電性材料を用いることにより、その直上層に形成される窒化物系半導体薄膜との界面抵抗をより効果的に低減することができる。これは、窒化物系半導体薄膜とのバンドギャップ差を小さくできるためである（窒化物系半導体薄膜としてＧａＮを適用した場合、そのバンドギャップは３．４ｅＶである）。バンドギャップが２．８ｅＶ～４．０ｅＶとなる導電性酸化膜の好適な材料としては、ＩＴＯ、ＺｎＯ、ＴｉＯ２、ＳｎＯ２、ＣｄＯ等を挙げることができる。また、比抵抗を効果的に下げるため、前述の材料に金属不純物を添加したものも好適に適用することができる。 In order to more effectively realize the low on-resistance of the vertical transistor, it is preferable to select a material in which the band gap of the conductive oxide film is 2.8 eV to 4.0 eV. By using a conductive material having a band gap in this range, it is possible to more effectively reduce the interface resistance with the nitride-based semiconductor thin film formed immediately above the conductive material. This is because the band gap difference from the nitride semiconductor thin film can be reduced (when GaN is applied as the nitride semiconductor thin film, the band gap is 3.4 eV). Suitable materials for the conductive oxide film having a band gap of 2.8 eV to 4.0 eV include ITO, ZnO, TiO 2 , SnO 2 , CdO, and the like. Further, in order to effectively reduce the specific resistance, a material obtained by adding a metal impurity to the above-described material can be suitably applied.
　積層体２０ａは、ドリフト層１３ａ、チャネル層１４ａ、コンタクト層１５ａを備える。ドリフト層１３ａには、不純物濃度が１×１０１６ｃｍ－３で、膜厚が５μｍのｎ－-ＧａＮを、チャネル層１４ａには、不純物濃度が１×１０１８ｃｍ－３のｐ‐ＧａＮを適用した。さらに、コンタクト層１５ａには、不純物濃度が５×１０１８ｃｍ－３のｎ＋‐ＧａＮを適用した。 The stacked body 20a includes a drift layer 13a, a channel layer 14a, and a contact layer 15a. The drift layer 13a is made of n − -GaN having an impurity concentration of 1 × 10 16 cm −3 and a film thickness of 5 μm, and the channel layer 14a is made of p-GaN having an impurity concentration of 1 × 10 18 cm −3. Applied. Further, n + -GaN having an impurity concentration of 5 × 10 18 cm −3 was applied to the contact layer 15a.
　ドリフト層１３ａの形状は、図３に示すように、凸部を有する構造となっている。チャネル層１４ａ及びコンタクト層１５ａは、ドリフト層１３ａの突出部の両脇部にこの順に形成されている（図３参照）。 The shape of the drift layer 13a has a structure having convex portions as shown in FIG. The channel layer 14a and the contact layer 15a are formed in this order on both sides of the protruding portion of the drift layer 13a (see FIG. 3).
　エミッタ電極５５は、コンタクト層１５ａの表面の所定の位置に形成されている。コレクタ電極５６は、前述したように、導電性半導体基板５０ａの裏面側に形成されている。エミッタ電極５５及びコレクタ電極５６は、ともに、Ｔｉ／Ａｌからなる材料を用いた。無論、エミッタ電極５５とコレクタ電極５６の組成比等は、適宜変更可能であり、両者で一致する必要ない。また、異なる材料を用いてもよい。 The emitter electrode 55 is formed at a predetermined position on the surface of the contact layer 15a. As described above, the collector electrode 56 is formed on the back side of the conductive semiconductor substrate 50a. The emitter electrode 55 and the collector electrode 56 are both made of Ti / Al. Of course, the composition ratio and the like of the emitter electrode 55 and the collector electrode 56 can be changed as appropriate and do not need to match. Different materials may be used.
　積層体２０ａの表面には、コンタクト層１５ａの表面の一部と、チャネル層１４ａの表面全体と、ドリフト層１３ａの表面の少なくとも一部を覆うように、ゲート絶縁膜１６ａが形成されている。そして、ゲート電極５１ａが、ゲート絶縁膜１６ａ上に、ゲート絶縁膜１６ａを介してドリフト層１３ａ、その外側に配置されるチャネル層１４ａ、コンタクト層１５ａと対向配置されるように形成されている。本実施形態２においては、ゲート電極５１ａとして、Ｎｉ／Ａｕを適用した。本実施形態２に係る縦型トランジスタ２は、上記のような構成となっている。 On the surface of the stacked body 20a, a gate insulating film 16a is formed so as to cover a part of the surface of the contact layer 15a, the entire surface of the channel layer 14a, and at least a part of the surface of the drift layer 13a. The gate electrode 51a is formed on the gate insulating film 16a so as to be opposed to the drift layer 13a, the channel layer 14a disposed outside the gate insulating film 16a, and the contact layer 15a. In the second embodiment, Ni / Au is applied as the gate electrode 51a. The vertical transistor 2 according to the second embodiment is configured as described above.
　次に、本実施形態２に係る縦型トランジスタの製造方法について説明する。まず、導電性半導体基板５０ａ上に導電性酸化膜１１ａを形成し、導電性酸化膜１１ａ上に窒化物系半導体薄膜１２ａを形成する。そして、窒化物系半導体薄膜１２ａの上層に、窒化物系半導体からなる積層体２０ａをエピタキシャル成長させ、積層体２０ａ表面にエミッタ電極５５を形成する。そして、導電性半導体基板５０ａ裏面にコレクタ電極５６を形成する。以下、本実施形態２に係る縦型トランジスタの製造方法の具体的な一例を、図４Ａ～図４Ｃを参照しつつ説明する。図４Ａ～図４Ｃは、本実施形態２に係る縦型トランジスタの製造工程を模式的に示す断面図である。 Next, a method for manufacturing a vertical transistor according to the second embodiment will be described. First, the conductive oxide film 11a is formed on the conductive semiconductor substrate 50a, and the nitride-based semiconductor thin film 12a is formed on the conductive oxide film 11a. Then, a stacked body 20a made of a nitride-based semiconductor is epitaxially grown on the nitride-based semiconductor thin film 12a, and an emitter electrode 55 is formed on the surface of the stacked body 20a. Then, a collector electrode 56 is formed on the back surface of the conductive semiconductor substrate 50a. Hereinafter, a specific example of the method for manufacturing the vertical transistor according to the second embodiment will be described with reference to FIGS. 4A to 4C. 4A to 4C are cross-sectional views schematically showing the manufacturing process of the vertical transistor according to the second embodiment.
　はじめに、実施形態１と同様にして、導電性半導体基板５０ａ上に導電性酸化膜１１ａ、窒化物系半導体薄膜１２ａとが貼り合わされた基板を作製する（図４Ａ）。実施形態１との違いは、上述したように材料が異なる点のみであり、製法としては図２Ａ～図２Ｃと全く同様に貼り合わせ基板を作製することが可能である。 First, in the same manner as in the first embodiment, a substrate in which the conductive oxide film 11a and the nitride semiconductor thin film 12a are bonded to the conductive semiconductor substrate 50a is manufactured (FIG. 4A). The only difference from Embodiment 1 is that the materials are different as described above. As a manufacturing method, a bonded substrate can be produced in exactly the same way as in FIGS. 2A to 2C.
　次に、窒化物系半導体薄膜１２ａ上に、有機金属気相成長法を用い、不純物濃度が１×１０１６ｃｍ－３で、膜厚が５μｍのｎ－-ＧａＮからなるドリフト層１３ａを成長させる。その後、選択イオン注入により、ドリフト層１３ａの一部領域にＭｇイオンを注入してチャネル層１４ａを形成する。次いで、チャネル層１４ａの一部にＳｉイオンを注入してコンタクト層１５ａを形成することで、窒化物系半導体からなる積層体２０ａを得る。積層体２０ａ表面に、保護膜（不図示）として２００ｎｍのＳｉＯ２膜を形成した後、１２５０℃で６０秒間の熱処理を行う。これにより、注入イオンが活性化する。その後、保護膜を緩衝フッ酸で除去する（図４Ｂ）。 Next, a drift layer 13a made of n − -GaN having an impurity concentration of 1 × 10 16 cm −3 and a thickness of 5 μm is grown on the nitride-based semiconductor thin film 12a by metal organic vapor phase epitaxy. . Thereafter, Mg ions are implanted into a partial region of the drift layer 13a by selective ion implantation to form the channel layer 14a. Next, Si ions are implanted into part of the channel layer 14a to form the contact layer 15a, thereby obtaining a stacked body 20a made of a nitride-based semiconductor. After forming a 200 nm SiO 2 film as a protective film (not shown) on the surface of the stacked body 20a, heat treatment is performed at 1250 ° C. for 60 seconds. Thereby, the implanted ions are activated. Thereafter, the protective film is removed with buffered hydrofluoric acid (FIG. 4B).
　積層体２０ａ上に、ＡＬＤ（Atomic Layer Deposition）法を用いて、Ａｌ２Ｏ３からなるゲート絶縁膜１６ａを形成する。エミッタ電極５５が形成される領域に開口パターンを形成したフォトレジスト・マスクを利用し、緩衝フッ酸でゲート絶縁膜１６ａの一部をエッチングした後、蒸着・リフトオフ法を用いて、Ｔｉ／Ａｕ（３０ｎｍ／１８０ｎｍ）電極を所定位置に形成する。次いで、７００℃、６０秒のＲＴＡを行って、エミッタ電極５５を得る（図４Ｃ）。 A gate insulating film 16a made of Al 2 O 3 is formed on the stacked body 20a by using an ALD (Atomic Layer Deposition) method. A portion of the gate insulating film 16a is etched with buffered hydrofluoric acid using a photoresist mask in which an opening pattern is formed in the region where the emitter electrode 55 is to be formed. 30 nm / 180 nm) electrodes are formed at predetermined positions. Next, RTA is performed at 700 ° C. for 60 seconds to obtain the emitter electrode 55 (FIG. 4C).
　ゲート電極５１ａが形成される領域に、開口パターンを形成したフォトレジスト・マスクを利用し、蒸着・リフトオフ法を用いて、Ｎｉ／Ａｕ（３０ｎｍ／３００ｎｍ）電極を所定位置に形成する。導電性半導体基板５０ａの裏面を研磨して薄層化した後、真空蒸着法を用いて導電性半導体基板５０ａ裏面にＴｉ／Ａｌからなるドレイン電極５３ａを形成することで、図３の構成になる縦型トランジスタを製造する。 A Ni / Au (30 nm / 300 nm) electrode is formed at a predetermined position in a region where the gate electrode 51a is to be formed by using a photoresist mask having an opening pattern and using a vapor deposition / lift-off method. After the back surface of the conductive semiconductor substrate 50a is polished and thinned, a drain electrode 53a made of Ti / Al is formed on the back surface of the conductive semiconductor substrate 50a by using a vacuum deposition method, so that the configuration of FIG. 3 is obtained. A vertical transistor is manufactured.
　本実施形態２では、比抵抗が３×１０－４Ωｃｍ以下（具体例では、１．５×１０－４Ωｃｍ）の導電性酸化膜１１ａを用いているため、導電性酸化膜１１ａと導電性半導体基板５０ａとの界面に大きな界面抵抗が生じることなく、接合を形成することができる。また、同様の理由により、導電性酸化膜１１ａと窒化物系半導体薄膜１２ａとの界面のいずれにも大きな界面抵抗を生じることなく、接合を形成することができる。 In the second embodiment, the conductive oxide film 11a having a specific resistance of 3 × 10 −4 Ωcm or less (in the specific example, 1.5 × 10 −4 Ωcm) is used. A junction can be formed without generating large interface resistance at the interface with the semiconductor substrate 50a. For the same reason, a junction can be formed without generating a large interface resistance at any of the interfaces between the conductive oxide film 11a and the nitride-based semiconductor thin film 12a.
　しかも、導電性酸化膜１１ａとして、ＩＴＯというバンドギャップがＧａＮに近い（ＩＴＯ：３ｅＶ、ＧａＮ：３．４ｅＶ）材料を用いているため、導電性酸化膜１１ａと窒化物系半導体薄膜１２ａとの界面の界面抵抗を特に低くすることができる。さらに、ＩＴＯのバンドギャップは、導電性半導体基板５０ａに用いているポリＳｉＣのバンドギャップ（２．３ｅＶ～３．２ｅＶ）とも近いため、導電性酸化膜１１ａと導電性半導体基板５０ａとの界面の界面抵抗を低くすることができる。以上の効果により、本実施形態２に係る縦型トランジスタ２は、従来の低コスト貼り合わせ技術を用いて作製された窒化物系半導体を用いた絶縁ゲートバイポーラトランジスタに比べて、オン抵抗を凡そ数１０％から、半分程度まで低減することができる。
［実施形態３］ Moreover, since the conductive oxide film 11a is made of a material having a band gap of ITO close to that of GaN (ITO: 3 eV, GaN: 3.4 eV), the interface between the conductive oxide film 11a and the nitride-based semiconductor thin film 12a. The interfacial resistance can be made particularly low. Further, since the band gap of ITO is close to the band gap (2.3 eV to 3.2 eV) of poly-SiC used for the conductive semiconductor substrate 50a, the interface between the conductive oxide film 11a and the conductive semiconductor substrate 50a. The interface resistance can be lowered. Due to the above-described effects, the vertical transistor 2 according to the second embodiment has an on-resistance approximately several times that of an insulated gate bipolar transistor using a nitride-based semiconductor manufactured using a conventional low-cost bonding technique. It can be reduced from 10% to about half.
[Embodiment 3]
　本実施形態３に係る縦型トランジスタは、いわゆる高電子移動度トランジスタ（ＨＥＭＴ：High Electron Mobility Transistor）である。 The vertical transistor according to the third embodiment is a so-called high electron mobility transistor (HEMT: High Electron Mobility Transistor).
　本実施形態３に係る縦型トランジスタは、以下の点を除く基本的な構造は、上記実施形態１と同様である。すなわち、上記実施形態１においては、導電性半導体基板５０にトレンチを形成していなかったのに対し、本実施形態３においては、導電性半導体基板に導電性酸化膜まで到達するトレンチを形成している点において相違する。また、積層体の構成が、上記実施形態１と異なる。 The basic structure of the vertical transistor according to Embodiment 3 is the same as that of Embodiment 1 except for the following points. That is, in Embodiment 1 above, no trench was formed in the conductive semiconductor substrate 50, whereas in Embodiment 3, a trench reaching the conductive oxide film was formed in the conductive semiconductor substrate. Is different. Moreover, the structure of a laminated body differs from the said Embodiment 1. FIG.
　図５に、本実施形態３に係る縦型トランジスタの構造を模式的に示す断面図を示す。本実施形態３に係る縦型トランジスタ３は、導電性半導体基板５０ｂ、ゲート電極５１ｂ、ソース電極５２ｂ、ドレイン電極５３ｂ、導電性酸化膜１１ｂ、窒化物系半導体薄膜１２ｂ、窒化物系半導体からなる積層体２０ｂ等を備える。 FIG. 5 is a cross-sectional view schematically showing the structure of the vertical transistor according to the third embodiment. The vertical transistor 3 according to the third embodiment includes a conductive semiconductor substrate 50b, a gate electrode 51b, a source electrode 52b, a drain electrode 53b, a conductive oxide film 11b, a nitride-based semiconductor thin film 12b, and a stacked layer composed of a nitride-based semiconductor. A body 20b and the like are provided.
　縦型トランジスタ３は、少なくとも以下の構造を備える。すなわち、導電性半導体基板５０ｂ上に、比抵抗が３×１０－４Ωｃｍ以下の導電性酸化膜１１ｂが形成されている。導電性酸化膜１１ｂ上には、これと貼り合せてなる、不純物濃度が５×１０１７ｃｍ－３以上のｎ＋型若しくはｐ＋型の窒化物系半導体薄膜１２ｂが形成されている。窒化物系半導体薄膜１２ｂ上には、エピタキシャル成長させることにより得た窒化物系半導体からなる積層体２０ｂが形成されている。積層体２０ｂ表面には、ソース電極５２ｂが形成されている。導電性半導体基板５０ｂの一部には、その裏面から導電性酸化膜１１ｂに達する裏面側トレンチ２３が形成されている。導電性半導体基板５０ｂの裏面と、前記裏面側トレンチ２３内壁とには、これらを覆うドレイン電極５３ｂが形成されている。また、積層体２０ｂ上には、ソース電極５２ｂとドレイン電極５３ｂとの間を流れる電流の大きさを制御する機能を有するゲート電極５１ｂが形成されている。 The vertical transistor 3 has at least the following structure. That is, the conductive oxide film 11b having a specific resistance of 3 × 10 −4 Ωcm or less is formed on the conductive semiconductor substrate 50b. On the conductive oxide film 11b, an n + -type or p + -type nitride-based semiconductor thin film 12b having an impurity concentration of 5 × 10 17 cm −3 or more is formed. On the nitride semiconductor thin film 12b, a stacked body 20b made of a nitride semiconductor obtained by epitaxial growth is formed. A source electrode 52b is formed on the surface of the stacked body 20b. A part of the conductive semiconductor substrate 50b is formed with a back side trench 23 that reaches the conductive oxide film 11b from the back side. A drain electrode 53b is formed on the back surface of the conductive semiconductor substrate 50b and the inner wall of the back surface side trench 23 to cover them. A gate electrode 51b having a function of controlling the magnitude of current flowing between the source electrode 52b and the drain electrode 53b is formed on the stacked body 20b.
　以下、本実施形態３の具体的な一例について説明する。導電性半導体基板５０ｂの構成、好ましい材料等については、上記実施形態１で述べたとおりである。本実施形態３においては、導電性半導体基板５０ｂとして、比抵抗が０．０２Ωｃｍのｎ型Ｓｉを用いた。 Hereinafter, a specific example of the third embodiment will be described. The configuration, preferable materials, and the like of the conductive semiconductor substrate 50b are as described in the first embodiment. In the third embodiment, n-type Si having a specific resistance of 0.02 Ωcm is used as the conductive semiconductor substrate 50b.
　導電性酸化膜１１ｂの比抵抗の範囲や、好ましい材料は、上記実施形態１と同様である。また、窒化物系半導体薄膜１２ｂの好ましい不純物濃度等についても、上記実施形態１で述べたとおりである。本実施形態３においては、導電性酸化膜１１ｂとして、比抵抗が３×１０－４ΩｃｍのＮｂ添加ＴｉＯ２を用いた。また、窒化物系半導体薄膜１２ｂとして、不純物濃度が５×１０１８ｃｍ－３で膜厚が０．１μｍのｎ＋-ＧａＮを用いた。 The range of the specific resistance of the conductive oxide film 11b and preferred materials are the same as those in the first embodiment. The preferable impurity concentration and the like of the nitride-based semiconductor thin film 12b are also as described in the first embodiment. In the third embodiment, Nb-added TiO 2 having a specific resistance of 3 × 10 −4 Ωcm is used as the conductive oxide film 11b. Further, n + -GaN having an impurity concentration of 5 × 10 18 cm −3 and a film thickness of 0.1 μm was used as the nitride-based semiconductor thin film 12b.
　積層体２０ｂは、ドリフト層１３ｂ、障壁層１７、チャネル層１４ｂ、チャネル層１４ｂにヘテロ接合する電子供給層１８がこの順に積層されている。ドリフト層１３ｂには、不純物濃度が１×１０１６ｃｍ－３で、膜厚が４μｍのｎ－-ＧａＮを、障壁層１７には、不純物濃度が１×１０１８ｃｍ－３で膜厚が０．５μｍのｐ‐ＧａＮを用いた。また、チャネル層１４ｂには、膜厚が５０ｎｍのノンドープＧａＮを、電子供給層１８には、膜厚が３０ｎｍのノンドープＡｌ０．２Ｇａ０．８Ｎを用いた。 In the stacked body 20b, a drift layer 13b, a barrier layer 17, a channel layer 14b, and an electron supply layer 18 heterojunction with the channel layer 14b are stacked in this order. The drift layer 13b is made of n − -GaN with an impurity concentration of 1 × 10 16 cm −3 and a film thickness of 4 μm, and the barrier layer 17 is made with an impurity concentration of 1 × 10 18 cm −3 and a film thickness of 0 .5 μm p-GaN was used. The channel layer 14b was made of non-doped GaN having a thickness of 50 nm, and the electron supply layer 18 was made of non-doped Al 0.2 Ga 0.8 N having a thickness of 30 nm.
　電子供給層１８の表面には、Ｔｉ／Ａｌからなるソース電極５２ｂとＮｉ／Ａｕからなるゲート電極５１ｂが形成されている。また、ゲート電極５１ｂに対して、ソース電極５２ｂが対向配置されていない側には、電子伝導領域として機能する不純物濃度が３×１０１８ｃｍ－３のｎ＋型領域１９が形成されている。電子伝導領域として機能するｎ＋型領域１９は、少なくともチャネル層１４ｂの実質的な表面から、障壁層１７よりも窒化物系半導体薄膜１２ｂ側に近い領域までに亘って延在する領域に形成されている。本実施形態３に係るｎ＋型領域１９は、チャネル層１４ｂの表面からドリフト層１３ｂの一部の領域に到達する領域に形成されている。なお、ｎ＋型領域１９は、電子供給層１８の表面から、障壁層１７よりも窒化物系半導体薄膜１２ｂ側に近い領域までに亘って延在する領域に形成するようにしてもよい。導電性半導体基板５０ｂの一部には、その裏面から導電性酸化膜１１ｂに達する裏面側トレンチ２３が形成されており、導電性半導体基板５０ｂの裏面と裏面側トレンチ２３内壁とを覆う、Ｔｉ／Ａｌからなるドレイン電極５３ｂが形成されている。 On the surface of the electron supply layer 18, a source electrode 52b made of Ti / Al and a gate electrode 51b made of Ni / Au are formed. Further, an n + type region 19 having an impurity concentration of 3 × 10 18 cm −3 that functions as an electron conduction region is formed on the side where the source electrode 52b is not disposed opposite to the gate electrode 51b. The n + -type region 19 functioning as an electron conducting region is formed in a region extending from at least a substantial surface of the channel layer 14b to a region closer to the nitride-based semiconductor thin film 12b side than the barrier layer 17. ing. The n + -type region 19 according to the third embodiment is formed in a region that reaches a partial region of the drift layer 13b from the surface of the channel layer 14b. The n + -type region 19 may be formed in a region extending from the surface of the electron supply layer 18 to a region closer to the nitride-based semiconductor thin film 12b side than the barrier layer 17. A part of the conductive semiconductor substrate 50b is formed with a back side trench 23 that reaches the conductive oxide film 11b from the back side, and covers the back side of the conductive semiconductor substrate 50b and the inner wall of the back side trench 23. A drain electrode 53b made of Al is formed.
　実施形態３に係る縦型トランジスタは、チャネル層１４ｂと電子供給層１８との界面付近に、分極効果により蓄積される２次元電子ガス２５をチャネルとする、いわゆる高電子移動度トランジスタ（ＨＥＭＴ：High Electron Mobility Transistor）となっている。 The vertical transistor according to the third embodiment is a so-called high electron mobility transistor (HEMT: High) that uses a two-dimensional electron gas 25 accumulated by a polarization effect as a channel near the interface between the channel layer 14b and the electron supply layer 18. Electron Mobility Transistor).
　次に、実施形態３に係る縦型トランジスタの製造方法の一例を、図６Ａ～図６Ｃを参照しつつ説明する。図６Ａ～図６Ｃは、本実施形態３に係る縦型トランジスタの製造工程を模式的に示す断面図である。 Next, an example of a method for manufacturing the vertical transistor according to the third embodiment will be described with reference to FIGS. 6A to 6C. 6A to 6C are cross-sectional views schematically showing the manufacturing process of the vertical transistor according to the third exemplary embodiment.
　はじめに、実施形態１と同様にして、導電性半導体基板５０ｂ上に導電性酸化膜１１ｂ、窒化物系半導体薄膜１２ｂとが貼り合わされた基板を作製する（図６Ａ）。実施形態１との違いは、導電性酸化膜１１ｂにＮｂ添加ＴｉＯ２を用いるという材料の違いのみで、製法としては図２Ａ～図２Ｃと全く同様に貼り合わせ基板を作製することが可能である。 First, in the same manner as in the first embodiment, a substrate in which the conductive oxide film 11b and the nitride semiconductor thin film 12b are bonded to the conductive semiconductor substrate 50b is manufactured (FIG. 6A). The only difference from the first embodiment is the difference in material in which Nb-added TiO 2 is used for the conductive oxide film 11b. As a manufacturing method, a bonded substrate can be manufactured in exactly the same manner as in FIGS. 2A to 2C. .
　次に、窒化物系半導体薄膜１２ｂ上に、有機金属気相成長法を用い、積層体２０ｂを得る。具体的には、不純物濃度が１×１０１６ｃｍ－３で膜厚が４μｍのｎ－-ＧａＮからなるドリフト層１３ｂと、不純物濃度が１×１０１８ｃｍ－３で膜厚が０．５μｍのｐ‐ＧａＮからなる障壁層１７と、膜厚が５０ｎｍのノンドープＧａＮからなるチャネル層１４ｂと、膜厚が３０ｎｍのノンドープＡｌ０．２Ｇａ０．８Ｎからなる電子供給層１８とを成長させる。次いで、選択イオン注入を用いて、積層体２０ｂの一部にＳｉイオンを注入してｎ＋型領域層１９を形成する。その後、積層体２０ｂ表面に、保護膜（不図示）として３００ｎｍのＳｉＯ２膜を形成した後、１２５０℃で６０秒間の熱処理を行う。これにより、注入イオンが活性化する。その後、保護膜を緩衝フッ酸で除去する（図６Ｂ）。 Next, a stacked body 20b is obtained on the nitride-based semiconductor thin film 12b by using a metal organic chemical vapor deposition method. Specifically, a drift layer 13b made of n − -GaN having an impurity concentration of 1 × 10 16 cm −3 and a film thickness of 4 μm, and an impurity concentration of 1 × 10 18 cm −3 and a film thickness of 0.5 μm. A barrier layer 17 made of p-GaN, a channel layer 14b made of non-doped GaN having a thickness of 50 nm, and an electron supply layer 18 made of non-doped Al 0.2 Ga 0.8 N having a thickness of 30 nm are grown. Next, by using selective ion implantation, Si ions are implanted into a part of the stacked body 20 b to form the n + -type region layer 19. Thereafter, a 300 nm SiO 2 film is formed as a protective film (not shown) on the surface of the stacked body 20b, and then heat treatment is performed at 1250 ° C. for 60 seconds. Thereby, the implanted ions are activated. Thereafter, the protective film is removed with buffered hydrofluoric acid (FIG. 6B).
　続いて、電子供給層１８上にソース電極５２ｂを形成する。具体的には、ソース電極５２ｂが形成される領域に開口パターンを形成したフォトレジスト・マスクを利用し、蒸着・リフトオフ法を用いて、Ｔｉ／Ａｌ（３０ｎｍ／１８０ｎｍ）電極パターンを、電子供給層１８表面の所定位置に形成する。その後、７００℃、６０秒のＲＴＡを行って、ソース電極５２ｂを得る。 Subsequently, the source electrode 52 b is formed on the electron supply layer 18. Specifically, a Ti / Al (30 nm / 180 nm) electrode pattern is formed on the electron supply layer by using a photoresist mask having an opening pattern in a region where the source electrode 52b is formed, and using an evaporation / lift-off method. 18 is formed at a predetermined position on the surface. Thereafter, RTA is performed at 700 ° C. for 60 seconds to obtain the source electrode 52b.
　次いで、同じく電子供給層１８上であって、ソース電極５２ｂと離間した位置にゲート電極５１ｂを形成する。具体的には、ゲート電極５１ｂが形成される領域に開口パターンを形成したフォトレジスト・マスクを利用し、蒸着・リフトオフ法を用いて、Ｎｉ／Ａｌ（３０ｎｍ／３００ｎｍ）電極パターンを、電子供給層１８表面の所定位置に形成する（図６Ｃ）。 Next, a gate electrode 51b is formed on the electron supply layer 18 at a position spaced from the source electrode 52b. Specifically, using a photoresist mask in which an opening pattern is formed in a region where the gate electrode 51b is to be formed, a Ni / Al (30 nm / 300 nm) electrode pattern is formed on the electron supply layer by vapor deposition / lift-off method. 18 is formed at a predetermined position on the surface (FIG. 6C).
　次に、導電性半導体基板５０ｂの裏面側にドレイン電極を形成する。具体的には、導電性半導体基板５０ｂの裏面を研磨して薄層化した後、所定の位置に開口パターンを形成したフォトレジスト・マスクを利用し、ＲＩＥ（Reactive Ion Etching）法を用いて、導電性半導体基板５０ｂの裏面から導電性酸化膜１１ｂに達する裏面側トレンチ２３を形成する。次いで、真空蒸着法を用いて導電性半導体基板５０ｂ裏面と前記裏面側トレンチ２３内壁とを覆うように、Ｔｉ／Ａｌからなるドレイン電極５３ｂを形成することで、図５の構成になる縦型トランジスタ３を完成する。 Next, a drain electrode is formed on the back side of the conductive semiconductor substrate 50b. Specifically, after polishing and thinning the back surface of the conductive semiconductor substrate 50b, a RIE (Reactive パ タ ー ン Ion Etching) method is used using a photoresist mask in which an opening pattern is formed at a predetermined position. A back side trench 23 reaching the conductive oxide film 11b from the back side of the conductive semiconductor substrate 50b is formed. Next, a vertical electrode having the configuration of FIG. 5 is formed by forming a drain electrode 53b made of Ti / Al so as to cover the back surface of the conductive semiconductor substrate 50b and the inner wall of the back surface side trench 23 by using a vacuum evaporation method. Complete 3
　縦型トランジスタ３によれば、チャネル層１４ｂと電子供給層１８との界面に、分極電荷により蓄積される２次元電子ガス２５をチャネルとする、いわゆる高電子移動度トランジスタが製造される。 According to the vertical transistor 3, a so-called high electron mobility transistor using a two-dimensional electron gas 25 accumulated by polarization charge as a channel at the interface between the channel layer 14b and the electron supply layer 18 is manufactured.
　本実施形態３では、比抵抗が３×１０－４Ωｃｍ以下（具体例では、３×１０－４Ωｃｍ）の導電性酸化膜１１ｂを用いているため、導電性酸化膜１１ｂと導電性半導体基板５０ｂとの界面に大きな界面抵抗を生じることなく、接合することができる。同様の理由により、導電性酸化膜１１ｂと窒化物系半導体薄膜１２ｂとの界面に大きな界面抵抗を生じることなく、接合を形成することができる。 In the third embodiment, since the conductive oxide film 11b having a specific resistance of 3 × 10 −4 Ωcm or less (specific example: 3 × 10 −4 Ωcm) is used, the conductive oxide film 11b and the conductive semiconductor substrate are used. Bonding can be performed without generating large interface resistance at the interface with 50b. For the same reason, a junction can be formed without generating a large interface resistance at the interface between the conductive oxide film 11b and the nitride-based semiconductor thin film 12b.
　しかも、導電性酸化膜１１ｂとして、Ｎｂ添加ＴｉＯ２というバンドギャップがＧａＮに近い（ＴｉＯ２：３．２ｅＶ、ＧａＮ：３．４ｅＶ）材料を用いているため、導電性酸化膜１１ｂと窒化物系半導体薄膜１２ｂとの界面の界面抵抗を特に低くすることができる。さらに、本実施形態３では、導電性半導体基板５０ｂの一部に、その裏面から導電性酸化膜１１ｂに達する裏面側トレンチ２３を形成し、ドレイン電極５３ｂが導電性酸化膜１１ｂに直接接触するように形成している。これにより、ｎ型Ｓｉからなる導電性半導体基板５０ｂと、Ｎｂ添加ＴｉＯ２からなる導電性酸化膜１１ｂとのバンドギャップ差に起因した界面抵抗をほぼ０にすることができる。以上の効果により、本実施形態３に係る縦型トランジスタは、従来の低コスト貼り合わせ技術を用いて作製された窒化物系半導体を用いた高電子移動度トランジスタに比べて、オン抵抗を凡そ数１０％から、半分程度まで低減することができる。 Moreover, since the conductive oxide film 11b is made of a material having a band gap of Nb-added TiO 2 close to that of GaN (TiO 2 : 3.2 eV, GaN: 3.4 eV), the conductive oxide film 11b and the nitride system are used. The interface resistance at the interface with the semiconductor thin film 12b can be particularly lowered. Further, in the third embodiment, the back side trench 23 reaching the conductive oxide film 11b from the back side is formed in a part of the conductive semiconductor substrate 50b, and the drain electrode 53b is in direct contact with the conductive oxide film 11b. Is formed. Thereby, the interface resistance caused by the band gap difference between the conductive semiconductor substrate 50b made of n-type Si and the conductive oxide film 11b made of Nb-added TiO 2 can be made almost zero. Due to the above-described effects, the vertical transistor according to the third embodiment has an on-resistance that is approximately several times higher than that of a high electron mobility transistor using a nitride-based semiconductor manufactured using a conventional low-cost bonding technique. It can be reduced from 10% to about half.
　本実施形態３に係る縦型トランジスタでは、導電性半導体基板５０ｂの一部に、導電性酸化膜１１ｂに達する裏面側トレンチ２３を形成している。この場合、ドレイン電極５３ｂ、又はコレクタ電極は、導電性半導体基板５０ｂの裏面だけでなく、裏面側トレンチ２３の側面及び底面にも接触するように形成することが好ましい。このような構成にすることで、導電性半導体基板５０ｂ／導電性酸化膜１１ｂ界面の界面抵抗を低減することができ、より低いオン抵抗の縦型トランジスタを実現することができる。 In the vertical transistor according to the third embodiment, the back-side trench 23 reaching the conductive oxide film 11b is formed in a part of the conductive semiconductor substrate 50b. In this case, the drain electrode 53b or the collector electrode is preferably formed so as to contact not only the back surface of the conductive semiconductor substrate 50b but also the side surface and the bottom surface of the back surface side trench 23. With such a configuration, the interface resistance at the interface of the conductive semiconductor substrate 50b / conductive oxide film 11b can be reduced, and a vertical transistor having a lower on-resistance can be realized.
　以上、本発明の具体例として実施形態１～３を例として説明したが、上記本実施形態１～３に示した材料や製造工程は、一例を示したものであってこれに限定されるものではない。窒化物系半導体としてＧａＮ系の例について述べたが、ＡｌＧａＮ、ＩｎＧａＮ、ＩｎＡｌＮ、ＩｎＡｌＧａＮ系などの窒化物系半導体においても、本発明を適用することができる。ゲート絶縁膜１６、１６ａには、ＳｉＯ２やＡｌ２Ｏ３だけでなく、ＳｉＮ、ＳｉＯＮ、ＡｌＮ、ＭｇＯ、Ｓｃ２Ｏ３、ＺｒＯ２、ＨｆＯ２、あるいはこれらの積層構造を用いることができる。また、電子供給層１８とゲート電極５１ｂとの間にゲート絶縁膜を設けてＭＩＳゲート構造とすることもできる。 As described above, the first to third embodiments have been described as specific examples of the present invention. However, the materials and manufacturing processes described in the first to third embodiments are only examples and are not limited thereto. is not. Although a GaN-based example has been described as the nitride-based semiconductor, the present invention can also be applied to nitride-based semiconductors such as AlGaN, InGaN, InAlN, and InAlGaN. As the gate insulating films 16 and 16a, not only SiO 2 and Al 2 O 3 but also SiN, SiON, AlN, MgO, Sc 2 O 3 , ZrO 2 , HfO 2 , or a stacked structure thereof can be used. Further, a MIS gate structure can be formed by providing a gate insulating film between the electron supply layer 18 and the gate electrode 51b.
　また、上記実施形態１～３は、各構造を自由に組み合わせることが可能である。例えば、上記実施形態１～３に示したそれぞれのチャネル構造は、これに限定されるものではなく、各チャネル構造を他の実施形態に適用することも可能である。例えば、実施形態１に示したトレンチゲート型のチャネルを、実施形態２に適用してトレンチゲート型ＩＧＢＴを作製することも可能である。また、実施形態３に示したＨＥＭＴ型のチャネルを実施形態１に適用することも可能である。さらに、実施形態３に示した導電性半導体基板５０ｂの一部に、その裏面から導電性酸化膜１１ｂに達する裏面側トレンチ２３を形成する構成は、実施形態１及び２に適用可能である。 Further, in the first to third embodiments, the structures can be freely combined. For example, each of the channel structures shown in the first to third embodiments is not limited to this, and each channel structure can be applied to other embodiments. For example, a trench gate type IGBT can be manufactured by applying the trench gate type channel described in the first embodiment to the second embodiment. Further, the HEMT type channel shown in the third embodiment can be applied to the first embodiment. Furthermore, the configuration in which the back-side trench 23 reaching the conductive oxide film 11b from the back surface is formed in a part of the conductive semiconductor substrate 50b shown in the third embodiment is applicable to the first and second embodiments.
　また、窒化物系半導体をエピタキシャル成長した積層体の層数や厚さ、組成などの構造は、実施形態１～３に挙げた構造に限定されない。例えば、実施形態２では貼り合わせにより得たｐ＋‐ＧａＮよりなる窒化物系半導体薄膜１２ａの上に、ｎ－-ＧａＮからなるドリフト層１３ａを成長させる例を説明した。しかしながら、エピタキシャル成長開始界面とｐｎ接合界面を一致させると良好なｐｎ接合を得るのが難しい場合には、ドリフト層１３ａ成長前にｐ＋‐ＧａＮ層をエピタキシャル成長させ、次いでｎ－-ＧａＮからなるドリフト層１３ａを成長させてもよい。これにより、エピタキシャル成長開始界面とｐｎ接合界面を異なる位置にすることができる。このようにエピタキシャル成長により得る積層体は、窒化物系半導体を積層したものであれば、その層数、厚さ、組成など自由に組み合わせて用いることができる。 Further, the number of layers, the thickness, the composition, and the like of the laminate obtained by epitaxially growing the nitride-based semiconductor are not limited to the structures described in the first to third embodiments. For example, in the second embodiment, the example in which the drift layer 13a made of n − -GaN is grown on the nitride semiconductor thin film 12a made of p + -GaN obtained by bonding has been described. However, if it is difficult to obtain a good pn junction when the epitaxial growth start interface and the pn junction interface coincide with each other, the p + -GaN layer is epitaxially grown before the growth of the drift layer 13a, and then the drift layer made of n − -GaN 13a may be grown. Thereby, the epitaxial growth start interface and the pn junction interface can be located at different positions. Thus, the laminated body obtained by epitaxial growth can be used by freely combining the number of layers, thickness, composition, etc., as long as nitride semiconductors are laminated.
　以上、実施形態を参照して本願発明を説明したが、本願発明は上記によって限定されるものではない。本願発明の構成や詳細には、発明のスコープ内で当業者が理解し得る様々な変更をすることができる。 As described above, the present invention has been described with reference to the embodiment, but the present invention is not limited to the above. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the invention.
　上記の実施形態の一部又は全部は、以下の付記のようにも記載され得るが、以下に限定されるものではない。 Some or all of the above embodiments may be described as in the following supplementary notes, but are not limited to the following.
（付記１）　導電性半導体基板と、前記導電性半導体基板表面に形成され、比抵抗が３×１０－４Ωｃｍ以下の導電性酸化膜と、前記導電性酸化膜上に貼り合せてなる、不純物濃度が５×１０１７ｃｍ－３以上のｎ＋型、又はｐ＋型の窒化物系半導体薄膜と、前記窒化物系半導体薄膜上にエピタキシャル成長された、窒化物系半導体からなる積層体と、前記積層体表面に形成されたソース電極、又はエミッタ電極と、前記導電性半導体基板裏面に形成されたドレイン電極、又はコレクタ電極と、前記ソース電極と前記ドレイン電極との間、若しくは前記エミッタ電極と前記コレクタ電極との間を流れる電流の大きさを制御する機能を有するゲート電極とを備える縦型トランジスタ。 (Supplementary Note 1) Impurity formed by bonding a conductive semiconductor substrate, a conductive oxide film having a specific resistance of 3 × 10 −4 Ωcm or less formed on the surface of the conductive semiconductor substrate, and the conductive oxide film An n + -type or p + -type nitride-based semiconductor thin film having a concentration of 5 × 10 17 cm −3 or more, a laminate composed of a nitride-based semiconductor epitaxially grown on the nitride-based semiconductor thin film, A source electrode or emitter electrode formed on the surface of the laminate, a drain electrode or collector electrode formed on the back surface of the conductive semiconductor substrate, and between the source electrode and the drain electrode or between the emitter electrode and the A vertical transistor comprising a gate electrode having a function of controlling a magnitude of a current flowing between the collector electrode.
（付記２）　前記導電性酸化膜の融点が、１３００℃以上であることを特徴とする付記１に記載の縦型トランジスタ。 (Additional remark 2) Melting | fusing point of the said conductive oxide film is 1300 degreeC or more, The vertical transistor of Additional remark 1 characterized by the above-mentioned.
（付記３）　前記導電性酸化膜のバンドギャップが、２．８ｅＶ以上、４．０ｅＶ以下であることを特徴とする付記１又は２に記載の縦型トランジスタ。 (Additional remark 3) The vertical transistor of Additional remark 1 or 2 characterized by the band gap of the said conductive oxide film being 2.8 eV or more and 4.0 eV or less.
（付記４）　前記導電性酸化膜が、ＩＴＯ、ＺｎＯ、ＴｉＯ２、ＳｎＯ２、ＣｄＯ、若しくは、これらに金属不純物を添加したもののいずれかであることを特徴とする付記１乃至３のいずれかに記載の縦型トランジスタ。 (Supplementary note 4) Any one of Supplementary notes 1 to 3, wherein the conductive oxide film is any one of ITO, ZnO, TiO 2 , SnO 2 , CdO, or a metal impurity added thereto. The vertical transistor as described.
（付記５）　前記導電性半導体基板が、Ｓｉ、ポリＳｉ、ポリＳｉＣのいずれかよりなることを特徴とする付記１乃至４のいずれかに記載の縦型トランジスタ。 (Supplementary Note 5) The vertical transistor according to any one of Supplementary Notes 1 to 4, wherein the conductive semiconductor substrate is made of any one of Si, poly-Si, and poly-SiC.
（付記６）　前記導電性半導体基板の一部に、その裏面から前記導電性酸化膜に達する裏面側トレンチが形成されており、前記ドレイン電極、又は前記コレクタ電極は、前記導電性半導体基板の裏面と前記裏面側トレンチの内壁とを覆うように形成されていることを特徴とする付記１乃至５のいずれかに記載の縦型トランジスタ。 (Additional remark 6) The back surface side trench which reaches the said conductive oxide film from the back surface is formed in a part of said conductive semiconductor substrate, The said drain electrode or the said collector electrode is a back surface of the said conductive semiconductor substrate The vertical transistor according to any one of appendices 1 to 5, wherein the vertical transistor is formed so as to cover the inner wall of the backside trench.
（付記７）　前記窒化物系半導体からなる積層体は、前記窒化物系半導体薄膜上に形成されたドリフト層と、前記ドリフト層上に形成された障壁層と、前記障壁層上に形成されたチャネル層と、前記チャネル層上にヘテロ接合する電子供給層とを備えており、前記ゲート電極は、前記積層体上に前記ソース電極と間隙を持って対向配置されるように形成され、前記ゲート電極に対して、前記ソース電極が対向配置されていない側に、少なくとも前記チャネル層の実質的な表面から、前記障壁層よりも前記窒化物系半導体薄膜側に近い領域までに亘って延在する電子伝導領域を備えていることを特徴とする付記１乃至６いずれかに記載の縦型トランジスタ。 (Additional remark 7) The laminated body which consists of the said nitride-type semiconductor was formed on the said drift layer formed on the said nitride-type semiconductor thin film, the barrier layer formed on the said drift layer, and the said barrier layer A channel layer; and an electron supply layer heterojunctioned on the channel layer, wherein the gate electrode is formed on the stacked body so as to be opposed to the source electrode with a gap, and the gate The electrode extends to the side where the source electrode is not opposed to the electrode, at least from the substantial surface of the channel layer to a region closer to the nitride-based semiconductor thin film side than the barrier layer. The vertical transistor according to any one of appendices 1 to 6, further comprising an electron conduction region.
（付記８）　前記導電性酸化膜の膜厚は、５ｎｍ以上、１０００ｎｍ以下であることを特徴とする付記１乃至７のいずれかに記載の縦型トランジスタ。 (Supplementary note 8) The vertical transistor according to any one of supplementary notes 1 to 7, wherein the conductive oxide film has a thickness of 5 nm or more and 1000 nm or less.
（付記９）　前記導電性酸化膜の膜厚は、１０ｎｍ以上、５００ｎｍ以下であることを特徴とする付記１乃至８のいずれかに記載の縦型トランジスタ。 (Appendix 9) The vertical transistor according to any one of appendices 1 to 8, wherein the conductive oxide film has a thickness of 10 nm or more and 500 nm or less.
（付記１０）　前記導電性酸化膜の膜厚は、２０ｎｍ以上、３００ｎｍ以下であることを特徴とする付記１乃至９のいずれかに記載の縦型トランジスタ。 (Supplementary note 10) The vertical transistor according to any one of supplementary notes 1 to 9, wherein the conductive oxide film has a thickness of 20 nm or more and 300 nm or less.
（付記１１）　前記窒化物系半導体薄膜は、前記不純物濃度が１×１０１８ｃｍ－３以上、５×１０２０ｃｍ－３以下であることを特徴とする付記１乃至１０のいずれかに記載の縦型トランジスタ。 (Appendix 11) The nitride semiconductor thin film according to any one of appendices 1 to 10, wherein the impurity concentration is 1 × 10 18 cm −3 or more and 5 × 10 20 cm −3 or less. Vertical transistor.
（付記１２）　導電性半導体基板上に、導電性酸化膜を形成し、前記導電性酸化膜上に、窒化物系半導体薄膜を形成し、前記窒化物系半導体薄膜の上層に、窒化物系半導体からなる積層体をエピタキシャル成長させ、前記積層体表面にソース電極、又はエミッタ電極を形成し、前記導電性半導体基板裏面にドレイン電極、又はコレクタ電極を形成する縦型トランジスタの製造方法。 (Supplementary Note 12) A conductive oxide film is formed on a conductive semiconductor substrate, a nitride semiconductor thin film is formed on the conductive oxide film, and a nitride semiconductor is formed on the nitride semiconductor thin film. A method of manufacturing a vertical transistor, comprising: epitaxially growing a laminate comprising: forming a source electrode or an emitter electrode on a surface of the laminate; and forming a drain electrode or a collector electrode on a back surface of the conductive semiconductor substrate.
（付記１３）　前記窒化物系半導体薄膜は、前記導電性酸化膜上に、窒化物系半導体バルク結晶を貼り合わせ、前記窒化物系半導体バルク結晶を厚み方向で分割することにより得ることを特徴とする付記１２に記載の縦型トランジスタの製造方法。 (Appendix 13) The nitride semiconductor thin film is obtained by bonding a nitride semiconductor bulk crystal on the conductive oxide film and dividing the nitride semiconductor bulk crystal in the thickness direction. The manufacturing method of the vertical transistor as described in appendix 12.
（付記１４）　縦型トランジスタが搭載された半導体装置であって、前記縦型トランジスタとして付記１乃至１１のいずれかに記載の縦型トランジスタを備える半導体装置。 (Appendix 14) A semiconductor device including a vertical transistor, the semiconductor device including the vertical transistor according to any one of Appendixes 1 to 11 as the vertical transistor.
　この出願は、２００９年７月１４日に出願された日本出願特願２００９－１６５３５８を基礎とする優先権を主張し、その開示の全てをここに取り込む。 This application claims priority based on Japanese Patent Application No. 2009-165358 filed on July 14, 2009, the entire disclosure of which is incorporated herein.
　本発明に係る窒化物系半導体を用いた縦型トランジスタは、低いオン抵抗を低コストに実現することができ、消費電力を小さくできる構造を有する。これらの利点を活用して、ＰＣの電源や自動車のパワーステアリングなどの電力制御装置に使用されるトランジスタへの応用が可能である。 The vertical transistor using the nitride semiconductor according to the present invention has a structure that can realize low on-resistance at low cost and reduce power consumption. Utilizing these advantages, it can be applied to a transistor used in a power control device such as a PC power supply or an automobile power steering.
１～３　　縦型トランジスタ
１１　　導電性酸化膜
１２　　窒化物系半導体薄膜
１３　　ドリフト層
１４　　チャネル層
１５　　コンタクト層
１６　　絶縁膜
１７　　障壁層
１８　　電子供給層
１９　　ｎ＋型領域
２０　　積層体
２１　　上面側トレンチ
２３　　裏面側トレンチ
２５　　２次元電子ガス
３０　　窒化物系半導体バルク結晶
５０　　導電性半導体基板
５１　　ゲート電極
５２　　ソース電極
５３　　ドレイン電極
５５　　エミッタ電極
５６　　コレクタ電極 1-3 Vertical transistor 11 Conductive oxide film 12 Nitride-based semiconductor thin film 13 Drift layer 14 Channel layer 15 Contact layer 16 Insulating film 17 Barrier layer 18 Electron supply layer 19 n + type region 20 Stack 21 Upper surface side trench 23 Back surface Side trench 25 Two-dimensional electron gas 30 Nitride semiconductor bulk crystal 50 Conductive semiconductor substrate 51 Gate electrode 52 Source electrode 53 Drain electrode 55 Emitter electrode 56 Collector electrode

Claims (10)

  1. 　導電性半導体基板と、
    　前記導電性半導体基板表面に形成され、比抵抗が３×１０－４Ωｃｍ以下の導電性酸化膜と、
    　前記導電性酸化膜上に貼り合せてなる、不純物濃度が５×１０１７ｃｍ－３以上のｎ＋型、又はｐ＋型の窒化物系半導体薄膜と、
    　前記窒化物系半導体薄膜上にエピタキシャル成長された、窒化物系半導体からなる積層体と、
    　前記積層体表面に形成されたソース電極、又はエミッタ電極と、
    　前記導電性半導体基板裏面に形成されたドレイン電極、又はコレクタ電極と、
    　前記ソース電極と前記ドレイン電極との間、若しくは前記エミッタ電極と前記コレクタ電極との間を流れる電流の大きさを制御する機能を有するゲート電極と
    を備える縦型トランジスタ。     A conductive semiconductor substrate;
    A conductive oxide film having a specific resistance of 3 × 10 −4 Ωcm or less formed on the surface of the conductive semiconductor substrate;
    An n + -type or p + -type nitride-based semiconductor thin film having an impurity concentration of 5 × 10 17 cm −3 or more, which is bonded to the conductive oxide film;
    A laminate made of a nitride semiconductor epitaxially grown on the nitride semiconductor thin film;
    A source electrode or an emitter electrode formed on the surface of the laminate,
    A drain electrode formed on the back surface of the conductive semiconductor substrate, or a collector electrode;
    A vertical transistor comprising a gate electrode having a function of controlling a magnitude of a current flowing between the source electrode and the drain electrode or between the emitter electrode and the collector electrode.
  2. 　前記導電性酸化膜の融点が、１３００℃以上であることを特徴とする請求項１に記載の縦型トランジスタ。 The vertical transistor according to claim 1, wherein the conductive oxide film has a melting point of 1300 ° C. or higher.
  3. 　前記導電性酸化膜のバンドギャップが、２．８ｅＶ以上、４．０ｅＶ以下であることを特徴とする請求項１又は２に記載の縦型トランジスタ。 3. The vertical transistor according to claim 1, wherein a band gap of the conductive oxide film is 2.8 eV or more and 4.0 eV or less.
  4. 　前記導電性酸化膜が、ＩＴＯ、ＺｎＯ、ＴｉＯ２、ＳｎＯ２、ＣｄＯ、若しくは、これらに金属不純物を添加したもののいずれかであることを特徴とする請求項１乃至３のいずれか１項に記載の縦型トランジスタ。 4. The conductive oxide film according to claim 1, wherein the conductive oxide film is any one of ITO, ZnO, TiO 2 , SnO 2 , CdO, or a metal impurity added thereto. Vertical transistor.
  5. 　前記導電性半導体基板が、Ｓｉ、ポリＳｉ、ポリＳｉＣのいずれかよりなることを特徴とする請求項１乃至４のいずれか１項に記載の縦型トランジスタ。 The vertical transistor according to any one of claims 1 to 4, wherein the conductive semiconductor substrate is made of any one of Si, poly-Si, and poly-SiC.
  6. 　前記導電性半導体基板の一部に、その裏面から前記導電性酸化膜に達する裏面側トレンチが形成されており、
    　前記ドレイン電極、又は前記コレクタ電極は、前記導電性半導体基板の裏面と前記裏面側トレンチの内壁とを覆うように形成されていることを特徴とする請求項１乃至５のいずれか１項に記載の縦型トランジスタ。     A back side trench reaching the conductive oxide film from the back side is formed in a part of the conductive semiconductor substrate,
    The said drain electrode or the said collector electrode is formed so that the back surface of the said conductive semiconductor substrate and the inner wall of the said back surface side trench may be covered. Vertical transistor.
  7. 　前記窒化物系半導体からなる積層体は、前記窒化物系半導体薄膜上に形成されたドリフト層と、前記ドリフト層上に形成された障壁層と、前記障壁層上に形成されたチャネル層と、前記チャネル層上にヘテロ接合する電子供給層とを備えており、
    　前記ゲート電極は、前記積層体上に前記ソース電極と間隙を持って対向配置されるように形成され、
    　前記ゲート電極に対して、前記ソース電極が対向配置されていない側に、少なくとも前記チャネル層の実質的な表面から、前記障壁層よりも前記窒化物系半導体薄膜側に近い領域までに亘って延在する電子伝導領域を備えていることを特徴とする請求項１乃至６いずれか１項に記載の縦型トランジスタ。     The laminate composed of the nitride-based semiconductor includes a drift layer formed on the nitride-based semiconductor thin film, a barrier layer formed on the drift layer, a channel layer formed on the barrier layer, An electron supply layer heterojunction on the channel layer,
    The gate electrode is formed on the stacked body so as to be opposed to the source electrode with a gap,
    The gate electrode extends to the side where the source electrode is not disposed so as to extend at least from the substantial surface of the channel layer to a region closer to the nitride-based semiconductor thin film side than the barrier layer. The vertical transistor according to claim 1, further comprising an existing electron conduction region.
  8. 　導電性半導体基板上に、導電性酸化膜を形成し、
    　前記導電性酸化膜上に、窒化物系半導体薄膜を形成し、
    　前記窒化物系半導体薄膜の上層に、窒化物系半導体からなる積層体をエピタキシャル成長させ、
    　前記積層体表面にソース電極、又はエミッタ電極を形成し、
    　前記導電性半導体基板裏面にドレイン電極、又はコレクタ電極を形成する縦型トランジスタの製造方法。     Forming a conductive oxide film on a conductive semiconductor substrate;
    Forming a nitride-based semiconductor thin film on the conductive oxide film;
    A laminate composed of a nitride-based semiconductor is epitaxially grown on the nitride-based semiconductor thin film,
    Forming a source electrode or an emitter electrode on the surface of the laminate;
    A method of manufacturing a vertical transistor, wherein a drain electrode or a collector electrode is formed on the back surface of the conductive semiconductor substrate.
  9. 　前記窒化物系半導体薄膜は、前記導電性酸化膜上に、窒化物系半導体バルク結晶を貼り合わせ、
    　前記窒化物系半導体バルク結晶を厚み方向で分割することにより得ることを特徴とする請求項８に記載の縦型トランジスタの製造方法。     The nitride-based semiconductor thin film is bonded to a nitride-based semiconductor bulk crystal on the conductive oxide film,
    The vertical transistor manufacturing method according to claim 8, wherein the nitride-based semiconductor bulk crystal is obtained by dividing the nitride-based semiconductor bulk crystal in a thickness direction.
  10. 　縦型トランジスタが搭載された半導体装置であって、前記縦型トランジスタとして請求項１～７のいずれか１項に記載の縦型トランジスタを備える半導体装置。 A semiconductor device having a vertical transistor mounted thereon, wherein the semiconductor device includes the vertical transistor according to claim 1 as the vertical transistor.
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Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013099424A1 (en) * 2011-12-29 2013-07-04 住友電気工業株式会社 Method for manufacturing silicon carbide semiconductor device
US9184258B2 (en) 2013-09-11 2015-11-10 Kabushiki Kaisha Toshiba GaN based semiconductor device and method of manufacturing the same
US10068986B1 (en) 2017-10-27 2018-09-04 Vanguard International Semiconductor Corporation Enhanced-mode high electron mobility transistor and method for forming the same
TWI637511B (en) * 2017-09-07 2018-10-01 世界先進積體電路股份有限公司 Enhanced-mode high electron mobility transistor and method for forming the same
JP2019096719A (en) * 2017-11-22 2019-06-20 株式会社東芝 Semiconductor device, inverter circuit, driver, vehicle, lift, power supply circuit, and computer
CN110571152A (en) * 2019-08-14 2019-12-13 青岛佳恩半导体有限公司 Preparation method of IGBT back electrode buffer layer
CN113257907A (en) * 2020-02-12 2021-08-13 苏州晶界半导体有限公司 Double-sided structure field effect transistor based on nitride
TWI791835B (en) * 2018-05-31 2023-02-11 新加坡商西拉娜亞洲私人有限公司 High voltage breakdown tapered vertical conduction junction transistor
WO2023123392A1 (en) * 2021-12-31 2023-07-06 Innoscience (Suzhou) Technology Co., Ltd. Nitride-based semiconductor device and method for manufacturing the same

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002241191A (en) * 2001-02-14 2002-08-28 Toyoda Gosei Co Ltd Method for growing semiconductor crystal
WO2005029588A1 (en) * 2003-09-24 2005-03-31 Sanken Electric Co., Ltd. Nitride semiconductor device and method for manufacturing same
JP2007013191A (en) * 2001-11-13 2007-01-18 Matsushita Electric Ind Co Ltd Semiconductor device and method for fabricating the same

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4633962B2 (en) * 2001-05-18 2011-02-16 日亜化学工業株式会社 Manufacturing method of nitride semiconductor substrate
JP2006210660A (en) * 2005-01-28 2006-08-10 Hitachi Cable Ltd Manufacturing method of semiconductor substrate
JP2008112843A (en) * 2006-10-30 2008-05-15 Shin Etsu Chem Co Ltd Process for manufacturing singly crystal silicon solar cell and single crystal silicon solar cell
JP2008251605A (en) * 2007-03-29 2008-10-16 Genelite Inc Manufacturing process of light-emitting element
JP4600576B2 (en) * 2008-05-08 2010-12-15 株式会社デンソー Semiconductor device and manufacturing method thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002241191A (en) * 2001-02-14 2002-08-28 Toyoda Gosei Co Ltd Method for growing semiconductor crystal
JP2007013191A (en) * 2001-11-13 2007-01-18 Matsushita Electric Ind Co Ltd Semiconductor device and method for fabricating the same
WO2005029588A1 (en) * 2003-09-24 2005-03-31 Sanken Electric Co., Ltd. Nitride semiconductor device and method for manufacturing same

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013099424A1 (en) * 2011-12-29 2013-07-04 住友電気工業株式会社 Method for manufacturing silicon carbide semiconductor device
JP2013140857A (en) * 2011-12-29 2013-07-18 Sumitomo Electric Ind Ltd Method of manufacturing silicon carbide semiconductor device
US8728877B2 (en) 2011-12-29 2014-05-20 Sumitomo Electric Industries, Ltd. Method for manufacturing silicon carbide semiconductor device with a single crystal substrate
US9184258B2 (en) 2013-09-11 2015-11-10 Kabushiki Kaisha Toshiba GaN based semiconductor device and method of manufacturing the same
US9466705B2 (en) 2013-09-11 2016-10-11 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
TWI637511B (en) * 2017-09-07 2018-10-01 世界先進積體電路股份有限公司 Enhanced-mode high electron mobility transistor and method for forming the same
US10068986B1 (en) 2017-10-27 2018-09-04 Vanguard International Semiconductor Corporation Enhanced-mode high electron mobility transistor and method for forming the same
JP2019096719A (en) * 2017-11-22 2019-06-20 株式会社東芝 Semiconductor device, inverter circuit, driver, vehicle, lift, power supply circuit, and computer
TWI791835B (en) * 2018-05-31 2023-02-11 新加坡商西拉娜亞洲私人有限公司 High voltage breakdown tapered vertical conduction junction transistor
CN110571152A (en) * 2019-08-14 2019-12-13 青岛佳恩半导体有限公司 Preparation method of IGBT back electrode buffer layer
CN113257907A (en) * 2020-02-12 2021-08-13 苏州晶界半导体有限公司 Double-sided structure field effect transistor based on nitride
WO2023123392A1 (en) * 2021-12-31 2023-07-06 Innoscience (Suzhou) Technology Co., Ltd. Nitride-based semiconductor device and method for manufacturing the same

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