WO2011005447A2

WO2011005447A2 - Semiconductor optical detector structure

Info

Publication number: WO2011005447A2
Application number: PCT/US2010/039007
Authority: WO
Inventors: Joel De Souza; Harold Hovel; Daniel Inns; Jee Kim; Devendra Sadana
Original assignee: International Business Machines Corporation
Priority date: 2009-06-22
Filing date: 2010-06-17
Publication date: 2011-01-13
Also published as: JP2012531048A; CN102804392A; WO2011005447A3; WO2010151478A1

Abstract

A semiconductor is disclosed with a substrate doped with a substrate doping. There is a crystalline semiconductor layer disposed on a front side of the substrate. The crystalline semiconductor layer has a layer doping. The substrate doping changes to the layer doping within a 100 angstrom transition region. In alternative embodiments, the layer doping has novel profiles. In other alternative embodiments, the substrate has a crystalline semiconductor layers disposed on each of a front and a back side of the substrate. Each of the crystalline semiconductor layers has a respective layer doping and each of these layer dopings changes to the substrate doping within a respective transition region less than 100 angstroms thick. In still other embodiments of this invention, an amorphous silicon layer is disposed on a side of the crystalline semiconductor layer opposite the substrate. The amorphous silicon layer has an amorphous doping so that a tunnel junction is formed between the doped crystalline semiconductor layer and the amorphous layer. Manufacturing these structures at below 700 degrees Centigrade enables the narrow transition regions of the structures.

Description

SEMICONDUCTOR OPTICAL DETECTOR STRUCTURE

Cross-Reference to Related Applications

[0001] This applications is related to an application entitled "Method of Making a

Semiconductor Optical Detector Structure" filed by the same inventive entity on the same day as this application and which is herein incorporated by reference in its entirety.

[0002] This application claims priority to provisional patent application serial

number 61/219,131 filed on June 22, 2009 entitled Low Cost, Low Thermal Budget Solar Cells.

Field of the Invention

[0003] This invention relates to a semiconductor optical detector structure. More

specifically, this invention relates to a solar cell structure made at low

temperature.

Background of the Invention

Description of the Prior Art

[0004] Solar cells are a highly promising method for enhancing the world's energy supply. Solar cells based on silicon are the major photovoltaics technology at present. Silicon solar cells can be made starting from semiconductor wafers which may consist of a single crystal or multiple crystal regions (multicrystal). These cells consist of P-N junctions, so called because the have regions of positive conductivity (P -region) and negative conductivity (N region). They also have optical coatings, termed anti-reflection coatings (AR), to minimize the amount of light reflected from the upper surface, and passivating layers required to minimize the amount of photocurrent that would be lost due to surface recombination.

Metal electrodes on the P-region and N-region are used to collect the current and voltage which ensue upon exposure to light. The junction on the side of the solar cell exposed to light is generally termed the emitter junction. Other

embellishments are often used to enhance the performance of the device, such as a P/P junction at the back (unexposed) surface consisting of different amounts of doping, known as a "back surface field," graded doping profiles at the exposed surface to create a front surface field, and "texturing" of the exposed surface to make it rougher to reflect less light along with the AR coatings.

[0005] Silicon solar cells, whether single crystal or multicrystal, are made by

procedures that require high temperatures, generally 850 degrees centigrade or higher. These high temperatures are used to create the P/N junction by diffusion of an n-type producing dopant such as phosphorus into a p-type wafer substrate, or a p-type producing dopant such as boron into an n-type wafer substrate. Other high temperature steps may be included, such as the back surface field formation by diffusion or by alloying of an aluminum layer, and a high temperature alloying step to alloy the metal electrodes to the silicon regions through one or more dielectric layers that form the antireflective coating. A detailed description of many of the process steps used to fabricate silicon solar cells can be found in Nijs et al, " Advanced Manufacturing Concepts for Crystalline Silicon Solar Cells," IEEE Transactions on Electron Devices Vol. 46, page 1948, October 1999 which is herein incorporated by reference.

[0006] Figure 1 shows a solar cell structure 100 made by methods practiced in the prior art. Substrate 105 has created on it a grown region 110 consisting of an interface 125, a doping level 115, and a surface 140. A transition region 130 is formed between the substrate 105 and the grown region 110 where some of the dopant 115 from the grown region 110 may have migrated below interface 125.

[0007] The doping level 115 may be constant or have a doping profile 150 which

may be erfc, Gaussian, constant, or graded. The substrate 105 has a substrate doping 107. The substrate doping 107 is generally constant and in the range of 10¹⁴ cm^"3 to 1017 cm^"3 and of opposite conductivity type as region 110.

[0008] There are several undesirable consequences of high temperature processing.

[0009] One potential consequence is a degradation in the minority carrier lifetime, the time that hole-electron pairs created by sunlight exist in free form before recombining and therefore being lost as power output. Such degradation can occur when heat treatments higher than 900 degrees centigrade are used and may be due to impurity interactions in the silicon wafer. This effect is particularly detrimental to high efficiency solar cells which require the high carrier lifetime to be highly efficient (greater than 20%, for example). The diffusion step used to create the front junction and/or back surface field uses temperatures approaching or exceeding 900 degrees centigrade, for example. The front junction is a P/N junction on the side of the substrate 105 exposed to the illumination and the back surface field is a junction such as the P / P junction described earlier on the rear side of the substrate 105 not exposed to the light.

[0010] A second undesirable consequence of high temperature processing is the

amount of energy required. Diffusion requires large furnaces heated to high temperatures for long times, such that fabricating the cell can take almost as much energy usage as the cell will be able to pay back in its lifetime. Deposition of the AR coatings and the Al alloying on the back, if used, also take up a large amount of energy, contributing to the amount of time needed for the cell to pay back the amount of energy used to create it. This high energy usage also adds considerably to the cost of manufacturing the cells, and supplying this high energy usage may involve burning fossil fuels to create the electricity to run the furnaces, contributing to pollution and problems with climate change.

[0011] The design and processing details of the standard silicon solar cells are

intimately connected to the temperatures required and energy used. One method for making solar cells in the prior art involves ion implantation into one or both silicon surfaces to create the needed doping. A high temperature anneal step is required to remove the damage created in the silicon by the ion bombardment. The resulting dopant profile 150 is known as an error function or complementary error function (erfc), with a peak near the surface 140 and slowly decaying dopant density away from the peak. The doping level is controlled by the amount of incident dopant ions used in the implantation and the implant potential used, normally tens to hundreds of kilovolts. The depth of the dopant profile is also related by the implant potential. The depth, dopant density, dopant profile, anneal temperature, and implant energy are all interrelated and dependent on each other. These interrelations reduce control of emitter parameters such as depth, dopant profile, and density and creates design trade offs in manufacturing.

[0012] Another type of dopant profile 150 is created by diffusion, resulting in a so- called Gaussian profile which looks similar to the erfc profile with a peak below the surface 140 and slowing decreasing density away from the peak. The dopant profile is controlled by the amount of dopant in the dopant source, which may be a gas, liquid, or solid source, the temperature during the diffusion, and the length of time the wafer remains at the high temperature. As in implantation, the dopant density, depth, length of time, and temperature for diffusion are all interrelated and dependent on each other. This causes the same manufacturing implantation problems stated above for the diffusion process.

[0013] A third dopant profile 150 type is a constant, unvarying profile that can be

obtained, for example, by epitaxial growth. The dopant density is controlled by the gas composition and the dopant depth is the thickness of the epitaxial layer. The growth rate of the silicon epitaxy is strongly temperature dependent and may involve even higher temperatures than used in diffusion or ion implantation annealing to obtain acceptable growth rates. Besides a constant dopant profile, a graded profile can be obtained in epitaxial growth by varying the gas composition during the growth. Epitaxial growth requires high temperatures that increase manufacturing costs and energy use.

[0014] The high temperatures involved in epitaxy result in a dopant transition region 130 where the dopant profile 150 extends farther from the surface 140 than the physical interface 125 between the original substrate surface and the grown layer 110. This transition is a result of some amount of dopant diffusing into the substrate 105 during the high temperature steps. This transition region 130 is unavoidable using prior art epitaxy methods and the dopant concentration and depth is related to both the dopant concentration in the epitaxial layer and the temperature and time taken to grow the layer. All these parameters are interrelated and dependent on one another causing the manufacturing limitations stated above for the epitaxial growth process as well. This diffusion and transfer region makes it difficult to create very abrupt junctions where the dopant profile 150 is very abrupt and the abrupt change occurs at the interface 125 with the substrate 105. It also makes it difficult to create a staircase-like dopant profile 150 where the profile consists of multiple abrupt regions of dopant density and thicknesses. The high temperatures involved in the prior art result in "washing out" of the abruptness due to interdiffusion.

[0015] A thick transition region 130 between the intentionally doped layer 110 and the substrate 105 can't be avoided in any of the prior art doping methods - ion implant, diffusion, or epitaxy, due to the high temperatures involved. The most abrupt or thin transition 130 would come from epitaxy, but the diffusion that takes place during growth results in transition regions of several hundreds of Angstroms at a minimum. Diffusion and ion implantation inherently do not have abrupt doping changes since the dopants are deposited over an extended range, so that their transition regions 130 describing their dopant abruptness are even larger than several hundreds of Angstroms.

[0016] Therefore, device designs and structures that suggest or require abrupt changes in doping profiles 150 and/or narrow transition regions 130, for example transition regions 130 with widths less than 100 Angstroms, are precluded by the prior art methods such as epitaxy, diffusion, or ion implantation.

[0017] Another difficulty associated with high temperature processing is that it

precludes the use of foreign substrates. (A foreign substrate is any substrate that is not composed of the material of the layer being grown.) Low cost solar cells generally require low cost foreign substrates such as glass, metal, ceramic, graphite, or plastic. Though silicon films can be produced on such substrates, for example by poly crystalline film growth, the quality of the silicon material is often compromised due to defects, overactive grain boundaries and dislocations, and impurities since the lattice properties of the foreign substrate differ from the growth layer causing unwanted interaction such as cross doping. Metallugical grade silicon can be consider as a foreign substrate and while it is the same material as a silicon grown layer it causes problems due to a high impurity concentration. The same high temperature processes used for single crystal cell fabrication are needed for cell fabrication on these foreign substrates, which further worsens the material quality and lowers the cell efficiency, increases costs, and causes similar design trade offs.

[0018] Moreover, since the major purpose of thin film solar cells is to reduce cost and reduce payback time, the thermal budget involved in producing these cells is of key importance. The thermal budget is defined as the product of time x temperature. The longer the time a device resides at high temperature and/or the higher the temperature, the larger is the thermal budget. Cells made with lower thermal budgets reduce the energy consumed in their manufacture and can minimize or prevent photocarrier lifetime degradation. It is also desirable for thick silicon cells to have low thermal budgets for the reasons stated above.

[0019] One type of silicon solar cell made without ion implantation, diffusion, or

epitaxy is the heterojunction cell known as HIT for "heterojunction with intrinsic" layer. This cell uses plasma enhanced chemical vapor deposition (PECVD) to deposit layers of amorphous silicon on one or both sides of a silicon wafer. These layers remain amorphous throughout the cell fabrication. Some degree of passivation is also provided by the PECVD layers. A layer of transparent conducting oxide (TCO) is deposited on top of the amorphous Si to provide lateral conduction since the amorphous silicon itself has very low conductivity that would degrade the device by adding a large series resistance. PECVD amorphous silicon deposition has a lower thermal budget than epitaxy, diffusion, or implant and anneal, though the required TCOs add to the budget. While these devices can be made at lower temperature, they comprise amorphous regions and TCO to provide conductivity above the amorphous region. [0020] Another type of solar cell incorporating amorphous silicon layers is the tandem junction cell which consists of an amorphous Si solar cell residing on top of a micro -crystalline Si cell and joined electrically and optically by heavily doped regions which act as low resistance tunneling junctions. Though this cell can be made using temperatures less than 900 degrees centigrade, the quality of the tandem junction cell is strongly limited by the poor quality of the microcrystalline portion which has grain sizes much less than 1 micron and often less than 0.1 micron. Thus the efficiency of the tandem junction cell is restricted to values less than about 12%.

Aspects of the Invention

[0021] An aspect of this invention is a low cost semiconductor optical device.

[0022] An aspect of this invention is a low thermal budget semiconductor optical device.

[0023] An aspect of this invention is a solar cell that is low cost and easier and

faster to manufacture.

[0024] An aspect of this invention is a low cost solar cell produced at temperatures less than 700 degrees F.

[0025] An aspect of this invention is an improved solar cell fabricated using a

foreign substrate.

[0026] An aspect of this invention is an improved solar cell device with a

semiconductor substrate with crystalline layers on both sides.

[0027] An aspect of this invention is a tandem junction cell with large grain size

crystalline Si region having average grain sizes larger than 1 micron and efficiency greater than 12%.

[0028] An aspect of this inventions is a silicon solar cell fabricated by a method which uses a low thermal budget, where the maximum temperature is kept low, where foreign substrates can be used if desired, where the efficiency and throughput (number of cells manufactured per unit of time) are kept at acceptable levels, the energy used and payback time are minimized, and the manufacturing cost can be reduced.

Summary of the Invention

[0029] The present invention is a semiconductor with a substrate doped with a

substrate doping. There is a crystalline semiconductor layer disposed on a front side of the substrate. The crystalline semiconductor layer has a layer doping. The substrate doping changes to the layer doping within a 100 angstrom transition region. In alternative embodiments, the layer doping has novel profiles. In other alternative embodiments, the substrate has a crystalline semiconductor layers disposed on each of a front and a back side of the substrate. Each of the crystalline semiconductor layers has a respective layer doping and each of these layer dopings changes to the substrate doping within a respective transition region less than 100 angstroms thick. In still other embodiments of this invention, an amorphous silicon layer is disposed on a side of the crystalline semiconductor layer opposite the substrate. The amorphous silicon layer has an amorphous doping so that a tunnel junction is formed between the doped crystalline semiconductor layer and the amorphous layer. Manufacturing these structures at below 700 degrees Centigrade enables the narrow transition regions of the structures.

Brief Description of the Figures

[0030] Figure 1 is a block diagram of a prior art structure showing a substrate, growth region with an interface, and a transition region.

[0031] Figure 2, comprising Figure 2A (prior art) and novel Figures 2B through 2D, shows various types of doping profiles in the growth region.

[0032] Figure 3 is a block diagram of one preferred structure, with various

alternatives showing two abrupt interfaces, i.e. transition regions with a negligible thickness.

[0033] Figure 4 is a block diagram of an alternate preferred structure showing two abrupt interfaces, i.e. transition regions with a negligible thickness.

[0034] Figure 5 is a flow chart of a preferred process for making a semiconductor optical detector at low temperature.

[0035] Figure 6 is a flow chart of a preferred process for making a semiconductor optical tandem junction structure at low temperature.

[0036] Figure 7 shows the spectral response, and light current- voltage behavior of a low temperature silicon solar cell.

[0037] Figure 8 is a block diagram of a tandem junction structure made by low temperature processing.

Detailed Description of the Invention

[0038] Various device structures are described comprising a semiconductor

substrate. An amorphous semiconductor layer is deposited on a first substrate surface, annealed at a temperature sufficient to crystalize the amorphous layer but equal to or less than 700C. In a preferred embodiment, passivation and antireflective coating layers are deposited at or below 700C as are metal electrodes contacting the semiconductor surfaces, creating a device capable of detecting electromagnetic radiation. The substrate 105 can comprise a single crystal or multicrystal semiconductor wafer or a thin film semiconductor residing on a foreign substrate (material) such as glass, quartz, metal, graphite, plastic, metallurgical grade silicon, or ceramic. In alternate embodiments, the substrate 105 can be silicon, silicon on glass, silicon on sapphire, silicon on quartz, silicon on metal, silicon on graphite, silicon on ceramic, a silicon and Germanium compound, metallurgical grade silicon, and solar grade silicon. In other embodiments, the substrate could be germanium, germanium on glass, germanium on sapphire, germanium on quartz, germanium on metal, germanium on graphite, and germanium on ceramic. The low temperature processes of this disclosure enable this wide diversity of substrates 105 including substrates made of foreign substances.

[0039] The semiconductor layer 110 (optionally 310) can be made of the following materials silicon, germanium, a compound of silicon and germanium, and a compound of silicon and carbon.

[0040] One preferred structure comprises amorphous semiconductor layers

deposited on both opposite sides of a semiconductor substrate 105 and crystallized at temperatures equal or less than 700C, followed by passivation and antireflection layers deposited on one opposite side of the substrate plus crystallized layer, and passivation and reflecting layers deposited on the other opposite side of the substrate plus crystallized layer. Metal electrodes are attached to both opposite sides of the substrate plus crystallized layers at temperatures equal or less than 700C.

[0041] Another preferred embodiment would use RTP (rapid thermal processing) to crystallize the deposited amorphous layers which could elevate the

temperature to 900C for very short periods such that the thermal budget is still minimized.

[0042] The structure resulting from the low temperature, low thermal budget

procedure has a transition region 130 much thinner than the prior art structures. The transition region is generally less than or equal to 100

Angstroms. Likewise, various doping profile 150, e.g., stepped doping, are easily accomplished in the structure since diffusion of the dopants after the doped layer deposition is negligible. Doping profiles 150 can be created to provide beneficial electric fields in the grown region 110 which aid in current collection.

[0043] Figure 2 shows various alternative embodiment (Figures 2 A through 2D) where the region 110 is shown more closely and where the surface 140 lies to the left, the interface 125 (the surface of the substrate 105 before the growth region 110 is applied) and transition region 130 lie toward the right.

[0044] Profile 160 in Figure 2 A is typical of prior art erfc or Gaussian profiles.

[0045] The profiles 162, 164 and 166 of Figures 2B, 2C, and 2D, respectively, represent profiles that are difficult or impossible to create in the prior art without dopant penetration to create a transition region 130 larger than 100 Angstroms. The profile 162 of Figure 2B is a step profile that has one or more abrupt changes in doping level between the surface 140 and the interface 125. The profile 164 of Figure 2C is a constant doping profile. The profile 166 of Figure 2D represents a graded profile.

[0046] This invention affords the flexibility to create these and other profiles since the profiles can be created in the amorphous silicon deposition. The created profiles (e.g., 162, 164, and 166) are maintained in the low temperature processing step. The invention provides a flexibility of profile design choice not provided by the prior art.

[0047] Figure 3 is a block diagram of a novel low thermal budget silicon cell

structure 300. Substrate 105 is a semiconductor with a substrate doping 107 and has recrystallized regions 110 and 310 on front 126 and back 326 surfaces (e.g. opposite sides) at front interface 125 and back interface 325, respectively. The front doped crystalline semiconductor layer 110 has a front layer doping 115 and the back doped crystalline semiconductor layer 310 has a back layer doping 315. In this embodiment, the front doped crystalline semiconductor layer 110 represents the emitter and the back doped crystalline semiconductor layer 310 represents the back surface field region of the device 300. The transition regions 330 (front) and 340 (back) are insignificantly thin for the low temperature cells 300 of the invention and can be made with thickness less than 100 angstroms because there is limited diffusion of dopant at the lower temperature processing step(s) 500.

[0048] A front passivating layer 360 resides on silicon surface 140 and AR coating 370 resides on top of the front passivating layer 360. The front passivating layer 360 and AR coating 370 are deposited by any well known methods such as chemical vapor deposition (CVD), evaporation, sputtering, spray coating, or other equivalent deposition methods.

[0049] Electrodes 350 reside at the front silicon surface 140 and electrode 380

resides on the back silicon surface (side) 390 of the back doped crystalline semiconductor layer 310. The back silicon surface (side) 390 is the side of the back doped crystalline semiconductor layer 310 opposite the back interface 325. The electrodes 350 and 380 are attached using known methods, e.g., plating, evaporation, sputtering or other equivalents.

[0050] Figure 4 shows a low thermal budget silicon cell 400 with a patterned back contact (355, 380) for higher cell efficiency. Back passivating layer 465 resides on the back silicon surface 390. Back electrodes 355 are fabricated through back passivating layer 465 using known techniques and electrically contact back silicon surface (side) 390. Back metallization layer 380 electrically contacts the electrodes 355 and also serves as a back surface reflecting layer to reflect some of the light penetrating throughout the silicon volume 450 back into the silicon instead of being lost.

[0051] Structures in Figure 4 with the same number as in Figure 3 are the same structures. The transition regions 330 and 340 are insignificantly thin for the low temperature cells (300, 400) of the invention and can be made with thickness less than 100 angstroms because there is limited diffusion of dopant at the lower temperature processing step(s) 500.

[0052] Figure 5 shows one preferred process 500 flow for fabricating low

temperature silicon cells in accordance with the invention.

[0053] Silicon solar cells can be made by depositing (510, optionally 515)

amorphous silicon onto silicon substrates (105, 505), preferably substrates of low cost, by low temperature processes such as evaporation or PECVD. Both the emitter 110 and optional back surface field (back doped crystalline semiconductor layer) 310 can be made by these low temperature processes. Unlike the prior art, the thickness, doping level, and deposition temperature are all independent and can be controlled as desired, including providing graded doping, step function doping, and other doping profiles as possible efficiency enhancements. See the doping profile description of Figure 2 above. This is accomplished because all steps in the process 500 are performed at temperatures less than or equal to 700 degrees Centigrade therefore the initial doping levels will be maintained. After growth/deposition of the amorphous silicon, these films are "crystallized" 520 by either an anneal at a low temperature (550 - 700C) and short time, for example 30 minutes to 6 hours, or by RTP (rapid thermal processing) 520 for seconds to minutes, for example, 30 seconds to 90 seconds. This creates a device (300, 400) with a crystalline structure since all amorphous material has been converted to crystalline layers (110 and 310).

[0054] Passivation (525, optionally 530) can be provided at low temperature by anodic oxidation or by PECVD of thin amorphous Si (aSi) wth Hydrogen (aSi:H) or other known processes. If there are two sides of the structure (300, 400) to be passivated, a front 525 and a back 530 passivation step are performed.

[0055] Antireflective coatings can be provided 535 by spin-on dielectrics such as TiO2, SiO2, and low temperature glass or other known materials. Spin-on techniques are known.

[0056] Opening for contacts are made 540. Contacts can be made 545 by

evaporation or preferably metal plating and/or screen printing. Other known methods can be used. The result is an all low-temperature solar cell made with a low thermal budget that comprises a crystalline structure.

[0057] In step 505 of Figure 5, the process 500 begins with a semiconductor

substrate 105 such as glass, metal, ceramic, graphite, metallurgical grade silicon, plastic, or any other known substrate material.

[0058] More preferred Si substrates 105 are chosen which could be solar grade multicrystalline, single crystalline, UMG (upgraded metallurgical grade), ribbon Si, thin film Si, or other. The substrate could be p-type or n-type. The substrate 105 may also consist of silicon-germanium alloy regions on glass, metal, graphite, ceramic, plastic, silicon, or any other substrate material. [0059] In step 510 a layer (growth layer 110) of doped amorphous semiconductor, e.g. silicon, carbon doped silicon, germanium, silicon - germanium

compounds, is deposited on the front surface of the substrate 105. The doped amorphous semiconductor is provided with a doping level and doping profile that can be any profile required by the device designer. Profiles are created in amorphous material by known methods such as changing gas composition, temperature variations, etc.

[0060] In step 515, a second amorphous semiconductor (e.g, silicon, carbon doped silicon, germanium, silicon - germanium compounds) layer (to become layer 310) is deposited on the back surface with a back layer doping level 315 and profile. Again the invention allows these profiles to be designed in the amorphous material using known techniques and maintained by the novel low temperature process. For example, for evaporated films, a dopant can be co- evaporated simultaneously with the amorphous semiconductor. For gaseous growth of the amorphous semiconductor, a dopant gas can be mixed to provide the desired dopant profiler

[0061 ] A front layer 110 of amorphous silicon is deposited 510 with an opposite conductivity type to the substrate 105 to act as the emitter. A back layer (after the crystallization step, layer 310) of amorphous silicon is optionally deposited 515 of the same conductivity type to the substrate 105 to act as the BSF (back surface field). The layers (to become layers 110, 310, respectively) can be deposited by evaporation, PECVD, plating, or other acceptable process. The thickness of each layer is chosen as desired, and the doping levels are chosen as desired. One preferred device type has the emitter and BSF on opposite sides of the substrate. Another preferred device type has both emitter and BSF deposited on the same side of the substrate ("Inter digitated Front surface Cell or" Interdigitated Back surface Cell").

[0062] The layers are deposited at a low temperature, 200 - 300C typical. In a preferred embodiment the doping gas is modulated during the deposition to provide differences in doping levels throughout the layer, providing high-low junctions for the "double emitter" approach where a higher doping level is provided just under the future electrical contacts, or a graded doping level which provides, for example, a built-in electric field to improve efficiency. The double emitter device structure is especially valuable in minimizing the photocarrier loss (hole-electron pairs created by incident radiation) while also minimizing the contact resistance.

[0063] In step 520, the amorphous silicon layers (aSi) are transformed to

crystallization by annealing at a temperature of 700 degrees centigrade or less. In this step, regions 110 and 310 in Figure 3 and 110 and 310 in Figure 4 are transformed from an amorphous state to a crystalline state. Since this transformation occurs at low temperature, the profiles implemented in these regions in steps 510 and 515 do not change. In this step a more preferred temperature range is between 400 and 600 degree centigrade.

[0064] In the anneal step 520 the substrate 105 acts as the seed for the

crystallization. Single crystal substrates 105 result in single crystal layers (110, 310) and polycrystalline substrates 105 result in poly layers, though poly layers can also be obtained on single crystal substrates 105 under some anneal conditions if desired. The anneal is usually carried out at temperatures of 400C to 700C for minutes to several hours; however, Rapid Thermal

Processing which takes the substrate and deposited films to high temperatures above 900C for a few seconds could also be used, while still providing a low thermal budget.

[0065] In step 525, a low temperature passivation is provided by known anodic oxidation or PECVD deposition or spin coating. Other known methods may be applicable only if they can be used at these low temperatures.

[0066] In step 530, an optional back surface passivation is provided with oxide or PECVD layers as described above for front surface passivation. Other methods may be applicable only if they can be used at these low temperatures.

[0067] Surface passivation (front 525 and optionally back 530) on either or both front and back surfaces can be provided by several techniques. In one method, a low temperature anodic oxidation is carried out in chemical solution by applying a bias between the cell and a counter electrode. In another approach, PECVD amorphous silicon with hydrogen is deposited to satisfy dangling bonds and lower surface recombination velocity. This amorphous Si region remains amorphous and acts as the passivating layer and not part of the emitter or back surface field junctions. In a third approach, thin films such as A12O3, silicon nitride, silicon dioxide, or HfO2 are deposited by one of several methods such as atomic layer deposition (ALD), evaporation, low pressure chemical vapor deposition (LPCVD), or PECVD. The passivating film can be thin, 10 nm for example, to satisfy the passivation function.

[0068] Antireflection coatings can be added in step 535 be several known methods - evaporation, sputtering, spray-coating, spin coating, PECVD, LPCVD. A particularly advantageous method is to spray on or spin on the AR coating materials followed by a low temperature anneal. For example, layers of TiO2, SiO2, "Low-K" material, and others can be spun-on and annealed at 200- 300C. The film thicknesses are controlled by the spin or spray conditions. Silicon nitride can also be deposited by low temperature processes such as PECVD and LPCVD. Other methods may be applicable only if they can be used at these low temperatures.

[0069] In step 540, a pattern is opened in the front and back surfaces for example by etching, laser ablation, or other known low temperature techniques in the positions where the metal electrodes (350, 355) will be located.

[0070] Patterning 540 can be employed to create desirable efficiency-enhancing structures. For example, a double emitter whereby a heavily doped region exists beneath the electrical contacts and more lightly doped emitter regions apply outside the contacts can be produced by etching off the heavily doped regions using the contact metal as a mask. A local back surface field (BSF) can be produced on the cell bottom by either a patterned deposition of the heavily doped amorphous silicon or etching the amorphous silicon from in between the metal contacts and applying a passivating layer in between. The metal layer covering the entire back then contacts the local electrodes while serving to reflect some of the light penetrating the entire silicon volume back into the silicon. Crystallization of the deposited doped amorphous silicon can be carried out either before or after patterning.

[0071] In step 545, the electrodes (350, 355) are deposited by a low temperature process such as evaporation, screen printing, or laser printing or other known low temperature (below 700 degrees Centigrade, more preferably less the 600 degrees centigrade) techniques.

[0072] Electrodes (350, 355) can be fabricated by evaporation, sputtering, screen printing, or plating, with the last two methods likely to be the lowest cost. A pattern can be etched in the surface coatings to reach the silicon surface. Etching can be done by, for example, wet chemical etch, RIE (reactive ion etch) or plasma etch. The metal electrode (350, 355) can then be deposited. Since the solar cell is functional at this stage, plating can be carried out by light-induced plating if desired. Some metals such as Ni could be deposited by electroless plating also. Light induced plating, normally involving copper plating, is carried out by immersing the solar cell in a copper sulfate solution and exposing it to light. The voltage and current generated by the solar cell itself result in copper deposition on the metal electrodes.

[0073] The low temperature process 500, e.g. used for silicon solar cells, can also be applied to thin silicon films situated on lower cost foreign substrates such as glass, ceramic, graphite, plastic, or metal. After creating the silicon film on the foreign substrate, by direct deposition such as CVD or layer transfer in which a thin silicon region is removed from a silicon substrate and transferred onto the foreign substrate, the processes of low temperature amorphous silicon deposition 510, crystallization 520, passivation 525, AR coating 535, and metallization 545 can all be carried out at temperatures of 700 degrees centigrade or less and generally at 600 degrees centigrade or less, resulting in a low cost, low thermal budget thin film silicon cell with high quality silicon material.

[0074] Similarly, silicon films can be deposited on alternate substrates 105 such as silicon on sapphire, silicon on quartz, silicon on germanium. Silicon can also be deposited onto hybrid substrates 105 such as germanium on metal, germanium on ceramic, germanium on glass, germanium on graphite, germanium on quartz, germanium on sapphire, or germanium on plastics such as polyimide which can withstand temperatures up to nearly 600⁰C. The deposited films may themselves be alloys with other elements, for example, amorphous silicon-germanium compounds or amorphous silicon containing carbon. In all cases, the concept which facilitates these flexibilities and opportunities are that devices are subsequently fabricated by low temperature, low thermal budget processes.

[0075] The amorphous Si films can be deposited by, for example, PECVD or

evaporation of Si in evaporator systems with suitably low base pressure to prevent silicon oxide formation. [0076] Figure 7 shows the results of a silicon solar cell 300 made 500 in accordance with the invention. The process flow 500 for this device (called a CMA-F Cell M3) includes a 10 ohm-cm p-type substrate wafer (505, 105), deposition 510 of heavily doped 0.8 μm thick e-beam deposited n-type layer (1E19 cm-3) amorphous silicon by evaporation on one side of the wafer, deposition 515 of heavily doped p-type 3 μm thick e-beam p-type layer (1E19 cm-3) amorphous silicon by evaporation onto the opposite side, crystallization 520 by annealing at 600⁰C, anodic oxidation for passivation 525 carried out at 25⁰C, PECVD of silicon nitride 535 at 25O⁰C, and metallization by metal evaporation (540, 545). In addition a copper plating was used to increase the thickness of the metal electrodes 350. The resulting cell is a back surface field silicon cell created with all steps in the process 500 with the temperatures in all process steps being less than or equal to 600⁰C.

[0077] The spectral response (internal quantum efficiency, IQE, versus wavelength) is indicated by 720. The graph 720 shows the number of charge carriers collected per incident photon over an incident wavelength of light between 300 and 1100 nanometers.

[0078] Graph 730 is a plot of the illuminated current-voltage behavior of the cell of graph 720. The cell was exposed to 1 sun of illumination intensity and provided a current density of nearly 35 milliamperes per centimeter over a range of output voltages between 0 and 0.35 volts.

[0079] The silicon cell has an efficiency (electrical power out of the device divided by solar power into the device) of 12.5%.

[0080] Figure 8 is a block diagram of a tandem junction crystalline silicon /

amorphous silicon device 800 made by low temperature processing 600 in accordance with the present invention. Refer also to process in Figure 600. An amorphous silicon region (to be crystallized into region 810 is deposited 610 on a suitable substrate 805 (step 605) by any known low temperature process 610 and recrystallized 620 at temperatures less than 700 degrees centigrade and preferably less than 600 degrees centigrade. The recrystallized region 810 has a grain size of 1 micron or larger. An amorphous silicon region is then deposited 630 on recrystallized region 810. (This is similar to step 515 except instead of depositing on a back surface, the amorphous semiconductor is deposited on recrystallized region 810.) A desired doping profile is incorporated in regions 810 and 820 to result in a connecting tunnel junction 830 is created 630. Regions 810 and 820 contain p-doped regions and n-doped regions to result in a crystalline silicon solar cell and an

amorphous silicon solar cell connected 630 by tunnel junction 830.

Passivating layers, anti-reflection coatings, and metal electrodes (not shown) are then applied 640 by methods described hereinabove.

Claims

Claims We claim:

1. A semiconductor structure comprising;

a semiconductor substrate with a substrate doping; and

a doped crystalline semiconductor layer with a layer doping, the doped crystalline semiconductor layer being disposed on a front surface of the semiconductor substrate at a front interface, where the substrate doping changes to the layer doping within a 100 angstrom transition region.

2. A structure, as in claim 1, where the layer doping has a doping profile.

3. A structure as in claim 1, where doping profile is any one or more of the following: a constant profile, a graded profile, a stepped profile.

4. A structure, as in claim 2, where the doping profile is a stepped profile with one or more thickness, each thickness having a thickness doping.

5. A structure, as in claim 1, where the substrate is one or more of the following materials: silicon, silicon on glass, silicon on sapphire, silicon on quartz, silicon on metal, silicon on graphite, silicon on ceramic, a silicon and germanium compound, metallurgical grade silicon, solar grade silicon, germanium, germanium on glass, germanium on sapphire, germanium on quartz, germanium on metal, germanium on graphite, and germanium on ceramic, glass, metal, ceramic, graphite, and plastic.

6. A structure, as in claim 1, where the doped crystalline semiconductor layer is one or more of the following materials: silicon, germanium, a compound silicon and germanium, and a compound of silicon and carbon.

7. A structure, as in claim 1, where the doped crystalline semiconductor layer is a single crystal layer.

8. A structure, as in claim 1, where the doped crystalline semiconductor layer is a poly crystal layer.

9. A semiconductor structure comprising;

a semiconductor substrate with a substrate doping, having a front substrate side, and a back substrate side;

a front doped crystalline semiconductor layer with a front layer doping, the front doped crystalline semiconductor layer being disposed on the semiconductor substrate on a front interface at the front substrate side, where the substrate doping changes to the front layer doping within 100 angstroms of the front interface and there is a desired doping profile across the thickness of the front doped crystalline

semiconductor layer; and a back doped crystalline semiconductor layer with a back layer doping, the back doped crystalline semiconductor layer being disposed on the semiconductor substrate on a back interface at the back substrate side, where the substrate layer doping changes to the back layer doping within 100 angstroms of the back interface.

10. A structure as in claim 9, where the substrate is one or more of the following materials: silicon, silicon on glass, silicon on sapphire, silicon on quartz, silicon on metal, silicon on graphite, silicon on ceramic, a silicon and germanium compound, metallurgical grade silicon, solar grade silicon, germanium, germanium on glass, germanium on sapphire, germanium on quartz, germanium on metal, germanium on graphite, and germanium on ceramic, glass, metal, ceramic, graphite, and plastic.

11. A structure, as in claim 9, where the front doped crystalline semiconductor layer is one or more of the following materials: silicon, germanium, a compound silicon and germanium, and a compound of silicon and carbon.

12. A structure, as in claim 9, where the back doped crystalline semiconductor layer is one or more of the following materials: silicon, germanium, a compound silicon and germanium, and a compound of silicon and carbon.

13. A structure, as in claim 9, further comprising a back contact electrode on a bottom side of the back doped crystalline semiconductor layer opposite the back interface and a front contact on a top side opposite the front interface of the front doped crystalline semiconductor layer.

14. A structure, as in claim 13, further comprising a front passivation layer disposed on the front doped crystalline semiconductor layer.

15. A structure, as in claim 14, further comprising an anti reflection coating disposed over the front passivation layer.

16. A structure, as in claim 13, further comprising a reflective coating disposed on the back doped crystalline semiconductor layer.

17. A structure, as in claim 13, where the back contact electrode is patterned.

18. A structure, as in claim 17, where a back passivating layer resides on the back doped crystalline semiconductor layer and the back contact electrode passes through the back passivating layer to electrically contact the back doped crystalline semiconductor layer.

19. A structure, as in claim 18, where the back contact electrode back reflects light.

20. A structure, as in claim 9, where the front doped crystalline semiconductor layer is one of the following: a single crystal layer and a poly crystal layer.

21. A structure, as in claim 9, where the back doped crystalline semiconductor layer is one of the following: a single crystal layer and a poly crystal layer.

22. A structure, as in claim 1, where the grain size of the doped crystalline semiconductor layer is greater than 1 micron.

23. A structure, as in claim 1, further comprising: an amorphous silicon layer disposed upon the doped crystalline semiconductor layer on an amorphous side of the doped crystalline semiconductor layer opposite the substrate, the amorphous silicon layer having an amorphous doping, the layer doping and the amorphous doping being at levels so that a tunnel junction is formed between the doped crystalline semiconductor layer and the amorphous layer.

24. A structure, as in claim 23, where the grain size of the doped crystalline semiconductor layer is greater than 1 micron.

25. A structure, as in claim 23, where the grain size of the amorphous silicon layer is greater than 1 micron.

26. A semiconductor structure comprising; a semiconductor substrate means with a substrate doping; and

a doped crystalline semiconductor layer means with a layer doping, the doped crystalline semiconductor layer being disposed on a front surface of the

semiconductor substrate at a front interface, where the substrate doping changes to the layer doping within a 100 angstrom transition region.