WO2010150488A1 - Power supply protection circuit and motor drive device provided with same - Google Patents

Power supply protection circuit and motor drive device provided with same Download PDF

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Publication number
WO2010150488A1
WO2010150488A1 PCT/JP2010/003992 JP2010003992W WO2010150488A1 WO 2010150488 A1 WO2010150488 A1 WO 2010150488A1 JP 2010003992 W JP2010003992 W JP 2010003992W WO 2010150488 A1 WO2010150488 A1 WO 2010150488A1
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WIPO (PCT)
Prior art keywords
voltage
transistor
power supply
protection circuit
power
Prior art date
Application number
PCT/JP2010/003992
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French (fr)
Japanese (ja)
Inventor
磯田峰明
鴨木豊
岸本憲一
Original Assignee
パナソニック株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by パナソニック株式会社 filed Critical パナソニック株式会社
Priority to CN201080028192.7A priority Critical patent/CN102804538B/en
Priority to JP2011519560A priority patent/JP5590031B2/en
Publication of WO2010150488A1 publication Critical patent/WO2010150488A1/en

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/0029—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries with safety or protection devices or circuits
    • H02J7/0031—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries with safety or protection devices or circuits using battery or load disconnect circuits
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/001—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection limiting speed of change of electric quantities, e.g. soft switching on or off

Definitions

  • the present invention relates to a power supply protection circuit that protects a power supply and circuit components connected to the power supply from an overcurrent, and a motor drive device including the same.
  • the conventional method of suppressing inrush current disclosed in Patent Document 1 includes a main switch that electrically connects a power source to the load side, and an auxiliary switch that is connected between the power source and the load side via a current limiting resistor.
  • the detection means for detecting the voltage on the load side and the control means for controlling these switches are provided. When the voltage drop on the load side is detected by the detection means, the control means turns off the main switch and turns on the auxiliary switch. When the detection means detects that the voltage on the load side has increased, the control means turns on the main switch and turns off the auxiliary switch.
  • the conventional method for preventing the inrush current as described above has a configuration in which a control means such as a microcomputer switches the switch, so it is necessary to control a relay as a switch through the control wiring, and the wiring is routed.
  • a control means such as a microcomputer switches the switch
  • a relay as a switch through the control wiring, and the wiring is routed.
  • the configuration uses a switch or a relay that utilizes contact or non-contact of a mechanical contact, for example, compared to a non-contact switch made of semiconductor, there are problems such as poor contact and longevity that reduce reliability. there were.
  • mechanical switches and relays have problems such as difficulty in miniaturization compared to semiconductors.
  • the present invention has been made to solve such a problem, and a power supply protection circuit capable of improving reliability with a simple configuration for power supply protection and circuit protection, and a motor drive including the same Providing equipment.
  • the power supply protection circuit of the present invention is a power supply protection circuit in which a DC power supply is connected to an input terminal having a positive voltage with respect to the ground terminal, and DC power is output from the output terminal, between the input terminal and the output terminal.
  • a current suppression unit provided; and a transistor having a source and drain connected in parallel with the current suppression unit.
  • the power protection circuit of the present invention applies a ground terminal voltage to the gate of the transistor when the output terminal voltage exceeds a predetermined voltage, and applies to the transistor gate when the output terminal voltage is lower than the predetermined voltage.
  • a switching control circuit for applying a voltage at the input terminal, and the transistor is a P-channel transistor.
  • the voltage at the output terminal is low at the moment when a positive voltage is supplied from the DC power supply to the input terminal, so that the voltage at the input terminal is applied to the gate of the transistor. That is, the voltage between the source and gate of the transistor is almost zero, and the transistor is turned off. As a result, a current flows from the input end to the output end via the current suppression unit, so that the current is output for a while from the moment the positive voltage is supplied.
  • the voltage at the output end increases, the voltage at the ground end is applied to the gate of the transistor. That is, the gate voltage with respect to the source of the transistor is a negative voltage, and the transistor is P-channel, so that the transistor is turned on. As a result, a current flows from the input terminal to the output terminal via the source and drain of the transistor, and DC power is supplied to the load in a state where the current is not suppressed.
  • the power supply protection circuit of the present invention uses a transistor, which is a semiconductor element, instead of a conventional mechanical switch or relay, so that it can be downsized and improved in reliability. Can be planned.
  • this transistor is a P-channel transistor, the transistor can be turned on and off by simple control such that the voltage at the ground end or the voltage at the input end is switched and applied to the gate.
  • the control of the transistor connected in parallel to the current suppression unit can also be configured with a simple circuit without a microcomputer or the like, and can be arranged together with the current suppression unit and the transistor, for example, on the same printed circuit board. Accordingly, there is no need for long wiring and the number of components can be reduced, so that occurrence of poor contact can be suppressed, and as a result, reliability can be improved.
  • the power supply protection circuit includes a voltage detector in which the switching control circuit detects the voltage at the output terminal and outputs a switching signal based on the detected voltage, and the voltage at the input terminal and the ground according to the switching signal.
  • a switching circuit that selects one of the end voltages and supplies the selected voltage to the gate of the transistor.
  • the switch circuit is configured to select the voltage at the ground terminal when the voltage at the output terminal exceeds a predetermined voltage, and to select the voltage at the input terminal when the voltage at the output terminal is lower than the predetermined voltage.
  • the voltage at the output terminal becomes high, the voltage at the ground terminal is output from the switch circuit and supplied to the gate of the transistor. That is, the gate voltage with respect to the source of the transistor is a negative voltage, and the transistor is turned on. As a result, a current flows from the input end to the output end via the source and drain of the transistor.
  • the switching control circuit can be configured with a very simple circuit, the reliability can be improved.
  • a semiconductor switch element as the switch circuit, it is possible to prevent contact failure and increase the life compared to a configuration using a mechanical switch or relay. Reliability can be increased.
  • the switching control circuit when the above-described transistor is the first transistor, the switching control circuit has a PNP in which the emitter is connected to the input terminal and the collector is connected to the ground via the first resistor.
  • the switching control circuit can be configured with a very simple circuit, the reliability can be improved.
  • the power supply protection circuit of this invention is the structure which used the current suppression part as the resistor.
  • the current suppression unit may be a constant current source circuit that outputs a constant current.
  • the current suppression unit may be a series circuit of a resistor and a fuse.
  • the power source protection circuit of the present invention is a power source protection circuit in which a DC power source is connected to an input terminal having a negative voltage with respect to the ground terminal, and DC power is output from the output terminal. And a transistor having a source and a drain connected in parallel with the current suppressing unit. Furthermore, when the absolute value of the output terminal voltage exceeds a predetermined voltage, the power supply protection circuit of the present invention applies a ground terminal voltage to the gate of the transistor, and the absolute value of the output terminal voltage is lower than the predetermined voltage. And a switching control circuit for applying a voltage at the input terminal to the gate of the transistor, and the transistor is an N-channel transistor. With such a configuration, a power source protection circuit against a negative voltage that can improve reliability with a simple configuration can be realized.
  • the power source protection circuit of the present invention is a power source protection circuit in which a DC power source is connected to an input terminal having a positive voltage with respect to the ground terminal, and DC power is output from the output terminal.
  • a first transistor having a source-drain connected in between, an emitter connected to an input terminal, a PNP-type second transistor connected to a ground terminal via a first resistor, and an anode output And a diode having a cathode connected to the ground end via a second resistor.
  • the power supply protection circuit of the present invention has a configuration in which the base of the second transistor is connected to the cathode of the diode, and the collector of the second transistor is connected to the gate of the first transistor. With such a configuration, when an abnormality such as a short circuit occurs in the load, the first transistor operates to cut off the abnormal overcurrent, so that the load and the power source can be protected from the abnormal overcurrent. .
  • the motor drive device of the present invention is configured to include the power supply protection circuit and an inverter that operates with DC power supplied via the power supply protection circuit, and to drive the motor by the inverter. With such a configuration, a motor driving device having a highly reliable power supply protection function can be realized.
  • the power supply protection function can be realized with a small number of parts using a semiconductor element, and therefore, it is possible to provide a power supply protection circuit capable of improving reliability with a simple configuration. Moreover, according to the motor drive device of the present invention, since such a power supply protection circuit is provided, it is possible to provide a motor drive device that can improve reliability with a simple configuration.
  • FIG. 1 is a block diagram of a power protection circuit according to Embodiment 1 of the present invention.
  • FIG. 2 is a characteristic diagram of a transistor of the power supply protection circuit in the same embodiment.
  • FIG. 3 is a diagram showing an operation waveform of each part of the power supply protection circuit in the same embodiment.
  • FIG. 4 is a circuit diagram of a power supply protection circuit in the same embodiment.
  • FIG. 5 is an operation explanatory diagram of the switching control circuit of the power protection circuit in the same embodiment.
  • FIG. 6 is a block diagram showing another configuration example of the power protection circuit in the same embodiment.
  • FIG. 7 is a block diagram showing another configuration example of the power protection circuit in the same embodiment.
  • FIG. 8 is a block diagram of the motor drive device according to Embodiment 2 of the present invention.
  • FIG. 1 is a block diagram of a power protection circuit 10 according to Embodiment 1 of the present invention.
  • the power protection circuit 10 is disposed between the DC power supply 50 and the load L.
  • the load L is an electric circuit, an electronic circuit, or the like that is operated by electric power supplied from the DC power supply 50, and will be described as the load L here.
  • DC power is normally supplied directly from the DC power supply 50 to the load L.
  • the DC power supply 50 is connected via the power protection circuit 10. In this configuration, DC power is supplied to the load L.
  • the power supply protection circuit 10 suppresses the inrush current from the DC power supply 50 to the load L side. Further, even when an abnormality such as a short circuit occurs in the load L and an overcurrent flows, the power supply protection circuit 10 acts to suppress this overcurrent, so that the load L and the DC power supply 50 are destroyed by the overcurrent. Can be prevented.
  • DC power is supplied from the DC power supply 50 to the input terminal VI to the power supply protection circuit 10 with the ground terminal GND as the ground.
  • the ground side that is a 0 (V) reference voltage of the DC power supply 50 is connected to the ground terminal GND, and the positive voltage side that is a DC voltage Vc that is a positive voltage with respect to this reference voltage is connected to the input terminal VI.
  • FIG. 1 shows an example in which an electrolytic capacitor Cl is connected so as to be parallel to the load L. Such an electrolytic capacitor Cl is normally connected to the load L in this way in order to remove ripples and noise included in the supply voltage from the DC power supply 50.
  • the power supply protection circuit 10 includes a current suppression resistor Rp as a current suppression unit, a transistor Q1 serving as a first transistor, and a switching control circuit 20.
  • the current suppression resistor Rp is provided between the input terminal VI and the output terminal VO.
  • the source and drain of the transistor Q1 are connected in parallel with the current suppressing resistor Rp. That is, the source S of the transistor Q1 is connected to the input terminal VI, and the drain D of the transistor Q1 is connected to the output terminal VO.
  • the transistor Q1 functions as a switch that performs electrical connection / disconnection, that is, on / off, between the input terminal VI and the output terminal VO. The on / off state of the transistor Q1 is switched based on the gate voltage of the transistor Q1.
  • the switching control circuit 20 includes a voltage detector 21 and a switch circuit 22.
  • the voltage detector 21 detects the voltage of the output terminal VO and outputs a switching signal Ssw based on the detected voltage.
  • the switch circuit 22 selects either the voltage at the input terminal VI or the voltage at the ground terminal GND according to the switching signal Ssw, and supplies the selected voltage to the gate G of the transistor Q1. At this time, the switch circuit 22 selects the voltage of the ground terminal GND when the voltage of the output terminal VO exceeds a predetermined voltage by the switching signal Ssw, and inputs the voltage when the voltage of the output terminal VO is lower than the predetermined voltage. Select the voltage at end VI.
  • the switching control circuit 20 applies the voltage of the ground terminal GND to the gate G of the transistor Q1 when the voltage of the output terminal VO exceeds a predetermined voltage. Further, the switching control circuit 20 applies the voltage of the input terminal VI to the gate G of the transistor Q1 when the voltage of the output terminal VO is lower than a predetermined voltage.
  • the transistor Q1 is a P-channel transistor. More specifically, for example, it is a P-channel MOS type field effect transistor (FET).
  • FET field effect transistor
  • FIG. 2 is a characteristic diagram of the transistor Q1 of the power supply protection circuit 10 according to the first embodiment of the present invention.
  • FIG. 2 shows an example of the characteristics of the drain current Id with respect to the gate-source voltage Vgs of the P-channel transistor.
  • the transistor Q1 is used as a switch for switching between a closed state and an open state based on such characteristics.
  • the switch 51 of the DC power supply 50 when the switch 51 of the DC power supply 50 is turned on and DC power is supplied from the DC power supply 50 to the load L via the power supply protection circuit 10 configured as described above, at least the current is supplied from the moment of supply. A direct current flows into the electrolytic capacitor Cl through the suppression resistor Rp. For this reason, the voltage of the output terminal VO becomes lower as the voltage of the output terminal VO is closer to the ground terminal GND. Therefore, the voltage at the input terminal VI is output from the switch circuit 22 and supplied to the gate G of the transistor Q1. Thereby, the voltage of the source S connected to the input terminal VI and the voltage of the gate G become substantially equal. That is, the gate-source voltage Vgs of the transistor Q1 is substantially 0 (V).
  • the voltage detector 21 determines that the predetermined voltage has been exceeded, and switches the switch circuit 22 so as to select the voltage at the ground terminal GND. From the switch circuit 22, the voltage at the ground terminal GND is output and supplied to the gate G of the transistor Q1.
  • a positive voltage is supplied to the source S of the transistor Q1 connected to the input terminal VI.
  • the voltage of the gate G that is the voltage of the ground terminal GND is a negative voltage with respect to the source S. That is, since the gate-source voltage Vgs becomes the voltage Von shown in FIG.
  • the drain current Id flows, and the source-drain of the transistor Q1 is turned on, that is, closed.
  • a current flows from the input terminal VI to the output terminal VO via the source and drain of the transistor Q1, and the DC power is supplied to the load L in a state where the current is not suppressed.
  • the transistor Q1 is preferably a transistor with low on-resistance.
  • FIG. 3 is a diagram showing operation waveforms of the power supply protection circuit 10 according to the first embodiment of the present invention.
  • FIG. 3 shows a state in which DC power is supplied from the DC power supply 50 at time T0 and then the voltage at the output terminal VO is stabilized.
  • the switching control circuit 20 determines that the voltage at the output terminal VO is lower than the predetermined voltage Vth, and applies the voltage at the input terminal VI to the gate G of the transistor Q1. Then, as shown in FIG. 3, the voltage Vgs of the gate G with respect to the source S becomes substantially 0 (V).
  • the source and drain of the transistor Q1 are in a high resistance state, and the source and drain are equivalent to an off state. Therefore, a state in which a direct current flows from the input terminal VI into the electrolytic capacitor Cl only through the current suppression resistor Rp continues. During this time, as shown in FIG. 3, the voltage at the output terminal VO gradually increases.
  • the switching control circuit 20 applies the voltage at the ground terminal GND to the gate G of the transistor Q1. Accordingly, the voltage Vgs of the gate G with respect to the source S becomes a negative voltage, so that the low resistance state is established between the source and drain of the transistor Q1, and the source and drain are equivalent to the on state. That is, DC power is output from the output terminal VO in a state equivalent to the direct connection between the input terminal VI and the output terminal VO.
  • the power supply protection circuit 10 supplies power in a current-suppressed state after the DC power supply 50 is turned on until the voltage at the output terminal VO becomes close to the supply voltage Vc.
  • An excessive current such as an inrush current flowing into the capacitor Cl can be suppressed.
  • the switching control circuit 20 applies the voltage at the input terminal VI to the gate G of the transistor Q1 to turn off the transistor Q1. For this reason, electric power is supplied from the DC power supply 50 to the load L side only through the current suppression resistor Rp.
  • the current suppression resistor Rp can suppress an excessive current flow to the load L side, and can prevent the load L and the DC power supply 50 from being destroyed or abnormal heat generation of the load L.
  • the power supply protection circuit 10 uses the transistor Q1, which is a semiconductor element, and can be reduced in size.
  • the transistor Q1 is a P-channel transistor.
  • the transistor Q1 can be turned on / off by simple control such as switching between the voltage at the ground terminal GND or the voltage at the input terminal VI and applying the desired protection to the gate G. Functions can be realized.
  • the power protection circuit 10 that transmits the positive voltage to the load L can be configured as a simple circuit, and is controlled together with the current suppression resistor Rp and the transistor Q1 such as the switching control circuit 20 on the same printed circuit board. Circuits can also be placed. Further, it is easy to integrate the transistor Q1 and the switching control circuit 20 into one IC.
  • FIG. 4 is a circuit diagram of the power supply protection circuit 10 according to the first embodiment of the present invention.
  • the switching control circuit 30 includes a transistor Q2 serving as a second transistor, a diode D1, a first resistor R1, and a second resistor R2.
  • the transistor Q2 is a PNP type bipolar transistor.
  • the emitter E of the transistor Q2 is connected to the input terminal VI.
  • the collector C of the transistor Q2 is connected to the ground terminal GND through the resistor R1.
  • the transistor Q2 is used as a switching element, and the emitter-collector is turned on and off based on the voltage applied between the emitter base of the transistor Q2. As a result, either the voltage at the ground terminal GND or the voltage at the input terminal VI is output from the collector C of the transistor Q2.
  • the anode A of the diode D1 is connected to the output terminal VO.
  • the cathode K of the diode D1 is connected to the ground terminal GND through the resistor R2.
  • the diode D1 is provided to generate a voltage used for switching the transistor Q2.
  • the diode D1 also serves to prevent an input current from flowing from the input terminal VI to the output terminal VO via the emitter E and base B of the transistor Q2.
  • the base B of the transistor Q2 is connected to the cathode K of the diode D1, and the collector C of the transistor Q2 is connected to the gate G of the transistor Q1.
  • FIG. 5 is an operation explanatory diagram of the switching control circuit 30 of the power protection circuit 10 according to the first embodiment of the present invention. Next, the operation of the switching control circuit 30 configured as described above and the power supply protection circuit 10 including the switching control circuit 30 will be described with reference to FIGS. 4 and 5.
  • the voltage at the output terminal VO is substantially the voltage at the ground terminal GND. That is, the voltage of the base B with respect to the emitter E of the transistor Q2 increases in the negative voltage direction. Therefore, a base current flows from the emitter E of the transistor Q2 connected to the input terminal VI to the ground terminal GND through the base B and the resistor R2. As a result, the transistor Q2 is turned on, and the collector C of the transistor Q2 is almost at the voltage of the input terminal VI. This voltage is applied to the gate G of the transistor Q1. Since the voltage Vgs between the gate and source of the transistor Q1 is almost 0 (V), the transistor Q1 is turned off. As a result, a current flows from the input terminal VI to the output terminal VO only through the current suppression resistor Rp.
  • FIG. 5 shows the voltage applied to the base B with the voltage of the emitter E as a reference.
  • the voltage is constant because the voltage is based on the emitter E.
  • the ground terminal GND is used as a reference, the voltage of the emitter E is naturally the voltage of the input terminal VI.
  • FIG. 5 shows a state in which a positive voltage is supplied from the DC power supply 50 to the input terminal VI at time T0.
  • FIG. 5 shows the voltage Vbe between the emitter and base of the transistor Q2. When a voltage that exceeds the emitter-base voltage Vbe in the negative direction is applied, the transistor Q2 is turned on.
  • the voltage applied to the base B of the transistor Q2 at this time is as follows.
  • a voltage Vtd obtained by adding the voltage Vd between both ends of the diode D1 to the voltage Vsd between the source and drain of the transistor Q1 is applied to the base B.
  • the transistor Q1 is preferably a transistor having a low on-resistance, a voltage close to the voltage Vd across the diode D1 is applied to the base B.
  • the base current does not flow through the transistor Q2, the voltage between the emitter E and the base B becomes the applied voltage Vtd, approximately the voltage Vd across the diode D1.
  • the voltage between the emitter E and the base B is a voltage Vb as shown by the solid line in FIG.
  • a voltage Vd slightly lower than the voltage Vbe is continuously applied between the emitter E and the base B by the diode D1.
  • the switching characteristic of the transistor Q1 becomes a desired characteristic by appropriately selecting the diode type of the diode of the on voltage Vd as the diode D1 with respect to the voltage Vbe that determines the on / off of the transistor Q2. Can be set easily.
  • the power supply protection circuit 10 supplies DC power so that current gradually flows to the electrolytic capacitor Cl and the load L via the current suppression resistor Rp from the time when DC power is supplied from the DC power supply 50. Inrush current that becomes a large current can be suppressed. Further, for example, even when a failure such as a short circuit of the electrolytic capacitor Cl occurs, the protection function works to detect a voltage abnormality of the output terminal VO and supply a direct current through the current suppression resistor Rp. Therefore, it is possible to protect the load L and the DC power supply 50 of the supply source from an overcurrent due to the above.
  • the power protection circuit of the present invention includes a current suppression unit provided between an input end and an output end, and a transistor having a source and drain connected in parallel with the current suppression unit. Further, the power protection circuit of the present invention applies a ground terminal voltage to the gate of the transistor when the output terminal voltage exceeds a predetermined voltage, and applies to the transistor gate when the output terminal voltage is lower than the predetermined voltage. And a switching control circuit for applying a voltage at the input terminal, and the transistor is a P-channel transistor. For this reason, it is possible to reduce the size and improve the reliability by using the transistor, which is a semiconductor element, instead of the conventional mechanical switch or relay.
  • this transistor is a P-channel transistor, the transistor can be turned on and off by simple control such as switching between the voltage at the ground end and the voltage at the input end to the gate. A protection function can be realized.
  • the control of the transistor connected in parallel to the current suppression unit can also be configured with a simple circuit without a microcomputer or the like, and can be arranged together with the current suppression unit and the transistor, for example, on the same printed circuit board.
  • there is no need for long wiring and the number of parts can be small, so that occurrence of poor contact can be suppressed, and as a result, reliability can be improved.
  • the reliability can be further improved. Therefore, according to the power protection circuit of the present invention, it is possible to provide a power protection circuit capable of improving reliability with a simple configuration.
  • FIG. 6 is a block diagram showing a power supply protection circuit 11 as another configuration example of the power supply protection circuit according to the first embodiment of the present invention.
  • FIG. 6 shows an example in which a constant current source circuit Dp is used as such a current suppressing unit.
  • the current suppression resistor Rp for example, a large amount of current flows into the electrolytic capacitor Cl when the power is turned on, and the amount of current decreases as time elapses.
  • the current suppressing effect at the time of turning on the power is reduced, and it takes time to switch to the transistor Q1.
  • the current suppressing unit is a constant current source circuit
  • the charging current to the electrolytic capacitor Cl can be constant, so that the amount of current when the power is turned on can be suppressed and the time for switching to the transistor Q1 can be shortened.
  • the current suppression unit may be a circuit in which a current suppression resistor Rp and a temperature interrupting fuse, for example, are connected in series.
  • FIG. 7 is a block diagram showing a power supply protection circuit 12 as still another configuration example of the power supply protection circuit according to the first embodiment of the present invention.
  • FIG. 7 shows an example in which such a current suppression unit is a series circuit of a current suppression resistor Rp and a fuse Fp. With such a configuration, when an inrush current or an overcurrent occurs, power supply can be interrupted by the fuse Fp.
  • the power protection circuit when a positive voltage is supplied has been described.
  • a negative voltage it can be realized by the following configuration. That is, a current suppression unit provided between an input terminal and an output terminal to which a negative voltage is supplied, a transistor whose source and drain are connected in parallel with the current suppression unit, and an absolute value of the voltage at the output terminal is a predetermined value
  • a switching control circuit that applies a voltage at the ground end to the gate of the transistor when exceeding the voltage, and applies a voltage at the input end to the gate of the transistor when the absolute value of the voltage at the output end is lower than a predetermined voltage.
  • This transistor is an N-channel transistor.
  • the configuration example in which power is supplied via the current suppression unit and the load and the power source are protected from overcurrent when the power is turned on or when an abnormality such as a load short circuit is described.
  • the protection function can be realized even if the configuration is not provided. That is, a power supply protection circuit in which a DC power source is connected to an input terminal having a positive voltage with respect to the ground terminal and DC power is output from the output terminal.
  • the power protection circuit is connected to, for example, an input terminal and an output terminal.
  • a first transistor having a source-drain connected in between, an emitter connected to an input terminal, a PNP-type second transistor connected to a ground terminal via a first resistor, and an anode output And a diode having a cathode connected to the ground end via a second resistor, a base of the second transistor connected to the cathode of the diode, and a collector of the second transistor serving as the first transistor It is good also as a structure connected to this gate. Even if the power supply protection circuit has such a configuration, if an abnormality such as a short circuit occurs in the load, the first transistor operates so as to cut off an abnormal overcurrent. While improving reliability, it is possible to protect the load and power supply from abnormal overcurrent.
  • FIG. 8 is a block diagram of motor drive device 100 according to Embodiment 2 of the present invention.
  • the motor drive device 100 includes the power supply protection circuit 10 described in the first embodiment and an inverter 60 for driving the motor 70.
  • the inverter 60 is supplied with DC power via the power protection circuit 10.
  • the motor drive device 100 includes the power supply protection circuit 10 with improved reliability, the motor drive device of the present invention provides a motor drive device that can improve reliability with a simple configuration. can do.
  • the power supply protection circuit 11 or the power supply protection circuit 12 may be used instead of the power supply protection circuit 10.
  • the power protection circuit of the present invention and the motor driving device including the power protection circuit can provide a highly reliable power protection function with a simple configuration.
  • a vehicle-mounted electric device or a vehicle that requires high reliability is used. It is useful for a motor drive device that drives a motor for electric appliances, and other electric devices and motor drive devices for home appliances and industrial use.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Emergency Protection Circuit Devices (AREA)
  • Protection Of Static Devices (AREA)

Abstract

Disclosed is a power supply protection circuit which is provided with: a current suppressing resistor (Rp) provided between an input terminal (VI) and an output terminal (VO); a transistor (Q1) wherein the source and the drain are connected in parallel to the current suppressing resistor (Rp) as a current suppressing section; and a switch control circuit (20), which applies the voltage of an ground terminal (GND) to the gate (G) of the transistor (Q1) when the voltage of the output terminal (VO) exceeds a predetermined voltage, and applies the voltage of the input terminal (VI) to the gate (G) of the transistor (Q1) when the voltage of the output terminal (VO) is lower than the predetermined voltage. The transistor (Q1) can be turned on and off only by means of simple control by having a P-channel transistor as the transistor (Q1).

Description

電源保護回路およびそれを備えたモータ駆動装置Power supply protection circuit and motor drive device including the same
　本発明は、過電流から電源やその電源に接続される回路部品などを保護する電源保護回路およびそれを備えたモータ駆動装置に関する。 The present invention relates to a power supply protection circuit that protects a power supply and circuit components connected to the power supply from an overcurrent, and a motor drive device including the same.
　従来、このような保護機能を実現する手法として、例えば、電源からの突入電流を抑制し、回路部品の破壊防止を図るような技術が提案されている。特許文献１に開示された従来の突入電流を抑制する方式は、電源を負荷側に電気接続するメインスイッチと、電源と負荷側との間に電流制限抵抗器を介して接続される補助スイッチと、負荷側の電圧を検出する検出手段と、これらスイッチを制御する制御手段とを設けた構成としている。そして、検出手段により負荷側の電圧低下を検出すると、制御手段は、メインスイッチをオフにし、補助スイッチをオンにする。また、検出手段により負荷側の電圧が高くなったのを検出すると、制御手段は、メインスイッチをオンにし、補助スイッチをオフにする。このような動作を行うことによって、例えば、電源が立ち上がったとき、まず、電流制限抵抗器を介して電力が負荷に供給され、負荷側の電解コンデンサに充電されることになる。そして、電解コンデンサの電圧が十分に高くなると、メインスイッチを介して電力が負荷に供給される。すなわち、電解コンデンサの電圧は十分に高くなっているので電解コンデンサに充電する充電電流の量は過大とならず、従来、このような突入電流抑制の方式によって回路部品の破壊などを防止していた。 Conventionally, as a technique for realizing such a protection function, for example, a technique has been proposed in which inrush current from a power source is suppressed to prevent destruction of circuit components. The conventional method of suppressing inrush current disclosed in Patent Document 1 includes a main switch that electrically connects a power source to the load side, and an auxiliary switch that is connected between the power source and the load side via a current limiting resistor. The detection means for detecting the voltage on the load side and the control means for controlling these switches are provided. When the voltage drop on the load side is detected by the detection means, the control means turns off the main switch and turns on the auxiliary switch. When the detection means detects that the voltage on the load side has increased, the control means turns on the main switch and turns off the auxiliary switch. By performing such an operation, for example, when the power supply is turned on, first, power is supplied to the load via the current limiting resistor, and the electrolytic capacitor on the load side is charged. Then, when the voltage of the electrolytic capacitor becomes sufficiently high, power is supplied to the load via the main switch. In other words, since the voltage of the electrolytic capacitor is sufficiently high, the amount of charging current charged in the electrolytic capacitor is not excessive, and conventionally, the destruction of circuit components has been prevented by such an inrush current suppression method. .
　しかしながら、上述したような従来の突入電流を防止する方式は、マイコンなどの制御手段がスイッチを切り替える構成であったため、制御用配線を介してスイッチとしてのリレーなどを制御する必要があり、配線引き回しなどによって信頼性が低下するなどの課題があった。また、機械的接点の接触、非接触を利用したスイッチやリレーを用いた構成であったため、例えば半導体による非接触スイッチに比べて、接触不良や寿命など、これらによっても信頼性が低下する課題があった。さらに、このような機械式のスイッチやリレーは、半導体に比べて小型化が難しいなどの課題もあった。 However, the conventional method for preventing the inrush current as described above has a configuration in which a control means such as a microcomputer switches the switch, so it is necessary to control a relay as a switch through the control wiring, and the wiring is routed. There was a problem such as a decrease in reliability. In addition, since the configuration uses a switch or a relay that utilizes contact or non-contact of a mechanical contact, for example, compared to a non-contact switch made of semiconductor, there are problems such as poor contact and longevity that reduce reliability. there were. Furthermore, such mechanical switches and relays have problems such as difficulty in miniaturization compared to semiconductors.
特開平２－２３１９２２号公報JP-A-2-231922
　本発明は、このような課題を解決するためになされたものであり、電源保護や回路保護に対して、簡易な構成で信頼性の向上を可能とした電源保護回路およびそれを備えたモータ駆動装置を提供する。 The present invention has been made to solve such a problem, and a power supply protection circuit capable of improving reliability with a simple configuration for power supply protection and circuit protection, and a motor drive including the same Providing equipment.
　本発明の電源保護回路は、グランド端に対して正電圧となる入力端に直流電源が接続され、出力端から直流電力を出力する電源保護回路であって、入力端と出力端との間に設けた電流抑制部と、電流抑制部と並列にソースドレイン間が接続されたトランジスタとを備える。さらに本発明の電源保護回路は、出力端の電圧が所定の電圧を超えるとき、トランジスタのゲートにグランド端の電圧を印加し、出力端の電圧が所定の電圧よりも低いとき、トランジスタのゲートに入力端の電圧を印加する切替制御回路とを備え、トランジスタをＰチャンネル型トランジスタとした構成である。 The power supply protection circuit of the present invention is a power supply protection circuit in which a DC power supply is connected to an input terminal having a positive voltage with respect to the ground terminal, and DC power is output from the output terminal, between the input terminal and the output terminal. A current suppression unit provided; and a transistor having a source and drain connected in parallel with the current suppression unit. Further, the power protection circuit of the present invention applies a ground terminal voltage to the gate of the transistor when the output terminal voltage exceeds a predetermined voltage, and applies to the transistor gate when the output terminal voltage is lower than the predetermined voltage. And a switching control circuit for applying a voltage at the input terminal, and the transistor is a P-channel transistor.
　このような構成により、入力端に直流電源から正電圧が供給された瞬間は出力端の電圧が低いため、トランジスタのゲートに入力端の電圧が印加される。すなわち、トランジスタのソースゲート間の電圧はほぼゼロとなり、トランジスタはオフとなる。これによって、入力端から出力端へは、電流抑制部を介して電流が流れることになるため、正電圧を供給した瞬間からしばらくは、電流を抑制した状態で出力することになる。 With such a configuration, the voltage at the output terminal is low at the moment when a positive voltage is supplied from the DC power supply to the input terminal, so that the voltage at the input terminal is applied to the gate of the transistor. That is, the voltage between the source and gate of the transistor is almost zero, and the transistor is turned off. As a result, a current flows from the input end to the output end via the current suppression unit, so that the current is output for a while from the moment the positive voltage is supplied.
　この後、出力端の電圧が高くなると、トランジスタのゲートにはグランド端の電圧が印加される。すなわち、トランジスタのソースに対するゲート電圧は負電圧となり、トランジスタはＰチャンネル型であるため、トランジスタはオンとなる。これによって、入力端から出力端へは、トランジスタのソースドレイン間を介して、電流が流れることになり、負荷には電流抑制されないような状態で直流電力が供給される。 After this, when the voltage at the output end increases, the voltage at the ground end is applied to the gate of the transistor. That is, the gate voltage with respect to the source of the transistor is a negative voltage, and the transistor is P-channel, so that the transistor is turned on. As a result, a current flows from the input terminal to the output terminal via the source and drain of the transistor, and DC power is supplied to the load in a state where the current is not suppressed.
　また、本発明の電源保護回路は、従来の機械式のスイッチやリレーに代えて、このように半導体素子であるトランジスタを利用しているため、小型化を図ることができ、信頼性の向上を図ることができる。そして、特に、このトランジスタをＰチャンネル型トランジスタとしているため、ゲートに対して、単にグランド端の電圧か入力端の電圧かを切り替えて印加するような簡易な制御のみで、このトランジスタをオンオフできる。このため、電流抑制部に並列に接続するトランジスタの制御も、マイコンなど必要なく簡易な回路で構成でき、電流抑制部やトランジスタとともに、例えば同一のプリント基板上などに配置できる。よって、長い配線引き回しなど必要なく、部品点数も少なくてよいため接触不良などの発生も抑制でき、その結果、信頼性の向上を図ることが可能となる。 In addition, the power supply protection circuit of the present invention uses a transistor, which is a semiconductor element, instead of a conventional mechanical switch or relay, so that it can be downsized and improved in reliability. Can be planned. In particular, since this transistor is a P-channel transistor, the transistor can be turned on and off by simple control such that the voltage at the ground end or the voltage at the input end is switched and applied to the gate. For this reason, the control of the transistor connected in parallel to the current suppression unit can also be configured with a simple circuit without a microcomputer or the like, and can be arranged together with the current suppression unit and the transistor, for example, on the same printed circuit board. Accordingly, there is no need for long wiring and the number of components can be reduced, so that occurrence of poor contact can be suppressed, and as a result, reliability can be improved.
　また、本発明の電源保護回路は、切替制御回路が、出力端の電圧を検出し、検出した電圧に基づく切替信号を出力する電圧検出器と、切替信号に応じて、入力端の電圧とグランド端の電圧とのいずれかを選択し、選択した電圧をトランジスタのゲートに供給するスイッチ回路とを備える。そして、スイッチ回路は、出力端の電圧が所定の電圧を超えるとき、グランド端の電圧を選択し、出力端の電圧が所定の電圧よりも低いとき、入力端の電圧を選択する構成である。 The power supply protection circuit according to the present invention includes a voltage detector in which the switching control circuit detects the voltage at the output terminal and outputs a switching signal based on the detected voltage, and the voltage at the input terminal and the ground according to the switching signal. A switching circuit that selects one of the end voltages and supplies the selected voltage to the gate of the transistor. The switch circuit is configured to select the voltage at the ground terminal when the voltage at the output terminal exceeds a predetermined voltage, and to select the voltage at the input terminal when the voltage at the output terminal is lower than the predetermined voltage.
　このような構成により、入力端に直流電源から正電圧が供給された瞬間は出力端の電圧が低いため、スイッチ回路から入力端の電圧が出力され、トランジスタのゲートに供給される。すなわち、トランジスタのソースゲート間の電圧はほぼゼロとなり、トランジスタはオフとなる。これによって、入力端から出力端へは、電流抑制部を介して電流が流れる。 With such a configuration, since the voltage at the output end is low at the moment when a positive voltage is supplied from the DC power supply to the input end, the voltage at the input end is output from the switch circuit and supplied to the gate of the transistor. That is, the voltage between the source and gate of the transistor is almost zero, and the transistor is turned off. As a result, a current flows from the input end to the output end via the current suppressing unit.
　この後、出力端の電圧が高くなると、スイッチ回路からグランド端の電圧が出力され、トランジスタのゲートに供給される。すなわち、トランジスタのソースに対するゲート電圧は負電圧となり、トランジスタはオンとなる。これによって、入力端から出力端へは、トランジスタのソースドレイン間を介して、電流が流れる。 After this, when the voltage at the output terminal becomes high, the voltage at the ground terminal is output from the switch circuit and supplied to the gate of the transistor. That is, the gate voltage with respect to the source of the transistor is a negative voltage, and the transistor is turned on. As a result, a current flows from the input end to the output end via the source and drain of the transistor.
　このように、切替制御回路は、非常に簡易な回路で構成できるため、信頼性の向上を図ることが可能となる。また、スイッチ回路として、半導体のスイッチ素子を用いた構成とすることにより、機械式のスイッチやリレーを用いた構成に比べて、接触不良を防止や高寿命化を図ることができ、これによっても信頼性を高めることができる。 Thus, since the switching control circuit can be configured with a very simple circuit, the reliability can be improved. In addition, by using a semiconductor switch element as the switch circuit, it is possible to prevent contact failure and increase the life compared to a configuration using a mechanical switch or relay. Reliability can be increased.
　また、本発明の電源保護回路は、上述のトランジスタを第１のトランジスタとしたとき、切替制御回路が、エミッタを入力端に接続し、コレクタを第１の抵抗器を介してグランドに接続したＰＮＰ型の第２のトランジスタと、アノードを出力端に接続し、カソードを第２の抵抗器を介してグランド端に接続したダイオードとを備える。そして、第２のトランジスタのベースをダイオードのカソードに接続し、第２のトランジスタのコレクタを第１のトランジスタのゲートに接続した構成である。 In the power protection circuit of the present invention, when the above-described transistor is the first transistor, the switching control circuit has a PNP in which the emitter is connected to the input terminal and the collector is connected to the ground via the first resistor. A second transistor of the type, and a diode having an anode connected to the output terminal and a cathode connected to the ground terminal via a second resistor. The base of the second transistor is connected to the cathode of the diode, and the collector of the second transistor is connected to the gate of the first transistor.
　このような構成により、入力端に直流電源から正電圧が供給された瞬間は、出力端の電圧が低いため、入力端の第２のトランジスタのエミッタからベースおよび第２の抵抗器を介してグランド端へとベース電流が流れる。このため、第２のトランジスタはオン状態となり、第２のトランジスタのコレクタは、ほぼ入力端の電圧となる。この電圧が第１のトランジスタのゲートに印加される。すなわち、第１のトランジスタのソースゲート間の電圧は、ほぼゼロとなるため、第１のトランジスタはオフとなる。これによって、入力端から出力端へは、電流抑制部を介して電流が流れる。 With such a configuration, at the moment when a positive voltage is supplied to the input terminal from the DC power supply, the voltage at the output terminal is low, so the emitter of the second transistor at the input terminal is grounded via the base and the second resistor. Base current flows to the end. Therefore, the second transistor is turned on, and the collector of the second transistor is almost at the voltage at the input end. This voltage is applied to the gate of the first transistor. That is, since the voltage between the source and gate of the first transistor is almost zero, the first transistor is turned off. As a result, a current flows from the input end to the output end via the current suppressing unit.
　この後、出力端の電圧が高くなると、第２のトランジスタのエミッタとダイオードのカソードとの間の電圧が小さくなり、ベース電流が流れなくなって、第２のトランジスタはオフ状態となる。そして、第１のトランジスタのゲートにはグランド端の電圧が印加される。すなわち、第１のトランジスタのソースに対するゲート電圧は負電圧となり、第１のトランジスタはオンとなる。これによって、入力端から出力端へは、第１のトランジスタのソースドレイン間を介して、電流が流れることになる。 Thereafter, when the voltage at the output terminal increases, the voltage between the emitter of the second transistor and the cathode of the diode decreases, the base current stops flowing, and the second transistor is turned off. A voltage at the ground end is applied to the gate of the first transistor. That is, the gate voltage with respect to the source of the first transistor is a negative voltage, and the first transistor is turned on. As a result, a current flows from the input end to the output end via the source and drain of the first transistor.
　このように、切替制御回路は、非常に簡易な回路で構成できるため、信頼性の向上を図ることが可能となる。また、本発明の電源保護回路は、電流抑制部を、抵抗器とした構成である。また、本発明の電源保護回路は、電流抑制部を、一定の電流を出力する定電流源回路としてもよい。また、本発明の電源保護回路は、電流抑制部を、抵抗器とヒューズとの直列回路としてもよい。このような構成により、電源投入時や負荷短絡のような異常時には、このような電流抑制部を介して電源供給するため、過電流による負荷や電源の破壊などを防止できる。 Thus, since the switching control circuit can be configured with a very simple circuit, the reliability can be improved. Moreover, the power supply protection circuit of this invention is the structure which used the current suppression part as the resistor. In the power protection circuit of the present invention, the current suppression unit may be a constant current source circuit that outputs a constant current. In the power supply protection circuit of the present invention, the current suppression unit may be a series circuit of a resistor and a fuse. With such a configuration, since power is supplied via such a current suppressing unit when power is turned on or when an abnormality such as a load short-circuit occurs, it is possible to prevent damage to the load or power due to overcurrent.
　また、本発明の電源保護回路は、グランド端に対して負電圧となる入力端に直流電源が接続され、出力端から直流電力を出力する電源保護回路であって、入力端と出力端との間に設けた電流抑制部と、電流抑制部と並列にソースドレイン間が接続されたトランジスタとを備える。さらに本発明の電源保護回路は、出力端の電圧の絶対値が所定の電圧を超えるとき、トランジスタのゲートにグランド端の電圧を印加し、出力端の電圧の絶対値が所定の電圧よりも低いとき、トランジスタのゲートに入力端の電圧を印加する切替制御回路とを備え、トランジスタをＮチャンネル型トランジスタとした構成である。このような構成により、簡易な構成で信頼性の向上を可能とした負電圧に対する電源保護回路も実現できる。 The power source protection circuit of the present invention is a power source protection circuit in which a DC power source is connected to an input terminal having a negative voltage with respect to the ground terminal, and DC power is output from the output terminal. And a transistor having a source and a drain connected in parallel with the current suppressing unit. Furthermore, when the absolute value of the output terminal voltage exceeds a predetermined voltage, the power supply protection circuit of the present invention applies a ground terminal voltage to the gate of the transistor, and the absolute value of the output terminal voltage is lower than the predetermined voltage. And a switching control circuit for applying a voltage at the input terminal to the gate of the transistor, and the transistor is an N-channel transistor. With such a configuration, a power source protection circuit against a negative voltage that can improve reliability with a simple configuration can be realized.
　また、本発明の電源保護回路は、グランド端に対して正電圧となる入力端に直流電源が接続され、出力端から直流電力を出力する電源保護回路であって、入力端と出力端との間にソースドレイン間が接続された第１のトランジスタと、エミッタを入力端に接続し、コレクタを第１の抵抗器を介してグランド端に接続したＰＮＰ型の第２のトランジスタと、アノードを出力端に接続し、カソードを第２の抵抗器を介してグランド端に接続したダイオードとを備える。さらに本発明の電源保護回路は、第２のトランジスタのベースをダイオードのカソードに接続し、第２のトランジスタのコレクタを第１のトランジスタのゲートに接続した構成である。このような構成により、負荷に短絡のような異常が生じた場合、第１のトランジスタは異常な過電流を遮断するように動作するため、異常な過電流から負荷や電源を保護することができる。 The power source protection circuit of the present invention is a power source protection circuit in which a DC power source is connected to an input terminal having a positive voltage with respect to the ground terminal, and DC power is output from the output terminal. A first transistor having a source-drain connected in between, an emitter connected to an input terminal, a PNP-type second transistor connected to a ground terminal via a first resistor, and an anode output And a diode having a cathode connected to the ground end via a second resistor. Furthermore, the power supply protection circuit of the present invention has a configuration in which the base of the second transistor is connected to the cathode of the diode, and the collector of the second transistor is connected to the gate of the first transistor. With such a configuration, when an abnormality such as a short circuit occurs in the load, the first transistor operates to cut off the abnormal overcurrent, so that the load and the power source can be protected from the abnormal overcurrent. .
　また、本発明のモータ駆動装置は、上記電源保護回路と、電源保護回路を介して供給された直流電力により動作するインバータとを備え、インバータによりモータを駆動する構成である。このような構成により、高い信頼性の電源保護機能を有したモータ駆動装置を実現できる。 Also, the motor drive device of the present invention is configured to include the power supply protection circuit and an inverter that operates with DC power supplied via the power supply protection circuit, and to drive the motor by the inverter. With such a configuration, a motor driving device having a highly reliable power supply protection function can be realized.
　本発明の電源保護回路によれば、半導体素子を利用したわずかな部品点数で、電源保護機能を実現できるため、簡易な構成で信頼性の向上を可能とした電源保護回路を提供することができる。また、本発明のモータ駆動装置によれば、このような電源保護回路を備えるため、簡易な構成で信頼性の向上を可能としたモータ駆動装置を提供することができる。 According to the power supply protection circuit of the present invention, the power supply protection function can be realized with a small number of parts using a semiconductor element, and therefore, it is possible to provide a power supply protection circuit capable of improving reliability with a simple configuration. . Moreover, according to the motor drive device of the present invention, since such a power supply protection circuit is provided, it is possible to provide a motor drive device that can improve reliability with a simple configuration.
図１は、本発明の実施の形態１における電源保護回路のブロック図である。FIG. 1 is a block diagram of a power protection circuit according to Embodiment 1 of the present invention. 図２は、同実施の形態における、電源保護回路のトランジスタの特性図である。FIG. 2 is a characteristic diagram of a transistor of the power supply protection circuit in the same embodiment. 図３は、同実施の形態における、電源保護回路の各部の動作波形を示す図である。FIG. 3 is a diagram showing an operation waveform of each part of the power supply protection circuit in the same embodiment. 図４は、同実施の形態における、電源保護回路の回路図である。FIG. 4 is a circuit diagram of a power supply protection circuit in the same embodiment. 図５は、同実施の形態における、電源保護回路の切替制御回路の動作説明図である。FIG. 5 is an operation explanatory diagram of the switching control circuit of the power protection circuit in the same embodiment. 図６は、同実施の形態における、電源保護回路の他の構成例を示すブロック図である。FIG. 6 is a block diagram showing another configuration example of the power protection circuit in the same embodiment. 図７は、同実施の形態における、電源保護回路の他の構成例を示すブロック図である。FIG. 7 is a block diagram showing another configuration example of the power protection circuit in the same embodiment. 図８は、本発明の実施の形態２におけるモータ駆動装置のブロック図である。FIG. 8 is a block diagram of the motor drive device according to Embodiment 2 of the present invention.
　以下、本発明の実施の形態における電源保護回路およびそれを備えたモータ駆動装置について図面を参照しながら説明する。 Hereinafter, a power supply protection circuit and a motor driving apparatus including the same according to an embodiment of the present invention will be described with reference to the drawings.
　（実施の形態１）
　図１は、本発明の実施の形態１における電源保護回路１０のブロック図である。図１に示すように、電源保護回路１０は、直流電源５０と負荷Ｌ間に配置される。負荷Ｌは直流電源５０から供給された電力によって動作する電気回路や電子回路などであり、ここでは負荷Ｌとして説明する。このような負荷Ｌに電源を供給する場合、通常、直流電源５０から負荷Ｌに対して直接に直流電力を供給するが、本実施の形態では、電源保護回路１０を介して、直流電源５０から負荷Ｌに直流電力を供給する構成である。本実施の形態では、このような構成とすることにより、電源保護回路１０によって直流電源５０から負荷Ｌ側への突入電流を抑制している。また、負荷Ｌにおいてショートのような異常が発生し、過電流が流れた場合も、電源保護回路１０はこの過電流を抑制するように作用するため、過電流による負荷Ｌや直流電源５０の破壊などを防止できる。 (Embodiment 1)
FIG. 1 is a block diagram of a power protection circuit 10 according to Embodiment 1 of the present invention. As shown in FIG. 1, the power protection circuit 10 is disposed between the DC power supply 50 and the load L. The load L is an electric circuit, an electronic circuit, or the like that is operated by electric power supplied from the DC power supply 50, and will be described as the load L here. When power is supplied to such a load L, DC power is normally supplied directly from the DC power supply 50 to the load L. In the present embodiment, the DC power supply 50 is connected via the power protection circuit 10. In this configuration, DC power is supplied to the load L. In the present embodiment, by adopting such a configuration, the power supply protection circuit 10 suppresses the inrush current from the DC power supply 50 to the load L side. Further, even when an abnormality such as a short circuit occurs in the load L and an overcurrent flows, the power supply protection circuit 10 acts to suppress this overcurrent, so that the load L and the DC power supply 50 are destroyed by the overcurrent. Can be prevented.
　電源保護回路１０には、直流電源５０からグランド端ＧＮＤをグランドとして、入力端ＶＩに直流電力が供給される。直流電源５０の０（Ｖ）の基準電圧となるグランド側がグランド端ＧＮＤに接続され、この基準電圧に対して正電圧の直流電圧Ｖｃとなる正電圧側が入力端ＶＩに接続される。 DC power is supplied from the DC power supply 50 to the input terminal VI to the power supply protection circuit 10 with the ground terminal GND as the ground. The ground side that is a 0 (V) reference voltage of the DC power supply 50 is connected to the ground terminal GND, and the positive voltage side that is a DC voltage Vc that is a positive voltage with respect to this reference voltage is connected to the input terminal VI.
　また、電源保護回路１０の出力端ＶＯから直流電源５０の直流電力が出力され、負荷Ｌに供給される。図１では、負荷Ｌに並列となるように、電解コンデンサＣｌが接続された一例を示している。このような電解コンデンサＣｌは、直流電源５０からの供給電圧に含まれるリップルやノイズなどを除去するため、通常このように負荷Ｌに接続される。 Further, the DC power of the DC power supply 50 is output from the output terminal VO of the power protection circuit 10 and supplied to the load L. FIG. 1 shows an example in which an electrolytic capacitor Cl is connected so as to be parallel to the load L. Such an electrolytic capacitor Cl is normally connected to the load L in this way in order to remove ripples and noise included in the supply voltage from the DC power supply 50.
　次に、電源保護回路１０は、電流抑制部としての電流抑制抵抗器Ｒｐと、第１のトランジスタとするトランジスタＱ１と、切替制御回路２０とを備える。図１に示すように、電流抑制抵抗器Ｒｐは、入力端ＶＩと出力端ＶＯとの間に設けている。そして、トランジスタＱ１のソースドレイン間が、電流抑制抵抗器Ｒｐと並列となるように接続される。すなわち、トランジスタＱ１のソースＳは、入力端ＶＩに接続され、トランジスタＱ１のドレインＤは、出力端ＶＯに接続される。詳細については、以下で説明するが、トランジスタＱ１は、入力端ＶＩと出力端ＶＯとの間の電気的接続、非接続、すなわちオンオフを行うスイッチとして機能する。また、トランジスタＱ１のオンオフは、トランジスタＱ１のゲート電圧に基づいて切り替えられる。 Next, the power supply protection circuit 10 includes a current suppression resistor Rp as a current suppression unit, a transistor Q1 serving as a first transistor, and a switching control circuit 20. As shown in FIG. 1, the current suppression resistor Rp is provided between the input terminal VI and the output terminal VO. The source and drain of the transistor Q1 are connected in parallel with the current suppressing resistor Rp. That is, the source S of the transistor Q1 is connected to the input terminal VI, and the drain D of the transistor Q1 is connected to the output terminal VO. As will be described in detail below, the transistor Q1 functions as a switch that performs electrical connection / disconnection, that is, on / off, between the input terminal VI and the output terminal VO. The on / off state of the transistor Q1 is switched based on the gate voltage of the transistor Q1.
　また、切替制御回路２０は、電圧検出器２１とスイッチ回路２２とを備える。電圧検出器２１は、出力端ＶＯの電圧を検出し、検出した電圧に基づく切替信号Ｓｓｗを出力する。スイッチ回路２２は、この切替信号Ｓｓｗに応じて、入力端ＶＩの電圧とグランド端ＧＮＤの電圧とのいずれかを選択し、選択した電圧をトランジスタＱ１のゲートＧに供給する。このとき、スイッチ回路２２は、切替信号Ｓｓｗによって、出力端ＶＯの電圧が所定の電圧を超えるとき、グランド端ＧＮＤの電圧を選択し、出力端ＶＯの電圧が所定の電圧よりも低いとき、入力端ＶＩの電圧を選択する。 The switching control circuit 20 includes a voltage detector 21 and a switch circuit 22. The voltage detector 21 detects the voltage of the output terminal VO and outputs a switching signal Ssw based on the detected voltage. The switch circuit 22 selects either the voltage at the input terminal VI or the voltage at the ground terminal GND according to the switching signal Ssw, and supplies the selected voltage to the gate G of the transistor Q1. At this time, the switch circuit 22 selects the voltage of the ground terminal GND when the voltage of the output terminal VO exceeds a predetermined voltage by the switching signal Ssw, and inputs the voltage when the voltage of the output terminal VO is lower than the predetermined voltage. Select the voltage at end VI.
　すなわち、切替制御回路２０は、出力端ＶＯの電圧が所定の電圧を超えるとき、トランジスタＱ１のゲートＧにグランド端ＧＮＤの電圧を印加する。また、切替制御回路２０は、出力端ＶＯの電圧が所定の電圧よりも低いとき、トランジスタＱ１のゲートＧに入力端ＶＩの電圧を印加する。 That is, the switching control circuit 20 applies the voltage of the ground terminal GND to the gate G of the transistor Q1 when the voltage of the output terminal VO exceeds a predetermined voltage. Further, the switching control circuit 20 applies the voltage of the input terminal VI to the gate G of the transistor Q1 when the voltage of the output terminal VO is lower than a predetermined voltage.
　そして、本実施の形態では、トランジスタＱ１をＰチャンネル型トランジスタとしている。より具体的には、例えば、Ｐチャンネル型のＭＯＳタイプの電界効果トランジスタ（ＦＥＴ）である。 In this embodiment, the transistor Q1 is a P-channel transistor. More specifically, for example, it is a P-channel MOS type field effect transistor (FET).
　図２は、本発明の実施の形態１における電源保護回路１０のトランジスタＱ１の特性図である。図２では、Ｐチャンネル型トランジスタのゲートソース間電圧Ｖｇｓに対する、ドレイン電流Ｉｄの特性の一例を示している。図２に示すように、Ｐチャンネル型トランジスタは、ソースＳに対してゲート電圧が負電圧となるとき、ソースドレイン間の抵抗が小さくなり、ソースＳに対してゲート電圧が０（Ｖ）以上になると、ソースドレイン間の抵抗が非常に大きくなる。すなわち、ソースドレイン間は、ソースＳに対してゲート電圧が負電圧のときオンとなり、０（Ｖ）以上でオフとなる。本実施の形態では、このような特性に基づき、閉状態と開状態とに切り替えるスイッチとしてトランジスタＱ１を利用している。 FIG. 2 is a characteristic diagram of the transistor Q1 of the power supply protection circuit 10 according to the first embodiment of the present invention. FIG. 2 shows an example of the characteristics of the drain current Id with respect to the gate-source voltage Vgs of the P-channel transistor. As shown in FIG. 2, when the gate voltage with respect to the source S becomes a negative voltage, the resistance between the source and the drain becomes small, and the gate voltage with respect to the source S becomes 0 (V) or more. Then, the resistance between the source and drain becomes very large. That is, between the source and the drain is turned on when the gate voltage is negative with respect to the source S, and turned off when the gate voltage is 0 (V) or more. In the present embodiment, the transistor Q1 is used as a switch for switching between a closed state and an open state based on such characteristics.
　例えば直流電源５０のスイッチ５１がオンされて、このように構成された電源保護回路１０を介して負荷Ｌ側に、直流電源５０から直流電力が供給された場合、供給された瞬間から、少なくとも電流抑制抵抗器Ｒｐを介して電解コンデンサＣｌに直流電流が流れ込む。このため、出力端ＶＯの電圧は、ほぼグランド端ＧＮＤの電圧に近いほど低くなっている。よって、スイッチ回路２２から入力端ＶＩの電圧が出力され、トランジスタＱ１のゲートＧに供給される。これにより、入力端ＶＩに接続されたソースＳの電圧とゲートＧの電圧とは、ほぼ等しくなる。すなわち、トランジスタＱ１のゲートソース間電圧Ｖｇｓは、ほぼ０（Ｖ）となる。このとき、ゲートソース間電圧Ｖｇｓは図２に示す電圧Ｖｏｆｆとなるため、ドレイン電流Ｉｄは流れず、トランジスタＱ１のソースドレイン間はオフ、すなわち開状態となる。これによって、入力端ＶＩから出力端ＶＯへは、電流抑制抵抗器Ｒｐのみを介して電流が流れることになる。このため、正電圧を供給した瞬間からしばらくは、電流抑制抵抗器Ｒｐによって電流を抑制した状態で、負荷Ｌ側に直流電力が供給される。 For example, when the switch 51 of the DC power supply 50 is turned on and DC power is supplied from the DC power supply 50 to the load L via the power supply protection circuit 10 configured as described above, at least the current is supplied from the moment of supply. A direct current flows into the electrolytic capacitor Cl through the suppression resistor Rp. For this reason, the voltage of the output terminal VO becomes lower as the voltage of the output terminal VO is closer to the ground terminal GND. Therefore, the voltage at the input terminal VI is output from the switch circuit 22 and supplied to the gate G of the transistor Q1. Thereby, the voltage of the source S connected to the input terminal VI and the voltage of the gate G become substantially equal. That is, the gate-source voltage Vgs of the transistor Q1 is substantially 0 (V). At this time, since the gate-source voltage Vgs becomes the voltage Voff shown in FIG. 2, the drain current Id does not flow, and the source-drain of the transistor Q1 is turned off, that is, opened. As a result, a current flows from the input terminal VI to the output terminal VO only through the current suppression resistor Rp. For this reason, DC power is supplied to the load L side for a while from the moment when the positive voltage is supplied while the current is suppressed by the current suppression resistor Rp.
　この後、除々に電解コンデンサＣｌが充電されるため、出力端ＶＯの電圧も高くなる。すると、電圧検出器２１は、所定の電圧を超えたと判定し、グランド端ＧＮＤの電圧を選択するようにスイッチ回路２２を切り替える。スイッチ回路２２からは、グランド端ＧＮＤの電圧が出力され、トランジスタＱ１のゲートＧに供給される。ここで、入力端ＶＩに接続されたトランジスタＱ１のソースＳには、正電圧が供給されている。このため、このソースＳを基準に考えると、グランド端ＧＮＤの電圧となるゲートＧの電圧は、ソースＳに対して負電圧となる。すなわち、ゲートソース間電圧Ｖｇｓは図２に示す電圧Ｖｏｎとなるため、ドレイン電流Ｉｄが流れ、トランジスタＱ１のソースドレイン間はオン、すなわち閉状態となる。これによって、入力端ＶＩから出力端ＶＯへは、トランジスタＱ１のソースドレイン間を介して、電流が流れることになり、負荷Ｌには電流抑制されないような状態で直流電力が供給される。なお、このように、トランジスタＱ１のソースドレイン間を介して直流電力を出力するため、トランジスタＱ１は、オン抵抗の低いトランジスタとすることが好ましい。 Thereafter, since the electrolytic capacitor Cl is gradually charged, the voltage at the output terminal VO also increases. Then, the voltage detector 21 determines that the predetermined voltage has been exceeded, and switches the switch circuit 22 so as to select the voltage at the ground terminal GND. From the switch circuit 22, the voltage at the ground terminal GND is output and supplied to the gate G of the transistor Q1. Here, a positive voltage is supplied to the source S of the transistor Q1 connected to the input terminal VI. For this reason, when the source S is considered as a reference, the voltage of the gate G that is the voltage of the ground terminal GND is a negative voltage with respect to the source S. That is, since the gate-source voltage Vgs becomes the voltage Von shown in FIG. 2, the drain current Id flows, and the source-drain of the transistor Q1 is turned on, that is, closed. As a result, a current flows from the input terminal VI to the output terminal VO via the source and drain of the transistor Q1, and the DC power is supplied to the load L in a state where the current is not suppressed. Note that in this manner, since DC power is output through the source and drain of the transistor Q1, the transistor Q1 is preferably a transistor with low on-resistance.
　図３は、本発明の実施の形態１における電源保護回路１０の動作波形を示す図である。図３では、時間Ｔ０において直流電源５０から直流電力を供給し、その後、出力端ＶＯの電圧が安定するまでの様子を示している。 FIG. 3 is a diagram showing operation waveforms of the power supply protection circuit 10 according to the first embodiment of the present invention. FIG. 3 shows a state in which DC power is supplied from the DC power supply 50 at time T0 and then the voltage at the output terminal VO is stabilized.
　図３に示すように、時間Ｔ０において直流電源５０から直流電力が投入されると、入力端ＶＩの電圧は直流電源５０の電圧Ｖｃとなる。一方、時間Ｔ０において、電流抑制抵抗器Ｒｐを介して電解コンデンサＣｌに直流電流が流れ込むため、出力端ＶＯの電圧は、ほぼグランド端ＧＮＤの電圧に近い。このため、切替制御回路２０は、出力端ＶＯの電圧が所定の電圧Ｖｔｈよりも低いと判定し、トランジスタＱ１のゲートＧに、入力端ＶＩの電圧を印加する。すると、図３に示すように、ソースＳを基準としたゲートＧの電圧Ｖｇｓはほぼ０（Ｖ）となる。これによって、トランジスタＱ１のソースドレイン間は高抵抗状態となり、ソースドレイン間はオフ状態と等価となる。よって、入力端ＶＩから電流抑制抵抗器Ｒｐのみを介して電解コンデンサＣｌに直流電流が流れ込む状態が継続する。この間、図３に示すように、出力端ＶＯの電圧は除々に高くなる。そして、出力端ＶＯの電圧が所定の電圧Ｖｔｈを超える時間Ｔ１になると、切替制御回路２０は、トランジスタＱ１のゲートＧに、グランド端ＧＮＤの電圧を印加する。これにより、ソースＳを基準としたゲートＧの電圧Ｖｇｓは負電圧となるため、トランジスタＱ１のソースドレイン間は低抵抗状態となり、ソースドレイン間はオン状態と等価となる。すなわち、入力端ＶＩと出力端ＶＯとが直接接続されたのと等価な状態で、出力端ＶＯから直流電力が出力される。 As shown in FIG. 3, when DC power is input from the DC power supply 50 at time T0, the voltage at the input terminal VI becomes the voltage Vc of the DC power supply 50. On the other hand, since a direct current flows into the electrolytic capacitor Cl through the current suppression resistor Rp at time T0, the voltage at the output terminal VO is substantially close to the voltage at the ground terminal GND. For this reason, the switching control circuit 20 determines that the voltage at the output terminal VO is lower than the predetermined voltage Vth, and applies the voltage at the input terminal VI to the gate G of the transistor Q1. Then, as shown in FIG. 3, the voltage Vgs of the gate G with respect to the source S becomes substantially 0 (V). As a result, the source and drain of the transistor Q1 are in a high resistance state, and the source and drain are equivalent to an off state. Therefore, a state in which a direct current flows from the input terminal VI into the electrolytic capacitor Cl only through the current suppression resistor Rp continues. During this time, as shown in FIG. 3, the voltage at the output terminal VO gradually increases. When the time T1 when the voltage at the output terminal VO exceeds the predetermined voltage Vth is reached, the switching control circuit 20 applies the voltage at the ground terminal GND to the gate G of the transistor Q1. Accordingly, the voltage Vgs of the gate G with respect to the source S becomes a negative voltage, so that the low resistance state is established between the source and drain of the transistor Q1, and the source and drain are equivalent to the on state. That is, DC power is output from the output terminal VO in a state equivalent to the direct connection between the input terminal VI and the output terminal VO.
　以上説明したように、電源保護回路１０は、直流電源５０を投入後、出力端ＶＯの電圧が供給電圧Ｖｃに近い電圧となるまで、電流抑制状態で電力供給するため、電源投入時に、例えば電解コンデンサＣｌに流れ込む突入電流のような過大電流を抑制できる。また、例えば、負荷Ｌとする電気回路や電解コンデンサＣｌにおいて短絡のような異常が発生した場合、出力端ＶＯの電圧が低下する。出力端ＶＯの電圧が低下すると、切替制御回路２０は、トランジスタＱ１のゲートＧに入力端ＶＩの電圧を印加し、トランジスタＱ１をオフ状態とする。このため、直流電源５０から電流抑制抵抗器Ｒｐのみを介して負荷Ｌ側へと電力供給することになる。すなわち、電流抑制抵抗器Ｒｐによって、負荷Ｌ側への過大な電流の流れ込みを抑制でき、負荷Ｌや直流電源５０の破壊や、負荷Ｌの異常な発熱などを防止できる。 As described above, the power supply protection circuit 10 supplies power in a current-suppressed state after the DC power supply 50 is turned on until the voltage at the output terminal VO becomes close to the supply voltage Vc. An excessive current such as an inrush current flowing into the capacitor Cl can be suppressed. Further, for example, when an abnormality such as a short circuit occurs in the electric circuit serving as the load L or the electrolytic capacitor Cl, the voltage at the output terminal VO decreases. When the voltage at the output terminal VO decreases, the switching control circuit 20 applies the voltage at the input terminal VI to the gate G of the transistor Q1 to turn off the transistor Q1. For this reason, electric power is supplied from the DC power supply 50 to the load L side only through the current suppression resistor Rp. In other words, the current suppression resistor Rp can suppress an excessive current flow to the load L side, and can prevent the load L and the DC power supply 50 from being destroyed or abnormal heat generation of the load L.
　さらに、上述した構成のように、電源保護回路１０は、半導体素子であるトランジスタＱ１を利用しており、小型化を図ることができる。そして、特に、本実施の形態では、このトランジスタＱ１をＰチャンネル型トランジスタとしている。このため、上述したように、ゲートＧに対して、単にグランド端ＧＮＤの電圧か入力端ＶＩの電圧かを切り替えて印加するような簡易な制御のみで、このトランジスタＱ１をオンオフでき、所望の保護機能を実現できる。このように、正電圧を負荷Ｌに伝送する電源保護回路１０は簡易な回路で構成でき、電流抑制抵抗器ＲｐやトランジスタＱ１とともに、例えば同一のプリント基板上などに切替制御回路２０のような制御回路も配置できる。また、トランジスタＱ１と切替制御回路２０とを１つのＩＣとするような集積化も容易である。 Furthermore, as in the configuration described above, the power supply protection circuit 10 uses the transistor Q1, which is a semiconductor element, and can be reduced in size. In particular, in this embodiment, the transistor Q1 is a P-channel transistor. For this reason, as described above, the transistor Q1 can be turned on / off by simple control such as switching between the voltage at the ground terminal GND or the voltage at the input terminal VI and applying the desired protection to the gate G. Functions can be realized. As described above, the power protection circuit 10 that transmits the positive voltage to the load L can be configured as a simple circuit, and is controlled together with the current suppression resistor Rp and the transistor Q1 such as the switching control circuit 20 on the same printed circuit board. Circuits can also be placed. Further, it is easy to integrate the transistor Q1 and the switching control circuit 20 into one IC.
　次に電源保護回路１０のさらに詳細な構成の一例について説明する。図４は、本発明の実施の形態１における電源保護回路１０の回路図である。図４に示すように、切替制御回路３０は、第２のトランジスタとするトランジスタＱ２と、ダイオードＤ１と、第１の抵抗器Ｒ１と、第２の抵抗器Ｒ２とを備える。 Next, an example of a more detailed configuration of the power supply protection circuit 10 will be described. FIG. 4 is a circuit diagram of the power supply protection circuit 10 according to the first embodiment of the present invention. As shown in FIG. 4, the switching control circuit 30 includes a transistor Q2 serving as a second transistor, a diode D1, a first resistor R1, and a second resistor R2.
　トランジスタＱ２は、ＰＮＰ型のバイポーラトランジスタである。トランジスタＱ２のエミッタＥは、入力端ＶＩに接続される。また、トランジスタＱ２のコレクタＣは、抵抗器Ｒ１を介してグランド端ＧＮＤに接続される。ここで、トランジスタＱ２は、スイッチ素子として利用しており、トランジスタＱ２のエミッタベース間に印加される電圧に基づき、エミッタコレクタ間がオンオフされる。これによって、トランジスタＱ２のコレクタＣからは、グランド端ＧＮＤの電圧と入力端ＶＩの電圧とのいずれかの電圧が出力される。 The transistor Q2 is a PNP type bipolar transistor. The emitter E of the transistor Q2 is connected to the input terminal VI. The collector C of the transistor Q2 is connected to the ground terminal GND through the resistor R1. Here, the transistor Q2 is used as a switching element, and the emitter-collector is turned on and off based on the voltage applied between the emitter base of the transistor Q2. As a result, either the voltage at the ground terminal GND or the voltage at the input terminal VI is output from the collector C of the transistor Q2.
　また、ダイオードＤ１のアノードＡは、出力端ＶＯに接続される。ダイオードＤ１のカソードＫは、抵抗器Ｒ２を介してグランド端ＧＮＤに接続される。ダイオードＤ１は、トランジスタＱ２をスイッチ操作するために利用する電圧を生成するために設けている。また、ダイオードＤ１は、入力端ＶＩからトランジスタＱ２のエミッタＥおよびベースＢを介して、入力電流が出力端ＶＯまで流れ込むのを防止する役目も果たす。そして、トランジスタＱ２のベースＢがダイオードＤ１のカソードＫに接続され、トランジスタＱ２のコレクタＣがトランジスタＱ１のゲートＧに接続される。 The anode A of the diode D1 is connected to the output terminal VO. The cathode K of the diode D1 is connected to the ground terminal GND through the resistor R2. The diode D1 is provided to generate a voltage used for switching the transistor Q2. The diode D1 also serves to prevent an input current from flowing from the input terminal VI to the output terminal VO via the emitter E and base B of the transistor Q2. The base B of the transistor Q2 is connected to the cathode K of the diode D1, and the collector C of the transistor Q2 is connected to the gate G of the transistor Q1.
　図５は、本発明の実施の形態１における電源保護回路１０の切替制御回路３０の動作説明図である。次に、図４および図５を参照しながら、以上のように構成された切替制御回路３０、およびこの切替制御回路３０を備えた電源保護回路１０の動作について説明する。 FIG. 5 is an operation explanatory diagram of the switching control circuit 30 of the power protection circuit 10 according to the first embodiment of the present invention. Next, the operation of the switching control circuit 30 configured as described above and the power supply protection circuit 10 including the switching control circuit 30 will be described with reference to FIGS. 4 and 5.
　まず、入力端ＶＩに直流電源５０から正電圧が供給された瞬間は、上述したように、出力端ＶＯの電圧はほぼグランド端ＧＮＤの電圧となる。すなわち、トランジスタＱ２のエミッタＥを基準にしたベースＢの電圧は、負電圧方向に高くなる。このため、入力端ＶＩに接続されたトランジスタＱ２のエミッタＥから、ベースＢおよび抵抗器Ｒ２を介して、グランド端ＧＮＤへとベース電流が流れることになる。これにより、トランジスタＱ２はオン状態となり、トランジスタＱ２のコレクタＣは、ほぼ入力端ＶＩの電圧となる。この電圧がトランジスタＱ１のゲートＧに印加される。そして、トランジスタＱ１のゲートソース間の電圧Ｖｇｓはほぼ０（Ｖ）となるため、トランジスタＱ１はオフ状態となる。これによって、入力端ＶＩから出力端ＶＯへは、電流抑制抵抗器Ｒｐのみを介して電流が流れる。 First, at the moment when a positive voltage is supplied to the input terminal VI from the DC power supply 50, as described above, the voltage at the output terminal VO is substantially the voltage at the ground terminal GND. That is, the voltage of the base B with respect to the emitter E of the transistor Q2 increases in the negative voltage direction. Therefore, a base current flows from the emitter E of the transistor Q2 connected to the input terminal VI to the ground terminal GND through the base B and the resistor R2. As a result, the transistor Q2 is turned on, and the collector C of the transistor Q2 is almost at the voltage of the input terminal VI. This voltage is applied to the gate G of the transistor Q1. Since the voltage Vgs between the gate and source of the transistor Q1 is almost 0 (V), the transistor Q1 is turned off. As a result, a current flows from the input terminal VI to the output terminal VO only through the current suppression resistor Rp.
　ここで、トランジスタＱ２のベースＢに印加される電圧について説明する。図５は、エミッタＥの電圧を基準にして、ベースＢに印加される電圧を示している。なお、図５では、エミッタＥを基準にした電圧を示しているため一定となっているが、グランド端ＧＮＤを基準にすると、当然のことながらエミッタＥの電圧は入力端ＶＩの電圧となる。また、図５では、時間Ｔ０において、入力端ＶＩに直流電源５０から正電圧が供給された様子を示している。また、図５では、トランジスタＱ２のエミッタベース間の電圧Ｖｂｅを示している。このエミッタベース間の電圧Ｖｂｅを負方向に超える電圧が印加されると、トランジスタＱ２はオンとなり、超えない場合はオフとなる。 Here, the voltage applied to the base B of the transistor Q2 will be described. FIG. 5 shows the voltage applied to the base B with the voltage of the emitter E as a reference. In FIG. 5, the voltage is constant because the voltage is based on the emitter E. However, when the ground terminal GND is used as a reference, the voltage of the emitter E is naturally the voltage of the input terminal VI. FIG. 5 shows a state in which a positive voltage is supplied from the DC power supply 50 to the input terminal VI at time T0. FIG. 5 shows the voltage Vbe between the emitter and base of the transistor Q2. When a voltage that exceeds the emitter-base voltage Vbe in the negative direction is applied, the transistor Q2 is turned on.
　図５に示すように、時間Ｔ０において、エミッタＥを基準にすると、ベースＢには、電流抑制抵抗器Ｒｐの両端電圧ＶｒｐにダイオードＤ１の両端電圧Ｖｄを加えた電圧Ｖｒｄが印加される。このとき、図５に示すように、この印加される電圧Ｖｒｄは、電圧Ｖｂｅを負方向に超える電圧となるため、エミッタＥからベースＢへとベース電流が流れ、トランジスタＱ２はオンとなる。なお、この時点において電圧Ｖｒｄが印加された瞬間にベース電流が流れ始めるため、エミッタＥとベースＢとの間の電圧は、印加される電圧Ｖｒｄではなく、ベース電流の流れによってトランジスタＱ２から生じる電圧Ｖｂｅとなる。すなわち、エミッタＥとベースＢとの間の電圧は、図５の実線で示すような電圧Ｖｂとなる。 As shown in FIG. 5, at time T0, when the emitter E is used as a reference, a voltage Vrd obtained by adding the voltage Vd across the diode D1 to the voltage Vrp across the current suppression resistor Rp is applied to the base B. At this time, as shown in FIG. 5, since the applied voltage Vrd exceeds the voltage Vbe in the negative direction, a base current flows from the emitter E to the base B, and the transistor Q2 is turned on. Since the base current starts to flow at the moment when the voltage Vrd is applied at this time, the voltage between the emitter E and the base B is not the applied voltage Vrd but the voltage generated from the transistor Q2 by the flow of the base current. Vbe. That is, the voltage between the emitter E and the base B is a voltage Vb as shown by the solid line in FIG.
　その後、時間の経過とともに、例えば電解コンデンサＣｌへの充電電流が減少するため、電流抑制抵抗器Ｒｐの両端電圧Ｖｒｐも減少する。このため、図５に示すように、時間の経過とともに、電圧Ｖｒｄは電圧Ｖｂｅに近くなる。 Thereafter, with the passage of time, for example, the charging current to the electrolytic capacitor Cl decreases, so the voltage Vrp across the current suppressing resistor Rp also decreases. For this reason, as shown in FIG. 5, the voltage Vrd approaches the voltage Vbe with time.
　そして、時間Ｔ１において、電圧Ｖｒｄが電圧Ｖｂｅを負方向に超えなくなると、エミッタＥからベースＢへのベース電流が遮断される。このため、トランジスタＱ２はオフ状態となり、トランジスタＱ１のゲートＧにはグランド端ＧＮＤの電圧が印加される。そして、トランジスタＱ１のソースＳに対するゲートＧの電圧は負電圧となるため、トランジスタＱ１はオン状態となる。これによって、入力端ＶＩから出力端ＶＯへは、トランジスタＱ１のソースドレイン間を介して、電流が流れることになる。 When the voltage Vrd does not exceed the voltage Vbe in the negative direction at time T1, the base current from the emitter E to the base B is cut off. For this reason, the transistor Q2 is turned off, and the voltage of the ground terminal GND is applied to the gate G of the transistor Q1. Since the voltage of the gate G with respect to the source S of the transistor Q1 is a negative voltage, the transistor Q1 is turned on. As a result, a current flows from the input terminal VI to the output terminal VO through the source and drain of the transistor Q1.
　ここで、この時点での、トランジスタＱ２のベースＢに印加される電圧は次のようになる。このとき、トランジスタＱ１はオン状態であるため、エミッタＥを基準にすると、ベースＢには、トランジスタＱ１のソースドレイン間電圧ＶｓｄにダイオードＤ１の両端電圧Ｖｄを加えた電圧Ｖｔｄが印加される。実際には、トランジスタＱ１はオン抵抗の低いトランジスタとすることが好適であるため、ベースＢには、ダイオードＤ１の両端電圧Ｖｄに近い電圧が印加される。また、このとき、トランジスタＱ２にはベース電流が流れていないため、エミッタＥとベースＢとの間の電圧は、印加される電圧Ｖｔｄ、近似的にはダイオードＤ１の両端電圧Ｖｄとなる。すなわち、エミッタＥとベースＢとの間の電圧は、図５の実線で示すような電圧Ｖｂとなる。図５に示す電圧Ｖｂからわかるように、一旦トランジスタＱ１がオン状態になると、エミッタＥとベースＢとの間には、ダイオードＤ１によって、電圧Ｖｂｅよりも少し低い電圧Ｖｄの印加が継続される。このような動作からわかるように、トランジスタＱ２のオンオフを決める電圧Ｖｂｅに対して、オン電圧Ｖｄのダイオードの品種をダイオードＤ１として適切に選定することで、トランジスタＱ１の切替特性が所望の特性となるように容易に設定することができる。 Here, the voltage applied to the base B of the transistor Q2 at this time is as follows. At this time, since the transistor Q1 is in the on state, when the emitter E is used as a reference, a voltage Vtd obtained by adding the voltage Vd between both ends of the diode D1 to the voltage Vsd between the source and drain of the transistor Q1 is applied to the base B. Actually, since the transistor Q1 is preferably a transistor having a low on-resistance, a voltage close to the voltage Vd across the diode D1 is applied to the base B. At this time, since the base current does not flow through the transistor Q2, the voltage between the emitter E and the base B becomes the applied voltage Vtd, approximately the voltage Vd across the diode D1. That is, the voltage between the emitter E and the base B is a voltage Vb as shown by the solid line in FIG. As can be seen from the voltage Vb shown in FIG. 5, once the transistor Q1 is turned on, a voltage Vd slightly lower than the voltage Vbe is continuously applied between the emitter E and the base B by the diode D1. As can be seen from such operation, the switching characteristic of the transistor Q1 becomes a desired characteristic by appropriately selecting the diode type of the diode of the on voltage Vd as the diode D1 with respect to the voltage Vbe that determines the on / off of the transistor Q2. Can be set easily.
　また、負荷Ｌにおいてショートのような異常が発生して過電流が流れた場合、この過電流は、トランジスタＱ１のソースドレイン間を流れる。このため、トランジスタＱ１のソースドレイン間には、トランジスタＱ１のオン抵抗とこの過電流とによる電圧Ｖｓｄが発生する。そして、この、電圧ＶｓｄにダイオードＤ１の両端電圧Ｖｄを加えた電圧Ｖｔｄが電圧Ｖｂｅを負方向に超えると、トランジスタＱ２にベース電流が流れ出し、トランジスタＱ１はオフ状態へと切り替えられる。そして、電流抑制抵抗器Ｒｐによって、この過電流が抑制されることになる。 Further, when an overcurrent flows due to an abnormality such as a short circuit in the load L, the overcurrent flows between the source and drain of the transistor Q1. Therefore, a voltage Vsd is generated between the source and drain of the transistor Q1 due to the on-resistance of the transistor Q1 and this overcurrent. When the voltage Vtd obtained by adding the voltage Vd across the diode D1 to the voltage Vsd exceeds the voltage Vbe in the negative direction, a base current flows out to the transistor Q2, and the transistor Q1 is switched to the off state. The overcurrent is suppressed by the current suppression resistor Rp.
　このように、電源保護回路１０は、直流電源５０から直流電力を供給した時点から、電流抑制抵抗器Ｒｐを介して電解コンデンサＣｌや負荷Ｌに除々に電流が流れるように直流電力を供給するため、大電流となる突入電流を抑制できる。また、例えば、電解コンデンサＣｌの短絡などの故障が生じた場合も、出力端ＶＯの電圧異常を検出し、電流抑制抵抗器Ｒｐを介して直流電流を供給するように保護機能が働くため、故障による過電流から負荷Ｌや供給元の直流電源５０の保護を図ることができる。 In this way, the power supply protection circuit 10 supplies DC power so that current gradually flows to the electrolytic capacitor Cl and the load L via the current suppression resistor Rp from the time when DC power is supplied from the DC power supply 50. Inrush current that becomes a large current can be suppressed. Further, for example, even when a failure such as a short circuit of the electrolytic capacitor Cl occurs, the protection function works to detect a voltage abnormality of the output terminal VO and supply a direct current through the current suppression resistor Rp. Therefore, it is possible to protect the load L and the DC power supply 50 of the supply source from an overcurrent due to the above.
　以上説明したように、本発明の電源保護回路は、入力端と出力端との間に設けた電流抑制部と、電流抑制部と並列にソースドレイン間が接続されたトランジスタとを備える。さらに本発明の電源保護回路は、出力端の電圧が所定の電圧を超えるとき、トランジスタのゲートにグランド端の電圧を印加し、出力端の電圧が所定の電圧よりも低いとき、トランジスタのゲートに入力端の電圧を印加する切替制御回路とを備え、トランジスタをＰチャンネル型トランジスタとした構成である。このため、従来の機械式のスイッチやリレーに代えて、このように半導体素子であるトランジスタを利用することにより、小型化を図ることができ、信頼性の向上を図ることができる。そして、このトランジスタをＰチャンネル型トランジスタとしているため、ゲートに対して、単にグランド端の電圧か入力端の電圧かを切り替えて印加するような簡易な制御のみで、このトランジスタをオンオフでき、所望の保護機能を実現できる。このため、電流抑制部に並列に接続するトランジスタの制御も、マイコンなど必要なく簡易な回路で構成でき、電流抑制部やトランジスタとともに、例えば同一のプリント基板上などに配置できる。そして、長い配線引き回しなど必要なく、部品点数も少なくてよいため接触不良などの発生も抑制でき、その結果、信頼性の向上を図ることが可能となる。また、例えばトランジスタＱ１と図４の切替制御回路３０とを１つのＩＣに集積化することによって、より信頼性を高めることができる。したがって、本発明の電源保護回路によれば、簡易な構成で信頼性の向上を可能とした電源保護回路を提供することができる。 As described above, the power protection circuit of the present invention includes a current suppression unit provided between an input end and an output end, and a transistor having a source and drain connected in parallel with the current suppression unit. Further, the power protection circuit of the present invention applies a ground terminal voltage to the gate of the transistor when the output terminal voltage exceeds a predetermined voltage, and applies to the transistor gate when the output terminal voltage is lower than the predetermined voltage. And a switching control circuit for applying a voltage at the input terminal, and the transistor is a P-channel transistor. For this reason, it is possible to reduce the size and improve the reliability by using the transistor, which is a semiconductor element, instead of the conventional mechanical switch or relay. Since this transistor is a P-channel transistor, the transistor can be turned on and off by simple control such as switching between the voltage at the ground end and the voltage at the input end to the gate. A protection function can be realized. For this reason, the control of the transistor connected in parallel to the current suppression unit can also be configured with a simple circuit without a microcomputer or the like, and can be arranged together with the current suppression unit and the transistor, for example, on the same printed circuit board. Further, there is no need for long wiring and the number of parts can be small, so that occurrence of poor contact can be suppressed, and as a result, reliability can be improved. Further, for example, by integrating the transistor Q1 and the switching control circuit 30 of FIG. 4 in one IC, the reliability can be further improved. Therefore, according to the power protection circuit of the present invention, it is possible to provide a power protection circuit capable of improving reliability with a simple configuration.
　なお、以上の説明では、電流抑制部を電流抑制抵抗器Ｒｐとした一例を挙げて説明したが、電流抑制部はこれに限定されず、例えば、一定の電流を出力する定電流源回路としてもよい。図６は、本発明の実施の形態１における電源保護回路の他の構成例としての電源保護回路１１を示すブロック図である。図６では、このような電流抑制部として定電流源回路Ｄｐとした一例を示している。電流抑制抵抗器Ｒｐとした場合、例えば電解コンデンサＣｌに流れ込む電流は、電源投入時は多く流れ、また一方時間の経過とともに電流量が少なくなる。このため、電源投入時の電流抑制効果が少なくなるとともにトランジスタＱ１へと切り替えるまでに時間がかかることになる。これに対し、電流抑制部を定電流源回路とした場合、電解コンデンサＣｌへの充電電流は一定とできるため、電源投入時の電流量を抑えるとともに、トランジスタＱ１へと切り替える時間の短縮を図れる。 In the above description, the current suppression unit is described as an example of the current suppression resistor Rp. However, the current suppression unit is not limited to this, and for example, as a constant current source circuit that outputs a constant current. Good. FIG. 6 is a block diagram showing a power supply protection circuit 11 as another configuration example of the power supply protection circuit according to the first embodiment of the present invention. FIG. 6 shows an example in which a constant current source circuit Dp is used as such a current suppressing unit. In the case of the current suppression resistor Rp, for example, a large amount of current flows into the electrolytic capacitor Cl when the power is turned on, and the amount of current decreases as time elapses. For this reason, the current suppressing effect at the time of turning on the power is reduced, and it takes time to switch to the transistor Q1. On the other hand, when the current suppressing unit is a constant current source circuit, the charging current to the electrolytic capacitor Cl can be constant, so that the amount of current when the power is turned on can be suppressed and the time for switching to the transistor Q1 can be shortened.
　また、電流抑制部を、電流抑制抵抗器Ｒｐと例えば温度遮断型ヒューズなどとを直列接続した回路としてもよい。図７は、本発明の実施の形態１における電源保護回路のさらに他の構成例としての電源保護回路１２を示すブロック図である。図７では、このような電流抑制部として、電流抑制抵抗器ＲｐとヒューズＦｐとの直列回路とした一例を示している。このような構成とすることにより、突入電流や過電流が生じた場合、ヒューズＦｐによって電力供給を遮断することができる。 Also, the current suppression unit may be a circuit in which a current suppression resistor Rp and a temperature interrupting fuse, for example, are connected in series. FIG. 7 is a block diagram showing a power supply protection circuit 12 as still another configuration example of the power supply protection circuit according to the first embodiment of the present invention. FIG. 7 shows an example in which such a current suppression unit is a series circuit of a current suppression resistor Rp and a fuse Fp. With such a configuration, when an inrush current or an overcurrent occurs, power supply can be interrupted by the fuse Fp.
　また、以上の説明では、正電圧が供給される場合の電源保護回路について説明したが、負電圧が供給される場合には、次のような構成とすることにより実現できる。すなわち、負電圧が供給される入力端と出力端との間に設けた電流抑制部と、電流抑制部と並列にソースドレイン間が接続されたトランジスタと、出力端の電圧の絶対値が所定の電圧を超えるとき、トランジスタのゲートにグランド端の電圧を印加し、出力端の電圧の絶対値が所定の電圧よりも低いとき、トランジスタのゲートに入力端の電圧を印加する切替制御回路とを備え、このトランジスタをＮチャンネル型トランジスタとする。このような構成とすることにより正電圧が供給される場合と同様に、簡易な構成で信頼性の向上を可能とした電源保護回路を実現できる。 In the above description, the power protection circuit when a positive voltage is supplied has been described. However, when a negative voltage is supplied, it can be realized by the following configuration. That is, a current suppression unit provided between an input terminal and an output terminal to which a negative voltage is supplied, a transistor whose source and drain are connected in parallel with the current suppression unit, and an absolute value of the voltage at the output terminal is a predetermined value A switching control circuit that applies a voltage at the ground end to the gate of the transistor when exceeding the voltage, and applies a voltage at the input end to the gate of the transistor when the absolute value of the voltage at the output end is lower than a predetermined voltage. This transistor is an N-channel transistor. By adopting such a configuration, a power supply protection circuit capable of improving reliability with a simple configuration can be realized as in the case where a positive voltage is supplied.
　また、以上の説明では、電源投入時や負荷短絡のような異常時に、電流抑制部を介して電源供給し、過電流から負荷や電源の保護を図る構成例について説明したが、電流抑制部を設けない構成とすることによっても保護機能を実現できる。すなわち、グランド端に対して正電圧となる入力端に直流電源が接続され、出力端から直流電力を出力する電源保護回路であって、この電源保護回路を、例えば、入力端と出力端との間にソースドレイン間が接続された第１のトランジスタと、エミッタを入力端に接続し、コレクタを第１の抵抗器を介してグランド端に接続したＰＮＰ型の第２のトランジスタと、アノードを出力端に接続し、カソードを第２の抵抗器を介してグランド端に接続したダイオードとを備え、第２のトランジスタのベースをダイオードのカソードに接続し、第２のトランジスタのコレクタを第１のトランジスタのゲートに接続した構成としてもよい。電源保護回路をこのような構成とすることによっても、負荷に短絡のような異常が生じた場合、第１のトランジスタは異常な過電流を遮断するように動作するため、やはり、簡易な構成で信頼性の向上を図りながら、異常な過電流から負荷や電源を保護することができる。 In the above description, the configuration example in which power is supplied via the current suppression unit and the load and the power source are protected from overcurrent when the power is turned on or when an abnormality such as a load short circuit is described. The protection function can be realized even if the configuration is not provided. That is, a power supply protection circuit in which a DC power source is connected to an input terminal having a positive voltage with respect to the ground terminal and DC power is output from the output terminal. The power protection circuit is connected to, for example, an input terminal and an output terminal. A first transistor having a source-drain connected in between, an emitter connected to an input terminal, a PNP-type second transistor connected to a ground terminal via a first resistor, and an anode output And a diode having a cathode connected to the ground end via a second resistor, a base of the second transistor connected to the cathode of the diode, and a collector of the second transistor serving as the first transistor It is good also as a structure connected to this gate. Even if the power supply protection circuit has such a configuration, if an abnormality such as a short circuit occurs in the load, the first transistor operates so as to cut off an abnormal overcurrent. While improving reliability, it is possible to protect the load and power supply from abnormal overcurrent.
　（実施の形態２）
　図８は、本発明の実施の形態２におけるモータ駆動装置１００のブロック図である。図８に示すように、モータ駆動装置１００は、実施の形態１で説明した電源保護回路１０とモータ７０を駆動するためのインバータ６０とを備える。そして、インバータ６０には電源保護回路１０を介して直流電力が供給される。このように、モータ駆動装置１００は、信頼性の向上を高めた電源保護回路１０を備えるため、本発明のモータ駆動装置は、簡易な構成で信頼性の向上を可能としたモータ駆動装置を提供することができる。なお、当然のことながら、電源保護回路１０に代えて、電源保護回路１１や電源保護回路１２であってもよい。 (Embodiment 2)
FIG. 8 is a block diagram of motor drive device 100 according to Embodiment 2 of the present invention. As shown in FIG. 8, the motor drive device 100 includes the power supply protection circuit 10 described in the first embodiment and an inverter 60 for driving the motor 70. The inverter 60 is supplied with DC power via the power protection circuit 10. Thus, since the motor drive device 100 includes the power supply protection circuit 10 with improved reliability, the motor drive device of the present invention provides a motor drive device that can improve reliability with a simple configuration. can do. As a matter of course, the power supply protection circuit 11 or the power supply protection circuit 12 may be used instead of the power supply protection circuit 10.
　本発明の電源保護回路およびそれを備えたモータ駆動装置は、簡易な構成で高い信頼性を有した電源保護機能が得られるため、例えば、高い信頼性が要求される車載用の電気装置や車載用のモータを駆動するモータ駆動装置、その他家電や産業用の電気装置やモータ駆動装置に有用である。 The power protection circuit of the present invention and the motor driving device including the power protection circuit can provide a highly reliable power protection function with a simple configuration. For example, a vehicle-mounted electric device or a vehicle that requires high reliability is used. It is useful for a motor drive device that drives a motor for electric appliances, and other electric devices and motor drive devices for home appliances and industrial use.
　Ｄ１　　ダイオード
　Ｑ１　　（第１の）トランジスタ
　Ｑ２　　（第２の）トランジスタ
　Ｒ１　　（第１の）抵抗器
　Ｒ２　　（第２の）抵抗器
　Ｒｐ　　電流抑制抵抗器（電流抑制部）
　Ｃｌ　　電解コンデンサ
　Ｌ　　負荷
　Ｄｐ　　定電流源回路
　Ｆｐ　　ヒューズ
　１０，１１，１２　　電源保護回路
　２０，３０　　切替制御回路
　２１　　電圧検出器
　２２　　スイッチ回路
　５０　　直流電源
　５１　　スイッチ
　６０　　インバータ
　７０　　モータ
　１００　　モータ駆動装置 D1 diode Q1 (first) transistor Q2 (second) transistor R1 (first) resistor R2 (second) resistor Rp current suppression resistor (current suppression unit)
Cl electrolytic capacitor L load Dp constant current source circuit Fp fuse 10, 11, 12 power protection circuit 20, 30 switching control circuit 21 voltage detector 22 switch circuit 50 DC power supply 51 switch 60 inverter 70 motor 100 motor drive device

Claims (10)

  1. グランド端に対して正電圧となる入力端に直流電源が接続され、出力端から直流電力を出力する電源保護回路であって、
    前記入力端と前記出力端との間に設けた電流抑制部と、
    前記電流抑制部と並列にソースドレイン間が接続されたトランジスタと、
    前記出力端の電圧が所定の電圧を超えるとき、前記トランジスタのゲートに前記グランド端の電圧を印加し、前記出力端の電圧が所定の電圧よりも低いとき、前記トランジスタのゲートに前記入力端の電圧を印加する切替制御回路とを備え、
    前記トランジスタをＰチャンネル型トランジスタとしたことを特徴とする電源保護回路。     A power supply protection circuit in which a DC power supply is connected to an input terminal having a positive voltage with respect to a ground terminal, and DC power is output from an output terminal,
    A current suppressing portion provided between the input end and the output end;
    A transistor in which a source and a drain are connected in parallel with the current suppressing unit;
    When the voltage at the output terminal exceeds a predetermined voltage, the voltage at the ground terminal is applied to the gate of the transistor, and when the voltage at the output terminal is lower than the predetermined voltage, the gate of the transistor has the input terminal. A switching control circuit for applying a voltage,
    A power supply protection circuit, wherein the transistor is a P-channel transistor.
  2. 前記切替制御回路は、
    前記出力端の電圧を検出し、検出した電圧に基づく切替信号を出力する電圧検出器と、
    前記切替信号に応じて、前記入力端の電圧と前記グランド端の電圧とのいずれかを選択し、選択した電圧を前記トランジスタのゲートに供給するスイッチ回路とを備え、
    前記スイッチ回路は、前記出力端の電圧が所定の電圧を超えるとき、前記グランド端の電圧を選択し、前記出力端の電圧が所定の電圧よりも低いとき、前記入力端の電圧を選択することを特徴とする請求項１に記載の電源保護回路。     The switching control circuit includes:
    A voltage detector that detects the voltage at the output end and outputs a switching signal based on the detected voltage;
    A switch circuit that selects one of the voltage at the input terminal and the voltage at the ground terminal in accordance with the switching signal and supplies the selected voltage to the gate of the transistor;
    The switch circuit selects the ground terminal voltage when the output terminal voltage exceeds a predetermined voltage, and selects the input terminal voltage when the output terminal voltage is lower than the predetermined voltage. The power supply protection circuit according to claim 1.
  3. 前記スイッチ回路は、半導体のスイッチ素子を用いて構成されることを特徴とする請求項２に記載の電源保護回路。 The power supply protection circuit according to claim 2, wherein the switch circuit is configured using a semiconductor switch element.
  4. 前記トランジスタを第１のトランジスタとしたとき、
    前記切替制御回路は、
    エミッタを前記入力端に接続し、コレクタを第１の抵抗器を介して前記グランド端に接続したＰＮＰ型の第２のトランジスタと、
    アノードを前記出力端に接続し、カソードを第２の抵抗器を介して前記グランド端に接続したダイオードとを備え、
    前記第２のトランジスタのベースを前記ダイオードのカソードに接続し、前記第２のトランジスタのコレクタを前記第１のトランジスタのゲートに接続したことを特徴とする請求項１に記載の電源保護回路。     When the transistor is a first transistor,
    The switching control circuit includes:
    A PNP-type second transistor having an emitter connected to the input terminal and a collector connected to the ground terminal via a first resistor;
    A diode having an anode connected to the output terminal and a cathode connected to the ground terminal via a second resistor;
    2. The power protection circuit according to claim 1, wherein a base of the second transistor is connected to a cathode of the diode, and a collector of the second transistor is connected to a gate of the first transistor.
  5. 前記電流抑制部は、抵抗器であることを特徴とする請求項１から４のいずれか１項に記載の電源保護回路。 The power supply protection circuit according to claim 1, wherein the current suppression unit is a resistor.
  6. 前記電流抑制部は、一定の電流を出力する定電流源回路であることを特徴とする請求項１から４のいずれか１項に記載の電源保護回路。 5. The power supply protection circuit according to claim 1, wherein the current suppressing unit is a constant current source circuit that outputs a constant current. 6.
  7. 前記電流抑制部は、抵抗器とヒューズとの直列回路であることを特徴とする請求項１から４のいずれか１項に記載の電源保護回路。 5. The power supply protection circuit according to claim 1, wherein the current suppression unit is a series circuit of a resistor and a fuse.
  8. グランド端に対して負電圧となる入力端に直流電源が接続され、出力端から直流電力を出力する電源保護回路であって、
    前記入力端と前記出力端との間に設けた電流抑制部と、
    前記電流抑制部と並列にソースドレイン間が接続されたトランジスタと、
    前記出力端の電圧の絶対値が所定の電圧を超えるとき、前記トランジスタのゲートに前記グランド端の電圧を印加し、前記出力端の電圧の絶対値が所定の電圧よりも低いとき、前記トランジスタのゲートに前記入力端の電圧を印加する切替制御回路とを備え、
    前記トランジスタをＮチャンネル型トランジスタとしたことを特徴とする電源保護回路。     A power protection circuit in which a DC power source is connected to an input terminal that is a negative voltage with respect to a ground terminal, and DC power is output from an output terminal,
    A current suppressing portion provided between the input end and the output end;
    A transistor in which a source and a drain are connected in parallel with the current suppressing unit;
    When the absolute value of the voltage at the output terminal exceeds a predetermined voltage, the voltage at the ground terminal is applied to the gate of the transistor, and when the absolute value of the voltage at the output terminal is lower than a predetermined voltage, A switching control circuit for applying a voltage of the input terminal to the gate,
    A power supply protection circuit, wherein the transistor is an N-channel transistor.
  9. グランド端に対して正電圧となる入力端に直流電源が接続され、出力端から直流電力を出力する電源保護回路であって、
    前記入力端と前記出力端との間にソースドレイン間が接続された第１のトランジスタと、エミッタを前記入力端に接続し、コレクタを第１の抵抗器を介して前記グランド端に接続したＰＮＰ型の第２のトランジスタと、アノードを前記出力端に接続し、カソードを第２の抵抗器を介して前記グランド端に接続したダイオードとを備え、
    前記第２のトランジスタのベースを前記ダイオードのカソードに接続し、前記第２のトランジスタのコレクタを前記第１のトランジスタのゲートに接続したことを特徴とする電源保護回路。     A power supply protection circuit in which a DC power supply is connected to an input terminal having a positive voltage with respect to a ground terminal, and DC power is output from an output terminal,
    A first transistor in which a source and a drain are connected between the input end and the output end, a PNP in which an emitter is connected to the input end, and a collector is connected to the ground end via a first resistor. A second transistor of the type, and a diode having an anode connected to the output terminal and a cathode connected to the ground terminal via a second resistor,
    A power supply protection circuit, wherein a base of the second transistor is connected to a cathode of the diode, and a collector of the second transistor is connected to a gate of the first transistor.
  10. 請求項１から９のいずれか１項に記載の電源保護回路と、
    前記電源保護回路を介して供給された前記直流電力により動作するインバータとを備え、前記インバータによりモータを駆動することを特徴とするモータ駆動装置。     A power protection circuit according to any one of claims 1 to 9,
    And a motor driven by the inverter, wherein the motor is driven by the DC power supplied via the power protection circuit.
PCT/JP2010/003992 2009-06-24 2010-06-16 Power supply protection circuit and motor drive device provided with same WO2010150488A1 (en)

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