WO2010146645A1 - Semiconductor device and method for manufacturing semiconductor device - Google Patents

Semiconductor device and method for manufacturing semiconductor device Download PDF

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Publication number
WO2010146645A1
WO2010146645A1 PCT/JP2009/060862 JP2009060862W WO2010146645A1 WO 2010146645 A1 WO2010146645 A1 WO 2010146645A1 JP 2009060862 W JP2009060862 W JP 2009060862W WO 2010146645 A1 WO2010146645 A1 WO 2010146645A1
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electrode layer
electrode
semiconductor device
organic
gate
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PCT/JP2009/060862
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French (fr)
Japanese (ja)
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隆 中馬
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パイオニア株式会社
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Priority to PCT/JP2009/060862 priority Critical patent/WO2010146645A1/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/60—Forming conductive regions or layers, e.g. electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having a potential-jump barrier or a surface barrier
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H10K10/466—Lateral bottom-gate IGFETs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/125—Active-matrix OLED [AMOLED] displays including organic TFTs [OTFT]

Definitions

  • the present invention relates to a semiconductor device, and more particularly to a method for forming an electrode of an organic thin film transistor using an electroless plating method.
  • organic TFT Thin Film Transistor
  • Organic TFT is a kind of field effect transistor (FET), which is basically a three-terminal element consisting of a drain, a source and a gate.
  • FET field effect transistor
  • a plating method is used to form metal wirings that function as the drain, source, and gate terminals of the organic TFT.
  • As a patterning method in the case of forming a metal wiring by using a plating method there are the following methods.
  • a gate electrode, a gate insulating layer, and a photocatalytic material are sequentially formed on a light-transmitting substrate, and then the substrate is selectively exposed in a state where the substrate is immersed in a solution containing a plating catalyst material.
  • a plating catalyst material By depositing a plating catalyst material on the photocatalyst material of the exposed portion by this, and further immersing this substrate in a plating solution containing the metal material to be plated, a metal film is formed on the plating catalyst material to form a drain electrode and a source electrode Is described.
  • Patent Document 2 a resist film having an opening in a region where a source electrode and a drain electrode are to be formed on a substrate is formed, and after pretreatment of the substrate exposed in the opening of the resist film, It is described that a metal film is deposited on a substrate exposed at an opening of a resist film to form a source electrode and a drain electrode by immersing the substrate after these treatments in a plating bath by adsorbing a catalyst on the substrate. ing.
  • a method for forming a metal wiring of a semiconductor element there are a sputtering method and a vapor deposition method. However, since these methods require processing under high vacuum, the scale of the apparatus is increased and the cost is increased. On the other hand, according to the plating method, since a vacuum process is not required, the apparatus scale can be made relatively small.
  • a plating method for forming a metal wiring of a semiconductor element an electroplating method and an electroless plating method are known.
  • Electroplating uses an electrochemical reaction in which metal ions are discharged and deposited on the surface of the cathode (material to be plated) by energizing the material to be plated as a cathode in an electrolytic solution containing the metal ions to be plated. It is a thing. As described above, in the electroplating method, since it is necessary to energize the portion to be plated, in the case of a wiring pattern in which an electrically independent portion is generated, it is difficult to perform plating on the wiring. There is. For example, the wiring of an organic EL drive circuit has an electrically independent portion, so that it is often difficult to form the wiring by an electroplating method.
  • the electroless plating method does not need to be energized, and after a catalyst is adsorbed to a material to be plated containing an organic material, a uniform film can be obtained by immersing it in a plating solution. it can. For this reason, it can be said that the electroless plating method is a process suitable for forming wiring of a drive circuit such as an organic EL.
  • a p-type semiconductor material such as pentacene or P3HT (poly (3-hexylthiophene)
  • P3HT poly (3-hexylthiophene)
  • these materials have a relatively high ionization potential, it is preferable to select a material having a relatively high work function as the source / drain electrode wiring in accordance with the ionization potential of the organic semiconductor material. This is because when the gap between the ionization potential of the organic semiconductor material and the work function of the electrode material is increased, a Schottky barrier is formed at these interfaces.
  • the manufacturing cost is significantly increased.
  • the area of the wiring portion usually reaches 10% or more of the substrate area. Will be used, resulting in a significant increase in manufacturing costs.
  • the amount of Au used is increased, the replenishment / replacement cycle of the plating solution is shortened and the running cost is increased.
  • the present invention has been made in view of the above points, and a specific metal (mainly a noble metal) introduced into the source / drain electrode in order to control the electrical contact between the source / drain electrode and the organic semiconductor material.
  • An object of the present invention is to provide a semiconductor device capable of suppressing the amount of the specific metal used and a method for manufacturing the same when forming the film by electroless plating.
  • the semiconductor device of the present invention is a semiconductor device including at least one organic thin film transistor, the gate electrode formed on a substrate, a gate insulating film formed so as to cover the gate electrode, and the gate insulating film A pair of source / drain electrodes extending from the top of the gate electrode to the substrate and having a separation portion above the gate electrode, and the gate insulating film exposed at the separation portion and An organic semiconductor layer provided in contact with a pair of source / drain electrodes; and a partition wall provided at a position sandwiching the organic semiconductor layer on the pair of source / drain electrodes, the source / drain electrodes Includes a first electrode layer extending from the upper part of the gate electrode to the upper part of the substrate, and the first electrode not covered with the partition wall. It is characterized in that it comprises a second electrode layer formed and in contact with the organic semiconductor layer, a by electroless plating on a part of.
  • the second electrode layer preferably includes a portion in contact with the channel region of the organic semiconductor layer.
  • the contact between the second electrode layer and the organic semiconductor layer is preferably ohmic contact.
  • the second electrode layer can be formed by a displacement plating method or a combination of a displacement plating method and a reduction plating method.
  • the second electrode layer is preferably made of a material having a smaller ionization tendency than the constituent material of the first electrode layer.
  • the second electrode layer is made of a noble metal or an alloy containing a noble metal. For example, gold or an alloy containing gold can be used. It is preferable that the partition wall has liquid repellency.
  • the method for manufacturing a semiconductor device is a method for manufacturing a semiconductor device including an organic thin film transistor, the step of forming a gate electrode on a substrate, and the step of forming a gate insulating film so as to cover the gate electrode.
  • a step of forming a first electrode layer on the gate insulating film extending from the upper part of the gate electrode to the upper part of the substrate and having a separation part on the upper part of the gate electrode, and corresponding to the gate electrode formation position A step of forming a partition wall having an opening in the portion on the first electrode layer, and one of the first electrode layers exposed in the opening by an electroless plating method using the partition wall as a mask.
  • Forming a second electrode layer so as to cover the portion, and in contact with the gate insulating film and the second electrode layer exposed in the opening of the first electrode layer in the opening It is characterized in that it comprises the steps of forming an organic semiconductor layer as.
  • the liquid repellent bank provided to ensure the accuracy of the formation position of the organic semiconductor layer is also used as a mask in the plating process.
  • the plating treatment part mainly made of noble metal introduced into the source / drain electrode is partly including the part where the source / drain electrode is in contact with the organic semiconductor layer. Therefore, the amount of the precious metal used can be suppressed, and the manufacturing cost and running cost can be suppressed.
  • FIG. 1 is a cross-sectional view showing a configuration of an organic EL drive circuit 100 according to an embodiment of the present invention.
  • the organic EL drive circuit 100 includes an organic TFT 1 that functions as a switching transistor, an organic TFT 2 that functions as a drive transistor, and an organic EL 3 that functions as a light emitting unit.
  • FIG. 2 is an equivalent circuit diagram of the organic EL drive circuit 100 corresponding to FIG.
  • the gate electrode 11a of the organic TFT 1 is connected to a scanning line that transmits a scan pulse
  • the source electrode 13 is connected to a data line that transmits a data signal corresponding to a display image or the like
  • the drain electrode 14 is connected to the gate electrode 11b of the organic TFT 2 and Connected to the storage capacitor 4.
  • the source electrode 15 of the organic transistor 2 is connected to the power supply line, and the drain electrode 16 is connected to the anode 31 of the organic EL 3.
  • the cathode 33 of the organic EL 3 is fixed at, for example, the ground
  • the organic TFT 1 and the organic TFT 2 are formed on the substrate 10 and have a so-called bottom contact structure.
  • a light transmissive material such as a glass substrate or a flexible plastic film is used.
  • the gate electrodes 11 a and 11 b of the organic TFT 1 and the organic TFT 2 are made of, for example, nickel phosphorus (Ni—P) and are provided on the substrate 10.
  • a gate insulating film 12 made of a polymer material in which, for example, PVP (Poly (4-vinylphenol)) and melamine are mixed is provided so as to cover them.
  • the source electrodes 13 and 15 and the drain electrodes 14 and 16 are first electrodes made of, for example, nickel phosphorus (Ni—P) extending from the gate electrode 11a or 11b to the substrate 10 through the gate insulating film 12, respectively.
  • the electrode layers 13a to 16a and second electrode layers 13b to 16b made of, for example, Au formed on a part of the first electrode layers 13a to 16a by an electroless plating method.
  • the source electrodes 13 and 15 and the drain electrodes 14 and 16 are separated from each other in the upper part of the gate electrodes 11a and 11b, respectively.
  • the drain electrode 14 of the organic TFT 1 is connected to the gate electrode 11 b of the organic TFT 2 via a contact hole provided in the gate insulating film 12.
  • an anode 31 of the organic EL 3 made of a transparent electrode material such as IZO (Indium Zinc Oxide) is provided on the gate insulating film 12.
  • the anode 31 of the organic EL 3 is connected to the drain electrode 16 of the organic TFT 2.
  • the organic semiconductor layers 17a and 17b are made of, for example, an organic semiconductor material such as tetrabenzoporphyrin, and the gate insulating film 12 exposed in the separated portions on the gate electrodes 11a and 11b of the source / drain electrodes, and the source / drain electrodes, respectively. 13, 14 or 15, 16 is provided. Regions sandwiched between the source electrodes 13 and 15 and the drain electrodes 14 and 16 in the organic semiconductor layers 17a and 17b become channel regions 18a and 18b.
  • an organic semiconductor material such as tetrabenzoporphyrin
  • a liquid repellent bank (partition wall) 20 is provided to separate these elements. That is, the liquid repellent bank 20 is provided at a position sandwiching the organic semiconductor layers 17a and 17b.
  • the liquid repellent bank 20 is made of, for example, an organic material such as photosensitive polyimide, and an opening is formed in the formation portion of the organic TFT 1, the organic TFT 2, and the organic EL 3 by an exposure / development process. Thereafter, the surface of the liquid repellent bank 20 is given liquid repellency by performing a surface treatment with CF 4 plasma or the like.
  • the liquid repellent bank 20 is formed on the first electrode layers 13a to 16a of the source / drain electrodes, and a part of the first electrode layers 13a to 16a and a separation portion of the source / drain electrodes in the opening thereof. A part of the gate insulating film 12 exposed in the step is exposed.
  • the liquid repellent bank 20 also serves as a mask when the second electrode layers 13b to 16b are formed on the first electrode layers 13a to 16a. That is, the second electrode layers 13b to 16b are formed only on a part of the first electrode layers 13a to 16a exposed in the openings of the liquid repellent bank 20 by the electroless plating method.
  • the second electrode layers 13b to 16b are formed only at portions where the source electrodes 13 and 15 and the drain electrodes 14 and 16 are in contact with the organic semiconductor layers 17a and 17b.
  • the second electrode layers 13b to 16b are introduced to control the contact between the organic semiconductors 17a and 17b and the source / drain electrodes, and the source electrodes 13 and 15 and the drain electrode 14 are introduced.
  • 16 are formed only in the portions in contact with the organic semiconductor layers 17a and 17b, the function is sufficiently exhibited.
  • the second electrode layers 13b to 16b are provided only on a part of the first electrode layers 13a to 16a including the portions in contact with the organic semiconductor layers 17a and 17b, so that Au It was decided to suppress the amount of use.
  • an interlayer insulating film 19 is provided so as to fill the opening of the liquid repellent bank 20.
  • An organic layer 32 forming a light emitting portion of the organic EL 3 is provided so as to extend on the liquid repellent bank 20, the interlayer insulating film 19, and the anode 31.
  • a cathode 33 made of, for example, Al is provided on the organic layer 32 so as to cover it.
  • FIGS. 4 (f) to (i) are cross-sectional views for each process step showing a manufacturing process of the organic EL driving circuit 100 according to the embodiment of the present invention.
  • a substrate 10 made of a glass substrate or a flexible plastic film is prepared. Before forming each element on the substrate 10, it may be cleaned with a cleaning liquid containing pure water, a surfactant or the like to remove oils and fats attached to the surface of the substrate 10.
  • the surface of the substrate 10 is roughened to improve the adhesion between the substrate 10 and the gate electrode 11 by the anchor effect. Specifically, fine irregularities are formed on the surface of the substrate 10 by etching the substrate 10 using an etching solution such as a chromic acid / sulfuric acid mixed solution. Thereafter, the chromium compound remaining on the surface of the substrate 10 is removed using hydrochloric acid or the like.
  • a catalyst serving as a nucleus of electroless plating for forming the gate electrode 11 is adsorbed on the substrate 10.
  • a Pd—Sn complex can be used as the catalyst.
  • substrate 10 is immersed in an acid solution, a tin salt is dissolved, and metal palladium is produced
  • the substrate 10 is immersed in a plating bath containing nickel sulfate and sodium hypophosphite to form a plating film made of nickel phosphorus (Ni—P) on the surface of the substrate 10.
  • the plating film formed on the substrate 10 is patterned using a known photolithography technique to form gate electrodes 11a and 11b (FIG. 3A).
  • a surface roughening process is performed on the substrate 10 using a mask corresponding to the pattern of the gate electrodes 11 a and 11 b.
  • the gate electrodes 11a and 11b may be patterned by allowing the catalyst to be adsorbed only in the portions where the etching is performed and selectively forming a plating film on the portions. Further, after the surface roughening treatment of the substrate 10 is performed, the surface of the substrate 10 is irradiated with plasma through a mask corresponding to the pattern of the gate electrodes 11a and 11b, thereby reducing the adsorption power to the catalyst.
  • Patterning of the gate electrodes 11a and 11b may be performed by performing a reforming process so that the catalyst is adsorbed only in a portion not irradiated with plasma and a plating film is selectively formed in this portion.
  • the gate electrodes 11a and 11b may be patterned by drawing a silane coupling agent having a catalytic function by an ink-jet method and selectively forming a plating film only on a portion where the silane coupling agent is present. .
  • the gate insulating film 12 is formed so as to cover the gate electrodes 11a and 11b.
  • an appropriate amount of a polymer material in which melamine is mixed with PVP (Poly (4-vinylphenol)) is dropped onto the gate electrode, a film is formed by a spin coating method, and the gate insulating film 12 is formed by subjecting it to heat treatment and curing. It forms (FIG.3 (b)).
  • a contact hole (not shown) for connecting the drain electrode 14 of the organic TFT 1 and the gate electrode 11 b of the organic TFT 2 is provided in the gate insulating film 12.
  • first electrode layers 13a to 16a made of nickel phosphorus (Ni—P) constituting the source electrodes 13 and 15 and the drain electrodes 14 and 16 are formed on the gate insulating film 12 by an electroless plating method.
  • the process of forming the nickel phosphorus (Ni—P) plating film by the electroless plating method is the same as the process of forming the gate electrodes 11a and 11b. That is, the gate insulating film 12 is roughened as necessary, a catalyst made of a Pd—Sn complex is adsorbed on the gate insulating film 12, an accelerator treatment with an acid solution is performed, and then the substrate 10 is nickel sulfate. And soak in a plating bath containing sodium hypophosphite.
  • a plating film made of nickel phosphorus (Ni—P) is formed on the substrate 10 and the gate electrode 11 via the gate insulating film 12.
  • the first electrode layers 13a to 16b are patterned by a known photolithography technique.
  • openings (separation portions) 30 for forming the channel regions 18a and 18b of the organic TFT are provided in the nickel phosphorus (Ni—P) plating film formed on the gate electrodes 11a and 11b, and the like.
  • a wiring pattern of the source / drain electrodes is formed.
  • the gate insulating film 12 located on the gate electrodes 11a and 11b is exposed in the opening (separation part) 30.
  • the first electrode layer 14 a of the organic TFT 1 is connected to the gate electrode 11 b of the organic TFT 2 via a contact hole (not shown) formed in the gate insulating film 12.
  • the first electrode layers 13a to 16a As a method of patterning the first electrode layers 13a to 16a, in addition to the above-described method, for example, a roughening process of the gate insulating film 12 is performed using a mask corresponding to the pattern of the source / drain electrodes.
  • the first electrode layers 13a to 16a may be patterned by adsorbing the catalyst only on the roughened portion and selectively forming a plating film on this portion.
  • the surface of the gate insulating film 12 is irradiated with plasma through a mask corresponding to the pattern of the source / drain electrodes, thereby reducing the adsorption power to the catalyst.
  • the first electrode layers 13a to 16a may be patterned by causing the catalyst to be adsorbed only on a portion not irradiated with plasma and selectively forming a plating film on this portion. Good.
  • the first electrode layers 13a to 16a are patterned by drawing a silane coupling agent having a catalytic function by an ink-jet method and selectively forming a plating film only on a portion where the silane coupling agent exists. It is good.
  • an IZO film which is a transparent electrode material, is formed on the gate insulating film 12 by, for example, a sputtering method, and patterned by a known photolithography technique to form the anode 31 of the organic EL 2.
  • the anode 31 is connected to the first electrode layer 16a of the organic TFT 2 (FIG. 3C).
  • an ITO (Indium Tin Oxide) film or the like may be used in addition to the IZO film.
  • a liquid repellent bank (partition wall) 20 is formed to separate the organic TFT 1, the organic TFT 2, and the organic EL 3.
  • a photosensitive polyimide film is formed by spin coating on the substrate on which the formation of the first electrode layers 13a to 16a has been completed, and the pattern of the liquid repellent bank 20 is applied to the photosensitive polyimide film.
  • the opening 21 is formed in a portion corresponding to the formation portion of the gate electrodes 11a and 11b and the formation portion of the anode 31.
  • the gate insulating film 12 exposed at the separation portion 30 of the first electrode layer, the tip portions of the first electrode layers 13a to 16a, and the anode 31 of the organic EL 3 are exposed.
  • the photosensitive polyimide film is subjected to a surface treatment using, for example, CF 4 plasma (FIG. 3D).
  • oxygen plasma treatment may be performed on the inner wall surface of the opening 21.
  • the second electrode layers 13b to 16b made of Au are selectively formed only at the tips of the first electrode layers 13a to 16a exposed at the openings 21 of the liquid repellent bank 20 by electroless plating.
  • the second electrode layers 13b to 16b are formed by using, for example, a substitution Au plating method and a reduction Au plating method in combination.
  • the substitution Au plating method uses the difference between the ionization tendency of the base metal to be plated and the ionization tendency of Au as the plating material, and the first electrode layers 13a to 16a made of nickel phosphorus (Ni-P).
  • An Au plating film is formed on the first electrode layers 13a to 16a by immersing the substrate 10 on which is formed in a cyan or non-cyan substitution gold plating bath.
  • the underlying nickel phosphorus (Ni—P) which has a relatively high ionization tendency, dissolves, and a reaction occurs in which Au precipitates on the nickel phosphorus (Ni—P).
  • the reaction stops when the underlying nickel phosphorus (Ni—P) is coated with Au, so that the deposited Au film becomes thin. Therefore, in this embodiment, the reduced Au plating process is performed subsequent to the replacement Au plating process to secure the film thickness of the Au plating film.
  • the reduced Au plating method is a plating method in which electrons released by oxidation of a reducing agent contained in a plating bath are transferred to Au ions to form an Au film on a material to be plated.
  • the first electrode layer in which the substituted Au plating film is formed by immersing the substrate 10 in a plating bath using potassium tetrahydroborate (KBH 4 ) or the like as a reducing agent and KAu (CN) 2 as a gold salt.
  • KH 4 potassium tetrahydroborate
  • KAu (CN) 2 as a gold salt.
  • a reduced Au plating film is further formed on 13a to 16a.
  • the first electrode layers 13a to 16a are exposed only at the opening 21 of the liquid repellent bank 20 formed in the previous step. Therefore, the first electrode layers 13a to 16a are exposed to the plating solution only in the exposed portion in the replacement Au plating step and the reduced Au plating step, and the second electrode layers 13b to 16b are exposed only to the exposed portion. Is formed. In this way, the second electrode layer is formed on the first electrode layers 13a to 16a, and the source electrodes 13 and 15 and the drain electrodes 14 and 16 are completed (FIG. 3E).
  • organic semiconductor layers 17a and 17b are formed in the opening 21 of the liquid repellent bank 20 by an ink jet method.
  • the ink jet method is a printing method in which a solution containing an organic semiconductor material is discharged from a nozzle to form a pattern, and can be formed in a non-contact manner with respect to the substrate 10 and can be printed over a wide area. Since it has an advantage that the amount of material can be minimized and high discharge position accuracy can be secured, it is a method suitable for film formation of an organic TFT. Furthermore, since the liquid repellent bank 20 is provided to separate the elements, the flight of the organic semiconductor material discharged from the nozzle is caused by the variation inherent in the head or the characteristics of the organic semiconductor material.
  • the landing error of all the droplets is corrected by the force of the surface energy, and the droplets are accommodated in the openings 21 of the liquid repellent bank 20. Thereafter, post-treatment such as heat treatment is performed on the coating film of the organic semiconductor material as necessary.
  • the organic semiconductor layers 17a and 17b are provided at the bottom of the opening 21 of the liquid repellent bank 20 so as to be in contact with the source electrodes 13 and 15, the drain electrodes 14 and 16 and the gate insulating film 12 (FIG. 4F). .
  • the interlayer insulation 19 is filled in the opening 21 of the liquid repellent bank 20 so as to cover the organic semiconductor layers 17a and 17b formed in the opening 21 of the liquid repellent bank 20.
  • the interlayer insulating film 19 can be formed using, for example, a polymer material in which the same PVP and melamine as the gate insulating film 12 are mixed using an ink jet method (FIG. 4G).
  • the organic layer 32 constituting the organic EL 3 is formed on the substrate.
  • PEDOT which is a conductive polymer
  • PPV polyparaphenylene vinylene
  • a film is formed and dried to form a light emitting layer (FIG. 4H).
  • Al is deposited on the organic layer 32 by, for example, a vacuum evaporation method or the like to form the cathode 33 of the organic EL 3 (FIG. 4 (i)). Thereafter, the elements formed on the substrate are sealed as necessary to complete the organic EL drive circuit 100.
  • the liquid repellent bank 20 provided to ensure the accuracy of the formation position of the organic semiconductor layers 17a and 17b is replaced with the second electrode layers 13b to 16b.
  • the second electrode layers 13b to 16b are also used as masks when forming using the electroless plating method, and the second electrode layers 13b to 16b are formed only in the portions where the source electrodes 13 and 15 and the drain electrodes 14 and 16 are in contact with the organic semiconductor layers 17a and 17b. Since it is formed, the amount of metal (mainly noble metal) constituting the second electrode layers 13b to 16b is suppressed as compared with the case where the entire surface of the first electrode layers 13a to 16b is plated. The manufacturing cost can be reduced.
  • the organic TFTs are formed in an array to form a drive circuit for an organic EL that constitutes the pixels of the display panel
  • the amount of Au used is suppressed to about several percent of the conventional one. And a significant cost reduction effect can be achieved.
  • the exchange cycle of a plating bath can be lengthened by this, a running cost can also be suppressed.
  • the liquid repellent bank 20 is used as a mask, a process for patterning the second electrode layers 13b to 16b is unnecessary.
  • the second electrode layers 13b to 16b are introduced for the purpose of controlling electrical contact between the source / drain electrodes and the organic semiconductor layer, and at least a portion in contact with the channel region of the organic semiconductor layer. If it is formed, the function is exhibited. Therefore, there is no adverse effect on the electrical characteristics due to the restriction of the formation region of the second electrode layer 14.
  • Au is used for the second electrode layers 13b to 16b.
  • the present invention is not limited to this.
  • noble metals such as copper (Cu) or alloys thereof. In this case, it is preferable to select a material having a work function approximate to the ionization potential of the organic semiconductor layers 17a and 17b.
  • the second electrode layers 13b to 16b are formed by using both displacement plating and reduction plating. However, in the case where the film thickness of the second electrode layers 13b to 16b can be reduced. Alternatively, the second electrode layers 13b to 16b may be formed only by displacement plating. In the above embodiment, the displacement plating and the reduction plating are each performed once. However, the plurality of layers may be formed by repeating the displacement plating and the reduction plating.
  • nickel phosphorus is used as the first electrode layers 13a to 16a.
  • the present invention is not limited to this, and the ionization tendency is larger than that of the second electrode layers 13b to 16b.
  • a plating material either a simple substance or an alloy can be used.
  • the first electrode layers 13a to 16a are not limited to the electroless plating method, and after the electrode material is formed by a sputtering method, a CVD method, a vacuum evaporation method, or the like, a desired patterning is performed by a photolithography technique or the like. It may be formed. Alternatively, the first electrode layers 13a to 16a may be formed by ejecting metal nano-ink in a line shape by an inkjet method. Further, the same modification can be made for the material and forming method of the gate electrodes 11a and 11b.
  • tetrabenzoporphyrin is used as the material of the organic semiconductor layers 17a and 17b.
  • the present invention is not limited to this, and other organic semiconductor materials can also be used.
  • organic semiconductor materials for low molecular weight materials, phthalocyanine derivatives, naphthalocyanine derivatives, azo compound derivatives, perylene derivatives, indigo derivatives, quinacridone derivatives, polycyclic quinone derivatives such as anthraquinones, cyanine derivatives, fullerene derivatives Or nitrogen-containing cyclic compound derivatives such as indole, carbazole, oxazole, inoxazole, thiazole, imidazole, pyrazole, oxadiazole, pyrazoline, thiathiazole, triazole, hydrazine derivative, triphenylamine derivative, triphenylmethane derivative, stilbene Quinone compound derivatives such as anthraquinone diphenoquinone, and poly
  • the structure of the low molecular compound mentioned above is pendant as an object or side chain used in the polymer main chain such as polyethylene chain, polysiloxane chain, polyether chain, polyester chain, polyamide chain, polyimide chain, etc.
  • Aromatic conjugated polymers such as polyparaphenylene, aliphatic conjugated polymers such as polyacetylene, heterocyclic conjugated polymers with polypinol and polythiophene ratios, polyanilines and polyphenylene sulfide, etc.
  • Hetero-atom conjugated polymers of this type complex type conjugated systems having a structure in which structural units of conjugated polymers such as poly (phenylene vinylene), poly (annelen vinylene) and poly (chenylene vinylene) are alternately bonded Carbon-based conjugated polymers such as molecules can be used.
  • polymers containing oligosilanes and carbon-based conjugated structures such as polysilanes, disilanylene-arylene polymers, and disilanylene carbon-based conjugated polymer structures such as (disilanylene) ethynylene polymers Can be used.
  • polymer chains made of inorganic elements such as phosphorus and nitrogen may be used, and polymers having aromatic chain ligands such as phthalocyanate polysiloxane coordinated, perylenetetracarboxylic Polymers in which perylenes such as acids are heat-treated and condensed, ladder-type polymers obtained by heat-treating polyethylene derivatives having a cyano group such as polyacrylonitrile, and organic compounds intercalated in perovskites
  • the composite material may be used.
  • a polymer material in which PVP and melamine are mixed is used as the material of the gate insulating film 12 and the interlayer insulating film 19.
  • Membranes can also be used.
  • the gate insulating film may be formed by anodizing the gate electrode.
  • simple substances such as Ta, Al, Mg, Ti, Nb, Zr, or alloys thereof are effective.
  • polymer materials such as polyimide, polyamide, polyester, polyacrylate, epoxy resin, phenol resin, and polyvinyl alcohol.
  • the surface of the gate insulating film may be subjected to water repellent treatment using OTS, HMDS, or the like.
  • the structure of the driving circuit in which the organic TFT and the organic EL are formed on the same plane is shown.
  • the present invention is not limited to this.
  • an interlayer as a smoothing layer is formed on the organic TFT.
  • a laminated structure in which an insulating film is provided and an organic EL is formed on the interlayer insulating film may be employed.
  • the device driven by the organic TFT may be a liquid crystal element or other devices.

Abstract

Disclosed is a semiconductor device wherein the amount of a specific metal (mainly a noble metal) introduced into a source/drain electrode for controlling electrical contact between the source/drain electrode and an organic semiconductor material can be suppressed when the metal is deposited by electroless plating.  A method for manufacturing the semiconductor device is also disclosed. A gate electrode is formed on a substrate.  A gate insulating film is so formed as to cover the gate electrode.  A first electrode layer is so formed on the gate insulating film as to extend from the position above the gate electrode to the position above the substrate, while being separated at the position above the gate electrode.  A partition wall having an opening at the position corresponding to the gate electrode-forming position is formed on the first electrode layer.  A second electrode layer is formed by electroless plating using the partition wall as a mask so as to cover a part of the first electrode exposed from the opening.  An organic semiconductor layer is so formed within the opening as to be in contact with the gate insulating electrode exposed from the separated portion of the first electrode layer and the second electrode layer.

Description

半導体装置および半導体装置の製造方法Semiconductor device and manufacturing method of semiconductor device
　本発明は半導体装置に関し、特に無電解めっき法を使用した有機薄膜トランジスタの電極形成方法に関する。 The present invention relates to a semiconductor device, and more particularly to a method for forming an electrode of an organic thin film transistor using an electroless plating method.
　現在、有機半導体を使った有機薄膜トランジスタ（以下、有機ＴＦＴ（Thin Film Transistor）と称する）の開発が活発化している。有機ＴＦＴは、デバイス特性においてはシリコン等の無機材料と比べて劣るものの、軽量、フレキシブル、低温プロセスが可能である、印刷による形成が可能であるといった特徴を有していることから電子ペーパやフレキシブルディスプレイ等のユニークな用途が拓けるものと期待されている。 Currently, the development of organic thin film transistors using organic semiconductors (hereinafter referred to as organic TFT (Thin Film Transistor)) has become active. Although organic TFT is inferior to inorganic materials such as silicon in device characteristics, it has features such as light weight, flexibility, low temperature process, and formation by printing. It is expected to open up unique uses such as displays.
　有機ＴＦＴは電界効果トランジスタ（ＦＥＴ）の一種であり、基本的にはドレイン、ソース、ゲートからなる三端子素子である。有機ＴＦＴのドレイン、ソース、ゲート端子として機能する金属配線の形成にはめっき法が用いられる場合がある。めっき法を用いて金属配線を形成する場合のパターニング方法としては、以下のようなものがある。 Organic TFT is a kind of field effect transistor (FET), which is basically a three-terminal element consisting of a drain, a source and a gate. In some cases, a plating method is used to form metal wirings that function as the drain, source, and gate terminals of the organic TFT. As a patterning method in the case of forming a metal wiring by using a plating method, there are the following methods.
　特許文献１には、透光性基板上にゲート電極、ゲート絶縁層および光触媒物質を順次形成した後、この基板をめっき触媒物質を含む溶液中に浸漬した状態で選択的に基板を露光することにより露光部分の光触媒物質上にめっき触媒物質を析出させ、さらにこの基板をめっきしようとする金属材料を含むめっき液に浸漬することによりめっき触媒物質上に金属膜を形成してドレイン電極およびソース電極を形成することが記載されている。 In Patent Document 1, a gate electrode, a gate insulating layer, and a photocatalytic material are sequentially formed on a light-transmitting substrate, and then the substrate is selectively exposed in a state where the substrate is immersed in a solution containing a plating catalyst material. By depositing a plating catalyst material on the photocatalyst material of the exposed portion by this, and further immersing this substrate in a plating solution containing the metal material to be plated, a metal film is formed on the plating catalyst material to form a drain electrode and a source electrode Is described.
　特許文献２には、基板上のソース電極およびドレイン電極を形成すべき領域において開口部を有するレジスト膜を形成し、このレジスト膜の開口部において露出した基板の前処理を行った後、この部位に触媒を吸着させ、これらの処理を経た基板をめっき浴中に浸漬することによりレジスト膜の開口部において露出した基板上に金属膜を析出させてソース電極およびドレイン電極を形成することが記載されている。 In Patent Document 2, a resist film having an opening in a region where a source electrode and a drain electrode are to be formed on a substrate is formed, and after pretreatment of the substrate exposed in the opening of the resist film, It is described that a metal film is deposited on a substrate exposed at an opening of a resist film to form a source electrode and a drain electrode by immersing the substrate after these treatments in a plating bath by adsorbing a catalyst on the substrate. ing.
特開２００７－５９８９３号公報JP 2007-59893 A 特開２００５－１５０６４０号公報JP 2005-150640 A
　半導体素子の金属配線を形成する手法としては、従来からスパッタ法や蒸着法等がある。しかしながら、これらの手法は高真空下での処理を要するため装置規模が大きくなり、コストがかかる。一方、めっき法によれば、真空プロセスを要しないため装置規模を比較的小さくできる。半導体素子の金属配線を形成すためのめっき法としては、電気めっき法および無電解めっき法が知られている。電気めっきは、めっきしようとする金属イオンを含む電解溶液中で、被めっき材を陰極として通電することにより、金属イオンが陰極(被めっき材)の表面で放電して析出する電気化学反応を利用したものである。このように、電気めっき法においては、めっきしようとする部分を通電する必要があることから、電気的に独立した部分が生じる配線パターンの場合、当該配線にめっき処理を施すことが困難となる場合がある。例えば有機ＥＬの駆動回路の配線は、電気的に独立した部分が生じるため、電気めっき法で形成することは困難となることが多い。 Conventionally, as a method for forming a metal wiring of a semiconductor element, there are a sputtering method and a vapor deposition method. However, since these methods require processing under high vacuum, the scale of the apparatus is increased and the cost is increased. On the other hand, according to the plating method, since a vacuum process is not required, the apparatus scale can be made relatively small. As a plating method for forming a metal wiring of a semiconductor element, an electroplating method and an electroless plating method are known. Electroplating uses an electrochemical reaction in which metal ions are discharged and deposited on the surface of the cathode (material to be plated) by energizing the material to be plated as a cathode in an electrolytic solution containing the metal ions to be plated. It is a thing. As described above, in the electroplating method, since it is necessary to energize the portion to be plated, in the case of a wiring pattern in which an electrically independent portion is generated, it is difficult to perform plating on the wiring. There is. For example, the wiring of an organic EL drive circuit has an electrically independent portion, so that it is often difficult to form the wiring by an electroplating method.
　一方、無電解めっき法は、電気めっき法と異なり、通電する必要はなく、有機材料を含む被めっき材に触媒を吸着させた後、これをめっき液に浸漬すれば均一な皮膜を得ることができる。このため、無電解めっき法は、有機ＥＬ等の駆動回路の配線の形成に適したプロセスであるといえる。 On the other hand, unlike the electroplating method, the electroless plating method does not need to be energized, and after a catalyst is adsorbed to a material to be plated containing an organic material, a uniform film can be obtained by immersing it in a plating solution. it can. For this reason, it can be said that the electroless plating method is a process suitable for forming wiring of a drive circuit such as an organic EL.
　有機ＴＦＴを構成する有機半導体層の材料としては、一般的にペンタセンやＰ３ＨＴ（ポリ（３－ヘキシルチオフェン））等のｐ型半導体材料が用いられる。これらの材料はイオン化ポテンシャルが比較的大きいため、ソース／ドレイン電極配線としては、有機半導体材料のイオン化ポテンシャルに応じて比較的仕事関数の高い材料を選択することが好ましい。これは、有機半導体材料のイオン化ポテンシャルと電極材料の仕事関数のギャップが大きくなると、これらの界面においてショットキー障壁が形成されてしまうからである。有機ＴＦＴの構成材料となり得る既存の有機半導体材料のイオン化ポテンシャルを考慮すると、ソース／ドレイン電極配線の材料としては、化学特性および電気特性にも優れるＡｕ（仕事関数４．７ｅＶ）が候補の１つとして挙げられる。 As a material for the organic semiconductor layer constituting the organic TFT, a p-type semiconductor material such as pentacene or P3HT (poly (3-hexylthiophene)) is generally used. Since these materials have a relatively high ionization potential, it is preferable to select a material having a relatively high work function as the source / drain electrode wiring in accordance with the ionization potential of the organic semiconductor material. This is because when the gap between the ionization potential of the organic semiconductor material and the work function of the electrode material is increased, a Schottky barrier is formed at these interfaces. Considering the ionization potential of the existing organic semiconductor material that can be a constituent material of the organic TFT, Au (work function 4.7 eV) having excellent chemical characteristics and electrical characteristics is one of the candidates as a material of the source / drain electrode wiring. As mentioned.
　しかしながら、Ａｕは非常に高価であり、配線材料に多量のＡｕを使用すると製造コストの著しい上昇を招く。回路構成にもよるが、例えば、有機ＥＬ表示パネルの駆動回路の場合、通常、配線部分の面積は基板面積の１０％以上にも及ぶため、従来の製造プロセスによれば、相当な量のＡｕが使用されることとなり、製造コストの著しい上昇を招く。また、Ａｕの使用量が多くなると、めっき液の補充／交換サイクルが短くなりランニングコストも高くなる。 However, Au is very expensive, and if a large amount of Au is used as the wiring material, the manufacturing cost is significantly increased. Depending on the circuit configuration, for example, in the case of a drive circuit for an organic EL display panel, the area of the wiring portion usually reaches 10% or more of the substrate area. Will be used, resulting in a significant increase in manufacturing costs. Further, when the amount of Au used is increased, the replenishment / replacement cycle of the plating solution is shortened and the running cost is increased.
　本発明は上記した点に鑑みてなされたものであり、ソース／ドレイン電極と有機半導体材料との電気的接触性をコントロールするためにソース／ドレイン電極に導入される特定の金属（主に貴金属）を無電解めっき法により形成する場合において、当該特定の金属の使用量を抑制することが可能な半導体装置およびその製造方法を提供することを目的とする。 The present invention has been made in view of the above points, and a specific metal (mainly a noble metal) introduced into the source / drain electrode in order to control the electrical contact between the source / drain electrode and the organic semiconductor material. An object of the present invention is to provide a semiconductor device capable of suppressing the amount of the specific metal used and a method for manufacturing the same when forming the film by electroless plating.
　本発明の半導体装置は、少なくとも１つの有機薄膜トランジスタを含む半導体装置であって、基板上に形成された前記ゲート電極と、前記ゲート電極を覆うように形成されたゲート絶縁膜と、前記ゲート絶縁膜を介して前記ゲート電極の上部から前記基板上まで延在し、且つ前記ゲート電極の上部において離間部を有する一対のソース／ドレイン電極と、前記離間部において露出している前記ゲート絶縁膜および前記一対のソース／ドレイン電極と接するように設けられた有機半導体層と、前記一対のソース／ドレイン電極上の前記有機半導体層を挟む位置に設けられた隔壁部と、を含み、前記ソース／ドレイン電極は、前記ゲート電極上部から前記基板上部まで延在している第１の電極層と、前記隔壁部で覆われていない前記第１の電極層の一部に無電解めっき法により形成され且つ前記有機半導体層と接している第２の電極層と、を含むことを特徴としている。 The semiconductor device of the present invention is a semiconductor device including at least one organic thin film transistor, the gate electrode formed on a substrate, a gate insulating film formed so as to cover the gate electrode, and the gate insulating film A pair of source / drain electrodes extending from the top of the gate electrode to the substrate and having a separation portion above the gate electrode, and the gate insulating film exposed at the separation portion and An organic semiconductor layer provided in contact with a pair of source / drain electrodes; and a partition wall provided at a position sandwiching the organic semiconductor layer on the pair of source / drain electrodes, the source / drain electrodes Includes a first electrode layer extending from the upper part of the gate electrode to the upper part of the substrate, and the first electrode not covered with the partition wall. It is characterized in that it comprises a second electrode layer formed and in contact with the organic semiconductor layer, a by electroless plating on a part of.
　前記第２の電極層は、前記有機半導体層のチャネル領域と接する部分を含んでいることが好ましい。また、前記第２の電極層と前記有機半導体層との接触は、オーミック性接触であることが好ましい。また、前記第２の電極層は、置換めっき法または、置換めっき法および還元めっき法を併用して形成することができる。前記第２の電極層は、前記第１の電極層の構成材料よりもイオン化傾向の小さい材料が用いられることが好ましい。前記第２の電極層は、貴金属または貴金属を含む合金からなり、例えば金または金を含む合金を使用することができる。前記隔壁部は、撥液性を有することが好ましい。 The second electrode layer preferably includes a portion in contact with the channel region of the organic semiconductor layer. The contact between the second electrode layer and the organic semiconductor layer is preferably ohmic contact. The second electrode layer can be formed by a displacement plating method or a combination of a displacement plating method and a reduction plating method. The second electrode layer is preferably made of a material having a smaller ionization tendency than the constituent material of the first electrode layer. The second electrode layer is made of a noble metal or an alloy containing a noble metal. For example, gold or an alloy containing gold can be used. It is preferable that the partition wall has liquid repellency.
　また、本発明の半導体装置の製造方法は、有機薄膜トランジスタを含む半導体装置の製造方法であって、基板上にゲート電極を形成する工程と、前記ゲート電極を覆うようにゲート絶縁膜を形成する工程と、前記ゲート絶縁膜上に前記ゲート電極上部から前記基板上部まで延在し、且つ前記ゲート電極上部において離間部を有する第１の電極層を形成する工程と、前記ゲート電極形成位置に対応する部分に開口部を有する隔壁部を前記第１の電極層の上に形成する工程と、前記隔壁部をマスクとして無電解めっき法により前記開口部において露出している前記第１の電極層の一部を覆うように第２の電極層を形成する工程と、前記開口部内に、前記第１の電極層の離間部において露出している前記ゲート絶縁膜と前記第２の電極層とに接するように有機半導体層を形成する工程と、を含むことを特徴としている。 The method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device including an organic thin film transistor, the step of forming a gate electrode on a substrate, and the step of forming a gate insulating film so as to cover the gate electrode. A step of forming a first electrode layer on the gate insulating film extending from the upper part of the gate electrode to the upper part of the substrate and having a separation part on the upper part of the gate electrode, and corresponding to the gate electrode formation position A step of forming a partition wall having an opening in the portion on the first electrode layer, and one of the first electrode layers exposed in the opening by an electroless plating method using the partition wall as a mask. Forming a second electrode layer so as to cover the portion, and in contact with the gate insulating film and the second electrode layer exposed in the opening of the first electrode layer in the opening It is characterized in that it comprises the steps of forming an organic semiconductor layer as.
　本発明の半導体装置および半導体装置の製造方法によれば、有機半導体層の形成位置の精度を確保するために設けられる撥液性バンクをめっき処理の際のマスクとしても使用し、有機半導体層とソース／ドレイン電極との電気的接触性をコントロールするためにソース／ドレイン電極に導入される主に貴金属からなるめっき処理部を、ソース／ドレイン電極が有機半導体層と接触する部分を含む一部にのみ形成することとしたので、当該貴金属の使用量を抑制することが可能となり製造コストおよびランニングコストを抑えることが可能となる。 According to the semiconductor device and the method for manufacturing a semiconductor device of the present invention, the liquid repellent bank provided to ensure the accuracy of the formation position of the organic semiconductor layer is also used as a mask in the plating process. In order to control the electrical contact with the source / drain electrode, the plating treatment part mainly made of noble metal introduced into the source / drain electrode is partly including the part where the source / drain electrode is in contact with the organic semiconductor layer. Therefore, the amount of the precious metal used can be suppressed, and the manufacturing cost and running cost can be suppressed.
本発明の実施例である有機ＥＬ駆動回路の構造を示す断面図である。It is sectional drawing which shows the structure of the organic electroluminescent drive circuit which is an Example of this invention. 本発明の実施例である有機ＥＬ駆動回路の等価回路図である。It is an equivalent circuit diagram of the organic EL drive circuit which is an embodiment of the present invention. 図３（ａ）～（ｅ）は、本発明の実施例である有機ＥＬ駆動回路の製造方法を示す断面図である。3A to 3E are cross-sectional views showing a method for manufacturing an organic EL driving circuit according to an embodiment of the present invention. 図４（ｆ）～（ｉ）は、本発明の実施例である有機ＥＬ駆動回路の製造方法を示す断面図である。4 (f) to 4 (i) are cross-sectional views showing a method for manufacturing an organic EL drive circuit according to an embodiment of the present invention.
　以下、本発明の実施例について図面を参照しつつ説明する。尚、以下に示す図において、実質的に同一又は等価な構成要素、部分には同一の参照符を付している。 Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings shown below, substantially the same or equivalent components and parts are denoted by the same reference numerals.
　図１は、本発明の一実施形態である有機ＥＬ駆動回路１００の構成を示す断面図である。有機ＥＬ駆動回路１００は、スイッチングトランジスタとして機能する有機ＴＦＴ１と、駆動トランジスタとして機能する有機ＴＦＴ２と、発光部として機能する有機ＥＬ３とを含んでいる。図２は、図１に対応する有機ＥＬ駆動回路１００の等価回路図である。有機ＴＦＴ１のゲート電極１１ａはスキャンパルスを伝送する走査線に接続され、ソース電極１３は表示画像等に応じたデータ信号を伝送するデータ線に接続され、ドレイン電極１４は有機ＴＦＴ２のゲート電極１１ｂおよびストレージキャパシタ４に接続される。有機トランジスタ２のソース電極１５は、電源ラインに接続され、ドレイン電極１６は有機ＥＬ３の陽極３１に接続される。有機ＥＬ３の陰極３３は例えば接地電位に固定される。 FIG. 1 is a cross-sectional view showing a configuration of an organic EL drive circuit 100 according to an embodiment of the present invention. The organic EL drive circuit 100 includes an organic TFT 1 that functions as a switching transistor, an organic TFT 2 that functions as a drive transistor, and an organic EL 3 that functions as a light emitting unit. FIG. 2 is an equivalent circuit diagram of the organic EL drive circuit 100 corresponding to FIG. The gate electrode 11a of the organic TFT 1 is connected to a scanning line that transmits a scan pulse, the source electrode 13 is connected to a data line that transmits a data signal corresponding to a display image or the like, and the drain electrode 14 is connected to the gate electrode 11b of the organic TFT 2 and Connected to the storage capacitor 4. The source electrode 15 of the organic transistor 2 is connected to the power supply line, and the drain electrode 16 is connected to the anode 31 of the organic EL 3. The cathode 33 of the organic EL 3 is fixed at, for example, the ground potential.
　有機ＴＦＴ１および有機ＴＦＴ２は、基板１０上に形成され、所謂ボトムコンタクト構造を有している。基板１０は、例えばガラス基板や可撓性プラスチックフィルム等の光透過性材料が用いられる。有機ＴＦＴ１および有機ＴＦＴ２のゲート電極１１ａ、１１ｂは、例えばニッケルリン（Ｎｉ－Ｐ）からなり、基板１０上に設けられる。ゲート電極１１ａ、１１ｂの上には、これらを覆うように例えばＰＶＰ（Poly（4-vinylphenol））とメラミンとを混合したポリマー材料からなるゲート絶縁膜１２が設けられる。 The organic TFT 1 and the organic TFT 2 are formed on the substrate 10 and have a so-called bottom contact structure. For the substrate 10, for example, a light transmissive material such as a glass substrate or a flexible plastic film is used. The gate electrodes 11 a and 11 b of the organic TFT 1 and the organic TFT 2 are made of, for example, nickel phosphorus (Ni—P) and are provided on the substrate 10. On the gate electrodes 11a and 11b, a gate insulating film 12 made of a polymer material in which, for example, PVP (Poly (4-vinylphenol)) and melamine are mixed is provided so as to cover them.
　ソース電極１３、１５およびドレイン電極１４、１６は、それぞれゲート絶縁膜１２を介してゲート電極１１ａ又は１１ｂ上から基板１０上に延在している例えばニッケルリン（Ｎｉ－Ｐ）からなる第１の電極層１３ａ～１６ａと、第１の電極層１３ａ～１６ａ上の一部に無電解めっき法により形成された例えばＡｕからなる第２の電極層１３ｂ～１６ｂとによって構成される。ソース電極１３、１５とドレイン電極１４、１６は、それぞれゲート電極１１ａ、１１ｂの上部において互いに離間している。有機ＴＦＴ１のドレイン電極１４は、ゲート絶縁膜１２に設けられたコンタクトホールを経由して有機ＴＦＴ２のゲート電極１１ｂに接続される。有機ＥＬ３の形成領域には、ゲート絶縁膜１２上に例えばＩＺＯ（Indium Zinc Oxide）等の透明電極材料からなる有機ＥＬ３の陽極３１が設けられる。有機ＥＬ３の陽極３１は、有機ＴＦＴ２のドレイン電極１６に接続される。 The source electrodes 13 and 15 and the drain electrodes 14 and 16 are first electrodes made of, for example, nickel phosphorus (Ni—P) extending from the gate electrode 11a or 11b to the substrate 10 through the gate insulating film 12, respectively. The electrode layers 13a to 16a and second electrode layers 13b to 16b made of, for example, Au formed on a part of the first electrode layers 13a to 16a by an electroless plating method. The source electrodes 13 and 15 and the drain electrodes 14 and 16 are separated from each other in the upper part of the gate electrodes 11a and 11b, respectively. The drain electrode 14 of the organic TFT 1 is connected to the gate electrode 11 b of the organic TFT 2 via a contact hole provided in the gate insulating film 12. In the formation region of the organic EL 3, an anode 31 of the organic EL 3 made of a transparent electrode material such as IZO (Indium Zinc Oxide) is provided on the gate insulating film 12. The anode 31 of the organic EL 3 is connected to the drain electrode 16 of the organic TFT 2.
　有機半導体層１７ａおよび１７ｂは、例えばテトラベンゾポルフィリン等の有機半導体材料からなり、それぞれソース／ドレイン電極のゲート電極１１ａ、１１ｂ上の離間部において露出しているゲート絶縁膜１２と、ソース／ドレイン電極１３、１４又は１５、１６とに接するように設けられる。有機半導体層１７ａ、１７ｂ内のソース電極１３、１５とドレイン電極１４、１６との間に挟まれた領域がチャネル領域１８ａ、１８ｂとなる。 The organic semiconductor layers 17a and 17b are made of, for example, an organic semiconductor material such as tetrabenzoporphyrin, and the gate insulating film 12 exposed in the separated portions on the gate electrodes 11a and 11b of the source / drain electrodes, and the source / drain electrodes, respectively. 13, 14 or 15, 16 is provided. Regions sandwiched between the source electrodes 13 and 15 and the drain electrodes 14 and 16 in the organic semiconductor layers 17a and 17b become channel regions 18a and 18b.
　有機ＴＦＴ１と有機ＴＦＴ２との間および有機ＴＦＴ２と有機ＥＬ３との間には、これら各素子間を隔てる撥液性バンク（隔壁部）２０が設けられる。すなわち、撥液性バンク２０は、有機半導体層１７ａ、１７ｂを挟む位置に設けられる。撥液性バンク２０は、例えば感光性ポリイミド等の有機材料からなり、露光・現像プロセスによって有機ＴＦＴ１、有機ＴＦＴ２、および有機ＥＬ３の形成部に開口部が形成される。その後、ＣＦ4プラズマ等による表面処理を行うことにより撥液性バンク２０の表面に撥液性が付与される。撥液性バンク２０は、ソース／ドレイン電極の第１の電極層１３ａ～１６ａの上に形成され、その開口部において第１の電極層１３ａ～１６ａの一部と、ソース／ドレイン電極の離間部において露出しているゲート絶縁膜１２の一部が露出するように形成される。基板１０上に各素子間を隔てる撥液性バンク２０が設けられることにより、有機ＴＦＴ１および有機ＴＦＴ２をインクジェット法で形成する際、有機半導体材料の液滴が撥液性バンク２０の撥液性によって、撥液性バンク２０の開口部内に自己整合的に整列し、高精度でのパターニングが可能となる。更に、撥液性バンク２０は、第１の電極層１３ａ～１６ａ上に第２の電極層１３ｂ～１６ｂを形成する際のマスクとしての役割も果たす。すなわち、撥液性バンク２０の開口部において露出した第１の電極層１３ａ～１６ａ上の一部にのみ無電解めっき法により第２の電極層１３ｂ～１６ｂが形成される。第２の電極層１３ｂ～１６ｂは、ソース電極１３、１５およびドレイン電極１４、１６が有機半導体層１７ａ、１７ｂと接する部分にのみ形成される。 Between the organic TFT 1 and the organic TFT 2 and between the organic TFT 2 and the organic EL 3, a liquid repellent bank (partition wall) 20 is provided to separate these elements. That is, the liquid repellent bank 20 is provided at a position sandwiching the organic semiconductor layers 17a and 17b. The liquid repellent bank 20 is made of, for example, an organic material such as photosensitive polyimide, and an opening is formed in the formation portion of the organic TFT 1, the organic TFT 2, and the organic EL 3 by an exposure / development process. Thereafter, the surface of the liquid repellent bank 20 is given liquid repellency by performing a surface treatment with CF 4 plasma or the like. The liquid repellent bank 20 is formed on the first electrode layers 13a to 16a of the source / drain electrodes, and a part of the first electrode layers 13a to 16a and a separation portion of the source / drain electrodes in the opening thereof. A part of the gate insulating film 12 exposed in the step is exposed. By providing the liquid repellent bank 20 that separates the elements on the substrate 10, when the organic TFT 1 and the organic TFT 2 are formed by the ink jet method, the liquid droplets of the organic semiconductor material are caused by the liquid repellent property of the liquid repellent bank 20. Alignment in a self-aligned manner within the opening of the liquid repellent bank 20 enables patterning with high accuracy. Further, the liquid repellent bank 20 also serves as a mask when the second electrode layers 13b to 16b are formed on the first electrode layers 13a to 16a. That is, the second electrode layers 13b to 16b are formed only on a part of the first electrode layers 13a to 16a exposed in the openings of the liquid repellent bank 20 by the electroless plating method. The second electrode layers 13b to 16b are formed only at portions where the source electrodes 13 and 15 and the drain electrodes 14 and 16 are in contact with the organic semiconductor layers 17a and 17b.
　有機半導体１７ａ、１７ｂのイオン化ポテンシャルの値と近似した仕事関数を持つＡｕを第２の電極層１３ｂ～１６ｂの材料として使用することにより、有機半導体層１７ａ、１７ｂとソース電極１３、１５およびドレイン電極１４、１６との間でオーミック性接触を形成することが可能となり、良好な電気特性を得ることが可能となる。このように第２の電極層１３ｂ～１６ｂは、有機半導体１７ａ、１７ｂとソース／ドレイン電極との間の接触性をコントロールするために導入されるものであり、ソース電極１３、１５およびドレイン電極１４、１６が有機半導体層１７ａ、１７ｂと接する部分にのみ形成されていればその機能は十分に発揮される。そこで、本実施例に係る半導体装置においては、有機半導体層１７ａ、１７ｂと接する部分を含む第１の電極層１３ａ～１６ａ上の一部にのみ第２電極層１３ｂ～１６ｂを設けることにより、Ａｕの使用量を抑制することとした。 By using Au having a work function approximate to the value of the ionization potential of the organic semiconductors 17a and 17b as the material of the second electrode layers 13b to 16b, the organic semiconductor layers 17a and 17b, the source electrodes 13 and 15, and the drain electrode It is possible to form an ohmic contact with the electrodes 14 and 16, and to obtain good electrical characteristics. Thus, the second electrode layers 13b to 16b are introduced to control the contact between the organic semiconductors 17a and 17b and the source / drain electrodes, and the source electrodes 13 and 15 and the drain electrode 14 are introduced. , 16 are formed only in the portions in contact with the organic semiconductor layers 17a and 17b, the function is sufficiently exhibited. Therefore, in the semiconductor device according to the present embodiment, the second electrode layers 13b to 16b are provided only on a part of the first electrode layers 13a to 16a including the portions in contact with the organic semiconductor layers 17a and 17b, so that Au It was decided to suppress the amount of use.
　有機半導体層１７ａ、１７ｂ上には、撥液性バンク２０の開口部を充填するように層間絶縁膜１９が設けられる。有機ＥＬ３の発光部を形成する有機層３２が撥液性バンク２０、層間絶縁膜１９、陽極３１上に延在するように設けられる。有機層３２上には、これを覆うように例えばＡｌ等からなる陰極３３が設けられる。 On the organic semiconductor layers 17a and 17b, an interlayer insulating film 19 is provided so as to fill the opening of the liquid repellent bank 20. An organic layer 32 forming a light emitting portion of the organic EL 3 is provided so as to extend on the liquid repellent bank 20, the interlayer insulating film 19, and the anode 31. A cathode 33 made of, for example, Al is provided on the organic layer 32 so as to cover it.
　次に、上記した構造を有する有機ＥＬ駆動回路１００の製造方法について図面を参照しつつ説明する。図３（ａ）～（ｅ）、図４（ｆ）～（ｉ）は、本発明の実施例である有機ＥＬ駆動回路１００の製造工程を示す各プロセスステップ毎の断面図である。 Next, a method for manufacturing the organic EL drive circuit 100 having the above-described structure will be described with reference to the drawings. 3 (a) to 3 (e) and FIGS. 4 (f) to (i) are cross-sectional views for each process step showing a manufacturing process of the organic EL driving circuit 100 according to the embodiment of the present invention.
　はじめに、ガラス基板や可撓性プラスチックフィルム等からなる基板１０を用意する。基板１０上に各素子を形成する前に純水や界面活性剤等を含む洗浄液で洗浄し、基板１０の表面に付着した油脂等を除去することとしてもよい。 First, a substrate 10 made of a glass substrate or a flexible plastic film is prepared. Before forming each element on the substrate 10, it may be cleaned with a cleaning liquid containing pure water, a surfactant or the like to remove oils and fats attached to the surface of the substrate 10.
　次に、アンカー効果によって、基板１０とゲート電極１１との密着性を向上させるため、基板１０表面の粗面化処理を行う。具体的には基板１０をクロム酸／硫酸混合液等のエッチング液を用いてエッチングすることにより、基板１０の表面に微細な凹凸を形成する。その後、基板１０の表面に残ったクロム化合物を塩酸等を用いて除去する。次に、ゲート電極１１を形成するための無電解めっきの核となる触媒を基板１０上に吸着させる。触媒としては、例えばＰｄ－Ｓｎ錯体を用いることができる。次に、基板１０を酸溶液に浸漬し、スズ塩を溶解させ、酸化還元反応により基板１０上に金属パラジウムを生成する。次に、基板１０を硫酸ニッケルおよび次亜リン酸ナトリウムを含むめっき浴に浸漬し、基板１０表面にニッケルリン（Ｎｉ－Ｐ）からなるめっき膜を形成する。次に、基板１０上に形成されためっき膜に公知のフォトリソ技術を用いてパターニングを行って、ゲート電極１１ａ、１１ｂを形成する（図３（ａ））。 Next, the surface of the substrate 10 is roughened to improve the adhesion between the substrate 10 and the gate electrode 11 by the anchor effect. Specifically, fine irregularities are formed on the surface of the substrate 10 by etching the substrate 10 using an etching solution such as a chromic acid / sulfuric acid mixed solution. Thereafter, the chromium compound remaining on the surface of the substrate 10 is removed using hydrochloric acid or the like. Next, a catalyst serving as a nucleus of electroless plating for forming the gate electrode 11 is adsorbed on the substrate 10. As the catalyst, for example, a Pd—Sn complex can be used. Next, the board | substrate 10 is immersed in an acid solution, a tin salt is dissolved, and metal palladium is produced | generated on the board | substrate 10 by oxidation-reduction reaction. Next, the substrate 10 is immersed in a plating bath containing nickel sulfate and sodium hypophosphite to form a plating film made of nickel phosphorus (Ni—P) on the surface of the substrate 10. Next, the plating film formed on the substrate 10 is patterned using a known photolithography technique to form gate electrodes 11a and 11b (FIG. 3A).
　尚、ゲート電極１１のパターニングを行う方法としては、上記した方法以外に、例えば、ゲート電極１１ａ、１１ｂのパターンに対応したマスクを用いて基板１０の粗面化処理を行って、粗面化処理が行われた部分にのみ触媒を吸着させ、この部分に選択的にめっき膜を形成することによりゲート電極１１ａ、１１ｂのパターニングを行うこととしてもよい。また、基板１０の粗面化処理を実施した後、ゲート電極１１ａ、１１ｂのパターンに対応したマスクを介して基板１０の表面にプラズマ照射を行うことにより、触媒に対する吸着力を低下させるような表面改質処理を行って、プラズマが照射されない部分にのみ触媒を吸着させ、この部分に選択的にめっき膜を形成することによりゲート電極１１ａ、１１ｂのパターニングを行うこととしてもよい。また、触媒機能を持つシランカップリング剤をインクジェット法により描画し、シランカップリング剤が存在する部分にのみ選択的にめっき膜を形成することによりゲート電極１１ａ、１１ｂのパターニングを行うこととしてもよい。 As a method for patterning the gate electrode 11, in addition to the above-described method, for example, a surface roughening process is performed on the substrate 10 using a mask corresponding to the pattern of the gate electrodes 11 a and 11 b. The gate electrodes 11a and 11b may be patterned by allowing the catalyst to be adsorbed only in the portions where the etching is performed and selectively forming a plating film on the portions. Further, after the surface roughening treatment of the substrate 10 is performed, the surface of the substrate 10 is irradiated with plasma through a mask corresponding to the pattern of the gate electrodes 11a and 11b, thereby reducing the adsorption power to the catalyst. Patterning of the gate electrodes 11a and 11b may be performed by performing a reforming process so that the catalyst is adsorbed only in a portion not irradiated with plasma and a plating film is selectively formed in this portion. Alternatively, the gate electrodes 11a and 11b may be patterned by drawing a silane coupling agent having a catalytic function by an ink-jet method and selectively forming a plating film only on a portion where the silane coupling agent is present. .
　次に、ゲート電極１１ａ、１１ｂを覆うようにゲート絶縁膜１２を形成する。例えば、ＰＶＰ（Poly（4-vinylphenol））にメラミンを混合したポリマー材料をゲート電極上に適量滴下してスピンコート法により成膜し、これに熱処理を施して硬化させることによりゲート絶縁膜１２を形成する（図３（ｂ））。その後、有機ＴＦＴ１のドレイン電極１４と有機ＴＦＴ２のゲート電極１１ｂとを接続するためのコンタクトホール（図示せず）をゲート絶縁膜１２に設ける。 Next, the gate insulating film 12 is formed so as to cover the gate electrodes 11a and 11b. For example, an appropriate amount of a polymer material in which melamine is mixed with PVP (Poly (4-vinylphenol)) is dropped onto the gate electrode, a film is formed by a spin coating method, and the gate insulating film 12 is formed by subjecting it to heat treatment and curing. It forms (FIG.3 (b)). Thereafter, a contact hole (not shown) for connecting the drain electrode 14 of the organic TFT 1 and the gate electrode 11 b of the organic TFT 2 is provided in the gate insulating film 12.
　次に、ゲート絶縁膜１２上にソース電極１３、１５およびドレイン電極１４、１６を構成するニッケルリン（Ｎｉ－Ｐ）からなる第１の電極層１３ａ～１６ａを無電解めっき法により形成する。無電解めっき法によりニッケルリン（Ｎｉ－Ｐ）めっき膜を形成するプロセスは、上記したゲート電極１１ａ、１１ｂを形成するプロセスと同様である。すなわち、必要に応じてゲート絶縁膜１２の粗面化処理を行い、Ｐｄ－Ｓｎ錯体からなる触媒をゲート絶縁膜１２上に吸着させ、酸溶液によるアクセレータ処理を行った後、基板１０を硫酸ニッケルおよび次亜リン酸ナトリウムを含むめっき浴に浸漬する。これにより、基板１０およびゲート電極１１上にゲート絶縁膜１２を介してニッケルリン（Ｎｉ－Ｐ）からなるめっき膜が形成される。その後、公知のフォトリソ技術によって第１の電極層１３ａ～１６ｂのパターニングを行う。かかるパターニング工程において、ゲート電極１１ａ、１１ｂ上に形成されたニッケルリン（Ｎｉ－Ｐ）めっき膜に有機ＴＦＴのチャネル領域１８ａ、１８ｂを形成するための開口部（離間部）３０等が設けられ、ソース／ドレイン電極の配線パターンが形成される。かかる開口部（離間部）３０においてゲート電極１１ａ、１１ｂ上に位置するゲート絶縁膜１２が露出する。また、有機ＴＦＴ１の第１の電極層１４ａは、ゲート絶縁膜１２に形成されたコンタクトホール（図示せず）を経由して、有機ＴＦＴ２のゲート電極１１ｂに接続される。 Next, first electrode layers 13a to 16a made of nickel phosphorus (Ni—P) constituting the source electrodes 13 and 15 and the drain electrodes 14 and 16 are formed on the gate insulating film 12 by an electroless plating method. The process of forming the nickel phosphorus (Ni—P) plating film by the electroless plating method is the same as the process of forming the gate electrodes 11a and 11b. That is, the gate insulating film 12 is roughened as necessary, a catalyst made of a Pd—Sn complex is adsorbed on the gate insulating film 12, an accelerator treatment with an acid solution is performed, and then the substrate 10 is nickel sulfate. And soak in a plating bath containing sodium hypophosphite. As a result, a plating film made of nickel phosphorus (Ni—P) is formed on the substrate 10 and the gate electrode 11 via the gate insulating film 12. Thereafter, the first electrode layers 13a to 16b are patterned by a known photolithography technique. In this patterning step, openings (separation portions) 30 for forming the channel regions 18a and 18b of the organic TFT are provided in the nickel phosphorus (Ni—P) plating film formed on the gate electrodes 11a and 11b, and the like. A wiring pattern of the source / drain electrodes is formed. The gate insulating film 12 located on the gate electrodes 11a and 11b is exposed in the opening (separation part) 30. The first electrode layer 14 a of the organic TFT 1 is connected to the gate electrode 11 b of the organic TFT 2 via a contact hole (not shown) formed in the gate insulating film 12.
　尚、第１の電極層１３ａ～１６ａのパターニングを行う方法としては、上記した方法以外に、例えば、ソース／ドレイン電極のパターンに対応したマスクを用いてゲート絶縁膜１２の粗面化処理を行って、粗面化処理が行われた部分にのみ触媒を吸着させ、この部分に選択的にめっき膜を形成することにより第１の電極層１３ａ～１６ａのパターニングを行うこととしてもよい。また、ゲート絶縁膜１２の粗面化処理を実施した後、ソース／ドレイン電極のパターンに対応したマスクを介してゲート絶縁膜１２の表面にプラズマ照射を行うことにより、触媒に対する吸着力を低下させるような表面改質処理を行って、プラズマが照射されない部分にのみ触媒を吸着させ、この部分に選択的にめっき膜を形成することにより第１の電極層１３ａ～１６ａのパターニングを行うこととしてもよい。また、触媒機能を持つシランカップリング剤をインクジェット法により描画し、シランカップリング剤が存在する部分にのみ選択的にめっき膜を形成することにより第１の電極層１３ａ～１６ａのパターニングを行うこととしてもよい。 As a method of patterning the first electrode layers 13a to 16a, in addition to the above-described method, for example, a roughening process of the gate insulating film 12 is performed using a mask corresponding to the pattern of the source / drain electrodes. Thus, the first electrode layers 13a to 16a may be patterned by adsorbing the catalyst only on the roughened portion and selectively forming a plating film on this portion. Further, after performing the roughening treatment of the gate insulating film 12, the surface of the gate insulating film 12 is irradiated with plasma through a mask corresponding to the pattern of the source / drain electrodes, thereby reducing the adsorption power to the catalyst. By performing such surface modification treatment, the first electrode layers 13a to 16a may be patterned by causing the catalyst to be adsorbed only on a portion not irradiated with plasma and selectively forming a plating film on this portion. Good. In addition, the first electrode layers 13a to 16a are patterned by drawing a silane coupling agent having a catalytic function by an ink-jet method and selectively forming a plating film only on a portion where the silane coupling agent exists. It is good.
　次に、例えばスパッタ法によりゲート絶縁膜１２上に透明電極材料であるＩＺＯ膜を形成し、公知のフォトリソ技術によってパターニングを行って有機ＥＬ２の陽極３１を形成する。陽極３１は、有機ＴＦＴ２の第１の電極層１６ａに接続される（図３（ｃ））。尚、陽極３１の材料としては、ＩＺＯ膜以外にＩＴＯ（Indium Tin Oxide）膜等を用いることとしてもよい。 Next, an IZO film, which is a transparent electrode material, is formed on the gate insulating film 12 by, for example, a sputtering method, and patterned by a known photolithography technique to form the anode 31 of the organic EL 2. The anode 31 is connected to the first electrode layer 16a of the organic TFT 2 (FIG. 3C). As a material of the anode 31, an ITO (Indium Tin Oxide) film or the like may be used in addition to the IZO film.
　次に、有機ＴＦＴ１、有機ＴＦＴ２および有機ＥＬ３の各素子間を隔てる撥液性バンク（隔壁部）２０を形成する。具体的には、第１の電極層１３ａ～１６ａの形成まで完了した基板上に、例えば感光性ポリイミド膜をスピンコート法により成膜し、感光性ポリイミド膜に撥液性バンク２０のパターンに対応したマスクを介して露光、現像することにより、ゲート電極１１ａ、１１ｂの形成部および陽極３１の形成部に対応する部分に開口部２１を形成する。すなわち、開口部２１において、第１の電極層の離間部３０において露出しているゲート絶縁膜１２、第１の電極層１３ａ～１６ａの先端部、および有機ＥＬ３の陽極３１が露出している。次に、パターニングされた感光性ポリイミド膜に撥液性を付与するために、感光性ポリイミド膜に例えばＣＦ4プラズマによる表面処理を行う（図３（ｄ））。尚、撥液性バンク２０の開口部２１内部には親水性を持たせるため、開口部２１の内壁面に対して酸素プラズマ処理を施すこととしてもよい。 Next, a liquid repellent bank (partition wall) 20 is formed to separate the organic TFT 1, the organic TFT 2, and the organic EL 3. Specifically, for example, a photosensitive polyimide film is formed by spin coating on the substrate on which the formation of the first electrode layers 13a to 16a has been completed, and the pattern of the liquid repellent bank 20 is applied to the photosensitive polyimide film. By exposing and developing through the mask, the opening 21 is formed in a portion corresponding to the formation portion of the gate electrodes 11a and 11b and the formation portion of the anode 31. That is, in the opening 21, the gate insulating film 12 exposed at the separation portion 30 of the first electrode layer, the tip portions of the first electrode layers 13a to 16a, and the anode 31 of the organic EL 3 are exposed. Next, in order to impart liquid repellency to the patterned photosensitive polyimide film, the photosensitive polyimide film is subjected to a surface treatment using, for example, CF 4 plasma (FIG. 3D). In order to give hydrophilicity to the inside of the opening 21 of the liquid repellent bank 20, oxygen plasma treatment may be performed on the inner wall surface of the opening 21.
　次に、無電解めっき法により、撥液性バンク２０の開口部２１において露出している第１の電極層１３ａ～１６ａの先端部にのみ選択的にＡｕからなる第２の電極層１３ｂ～１６ｂを形成する。第２の電極層１３ｂ～１６ｂは、例えば、置換Ａｕめっき法および還元Ａｕめっき法を併用して形成される。 Next, the second electrode layers 13b to 16b made of Au are selectively formed only at the tips of the first electrode layers 13a to 16a exposed at the openings 21 of the liquid repellent bank 20 by electroless plating. Form. The second electrode layers 13b to 16b are formed by using, for example, a substitution Au plating method and a reduction Au plating method in combination.
　置換Ａｕめっき法は、めっき処理される下地金属のイオン化傾向とめっき材料であるＡｕのイオン化傾向の差を利用するものであり、ニッケルリン（Ｎｉ－Ｐ）からなる第１の電極層１３ａ～１６ａが形成された基板１０をシアン系又は非シアン系の置換金めっき浴に浸漬することにより、第１の電極層１３ａ～１６ａ上にＡｕめっき膜を形成する。めっき浴中では、比較的イオン化傾向の大きい下地のニッケルリン（Ｎｉ－Ｐ）が溶解し、ニッケルリン（Ｎｉ－Ｐ）上にＡｕが析出する反応が起る。置換Ａｕめっき法においては、下地のニッケルリン（Ｎｉ－Ｐ）がＡｕで被覆された時点で反応が停止するため、析出するＡｕの膜厚は薄くなってしまう。そこで、本実施例においては、置換Ａｕめっき処理に引き続き還元Ａｕめっき処理を行い、Ａｕめっき膜の膜厚を確保することとした。 The substitution Au plating method uses the difference between the ionization tendency of the base metal to be plated and the ionization tendency of Au as the plating material, and the first electrode layers 13a to 16a made of nickel phosphorus (Ni-P). An Au plating film is formed on the first electrode layers 13a to 16a by immersing the substrate 10 on which is formed in a cyan or non-cyan substitution gold plating bath. In the plating bath, the underlying nickel phosphorus (Ni—P), which has a relatively high ionization tendency, dissolves, and a reaction occurs in which Au precipitates on the nickel phosphorus (Ni—P). In the substitutional Au plating method, the reaction stops when the underlying nickel phosphorus (Ni—P) is coated with Au, so that the deposited Au film becomes thin. Therefore, in this embodiment, the reduced Au plating process is performed subsequent to the replacement Au plating process to secure the film thickness of the Au plating film.
　還元Ａｕめっき法は、めっき浴中に含まれる還元剤の酸化によって放出される電子がＡｕイオンに転位して被めっき材にＡｕ皮膜を形成するめっき法である。例えばテトラヒドロほう酸カリウム（ＫＢＨ4）等を還元剤とし、ＫＡｕ（ＣＮ）2を金塩として用いためっき浴中に基板１０を浸漬することにより、置換Ａｕめっき膜が形成された第１の電極層１３ａ～１６ａ上に更に還元Ａｕめっき膜が形成される。 The reduced Au plating method is a plating method in which electrons released by oxidation of a reducing agent contained in a plating bath are transferred to Au ions to form an Au film on a material to be plated. For example, the first electrode layer in which the substituted Au plating film is formed by immersing the substrate 10 in a plating bath using potassium tetrahydroborate (KBH 4 ) or the like as a reducing agent and KAu (CN) 2 as a gold salt. A reduced Au plating film is further formed on 13a to 16a.
　第１の電極層１３ａ～１６ａは、先の工程で形成した撥液性バンク２０の開口部２１においてのみ露出している。このため、第１の電極層１３ａ～１６ａは、置換Ａｕめっき工程および還元Ａｕめっき工程において、この露出部分にのみがめっき液に曝されて、この露出部分にのみ第２の電極層１３ｂ～１６ｂが形成される。このようにして第１の電極層１３ａ～１６ａ上に第２の電極層が形成され、ソース電極１３、１５およびドレイン電極１４、１６が完成する（図３（ｅ））。 The first electrode layers 13a to 16a are exposed only at the opening 21 of the liquid repellent bank 20 formed in the previous step. Therefore, the first electrode layers 13a to 16a are exposed to the plating solution only in the exposed portion in the replacement Au plating step and the reduced Au plating step, and the second electrode layers 13b to 16b are exposed only to the exposed portion. Is formed. In this way, the second electrode layer is formed on the first electrode layers 13a to 16a, and the source electrodes 13 and 15 and the drain electrodes 14 and 16 are completed (FIG. 3E).
　次に、インクジェット法により撥液性バンク２０の開口部２１内に有機半導体層１７ａ、１７ｂを形成する。インクジェット法は、有機半導体材料含む溶液をノズルより吐出してパターンを形成する印刷法であり、基板１０に対して非接触で成膜することができる、広面積に印刷することができる、使用する材料の量を最小限に抑えることできる、高い吐出位置精度を確保することができるといった利点を有することから、有機ＴＦＴの成膜に好適な手法である。更に、各素子間を隔てる撥液性バンク２０が設けられているため、ヘッド固有のばらつき或いは有機半導体材料の特性等により、ノズルより吐出された有機半導体材料に飛行曲がりが生じた場合であっても、液滴の自己パターニング現象により、全ての液滴は表面エネルギーの力で着弾誤差が補正され、撥液性バンク２０の開口部２１内に収まるようになる。その後、有機半導体材料の塗膜に対し、必要に応じて加熱処理等の後処理を行う。有機半導体層１７ａ、１７ｂは、撥液性バンク２０の開口部２１の底部において、ソース電極１３、１５、ドレイン電極１４、１６およびゲート絶縁膜１２と接するように設けられる（図４（ｆ））。 Next, organic semiconductor layers 17a and 17b are formed in the opening 21 of the liquid repellent bank 20 by an ink jet method. The ink jet method is a printing method in which a solution containing an organic semiconductor material is discharged from a nozzle to form a pattern, and can be formed in a non-contact manner with respect to the substrate 10 and can be printed over a wide area. Since it has an advantage that the amount of material can be minimized and high discharge position accuracy can be secured, it is a method suitable for film formation of an organic TFT. Furthermore, since the liquid repellent bank 20 is provided to separate the elements, the flight of the organic semiconductor material discharged from the nozzle is caused by the variation inherent in the head or the characteristics of the organic semiconductor material. However, due to the self-patterning phenomenon of the droplets, the landing error of all the droplets is corrected by the force of the surface energy, and the droplets are accommodated in the openings 21 of the liquid repellent bank 20. Thereafter, post-treatment such as heat treatment is performed on the coating film of the organic semiconductor material as necessary. The organic semiconductor layers 17a and 17b are provided at the bottom of the opening 21 of the liquid repellent bank 20 so as to be in contact with the source electrodes 13 and 15, the drain electrodes 14 and 16 and the gate insulating film 12 (FIG. 4F). .
　次に、撥液性バンク２０の開口部２１内に形成された有機半導体層１７ａ、１７ｂを覆うように、撥液性バンク２０の開口部２１内に層間絶縁１９を充填する。層間絶縁膜１９は、例えばゲート絶縁膜１２と同じＰＶＰとメラミンとを混合したポリマー材料をインクジェット法を用いて形成することが可能である（図４（ｇ））。 Next, the interlayer insulation 19 is filled in the opening 21 of the liquid repellent bank 20 so as to cover the organic semiconductor layers 17a and 17b formed in the opening 21 of the liquid repellent bank 20. The interlayer insulating film 19 can be formed using, for example, a polymer material in which the same PVP and melamine as the gate insulating film 12 are mixed using an ink jet method (FIG. 4G).
　次に、有機ＥＬ３を構成する有機層３２を基板上に形成する。具体的には、導電性ポリマーであるＰＥＤＯＴをスピンコート法により成膜し、乾燥させて陽極バッファ層を形成した後、陽極バッファ層の上にＰＰＶ（ポリパラフェニレンビニレン）等をスピンコート法により成膜し、乾燥させて発光層を形成する（図４（ｈ））。 Next, the organic layer 32 constituting the organic EL 3 is formed on the substrate. Specifically, PEDOT, which is a conductive polymer, is formed by spin coating and dried to form an anode buffer layer, and then PPV (polyparaphenylene vinylene) or the like is formed on the anode buffer layer by spin coating. A film is formed and dried to form a light emitting layer (FIG. 4H).
　次に、例えば真空蒸着法等により有機層３２上にＡｌを堆積させ、有機ＥＬ３の陰極３３を形成する（図４（ｉ））。その後、必要に応じて基板上に形成された各素子を封止して有機ＥＬ駆動回路１００が完成する。 Next, Al is deposited on the organic layer 32 by, for example, a vacuum evaporation method or the like to form the cathode 33 of the organic EL 3 (FIG. 4 (i)). Thereafter, the elements formed on the substrate are sealed as necessary to complete the organic EL drive circuit 100.
　このように、本発明の半導体装置の製造方法によれば、有機半導体層１７ａ、１７ｂの形成位置の精度を確保するために設けられる撥液性バンク２０を、第２の電極層１３ｂ～１６ｂを無電解めっき法を用いて形成する際のマスクとしても使用し、ソース電極１３、１５およびドレイン電極１４、１６が有機半導体層１７ａ、１７ｂと接触する部分においてのみ第２の電極層１３ｂ～１６ｂを形成することとしたので、第１の電極層１３ａ～１６ｂの全面にめっき処理を施す場合と比較して、第２の電極層１３ｂ～１６ｂを構成する金属（主に貴金属）の使用量を抑制することができ製造コストを抑えることが可能となる。特に、本実施例の如く、有機ＴＦＴをアレイ状に形成して、表示パネルの画素を構成する有機ＥＬの駆動回路を形成する場合には、Ａｕの使用量を従来の数％程度にまで抑えることが可能となり、大幅なコスト削減効果をもたらすことが可能となる。また、これにより、めっき浴の交換サイクルを長くすることができるので、ランニングコストも抑えることが可能となる。また、撥液性バンク２０をマスクとして利用するので、第２の電極層１３ｂ～１６ｂのパターニングを行うための工程は不要である。 As described above, according to the method for manufacturing a semiconductor device of the present invention, the liquid repellent bank 20 provided to ensure the accuracy of the formation position of the organic semiconductor layers 17a and 17b is replaced with the second electrode layers 13b to 16b. The second electrode layers 13b to 16b are also used as masks when forming using the electroless plating method, and the second electrode layers 13b to 16b are formed only in the portions where the source electrodes 13 and 15 and the drain electrodes 14 and 16 are in contact with the organic semiconductor layers 17a and 17b. Since it is formed, the amount of metal (mainly noble metal) constituting the second electrode layers 13b to 16b is suppressed as compared with the case where the entire surface of the first electrode layers 13a to 16b is plated. The manufacturing cost can be reduced. In particular, as in this embodiment, when the organic TFTs are formed in an array to form a drive circuit for an organic EL that constitutes the pixels of the display panel, the amount of Au used is suppressed to about several percent of the conventional one. And a significant cost reduction effect can be achieved. Moreover, since the exchange cycle of a plating bath can be lengthened by this, a running cost can also be suppressed. In addition, since the liquid repellent bank 20 is used as a mask, a process for patterning the second electrode layers 13b to 16b is unnecessary.
　ここで、第２の電極層１３ｂ～１６ｂは、ソース／ドレイン電極と有機半導体層との電気的接触性をコントロールすることを目的としてに導入されるところ、少なくとも有機半導体層のチャネル領域と接する部分に形成されていればその機能は発揮されるので、第２の電極層１４の形成領域を制限したことによる電気的特性への悪影響はない。 Here, the second electrode layers 13b to 16b are introduced for the purpose of controlling electrical contact between the source / drain electrodes and the organic semiconductor layer, and at least a portion in contact with the channel region of the organic semiconductor layer. If it is formed, the function is exhibited. Therefore, there is no adverse effect on the electrical characteristics due to the restriction of the formation region of the second electrode layer 14.
　上記した本発明に係る有機ＴＦＴの構造および製法は例示にすぎず、種々の改変を行うことが可能である。上記の実施例では、第２の電極層１３ｂ～１６ｂとしてＡｕを使用することとしたが、これに限定されず、例えばパラジウム（Ｐｄ）、ロジウム（Ｒｈ）、イリジウム（Ｉｒ）、銀（Ａｇ）、銅（Ｃｕ）等の貴金属、若しくはこれらの合金を用いることが可能である。この場合、有機半導体層１７ａ、１７ｂのイオン化ポテンシャルに近似した仕事関数を持つ材料を選定することが好ましい。 The structure and manufacturing method of the organic TFT according to the present invention described above are merely examples, and various modifications can be made. In the above embodiment, Au is used for the second electrode layers 13b to 16b. However, the present invention is not limited to this. For example, palladium (Pd), rhodium (Rh), iridium (Ir), silver (Ag) It is possible to use noble metals such as copper (Cu) or alloys thereof. In this case, it is preferable to select a material having a work function approximate to the ionization potential of the organic semiconductor layers 17a and 17b.
　また、上記の実施例では、置換めっきおよび還元めっきを併用して第２の電極層１３ｂ～１６ｂを形成することとしたが、第２の電極層１３ｂ～１６ｂの膜厚を薄くできる場合等においては、置換めっきのみで第２の電極層１３ｂ～１６ｂを形成することとしてもよい。また、上記の実施例では、置換めっきおよび還元めっきをそれぞれ１回ずつ行うこととしたが、置換めっきおよび還元めっきを繰り返して複数の層を形成するようにしてもよい。 In the above embodiment, the second electrode layers 13b to 16b are formed by using both displacement plating and reduction plating. However, in the case where the film thickness of the second electrode layers 13b to 16b can be reduced. Alternatively, the second electrode layers 13b to 16b may be formed only by displacement plating. In the above embodiment, the displacement plating and the reduction plating are each performed once. However, the plurality of layers may be formed by repeating the displacement plating and the reduction plating.
　また、上記の実施例では、第１の電極層１３ａ～１６ａとしてニッケルリン（Ｎｉ－Ｐ）を用いることとしたが、これに限定されず、第２電極層１３ｂ～１６ｂよりもイオン化傾向が大きいめっき材料であれば、単体、合金いずれの材料も用いることが可能である。また、第１の電極層１３ａ～１６ａは、無電解めっき法に限らず、スパッタ法、ＣＶＤ法、真空蒸着法等により電極材料を成膜した後、フォトリソ技術等によって所望のパターニングを行うことにより形成してもよい。また、インクジェット法により金属のナノインクをライン状に吐出することにより第１電極層１３ａ～１６ａを形成することとしてもよい。また、ゲート電極１１ａ、１１ｂの材料および形成方法についてもこれと同様の改変を行うことが可能である。 In the above embodiment, nickel phosphorus (Ni—P) is used as the first electrode layers 13a to 16a. However, the present invention is not limited to this, and the ionization tendency is larger than that of the second electrode layers 13b to 16b. As long as it is a plating material, either a simple substance or an alloy can be used. The first electrode layers 13a to 16a are not limited to the electroless plating method, and after the electrode material is formed by a sputtering method, a CVD method, a vacuum evaporation method, or the like, a desired patterning is performed by a photolithography technique or the like. It may be formed. Alternatively, the first electrode layers 13a to 16a may be formed by ejecting metal nano-ink in a line shape by an inkjet method. Further, the same modification can be made for the material and forming method of the gate electrodes 11a and 11b.
　また、上記の実施例では、有機半導体層１７ａ、１７ｂの材料としてテトラベンゾポルフィリンを用いることとしたが、これに限定されず、他の有機半導体材料を使用することも可能である。例えば、低分子系材料ではフタロシアニン系誘導体、ナフタロシアニン系誘導体、アゾ化合物系誘導体、ペリレン系誘導体、インジゴ系誘導体、キナクリドン系誘導体、アントラキノン類などの多環キノン系誘導体、シアニン系誘導体、フラーレン類誘導体、あるいはインドール、カルバゾール、オキサゾール、インオキサゾール、チアゾール、イミダゾール、ピラゾール、オキサアジアゾール、ピラゾリン、チアチアゾール、トリアゾールなどの含窒素環式化合物誘導体、ヒドラジン誘導体、トリフェニルアミン誘導体、トリフェニルメタン誘導体、スチルベン類、アントラキノンジフェノキノン等のキノン化合物誘導体、ペンタセン、アントラセン、ビレン、フェナントレン、コロネンなどの多環芳香族化合物誘導体などである。高分子材料では、上述した低分子化合物の構造がポリエチレン鎖、ポリシロキサン鎖、ポリエーテル鎖、ポリエステル鎖、ポリアミド鎖、ポリイミド鎖等の高分子の主鎖中に用いられた物あるいは側鎖としてペンダント状に結合したもの、もしくはポリパラフェニレン等の芳香族系共役性高分子、ポリアセチレン等の脂肪族系共役性高分子、ポリピノールやポリチオフェン率の複素環式共役性高分子、ポリアニリン類やポリフェニレンサルファイド等の含ヘテロ原子共役性高分子、ポリ（フェニレンビニレン）やポリ（アニーレンビニレン）やポリ（チェニレンビニレン）等の共役性高分子の構成単位が交互に結合した構造を有する複合型共役系高分子等の炭素系共役高分子を用いることができる。また、ポリシラン類やジシラニレンアリレンポリマー類、（ジシラニレン）エチニレンポリマー類のようなジシラニレン炭素系共役性ポリマー構造などのオリゴシラン類と炭素系共役性構造が交互に連鎖した高分子類などを用いることができる。他にもリン系、窒素系等の無機元素からなる高分子鎖でも良く、さらにフタロシアナートポリシロキサンのような高分子鎖の芳香族系配位子が配位した高分子類、ペリレンテトラカルボン酸のようなペリレン類を熱処理して縮環させた高分子類、ポリアクリロニトリルなどのシアノ基を有するポリエチレン誘導体を熱処理して得られるラダー型高分子類、さらにペロブスカイト類に有機化合物がインターカレートした複合材料を用いてもよい。 In the above embodiment, tetrabenzoporphyrin is used as the material of the organic semiconductor layers 17a and 17b. However, the present invention is not limited to this, and other organic semiconductor materials can also be used. For example, for low molecular weight materials, phthalocyanine derivatives, naphthalocyanine derivatives, azo compound derivatives, perylene derivatives, indigo derivatives, quinacridone derivatives, polycyclic quinone derivatives such as anthraquinones, cyanine derivatives, fullerene derivatives Or nitrogen-containing cyclic compound derivatives such as indole, carbazole, oxazole, inoxazole, thiazole, imidazole, pyrazole, oxadiazole, pyrazoline, thiathiazole, triazole, hydrazine derivative, triphenylamine derivative, triphenylmethane derivative, stilbene Quinone compound derivatives such as anthraquinone diphenoquinone, and polycyclic aromatic compound derivatives such as pentacene, anthracene, bilene, phenanthrene, and coronene. In the polymer material, the structure of the low molecular compound mentioned above is pendant as an object or side chain used in the polymer main chain such as polyethylene chain, polysiloxane chain, polyether chain, polyester chain, polyamide chain, polyimide chain, etc. Aromatic conjugated polymers such as polyparaphenylene, aliphatic conjugated polymers such as polyacetylene, heterocyclic conjugated polymers with polypinol and polythiophene ratios, polyanilines and polyphenylene sulfide, etc. Hetero-atom conjugated polymers of this type, complex type conjugated systems having a structure in which structural units of conjugated polymers such as poly (phenylene vinylene), poly (annelen vinylene) and poly (chenylene vinylene) are alternately bonded Carbon-based conjugated polymers such as molecules can be used. In addition, polymers containing oligosilanes and carbon-based conjugated structures such as polysilanes, disilanylene-arylene polymers, and disilanylene carbon-based conjugated polymer structures such as (disilanylene) ethynylene polymers Can be used. In addition, polymer chains made of inorganic elements such as phosphorus and nitrogen may be used, and polymers having aromatic chain ligands such as phthalocyanate polysiloxane coordinated, perylenetetracarboxylic Polymers in which perylenes such as acids are heat-treated and condensed, ladder-type polymers obtained by heat-treating polyethylene derivatives having a cyano group such as polyacrylonitrile, and organic compounds intercalated in perovskites The composite material may be used.
　また、上記の実施例ではゲート絶縁膜１２および層間絶縁膜１９の材料としてＰＶＰとメラミンとを混合したポリマー材料を用いることとしたが、これに限定されず、無機材料、有機材料のいずれの絶縁膜も使用することができる。例えば、LiOx、LiNx、NaOx、KOx、RbOx、CsOx、BeOx、MgOx、MgNx、CaOx、CaNx、SrOx、BaOx、ScOx、YOx、YNx、LaOx、LaNx、CeOx、PrOx、NdOx、SmOx、EuOx、GdOx、TbOx、DyOx、HoOx、ErOx、TmOx、YbOx、LuOx、TiOx、TiNx、ZrOx、ZrNx、HfOx、HfNx、ThOx、VOx、VNx、NbOx、TaOx、TaNx、CrOx、CrNx、MoOx、MoNx、WOx、WNx、MnOx、ReOx、FeOx、FeNx、RuOx、OsOx、CoOx、RhOx、IrOx、NiOx、PdOx、PtOx、CuOx、CuNx、AgOx、AuOx、ZnOx、CdOx、HgOx、BOx、BNx、AlOx、AlNx、GaOx、GaNx、InOx、TiOx、TiNx、SiOx、SiNx、GeOx、SnOx、PbOx、POx、PNx、AsOx、SbOx、SeOx、TeOxなどの金属酸化物、LiAlO2、Li2SiO3、Li2TiO3、Na2Al22O34、NaFeO2、Na4SiO4、K2SiO3、K2TiO3、K2WO4、Rb2CrO4、Cs2CrO4、MgAl2O4、MgFe2O4、MgTiO3、CaTiO3、CaWO4、CaZrO3、SrFe12O19、SrTiO3、SrZrO3、BaAl2O4、BaFe12O19、BaTiO3、Y3Al5O12、Y3Fe5O12、LaFeO3、La3Fe5O12、La2Ti2O7、CeSnO4、CeTiO4、Sm3Fe5O12、EuFeO3、Eu3Fe5O12、GdFeO3、Gd3Fe5O12、DyFeO3、Dy3Fe5O12、HoFeO3、Ho3Fe5O12、ErFeO3、Er3Fe5O12、Tm3Fe5O12、LuFeO3、Lu3Fe5O12、NiTiO3、Al2TiO3、FeTiO3、BaZrO3、LiZrO3、MgZrO3、HfTiO4、NH4VO3、AgVO3、LiVO3、BaNb2O6、NaNbO3、SrNb2O6、KTaO3、NaTaO3、SrTa2O6、CuCr2O4、Ag2CrO4、BaCrO4、K2MoO4、Na2MoO4、NiMoO4、BaWO4、Na2WO4、SrWO4、MnCr2O4、MnFe2O4、MnTiO3、MnWO4、CoFe2O4、ZnFe2O4、FeWO4、CoMoO4、CuTiO3、CuWO4、Ag2MoO4、Ag2WO4、ZnAl2O4、ZnMoO4、ZnWO4、CdSnO3、CdTiO3、CdMoO4、CdWO4、NaAlO2、MgAl2O4、SrAl2O4、Gd3Ga5O12、InFeO3、MgIn2O4、Al2TiO5、FeTiO3、MgTiO3、Na2SiO3、CaSiO3、ZrSiO4、K2GeO3、Li2GeO3、Na2GeO3、Bi2Sn3O9、MgSnO3、SrSnO3、PbSiO3、PbMoO4、PbTiO3、SnO2-Sb2O3、CuSeO4、Na2SeO3、ZnSeO3、K2TeO3、K2TeO4、Na2TeO3、Na2TeO4などの金属複合酸化物、FeS、Al2S3、MgS、ZnSなどの硫化物、LiF、MgF2、SmF3などのフッ化物、HgCl、FeCl2、CrCl3などの塩化物、AgBr、CuBr、MnBr2などの臭化物、PbI2、CuI、FeI2などのヨウ化物、またはSiAlONなどの金属酸化窒化物でも有効である。またボトムコンタクト構造ではゲート電極を陽極酸化することによりゲート絶縁膜を形成してもよい。例えばTa、Al、Mg、Ti、Nb、Zr等の単体もしくはそれらの合金などが有効である。また、ポリイミド、ポリアミド、ポリエステル、ポリアクリレート、エポキシ樹脂、フェノール樹脂、ポリビニルアルコール、などポリマー系材料でも有効である。また、ゲート絶縁膜表面をOTS、HMDSなどで撥水処理を行っても良い。 In the above embodiment, a polymer material in which PVP and melamine are mixed is used as the material of the gate insulating film 12 and the interlayer insulating film 19. However, the present invention is not limited to this. Membranes can also be used. For example, LiOx, LiNx, NaOx, KOx, RbOx, CsOx, BeOx, MgOx, MgNx, CaOx, CaNx, SrOx, BaOx, ScOx, YOx, YNx, LaOx, LaNx, CeOx, PrOx, NdOx, SmOx, E TbOx, DyOx, HoOx, ErOx, TmOx, YbOx, LuOx, TiOx, TiNx, ZrOx, ZrNx, HfOx, HfNx, ThOx, VOx, VNx, NbOx, TaOx, TaNx, CrOx, CrNx, MoOx, MoN MnOx, ReOx, FeOx, FeNx, RuOx, OsOx, CoOx, RhOx, IrOx, NiOx, PdOx, PtOx, CuOx, CuNx, AgOx, AuOx, ZnOx, CdOx, HgOx, BOx, BNx, AlOx, Nx InOx, TiOx, TiNx, SiOx, SiNx, GeOx, SnOx, pbOx, POx, PNx, AsOx, sbOx, SeOx, metal oxides such as TeOx, LiAlO 2, Li 2 SiO 3, Li 2 TiO 3, Na 2 Al 22 O 34 , NaFeO 2 , Na 4 SiO 4 , K 2 SiO 3 , K 2 TiO 3 , K 2 WO 4 , Rb 2 CrO 4 , Cs 2 CrO 4 , MgAl 2 O 4 , MgFe 2 O 4 , MgTiO 3 , CaTiO 3, CaWO 4, CaZrO 3, SrFe 12 O 19, SrTiO 3, SrZrO 3, BaAl 2 O 4, BaFe 12 O 19, BaTiO 3, Y 3 A l5 O 12, Y 3 Fe 5 O 12, LaFeO 3, La 3 Fe 5 O 12 , La 2 Ti 2 O 7 , CeSnO 4 , CeTiO 4 , Sm 3 Fe 5 O 12 , EuFeO 3 , Eu 3 Fe 5 O 12 , GdFeO 3 , Gd 3 Fe 5 O 12 , DyFeO 3 , Dy 3 Fe 5 O 12 , HoFeO 3 , Ho 3 Fe 5 O 12 , ErFeO 3 , Er 3 Fe 5 O 12 , Tm 3 Fe 5 O 12 , LuFeO 3 , Lu 3 Fe 5 O 12 , NiTiO 3 , Al 2 TiO 3 , FeTiO 3 , BaZrO 3, LiZrO 3, MgZrO 3, HfTiO 4, NH 4 VO 3, AgVO 3, LiVO 3, BaNb 2 O 6, NaNbO 3, SrNb 2 O 6, KTaO 3, NaTaO 3, SrTa 2 O 6, CuCr 2 O 4 , Ag 2 CrO 4 , BaCrO 4 , K 2 MoO 4 , Na 2 MoO 4 , NiMoO 4 , BaWO 4 , Na 2 WO 4 , SrWO 4 , MnCr 2 O 4 , MnFe 2 O 4 , MnTiO 3 , MnWO 4 , CoFe 2 O 4 , ZnFe 2 O 4 , FeWO 4 , CoMoO 4 , CuTiO 3 , CuWO 4 , Ag 2 MoO 4 , Ag 2 WO 4 , ZnAl 2 O 4 , ZnMoO 4 , ZnWO 4 , CdSnO 3 , CdTiO 3 , CdMoO 4 , CdWO 4 , NaAlO 2 , MgAl 2 O 4 , SrAl 2 O 4 , Gd 3 Ga 5 O 12 , InFeO 3 , MgIn 2 O 4 , Al 2 TiO 5 , FeTiO 3 , MgTiO 3 , Na 2 SiO 3 , CaSiO 3 , ZrSiO 4 , K 2 GeO 3 , Li 2 GeO 3 , Na 2 GeO 3 , Bi 2 Sn 3 O 9 , MgSnO 3 , SrSn O 3 , PbSiO 3 , PbMoO 4 , PbTiO 3 , SnO 2 -Sb 2 O 3 , CuSeO 4 , Na 2 SeO 3 , ZnSeO 3 , K 2 TeO 3 , K 2 TeO 4 , Na 2 TeO 3 , Na 2 TeO 4 Metal composite oxides such as, sulfides such as FeS, Al 2 S 3 , MgS, ZnS, fluorides such as LiF, MgF 2 , SmF 3 , chlorides such as HgCl, FeCl 2 , CrCl 3 , AgBr, CuBr, Even bromides such as MnBr 2 , iodides such as PbI 2 , CuI, and FeI 2 , or metal oxynitrides such as SiAlON are also effective. In the bottom contact structure, the gate insulating film may be formed by anodizing the gate electrode. For example, simple substances such as Ta, Al, Mg, Ti, Nb, Zr, or alloys thereof are effective. Further, it is also effective for polymer materials such as polyimide, polyamide, polyester, polyacrylate, epoxy resin, phenol resin, and polyvinyl alcohol. Further, the surface of the gate insulating film may be subjected to water repellent treatment using OTS, HMDS, or the like.
　また、上記の実施例では、有機ＴＦＴと有機ＥＬとを同一平面に形成した駆動回路の構造を示したが、これに限定されず、例えば有機ＴＦＴを形成した後その上部に平滑層としての層間絶縁膜を設け、この層間絶縁膜上に有機ＥＬを形成した積層構造としてもよい。また、有機ＴＦＴによって駆動されるデバイスは、液晶素子やその他のデバイスであってもよい。 In the above embodiment, the structure of the driving circuit in which the organic TFT and the organic EL are formed on the same plane is shown. However, the present invention is not limited to this. For example, after forming the organic TFT, an interlayer as a smoothing layer is formed on the organic TFT. A laminated structure in which an insulating film is provided and an organic EL is formed on the interlayer insulating film may be employed. Further, the device driven by the organic TFT may be a liquid crystal element or other devices.
　１０　基板
　１１ａ、１１ｂ　ゲート電極
　１２　ゲート絶縁膜
　１３、１５　ソース電極
　１４、１６　ドレイン電極
　１３ａ、１４ａ、１５ａ、１６ａ　第１の電極層
　１３ｂ、１４ｂ、１５ｂ、１６ｂ　第２の電極層
　１７ａ、１７ｂ　有機半導体層
　１８ａ、１８ｂ　チャネル領域
　１９　層間絶縁膜
　２０　撥液性バンク
　２１　開口部
　３０　開口部（離間部）
　３１　陽極
　３２　有機層
　３３　陰極 DESCRIPTION OF SYMBOLS 10 Substrate 11a, 11b Gate electrode 12 Gate insulating film 13, 15 Source electrode 14, 16 Drain electrode 13a, 14a, 15a, 16a 1st electrode layer 13b, 14b, 15b, 16b 2nd electrode layer 17a, 17b Organic semiconductor Layers 18a and 18b Channel region 19 Interlayer insulating film 20 Liquid repellent bank 21 Opening 30 Opening (separating part)
31 Anode 32 Organic layer 33 Cathode

Claims (17)

  1. 　少なくとも１つの有機薄膜トランジスタを含む半導体装置であって、
    　基板上に形成された前記ゲート電極と、
    　前記ゲート電極を覆うように形成されたゲート絶縁膜と、
    　前記ゲート絶縁膜を介して前記ゲート電極の上部から前記基板上まで延在し、且つ前記ゲート電極の上部において離間部を有する一対のソース／ドレイン電極と、
    　前記離間部において露出している前記ゲート絶縁膜および前記一対のソース／ドレイン電極と接するように設けられた有機半導体層と、
    　前記一対のソース／ドレイン電極上の前記有機半導体層を挟む位置に設けられた隔壁部と、を含み、
    　前記ソース／ドレイン電極は、前記ゲート電極上部から前記基板上部まで延在している第１の電極層と、前記隔壁部で覆われていない前記第１の電極層の一部に形成され且つ前記有機半導体層と接している第２の電極層と、を含むことを特徴とする半導体装置。     A semiconductor device comprising at least one organic thin film transistor,
    The gate electrode formed on the substrate;
    A gate insulating film formed to cover the gate electrode;
    A pair of source / drain electrodes extending from the upper part of the gate electrode to the substrate via the gate insulating film, and having a separation portion on the upper part of the gate electrode;
    An organic semiconductor layer provided so as to be in contact with the gate insulating film and the pair of source / drain electrodes exposed in the separation portion;
    A partition portion provided at a position sandwiching the organic semiconductor layer on the pair of source / drain electrodes,
    The source / drain electrodes are formed on a first electrode layer extending from an upper part of the gate electrode to an upper part of the substrate, and a part of the first electrode layer not covered with the partition wall, and And a second electrode layer in contact with the organic semiconductor layer.
  2. 　前記第２の電極層は、前記有機半導体層のチャネル領域と接する部分を含んでいることを特徴とする請求項１に記載の半導体装置。 The semiconductor device according to claim 1, wherein the second electrode layer includes a portion in contact with a channel region of the organic semiconductor layer.
  3. 　前記第２の電極層と前記有機半導体層との接触は、オーミック性接触であることを特徴とする請求項１又は２に記載の半導体装置。 3. The semiconductor device according to claim 1, wherein the contact between the second electrode layer and the organic semiconductor layer is an ohmic contact.
  4. 　前記第２の電極層は、置換めっき法によって形成されることを特徴とする請求項１乃至３のいずれか１つに記載の半導体装置。 4. The semiconductor device according to claim 1, wherein the second electrode layer is formed by a displacement plating method.
  5. 　前記第２の電極層は、置換めっき法および還元めっき法を併用して形成されることを特徴とする請求項１乃至３のいずれか１つに記載の半導体装置。 4. The semiconductor device according to claim 1, wherein the second electrode layer is formed by using a displacement plating method and a reduction plating method in combination.
  6. 　前記第２の電極層は、前記第１の電極層の構成材料よりもイオン化傾向の小さい材料からなることを特徴とする請求項１乃至５のいずれか１つに記載の半導体装置。 The semiconductor device according to claim 1, wherein the second electrode layer is made of a material having a smaller ionization tendency than the constituent material of the first electrode layer.
  7. 　前記第２の電極層は、貴金属または貴金属を含む合金からなることを特徴とする請求項６に記載の半導体装置。 The semiconductor device according to claim 6, wherein the second electrode layer is made of a noble metal or an alloy containing a noble metal.
  8. 　前記第２の電極層は、金または金を含む合金からなることを特徴とする請求項７に記載の半導体装置。 The semiconductor device according to claim 7, wherein the second electrode layer is made of gold or an alloy containing gold.
  9. 　前記隔壁部は、撥液性を有することを特徴とする請求項１乃至８のいずれか１つに記載の半導体装置。 9. The semiconductor device according to claim 1, wherein the partition wall has liquid repellency.
  10. 　前記有機薄膜トランジスタに接続された有機ＥＬ素子を更に含むことを特徴とする請求項１乃至９のいずれか１つに記載の半導体装置。 The semiconductor device according to claim 1, further comprising an organic EL element connected to the organic thin film transistor.
  11. 　有機薄膜トランジスタを含む半導体装置の製造方法であって、
    　基板上にゲート電極を形成する工程と、
    　前記ゲート電極を覆うようにゲート絶縁膜を形成する工程と、
    　前記ゲート絶縁膜上に前記ゲート電極上部から前記基板上部まで延在し、且つ前記ゲート電極上部において離間部を有する第１の電極層を形成する工程と、
    　前記ゲート電極形成位置に対応する部分に開口部を有する隔壁部を前記第１の電極層の上に形成する工程と、
    　前記隔壁部をマスクとして無電解めっき法により前記開口部において露出している前記第１の電極層の一部を覆うように第２の電極層を形成する工程と、
    　前記開口部内に、前記第１の電極層の離間部において露出している前記ゲート絶縁膜と前記第２の電極層とに接するように有機半導体層を形成する工程と、を含むことを特徴とする半導体装置の製造方法。     A method of manufacturing a semiconductor device including an organic thin film transistor,
    Forming a gate electrode on the substrate;
    Forming a gate insulating film so as to cover the gate electrode;
    Forming on the gate insulating film a first electrode layer extending from the upper part of the gate electrode to the upper part of the substrate and having a separation part on the upper part of the gate electrode;
    Forming a partition wall having an opening in a portion corresponding to the gate electrode formation position on the first electrode layer;
    Forming a second electrode layer so as to cover a part of the first electrode layer exposed in the opening by an electroless plating method using the partition wall as a mask;
    Forming an organic semiconductor layer in the opening so as to be in contact with the gate insulating film and the second electrode layer exposed at a separation portion of the first electrode layer. A method for manufacturing a semiconductor device.
  12. 　前記第２電極層を形成する工程は、置換めっき工程を含むことを特徴とする請求項１１に記載の半導体装置の製造方法。 12. The method of manufacturing a semiconductor device according to claim 11, wherein the step of forming the second electrode layer includes a displacement plating step.
  13. 　前記第２電極層を形成する工程は、置換めっき工程および還元めっき工程を含むことを特徴とする請求項１１に記載の半導体装置の製造方法。 12. The method of manufacturing a semiconductor device according to claim 11, wherein the step of forming the second electrode layer includes a displacement plating step and a reduction plating step.
  14. 　前記第２の電極層は、前記第１の電極層の構成材料よりもイオン化傾向の小さい材料からなることを特徴とする請求項１２又は１３に記載の半導体装置の製造方法。 14. The method of manufacturing a semiconductor device according to claim 12, wherein the second electrode layer is made of a material having a smaller ionization tendency than the constituent material of the first electrode layer.
  15. 　前記第２の電極層は、貴金属または貴金属を含む合金からなることを特徴とする請求項１４に記載の半導体装置の製造方法。 15. The method of manufacturing a semiconductor device according to claim 14, wherein the second electrode layer is made of a noble metal or an alloy containing a noble metal.
  16. 　前記隔壁部は撥液性を有することを特徴とする請求項１１乃至１５のいずれか１つに記載の半導体装置の製造方法。 The method of manufacturing a semiconductor device according to claim 11, wherein the partition wall portion has liquid repellency.
  17. 　前記有機半導体層はインクジェット法により形成されることを特徴とする請求項１６に記載の半導体装置の製造方法。 The method of manufacturing a semiconductor device according to claim 16, wherein the organic semiconductor layer is formed by an inkjet method.
PCT/JP2009/060862 2009-06-15 2009-06-15 Semiconductor device and method for manufacturing semiconductor device WO2010146645A1 (en)

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