WO2010106779A1 - 半導体素子用基板の製造方法および半導体装置 - Google Patents
半導体素子用基板の製造方法および半導体装置 Download PDFInfo
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- WO2010106779A1 WO2010106779A1 PCT/JP2010/001829 JP2010001829W WO2010106779A1 WO 2010106779 A1 WO2010106779 A1 WO 2010106779A1 JP 2010001829 W JP2010001829 W JP 2010001829W WO 2010106779 A1 WO2010106779 A1 WO 2010106779A1
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
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- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
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Definitions
- the present invention relates to a semiconductor element substrate for mounting a semiconductor element.
- the present invention relates to a method for manufacturing a lead frame substrate and a semiconductor device using the same.
- Interposer semiconductor element mounting board
- a semiconductor element is mounted on one surface of the interposer, and connection with the printed circuit board is made on the other surface or the periphery of the substrate.
- the interposer has a metal lead frame inside or on the surface, and an electrical connection path is routed by the lead frame to extend the pitch of external connection terminals for connection to a printed circuit board.
- FIGS. 2A to 2C are diagrams schematically showing a structure of an interposer using a QFN (Quad Flat Non-lead) type lead frame which is an example of a conventional interposer.
- a flat portion 15 of the lead frame on which the semiconductor element 16 is mounted is provided at the center of the lead frame made of mainly aluminum or copper.
- Leads 17 having a wide pitch are disposed on the outer periphery of the lead frame.
- the lead 17 and the electrical connection terminal of the semiconductor element 16 are connected by a wire bonding method using a metal wire 18 such as a gold wire.
- FIG. 2B the whole is finally molded with a molding resin 19 and integrated. 2A and 2B holds the lead frame, and after being molded with the molding resin 19, it is removed as shown in FIG. 2C.
- the connection between the printed board and the interposer is performed by attaching a metal pin to the extraction electrode 20 on the outer peripheral portion of the interposer.
- BGA Ball Grid Array
- solder balls are arranged in an array on external connection terminals on the outer periphery of an interposer.
- a method of multilayering and stacking the wiring layers of the interposer is often employed.
- Connection terminals of a semiconductor element having a small area and a large number of terminals are often formed in an array on the bottom surface of the semiconductor element. For this reason, a flip chip connection method is often employed in which the external connection terminals on the interposer side are arranged in the same array as the connection terminals of the semiconductor element, and a small solder ball is used for connection between the interposer and the printed circuit board. Wiring in the interposer is perforated from above with a drill or a laser in the vertical direction, and metal plating is performed in the hole, so that electrical conduction between the upper and lower layers is performed.
- the pitch of the external connection terminals can be reduced to about 150 to 200 ⁇ m, so that the number of connection terminals can be increased.
- the reliability and stability of the bonding are lowered, and it is not suitable for in-vehicle use where high reliability is required.
- these interposers are made of ceramic, P-BGA (Plastic Ball Grid Array), CSP (Chip Size Package), or LGA (Land Dry Array) depending on the material and structure used.
- P-BGA Physical Ball Grid Array
- CSP Chip Size Package
- LGA Land Dry Array
- Any of the above interposers can be used to reduce the size, increase the number of pins, or increase the speed of the semiconductor element.
- the pitch of the connection part with the semiconductor element is reduced, that is, the fine pitch and the high-speed signal are compatible. Is progressing. Considering the progress of miniaturization, the pitch of terminal portions of recent interposers needs to be about 80 to 100 ⁇ m.
- a lead frame serving as a conductive portion / cum / support member is typically formed by etching a thin metal plate.
- the thickness of the metal plate is desirably about 120 ⁇ m.
- a certain degree of metal layer thickness and land area are required. Considering the above conditions, it can be said that the minimum thickness of the metal plate for the lead frame is about 100 to 120 ⁇ m. In this case, if etching is performed from both sides of the metal plate, the lead pitch is limited to about 120 ⁇ m and the lead wire width is limited to about 60 ⁇ m.
- the lead frame is affixed to a holding material 21 made of polyimide tape, and the semiconductor element 16 is fixed to the flat portion 15 of the lead frame with fixing resin or fixing tape 22. Thereafter, wire bonding is performed, and a plurality of chips, that is, the semiconductor elements 16 are collectively molded with the molding resin 19 by a transfer molding method. After that, exterior processing is performed, and the interposer is cut into one piece.
- the molding resin 19 wraps around the connection terminal surface on the back surface of the lead frame and does not adhere to the connection terminals during molding. Therefore, the holding material 21 is necessary in the manufacturing process of the interposer. However, since the holding material 21 is finally unnecessary, it is necessary to remove and hold the holding material 21 after molding, leading to an increase in cost.
- Patent Document 1 discloses a lead frame-shaped substrate for a semiconductor element having a structure in which a resin for pre-molding is used as a support for wiring.
- a method of manufacturing the lead frame-shaped substrate for semiconductor elements described in Patent Document 1 will be described below.
- a resist pattern for forming a connection post is formed on the first surface of a copper metal plate, and a resist pattern for forming a wiring pattern is formed on the second surface.
- a premolding resin is applied to the first surface to form a premold layer, and then etching is performed from the second surface to form a wiring.
- the resist on both sides is peeled off.
- the lead frame-like semiconductor element substrate manufactured in this way has a stable etching because the pre-mold resin is a support even if the thickness of the metal is reduced to a level that enables fine etching. Is possible.
- the wire bonding property is also excellent.
- a holding material such as polyimide tape is not used, the cost spent on it can be reduced.
- the premold resin may become spherical due to the effect of the surface tension, and may remain in a narrow range. In this case, even if a small amount of the premold resin is injected, the premold resin is high. There is also a concern about the occurrence of defects due to high height and the occurrence of defects due to application beyond the height of the connection posts.
- a countermeasure plan for providing a plurality of injection locations at the bottom of the application surface is also conceivable, but due to the high viscosity of the premold resin, the premold resin is While moving from one injection location to another, this premold resin pulls the yarn, and the yarn adheres to the bottom of the connection post, and the premold resin moves on the application surface. It is thought that the defect that bubbles are included due to this is likely to occur.
- the present invention easily provides a premold resin to an appropriate thickness in the process of manufacturing a lead frame-like semiconductor element substrate with a premold using a liquid resin.
- a method for manufacturing a semiconductor element substrate and a semiconductor device are provided.
- a first aspect of the present invention is a method for manufacturing a substrate for a semiconductor element, which includes a mask process, a molding process, and a wiring pattern forming process, wherein the mask process is performed on a first surface of a metal plate.
- the first photosensitive resin layer developed is formed on the first surface of the metal plate by selectively performing exposure according to the pattern of 1 and developing the first photosensitive resin layer. Forming a first etching mask for forming a connection post, and selectively exposing the second photosensitive resin layer in accordance with a second pattern, whereby the second photosensitive resin layer is exposed.
- the development is performed on the second surface of the metal plate by developing the conductive resin layer.
- a method for manufacturing a substrate for a semiconductor element, comprising etching the second surface of the plate to form a wiring pattern.
- a substrate for a semiconductor element according to the first aspect of the present invention, wherein the liquid resin for pre-molding is applied in a vacuum chamber.
- the thickness of applying the liquid resin for the pre-mold is not set higher than the height of the connection post.
- the first and second etching masks are peeled off after the molding step and the wiring pattern forming step are completed. It is a manufacturing method of the board
- the first and second etching masks are removed after the molding step and the wiring pattern forming step are completed. This is a method for manufacturing a semiconductor element substrate.
- a metal plate having a first surface and a second surface different from the first surface, a connection post disposed on the first surface of the metal plate,
- a semiconductor element comprising: a wiring pattern disposed on the second surface of the metal plate; and a premold resin layer in which a portion of the first surface where the connection posts do not exist is filled with a premold resin. Substrate.
- a semiconductor element is mounted on the semiconductor element substrate according to the sixth aspect of the present invention, and the semiconductor element substrate and the semiconductor element are electrically connected by wire bonding. It is a semiconductor substrate characterized by the above-mentioned.
- the eighth aspect of the present invention is the semiconductor element substrate according to the sixth aspect of the present invention, characterized in that the height of the pre-mold resin layer is not higher than the height of the connection post.
- a ninth aspect of the present invention is the semiconductor substrate according to the seventh aspect of the present invention, wherein the height of the premold resin layer is not higher than the height of the connection post.
- the present invention when manufacturing a lead frame type substrate with a pre-mold, it is possible to prevent the height of the liquid pre-mold resin from being higher than that of the connection post without including bubbles.
- This height of the pre-mold resin has the advantages that it has sufficient rigidity as a support for the lead frame-shaped substrate and that the connection posts are easily exposed. Therefore, it has sufficient mechanical strength, and high reliability and high bonding strength can be obtained for electrical connection.
- Explanatory drawing which shows typically the manufacturing process of the board
- Explanatory drawing which shows typically the manufacturing process of the board
- Explanatory drawing which shows typically the manufacturing process of the board
- Explanatory drawing which shows typically the manufacturing process of the board
- Explanatory drawing which shows typically the manufacturing process of the board
- Explanatory drawing which shows typically the manufacturing process of the board
- Explanatory drawing which shows typically the manufacturing process of the board
- Explanatory drawing which shows typically the manufacturing process of the board
- the LGA size of each manufactured unit is 10 mm square, and has external connection parts in an array shape in plan view of 168 pins.
- the LGA was multifaceted to the substrate and cut and cut after the following manufacturing steps to obtain individual LGA type lead frame type substrates.
- a long strip-shaped copper substrate 1 having a width of 150 mm and a thickness of 150 ⁇ m was prepared.
- both sides of the copper substrate 1 are coated with a photosensitive resist 2 (manufactured by Tokyo Ohka Kogyo Co., Ltd., OFPR4000) to a thickness of 5 ⁇ m with a roll coater, and then prebaked at 90 ° C. did.
- a photosensitive resist 2 manufactured by Tokyo Ohka Kogyo Co., Ltd., OFPR4000
- First resist pattern 3 and second resist pattern 7 were obtained.
- the connection post 5 is provided on one surface side of the copper substrate 1 (the surface opposite to the surface on which the semiconductor element 10 is mounted, in the present embodiment, hereinafter referred to as the first surface side).
- a first resist pattern 3 for forming is formed on one surface side of the copper substrate 1 (the surface on which the semiconductor element 10 is mounted, which will be referred to as the second surface side in this embodiment). Formed.
- the semiconductor element 10 is mounted on the upper surface of the lead frame at the center of the copper substrate 1.
- a wire bonding land 4 is formed on the upper surface of the outer periphery of the lead frame near the outer periphery of the semiconductor element 10.
- the outer periphery of the semiconductor element 10 and the land 4 are connected by a thin gold wire 8.
- connection posts 5 for guiding an electrical signal from the upper wiring to the back surface are arranged, for example, in an array in plan view. Further, it is necessary to electrically connect some of the lands 4 to the connection posts 5. Therefore, the wiring patterns 6 respectively connected to some of the lands 4 are formed radially, for example, from the outer periphery of the substrate toward the center so as to be connected to the connection posts 5 (not shown).
- the first etching treatment is performed, As shown in FIG. 1D, the thickness of the copper substrate 1 portion exposed from the first resist pattern 3 on the first surface side was reduced to 30 ⁇ m.
- the specific gravity of the ferric chloride solution was 1.38, and the liquid temperature was 50 ° C.
- the copper substrate 1 in the portion where the first resist pattern 3 for forming the connection post 5 is formed is not etched. Therefore, in the thickness direction of the copper substrate 1, external connection with the printed circuit board extending from the etching surface formed by the first etching process to the lower side surface of the copper substrate 1 is possible.
- a connection post 5 can be formed.
- the copper substrate 1 at the site where the etching process is to be performed is not completely dissolved and removed by the etching process, but the etching process is terminated when the copper substrate 1 has a predetermined thickness. Etching is performed halfway.
- the resist pattern 3 was peeled off with a 20% aqueous sodium hydroxide solution, and the temperature of the peeling solution was 100 ° C.
- a liquid resin for premolding was applied to the lower surface of the first surface formed by the first etching by a potting method.
- a liquid thermosetting resin (“SMC-376KF1” manufactured by Shin-Etsu Chemical Co., Ltd.) was used as the liquid resin for premolding.
- a release film 14 having a low elastic modulus of 5 to 0.01 GPa was placed on the applied liquid resin for premolding, and was pressed in a vacuum chamber to form a premolding resin layer 11. The thickness of the release film 14 was adjusted to 130 ⁇ m so that the liquid for pre-molding was filled to a height not covering the bottom surface of the connection post.
- a vacuum / pressure laminating apparatus was used.
- the pre-mold liquid resin was pressed at a temperature of 100 ° C., a vacuum degree in the vacuum chamber of 0.2 torr, and a press time of 30 seconds.
- covering the liquid resin for premolding with the release film 14 having a low elastic modulus and performing the vacuum press processing not only simplifies the processing by the potting method using the liquid resin, but also the premolding.
- By adjusting the application amount of the liquid resin for connection it is possible to make the connection post higher than the resin surface in terms of eliminating the defect that the resin is covered on the connection post 5, and it is stable with the printed circuit board. It is effective in that it can be connected to. Further, by performing press working in a vacuum chamber, there is an effect of eliminating voids generated in the resin, and generation of voids in the resin can be suppressed.
- the liquid resin was pressed, it was heated at 180 ° C. for 60 minutes as a post bake. After the post-baking of the premold resin, the release film was removed, the back sheet on the second surface was removed, and then the second surface was etched.
- the etching solution a ferric chloride solution was used, the specific gravity of the solution was 1.32 and the temperature of the solution was 50 ° C. The purpose of the etching is to form the wiring pattern 6 on the second surface, and the copper exposed from the second resist pattern 7 on the second surface is dissolved and removed.
- the second resist pattern 7 and the release film 14 on the second surface were peeled off to obtain a desired lead frame LGA substrate.
- the exposed metal surface of the first surface was subjected to a surface treatment by an electroless nickel / palladium / gold plating forming method to form a plating layer 12.
- an electrolytic plating method can also be applied.
- the electrolytic plating method since it is necessary to form a plating electrode for supplying a plating current, the wiring area is narrowed as much as the plating electrode is formed, so that it is difficult to route the wiring. We are concerned about defects.
- the electroless nickel / palladium / gold plating forming method that does not require a supply electrode is generally preferred.
- the plating layer 12 was formed on the metal surface by the procedures of acidic degreasing, soft etching, acid cleaning, platinum catalyst activation treatment, pre-dip, electroless platinum plating, and electroless gold plating.
- the plating thickness was 3 ⁇ m for nickel, 0.2 ⁇ m for palladium, and 0.03 ⁇ m for gold.
- nickel is Enplate NI (made by Meltex)
- palladium is Paulobond EP (made by Rohm and Haas)
- gold is Paulobond IG (made by Rohm and Haas).
- the semiconductor element 10 was bonded and mounted on the lead frame with a fixing adhesive or a fixing tape 13. After that, wire bonding was performed between the electrical connection terminals of the semiconductor element 10 and the wire bonding lands 4 of the wiring pattern using the fine gold wires 8. Thereafter, molding was performed so as to cover the lead frame and the semiconductor element 10. Thereafter, the imprinted semiconductor substrate was cut to obtain individual semiconductor substrates.
- the manufacturing method and the semiconductor device for a semiconductor element substrate according to the present embodiment facilitate the premold resin to an appropriate thickness in the process of manufacturing a lead frame-shaped semiconductor element substrate with a premold using a liquid resin. It could be provided.
- the height of the liquid pre-mold resin can be prevented from becoming higher than that of the connection post without including bubbles.
- This height of the pre-mold resin has the advantages that it has sufficient rigidity as a support for the lead frame type substrate and that the connection posts are easily exposed. Therefore, it has sufficient mechanical strength, and high reliability and high bonding strength can be obtained for electrical connection.
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Abstract
Description
本願は、2009年3月17日に、日本に出願された特願2009-064231号に基づき優先権を主張し、その内容をここに援用する。
このインターポーザの一方の面に、半導体素子を実装し、他方の面もしくは基板の周辺でプリント基板との接続が成される。インターポーザは内部もしくは表面に金属リードフレームを有しており、リードフレームにより電気的接続経路を引き回して、プリント基板との接続を行う外部接続端子のピッチを拡張している。
図2Aに示すように、材質が主にアルミニウムまたは銅のいずれかで出来たリードフレームの中央部に半導体素子16を搭載するリードフレームの平坦部分15を設ける。リードフレームの外周部にはピッチの広いリード17を配設する。リード17と半導体素子16の電気的接続用端子との接続は、金線などのメタルワイヤー18を使用したワイヤーボンディング法によって行われる。図2Bに示すように、最終的には全体をモールド用樹脂19でモールドして一体化する。
尚、図2Aと図2B中に描かれた保持材21はリードフレームを保持するもので、モールド用樹脂19でモールドした後に図2Cに示すように除去される。
面積が狭く端子数が多い半導体素子においては、配線層が一層のみのインターポーザではピッチの変換が困難である。その為、インターポーザの配線層を多層化し積層する手法がよく採用されている。
但し、接合の信頼性や安定性は低下し、高い信頼性が要求される車載用などには向いていない。
上記のいずれのインターポーザも、半導体素子の小型化、多ピン化、又は高速化に対応して、インターポーザ側でも、半導体素子との接続部分のピッチの微細化すなわちファインピッチ化や高速信号への適合化が進んでいる。微細化の進展を考慮すると、最近のインターポーザの端子部分のピッチは凡そ80~100μmが必要である。
上記の条件を考慮すると、リードフレーム用の金属板の厚さとしては最低でも凡そ100~120μm程度が必要といえる。
また、その場合には、金属板の両側からエッチング加工を行うとして、リードのピッチで120μm程度まで、リード線幅は60μm程度までの微細化が限界とされている。
その後、ワイヤーボンディングを行い、トランスファーモールド法で複数のチップすなわち半導体素子16をモールド用樹脂19で一括してモールドしてしまう。
しかる後に、外装加工を施し、インターポーザが1個1個になるよう断裁してしまう。
しかし、最終的には保持材21は不要であるため、モールド加工をした後に、保持材21を取り外して棄てる必要があり、コストアップに繋がってしまう。
例えば銅製の金属板の第1の面には接続用ポスト形成用のレジストパターンを、また第2の面には配線パターン形成用のレジストパターンをそれぞれ形成し、第1の面の上から、金属板を所望の厚さまでエッチングしたのち、第1の面にプリモールド用樹脂を塗布し、プリモールド層を形成し、その後に、第2の面からエッチングを行い、配線を形成して、最後に両面のレジストを剥離している。
このようにして製造したリードフレーム状の半導体素子用基板は、金属の厚さをファインエッチングが可能なレベルまで薄くしても、プリモールド用樹脂が支持体となっている為に、安定したエッチングが可能である。また超音波エネルギーの拡散が小さい為に、ワイヤーボンディング性にも優れる。さらに、ポリイミドテープなどの保持材を使用しない為、それに費やしていたコストも削減できる。
このような厚さを制御して塗布する為の具体策としては、例えば、シリンジ等を用いて塗布面の底の一点から樹脂を流し込み、それが塗布面全体まで濡れ広がるのを待つ手法が考えられる。しかし、プリモールド用樹脂はある程度の粘性を持っている為に、プリモールド用樹脂が塗布面の全体に濡れ広がるのにあまりに長い時間を要してしまうことになるので、これでは生産性の面では問題となってしまう。
また、ディスペンサー等の装置を用いて、塗布面の底に複数の注入箇所を設けてやる対策案も考えられるが、やはりプリモールド用樹脂の粘性の高さの為に、プリモールド用樹脂が、ある注入箇所から他の箇所に移動していく間に、このプリモールド用樹脂が糸をひき、糸が接続用ポストの底面に付着するという不良や、塗布面をプリモールド用樹脂が移動することによって気泡を含んでしまうという不良も発生しやすいと考えられる。
尚、銅基板1の一方の面側(半導体素子10が搭載される面とは反対側の面であり、本実施例では以下、第1の面側と記す)には、接続用ポスト5を形成するための第1のレジストパターン3を形成する。銅基板1の他方の面側(半導体素子10が搭載される面であり、本実施例では以下、第2の面側と記す)には、配線パターンを形成するための第2のレジストパターン7を形成した。
また、ランド4のうち幾つかを、接続用ポスト5に電気的に接続させる必要がある。その為、ランド4の幾つかと各々接続した配線パターン6を接続用ポスト5と接続するよう基板の外周から中心方向に向けて、例えば放射状に形成している(図示せず)。
塩化第二鉄溶液の比重は1.38、液温50℃とした。第1回目のエッチングの際、接続用ポスト5形成用の第1のレジストパターン3が形成された部位の銅基板1には、エッチング処理が行われない。そのため、銅基板1の厚み方向に、第1回目のエッチング処理で形成されたエッチング面から銅基板1下側面までの高さを有して延在する、プリント基板との外部接続を可能とした接続用ポスト5を形成することが出来る。
なお、第1回目のエッチングでは、エッチング処理を行う部位の銅基板1をエッチング処理で完全に溶解除去するものではなく、所定の厚さの銅基板1となった段階でエッチング処理を終了するよう、中途までエッチング処理を行う。
上記プレス加工に際しては、真空加圧式ラミネート装置を用いた。プレス部の温度は100℃、真空チャンバー内の真空度は0.2torr、プレス時間は30秒にてプリモールド用液状樹脂のプレス加工を行った。
また、真空チャンバー内でのプレス加工を行うことによって、樹脂内に生じた空隙を解消する効果があり、樹脂内のボイドの発生を抑えることができる。
ここで、リードフレームへのめっき層12の形成には他に、電解めっき法も適用可能ではある。しかし、電解めっき法によると、めっき電流を供給するためのめっき電極の形成が必要になるので、めっき電極を形成する分、配線領域が狭くなってしまうことから、配線の引き回しが困難になり易い欠点も心配される。
この観点で、供給用電極が不要な、無電解ニッケル/パラジウム/金めっき形成法の方が一般に好ましい。
めっき厚さはニッケルが3μm、パラジウムが0.2μm、金が0.03μmとした。使用しためっき液は、ニッケルがエンプレートNI(メルテックス社製)、パラジウムがパウロボンドEP(ロームアンドハース社製)、金がパウロボンドIG(ロームアンドハース社製)である。
プリモールド樹脂のこの高さは、リードフレーム型基板の支持体として、十分な剛性をもち、且つ、接続用ポストが露出しやすいという長所を呈する。そのため、十分な機械的強度を持ち、且つ、電気的な接続を行うことについても高い信頼性と高い接合強度を得られる。
2 感光性レジスト
3 第1のレジストパターン
4 ワイヤボンディング用ランド
5 接続用ポスト
6 配線パターン
7 第2のレジストパターン
8 金細線
10 半導体素子
11 プリモールド樹脂層
12 めっき層
13 固定用接着剤もしくは固定用テープ
14 離型フィルム
15 リードフレームの平坦部分
16 半導体素子
17 リード
18 メタルワイヤー
19 モールド用樹脂
20 取り出し電極
21 保持材
22 固定用樹脂もしくは固定用テープ
Claims (9)
- マスク工程と、モールド工程と、配線パターン形成工程と、を含む半導体素子用基板の製造方法であって、
前記マスク工程は、
金属板の第1の面に第1の感光性樹脂層を設けることと、
前記金属板の前記第1の面とは異なる第2の面に第2の感光性樹脂層を設けることと、
前記第1の感光性樹脂層に対し第1のパターンに応じて選択的に露光を行い、前記第1の感光性樹脂層を現像することにより、前記金属板の前記第1の面に、前記現像された前記第1の感光性樹脂層からなる、接続用ポスト形成用の第1のエッチング用マスクを形成することと、
前記第2の感光性樹脂層に対し第2のパターンに応じて選択的に露光を行い、前記第2の感光性樹脂層を現像することにより、前記該金属板の前記第2の面に、前記現像された前記第2の感光性樹脂層からなる、配線パターン形成用の第2のエッチング用マスクを形成することと、を含み、
前記モールド工程は、
前記マスク工程の後に、前記第1の面側から前記金属板の中途まで前記金属板の前記第1の面のエッチングを行い、前記接続用ポストを形成することと、
プリモールド用の液状樹脂を前記エッチングされた前記金属板の前記第1の面に塗布することと、
前記塗布されたプリモールド用の液状樹脂を硬化させてプリモールド樹脂層を形成することと、を含み、
前記配線パターン形成工程は、
前記第2の面側から前記金属板の前記第2の面のエッチングを行い、配線パターンを形成すること、
を含む、半導体素子用基板の製造方法。 - 前記プリモールド用の液状樹脂の塗布を真空チャンバー内で行うこと、を特徴とする請求項1に記載の半導体素子用基板の製造方法。
- 前記プリモールド用の液状樹脂を塗布する厚さを前記接続用ポストの高さよりも高くしないこと、を特徴とする請求項1又は2のいずれかに記載の半導体素子用基板の製造方法。
- 前記モールド工程、及び前記配線パターン形成工程が終了した後に、前記第1及び第2のエッチング用マスクを剥離すること、を特徴とする請求項1又は2のいずれかに記載の半導体素子用基板の製造方法。
- 前記モールド工程、及び前記配線パターン形成工程が終了した後に、前記第1及び第2のエッチング用マスクを剥離すること、を特徴とする請求項3に記載の半導体素子用基板の製造方法。
- 第1の面および前記第1の面とは異なる第2の面を持つ金属板と、
前記金属板の前記第1の面に配置された接続用ポストと、
前記金属板の前記第2の面に配置された配線パターンと、
前記第1の面の前記接続用ポストの存在しない部分にプリモールド用樹脂が充填されたプリモールド樹脂層と、
を含む、半導体素子用基板。 - 請求項6に記載の半導体素子用基板に、半導体素子が実装されており、前記半導体素子用基板と前記半導体素子とがワイヤーボンディングで電気的に接続されていること、を特徴とする、半導体基板。
- 前記プリモールド樹脂層の高さが前記接続用ポストの高さよりも高くないこと、を特徴とする、請求項6に記載の半導体素子用基板。
- 前記プリモールド樹脂層の高さが前記接続用ポストの高さよりも高くないこと、を特徴とする、請求項7に記載の半導体基板。
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- 2010-03-15 KR KR1020117022905A patent/KR101648602B1/ko active IP Right Grant
- 2010-03-15 TW TW99107433A patent/TWI473175B/zh not_active IP Right Cessation
- 2010-03-15 CN CN201080012230.XA patent/CN102356462B/zh not_active Expired - Fee Related
- 2010-03-15 SG SG2011067980A patent/SG174486A1/en unknown
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2011
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Also Published As
Publication number | Publication date |
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KR20110129446A (ko) | 2011-12-01 |
US20120061809A1 (en) | 2012-03-15 |
TWI473175B (zh) | 2015-02-11 |
TW201113956A (en) | 2011-04-16 |
CN102356462B (zh) | 2015-07-29 |
SG174486A1 (en) | 2011-11-28 |
JP2010219288A (ja) | 2010-09-30 |
JP5672652B2 (ja) | 2015-02-18 |
KR101648602B1 (ko) | 2016-08-16 |
CN102356462A (zh) | 2012-02-15 |
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