WO2010095313A1 - 表示装置および表示装置の駆動方法 - Google Patents
表示装置および表示装置の駆動方法 Download PDFInfo
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- WO2010095313A1 WO2010095313A1 PCT/JP2009/068414 JP2009068414W WO2010095313A1 WO 2010095313 A1 WO2010095313 A1 WO 2010095313A1 JP 2009068414 W JP2009068414 W JP 2009068414W WO 2010095313 A1 WO2010095313 A1 WO 2010095313A1
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- 238000000034 method Methods 0.000 title claims description 32
- 230000005855 radiation Effects 0.000 description 31
- 239000004973 liquid crystal related substance Substances 0.000 description 19
- 239000003990 capacitor Substances 0.000 description 18
- 230000000694 effects Effects 0.000 description 16
- 238000010586 diagram Methods 0.000 description 14
- 230000007704 transition Effects 0.000 description 11
- 238000001514 detection method Methods 0.000 description 5
- 230000000630 rising effect Effects 0.000 description 5
- 239000011159 matrix material Substances 0.000 description 3
- 230000001174 ascending effect Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 230000003111 delayed effect Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
- G09G3/3655—Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3614—Control of polarity reversal in general
Definitions
- the present invention relates to a display device that performs common inversion driving.
- Common inversion driving is to invert the common electrode potential between positive and negative in AC driving.
- the gradation reference voltage range Vp of the positive polarity data and the gradation reference voltage range Vn of the negative polarity data are made equal to each other, and the common electrode potential Vcom is set to the corresponding level. Inversion is performed for each horizontal period between the binary level of the voltage level V1 on the higher side and the voltage level V2 on the lower side of the adjustment reference voltage range.
- the common electrode potential Vcom is set to the voltage level V2.
- the common electrode potential Vcom is set to the voltage level V1.
- the common inversion driving it is not necessary to prepare the gradation reference voltage ranges for the positive polarity data and the negative polarity data separately, so that the power supply voltage can be lowered. Further, since the gradation reference voltage is common to the positive polarity data and the negative polarity data, the configuration of the circuit that generates the gradation reference voltage can be simplified.
- the common electrode potential Vcom is supplied from the output stage 101 of the common electrode driving circuit to the common electrode 103 as shown in FIG.
- the output stage 101 is in accordance with a common polarity inversion signal that is switched between High and Low.
- the voltage level V1 on the high potential side and the voltage level V2 on the low potential side are switched every horizontal period and output from the COM output terminal 102.
- the common electrode 103 is connected to the COM output terminal 102, and a liquid crystal capacitor CL is formed with a liquid crystal layer interposed between the common electrode 103 and the pixel electrode 104.
- the common electrode 103 itself also has a capacitor. Therefore, the common inversion driving is an operation in which the common electrode driving circuit charges these capacitors alternately positive and negative.
- JP 2006-178072 A Japanese Patent Laid-Open No. 4-28489 (published October 9, 1992)
- the output stage 101 including the push-pull output stage of the common electrode driving circuit includes the output transistor Tp including the p-channel field effect transistor on the positive side of the common electrode potential Vcom and the negative polarity.
- the ON resistance of the output transistor Tn formed of the n-channel field effect transistor on the side is small, and these ON resistances dominate the output impedance of the output stage 101.
- the output transistors Tp and Tn may be bipolar transistors. When the common polarity inversion signal is at a high level, the output transistor Tn is turned on. When the common polarity inversion signal is at a low level, the output transistor Tp is turned on. This inrush current causes radiation noise.
- the liquid crystal display device when the liquid crystal display device includes the capacitive touch panel 112 on the liquid crystal panel 111 through a gap, the capacitance change in the detection operation of the touch panel 112. Therefore, the detection operation of the touch panel 112 is easily affected by the radiation noise. As a result, an error due to radiation noise occurs in the detection result, the detection accuracy of the touch panel 112 is lowered, and a significant reduction in sensitivity is caused.
- the VCOMH generation circuit 110 (high potential side voltage generation circuit) outputs the high potential side voltage VCOM based on the high potential side input voltage
- the VCOML generation circuit 120 ( The low potential side voltage generating circuit) outputs the low potential side voltage VCOM based on the low potential side input voltage.
- the power supply circuit 100 can control the supply capability of the common electrode potential by the VCOMH generation circuit 110 and the VCOML generation circuit 120. When the common electrode potential drops due to the polarity inversion of the common electrode potential or voltage application to the pixel electrode, the supply capability of the common electrode potential is increased, and at other times, the supply capability is reduced.
- Patent Document 1 increases the supply capability of the common electrode potential when the drop of the common electrode potential is large, the peak of the inrush current is large. Therefore, when a touch panel is mounted on the liquid crystal panel, the influence of radiation noise due to inrush current is large, and the detection accuracy of the touch panel is lowered.
- the display drive circuit of the plasma display panel of Patent Document 2 shown in FIG. 14 has a configuration in which capacitive display cells 11 arranged in a matrix are driven by a Y-side driver circuit 12 and an X-side driver circuit 13.
- the Y-side applied pulse YSUS is supplied to the transistor QY1 from the Y-side timing generator 32
- the Y-side tristate control signal YTSC is supplied to the transistor QY2
- the X-side applied pulse XSUS is supplied to the transistor QX2 from the X-side timing generator 33.
- An X-side tristate control signal XTSC is supplied.
- the tri-state control signals YTSC and XTSC are set so that the outputs of the Y-side driver circuit 12 and the X-side driver circuit 13 are in a high impedance state when they are “L”.
- the control signal YTSC or XTSC is set to “L” to set the output of the Y-side driver circuit 12 or X-side driver circuit 13 to a high impedance state, and the current level of the displacement current flowing through the capacitance of the display cell 11 is lowered.
- the pulse falls, the pulse falls while the current is suppressed, and the high voltage X-side application pulse XSUS or the Y-side application pulse YSUS is given to the counter electrode driver circuit, so that the counter electrode Set the output of the driver circuit on the side to a low impedance state.
- radiation noise due to switching and ground noise due to discharge current can be suppressed when the high-voltage applied pulse falls.
- the present invention has been made in view of the above-described conventional problems, and an object of the present invention is to realize a display device capable of effectively suppressing radiation noise when the common electrode potential is inverted, and a display device driving method. There is to do.
- the display device of the present invention is a display device that performs common inversion driving, and the output stage of the common electrode driving circuit has a plurality of outputs each capable of outputting a voltage to the common electrode.
- a sub-output stage, and each supply period of the common electrode potential of each polarity is divided into a plurality of partial periods, and each of the partial periods includes one or more sub-output stages selected for each of the partial periods.
- the overall load driving capability of the final sub-output stage consisting of one or more sub-output stages selected during the partial period in which a voltage is supplied to the common electrode and the final potential of the common electrode potential of each polarity is supplied
- the overall load driving capability of the initial sub-output stage composed of one or more sub-output stages selected in the partial period including the start of the polarity inversion operation of the common electrode potential is smaller.
- the start timing of each period of the partial period included in the transition time in which the polarity of the common electrode potential is reversed including the partial period in which the voltage is output by the initial sub-output stage as the current flowing in the common electrode
- a display device driving method is a display device driving method that performs common inversion driving, and each of the plurality of sub-output stages is capable of outputting a voltage to a common electrode. And each supply period of the common electrode potential of each polarity is divided into a plurality of partial periods, and each partial period is provided in the output stage of the common electrode driving circuit selected for each partial period.
- the overall load drive capability of the initial sub-output stage composed of one or more sub-output stages selected in the partial period including the start of the polarity inversion operation of the common electrode potential is smaller than the overall load drive capability of It is characterized in that.
- the start timing of each period of the partial period included in the transition time in which the polarity of the common electrode potential is reversed including the partial period in which the voltage is output by the initial sub-output stage as the current flowing in the common electrode
- the display device of the present invention is a display device that performs common inversion driving, and in each supply period of the common electrode potential of each polarity, after the polarity inversion of the common electrode potential is started,
- the waveform of the common electrode potential once reaches the potential on the opposite polarity side of the final potential of the common electrode potential of each polarity, and then reaches the final potential at a rate of change larger than when the potential reaches the middle potential. It is characterized by rising toward the potential.
- the display device driving method of the present invention is a display device driving method that performs common inversion driving, wherein the polarity inversion of the common electrode potential is performed in each supply period of the common electrode potential of each polarity.
- the display device is a display device that performs common inversion driving, and the output stage of the common electrode driving circuit includes a plurality of sub-output stages each capable of outputting a voltage to the common electrode.
- Each of the supply periods of the common electrode potential of each polarity is divided into a plurality of partial periods, and each of the partial periods includes a common electrode by one or more sub-output stages selected for each of the partial periods.
- the common electrode is more than the overall load driving capability of the final sub-output stage composed of one or more sub-output stages selected in the partial period for supplying the voltage to the common electrode potential of each polarity.
- the overall load driving capability of the initial sub-output stage composed of one or more sub-output stages selected in the partial period including the start of the potential polarity reversal operation is smaller.
- the display device driving method of the present invention is a display device driving method that performs common inversion driving, and includes a plurality of sub-output stages each capable of outputting a voltage to a common electrode. And each supply period of the common electrode potential of each polarity is divided into a plurality of partial periods, and each of the partial periods is provided for the output stage of the common electrode driving circuit selected for each partial period.
- the sub-output stage supplies a voltage to the common electrode and supplies the final arrival potential of the common electrode potential of each polarity.
- the entire final sub-output stage comprising one or more sub-output stages selected in the partial period is supplied.
- the overall load driving capability of the initial sub-output stage composed of one or more sub-output stages selected in the partial period including the start of the polarity inversion operation of the common electrode potential is smaller than the load driving capability.
- FIG. 1 showing an embodiment of the present invention, is a circuit block diagram showing a first configuration of an output stage of a common electrode driving circuit.
- FIG. It is a wave form diagram which shows the operation
- FIG. 5 is a waveform diagram showing operation waveforms of the output stage of FIG. 4.
- FIG. 11 is a circuit block diagram illustrating a third configuration of the output stage of the common electrode driving circuit according to the embodiment of the present invention.
- FIG. 9 is a circuit block diagram illustrating a fourth configuration of the output stage of the common electrode driving circuit according to the embodiment of the present invention. It is a wave form diagram which shows the operation
- FIG. 10 is a circuit diagram illustrating in detail a configuration of an output stage of the common electrode driving circuit of FIG. 9. It is sectional drawing which shows a prior art and shows the structure of the liquid crystal display device carrying a touch panel. It is a circuit block diagram which shows a prior art and shows the other structural example of a common electrode drive circuit. It is a circuit block diagram which shows a prior art and shows the structure of the display drive circuit of a plasma display panel.
- FIG. 15 is a waveform diagram showing operation waveforms of the display drive circuit of FIG. 14.
- FIGS. 1 to 8 Embodiments of the present invention will be described with reference to FIGS. 1 to 8 as follows.
- FIG. 3 shows a configuration of a liquid crystal display device (display device) 1 according to the present embodiment.
- the liquid crystal display device 1 is an active matrix display device, and includes a gate driver 3 as a scanning signal line drive circuit, a source driver 4 as a data signal line drive circuit, a display unit 2, a gate driver 3 and a source driver 4
- the display control circuit 5 and the power supply circuit 6 are provided.
- the liquid crystal display device 1 performs driving in which the data polarities of all the pixels are the same during the same horizontal period for each row, such as gate line inversion driving as alternating current driving or driving in which the polarity is inverted for each row. . Further, common inversion driving is performed to invert the polarities of the common electrode potentials in a period in which positive polarity data is supplied to the panel and a period in which negative polarity data is supplied to the panel.
- the display unit 2 includes gate lines GL1 to GLm as a plurality (m) of scanning signal lines, and source lines as a plurality (n) of data signal lines intersecting each of the gate lines GL1 to GLm. SL1 to SLn, and a plurality (m ⁇ n) of picture elements PIX... Provided corresponding to the intersections of the gate lines GL1 to GLm and the source lines SL1 to SLn, respectively.
- the display unit 2 includes storage capacitor lines CSL... In parallel with the gate lines GL1 to GLm, and one display element row composed of n picture elements arranged in the direction. A storage capacitor line CSL is allocated.
- the plurality of picture elements PIX are arranged in a matrix to form a picture element array, and each picture element PIX includes a TFT 14, a liquid crystal capacitor CL, and a holding capacitor Cs.
- the gate electrode of the TFT 14 is connected to the gate line GLj (1 ⁇ j ⁇ m), the source electrode is connected to the source line SLi (1 ⁇ i ⁇ n), and the drain electrode is connected to the pixel electrode.
- the liquid crystal capacitor CL is composed of a picture element electrode, a common electrode facing the picture element electrode, and a liquid crystal layer sandwiched therebetween.
- a common electrode potential Vcom is applied from the power supply circuit 6 to the common electrode.
- a storage capacitor potential Vcs is applied from the power supply circuit 6 to the storage capacitor lines CSL.
- the liquid crystal capacitor CL and the holding capacitor Cs constitute a pixel capacitor. However, there is a parasitic capacitor formed between the pixel electrode and the peripheral wiring as another capacitor constituting the pixel capacitor.
- the display control circuit 5 supplies the gate driver 3 with the gate start pulse GSP and the gate clock signal GCK, and supplies the source driver 4 with the source start pulse SSP, the source clock signal SCK, and the display data DA.
- the power supply circuit 6 generates and supplies a gradation reference voltage to the source driver 4 and generates and outputs the common electrode potential Vcom and the storage capacitor potential Vcs.
- FIG. 1 shows the configuration of the output stage 11 of the common electrode driving circuit according to this embodiment.
- the output stage 11 includes a first output stage (sub output stage, final sub output stage) 11a, a first switch SWa, a second output stage (sub output stage, initial sub output stage) 11b, and a second switch SWb. ing.
- Each of the first output stage 11a and the second output stage 11b is composed of output transistors Tp and Tn, as in FIG.
- the output transistor Tp of the second output stage 11b has a higher ON resistance than the output transistor Tp of the first output stage 11a, and the output transistor Tn of the second output stage 11b is more ON than the output transistor Tn of the first output stage 11a.
- the resistance is set large. Increasing the ON resistance can be realized by reducing the channel width W of the transistor or increasing the channel length L.
- the output impedance of the second output stage 11b is larger than the output impedance of the first output stage 11a. That is, the second output stage 11b has a smaller load driving capability than the first output stage 11a.
- Both the output of the first output stage 11 a and the output of the second output stage 11 b are connected to the COM output terminal 102. Both the first output stage 11a and the second output stage 11b output a voltage level V1 that is a positive common electrode potential Vcom via an output transistor Tp, and a negative common electrode potential via an output transistor Tn. A voltage level V2 (V2 ⁇ V1) which is Vcom is output.
- the first switch SWa is connected in series to the input side of the first output stage 11a with respect to the first output stage 11a, and ON / OFF of the input of the common polarity inversion signal to the first output stage 11a according to the control signal s1.
- the second switch SWb is connected in series to the input side of the second output stage 11b with respect to the second output stage 11b, and ON / OFF of the input of the common polarity inversion signal to the second output stage 11b according to the control signal s1. Turn off.
- the terminal opposite to the input side of the first output stage 11a of the first switch SWa and the terminal opposite to the input side of the second output stage 11b of the second switch SWb both supply a common polarity inversion signal. Connected to the original.
- FIG. 2 shows operation waveforms of the output stage 11 having the above configuration.
- the output stage 11 supplies the common electrode potential Vcom to the COM output terminal 102 in accordance with the input common polarity inversion signal and the control signal s1.
- the common polarity inversion signal (not shown) is composed of a High period and a Low period each equal to one horizontal period, and one of the High period and the Low period has the positive polarity (voltage) of the common electrode potential Vcom.
- Level V1 is instructed, and the other period is instructed to make the common electrode potential Vcom negative (voltage level V2).
- the control signal s1 becomes a high level in the first period (partial period) t1 of each horizontal period in which the common electrode potential Vcom becomes positive, and becomes a low level in the remaining period (partial period) t2 of the horizontal period. It has a waveform and becomes a high level in the first period (partial period) t3 of each horizontal period in which the common electrode potential Vcom becomes negative, and at a low level in the remaining period (partial period) t4 of the horizontal period. Has a waveform.
- the first switch SWa is turned on when the control signal s1 is at the low level, and is turned off when the control signal s1 is at the high level.
- the second switch SWa is turned on when the control signal s1 is at a high level, and is turned off when the control signal s1 is at a low level.
- the second switch SWb is turned on and the first switch SWa is turned off in the periods t1 and t3, and the first switch SWa is turned on and the second switch SWb in the periods t2 and t4. Is turned off.
- the common electrode potential Vcom is supplied by the output from the second output stage 11b in the period (partial period including the start of the polarity reversal operation) t1 and t3, and from the first output stage 11a in the period t2 and t4.
- the common electrode potential Vcom is supplied by the output.
- each supply period of the common electrode potential of each polarity is divided into a plurality of partial periods.
- the time constant of the waveform change of the common electrode potential Vcom in the periods t1 and t3 is the common electrode in the periods t2 and t4. It is larger than the time constant of the waveform change of the potential Vcom. Therefore, when the positive common electrode potential Vcom is supplied, it slowly rises to the first potential level in the middle of the period t1, and then rises quickly in the period t2 to reach the voltage level V1, which is the final potential level.
- the fall of the positive common electrode potential Vcom is equal to the rise of the negative common electrode potential Vcom, and slowly falls to the second potential level in the middle of the period t3 (rises for the negative polarity). It falls rapidly in period t4 (rises for negative polarity) and reaches a voltage level V2 which is the final potential level.
- the falling of the negative common electrode potential Vcom is equal to the rising of the positive common electrode potential Vcom.
- the waveform of the common electrode potential Vcom is the waveform of the common electrode potential Vcom after the polarity inversion of the common electrode potential Vcom is started in each supply period of the common electrode potential Vcom of each polarity. Once reaching the potential halfway on the opposite polarity side of the final potential of the common electrode potential Vcom of each polarity, it rises toward the final potential at a higher rate of change than when reaching the middle potential. .
- the scanning signal Vg for turning on the TFT 14 of the picture element PIX is a pulse waveform that becomes a high level only in each of the periods t2 and t4. That is, the data writing period to the picture element PIX is set within each of the periods t2 and t4.
- FIG. 4 shows the configuration of the output stage 12 of the common electrode driving circuit according to this embodiment.
- the output stage 12 includes a first output stage (sub output stage, final sub output stage) 12a, a first switch SWd, a second output stage (sub output stage, initial sub output stage) 12b, and a second switch SWe. ing.
- Each of the first output stage 12a and the second output stage 12b is composed of output transistors Tp and Tn, as in FIG.
- the first output stage 12a outputs a voltage level V1 that is a positive common electrode potential Vcom via the output transistor Tp, and a voltage level V2 that is a negative common electrode potential Vcom via the output transistor Tn.
- the second output stage 12b outputs a voltage level V3 that is a positive common electrode potential Vcom via the output transistor Tp, and a voltage level that is a negative common electrode potential Vcom via the output transistor Tn.
- V4 is output.
- the voltage level V3 is closer to the voltage level V2 which is the opposite polarity than the voltage level V1
- the voltage level V4 is closer to the voltage level V1 which is the opposite polarity than the voltage level V2.
- Both the output of the first output stage 12 a and the output of the second output stage 12 b are connected to the COM output terminal 102.
- the first switch SWd is connected in series to the input side of the first output stage 12a with respect to the first output stage 12a, and ON / OFF of the input of the common polarity inversion signal to the first output stage 12a according to the control signal s2.
- the second switch SWe is connected in series to the input side of the second output stage 11b with respect to the second output stage 12b, and ON / OFF of the input of the common polarity inversion signal to the second output stage 12b according to the control signal s2. Turn off.
- the terminal opposite to the input side of the first output stage 12a of the first switch SWd and the terminal opposite to the input side of the second output stage 12b of the second switch SWe both supply a common polarity inversion signal. Connected to the original.
- FIG. 5 shows operation waveforms of the output stage 12 having the above configuration.
- the output stage 12 supplies the common electrode potential Vcom to the COM output terminal 102 in accordance with the input common polarity inversion signal and the control signal s2.
- the common polarity inversion signal (not shown) is composed of a High period and a Low period each equal to one horizontal period, and one of the High period and the Low period has the positive polarity (voltage) of the common electrode potential Vcom.
- Level V1 is instructed, and the other period is instructed to make the common electrode potential Vcom negative (voltage level V2).
- the control signal s2 becomes High level in the first period (partial period) t1 of each horizontal period in which the common electrode potential Vcom becomes positive, and becomes Low level in the remaining period (partial period) t2 of the horizontal period. It has a waveform and becomes a high level in the first period (partial period) t3 of each horizontal period in which the common electrode potential Vcom becomes negative, and at a low level in the remaining period (partial period) t4 of the horizontal period. Has a waveform.
- the first switch SWd is turned on when the control signal s2 is at the low level, and is turned off when the control signal s2 is at the high level.
- the second switch SWe is turned on when the control signal s2 is at a high level, and is turned off when the control signal s2 is at a low level.
- the second switch SWe is turned on and the first switch SWd is turned off in the periods t1 and t3, and the first switch SWd is turned on and the second switch SWe in the periods t2 and t4. Is turned off.
- the common electrode potential Vcom is supplied by the output from the second output stage 12b in the period (partial period including the start of the polarity reversal operation) t1 and t3, and from the first output stage 12a in the period t2 and t4.
- the common electrode potential Vcom is supplied by the output.
- each supply period of the common electrode potential of each polarity is divided into a plurality of partial periods.
- the time constant of the waveform change of the common electrode potential Vcom in the periods t1 and t3 is the common electrode in the periods t2 and t4.
- the final ultimate voltage possible is smaller than the period t2 ⁇ t4. Therefore, when the positive common electrode potential Vcom is supplied, the voltage level rises to the voltage level V3 in the period t1, and then reaches the voltage level V1, which is the final potential level, in the period t2.
- the fall of the positive common electrode potential Vcom is equal to the rise of the negative common electrode potential Vcom, falls to the voltage level V4 in the period t3 (rises for the negative polarity), and then reaches the final potential in the period t4.
- the falling of the negative common electrode potential Vcom is equal to the rising of the positive common electrode potential Vcom.
- the waveform of the common electrode potential Vcom is the waveform of the common electrode potential Vcom after the polarity inversion of the common electrode potential Vcom is started in each supply period of the common electrode potential Vcom of each polarity. Once reaching the potential halfway on the opposite polarity side of the final potential of the common electrode potential Vcom of each polarity, it rises toward the final potential at a higher rate of change than when reaching the middle potential. .
- the scanning signal Vg for turning on the TFT 14 of the picture element PIX is a pulse waveform that becomes a high level only in each of the periods t2 and t4. That is, the data writing period to the picture element PIX is set within each of the periods t2 and t4.
- FIG. 6 shows the configuration of the output stage 13 of the common electrode driving circuit according to this embodiment.
- the output stage 13 includes a first output stage (sub output stage, final sub output stage) 13a, a first switch SWf, a second output stage (sub output stage) 13b, a second switch SWg, and a third output stage (sub output stage). , Initial sub output stage) 13c, and a third switch SWh.
- Each of the first output stage 13a, the second output stage 13b, and the third output stage 13c is composed of output transistors Tp and Tn, as in FIG.
- the first output stage 13a outputs a voltage level V1 that is a positive common electrode potential Vcom via the output transistor Tp, and a voltage level V2 that is a negative common electrode potential Vcom via the output transistor Tn.
- the second output stage 13b outputs a voltage level V3 that is a positive common electrode potential Vcom via an output transistor Tp, and outputs a voltage level V4 that is a negative common electrode potential Vcom via an output transistor Tn.
- the third output stage 13c outputs a voltage level V5 that is a positive common electrode potential Vcom via the output transistor Tp, and outputs a voltage level V6 that is a negative common electrode potential Vcom via the output transistor Tn.
- the output of the first output stage 13a, the output of the second output stage 13b, and the output of the third output stage 13c are all connected to the COM output terminal 102.
- the first switch SWf is connected in series to the input side of the first output stage 13a with respect to the first output stage 13a, and ON / OFF of the input of the common polarity inversion signal to the first output stage 13a according to the control signal s3.
- the second switch SWg is connected in series to the input side of the second output stage 13b with respect to the second output stage 13b, and ON / OFF of the input of the common polarity inversion signal to the second output stage 13b according to the control signal s3. Turn off.
- the third switch SWh is connected in series to the input side of the third output stage 13c with respect to the third output stage 13c, and ON / OFF of the input of the common polarity inversion signal to the third output stage 13c according to the control signal s3. Turn off.
- the output transistor Tp of the second output stage 13b has a higher ON resistance than the output transistor Tp of the first output stage 13a, and the output transistor Tn of the second output stage 13b is more ON than the output transistor Tn of the first output stage 13a.
- the resistance is set large.
- the output transistor Tp of the third output stage 13c has a higher ON resistance than the output transistor Tp of the second output stage 13b, and the output transistor Tn of the third output stage 13c has a higher ON resistance than the output transistor Tn of the second output stage 13b. It is set large. Increasing the ON resistance can be realized by reducing the channel width W of the transistor or increasing the channel length L.
- the output impedance of the second output stage 13b is larger than the output impedance of the first output stage 13a
- the output impedance of the third output stage 13c is larger than the output impedance of the second output stage 13b. That is, the second output stage 13b has a smaller load driving capability than the first output stage 13a, and the third output stage 13c has a smaller load driving capability than the second output stage 13b.
- the output stage 13 is not limited to the above, and may generally include a first output stage to an nth output stage (n is an integer of 2 or more). Further, a plurality of the first output stage to the n-th output stage may have the same output impedance, that is, the same load driving capability. Further, a plurality of the first to n-th output stages may supply the common electrode potential Vcom at the same time. In general, of the first output stage to the n-th output stage, the total load drive capacity that is the sum of the load drive capacity of one or more output stages that supply the final ultimate potential of the common electrode potential Vcom of each polarity.
- the polarity inversion operation of the common electrode potential may be started by one or more output stages that reduce the overall load driving capability.
- the magnitude relationship of the load driving capability in the period between the partial period including the start of the polarity inversion operation and the partial period for supplying the final potential is not particularly defined.
- the total load driving capability of each output stage can be expressed as the sum of currents that each output stage can output to the same load.
- the second output stage 13b has a smaller load drive capability than the first output stage 13a
- the third output stage 13c has a load drive capability than the second output stage 13b.
- Ability is reduced.
- the output stage 13 is not limited to the above, and may generally include a first output stage to an nth output stage (n is an integer of 2 or more). Further, a plurality of the first output stage to the n-th output stage may have the same power supply voltage of the common electrode potential, that is, the same load driving capability. A plurality of the first to nth output stages having the same power supply voltage may supply the common electrode potential Vcom at the same time. In general, of the first output stage to the n-th output stage, the total load drive capacity that is the sum of the load drive capacity of one or more output stages that supply the final ultimate potential of the common electrode potential Vcom of each polarity.
- the polarity inversion operation of the common electrode potential may be started by one or more output stages that reduce the overall load driving capability.
- the magnitude relationship of the load driving capability in the period between the period including the start of the polarity inversion operation and the period for supplying the final ultimate potential is not particularly defined.
- the total load driving capability of each output stage can be expressed as the sum of currents that each output stage can output to the same load.
- FIG. 7 shows the configuration of the output stage 14 of the common electrode driving circuit according to this embodiment.
- the output stage 14 includes a first output stage (sub output stage, final sub output stage) 14a, a first switch SWi, a second output stage (sub output stage, initial sub output stage) 14b, and a second switch SWj. ing.
- the second output stage 14b includes a voltage dividing circuit in which the resistor R1 and the resistor R2 are connected in series so as to divide the voltage level V1 and the voltage level V2 (V2 ⁇ V1). A voltage level V1 is applied to one end of the resistor R1, and a voltage level V2 is applied to one end of the resistor R2.
- the first output stage 14a is composed of output transistors Tp and Tn as in FIG.
- the ON resistance of the output transistor Tp of the first output stage 14a is smaller than the resistance value of the resistor R1 of the second output stage 14b, and the ON resistance of the output transistor Tn of the first output stage 14a is the second output stage 14b. Is set smaller than the resistance value of the resistor R2.
- the ON resistance can be realized by adjusting the channel width W and channel length L of the transistor.
- the output impedance of the second output stage 14b is larger than the output impedance of the first output stage 14a. That is, the second output stage 14b has a smaller load driving capability than the first output stage 14a.
- the output of the first output stage 14 a is connected to the COM output terminal 102.
- the first output stage 14a outputs a voltage level V1 that is a positive common electrode potential Vcom via the output transistor Tp, and a voltage level V2 (V2 ⁇ V) that is a negative common electrode potential Vcom via the output transistor Tn. V1) is output.
- the first switch SWi is connected in series to the input side of the first output stage 14a with respect to the first output stage 14a, and ON / OFF of the input of the common polarity inversion signal to the first output stage 14a according to the control signal s4. Turn off.
- the second switch SWj is connected to the output side of the second output stage 14b (the connection point between the resistor R1 and the resistor R2) with respect to the second output stage 14b, and is connected to the second output stage 14b according to the control signal s4. Turns on / off the input of the common polarity inversion signal.
- the terminal opposite to the input side of the first output stage 14a of the first switch SWi is connected to the supply source of the common polarity inversion signal.
- FIG. 8 shows operation waveforms of the output stage 14 configured as described above.
- the output stage 14 supplies the common electrode potential Vcom to the COM output terminal 102 in accordance with the input common polarity inversion signal and the control signal s4.
- the common polarity inversion signal (not shown) is composed of a High period and a Low period each equal to one horizontal period, and one of the High period and the Low period has the positive polarity (voltage) of the common electrode potential Vcom.
- Level V1 is instructed, and the other period is instructed to make the common electrode potential Vcom negative (voltage level V2).
- the control signal s4 becomes High level in the first period (partial period) t1 of each horizontal period in which the common electrode potential Vcom becomes positive, and becomes Low level in the remaining period (partial period) t2 of the horizontal period. It has a waveform and becomes a high level in the first period (partial period) t3 of each horizontal period in which the common electrode potential Vcom becomes negative, and at a low level in the remaining period (partial period) t4 of the horizontal period. Has a waveform.
- the first switch SWa is turned on when the control signal s1 is at the low level, and is turned off when the control signal s1 is at the high level.
- the second switch SWa is turned on when the control signal s1 is at a high level, and is turned off when the control signal s1 is at a low level.
- the second switch SWj is turned on and the first switch SWi is turned off in the periods t1 and t3, and the first switch SWi is turned on and the second switch SWj in the periods t2 and t4. Is turned off.
- the common electrode potential Vcom is supplied by the output from the second output stage 14b in the periods t1 and t3, and the common electrode potential Vcom is supplied by the output from the first output stage 14a in the periods t2 and t4.
- each supply period of the common electrode potential of each polarity is divided into a plurality of partial periods.
- the time constant of the waveform change of the common electrode potential Vcom in the periods t1 and t3 is the common electrode in the periods t2 and t4. It is larger than the time constant of the waveform change of the potential Vcom. Therefore, when supplying the common electrode potential Vcom having the positive polarity, it slowly rises to the first potential level that is lower than (V1 ⁇ V2) ⁇ R2 / (R1 + R2) in the period t1, and then quickly in the period t2. It rises and reaches the voltage level V1, which is the final potential level.
- the fall of the positive common electrode potential Vcom is equal to the rise of the negative common electrode potential Vcom, and slowly falls to the second potential level in the middle of becoming (V1 ⁇ V2) ⁇ R2 / (R1 + R2) or more in the period t3. It falls (rises for negative polarity) and then falls rapidly (rises for negative polarity) in period t4 to reach the voltage level V2 which is the final potential level.
- the falling of the negative common electrode potential Vcom is equal to the rising of the positive common electrode potential Vcom.
- the waveform of the common electrode potential Vcom is the waveform of the common electrode potential Vcom after the polarity inversion of the common electrode potential Vcom is started in each supply period of the common electrode potential Vcom of each polarity. Once reaching the potential halfway on the opposite polarity side of the final potential of the common electrode potential Vcom of each polarity, it rises toward the final potential at a higher rate of change than when reaching the middle potential. .
- the scanning signal Vg for turning on the TFT 14 of the picture element PIX is a pulse waveform that becomes a high level only in each of the periods t2 and t4. That is, the data writing period to the picture element PIX is set within each of the periods t2 and t4.
- the display device of the present invention is a display device that performs common inversion driving, and the output stage of the common electrode driving circuit has a plurality of outputs each capable of outputting a voltage to the common electrode.
- a sub-output stage, and each supply period of the common electrode potential of each polarity is divided into a plurality of partial periods, and each of the partial periods includes one or more sub-output stages selected for each of the partial periods.
- the overall load driving capability of the final sub-output stage consisting of one or more sub-output stages selected during the partial period in which a voltage is supplied to the common electrode and the final potential of the common electrode potential of each polarity is supplied
- the overall load driving capability of the initial sub-output stage composed of one or more sub-output stages selected in the partial period including the start of the polarity inversion operation of the common electrode potential is smaller.
- the start timing of each period of the partial period included in the transition time in which the polarity of the common electrode potential is reversed including the partial period in which the voltage is output by the initial sub-output stage as the current flowing in the common electrode
- the display device of the present invention is characterized in that the overall output impedance of the initial sub-output stage is larger than the overall output impedance of the final sub-output stage.
- the display device of the present invention is characterized in that the initial sub-output stage and the final sub-output stage include a sub-output stage that outputs a voltage by a push-pull operation using a transistor. It is said.
- the output impedance can be set by the ON resistance of the transistor.
- the display device of the present invention is configured such that, in each supply period of the common electrode potential of each polarity, the power supply voltage of the voltage output by the initial sub-output stage is on the opposite polarity side to the final ultimate potential. It is characterized by being close to.
- the initial sub output stage includes a sub output stage that outputs a voltage divided by a resistor, and the final sub output stage uses a transistor. And a sub output stage for outputting a voltage by the push-pull operation.
- a display device driving method is a display device driving method that performs common inversion driving, and each of the plurality of sub-output stages is capable of outputting a voltage to a common electrode. And each supply period of the common electrode potential of each polarity is divided into a plurality of partial periods, and each partial period is provided in the output stage of the common electrode driving circuit selected for each partial period.
- the overall load drive capability of the initial sub-output stage composed of one or more sub-output stages selected in the partial period including the start of the polarity inversion operation of the common electrode potential is smaller than the overall load drive capability of It is characterized in that.
- the start timing of each period of the partial period included in the transition time in which the polarity of the common electrode potential is reversed including the partial period in which the voltage is output by the initial sub-output stage as the current flowing in the common electrode
- the display device driving method of the present invention is characterized in that the overall output impedance of the initial sub-output stage is larger than the overall output impedance of the final sub-output stage.
- the initial sub-output stage and the final sub-output stage include a sub-output stage that outputs a voltage by a push-pull operation using a transistor. It is characterized by that.
- the output impedance can be set by the ON resistance of the transistor.
- the display device driving method of the present invention is configured such that, in each supply period of the common electrode potential of each polarity, the power supply voltage of the voltage output by the initial sub-output stage is higher than the final ultimate potential. It is characterized by being close to the opposite polarity side.
- the initial sub-output stage includes a sub-output stage that outputs a voltage divided by a resistor
- the final sub-output stage includes: A sub-output stage that outputs a voltage by push-pull operation using a transistor is included.
- the display device of the present invention is a display device that performs common inversion driving, and in each supply period of the common electrode potential of each polarity, after the polarity inversion of the common electrode potential is started,
- the waveform of the common electrode potential once reaches the potential on the opposite polarity side of the final potential of the common electrode potential of each polarity, and then reaches the final potential at a rate of change larger than when the potential reaches the middle potential. It is characterized by rising toward the potential.
- the display device driving method of the present invention is a display device driving method that performs common inversion driving, wherein the polarity inversion of the common electrode potential is performed in each supply period of the common electrode potential of each polarity.
- the present invention can be suitably used for various display devices including a liquid crystal display device.
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Abstract
Description
高電位側の電圧レベルV1と低電位側の電圧レベルV2とを1水平期間ごとに切り替えて、COM出力端子102から出力する。コモン電極103はCOM出力端子102に接続されており、絵素電極104との間に液晶層を挟んで液晶容量CLを形成するが、コモン電極103自身も容量を有している。従って、コモン反転駆動は、コモン電極駆動回路がこれらの容量を交互に正負に充電する動作となる。
2 表示部
11~14 出力段
11a、12a、13a、14a
第1出力段(サブ出力段、最終サブ出力段)
11b、12b、14b
第2出力段(サブ出力段、初期サブ出力段)
13b 第2出力段(サブ出力段)
13c 第3出力段(サブ出力段、初期サブ出力段)
103 コモン電極
t1~t4 期間(部分期間)
Vcom コモン電極電位
Claims (12)
- コモン反転駆動を行う表示装置であって、
コモン電極駆動回路の出力段は、
それぞれがコモン電極に電圧を出力することが可能な複数のサブ出力段を備えており、
各極性のコモン電極電位の各供給期間を複数の部分期間に分割して、各上記部分期間には上記部分期間ごとに選択された1つ以上のサブ出力段によって、コモン電極に電圧を供給し、
各極性のコモン電極電位の最終到達電位を供給する上記部分期間に選択される1つ以上のサブ出力段からなる最終サブ出力段の全体の負荷駆動能力よりも、コモン電極電位の極性反転動作の開始を含む上記部分期間に選択される1つ以上のサブ出力段からなる初期サブ出力段の全体の負荷駆動能力のほうが小さいことを特徴とする表示装置。 - 上記初期サブ出力段の全体の出力インピーダンスは、上記最終サブ出力段の全体の出力インピーダンスよりも大きいことを特徴とする請求項1に記載の表示装置。
- 上記初期サブ出力段および上記最終サブ出力段は、トランジスタを用いたプッシュプル動作により電圧を出力するサブ出力段を含んでいることを特徴とする請求項2に記載の表示装置。
- 各極性のコモン電極電位の各供給期間において、上記初期サブ出力段が出力する電圧の電源電圧は、上記最終到達電位よりも反対極性側に近いことを特徴とする請求項1に記載の表示装置。
- 上記初期サブ出力段は、抵抗により分圧された電圧を出力するサブ出力段を含んでおり、
上記最終サブ出力段は、トランジスタを用いたプッシュプル動作により電圧を出力するサブ出力段を含んでいることを特徴とする請求項2に記載の表示装置。 - コモン反転駆動を行う表示装置の駆動方法であって、
それぞれがコモン電極に電圧を出力することが可能な複数のサブ出力段を備えており、
各極性のコモン電極電位の各供給期間を複数の部分期間に分割して、各上記部分期間には上記部分期間ごとに選択された、コモン電極駆動回路の出力段に備えられる1つ以上のサブ出力段によって、コモン電極に電圧を供給し、
各極性のコモン電極電位の最終到達電位を供給する上記部分期間に選択される1つ以上のサブ出力段からなる最終サブ出力段の全体の負荷駆動能力よりも、コモン電極電位の極性反転動作の開始を含む上記部分期間に選択される1つ以上のサブ出力段からなる初期サブ出力段の全体の負荷駆動能力のほうが小さいことを特徴とする表示装置の駆動方法。 - 上記初期サブ出力段の全体の出力インピーダンスは、上記最終サブ出力段の全体の出力インピーダンスよりも大きいことを特徴とする請求項6に記載の表示装置の駆動方法。
- 上記初期サブ出力段および上記最終サブ出力段は、トランジスタを用いたプッシュプル動作により電圧を出力するサブ出力段を含んでいることを特徴とする請求項7に記載の表示装置の駆動方法。
- 各極性のコモン電極電位の各供給期間において、上記初期サブ出力段が出力する電圧の電源電圧は、上記最終到達電位よりも反対極性側に近いことを特徴とする請求項6に記載の表示装置の駆動方法。
- 上記初期サブ出力段は、抵抗により分圧された電圧を出力するサブ出力段を含んでおり、
上記最終サブ出力段は、トランジスタを用いたプッシュプル動作により電圧を出力するサブ出力段を含んでいることを特徴とする請求項7に記載の表示装置の駆動方法。 - コモン反転駆動を行う表示装置であって、
各極性のコモン電極電位の各供給期間において、コモン電極電位の極性反転が開始されてから、コモン電極電位の波形が、各極性のコモン電極電位の最終到達電位よりも反対極性側の途中の電位に一旦到達してから、上記途中の電位への到達時よりも大きい変化率で上記最終到達電位へ向かって立ち上がることを特徴とする表示装置。 - コモン反転駆動を行う表示装置の駆動方法であって、
各極性のコモン電極電位の各供給期間において、コモン電極電位の極性反転が開始されてから、コモン電極電位を、各極性のコモン電極電位の最終到達電位よりも反対極性側の途中の電位に一旦到達してから、上記途中の電位への到達時よりも大きい変化率で上記最終到達電位へ向かって立ち上がる波形とすることを特徴とする表示装置の駆動方法。
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BRPI0924750A BRPI0924750A2 (pt) | 2009-02-18 | 2009-10-27 | dispositivo de exibição e método para o acionamento do mesmo |
CN2009801566911A CN102318000A (zh) | 2009-02-18 | 2009-10-27 | 显示装置和显示装置的驱动方法 |
US13/138,427 US20110298773A1 (en) | 2009-02-18 | 2009-10-27 | Display device and method for driving same |
RU2011135308/08A RU2486607C2 (ru) | 2009-02-18 | 2009-10-27 | Дисплейное устройство и способ управления им |
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