WO2010088822A1 - 发送、接收时钟的方法及传递时钟的装置 - Google Patents
发送、接收时钟的方法及传递时钟的装置 Download PDFInfo
- Publication number
- WO2010088822A1 WO2010088822A1 PCT/CN2009/074171 CN2009074171W WO2010088822A1 WO 2010088822 A1 WO2010088822 A1 WO 2010088822A1 CN 2009074171 W CN2009074171 W CN 2009074171W WO 2010088822 A1 WO2010088822 A1 WO 2010088822A1
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- WIPO (PCT)
- Prior art keywords
- clock
- receiving
- transmitting
- encoded
- module
- Prior art date
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W56/00—Synchronisation arrangements
- H04W56/001—Synchronization between nodes
- H04W56/0015—Synchronization between nodes one node acting as a reference for the others
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
Definitions
- the present invention relates to the field of communications, and more particularly to a method for transmitting and receiving a clock between boards in a multimode base station and a device for transmitting a clock.
- the clock board in the base station is used to extract and recover the clock from the reference clock, and then generate a new clock according to the requirements of the system and distribute it to other boards.
- the clock that needs to be transmitted generally includes two clock signals, the first clock signal is used to pass a certain clock frequency, and the second clock signal is used to transmit a timing signal.
- a base station only needs to carry a standard service.
- a CDMA base station is only used in a CDMA system, so the clock requirement is also single, and the clock board only needs to distribute a single clock frequency according to the requirements of the system.
- the timing signal can be.
- the same base station architecture requires compatibility with multiple standards of services, such as CDMA/WCDMA/GSM.
- Different systems have different requirements for the first clock signal and the second clock signal, so the multimode base station needs to consider how to transmit multiple clocks.
- the first clock and the second clock required by the CDMA system take a pair of lines
- the first clock and the second clock required by the WCDMA system go to another pair of lines, etc.
- the user board selects according to their own needs. Enter the clock.
- This method not only increases the backplane routing, but also brings more work to the PCB design, which is not conducive to system expansion.
- the technical problem to be solved by the present invention is to provide a method for transmitting and receiving a clock and a device for transmitting a clock, which can realize transmitting a plurality of clock signals on a pair of interconnect lines.
- the present invention provides a method for transmitting a clock, comprising: a transmitting end selecting a first clock frequency, encoding a second clock for each system, and using the pair of interconnect lines The first clock frequency and the encoded second clock are sent to the respective receiving ends.
- the transmitting end calculates a common divisor of each second clock cycle before starting encoding, and determines a delay T1 of the encoding phase, a delay T2 of the sending phase, and a delay T3 of the decoding phase;
- the transmitting end continuously transmits the first clock frequency through a first clock transmission line
- the transmitting end encodes each second clock and codes the encoded code words into a sequence according to a predetermined rule, and then adds a protection bit, a start bit, and a stop bit to form a fixed length data frame, and then one by one.
- the bit is transmitted to the receiving end through the second clock transmission line.
- the present invention also provides a method for receiving a clock, comprising: each receiving end receiving the first clock frequency from a first clock transmission line, counting locally with the first clock frequency, and receiving the encoded code from a second clock transmission line The second clock and parses the encoded second clock.
- the second clock required by the receiving end is generated by the first clock count.
- the encoded second clock is encapsulated into a data frame, and the data frame includes a protection bit, and after receiving the data frame, each receiving end determines whether the protection bit is correct, and if correct, the code of the corresponding part The word is decoded, otherwise the data frame is discarded.
- the present invention also provides an apparatus for transmitting a clock, the apparatus comprising a transmitting end, a first clock transmission line, and a second clock transmission line;
- the transmitting end includes a control module, one or more clock encoding modules, and a sending module; the control module is configured to select a first clock frequency and send the same to the sending module; each of the multiple clock encoding modules Corresponding to the second clock of the system, the clock encoding module is configured to encode the second clock of the corresponding system, and send the encoded codeword to the sending module; the sending module is configured to transmit the line through the first clock Sending the first clock frequency, And transmitting the encoded second clock through the second clock transmission line.
- control module is further configured to calculate a common divisor of each second clock cycle, and send the common divisor to each clock encoding module;
- the clock encoding module is configured to: after receiving the start coding flag, encode the corresponding second clock by using the common number.
- the sending module is further configured to: after receiving the codewords sent by the clock encoding modules, group the codewords into a sequence, and add a protection bit, a start bit, and a stop bit to form a fixed length data frame. After receiving the first clock frequency, the sending module continuously sends the first clock frequency through the first clock transmission line, and receives the flag for starting transmission to send the data frame through the second clock transmission line.
- the present invention also provides an apparatus for receiving a clock, including one or more receiving ends; the receiving end includes a decoding module and a clock phase locked loop;
- the clock phase locked loop is configured to receive a first clock frequency from a first clock transmission line
- the decoding module is configured to receive a data frame from the second clock transmission line and parse the required second clock according to the data frame.
- the clock phase locked loop is further configured to: when the received first clock frequency is not the first clock required by the receiving end, recover the first required by the receiving end according to the first clock frequency a clock.
- the decoding module is further configured to: after receiving the data frame, determine whether the protection bit is correct, and if yes, decode the corresponding codeword, otherwise discard the data frame, and use the first The clock is counted locally, producing the second clock required by the receiver.
- the invention provides a method for transmitting and receiving a clock and a device for transmitting a clock, which encodes and framing a plurality of clocks at a transmitting end according to the method of the present invention, thereby realizing transmission of multiple clocks on a pair of interconnected lines. Signals, the board at the receiving end can accurately recover the clock it needs according to the corresponding decoding rules.
- FIG. 1 is a schematic structural view of an apparatus for transmitting a clock according to the present invention
- FIG. 3 is a flow chart of a method for transmitting a clock according to an example of the present invention.
- FIG. 5 is a schematic structural diagram of a data frame after encoding according to an embodiment of the present invention.
- the invention provides a method for transmitting and receiving a clock and a device for transmitting a clock, which encodes and framing a plurality of clocks at a transmitting end according to the method of the present invention, thereby realizing transmission of a plurality of clocks on a pair of interconnected lines, and a single receiving end According to the corresponding decoding rules, the board can accurately recover the clock it needs.
- the clock board In a multimode base station, the clock board outputs a high-stability reference frequency to the user board by locking the reference input clock, which is hereinafter referred to as the first clock; and the user board is required to provide a high-accuracy clock reference, hereinafter referred to as the second clock.
- Figure 1 illustrates the connection between the multimode base station clock board (the transmitter in the figure) and each user board (the receiver in the figure).
- the clock board passes the first clock through a pair of interconnects on the backplane.
- the second clock is delivered to each receiving end.
- the second clock needs to be encoded. The following is an example to illustrate the way the multi-mode base station clock code is transmitted.
- the embodiment provides a device for transmitting a clock, as shown in FIG. 1 , including a transmitting end, a receiving end, a first clock transmission line, and a second clock transmission line;
- the transmitting end includes a control module, one or more clock encoding modules, and a sending module.
- the control module is configured to select a suitable first clock frequency, and send the first clock frequency to the sending module, where the first clock frequency must be To meet the requirements of the various frequency clocks required by the receiving board, in addition, you need to consider the timing requirements of the receiving end device, the first clock.
- the frequency should not be too high.
- the control module is further configured to calculate a common divisor of each second clock cycle, and send the common divisor to each clock encoding module; and is also used to determine a delay T1 of the encoding phase, a delay T2 of the transmitting phase, and a delay of the decoding phase. T3;
- the clock encoding module is configured to encode the second clock of the system according to the received common divisor, and the encoding rule is selected according to the requirements of the standard. The present invention does not limit this.
- the clock encoding module is further configured to send the encoded codeword to the sending module.
- the sending module is configured to continuously send the first clock frequency through the first clock transmission line after receiving the first clock frequency, and may also be used to receive a codeword sent by each clock encoding module and then form a sequence according to a predetermined rule.
- the predetermined rule may be, but is not limited to, arranging the code words in a sequence as shown in FIG. 5, and the order of arrangement is not limited; the sending module may also be used to add a protection bit to the sequence, which may be, but is not limited to, parity.
- the check code, and the start bit and the stop bit are combined to form a data frame, and are used to transmit the data frame through the second clock transmission line after receiving the start transmission flag.
- the first clock signal is a higher frequency clock signal
- the second clock signal is a lower frequency timing signal
- the second clock signal period includes an integer number of first clock signal periods.
- the receiving end includes a decoding module and a clock phase locked loop
- the clock phase-locked loop is configured to receive the first clock frequency from the first clock transmission line. If the first clock frequency is the clock frequency required by itself, the first clock frequency can be directly used, otherwise the clock phase-locked loop is Recovering the clock frequency required by the first clock frequency according to the first clock frequency; the decoding module is configured to receive the data frame from the second clock transmission line, and decode the codeword corresponding to the standard according to the decoding rule corresponding to the encoding rule; Determining whether the protection bit is correct when the received data frame has a protection bit, if it is correct, decoding the codeword of the corresponding part (the corresponding part refers to the coding of the second clock of the standard), otherwise discarding the data frame; The decoding module is further configured to: when the second clock cannot be correctly parsed, the first clock that is recovered is locally counted, and the second clock required by the receiving end is generated, and when the second clock is correctly parsed, the local counting is generated. The second clock is synchronized to the parsed second clock.
- the embodiment provides a method for transmitting a clock. As shown in FIG. 3, the method includes the following steps: Step 301a: The transmitting end selects a suitable first clock frequency for transmission, and then performs step 304a;
- the receiving board may be a different board, the required clock frequency is different. Therefore, the first clock frequency must be selected to meet the requirements of the various frequency clocks required by the board at the receiving end. In addition, it is also necessary to consider the timing requirements of the receiving device. The first clock frequency cannot be too ⁇ 3 ⁇ 4.
- Step 301b The transmitting end calculates the common divisor of each second clock cycle to be delivered, and then performs step 302;
- the CDMA system requires a timing signal to be transmitted in a period of 2 seconds.
- the GSM system requires a timing signal to be transmitted in a period of 60 ms.
- the WCDMA system requires a timing signal to be transmitted in a period of 10 ms. Then 10 ms is a common divisor of each timing signal period, and 10 ms can be selected.
- the encoded signal is transmitted periodically.
- the first clock count can be used to generate a timing signal in a common-count period.
- Step 302 Accurately calculate the delay of each phase, including the delay T1 of the coding phase, the delay of the transmission phase ⁇ 2, and the delay of the decoding phase ⁇ 3;
- Step 303 The transmitting end starts to independently encode the required encoding of the clock according to the foregoing common number, and the codewords of the encoding modules are arranged according to certain rules according to a certain rule.
- the sequence if it can be arranged in a sequence as shown in FIG. 5, is not limited in the order of arrangement, and then a protection bit can be added after the sequence, and the protection bit can be, but is not limited to, a parity code, and finally added
- Each coding module can select an encoding rule according to the needs of the system. In this step, when the coding clock period of the coding module coincides with the periodic timing signal of the corresponding system, the effective coding is output, otherwise the invalid coding is output.
- the composed data frame length is fixed.
- Step 304a The transmitting end continuously transmits the first clock frequency through the first clock transmission line.
- Step 305a Each receiving end receives the first clock frequency from the first clock transmission line. If the first clock frequency is the clock frequency required by itself, the first clock frequency can be directly used, otherwise the clock phase locked loop is used to recover. Outputting the clock frequency required by itself; then counting the local clock with the first clock to obtain a timing signal synchronized with the second clock, and the timing signal is also generated periodically;
- Step 305b Each receiving end further receives a data frame composed of the encoded second clock from the second clock transmission line, and decodes the codeword corresponding to the data frame according to the decoding rule corresponding to the coding rule, and parses the required first The two clocks, the corresponding part of the code word refers to the part corresponding to the receiving end system.
- each receiving end After receiving the data frame, each receiving end first determines whether the protection bit is correct, and if yes, decodes the codeword of the corresponding part, otherwise discards the data frame. If the receiving end correctly parses out the second clock, the timing signal obtained by counting the first clock is synchronized with the second clock that is parsed. If the receiving end does not receive the data frame for a period of time or determines that the codeword received by the receiving end has When the second clock is not parsed from the error, the timing signal is used instead of the second clock to be distributed to other modules.
- the first clock frequency selected in this embodiment is 61.44 MHz, which is a relatively common clock frequency transmitted by the optical module, and the receiving end can lock out the clock frequency required by the receiving terminal, such as required by the CDMA system. 39.3216MHz, 13MHz required by the GSM system.
- a multimode base station is designed to be compatible with CDMA, WCDMA, GSM, TD-SCDMA,
- CDMA requires transmission of a PP2S pulse with a period of 2 seconds, which is aligned with GPS time
- WCDMA requires transmission to generate a continuous frame synchronization signal with a period of 10 ms
- GSM requires transmission with a period of 60 ms.
- a continuous frame synchronization signal is generated
- TD-SCDMA also requires transmission to generate a continuous frame synchronization signal with a period of 10 ms
- WIMAX requires a PP1S pulse with a transmission period of 1 second, which is aligned with the GPS time.
- Step 1 Calculate the greatest common divisor of each second clock. Obviously, for this base station, the greatest common divisor of the second clock is 10 ms.
- Step 2 Generate a pulse signal with a period of 10ms using the first clock count, count and generate a pulse signal with a period of 2s, count and generate a pulse signal with a period of 60ms, and generate a pulse signal with a period of Is, each pulse signal. Aligned with the 10ms pulse signal.
- Step 3 Accurately calculate the delay of the coding phase Tl, the delay of the transmission phase ⁇ 2 and the delay of the decoding phase ⁇ 3, the first clock samples to the 10ms pulse signal, and the coding modules of each system start to encode independently.
- the CDMA coding module samples a 10ms pulse and a PP2S pulse at the same time, a codeword A is generated, and if only a 10ms pulse is generated, another code B is generated (ie, for the CDMA receiver, an invalid code is generated).
- GSM encoding module if you sample to 10ms pulse and 60ms pulse at the same time, add 13 to the frame number. If you only sample to 10ms pulse, keep the frame number unchanged. Other coding modules also follow the respective 10ms pulse. Rule coding.
- the CPU when the coding module is started, the CPU notifies the current time information of the coding module, and the coding module calculates a value based on this information, and then adds 100 to this value every 10 ms. For example, when the WCDMA module is started, the initial value is 0, and then 1 is added every 10ms.
- the first clock is transmitted continuously, and the second clock is transmitted every 10 ms.
- 5 invalid codes have no effect on the receiving end, which can be understood as direct discarding.
- Step 4 Arrange the code words of each coding module into a sequence according to a certain rule, and add some protection bits to the code words of the entire sequence, such as adding a parity check code.
- Step 5 Send the code words with the protection bits one by one to the interconnect on the backplane.
- the transmit module is controlled by the first clock, and each bit is sent at the same time.
- Step 6 At each receiving end, a decoding module decodes the received codeword according to the corresponding rule, and parses out the second clock required by itself.
- Step 7 The decoding module of each receiving end has a hold function, that is, the code word is not received for a period of time. Or when the received codeword is wrong, the decoding module can count locally with the first clock and continue to output the second clock required by the receiving end.
- the second clock generated by the local counting is synchronized with the parsed second clock.
- Step 8 The clock in step 2 needs to be generated with respect to the reference advance time T to ensure that the second clock recovered by the receiving end is aligned with the reference clock.
- a in Figure 2 represents the PP2S pulse required for CDMA
- B represents the 60ms pulse required for GSM
- C represents the 10ms pulse required for WCDMA
- D represents the greatest common divisor of the three clocks
- 10ms pulse represents the coded The second clock changes every 10ms.
- a in Fig. 4 denotes a first clock, and the previous pulse of the B signal indicates an indication signal to start encoding, and the latter pulse is aligned with the reference signal.
- the meanings of T, Tl, T2, T3 are as described above.
- C denotes the recovered signal in the receiving end and is aligned with the reference signal.
- the clocks required by various base stations can be transmitted on a pair of interconnect lines, and the receiving end can accurately recover the clocks required by itself. It reduces the interconnection on the backplane, increases flexibility, and avoids inaccurate clocks recovered from the receiver.
- the method for transmitting and receiving a clock and the method for transmitting a clock provided by the present invention encode and framing a plurality of clocks at a transmitting end, thereby transmitting a clock required by various base stations on a pair of interconnect lines.
- the receiving end can accurately recover the clock it needs. It reduces the interconnection on the backplane, increases flexibility, and avoids inaccurate clocks recovered from the receiver.
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- Synchronisation In Digital Transmission Systems (AREA)
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Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
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RU2011135320/07A RU2491785C2 (ru) | 2009-02-04 | 2009-09-24 | Способ передачи и приема тактового сигнала и устройство для передачи тактового сигнала |
US13/146,770 US20110286400A1 (en) | 2009-02-04 | 2009-09-24 | Method for sending and receiving clock, apparatus for transmitting clock |
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CN200910005147.9A CN101478385B (zh) | 2009-02-04 | 2009-02-04 | 发送、传递时钟的方法及传递时钟的装置 |
CN200910005147.9 | 2009-02-04 |
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WO2010088822A1 true WO2010088822A1 (zh) | 2010-08-12 |
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PCT/CN2009/074171 WO2010088822A1 (zh) | 2009-02-04 | 2009-09-24 | 发送、接收时钟的方法及传递时钟的装置 |
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US (1) | US20110286400A1 (zh) |
CN (1) | CN101478385B (zh) |
RU (1) | RU2491785C2 (zh) |
WO (1) | WO2010088822A1 (zh) |
Families Citing this family (5)
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CN101478385B (zh) * | 2009-02-04 | 2012-09-26 | 中兴通讯股份有限公司 | 发送、传递时钟的方法及传递时钟的装置 |
US20150009834A1 (en) * | 2013-07-08 | 2015-01-08 | Qualcomm Incorporated | Generation of timing pulses based on acquired synchronization |
CN103684736A (zh) * | 2013-11-21 | 2014-03-26 | 国网上海市电力公司 | 一种高速通信中时钟同步的方法 |
CN104978842B (zh) * | 2015-06-10 | 2018-03-06 | 烟台东方威思顿电气有限公司 | 一种低压集中器时钟自我修复的方法 |
CN106998584B (zh) * | 2016-01-25 | 2020-05-26 | 大唐移动通信设备有限公司 | 一种信号传输方法及装置、基站 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
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CN1768540A (zh) * | 2003-03-31 | 2006-05-03 | 诺基亚公司 | 在基站分发帧同步信息的设备和方法 |
CN101047428A (zh) * | 2006-05-26 | 2007-10-03 | 华为技术有限公司 | 支持多模基站时钟同步信号传送的装置和方法 |
CN101188817A (zh) * | 2006-11-15 | 2008-05-28 | 华为技术有限公司 | 多制式基站及其信号收发方法和无线通信网络 |
CN101478385A (zh) * | 2009-02-04 | 2009-07-08 | 中兴通讯股份有限公司 | 发送、接收时钟的方法及传递时钟的装置 |
Family Cites Families (1)
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DE19849458A1 (de) * | 1998-10-28 | 2000-05-04 | Philips Corp Intellectual Pty | Drahtloses Netzwerk mit einer Taktsynchronisation |
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2009
- 2009-02-04 CN CN200910005147.9A patent/CN101478385B/zh active Active
- 2009-09-24 US US13/146,770 patent/US20110286400A1/en not_active Abandoned
- 2009-09-24 WO PCT/CN2009/074171 patent/WO2010088822A1/zh active Application Filing
- 2009-09-24 RU RU2011135320/07A patent/RU2491785C2/ru active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1768540A (zh) * | 2003-03-31 | 2006-05-03 | 诺基亚公司 | 在基站分发帧同步信息的设备和方法 |
CN101047428A (zh) * | 2006-05-26 | 2007-10-03 | 华为技术有限公司 | 支持多模基站时钟同步信号传送的装置和方法 |
CN101188817A (zh) * | 2006-11-15 | 2008-05-28 | 华为技术有限公司 | 多制式基站及其信号收发方法和无线通信网络 |
CN101478385A (zh) * | 2009-02-04 | 2009-07-08 | 中兴通讯股份有限公司 | 发送、接收时钟的方法及传递时钟的装置 |
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Publication number | Publication date |
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CN101478385B (zh) | 2012-09-26 |
RU2491785C2 (ru) | 2013-08-27 |
RU2011135320A (ru) | 2013-03-10 |
CN101478385A (zh) | 2009-07-08 |
US20110286400A1 (en) | 2011-11-24 |
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