WO2010088822A1 - 发送、接收时钟的方法及传递时钟的装置 - Google Patents

发送、接收时钟的方法及传递时钟的装置 Download PDF

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Publication number
WO2010088822A1
WO2010088822A1 PCT/CN2009/074171 CN2009074171W WO2010088822A1 WO 2010088822 A1 WO2010088822 A1 WO 2010088822A1 CN 2009074171 W CN2009074171 W CN 2009074171W WO 2010088822 A1 WO2010088822 A1 WO 2010088822A1
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Prior art keywords
clock
receiving
transmitting
encoded
module
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PCT/CN2009/074171
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English (en)
French (fr)
Inventor
傅小明
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中兴通讯股份有限公司
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Application filed by 中兴通讯股份有限公司 filed Critical 中兴通讯股份有限公司
Priority to RU2011135320/07A priority Critical patent/RU2491785C2/ru
Priority to US13/146,770 priority patent/US20110286400A1/en
Publication of WO2010088822A1 publication Critical patent/WO2010088822A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W56/00—Synchronisation arrangements
    • H04W56/001—Synchronization between nodes
    • H04W56/0015—Synchronization between nodes one node acting as a reference for the others
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Definitions

  • the present invention relates to the field of communications, and more particularly to a method for transmitting and receiving a clock between boards in a multimode base station and a device for transmitting a clock.
  • the clock board in the base station is used to extract and recover the clock from the reference clock, and then generate a new clock according to the requirements of the system and distribute it to other boards.
  • the clock that needs to be transmitted generally includes two clock signals, the first clock signal is used to pass a certain clock frequency, and the second clock signal is used to transmit a timing signal.
  • a base station only needs to carry a standard service.
  • a CDMA base station is only used in a CDMA system, so the clock requirement is also single, and the clock board only needs to distribute a single clock frequency according to the requirements of the system.
  • the timing signal can be.
  • the same base station architecture requires compatibility with multiple standards of services, such as CDMA/WCDMA/GSM.
  • Different systems have different requirements for the first clock signal and the second clock signal, so the multimode base station needs to consider how to transmit multiple clocks.
  • the first clock and the second clock required by the CDMA system take a pair of lines
  • the first clock and the second clock required by the WCDMA system go to another pair of lines, etc.
  • the user board selects according to their own needs. Enter the clock.
  • This method not only increases the backplane routing, but also brings more work to the PCB design, which is not conducive to system expansion.
  • the technical problem to be solved by the present invention is to provide a method for transmitting and receiving a clock and a device for transmitting a clock, which can realize transmitting a plurality of clock signals on a pair of interconnect lines.
  • the present invention provides a method for transmitting a clock, comprising: a transmitting end selecting a first clock frequency, encoding a second clock for each system, and using the pair of interconnect lines The first clock frequency and the encoded second clock are sent to the respective receiving ends.
  • the transmitting end calculates a common divisor of each second clock cycle before starting encoding, and determines a delay T1 of the encoding phase, a delay T2 of the sending phase, and a delay T3 of the decoding phase;
  • the transmitting end continuously transmits the first clock frequency through a first clock transmission line
  • the transmitting end encodes each second clock and codes the encoded code words into a sequence according to a predetermined rule, and then adds a protection bit, a start bit, and a stop bit to form a fixed length data frame, and then one by one.
  • the bit is transmitted to the receiving end through the second clock transmission line.
  • the present invention also provides a method for receiving a clock, comprising: each receiving end receiving the first clock frequency from a first clock transmission line, counting locally with the first clock frequency, and receiving the encoded code from a second clock transmission line The second clock and parses the encoded second clock.
  • the second clock required by the receiving end is generated by the first clock count.
  • the encoded second clock is encapsulated into a data frame, and the data frame includes a protection bit, and after receiving the data frame, each receiving end determines whether the protection bit is correct, and if correct, the code of the corresponding part The word is decoded, otherwise the data frame is discarded.
  • the present invention also provides an apparatus for transmitting a clock, the apparatus comprising a transmitting end, a first clock transmission line, and a second clock transmission line;
  • the transmitting end includes a control module, one or more clock encoding modules, and a sending module; the control module is configured to select a first clock frequency and send the same to the sending module; each of the multiple clock encoding modules Corresponding to the second clock of the system, the clock encoding module is configured to encode the second clock of the corresponding system, and send the encoded codeword to the sending module; the sending module is configured to transmit the line through the first clock Sending the first clock frequency, And transmitting the encoded second clock through the second clock transmission line.
  • control module is further configured to calculate a common divisor of each second clock cycle, and send the common divisor to each clock encoding module;
  • the clock encoding module is configured to: after receiving the start coding flag, encode the corresponding second clock by using the common number.
  • the sending module is further configured to: after receiving the codewords sent by the clock encoding modules, group the codewords into a sequence, and add a protection bit, a start bit, and a stop bit to form a fixed length data frame. After receiving the first clock frequency, the sending module continuously sends the first clock frequency through the first clock transmission line, and receives the flag for starting transmission to send the data frame through the second clock transmission line.
  • the present invention also provides an apparatus for receiving a clock, including one or more receiving ends; the receiving end includes a decoding module and a clock phase locked loop;
  • the clock phase locked loop is configured to receive a first clock frequency from a first clock transmission line
  • the decoding module is configured to receive a data frame from the second clock transmission line and parse the required second clock according to the data frame.
  • the clock phase locked loop is further configured to: when the received first clock frequency is not the first clock required by the receiving end, recover the first required by the receiving end according to the first clock frequency a clock.
  • the decoding module is further configured to: after receiving the data frame, determine whether the protection bit is correct, and if yes, decode the corresponding codeword, otherwise discard the data frame, and use the first The clock is counted locally, producing the second clock required by the receiver.
  • the invention provides a method for transmitting and receiving a clock and a device for transmitting a clock, which encodes and framing a plurality of clocks at a transmitting end according to the method of the present invention, thereby realizing transmission of multiple clocks on a pair of interconnected lines. Signals, the board at the receiving end can accurately recover the clock it needs according to the corresponding decoding rules.
  • FIG. 1 is a schematic structural view of an apparatus for transmitting a clock according to the present invention
  • FIG. 3 is a flow chart of a method for transmitting a clock according to an example of the present invention.
  • FIG. 5 is a schematic structural diagram of a data frame after encoding according to an embodiment of the present invention.
  • the invention provides a method for transmitting and receiving a clock and a device for transmitting a clock, which encodes and framing a plurality of clocks at a transmitting end according to the method of the present invention, thereby realizing transmission of a plurality of clocks on a pair of interconnected lines, and a single receiving end According to the corresponding decoding rules, the board can accurately recover the clock it needs.
  • the clock board In a multimode base station, the clock board outputs a high-stability reference frequency to the user board by locking the reference input clock, which is hereinafter referred to as the first clock; and the user board is required to provide a high-accuracy clock reference, hereinafter referred to as the second clock.
  • Figure 1 illustrates the connection between the multimode base station clock board (the transmitter in the figure) and each user board (the receiver in the figure).
  • the clock board passes the first clock through a pair of interconnects on the backplane.
  • the second clock is delivered to each receiving end.
  • the second clock needs to be encoded. The following is an example to illustrate the way the multi-mode base station clock code is transmitted.
  • the embodiment provides a device for transmitting a clock, as shown in FIG. 1 , including a transmitting end, a receiving end, a first clock transmission line, and a second clock transmission line;
  • the transmitting end includes a control module, one or more clock encoding modules, and a sending module.
  • the control module is configured to select a suitable first clock frequency, and send the first clock frequency to the sending module, where the first clock frequency must be To meet the requirements of the various frequency clocks required by the receiving board, in addition, you need to consider the timing requirements of the receiving end device, the first clock.
  • the frequency should not be too high.
  • the control module is further configured to calculate a common divisor of each second clock cycle, and send the common divisor to each clock encoding module; and is also used to determine a delay T1 of the encoding phase, a delay T2 of the transmitting phase, and a delay of the decoding phase. T3;
  • the clock encoding module is configured to encode the second clock of the system according to the received common divisor, and the encoding rule is selected according to the requirements of the standard. The present invention does not limit this.
  • the clock encoding module is further configured to send the encoded codeword to the sending module.
  • the sending module is configured to continuously send the first clock frequency through the first clock transmission line after receiving the first clock frequency, and may also be used to receive a codeword sent by each clock encoding module and then form a sequence according to a predetermined rule.
  • the predetermined rule may be, but is not limited to, arranging the code words in a sequence as shown in FIG. 5, and the order of arrangement is not limited; the sending module may also be used to add a protection bit to the sequence, which may be, but is not limited to, parity.
  • the check code, and the start bit and the stop bit are combined to form a data frame, and are used to transmit the data frame through the second clock transmission line after receiving the start transmission flag.
  • the first clock signal is a higher frequency clock signal
  • the second clock signal is a lower frequency timing signal
  • the second clock signal period includes an integer number of first clock signal periods.
  • the receiving end includes a decoding module and a clock phase locked loop
  • the clock phase-locked loop is configured to receive the first clock frequency from the first clock transmission line. If the first clock frequency is the clock frequency required by itself, the first clock frequency can be directly used, otherwise the clock phase-locked loop is Recovering the clock frequency required by the first clock frequency according to the first clock frequency; the decoding module is configured to receive the data frame from the second clock transmission line, and decode the codeword corresponding to the standard according to the decoding rule corresponding to the encoding rule; Determining whether the protection bit is correct when the received data frame has a protection bit, if it is correct, decoding the codeword of the corresponding part (the corresponding part refers to the coding of the second clock of the standard), otherwise discarding the data frame; The decoding module is further configured to: when the second clock cannot be correctly parsed, the first clock that is recovered is locally counted, and the second clock required by the receiving end is generated, and when the second clock is correctly parsed, the local counting is generated. The second clock is synchronized to the parsed second clock.
  • the embodiment provides a method for transmitting a clock. As shown in FIG. 3, the method includes the following steps: Step 301a: The transmitting end selects a suitable first clock frequency for transmission, and then performs step 304a;
  • the receiving board may be a different board, the required clock frequency is different. Therefore, the first clock frequency must be selected to meet the requirements of the various frequency clocks required by the board at the receiving end. In addition, it is also necessary to consider the timing requirements of the receiving device. The first clock frequency cannot be too ⁇ 3 ⁇ 4.
  • Step 301b The transmitting end calculates the common divisor of each second clock cycle to be delivered, and then performs step 302;
  • the CDMA system requires a timing signal to be transmitted in a period of 2 seconds.
  • the GSM system requires a timing signal to be transmitted in a period of 60 ms.
  • the WCDMA system requires a timing signal to be transmitted in a period of 10 ms. Then 10 ms is a common divisor of each timing signal period, and 10 ms can be selected.
  • the encoded signal is transmitted periodically.
  • the first clock count can be used to generate a timing signal in a common-count period.
  • Step 302 Accurately calculate the delay of each phase, including the delay T1 of the coding phase, the delay of the transmission phase ⁇ 2, and the delay of the decoding phase ⁇ 3;
  • Step 303 The transmitting end starts to independently encode the required encoding of the clock according to the foregoing common number, and the codewords of the encoding modules are arranged according to certain rules according to a certain rule.
  • the sequence if it can be arranged in a sequence as shown in FIG. 5, is not limited in the order of arrangement, and then a protection bit can be added after the sequence, and the protection bit can be, but is not limited to, a parity code, and finally added
  • Each coding module can select an encoding rule according to the needs of the system. In this step, when the coding clock period of the coding module coincides with the periodic timing signal of the corresponding system, the effective coding is output, otherwise the invalid coding is output.
  • the composed data frame length is fixed.
  • Step 304a The transmitting end continuously transmits the first clock frequency through the first clock transmission line.
  • Step 305a Each receiving end receives the first clock frequency from the first clock transmission line. If the first clock frequency is the clock frequency required by itself, the first clock frequency can be directly used, otherwise the clock phase locked loop is used to recover. Outputting the clock frequency required by itself; then counting the local clock with the first clock to obtain a timing signal synchronized with the second clock, and the timing signal is also generated periodically;
  • Step 305b Each receiving end further receives a data frame composed of the encoded second clock from the second clock transmission line, and decodes the codeword corresponding to the data frame according to the decoding rule corresponding to the coding rule, and parses the required first The two clocks, the corresponding part of the code word refers to the part corresponding to the receiving end system.
  • each receiving end After receiving the data frame, each receiving end first determines whether the protection bit is correct, and if yes, decodes the codeword of the corresponding part, otherwise discards the data frame. If the receiving end correctly parses out the second clock, the timing signal obtained by counting the first clock is synchronized with the second clock that is parsed. If the receiving end does not receive the data frame for a period of time or determines that the codeword received by the receiving end has When the second clock is not parsed from the error, the timing signal is used instead of the second clock to be distributed to other modules.
  • the first clock frequency selected in this embodiment is 61.44 MHz, which is a relatively common clock frequency transmitted by the optical module, and the receiving end can lock out the clock frequency required by the receiving terminal, such as required by the CDMA system. 39.3216MHz, 13MHz required by the GSM system.
  • a multimode base station is designed to be compatible with CDMA, WCDMA, GSM, TD-SCDMA,
  • CDMA requires transmission of a PP2S pulse with a period of 2 seconds, which is aligned with GPS time
  • WCDMA requires transmission to generate a continuous frame synchronization signal with a period of 10 ms
  • GSM requires transmission with a period of 60 ms.
  • a continuous frame synchronization signal is generated
  • TD-SCDMA also requires transmission to generate a continuous frame synchronization signal with a period of 10 ms
  • WIMAX requires a PP1S pulse with a transmission period of 1 second, which is aligned with the GPS time.
  • Step 1 Calculate the greatest common divisor of each second clock. Obviously, for this base station, the greatest common divisor of the second clock is 10 ms.
  • Step 2 Generate a pulse signal with a period of 10ms using the first clock count, count and generate a pulse signal with a period of 2s, count and generate a pulse signal with a period of 60ms, and generate a pulse signal with a period of Is, each pulse signal. Aligned with the 10ms pulse signal.
  • Step 3 Accurately calculate the delay of the coding phase Tl, the delay of the transmission phase ⁇ 2 and the delay of the decoding phase ⁇ 3, the first clock samples to the 10ms pulse signal, and the coding modules of each system start to encode independently.
  • the CDMA coding module samples a 10ms pulse and a PP2S pulse at the same time, a codeword A is generated, and if only a 10ms pulse is generated, another code B is generated (ie, for the CDMA receiver, an invalid code is generated).
  • GSM encoding module if you sample to 10ms pulse and 60ms pulse at the same time, add 13 to the frame number. If you only sample to 10ms pulse, keep the frame number unchanged. Other coding modules also follow the respective 10ms pulse. Rule coding.
  • the CPU when the coding module is started, the CPU notifies the current time information of the coding module, and the coding module calculates a value based on this information, and then adds 100 to this value every 10 ms. For example, when the WCDMA module is started, the initial value is 0, and then 1 is added every 10ms.
  • the first clock is transmitted continuously, and the second clock is transmitted every 10 ms.
  • 5 invalid codes have no effect on the receiving end, which can be understood as direct discarding.
  • Step 4 Arrange the code words of each coding module into a sequence according to a certain rule, and add some protection bits to the code words of the entire sequence, such as adding a parity check code.
  • Step 5 Send the code words with the protection bits one by one to the interconnect on the backplane.
  • the transmit module is controlled by the first clock, and each bit is sent at the same time.
  • Step 6 At each receiving end, a decoding module decodes the received codeword according to the corresponding rule, and parses out the second clock required by itself.
  • Step 7 The decoding module of each receiving end has a hold function, that is, the code word is not received for a period of time. Or when the received codeword is wrong, the decoding module can count locally with the first clock and continue to output the second clock required by the receiving end.
  • the second clock generated by the local counting is synchronized with the parsed second clock.
  • Step 8 The clock in step 2 needs to be generated with respect to the reference advance time T to ensure that the second clock recovered by the receiving end is aligned with the reference clock.
  • a in Figure 2 represents the PP2S pulse required for CDMA
  • B represents the 60ms pulse required for GSM
  • C represents the 10ms pulse required for WCDMA
  • D represents the greatest common divisor of the three clocks
  • 10ms pulse represents the coded The second clock changes every 10ms.
  • a in Fig. 4 denotes a first clock, and the previous pulse of the B signal indicates an indication signal to start encoding, and the latter pulse is aligned with the reference signal.
  • the meanings of T, Tl, T2, T3 are as described above.
  • C denotes the recovered signal in the receiving end and is aligned with the reference signal.
  • the clocks required by various base stations can be transmitted on a pair of interconnect lines, and the receiving end can accurately recover the clocks required by itself. It reduces the interconnection on the backplane, increases flexibility, and avoids inaccurate clocks recovered from the receiver.
  • the method for transmitting and receiving a clock and the method for transmitting a clock provided by the present invention encode and framing a plurality of clocks at a transmitting end, thereby transmitting a clock required by various base stations on a pair of interconnect lines.
  • the receiving end can accurately recover the clock it needs. It reduces the interconnection on the backplane, increases flexibility, and avoids inaccurate clocks recovered from the receiver.

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  • Computer Networks & Wireless Communication (AREA)
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Description

发送、 接收时钟的方法及传递时钟的装置
技术领域
本发明涉及通信领域， 尤其是多模基站中板间发送、 接收时钟的方法及 传递时钟的装置。
背景技术
基站中的时钟单板， 用于从参考时钟中提取和恢复时钟， 再根据***的 要求产生新的时钟并分发至其他单板。 需要传递的时钟一般包括两个时钟信 号， 第一时钟信号用于传递某个时钟频率， 第二时钟信号用于传递定时信号。 传统的基站架构下， 一个基站只需要承载一种制式的业务， 如 CDMA基站仅 仅用于 CDMA***， 因此对时钟的要求也是单一的， 时钟板只需要根据*** 的需求分发某个单一的时钟频率和定时信号即可。
对于多模基站， 同一基站架构下要求兼容多种制式的业务， 如 CDMA/WCDMA/GSM等。 而不同的制式对第一时钟信号和第二时钟信号要 求是不同的， 因此多模基站需要考虑如何传递多个时钟。
对于多模基站传递多个时钟， 一般是通过不同的硬件连线传递不同的时 钟。 比如 CDMA***要求的第一时钟和第二时钟走一对线， WCDMA***要 求的第一时钟和第二时钟走另外一对线， ... ...等等， 用户板根据自己的需求 选择输入的时钟。 这种方式既增加了背板走线， 给 PCB设计带来了更多的工 作量， 又不利于***扩展。
发明内容
本发明要解决的技术问题是提供发送、 接收时钟的方法及传递时钟的装 置， 可实现在一对互连线上传递多种时钟信号。
为了解决上述问题， 本发明提供了一种发送时钟的方法， 包括： 发送端 选择第一时钟频率， 为各制式的第二时钟编码， 以及通过一对互连线将所述 第一时钟频率及编码后的第二时钟发送至各接收端。
进一步地， 所述发送端开始编码前计算各第二时钟周期的公约数， 以及 确定编码阶段的时延 T1 , 发送阶段的时延 T2及解码阶段的时延 T3；
所述发送端在周期定时信号到达前 tl时间以所述公约数为周期为各制式 的第二时钟编码， 所述 tl= Tl+T2+T3。
进一步地， 所述发送端通过第一时钟传递线路连续发送所述第一时钟频 率；
所述发送端在周期定时信号到达前 t2时间开始发送编码后的第二时钟， 所述 t2=T2+T3。
进一步地， 所述发送端对各第二时钟编码后将编码后的码字按预定规则 排列成一个序列， 之后加上保护位、 起始位及终止位， 组成固定长度的数据 帧， 然后逐一比特通过第二时钟传递线路发送至接收端。
本发明还提供一种接收时钟的方法， 包括： 各接收端从第一时钟传递线 路接收上述第一时钟频率， 用所述第一时钟频率在本地计数， 从第二时钟传 递线路接收上述编码后的第二时钟并解析所述编码后的第二时钟。
进一步地， 当接收端不能解析出正确的第二时钟时， 用所述第一时钟计 数产生所述接收端所需的第二时钟。
进一步地， 所述编码后的第二时钟封装为数据帧， 所述数据帧包括保护 位， 所述各接收端收到数据帧后， 先判断保护位是否正确， 若正确则对对应 部分的码字进行解码， 否则丟弃该数据帧。
本发明还提供一种发送时钟的装置， 所述装置包括发送端、 第一时钟传 递线路及第二时钟传递线路；
所述发送端包括控制模块、 一个或多个时钟编码模块以及发送模块； 所述控制模块用于选择第一时钟频率 , 并将其发送至发送模块； 所述多个时钟编码模块中的每一个对应一制式的第二时钟， 所述时钟编 码模块用于为对应制式的第二时钟编码，并将编码后的码字发送至发送模块； 所述发送模块用于通过所述第一时钟传递线路发送所述第一时钟频率， 以及通过所述第二时钟传递线路发送编码后的第二时钟。
进一步地， 所述控制模块还用于计算各第二时钟周期的公约数， 并将该 公约数发送至各时钟编码模块；
所述控制模块还用于确定编码阶段的时延 T1、 发送阶段的时延 T2及解 码阶段的时延 T3;以及在周期定时信号到达前 tl时间向各时钟编码模块发送 开始编码的标志， 所述 tl=Tl+T2+T3;
所述时钟编码模块用于收到所述开始编码的标志后以所述公约数为周期 对对应的第二时钟进行编码。
进一步地， 控制模块还用于周期定时信号到达前 t2时间向发送模块发送 一开始发送的标志， 所述 t2=T2+T3;
所述发送模块还用于收到所述各时钟编码模块发来的码字后， 将所述码 字组成一个序列， 并加上保护位、 起始位及终止位， 组成固定长度的数据帧； 所述发送模块收到第一时钟频率后通过第一时钟传递线路连续发送第一 时钟频率，收到所述开始发送的标志通过第二时钟传递线路发送所述数据帧。
本发明还提供了一种接收时钟的装置， 包括一个或多个接收端； 所述接收端包括解码模块及时钟锁相环；
所述时钟锁相环用于从第一时钟传递线路接收第一时钟频率；
所述解码模块用于从第二时钟传递线路接收数据帧， 并根据所述数据帧 解析出所需的第二时钟。
进一步地， 所述时钟锁相环还用于当收到的所述第一时钟频率不是该接 收端所需的第一时钟时， 根据所述第一时钟频率恢复出该接收端所需的第一 时钟。
进一步地， 所述解码模块还用于收到所述数据帧后先判断所述保护位是 否正确， 若正确则对对应的码字进行解码， 否则丟弃所述数据帧， 并用所述 第一时钟在本地计数， 产生该接收端所需的第二时钟。
本发明提供了发送、 接收时钟的方法及传递时钟的装置， 将多种时钟在 发送端按照本发明方法编码、 组帧， 从而实现在一对互连线上传递多种时钟 信号， 接收端的单板按照对应的解码规则， 可以准确地恢复出自己所需的时 钟。
附图概述
图 1是本发明传递时钟的装置结构示意图；
图 2是本发明实例方法的编码时序图；
图 3是本发明实例方法传递时钟的流程图；
图 4是本发明实施例编解码时序图；
图 5是本发明实施例编码后数据帧的结构示意图。
本发明的较佳实施方式
本发明提供了发送、 接收时钟的方法及传递时钟的装置， 将多种时钟在 发送端按照本发明的方法编码、 组帧， 从而实现在一对互连线上传递多种时 钟，接收端的单板按照对应的解码规则， 可以准确地恢复出自己所需的时钟。
多模基站中， 时钟板通过锁定参考输入的时钟， 给用户板输出一个高稳 定度的基准频率， 以下称第一时钟； 同时需要给用户板提供一个高准确度的 时钟基准， 以下称第二时钟。 图 1 中说明了多模基站时钟板（即图中的发送 端 )和各用户板（即图中的接收端 ) 的连接关系， 时钟板通过背板上的一对 互连线将第一时钟和第二时钟传递到各接收端。 为了适应多种制式基站下多 时钟的要求， 需要对第二时钟进行编码。 下面通过一个实例说明多模基站时 钟编码传递的方式。
本实施例提供一种传递时钟的装置， 如图 1所示， 包括发送端、 接收端、 第一时钟传递线路及第二时钟传递线路；
发送端包括控制模块、 一个或多个时钟编码模块、 发送模块； 其中， 控制模块用于选择一个合适的第一时钟频率， 并将该第一时钟频率发送 至发送模块， 该第一时钟频率必须要满足接收端的单板能恢复出自己所需的 各种频率时钟的要求， 另外， 还需要考虑接收端器件的时序要求， 第一时钟 频率不能太高。
控制模块还用于计算各第二时钟周期的公约数， 并将该公约数发送至各 时钟编码模块； 还用于确定编码阶段的时延 T1 , 发送阶段的时延 T2和解码 阶段的时延 T3;
控制模块还用于当周期定时信号到达前 tl时间向各制式的时钟编码模块 发送一开始编码的标志， tl=Tl+T2+T3 , 以及周期定时信号到达前 t2 ( t2=T2+T3 ) 时间向发送模块发送一开始发送的标志；
时钟编码模块用于收到开始编码的标志后， 以收到的公约数为周期对该 制式的第二时钟进行编码， 其编码规则按该制式的要求进行选择， 本发明对 此不作限制。 时钟编码模块还用于将编码后的码字发送至发送模块。
发送模块用于收到第一时钟频率后通过第一时钟传递线路连续发送第一 时钟频率， 还可以用于收到各时钟编码模块发来的码字后将其按预定的规则 组成一个序列， 该预定的规则可以但不限于是如图 5所示的将各码字顺序排 成一列， 其排列顺序不作限制； 发送模块还可以用于为上述序列加上保护位， 可以但不限于是奇偶校验码， 以及加上起始位和终止位组成数据帧， 并用于 收到开始发送的标志后通过第二时钟传递线路发送上述数据帧。
第一时钟信号是个频率较高的时钟信号， 第二时钟信号是频率较低的定 时信号， 一个第二时钟信号周期包含整数个第一时钟信号周期。
接收端包括解码模块及时钟锁相环； 其中，
时钟锁相环用于从第一时钟传递线路接收第一时钟频率， 若该第一时钟 频率即为自己所需的时钟频率， 则可直接使用该第一时钟频率， 否则时钟锁 相环才艮据该第一时钟频率恢复出自己所需的时钟频率； 解码模块用于从第二时钟传递线路接收数据帧， 并按编码规则对应的解 码规则对该制式对应的码字进行解码； 还可以用于当收到的数据帧有保护位 时判断该保护位是否正确， 若正确则对对应部分的码字进行解码（对应部分 指该制式第二时钟的编码） ， 否则丟弃该数据帧； 解码模块还用于当不能正确解析出第二时钟时， 用恢复出的第一时钟在 本地计数， 产生该接收端所需的第二时钟， 当正确解析出第二时钟时， 将本 地计数产生的第二时钟同步于解析出的第二时钟。
本实施例提供一种传递时钟的方法， 如图 3所示， 包括以下步骤： 步骤 301a: 发送端选择一个合适的第一时钟频率用于传递， 然后执行步 骤 304a;
由于接收端单板可能是不同制式的单板， 需要的时钟频率也不相同， 因 此选择的第一时钟频率必须要满足接收端的单板能恢复出自己所需的各种频 率时钟的要求。 另外， 还需要考虑接收端器件的时序要求， 第一时钟频率不 能太 τ¾。
步骤 301b: 发送端计算需要传递的各个第二时钟周期的公约数， 然后执 行步骤 302;
如 CDMA***要求以 2秒为周期传递定时信号， GSM***要求以 60ms 为周期传递定时信号， WCDMA***要求以 10ms为周期传递定时信号， 则 10ms为各个定时信号周期的公约数， 可以选择 10ms为周期发送编码后的信 号。
该步中， 可以用第一时钟计数产生以公约数为周期的定时信号。
步骤 302: 精确计算出各个阶段的时延， 包括编码阶段的时延 Tl、 发送 阶段的时延 Τ2及解码阶段的时延 Τ3;
步骤 303: 发送端在周期定时信号到达前提前时间 tl按照各个制式， 以 上述公约数为周期编码对时钟的要求编码开始独立编码， 将各个编码模块编 好的码字按照一定的规则排列成一个序列，如可以是按如图 5所示的 顺序排 成一列， 其排列顺序不作限制， 然后可以在该序列之后加上保护位， 该保护 位可以但不限于是奇偶校验码， 最后加上起始位和终止位， 组成一数据帧； 其中 tl=Tl+T2+T3; 整个编码过程所用时间为 Tl。 还可以预留一些数据以做 扩展用 （在图 5中未示出） 。 然后执行步骤 304b。
各编码模块可根据该制式的需要选择编码规则。 该步中，当编码模块的编码时钟周期与对应制式的周期定时信号重合时 , 输出有效编码， 否则输出无效编码。
当制式确定时， 组成的数据帧长度固定。
步骤 304a: 发送端通过第一时钟传递线路连续发送第一时钟频率； 步骤 304b: 发送端在周期定时信号到达前提前时间 t2 ( t2=T2+T3 )开始 通过第二时钟传递线路发送编码后第二时钟组成的数据帧， 该数据帧是逐一 比特发送到背板上的互连线上；
步骤 305a: 各接收端从第一时钟传递线路接收第一时钟频率， 若该第一 时钟频率即为自己所需的时钟频率， 则可直接使用该第一时钟频率， 否则通 过时钟锁相环恢复出自己所需的时钟频率； 之后用第一时钟在本地计数得到 一个与第二时钟同步的定时信号， 这个定时信号也是周期性地产生；
步骤 305b: 各接收端还从第二时钟传递线路接收编码后第二时钟组成的 数据帧， 并对该数据帧对应部分的码字按照编码规则对应的解码规则解码， 解析出自己所需的第二时钟， 对应部分的码字指该接收端制式对应的部分。
进一步地， 各接收端收到数据帧后先判断保护位是否正确， 若正确则对 对应部分的码字进行解码， 否则丟弃该数据帧。 若接收端正确解析出第二时 钟， 则将第一时钟计数得到的定时信号同步于解析出的第二时钟， 若接收端 一段时间内收不到数据帧或判断自己收到的码字中有误码， 不能从中解析出 第二时钟时， 则用该定时信号替代第二时钟分发给其他模块。
下面通过一应用实例进一步说明本发明
本实施例中选择的第一时钟频率为 61.44MHz,为用光模块传输的一个比 较通用的时钟频率， 同时接收端可以通过这个时钟频率锁出自己所需的时钟 频率， 如 CDMA***所需要的 39.3216MHz, GSM***所需要的 13MHz等。
某多模基站设计时考虑兼容 CDMA、 WCDMA、 GSM、 TD-SCDMA,
WIMAX五种不同制式， 各种制式的基站***对第二时钟的要求都不同。 其 中 CDMA要求传送一个周期为 2秒的 PP2S脉冲，与 GPS时间对齐； WCDMA 要求传送以周期为 10ms产生连续帧同步信号； GSM要求传送以周期为 60ms 产生连续的帧同步信号； TD-SCDMA也要求传送以周期为 10ms产生连续的 帧同步信号， WIMAX要求传送周期为 1秒的 PP1S脉冲， 与 GPS时间对齐。 实施的步骤如下：
步骤 1 : 计算出各第二时钟的最大公约数， 显然对于这个基站来说， 第 二时钟的最大公约数为 10ms。
步骤 2: 用第一时钟计数产生一个周期为 10ms的脉冲信号， 计数产生一 个周期为 2s的脉冲信号， 计数产生一个周期为 60ms的脉冲信号， 计数产生 一个周期为 Is的脉冲信号， 各个脉冲信号与 10ms脉冲信号对齐。
步骤 3: 准确计算出编码阶段的延时 Tl、发送阶段的延时 Τ2及解码阶段 的延时 Τ3 , 第一时钟釆样到 10ms脉冲信号， 各个制式的编码模块开始独立 编码。
比如 CDMA编码模块， 如果同时釆样到 10ms脉冲和 PP2S脉冲， 产生 一个码字 A, 如果只釆样到 10ms脉冲， 则产生另一个码子 B (即对于 CDMA 接收端来说， 产生的是无效编码） 。 GSM编码模块， 如果同时釆样到 10ms 脉冲和 60ms脉冲， 将帧号数加上 13 , 如果只釆样到 10ms脉冲， 将帧号数保 持不变， 其他编码模块也在 10ms 脉冲到来时按照各自的规则编码。 如 TD-SCDMA编码模块，在启动编码模块时， CPU通知编码模块当前的时间信 息，编码模块根据这个信息计算得到一个数值，之后每 10ms将这个数值加上 100。 如 WCDMA模块， 启动编码模块时， 初始值为 0, 之后每 10ms加 1。
第一时钟是连续发送的， 第二时钟每 10ms发送一次。 对于 GSM模块来 说， 5次无效编码对于接收端是没有作用的， 可以理解为直接丟弃。
步骤 4: 将各个编码模块编好的码字按照一定的规则排列成一个序列， 对整个序列的码字加上一些保护位， 比如加上奇偶校验码等。
步骤 5: 将加上保护位的码字逐一比特发送到背板上的互连线上， 发送 模块由第一时钟控制， 每个比特发送的时间相同。
步骤 6: 在各接收端， 用一个解码模块对接收到的码字按照对应的规则 解码， 解析出自己所需的第二时钟。
步骤 7: 各接收端的解码模块具有保持功能， 即当一段时间收不到码字 或者收到的码字错误时， 解码模块可以用第一时钟在本地计数， 继续输出接 收端所需的第二时钟。 当收到时钟板发送的正确码字时， 将本地计数产生的 第二时钟同步于解析出来的第二时钟。 步骤 8: 步骤 2中的时钟需要相对参考提前时间 T产生， 以保证接收端 恢复出来的第二时钟和参考时钟对齐。
附图 2中的 A表示 CDMA所需的 PP2S脉冲， B表示 GSM所需的 60ms 脉冲 , C表示 WCDMA所需的 10ms脉冲 , D表示三个时钟的最大公约数 10ms 脉冲， E表示编码后的第二时钟， 每 10ms变化一次。
附图 4中的 A表示第一时钟， B信号的前一个脉冲表示开始编码的指示 信号， 后一个脉冲与参考信号对齐的。 T, Tl , T2, T3的意义如前文中所述。 C表示接收端中恢复出来的信号， 与参考信号对齐。
釆用本发明所述的技术方案， 可以在一对互连线上传递各种制式基站所 需的时钟， 接收端可以准确恢复出自己所需的时钟。 既减少了背板上的互连 线， 增加了灵活性， 又可避免接收端恢复出来的时钟不准确。
工业实用性 本发明所提供的发送、 接收时钟的方法及传递时钟的装置， 将多种时钟 在发送端编码、 组帧， 从而可以在一对互连线上传递各种制式基站所需的时 钟， 接收端可以准确恢复出自己所需的时钟。 既减少了背板上的互连线， 增 加了灵活性， 又可避免接收端恢复出来的时钟不准确。

Claims

权 利 要 求 书
1、 一种发送时钟的方法， 包括：
发送端选择第一时钟频率， 为各制式的第二时钟编码， 以及通过一对互 连线将所述第一时钟频率及编码后的第二时钟发送至各接收端。
2、如权利要求 1所述的方法， 在所述发送端为各制式的第二时钟编码的 步骤之前， 还包括： 所述发送端计算所述各制式的第二时钟的周期的公约数， 以及确定编码阶段的时延 T1 , 发送阶段的时延 T2及解码阶段的时延 T3; 所述发送端为各制式的第二时钟编码的步骤包括： 所述发送端在周期定 时信号到达前 tl时间以所述公约数为周期为各制式的第二时钟编码， 其中， 所述 tl= Tl+T2+T3。
3、 如权利要求 2所述的方法， 其中，
所述发送端将所述第一时钟频率及编码后的第二时钟发送至各接收端的 步骤包括：
所述发送端通过第一时钟传递线路连续发送所述第一时钟频率； 以及 所述发送端在所述周期定时信号到达前 t2时间开始发送编码后的第二时 钟， 其中， 所述 t2=T2+T3。
4、 如权利要求 1所述的方法， 其中，
所述发送端将编码后的第二时钟发送至各接收端的步骤包括： 所述发送 端对各第二时钟编码后将编码后的码字按预定规则排列成一个序列， 之后加 上保护位、 起始位及终止位， 组成固定长度的数据帧， 然后逐一比特通过第 二时钟传递线路发送至所述接收端。
5、 一种接收时钟的方法， 包括： 各接收端从第一时钟传递线路接收第一 时钟频率， 用所述第一时钟频率在本地计数， 从第二时钟传递线路接收编码 后的第二时钟并解析所述编码后的第二时钟。
6、 如权利要求 5所述的方法， 还包括：
当所述接收端不能解析出正确的第二时钟时， 所述接收端用所述第一时 钟频率计数产生所述接收端所需的第二时钟。
7、 如权利要求 5所述的方法， 其中，
所述编码后的第二时钟封装为数据帧， 所述数据帧包括保护位； 所述接收端接收所述编码后的第二时钟并解析所述编码后的第二时钟的 步骤包括所述接收端收到所述数据帧后， 先判断所述保护位是否正确， 若正 确则对所述接收端对应部分的码字进行解码， 否则丟弃所述数据帧。
8、 一种发送时钟的装置， 包括发送端、 第一时钟传递线路及第二时钟传 递线路； 其中
所述发送端包括控制模块、 一个或多个时钟编码模块以及发送模块； 所述控制模块设置为选择第一时钟频率， 并将所述第一时钟频率发送至 所述发送模块；
所述多个时钟编码模块中的每一个对应一制式的第二时钟， 所述时钟编 码模块设置为为对应制式的第二时钟编码， 并将编码后的码字发送至所述发 送模块；
所述发送模块设置为通过所述第一时钟传递线路发送所述第一时钟频 率， 以及通过所述第二时钟传递线路发送编码后的第二时钟。
9、 如权利要求 8所述的装置， 其中，
所述控制模块还设置为计算各第二时钟周期的公约数， 并将所述公约数 发送至各所述时钟编码模块； 确定编码阶段的时延 Tl、 发送阶段的时延 Τ2 及解码阶段的时延 Τ3;以及在周期定时信号到达前 tl时间向各所述时钟编码 模块发送开始编码的标志， 所述 tl=Tl+T2+T3;
所述时钟编码模块还设置为在收到所述开始编码的标志后以所述公约数 为周期对对应的第二时钟进行编码。
10、 如权利要求 9所述的装置， 其中，
所述控制模块还设置为在周期定时信号到达前 t2时间向所述发送模块发 送一开始发送的标志， 所述 t2=T2+T3;
所述发送模块还设置为在收到各所述时钟编码模块发来的码字后， 将所 述码字组成一个序列， 并加上保护位、 起始位及终止位， 组成固定长度的数 据帧； 在收到所述第一时钟频率后， 通过所述第一时钟传递线路连续发送所 述第一时钟频率； 以及在收到所述开始发送的标志后， 通过所述第二时钟传 递线路发送所述数据帧。
11、 一种接收时钟的装置， 包括一个或多个接收端；
所述接收端包括解码模块及时钟锁相环； 其中，
所述时钟锁相环设置为从第一时钟传递线路接收第一时钟频率； 所述解码模块设置为从第二时钟传递线路接收数据帧， 并根据所述数据 帧解析出所需的第二时钟。
12、 如权利要求 11所述的接收时钟的装置， 其中，
所述时钟锁相环还设置为在收到的所述第一时钟频率不是所述时钟锁相 环所在接收端所需的第一时钟时， 根据所述第一时钟频率恢复出所述时钟锁 相环所在接收端所需的第一时钟。
13、 如权利要求 11所述的接收时钟的装置， 其中，
所述解码模块还设置为在收到所述数据帧后先判断所述数据帧的保护位 是否正确，若正确则对对应所述解码模块所在接收端的制式的码字进行解码， 否则丟弃所述数据帧， 并用所述第一时钟频率在本地计数， 产生所述解码模 块所在接收端所需的第二时钟。
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