WO2010064446A1 - Nonvolatile memory element and nonvolatile memory device - Google Patents

Nonvolatile memory element and nonvolatile memory device Download PDF

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Publication number
WO2010064446A1
WO2010064446A1 PCT/JP2009/006622 JP2009006622W WO2010064446A1 WO 2010064446 A1 WO2010064446 A1 WO 2010064446A1 JP 2009006622 W JP2009006622 W JP 2009006622W WO 2010064446 A1 WO2010064446 A1 WO 2010064446A1
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Prior art keywords
nonvolatile memory
oxide layer
memory element
electrode
layer
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PCT/JP2009/006622
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French (fr)
Japanese (ja)
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高木剛
魏志強
二宮健生
村岡俊作
神澤好彦
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パナソニック株式会社
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Priority to US12/990,323 priority Critical patent/US8279657B2/en
Priority to JP2010527685A priority patent/JP4607257B2/en
Priority to CN200980114976.9A priority patent/CN102017145B/en
Publication of WO2010064446A1 publication Critical patent/WO2010064446A1/en
Priority to US13/599,286 priority patent/US8565005B2/en

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    • H—ELECTRICITY
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/101—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including resistors or capacitors only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0007—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising metal oxide memory material, e.g. perovskites
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/20—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/021—Formation of switching materials, e.g. deposition of layers
    • H10N70/026—Formation of switching materials, e.g. deposition of layers by physical vapor deposition, e.g. sputtering
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    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/061—Shaping switching materials
    • H10N70/063—Shaping switching materials by etching of pre-deposited switching material layers, e.g. lithography
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    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
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    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides
    • H10N70/8833—Binary metal oxides, e.g. TaOx
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G11C2013/0073—Write using bi-directional cell biasing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G11C2013/0083—Write to perform initialising, forming process, electro forming or conditioning
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/30—Resistive cell, memory material aspects
    • G11C2213/31—Material having complex metal oxide, e.g. perovskite structure
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/30—Resistive cell, memory material aspects
    • G11C2213/32—Material having simple binary metal oxide structure
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/50—Resistive cell structure aspects
    • G11C2213/56—Structure including two electrodes, a memory active layer and a so called passive or source or reservoir layer which is NOT an electrode, wherein the passive or source or reservoir layer is a source of ions which migrate afterwards in the memory active layer to be only trapped there, to form conductive filaments there or to react with the material of the memory active layer in redox way

Definitions

  • the present invention relates to a nonvolatile memory element, and in particular, a so-called variable resistance nonvolatile memory element that reversibly transits between a high resistance state and a low resistance state based on the polarity of an applied voltage, and the nonvolatile memory device
  • the present invention relates to a nonvolatile memory device provided with a memory element.
  • Nonvolatile memory elements that perform storage have been proposed (see, for example, Patent Document 1).
  • a nonvolatile memory element called a phase change memory is proposed in which the resistance state of the resistance change layer is changed by changing the crystal state of the resistance change layer by an electric pulse (see, for example, Patent Document 2). .
  • Nonvolatile memory elements are roughly classified into two types depending on the material used for the resistance change layer.
  • One of them is a perovskite material (Pr 1-x Ca x MnO 3 (PCMO), La 1-x Sr x MnO 3 (LSMO), GdBaCo x O y (GBCO), etc.) disclosed in Patent Document 3 and the like) Is a variable resistance nonvolatile memory element using the above in the variable resistance layer.
  • the other is a variable resistance nonvolatile memory element using a binary transition metal oxide. Since the binary transition metal oxide has a very simple composition and structure as compared with the above-described perovskite material, composition control and film formation at the time of manufacture are easy. In addition, there is an advantage that the compatibility with the semiconductor manufacturing process is relatively good, and many studies have been made in recent years.
  • Patent Document 4 and Non-Patent Document 1 disclose NiO, V 2 O 5 , ZnO, Nb 2 O 5 , TiO 2 , WO 3 , and CoO as resistance change materials.
  • Patent Document 5 discloses a resistance change type non-volatile using a suboxide (an oxide deviating from the stoichiometric composition) such as Ni, Ti, Hf, Nb, Zn, W, and Co as a resistance change material.
  • a storage element is disclosed.
  • an example in which a structure in which the surface of TiN is oxidized to form a nanometer order TiO 2 crystal film is used for the resistance change layer has also been proposed (see, for example, Patent Document 6 and Non-Patent Document 2). ).
  • Patent Document 7 a so-called one-time programmable memory that can be written only once using titanium oxide and tantalum oxide (Ta 2 O 5 ) as a resistance change material has been proposed (see, for example, Patent Document 7).
  • JP 2006-40946 A Japanese Patent Application Laid-Open No. 2004-346989 US Pat. No. 6,473,332 JP 2004-363604 A JP 2005-317976 A JP 2007-180202 A JP-A-7-263647
  • the conventional nonvolatile memory element using the transition metal oxide as described above for the resistance change layer has the following problems.
  • Non-Patent Document 1 the resistance change material is put into a high resistance state by using a relatively short electric pulse of about 100 ns. To a low resistance state.
  • a long pulse on the order of ⁇ s is required, and it is difficult to increase the speed.
  • an electrical pulse different from the polarity (positive or negative), magnitude (voltage value), and width (time) of an electrical pulse that can obtain a steady resistance state change is applied once.
  • the process of changing the resistance state of the resistance change type nonvolatile memory element immediately after manufacture by adding about ten times is defined as “initial break”.
  • an electrical pulse having a magnitude of 2 V and a width of 100 ns an electrical current having a different size and width is manufactured immediately after its manufacture.
  • the initial break process for the nonvolatile memory element whose initial state is the high resistance state is considered to be the same as the dielectric breakdown process of the dielectric film. For example, it is described in K. Kinoshita et al., Applied Physics Letters vol.89, 103509.
  • Patent Documents 6 and Non-Patent Document 2 the structure as to form by oxidizing the surface of TiN microcrystalline TiO 2 variable resistance having a (TiO 2 ⁇ TiN structure) In the nonvolatile memory element, the initial break is unnecessary.
  • TiO 2 is an aggregate of minute crystals (hereinafter referred to as nanocrystals) on the order of nanometers, and the state of resistance change is said to change depending on the size of the crystals.
  • the crystal structure largely depends on the manufacturing method (formed by oxidation in the above-mentioned Patent Document 6), and therefore, there may be a large variation in manufacturing. Therefore, when nanocrystals are used for the resistance change layer, there is a problem that the resistance change state is likely to vary.
  • the transition metal oxide composed of Ta 2 O 5 disclosed in Patent Document 7 when used as a main component in the resistance change layer, it can be used only for one operation from the high resistance state to the low resistance state. Since it functions as an antifuse, there is a problem that it cannot be rewritten.
  • the present invention has been made in view of such circumstances, and a main object of the present invention is a non-volatile memory element that can operate stably at a high speed at a low break voltage and a non-volatile memory element including the non-volatile memory element. It is to provide a sex memory device.
  • a nonvolatile memory element is a variable resistance nonvolatile memory element, which includes a first electrode, a second electrode, the first electrode, and the first electrode.
  • a resistance change layer interposed between the second electrode and reversibly transitioning between a high resistance state and a low resistance state based on a polarity of a voltage applied between the first electrode and the second electrode;
  • the resistance change layer is in an initial state having a resistance value higher than the resistance value of the nonvolatile memory element when the resistance change layer is in the high resistance state, an initial break is applied to apply a voltage with the load element connected.
  • the resistance change layer has a characteristic of changing to a state where the transition is possible by being performed, and the variable resistance layer includes at least a first oxide layer including an oxide of a first transition metal, and the first transition metal.
  • a second oxidation comprising an oxide of a different second transition metal
  • a standard electrode potential of the second transition metal is smaller than a standard electrode potential of the first transition metal, and (1) a dielectric constant of the second oxide layer is (1) and (2) in which the dielectric constant of the first oxide layer is larger than (2) the band gap of the second oxide layer is smaller than the band gap of the first oxide layer. At least one of the above is satisfied.
  • the second oxide layer containing the second transition metal having a small standard electrode potential that is, the second oxidation layer that is more easily oxidized among the first and second oxide layers constituting the resistance change layer.
  • the dielectric constant of the material layer is greater than the dielectric constant of the first oxide layer, and at least one of the band gap of the second oxide layer is smaller than the band gap of the first oxide layer is satisfied Therefore, the second oxide layer having a high resistivity has a smaller breakdown field strength than the first oxide layer having a low resistivity, and as a result, the nonvolatile memory in which the initial state is in a high resistance state.
  • the break voltage in the initial break of the element that is, the nonvolatile memory element having a variable resistance layer having a laminated structure of transition metal oxide layers) is reduced.
  • a dielectric constant of the second oxide layer is larger than a dielectric constant of the first oxide layer
  • the second Both of the band gap of the oxide layer may be smaller than the band gap of the first oxide layer
  • the second electrode is formed so as to be in contact with the second oxide layer, and a standard electrode potential of the second electrode is a standard of the second transition metal. It is preferably larger than the electrode potential.
  • the standard electrode potential of the first transition metal is smaller than the standard electrode potential of the second electrode.
  • the oxygen deficiency of the first oxide layer is larger than the oxygen deficiency of the second oxide layer.
  • the thickness of the second oxide layer is thinner than the thickness of the first oxide layer.
  • the resistivity of the second oxide layer is larger than the resistivity of the first oxide layer.
  • a load element may be electrically connected to the nonvolatile memory element according to the above aspect, and the load element may be a fixed resistor, a transistor, or a diode.
  • the first transition metal is preferably Ta
  • the second transition metal is preferably Ti, Sr, or Nb.
  • the nonvolatile memory device of one embodiment of the present invention includes a semiconductor substrate, a plurality of first wirings formed in parallel to each other on the semiconductor substrate, and the semiconductor above the plurality of first wirings.
  • a plurality of second wirings formed parallel to each other in a plane parallel to the main surface of the substrate and three-dimensionally intersecting with the plurality of first wirings; the plurality of first wirings;
  • a selection circuit to be selected, a writing circuit for writing data by applying a voltage to the nonvolatile memory element selected by the selection circuit, and a resistance value of the nonvolatile memory element selected by the selection circuit are detected Characterized in that it comprises a read circuit for reading data in Rukoto.
  • the nonvolatile memory device includes the nonvolatile memory element according to the present invention having the above-described characteristics, the break voltage in the initial break of the nonvolatile memory element in which the initial state is in the high resistance state is reduced. Is done.
  • the nonvolatile memory device may further include a current suppressing element electrically connected to each of the nonvolatile memory elements.
  • a nonvolatile memory device includes a semiconductor substrate, a plurality of word lines and a plurality of bit lines formed on the semiconductor substrate, and the plurality of word lines and the plurality of bit lines, respectively.
  • a memory cell array including a plurality of connected transistors, and a plurality of nonvolatile memory elements according to the above-described aspect provided in one-to-one correspondence with the plurality of transistors, and a nonvolatile memory element included in the memory cell array
  • a selection circuit for selecting at least one nonvolatile memory element, a writing circuit for writing data by applying a voltage to the nonvolatile memory element selected by the selection circuit, and a nonvolatile circuit selected by the selection circuit And a reading circuit that reads data by detecting a resistance value of the memory element.
  • the nonvolatile memory device includes the nonvolatile memory element according to the present invention having the above-described characteristics, the break voltage in the initial break of the nonvolatile memory element in which the initial state is in the high resistance state is reduced. Is done.
  • the break voltage in the initial break of the nonvolatile memory element is reduced, and the resistance value of the nonvolatile memory element can be changed reliably. Operation can be realized.
  • FIG. 1 is a cross-sectional view showing a configuration of a nonvolatile memory element according to Embodiment 1 of the present invention.
  • FIG. 2 is a cross-sectional view showing a manufacturing process of the nonvolatile memory element according to Embodiment 1 of the present invention.
  • FIG. 3 is a diagram showing an operation example of the nonvolatile memory element according to Embodiment 1 of the present invention when information is written.
  • FIG. 4 is a diagram illustrating an operation example of the nonvolatile memory element according to Embodiment 1 of the present invention when reading information.
  • FIG. 1 is a cross-sectional view showing a configuration of a nonvolatile memory element according to Embodiment 1 of the present invention.
  • FIG. 2 is a cross-sectional view showing a manufacturing process of the nonvolatile memory element according to Embodiment 1 of the present invention.
  • FIG. 3 is a diagram showing an operation example of the nonvolatile memory element according to Embodiment 1 of the
  • FIG. 5 is a graph showing the correlation between the difference between the standard electrode potential of the transition metal constituting the oxygen-deficient transition metal oxide and the standard electrode potential of the electrode material, and the resistance change of the oxygen-deficient metal oxide.
  • FIG. 6 is a diagram showing a change in resistance with respect to the number of electric pulses applied when Pt is used for the second electrode in a nonvolatile memory element using an oxygen-deficient tantalum oxide.
  • FIG. 7 is a diagram showing a change in resistance with respect to the number of electric pulses applied when Ir is used for the second electrode in a nonvolatile memory element using an oxygen-deficient tantalum oxide.
  • FIG. 8 is a diagram showing a change in resistance with respect to the number of electric pulses applied when Ag is used for the second electrode in a nonvolatile memory element using an oxygen-deficient tantalum oxide.
  • FIG. 9 is a diagram showing a change in resistance with respect to the number of electric pulses applied when Cu is used for the second electrode in a nonvolatile memory element using an oxygen-deficient tantalum oxide.
  • FIG. 10 is a diagram showing a change in resistance with respect to the number of electric pulses applied when Ni is used for the second electrode in a nonvolatile memory element using an oxygen-deficient tantalum oxide.
  • FIG. 11 is a diagram showing a change in resistance with respect to the number of electric pulses applied when W is used for the second electrode in a nonvolatile memory element using an oxygen-deficient tantalum oxide.
  • FIG. 12 is a diagram showing a change in resistance with respect to the number of electric pulses applied when Ta is used for the second electrode in a nonvolatile memory element using an oxygen-deficient tantalum oxide.
  • FIG. 13 is a diagram showing a change in resistance with respect to the number of electric pulses applied when Ti is used for the second electrode in a nonvolatile memory element using an oxygen-deficient tantalum oxide.
  • FIG. 14 is a diagram showing a change in resistance with respect to the number of electric pulses applied when Al is used for the second electrode in a nonvolatile memory element using an oxygen-deficient tantalum oxide.
  • FIG. 15 is a diagram showing a change in resistance with respect to the number of electric pulses applied when Pt is used for the second electrode in a nonvolatile memory element using oxygen-deficient hafnium oxide.
  • FIG. 16 is a diagram showing a change in resistance with respect to the number of electric pulses applied when Cu is used for the second electrode in a nonvolatile memory element using an oxygen-deficient hafnium oxide.
  • FIG. 17 is a diagram showing a change in resistance with respect to the number of electric pulses applied when W is used for the second electrode in a nonvolatile memory element using oxygen-deficient hafnium oxide.
  • FIG. 18 is a diagram showing a change in resistance with respect to the number of electric pulses applied when Ta is used for the second electrode in a nonvolatile memory element using oxygen-deficient hafnium oxide.
  • FIG. 19 is a diagram showing a change in resistance with respect to the number of electric pulses applied when Hf is used for the second electrode in a nonvolatile memory element using oxygen-deficient hafnium oxide.
  • FIG. 20 is a diagram showing a change in resistance with respect to the number of electric pulses applied when Ti is used for the second electrode in a nonvolatile memory element using oxygen-deficient hafnium oxide.
  • FIG. 21 is a diagram showing a change in resistance with respect to the number of electric pulses applied when Al is used for the second electrode in a nonvolatile memory element using oxygen-deficient hafnium oxide.
  • FIG. 22 is a graph showing the electrical characteristics of a single nonvolatile memory element for experiment when the thickness of the second tantalum oxide layer is 3 nm.
  • FIG. 23 is a graph showing the electrical characteristics of the experimental nonvolatile memory element when the thickness of the second tantalum oxide layer is 3 nm and the load element is connected.
  • FIG. 24 is a graph showing the relationship between the initial resistance value of the variable resistance layer and the break voltage when the thickness ⁇ of the second tantalum oxide layer is changed, and the relationship between the initial resistance value and the leakage current.
  • FIG. 25 is a block diagram showing a configuration of the nonvolatile memory device according to Embodiment 2 of the present invention.
  • FIG. 26 is a perspective view showing the configuration (configuration corresponding to 4 bits) of part A in FIG.
  • FIG. 27 is a cross-sectional view showing a configuration of a nonvolatile memory element included in the nonvolatile memory device according to Embodiment 2 of the present invention.
  • FIG. 28 is a timing chart showing an operation example of the nonvolatile memory device according to Embodiment 2 of the present invention.
  • FIG. 29 is a block diagram showing a configuration of the nonvolatile memory device according to Embodiment 3 of the present invention.
  • FIG. 30 is a cross-sectional view showing the configuration (configuration corresponding to 2 bits) of part C in FIG.
  • FIG. 31 is a timing chart showing an operation example of the nonvolatile memory device according to Embodiment 3 of the present invention.
  • FIG. 1 is a cross-sectional view showing a configuration of a nonvolatile memory element 100 according to Embodiment 1 of the present invention.
  • the nonvolatile memory element 100 is a variable resistance nonvolatile memory element, and includes a substrate 101, an oxide layer 102 formed on the substrate 101, and an oxide layer 102.
  • the first electrode layer 103, the second electrode layer 105, and the variable resistance layer 104 sandwiched between the first electrode layer 103 and the second electrode layer 105 are provided.
  • the first electrode layer 103 and the second electrode layer 105 are electrically connected to the resistance change layer 104.
  • the resistance change layer 104 is a bipolar resistance change layer that reversibly transitions between a high resistance state and a low resistance state based on the polarity of the voltage applied between the first electrode layer 103 and the second electrode layer 105.
  • a first oxide layer 104a made of tantalum oxide having a composition represented by TaO x , and titanium oxide formed on the first oxide layer 104a and having a composition represented by TiO 2
  • the second oxide layer 104b made of a material.
  • the first oxide layer 104a (TaO x in this embodiment) and the second oxide layer 104b (TiO 2 in this embodiment) satisfy the following relationship. That is, the standard electrode potential of the transition metal (second transition metal) included in the second oxide layer 104b is greater than the standard electrode potential of the transition metal (first transition metal) included in the first oxide layer 104a. Is also small. Further, (1) the dielectric constant of the second oxide layer 104b is larger than the dielectric constant of the first oxide layer 104a, and (2) the band gap of the second oxide layer 104b is the first oxidation. At least one of smaller than the band gap of the material layer 104a is satisfied. In the present embodiment, both (1) and (2) are satisfied. This significance will be described later.
  • the nonvolatile memory element 100 is connected to the load element when it is in an initial state having a resistance value higher than the resistance value of the nonvolatile memory element 100 when the resistance change layer 104 is in the high resistance state.
  • the initial break is applied in which the voltage is applied, the high-resistance state and the low-resistance state can be changed to a state capable of transition.
  • a pulse voltage satisfying a predetermined condition is applied between the first electrode layer 103 and the second electrode layer 105 by an external power source.
  • the relative potential (voltage) of the second electrode layer 105 with respect to the first electrode layer 103 is defined as a voltage applied between the first electrode layer 103 and the second electrode layer 105. Therefore, the applied voltage at which the potential of the second electrode layer 105 is higher than that of the first electrode layer 103 is a positive applied voltage, while the applied voltage at which the potential of the second electrode layer 105 is lower than that of the first electrode layer 103 is negative. Applied voltage.
  • the substrate 101 for example, a silicon single crystal substrate or a semiconductor substrate can be used. However, the present invention is not limited to this. Since the resistance change layer 104 can be formed at a relatively low substrate temperature, the resistance change layer 104 can be formed on a resin material or the like.
  • the first electrode layer 103 and the second electrode layer 105 correspond to the first electrode and the second electrode according to the present invention, respectively.
  • Au gold
  • Pt platinum
  • Ir iridium
  • Pd Palladium
  • Ag silver
  • Ni nickel
  • W tungsten
  • Cu copper
  • TaN tantalum nitride
  • the nonvolatile memory element configured as described above can be manufactured as follows.
  • 2 (a) to 2 (c) are cross-sectional views showing manufacturing steps of the nonvolatile memory element according to Embodiment 1 of the present invention.
  • an oxide layer 102 having a thickness of 200 nm is formed on a substrate 101 made of single crystal silicon by a thermal oxidation method. Then, a TaN thin film having a thickness of 100 nm as the first electrode layer 103 is formed on the oxide layer 102 by a sputtering method. After that, a first oxide layer 104a is formed on the first electrode layer 103 by a reactive sputtering method using a Ta target.
  • the first oxide layer 104a was deposited under the conditions described below. That is, after setting the substrate in the sputtering apparatus, the inside of the sputtering apparatus is evacuated to about 8 ⁇ 10 ⁇ 6 Pa. Then, using tantalum as a target, the power is set to 1.6 kW, argon gas is supplied at 34 sccm, oxygen gas is supplied at 21 sccm, the pressure in the sputtering apparatus is maintained at 0.17 Pa, and sputtering is performed for 20 seconds. As a result, a first oxide layer having a resistivity of 6 m ⁇ cm and an oxygen content of about 61 at% (TaO 1.6 ) can be deposited to 30 nm.
  • TaO 1.6 is an example of the first oxide layer according to the present invention, but the first oxide layer according to the present invention is not limited to such a material, and as described above.
  • the dielectric constant of the second oxide layer 104b is larger than the dielectric constant of the first oxide layer 104a; and (2) the band gap of the second oxide layer 104b is the first oxide.
  • Any oxide layer may be used as long as at least one of the layers 104a smaller than the band gap is satisfied.
  • TaO x (0.8 ⁇ x ⁇ 1.9) may be used.
  • a second oxide layer 104b is formed on the first oxide layer 104a by a sputtering method using TiO 2 as a target.
  • an oxide layer with a thickness of 3 nm is deposited to form the second oxide layer 104b.
  • an Ir thin film having a thickness of 150 nm as the second electrode layer 105 is formed on the second oxide layer 104b by a sputtering method.
  • a photoresist pattern 106 is formed by a photoresist process, and an element region 107 is formed by dry etching (see FIG. 2C).
  • the element region 107 has a square shape with a side of 0.5 ⁇ m.
  • FIG. 3 is a diagram illustrating an operation example of the nonvolatile memory element according to the present embodiment when information is written.
  • the resistance value of the layer 104 changes. That is, when a negative voltage pulse (voltage E1 volt, pulse width 100 ns) is applied between the electrodes, the resistance value of the resistance change layer 104 decreases from the high resistance value Rb to the low resistance value Ra. That is, a transition from the high resistance state to the low resistance state.
  • the resistance value of the resistance change layer 104 increases from the low resistance value Ra to the high resistance value Rb. That is, a transition from the low resistance state to the high resistance state.
  • the high resistance value Rb is assigned to information “0”, and the low resistance value Ra is assigned to information “1”. Therefore, in the present embodiment, information “0” is written by applying a positive voltage pulse between the electrodes so that the resistance value of the resistance change layer 104 becomes the high resistance value Rb. Information “1” is written by applying a negative voltage pulse between the electrodes such that the resistance value of the change layer 104 becomes the low resistance value Ra.
  • FIG. 4 is a diagram illustrating an operation example of the nonvolatile memory element 100 according to the present embodiment when information is read.
  • the read voltage E3 volts (
  • a current is output corresponding to the resistance value of the resistance change layer 104, and the written information (“0” or “1”) can be read by detecting the output current value.
  • the output current value Ia corresponds to the low resistance value Ra
  • the output current value Ib corresponds to the high resistance value Rb. Therefore, when the output current value Ia is detected, the information “1” is displayed. When the output current value Ib is detected, the information “0” is read out.
  • the resistance change layer 104 includes the stacked structure of the first oxide layer 104a and the second oxide layer 104b, and the first oxide layer 104a includes TaO. x , the second oxide layer 104b is composed of TiO 2 respectively.
  • the materials of the first oxide layer 104a and the second oxide layer 104b are not limited to this.
  • what is suitable as a material of the 1st oxide layer 104a and the 2nd oxide layer 104b is demonstrated.
  • the second oxide layer 104b has a higher resistivity than the first oxide layer 104a. This is because the following reasoning holds for the mechanism of resistance change of the resistance change layer in the nonvolatile memory element.
  • the resistance change of the variable resistance layer in the nonvolatile memory element is not clearly understood at the present time, it is presumed that it is caused by the movement of oxygen atoms at the interface between the electrode and the variable resistance layer.
  • the second oxide layer 104b in this embodiment is considered to play a role of effectively applying a voltage in the vicinity of the interface. More specifically, it is considered that the resistance change phenomenon is caused by oxygen atoms gathering or diffusing due to an electric field near the interface between the second electrode layer and the resistance change layer.
  • a positive voltage is applied to the second electrode layer (the case where a positive voltage is applied with reference to the first electrode layer is referred to as a “positive voltage”), the oxygen atoms are negatively charged.
  • the resistance variable layer has a high resistance.
  • a negative voltage is applied (a negative voltage is applied with reference to the first electrode layer is referred to as a “negative voltage”)
  • oxygen atoms diffuse into the resistance change layer and the resistance value decreases.
  • a high resistance layer exists at the interface (more precisely, the resistance change layer side interface)
  • a large voltage is applied to this layer, so that oxygen is injected into the high resistance layer.
  • this high resistance layer approaches the insulator.
  • the resistance of the resistance change layer itself increases, and a high resistance state is obtained.
  • the voltage is evenly applied to the resistance change layer, and a layer close to an insulator is hardly formed near the interface. As a result, the resistance change phenomenon hardly occurs.
  • the second oxide layer 104b having a higher resistivity than the first oxide layer 104a is provided at the interface between the second electrode layer 105 and the resistance change layer 104. Is desirable.
  • the second transition metal contained in the second oxide layer 104b is more likely to be oxidized than the first transition metal contained in the first oxide layer 104a. desirable.
  • the second oxide layer 104b is composed of a second transition metal that is more easily oxidized than the first transition metal, when a positive voltage is applied between the first electrode layer 103 and the second electrode layer 105, Since the resistance of the second oxide layer 104b is easily increased, the resistance change layer 104 can be easily in a high resistance state.
  • the standard electrode potential of the second transition metal included in the second oxide layer 104b is higher than the standard electrode potential of the first transition metal included in the first oxide layer 104a. It is desirable that the particle size is small (that is, easily oxidized). For the same reason, it can be said that the oxygen deficiency of the second oxide layer 104b is preferably smaller than the oxygen deficiency of the first oxide layer 104a.
  • the degree of oxygen deficiency is the degree (ratio) of oxygen deficiency in the stoichiometric composition.
  • the standard electrode potential of the second transition metal contained in the second oxide layer 104b is smaller than the standard electrode potential of the first transition metal contained in the first oxide layer 104a.
  • the degree of oxidation is naturally higher in the second oxide layer 104b than in the first oxide layer 104a. Therefore, for example, even if the thermal budget is enlarged during the semiconductor manufacturing process, there is an advantage that the collapse of the oxygen concentration profile in the resistance change film can be suppressed. This brings about an effect of facilitating application to a cross-point type non-volatile memory device having a multi-layered structure aiming at large capacity.
  • the breakdown field strength (Breakdown Strength) of the oxide layer and the dielectric constant There is a correlation that the strength of the dielectric breakdown field decreases as the dielectric constant increases. Therefore, in order to reduce the break voltage of the nonvolatile memory element, the dielectric constant of the second oxide layer 104b is set to be the dielectric constant of the first oxide layer 104a in order to reduce the strength of the breakdown electric field. It can be said that it is desirable to be larger than the rate. Thereby, a nonvolatile memory element capable of performing a stable resistance change operation with a lower break voltage can be realized.
  • the reason why the break voltage is lowered by reducing the strength of the dielectric breakdown electric field of the second oxide layer 104b is as follows. That is, the initial state of the nonvolatile memory element having the variable resistance layer formed of the laminated structure of the transition metal oxide layer is a high resistance state having an extremely high resistance value determined by the second oxide layer 104b having a high resistivity. is there. Therefore, in order to perform the initial break that destroys the initial state, it is necessary to perform dielectric breakdown on the second oxide layer 104b. Therefore, by reducing the strength of the dielectric breakdown electric field of the second oxide layer 104b, the voltage required for the initial break, that is, the break voltage is lowered.
  • the band gap of the second oxide layer 104b is less than the band of the first oxide layer 104a in order to reduce the strength of the breakdown electric field. It can be said that it is desirable to be smaller than the gap.
  • the dielectric constant of the second oxide layer 104b is higher than the dielectric constant of the first oxide layer 104a.
  • at least one of the band gap of the second oxide layer 104b is smaller than the band gap of the first oxide layer 104a is selected. ing.
  • Table 1 summarizes the data on physical properties of various transition metals.
  • the first oxide layer 104a is composed of an oxide such as TaO x , NiO x , WO x , CoO x, or FeO x
  • the oxide layer 104b is preferably made of an oxide such as TiO 2 , SrTiO 3, or Nb 2 O 5 .
  • the first oxide layer 104a is TaO x (0.8 ⁇ x ⁇ 1.9)
  • TiO 2 , SrTiO 3 and Nb 2 O 5 are preferable as the second oxide layer 104b.
  • the standard electrode potential of the second transition metal constituting the second oxide layer 104b is the standard of the first transition metal constituting the first oxide layer 104a.
  • the dielectric constant of the second oxide layer 104b is larger than the dielectric constant of the first oxide layer 104a, and (2) the band of the second oxide layer 104b. This is because the gap is smaller than the band gap of the first oxide layer 104a.
  • the physical property value of TaO x (0.8 ⁇ x ⁇ 1.9) is expected to be substantially the same as or slightly smaller than the physical property value of Ta 2 O 5 in Table 1 above.
  • the resistance value of the entire resistance change layer 104 can be controlled by the thicknesses of the first oxide layer 104a and the second oxide layer 104b. Therefore, when considering these thicknesses, if the thickness of the second oxide layer 104b, which is a high resistance layer, is too large, the initial resistance value of the resistance change layer 104 becomes high, so that the resistance change can be started. Inconveniences such as difficulty and initial break become essential. On the other hand, if the thickness is too small, there may be a problem that a stable resistance changing operation cannot be obtained. Considering the above, it can be said that at least the thickness of the second oxide layer 104b is desirably smaller than the thickness of the first oxide layer 104a.
  • the inventors conducted the following experiment using two types of oxygen-deficient transition metal oxides as a resistance change layer.
  • the oxygen-deficient transition metal oxide means that when the transition metal is A and the oxide is represented by AO x , x is represented by a non-stoichiometric ratio, and oxygen is derived from the stoichiometric composition. This refers to the missing oxide.
  • a first sample element formed by sandwiching an oxygen-deficient tantalum oxide between a lower electrode (first electrode) and an upper electrode (second electrode), and a second sample formed by sandwiching an oxygen-deficient hafnium oxide in the same manner.
  • Two sample elements were produced.
  • the material of the first electrode was fixed to W (tungsten), and the material of the second electrode was changed to a plurality of types of materials shown in Tables 3 and 4 below.
  • Table 3 shows the configuration of the first sample element
  • Table 4 shows the configuration of the second sample element.
  • the reason why the material of the first electrode is fixed to W is that W is relatively resistant to oxidation, is a stable material, and is relatively easy to process.
  • the inventors examined the state of resistance change of the first and second sample elements.
  • the voltage pulse when increasing the resistance is +1.8 to +2.5 V, 100 ns and the resistance is decreased
  • the voltage pulse of ⁇ 1.3V to ⁇ 1.6V was set to 100 ns.
  • the voltage pulse when the resistance is increased is +1.6 to +1.9 V and 100 ns
  • the voltage pulse when the resistance is decreased is ⁇ 1.1 V to ⁇ 1.3 V. 100 ns.
  • FIGS. The measurement results for the elements shown in Tables 3 and 4 are shown in FIGS. These measurement results are collectively shown in FIG. That is, in FIG. 5, a total of 16 graphs shown in FIGS. 6 to 21 are reduced and arranged.
  • Figure 5 is a difference between the standard electrode potential E E standard electrode potential E T and the electrode material of a transition metal forming the oxygen-deficient transition metal oxide (E E -E T), an oxygen-deficient metal oxide It is a graph which shows a correlation with resistance change (small each graph arrange
  • the seven graphs arranged in the upper part of FIG. 5 show the correlation regarding the second sample element (HfO x ), and the nine graphs arranged in the lower part of FIG. 5 relate to the first sample element (TaO x ). Show correlation.
  • FIGS. 6 to 14 are graphs showing the state of resistance change according to the number of voltage pulse applications in the first sample element. More specifically, FIGS.
  • FIG. 15 to FIG. 21 are graphs showing the state of resistance change according to the number of voltage pulse applications in the second sample element. More specifically, FIGS. 15 to 21 show Hf—A (platinum), Hf—B (copper), Hf—C (tungsten), Hf—D (tantalum), Hf—E (hafnium), Hf. The measurement results for -F (titanium) and Hf-G (aluminum) are shown. Note that the second electrode material and (E E -E T ) are shown at the top of the graphs in FIGS.
  • the change width was as follows.
  • the relationship between the standard electrode potential of the transition metal constituting the oxygen-deficient transition metal oxide and the standard electrode potential of the electrode material becomes important.
  • the transition metal is easily oxidized (that is, the standard electrode potential is small) compared to the electrode material. It can be said that a stable resistance change operation can be realized by using an oxide layer containing a metal at the electrode side interface of the resistance change layer. Therefore, it is desirable that the standard electrode potential of the second electrode is larger than the standard electrode potential of the transition metal that constitutes the second oxide layer, and the standard electrode of the transition metal that constitutes the first oxide layer. It is desirable that it be greater than the potential.
  • the second electrode layer 105 is formed using a material having a higher standard electrode potential than the transition metal included in the second oxide layer 104b.
  • a material having a standard electrode potential larger than this specifically W, Cu, and Ni. Etc. can be used.
  • W, Cu, Ni, and the like do not have a large standard electrode potential as compared with noble metal-based electrode materials such as Au, Pt, and Ir, but the standard electrode potential of Ti is relatively small. It can be used as a material. Since W, Cu, Ni, and the like are low-cost materials that are compatible with semiconductor processes, the manufacturing cost of the nonvolatile memory element 100 can be reduced.
  • the nonvolatile memory element may be used by being connected in series to a load element such as a fixed resistor, a transistor, and a diode (specific examples are described in Embodiments 2 and 3 to be described later).
  • a load element such as a fixed resistor, a transistor, and a diode (specific examples are described in Embodiments 2 and 3 to be described later).
  • the present inventors conducted the following experiment in order to confirm the above problem.
  • This experimental nonvolatile memory element (hereinafter referred to as experimental element) was fabricated as follows. First, a TaN thin film as a first electrode layer is formed on an oxide layer formed on a silicon substrate, and a first tantalum oxide layer is formed thereon by reactive sputtering using a Ta target. Formed. Next, a second tantalum oxide layer having an oxygen content higher than that of the first tantalum oxide layer was formed by oxidizing the outermost surface of the first tantalum oxide layer with oxygen plasma. Then, an Ir thin film as a second electrode layer was formed on the second tantalum oxide layer by a sputtering method. Experiments in which the first electrode layer, the first tantalum oxide layer (TaO 1.6 ), the second tantalum oxide layer (TaO 2.47 ), and the second electrode layer are stacked through such a process. An element was produced.
  • variable resistance layer is composed of the first tantalum oxide layer and the second tantalum oxide layer having a higher resistance than the first tantalum oxide layer.
  • 22 (a) and 22 (b) are graphs showing electrical characteristics of the experimental element alone (that is, when no load element is connected) when the thickness of the second tantalum oxide layer is 3 nm.
  • 22A shows current (vertical axis) -voltage (horizontal axis) characteristics
  • FIG. 22B shows resistance (vertical axis) -voltage (horizontal axis) characteristics.
  • 23 (a) and 23 (b) are graphs showing the electrical characteristics of the experimental element when the thickness is 3 nm and the load element is connected.
  • FIG. 23 (a) shows the current.
  • FIG. 23B shows the resistance (vertical axis) -voltage (horizontal axis) characteristics.
  • the resistance value measured at 50 mV is shown.
  • the resistance change is started by applying a voltage of about ⁇ 1V. That is, in this case, the break voltage is about ⁇ 1V.
  • the break voltage is about ⁇ 1V.
  • FIGS. 23A and 23B when a load element (here, 1 k ⁇ resistor) is connected to the experimental element, the applied voltage is up to about ⁇ 3.5V. The resistance change will not start unless the value is raised. That is, in this case, the break voltage is about ⁇ 3.5V.
  • FIG. 24 is a graph showing the relationship between the initial resistance value of the variable resistance layer and the break voltage when the thickness d of the second tantalum oxide layer is changed, and the relationship between the initial resistance value and the leakage current. .
  • the horizontal axis represents the initial resistance value of the variable resistance layer measured at an applied voltage of 100 mV
  • the vertical axis represents the break voltage or the leak current flowing during the break.
  • the x plotted points indicate the break voltage when the load element is connected to the experimental element
  • the black square plot points indicate the break voltage when the experimental element alone
  • the triangular plot points indicate The current values of the leak currents (both when the load element is connected to the experimental element and when the experimental element alone is common) are shown.
  • the break voltage decreases as the thickness d of the second tantalum oxide layer decreases. This seems to indicate that the onset of resistance change is dominated by the electric field.
  • the load element is connected to the experimental element ( ⁇ plotted point)
  • the load element is connected up to about 4.5 nm when the thickness d of the second tantalum oxide layer is decreased.
  • the break voltage of the experimental element alone that has not been reduced is about the same value, but if it is made thinner than 4.5 nm, the leakage current increases and the break voltage becomes larger than that of the experimental element alone. I understand that. This indicates that if the leakage current can be reduced, it is possible to suppress the increase of the break voltage and start the resistance change at a low voltage even when the load element is connected.
  • the break voltage can be lowered by selecting the material of the resistance change layer and the electrode as described above, so that such a request can be met. .
  • conduction band offset In Table 1 above, the conduction band offset (eV) with respect to Si is described as one of the physical property values of the material. As described above, when the nonvolatile memory element is connected to the load element, a leakage current is generated, but by configuring the second oxide layer using a material having a large conduction band offset value, The leakage current can be reduced.
  • the second oxide layer 104b is preferably composed of Ti, Sr, Nb, or the like having a relatively large value rather than Ta having a relatively small conduction band offset. . That is, as a metal constituting the second oxide layer 104b, Ti, Sr, and Nb are not only from the viewpoint of the dielectric constant and band gap of the second oxide layer 104b but also from the viewpoint of the conduction band offset. It turns out that it is preferable.
  • the nonvolatile memory element 100 according to Embodiment 1 described above can be applied to various types of nonvolatile memory devices.
  • the non-volatile memory device according to the second embodiment is a non-volatile memory device including the non-volatile memory element according to the first embodiment.
  • the non-volatile memory device according to the second embodiment is the same as that of the first embodiment at the intersection (three-dimensional intersection) between the word line and the bit line. This is a so-called cross-point type in which such a nonvolatile memory element is interposed.
  • FIG. 25 is a block diagram showing a configuration of the nonvolatile memory device 200 according to Embodiment 2 of the present invention.
  • FIG. 26 is a perspective view showing the configuration of part A in FIG. 25 (physical configuration of memory cells for 4 bits).
  • the nonvolatile memory device 200 includes a memory main body 201 on a semiconductor substrate.
  • the memory main body 201 includes a memory cell array 202, a row selection circuit / driver, and the like. 203, a column selection circuit / driver 204, a write circuit 205 for writing information, a sense amplifier 206 for detecting the amount of current flowing through the selected bit line and discriminating data “1” or “0”; And a data input / output circuit 207 for performing input / output processing of input / output data via a terminal DQ.
  • the nonvolatile memory device 200 further includes an address input circuit 208 that receives an address signal input from the outside, and a control circuit 209 that controls the operation of the memory body 201 based on the control signal input from the outside. I have.
  • the memory cell array 202 includes a plurality of word lines WL0, WL1, WL2,... Formed in parallel with each other on a semiconductor substrate and these word lines WL0, WL1, WL2,.
  • memory cells M111, M112, M113, M121, M122, M123 provided in a matrix corresponding to the intersections of these word lines WL0, WL1, WL2,... And bit lines BL0, BL1, BL2,. , M131, M132, M133,... (Hereinafter referred to as “memory cells M111, M112,...”).
  • the memory cells M111, M112,... Correspond to the nonvolatile memory element 100 according to the first embodiment. However, in the present embodiment, these memory cells M111, M112,... Have a current suppressing element connected in series to the nonvolatile memory element 100, as will be described later.
  • the address input circuit 208 receives an address signal from an external circuit (not shown), outputs a row address signal to the row selection circuit / driver 203 based on the address signal, and outputs a column address signal to the column selection circuit / driver 204. Output to.
  • the address signal is a signal indicating the address of a specific memory cell selected from among the plurality of memory cells M111, M112,... Constituting the memory cell array 202.
  • the row address signal is a signal indicating a row address among the addresses indicated by the address signal
  • the column address signal is also a signal indicating a column address.
  • the control circuit 209 In the information write cycle, the control circuit 209 outputs a write signal instructing application of a write voltage to the write circuit 205 according to the input data Din input to the data input / output circuit 207. On the other hand, in the information read cycle, the control circuit 209 outputs a read signal for instructing a read operation to the column selection circuit / driver 204.
  • the row selection circuit / driver 203 receives the row address signal output from the address input circuit 208, selects one of the plurality of word lines WL0, WL1, WL2,... According to the row address signal, A predetermined voltage is applied to the selected word line. That is, the row selection circuit / driver 203 is an example of a selection circuit that selects at least one nonvolatile memory element from the nonvolatile memory elements included in the memory cell array 202.
  • the column selection circuit / driver 204 receives the column address signal output from the address input circuit 208 and selects one of the plurality of bit lines BL0, BL1, BL2,... According to the column address signal. Then, a write voltage or a read voltage is applied to the selected bit line. That is, the column selection circuit / driver 204 is an example of a selection circuit that selects at least one nonvolatile memory element from the nonvolatile memory elements included in the memory cell array 202.
  • the write circuit 205 When the write circuit 205 receives the write signal output from the control circuit 209, the write circuit 205 outputs a signal instructing the row selection circuit / driver 203 to apply a voltage to the selected word line, and the column selection circuit / A signal instructing the driver 204 to apply a write voltage to the selected bit line is output.
  • the writing circuit 205 writes data by applying a voltage to a nonvolatile memory element (here, a memory cell) selected by the selection circuit (row selection circuit / driver 203 and column selection circuit / driver 204). It is an example of a circuit.
  • the sense amplifier 206 detects the amount of current flowing through the selected bit line to be read in the information read cycle, and determines data “1” or “0”.
  • the output data DO obtained as a result is output to an external circuit via the data input / output circuit 207. That is, the sense amplifier 206 is a read circuit that reads data by detecting the resistance value of the nonvolatile memory element that constitutes the memory cell selected by the selection circuit (row selection circuit / driver 203 and column selection circuit / driver 204). It is an example.
  • a sense amplifier instead of the sense amplifier 206, a sense amplifier configured to form an RC circuit with the resistance value of the nonvolatile memory element and the capacitance formed in the read circuit and measure the time constant thereof. May be used.
  • nonvolatile memory device having a multilayer structure by stacking the memory cell arrays 202 in the nonvolatile memory device 200 according to the present embodiment shown in FIGS. 25 and 26 three-dimensionally.
  • multi-layered memory cell array configured as described above, it is possible to realize an ultra-large capacity nonvolatile memory.
  • FIG. 27 is a cross-sectional view showing a configuration of a memory cell (here, a nonvolatile memory element 210 including a current suppressing element as a load element) included in the nonvolatile memory device 200 according to Embodiment 2 of the present invention. Note that FIG. 27 shows a configuration in B part (one cross point) in FIG.
  • the nonvolatile memory element 210 included in the nonvolatile memory device according to the present embodiment includes an upper wiring 211 (corresponding to the lower wiring 212 (corresponding to the word line WL1 in FIG. 26) that is a copper wiring.
  • the lower electrode 217, the current suppressing element 216, the internal electrode 215, the resistance change layer 214, and the upper electrode 213 are stacked in this order. Configured.
  • the internal electrode 215, the resistance change layer 214, and the upper electrode 213 are the first electrode layer 103, the resistance change layer 104, and the second electrode in the nonvolatile memory element 100 according to Embodiment 1 shown in FIG. Each corresponds to the layer 105. Therefore, the resistance change layer 214 is formed in the same manner as the resistance change layer 104 in the first embodiment.
  • the current suppression element 216 is an example of a load element connected in series with the resistance change layer 214 via the internal electrode 215.
  • the current suppressing element 216 is an element having a function of suppressing a current typified by a diode, and exhibits a nonlinear current characteristic with respect to a voltage. Further, the current suppressing element 216 has a bidirectional current characteristic with respect to the voltage, and conducts at a predetermined threshold voltage Vf (for example, +1 V or more or ⁇ 1 V or less with respect to one electrode). It is configured.
  • FIG. 28 is a timing chart showing an operation example of the nonvolatile memory device 200 according to Embodiment 2 of the present invention.
  • the information “0” is assigned to the information when the resistance change layer 214 is in the low resistance state.
  • a voltage value VP in FIG. 28 indicates a pulse voltage necessary for resistance change of a memory cell formed of a nonvolatile memory element and a current suppressing element.
  • Vf the relationship of VP / 2 ⁇ threshold voltage Vf is satisfied. This is because the leakage current flowing around the unselected memory cells can be suppressed. As a result, it is possible to suppress an excessive current supplied to the memory cell that does not need to write information, and to further reduce the current consumption. Further, there is an advantage that unintentional shallow writing (generally referred to as disturb) to unselected memory cells is suppressed.
  • a write cycle time that is a time required for one write cycle is indicated by tW
  • a read cycle time that is a time required for one read cycle is indicated by tR.
  • a pulse voltage VP having a pulse width tP is applied to the word line WL0, and a voltage of 0V is similarly applied to the bit line BL0 according to the timing.
  • a write voltage for writing information “1” to the memory cell M111 is applied, and as a result, the resistance change layer of the memory cell M111 has a high resistance. That is, information “1” is written in the memory cell M111.
  • a voltage of 0V having a pulse width tP is applied to the word line WL1, and the pulse voltage VP is similarly applied to the bit line BL1 according to the timing.
  • a write voltage for writing information “0” to M122 is applied, and as a result, the resistance change layer of the memory cell M122 has a low resistance. That is, information “0” is written in the memory cell M122.
  • a pulse voltage having a smaller amplitude than the pulse at the time of writing and having a value larger than 0V and smaller than VP / 2 is applied to the word line WL0.
  • a pulse voltage having a smaller amplitude than the pulse at the time of writing and having a value larger than VP / 2 and smaller than VP is applied to the bit line BL0.
  • the same voltage as that for the read cycle for the previous memory cell M111 is applied to the word line WL1 and the bit line BL1.
  • a current corresponding to the resistance value of the resistance change layer 214 of the memory cell M122 whose resistance has been reduced is output, and information “0” is read by detecting the output current value.
  • the nonvolatile memory device 200 includes the nonvolatile memory element 210 that can perform a good resistance change operation like the nonvolatile memory element 100 according to the first embodiment, and thus realizes stable operation. can do.
  • the non-volatile memory device is a non-volatile memory device including the non-volatile memory element 100 according to the first embodiment, and the unit memory cell includes one transistor and one non-volatile memory unit.
  • FIG. 29 is a block diagram showing a configuration of the nonvolatile memory device 300 according to Embodiment 3 of the present invention.
  • FIG. 30 is a cross-sectional view showing the configuration of part C in FIG. 29 (physical configuration of a memory cell for 2 bits).
  • the nonvolatile memory device 300 includes a memory main body 301 on a semiconductor substrate.
  • the memory main body 301 includes a memory cell array 302, a row selection circuit, A driver 303, a column selection circuit 304, a writing circuit 305 for writing information, a sense amplifier 306 for detecting the amount of current flowing through the selected bit line and determining data “1” or “0”; And a data input / output circuit 307 for performing input / output processing of input / output data via the terminal DQ.
  • the nonvolatile memory device 300 includes a cell plate power supply (VCP power supply) 308, an address input circuit 309 that receives an address signal input from the outside, and a control signal input from the outside. And a control circuit 310 for controlling the operation.
  • VCP power supply cell plate power supply
  • the memory cell array 302 includes a plurality of word lines WL0, WL1, WL2,... And bit lines BL0, BL1, BL2,... , WL1, WL2,... And bit lines BL0, BL1, BL2,..., And a plurality of transistors (for example, NMOS transistors) T11, T12, T13, T21, T22, T23, T31, T32, respectively. , T33,... (Hereinafter referred to as “transistors T11, T12,...”) And a plurality of memory cells M211, M212, M213, M221, M222, M223 provided one-to-one with the transistors T11, T12,. M231, M232, M233 (hereinafter referred to as “memory cells M211, M212,...”) ) And a.
  • transistors for example, NMOS transistors
  • the memory cell array 302 includes a plurality of plate lines PL0, PL1, PL2,... Arranged in parallel to the word lines WL0, WL1, WL2,.
  • bit line BL0 is arranged above the word lines WL0 and WL1, and plate lines PL0 and PL1 are arranged between the word lines WL0 and WL1 and the bit line BL0.
  • the memory cells M211, M212,... Correspond to the nonvolatile memory element 100 according to the first embodiment. More specifically, the nonvolatile memory element 313 in FIG. 30 corresponds to the memory cells M211, M212,... In FIG. 29.
  • the nonvolatile memory element 313 includes the upper electrode 314, the resistance change layer 315, and the lower electrode. 316. Then, the upper electrode 314, the resistance change layer 315, and the lower electrode 316 are the first electrode layer 103, the resistance change layer 104, and the second electrode in the nonvolatile memory element 100 according to Embodiment 1 shown in FIG. Each corresponds to the electrode layer 105. Therefore, resistance change layer 315 is formed in the same manner as resistance change layer 104 in the first embodiment.
  • reference numeral 317 indicates a plug layer
  • reference numeral 318 indicates a metal wiring layer
  • reference numeral 319 indicates a source and drain region.
  • the gates of the transistors T11, T21, T31,... are on the word line WL0
  • the gates of the transistors T12, T22, T32, ... are on the word line WL1
  • the gates of the transistors T13, T23, T33,. Each is connected.
  • the sources of the transistors T11, T12,... are connected to the memory cells M211, M212,.
  • the memory cells M212, M222, M232,... are connected to the plate line PL1, and the memory cells M213, M223, M233,. ing.
  • the address input circuit 309 receives an address signal from an external circuit (not shown), outputs a row address signal to the row selection circuit / driver 303 based on the address signal, and outputs a column address signal to the column selection circuit 304.
  • the address signal is a signal indicating the address of a specific memory cell selected from among the plurality of memory cells M211, M212,... Constituting the memory cell array 302.
  • the row address signal is a signal indicating a row address among the addresses indicated by the address signal
  • the column address signal is a signal indicating a column address among the addresses indicated by the address signal.
  • control circuit 310 In the information write cycle, the control circuit 310 outputs a write signal instructing application of a write voltage to the write circuit 305 in accordance with the input data Din input to the data input / output circuit 307. On the other hand, in the information read cycle, the control circuit 310 outputs a read signal instructing application of a read voltage to the column selection circuit 304.
  • the row selection circuit / driver 303 receives the row address signal output from the address input circuit 309, selects one of the plurality of word lines WL0, WL1, WL2,... According to the row address signal, A predetermined voltage is applied to the selected word line. That is, the row selection circuit / driver 303 is an example of a selection circuit that selects at least one nonvolatile memory element from the nonvolatile memory elements included in the memory cell array 302.
  • the column selection circuit 304 receives the column address signal output from the address input circuit 309, selects one of the plurality of bit lines BL0, BL1, BL2,... According to the column address signal, A write voltage or a read voltage is applied to the selected bit line. That is, the column selection circuit 304 is an example of a selection circuit that selects at least one nonvolatile memory element from the nonvolatile memory elements included in the memory cell array 302.
  • the write circuit 305 When the write circuit 305 receives the write signal output from the control circuit 310, the write circuit 305 outputs a signal instructing the column selection circuit 304 to apply the write voltage to the selected bit line. That is, the writing circuit 305 is a writing circuit that writes data by applying a voltage to a nonvolatile memory element (here, a memory cell) selected by a selection circuit (row selection circuit / driver 303 and column selection circuit 304). It is an example.
  • the sense amplifier 306 detects the amount of current flowing through the selected bit line to be read in the information read cycle, and determines that the data is “1” or “0”.
  • the output data DO obtained as a result is output to an external circuit via the data input / output circuit 307.
  • the sense amplifier 306 is an example of a read circuit that reads data by detecting the resistance value of the nonvolatile memory element that constitutes the memory cell selected by the selection circuit (row selection circuit / driver 303 and column selection circuit 304). It is.
  • one transistor is required for each memory cell, so that the cross-point configuration of the second embodiment is used. Compared with the memory capacity. However, since a current suppressing element such as a diode is unnecessary, there is an advantage that it can be easily combined with a CMOS process and the operation can be easily controlled.
  • FIG. 31 is a timing chart showing an operation example of the nonvolatile memory device 300 according to Embodiment 3 of the present invention.
  • an example of operation when the variable resistance layer 315 is assigned to the information “1” when the resistance change layer 315 is in the high resistance state and the information “0” is assigned to the case where the resistance change layer 315 is in the low resistance state is shown.
  • the information “1” when the resistance change layer 315 is in the high resistance state and the information “0” is assigned to the case where the resistance change layer 315 is in the low resistance state is shown.
  • the memory cells M211 and M222 For convenience of explanation, only the case where information is written to and read from the memory cells M211 and M222 is shown.
  • a voltage value VP indicates a pulse voltage necessary for resistance change of the variable resistance element
  • a voltage value VT indicates a threshold voltage of the transistor. Further, the voltage VP is constantly applied to the plate line, and the bit line is also precharged to the voltage VP when not selected.
  • a pulse voltage having a pulse width tP (a voltage higher than (2VP + transistor threshold voltage VT)) is applied to the word line WL0, and the transistor T11 is turned on. Then, according to the timing, the pulse voltage 2VP is applied to the bit line BL0.
  • a write voltage for writing information “1” to the memory cell M211 is applied, and as a result, the resistance change layer of the memory cell M211 has a high resistance. That is, information “1” is written in the memory cell M211.
  • a pulse voltage having a pulse width tP (a voltage higher than (2VP + transistor threshold voltage VT)) is applied to the word line WL1, and the transistor T22 is turned on. Become. Depending on the timing, a voltage of 0 V is applied to the bit line BL1. As a result, a write voltage for writing information “0” to the memory cell M222 is applied, and as a result, the resistance change layer of the memory cell M222 has a low resistance. That is, information “0” is written in the memory cell M222.
  • tP a voltage higher than (2VP + transistor threshold voltage VT)
  • a predetermined voltage is applied to the word line WL0 in order to turn on the transistor T11.
  • a pulse voltage having an amplitude smaller than the pulse width at the time of writing is Applied to the bit line BL0.
  • a current corresponding to the resistance value of the resistance change layer of the memory cell M211 with the increased resistance is output, and information “1” is read by detecting the output current value.
  • the same voltage as that for the previous read cycle for the memory cell M211 is applied to the word line WL1 and the bit line BL1.
  • a current corresponding to the resistance value of the resistance change layer of the memory cell M222 whose resistance is reduced is output, and information “0” is read by detecting the output current value.
  • the non-volatile memory device 300 of the present embodiment also has a non-volatile memory element 313 that can perform a good resistance change operation like the non-volatile memory element 100 of the first embodiment. Therefore, stable operation can be realized.
  • the nonvolatile memory element and the nonvolatile memory device of the present invention are used as a memory element used in various electronic devices, in particular, a memory element and a memory device that operate at a low break voltage, such as a digital home appliance, a memory card, a personal computer, and a mobile phone. It is useful as a storage element and a storage device used in various electronic devices such as type telephones.
  • Nonvolatile memory element 101 Substrate 102 Oxide layer 103 1st electrode layer 104 Resistance change layer 104a 1st oxide layer 104b 2nd oxide layer 105 2nd electrode layer 106 Photoresist pattern 107 Element area 200 Nonvolatile memory Device 201 Memory main body 202 Memory cell array 203 Row selection circuit / driver 204 Column selection circuit / driver 205 Write circuit 206 Sense amplifier 207 Data input / output circuit 208 Address input circuit 209 Control circuit 210 Non-volatile memory element 211 Upper wiring 212 Lower wiring 213 Upper electrode 214 Resistance change layer 215 Internal electrode 216 Current suppression element 217 Lower electrode 300 Non-volatile memory device 301 Memory main body 302 Memory cell array 303 Row selection circuit / driver 04 Column selection circuit 305 Write circuit 306 Sense amplifier 307 Data input / output circuit 308 VCP power supply 309 Address input circuit 310 Control circuit 313 Non-volatile memory element 314 Upper electrode 315 Resistance change layer 316 Lower electrode

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Abstract

Provided is a nonvolatile memory element capable of stable resistance change operation at a low breakdown voltage. The nonvolatile memory element (100) is equipped with a first electrode layer (103), a second electrode layer (105), and a resistance change layer (104) which is between the electrode layers (103 and 105) and reversibly transitions between a high-resistance state and a low-resistance state based on the polarity of a voltage applied between the electrode layers (103 and 105). The resistance change layer (104) is configured by layering of a first oxide layer (104a) containing an oxide of a first transition metal and a second oxide layer (104b) containing an oxide of a second transition metal different from the first transition metal. The standard electrode potential of the second transition metal is lower than the standard electrode potential of the first transition metal, and at least either (1) the dielectric constant of the second oxide layer (104b) is higher than the dielectric constant of the first oxide layer (104a), or (2) the band gap of the second oxide layer (104b) is smaller than the band gap of the first oxide layer (104a) is satisfied.

Description

不揮発性記憶素子及び不揮発性記憶装置Nonvolatile memory element and nonvolatile memory device
　本発明は、不揮発性記憶素子に関し、特に、印加される電圧の極性に基づいて可逆的に高抵抗状態と低抵抗状態とを遷移する、いわゆる抵抗変化型の不揮発性記憶素子、及びその不揮発性記憶素子を備えた不揮発性記憶装置に関する。 The present invention relates to a nonvolatile memory element, and in particular, a so-called variable resistance nonvolatile memory element that reversibly transits between a high resistance state and a low resistance state based on the polarity of an applied voltage, and the nonvolatile memory device The present invention relates to a nonvolatile memory device provided with a memory element.
　近年、デジタル技術の進展に伴い、携帯型情報機器及び情報家電等の電子機器が、より一層高機能化している。そのため、不揮発性記憶素子の大容量化、書き込み電力の低減、書き込み及び読み出し時間の高速化、及び長寿命化の要求が高まっている。 In recent years, electronic devices such as portable information devices and information home appliances have become more sophisticated with the progress of digital technology. Therefore, there are increasing demands for increasing the capacity of nonvolatile memory elements, reducing write power, speeding up writing and reading times, and extending the lifetime.
　こうした要求に対して、既存のフローティングゲートを用いたフラッシュメモリの微細化には限界があると言われている。他方、抵抗変化層を記憶部の材料として用いる抵抗変化型の不揮発性記憶素子の場合、抵抗変化層を下部電極と上部電極とでサンドイッチしたような単純な構造の記憶素子で構成することができるため、さらなる微細化、高速化、及び低消費電力化が期待されている。 In response to these requirements, it is said that there is a limit to the miniaturization of existing flash memory using floating gates. On the other hand, in the case of a resistance change type nonvolatile memory element using the resistance change layer as a material for the memory part, it can be configured by a memory element having a simple structure in which the resistance change layer is sandwiched between a lower electrode and an upper electrode. Therefore, further miniaturization, higher speed, and lower power consumption are expected.
　例えば、上部電極と下部電極との間に電圧を印加することによって抵抗変化層内に金属イオンを出し入れして高抵抗状態及び低抵抗状態を作り出し、これらの各状態に数値を割り当てることにより情報の記憶を行う不揮発性記憶素子が提案されている（例えば、特許文献１を参照）。また、電気パルスによって抵抗変化層の結晶状態を変化させることにより抵抗変化層の抵抗状態を変化させる、相変化型メモリと呼ばれる不揮発性記憶素子も提案されている（例えば、特許文献２を参照）。 For example, by applying a voltage between the upper electrode and the lower electrode, metal ions are taken in and out of the resistance change layer to create a high resistance state and a low resistance state, and information is assigned by assigning a numerical value to each of these states. Nonvolatile memory elements that perform storage have been proposed (see, for example, Patent Document 1). In addition, a nonvolatile memory element called a phase change memory is proposed in which the resistance state of the resistance change layer is changed by changing the crystal state of the resistance change layer by an electric pulse (see, for example, Patent Document 2). .
　さらに、上記に加えて、抵抗変化層に金属酸化物を用いた抵抗変化型の不揮発性記憶素子に関する提案もなされている。このような不揮発性記憶素子は、抵抗変化層に用いる材料によって大きく２種類に分類される。その一つは、特許文献３等に開示されているペロブスカイト材料（Ｐｒ１－ｘＣａｘＭｎＯ３（ＰＣＭＯ）、Ｌａ１－ｘＳｒｘＭｎＯ３（ＬＳＭＯ）、ＧｄＢａＣｏｘＯｙ（ＧＢＣＯ）等）を抵抗変化層に用いた抵抗変化型の不揮発性記憶素子である。 Further, in addition to the above, proposals have been made regarding a resistance change type nonvolatile memory element using a metal oxide in the resistance change layer. Such nonvolatile memory elements are roughly classified into two types depending on the material used for the resistance change layer. One of them is a perovskite material (Pr 1-x Ca x MnO 3 (PCMO), La 1-x Sr x MnO 3 (LSMO), GdBaCo x O y (GBCO), etc.) disclosed in Patent Document 3 and the like) Is a variable resistance nonvolatile memory element using the above in the variable resistance layer.
　また、他の一つは、２元系の遷移金属酸化物を用いた抵抗変化型の不揮発性記憶素子である。２元系の遷移金属酸化物は、上述のペロブスカイト材料と比較しても組成及び構造が非常に単純であるため、製造時における組成制御及び成膜が容易である。その上、半導体製造プロセスとの整合性も比較的良好であるという利点もあり、近年多くの研究がなされている。例えば、特許文献４及び非特許文献１には、抵抗変化材料としてＮｉＯ、Ｖ２Ｏ５、ＺｎＯ、Ｎｂ２Ｏ５、ＴｉＯ２、ＷＯ３、ＣｏＯが開示されている。また、特許文献５には、Ｎｉ、Ｔｉ、Ｈｆ、Ｎｂ、Ｚｎ、Ｗ、Ｃｏ等のサブオキサイド（化学量論的組成からずれた酸化物）を抵抗変化材料として用いた抵抗変化型の不揮発性記憶素子が開示されている。その他にも、ＴｉＮの表面を酸化してナノメートルオーダーのＴｉＯ２結晶膜を形成したような構造を抵抗変化層に用いる例も提案されている（例えば、特許文献６及び非特許文献２を参照）。 The other is a variable resistance nonvolatile memory element using a binary transition metal oxide. Since the binary transition metal oxide has a very simple composition and structure as compared with the above-described perovskite material, composition control and film formation at the time of manufacture are easy. In addition, there is an advantage that the compatibility with the semiconductor manufacturing process is relatively good, and many studies have been made in recent years. For example, Patent Document 4 and Non-Patent Document 1 disclose NiO, V 2 O 5 , ZnO, Nb 2 O 5 , TiO 2 , WO 3 , and CoO as resistance change materials. Patent Document 5 discloses a resistance change type non-volatile using a suboxide (an oxide deviating from the stoichiometric composition) such as Ni, Ti, Hf, Nb, Zn, W, and Co as a resistance change material. A storage element is disclosed. In addition, an example in which a structure in which the surface of TiN is oxidized to form a nanometer order TiO 2 crystal film is used for the resistance change layer has also been proposed (see, for example, Patent Document 6 and Non-Patent Document 2). ).
　さらに、酸化チタン及び酸化タンタル（Ｔａ２Ｏ５）を抵抗変化材料として用い、一度だけの書き込みが可能な所謂ワンタイムプログラマブルメモリも提案されている（例えば、特許文献７を参照）。 Furthermore, a so-called one-time programmable memory that can be written only once using titanium oxide and tantalum oxide (Ta 2 O 5 ) as a resistance change material has been proposed (see, for example, Patent Document 7).
特開２００６－４０９４６号公報JP 2006-40946 A 特開２００４－３４９６８９号公報Japanese Patent Application Laid-Open No. 2004-346989 米国特許第６４７３３３２号明細書US Pat. No. 6,473,332 特開２００４－３６３６０４号公報JP 2004-363604 A 特開２００５－３１７９７６号公報JP 2005-317976 A 特開２００７－１８０２０２号公報JP 2007-180202 A 特開平７－２６３６４７号公報JP-A-7-263647
　しかしながら、上述したような遷移金属酸化物を抵抗変化層に用いた従来の不揮発性記憶素子には、以下のような問題がある。 However, the conventional nonvolatile memory element using the transition metal oxide as described above for the resistance change layer has the following problems.
　ＮｉＯ等の遷移金属酸化物を用いた従来の不揮発性記憶素子では、非特許文献１に開示されているように、１００ｎｓ程度の比較的短い電気的パルスを用いて、抵抗変化材料を高抵抗状態から低抵抗状態へ変化させることができる。しかしながら、低抵抗状態から高抵抗状態へ変化させるためには、μｓオーダーの長パルスが必要になるため、高速化を図ることが困難であるという問題がある。 In a conventional nonvolatile memory element using a transition metal oxide such as NiO, as disclosed in Non-Patent Document 1, the resistance change material is put into a high resistance state by using a relatively short electric pulse of about 100 ns. To a low resistance state. However, in order to change from the low resistance state to the high resistance state, a long pulse on the order of μs is required, and it is difficult to increase the speed.
　また、抵抗変化材料を上下の電極で挟んだ構造を形成した直後は、抵抗状態の変化が起こらないという問題がある。この場合に、抵抗状態の変化を発現させるためには、特殊な電気的刺激を上下電極間に数十回から数千回加える「慣らし」の工程（フォーミング工程と呼ぶことがある）が必要であるとされている。しかしながら、このようなフォーミング工程は製造工程の一つと捉えることができるため、コストの増大及び製造プロセスの複雑化を招く原因となり得る。 Also, there is a problem that the resistance state does not change immediately after forming a structure in which a resistance variable material is sandwiched between upper and lower electrodes. In this case, a “break-in” process (sometimes referred to as a forming process) in which special electrical stimulation is applied tens to thousands of times between the upper and lower electrodes is necessary to cause a change in the resistance state. It is said that there is. However, since such a forming process can be regarded as one of the manufacturing processes, it can cause an increase in cost and a complicated manufacturing process.
　なお、本明細書では、定常的な抵抗状態の変化を得ることができる電気的パルスの極性（正または負）、大きさ（電圧値）及び幅（時間）とは異なる電気的パルスを一回から十回程度加えることによって製造直後の抵抗変化型の不揮発性記憶素子の抵抗状態を変化させる工程を「初期ブレイク」と定義する。例えば、２Ｖの大きさで１００ｎｓの幅を持つ電気的パルスにより抵抗状態が変化する潜在的能力を有する不揮発性記憶素子を動作させるために、その製造直後にこれとは異なる大きさ及び幅の電気的パルスを加える必要がある場合（例えば、±３Ｖで１μｓの電気的パルスを１０回加える等）、初期ブレイクが必要であると表現する。 In this specification, an electrical pulse different from the polarity (positive or negative), magnitude (voltage value), and width (time) of an electrical pulse that can obtain a steady resistance state change is applied once. The process of changing the resistance state of the resistance change type nonvolatile memory element immediately after manufacture by adding about ten times is defined as “initial break”. For example, in order to operate a nonvolatile memory element having the potential to change its resistance state by an electrical pulse having a magnitude of 2 V and a width of 100 ns, an electrical current having a different size and width is manufactured immediately after its manufacture. When it is necessary to apply an electrical pulse (for example, 10 electrical pulses of 1 μs at ± 3 V are applied 10 times), it is expressed that an initial break is necessary.
　初期状態が高抵抗状態にある不揮発性記憶素子に対する初期ブレイクの過程は、誘電体膜の絶縁破壊過程と同様であると考えられている。例えば、K. Kinoshita et al., Applied Physics Letters vol.89, 103509.（非特許文献３）に記載されている。 The initial break process for the nonvolatile memory element whose initial state is the high resistance state is considered to be the same as the dielectric breakdown process of the dielectric film. For example, it is described in K. Kinoshita et al., Applied Physics Letters vol.89, 103509.
　他方、上記特許文献６及び上記非特許文献２に開示されている、ＴｉＮの表面を酸化して微結晶性のＴｉＯ２を形成したような構造（ＴｉＯ２・ＴｉＮ構造）を有する抵抗変化型の不揮発性記憶素子では、初期ブレイクは不要とされている。この場合、ＴｉＯ２がナノメートルオーダーの微小な結晶（以下、ナノ結晶という）の集合体をなしており、この結晶のサイズによって抵抗変化の状態が変化するとされているが、一般にナノ結晶のサイズ及び結晶構造は製造方法（上記特許文献６では酸化によって形成されている）に大きく依存し、そのため製造時のばらつきが大きくなる可能性がある。したがって、抵抗変化層にナノ結晶を用いると、抵抗変化の状態にばらつきが生じやすいという問題がある。 On the other hand, disclosed in Patent Documents 6 and Non-Patent Document 2, the structure as to form by oxidizing the surface of TiN microcrystalline TiO 2 variable resistance having a (TiO 2 · TiN structure) In the nonvolatile memory element, the initial break is unnecessary. In this case, TiO 2 is an aggregate of minute crystals (hereinafter referred to as nanocrystals) on the order of nanometers, and the state of resistance change is said to change depending on the size of the crystals. In addition, the crystal structure largely depends on the manufacturing method (formed by oxidation in the above-mentioned Patent Document 6), and therefore, there may be a large variation in manufacturing. Therefore, when nanocrystals are used for the resistance change layer, there is a problem that the resistance change state is likely to vary.
　また、上記特許文献７に開示されているＴａ２Ｏ５からなる遷移金属酸化物を主成分として抵抗変化層に用いた場合では、高抵抗状態から低抵抗状態への１回動作のみに利用可能なアンチヒューズとして機能するため、書き換えができないという問題がある。 In addition, when the transition metal oxide composed of Ta 2 O 5 disclosed in Patent Document 7 is used as a main component in the resistance change layer, it can be used only for one operation from the high resistance state to the low resistance state. Since it functions as an antifuse, there is a problem that it cannot be rewritten.
　本発明は斯かる事情に鑑みてなされたものであり、その主たる目的は、低いブレイク電圧で、しかも高速で安定した動作をすることができる不揮発性記憶素子及びその不揮発性記憶素子を備えた不揮発性記憶装置を提供することにある。 The present invention has been made in view of such circumstances, and a main object of the present invention is a non-volatile memory element that can operate stably at a high speed at a low break voltage and a non-volatile memory element including the non-volatile memory element. It is to provide a sex memory device.
　上述した課題を解決するために、本発明の一の態様の不揮発性記憶素子は、抵抗変化型の不揮発性記憶素子であって、第１電極と、第２電極と、前記第１電極と前記第２電極との間に介在し、前記第１電極及び前記第２電極間に与えられる電圧の極性に基づいて可逆的に高抵抗状態と低抵抗状態とを遷移する抵抗変化層とを備え、前記抵抗変化層が前記高抵抗状態にあるときの当該不揮発性記憶素子の抵抗値よりも高い抵抗値をもつ初期状態にあるときに、負荷素子が接続された状態で電圧を印加する初期ブレイクが行われることよって前記遷移が可能な状態に変化する特性を有し、前記抵抗変化層は、少なくとも第１の遷移金属の酸化物を含む第１の酸化物層と、前記第１の遷移金属とは異なる第２の遷移金属の酸化物を含む第２の酸化物層との積層構造を含み、前記第２の遷移金属の標準電極電位が前記第１の遷移金属の標準電極電位よりも小さく、かつ、（１）前記第２の酸化物層の誘電率が前記第１の酸化物層の誘電率よりも大きい、（２）前記第２の酸化物層のバンドギャップが前記第１の酸化物層のバンドギャップよりも小さい、において、（１）と（２）の少なくとも一方が満たされていることを特徴とする。 In order to solve the above-described problem, a nonvolatile memory element according to one embodiment of the present invention is a variable resistance nonvolatile memory element, which includes a first electrode, a second electrode, the first electrode, and the first electrode. A resistance change layer interposed between the second electrode and reversibly transitioning between a high resistance state and a low resistance state based on a polarity of a voltage applied between the first electrode and the second electrode; When the resistance change layer is in an initial state having a resistance value higher than the resistance value of the nonvolatile memory element when the resistance change layer is in the high resistance state, an initial break is applied to apply a voltage with the load element connected. The resistance change layer has a characteristic of changing to a state where the transition is possible by being performed, and the variable resistance layer includes at least a first oxide layer including an oxide of a first transition metal, and the first transition metal. A second oxidation comprising an oxide of a different second transition metal A standard electrode potential of the second transition metal is smaller than a standard electrode potential of the first transition metal, and (1) a dielectric constant of the second oxide layer is (1) and (2) in which the dielectric constant of the first oxide layer is larger than (2) the band gap of the second oxide layer is smaller than the band gap of the first oxide layer. At least one of the above is satisfied.
　これにより、標準電極電位が小さい第２の遷移金属を含む第２の酸化物層、つまり、抵抗変化層を構成する第１及び第２の酸化物層のうち、より酸化されやすい第２の酸化物層の誘電率が第１の酸化物層の誘電率よりも大きい、及び、第２の酸化物層のバンドギャップが第１の酸化物層のバンドギャップよりも小さい、の少なくとも一方が満たされるので、抵抗率の高い第２の酸化物層は、抵抗率の低い第１の酸化物層に比べて絶縁破壊電界の強度が小さくなり、その結果、初期状態が高抵抗状態にある不揮発性記憶素子（つまり、遷移金属酸化物層の積層構造からなる抵抗変化層をもつ不揮発性記憶素子）の初期ブレイクにおけるブレイク電圧が低減される。 As a result, the second oxide layer containing the second transition metal having a small standard electrode potential, that is, the second oxidation layer that is more easily oxidized among the first and second oxide layers constituting the resistance change layer. The dielectric constant of the material layer is greater than the dielectric constant of the first oxide layer, and at least one of the band gap of the second oxide layer is smaller than the band gap of the first oxide layer is satisfied Therefore, the second oxide layer having a high resistivity has a smaller breakdown field strength than the first oxide layer having a low resistivity, and as a result, the nonvolatile memory in which the initial state is in a high resistance state. The break voltage in the initial break of the element (that is, the nonvolatile memory element having a variable resistance layer having a laminated structure of transition metal oxide layers) is reduced.
　ここで、上記態様に係る不揮発性記憶素子において、（１）前記第２の酸化物層の誘電率が前記第１の酸化物層の誘電率よりも大きい、及び、（２）前記第２の酸化物層のバンドギャップが前記第１の酸化物層のバンドギャップよりも小さい、の両方が満たされていてもよい。 Here, in the nonvolatile memory element according to the above aspect, (1) a dielectric constant of the second oxide layer is larger than a dielectric constant of the first oxide layer, and (2) the second Both of the band gap of the oxide layer may be smaller than the band gap of the first oxide layer.
　なお、上記態様に係る不揮発性記憶素子において、前記第２電極が前記第２の酸化物層と接するように形成されており、前記第２電極の標準電極電位が前記第２の遷移金属の標準電極電位よりも大きいのが好ましい。これにより、酸素不足型遷移金属酸化物層（つまり、第２の酸化物層）とそれに接する電極との関係において、酸素不足型遷移金属酸化物層が抵抗変化し得る条件が満たされることになるので、不揮発性記憶素子の抵抗が確実に変化できることが保証され、安定した動作が実現される。 In the nonvolatile memory element according to the above aspect, the second electrode is formed so as to be in contact with the second oxide layer, and a standard electrode potential of the second electrode is a standard of the second transition metal. It is preferably larger than the electrode potential. As a result, in the relationship between the oxygen-deficient transition metal oxide layer (that is, the second oxide layer) and the electrode in contact therewith, the conditions under which the oxygen-deficient transition metal oxide layer can change resistance are satisfied. Therefore, it is ensured that the resistance of the nonvolatile memory element can be changed reliably, and a stable operation is realized.
　また、上記態様に係る不揮発性記憶素子において、前記第１の遷移金属の標準電極電位が前記第２電極の標準電極電位より小さいことが好ましい。 In the nonvolatile memory element according to the above aspect, it is preferable that the standard electrode potential of the first transition metal is smaller than the standard electrode potential of the second electrode.
　また、上記態様に係る不揮発性記憶素子において、前記第１の酸化物層の酸素欠損度が前記第２の酸化物層の酸素欠損度よりも大きいことが好ましい。 In the nonvolatile memory element according to the above aspect, it is preferable that the oxygen deficiency of the first oxide layer is larger than the oxygen deficiency of the second oxide layer.
　また、上記態様に係る不揮発性記憶素子において、前記第２の酸化物層の厚みが前記第１の酸化物層の厚みよりも薄いことが好ましい。 In the nonvolatile memory element according to the above aspect, it is preferable that the thickness of the second oxide layer is thinner than the thickness of the first oxide layer.
　また、上記態様に係る不揮発性記憶素子において、前記第２の酸化物層の抵抗率が前記第１の酸化物層の抵抗率よりも大きいことが好ましい。 In the nonvolatile memory element according to the above aspect, it is preferable that the resistivity of the second oxide layer is larger than the resistivity of the first oxide layer.
　また、上記態様に係る不揮発性記憶素子には負荷素子が電気的に接続されていてもよく、この負荷素子が、固定抵抗、トランジスタ、またはダイオードであってもよい。 Further, a load element may be electrically connected to the nonvolatile memory element according to the above aspect, and the load element may be a fixed resistor, a transistor, or a diode.
　また、上記態様に係る不揮発性記憶素子において、前記第１の遷移金属がＴａであることが好ましく、さらに、前記第２の遷移金属がＴｉ、Ｓｒ又はＮｂであることが好ましい。これにより、第２の酸化物層の誘電率が第１の酸化物層の誘電率よりも大きい、及び、第２の酸化物層のバンドギャップが第１の酸化物層のバンドギャップよりも小さい、の両方が満たされた、ブレイク電圧の低い不揮発性記憶素子が実現される。 In the nonvolatile memory element according to the above aspect, the first transition metal is preferably Ta, and the second transition metal is preferably Ti, Sr, or Nb. Thereby, the dielectric constant of the second oxide layer is larger than the dielectric constant of the first oxide layer, and the band gap of the second oxide layer is smaller than the band gap of the first oxide layer. Thus, a non-volatile memory element with a low break voltage that satisfies both of the requirements is realized.
　また、本発明の一の態様の不揮発性記憶装置は、半導体基板と、前記半導体基板上に互いに平行に形成された複数の第１の配線と、前記複数の第１の配線の上方に前記半導体基板の主面に平行な面内において互いに平行に且つ前記複数の第１の配線と立体交差するように形成された複数の第２の配線と、前記複数の第１の配線と前記複数の第２の配線との立体交差点に対応して設けられた上記態様に係る不揮発性記憶素子とを具備するメモリセルアレイと、前記メモリセルアレイが具備する不揮発性記憶素子から、少なくとも一つの不揮発性記憶素子を選択する選択回路と、前記選択回路で選択された不揮発性記憶素子に電圧を印加することでデータを書き込む書き込み回路と、前記選択回路で選択された不揮発性記憶素子の抵抗値を検出することでデータを読み出す読み出し回路とを備えることを特徴とする。 The nonvolatile memory device of one embodiment of the present invention includes a semiconductor substrate, a plurality of first wirings formed in parallel to each other on the semiconductor substrate, and the semiconductor above the plurality of first wirings. A plurality of second wirings formed parallel to each other in a plane parallel to the main surface of the substrate and three-dimensionally intersecting with the plurality of first wirings; the plurality of first wirings; A memory cell array including the nonvolatile memory element according to the above aspect provided corresponding to a three-dimensional intersection with the two wirings, and at least one nonvolatile memory element from the nonvolatile memory element included in the memory cell array. A selection circuit to be selected, a writing circuit for writing data by applying a voltage to the nonvolatile memory element selected by the selection circuit, and a resistance value of the nonvolatile memory element selected by the selection circuit are detected Characterized in that it comprises a read circuit for reading data in Rukoto.
　これにより、上記態様に係る不揮発性記憶装置は、上述した特徴を有する本発明に係る不揮発性記憶素子を備えるので、初期状態が高抵抗状態にある不揮発性記憶素子の初期ブレイクにおけるブレイク電圧が低減される。 Thereby, since the nonvolatile memory device according to the above aspect includes the nonvolatile memory element according to the present invention having the above-described characteristics, the break voltage in the initial break of the nonvolatile memory element in which the initial state is in the high resistance state is reduced. Is done.
　ここで、上記態様に係る不揮発性記憶装置において、さらに、前記不揮発性記憶素子のそれぞれに電気的に接続された電流抑制素子を備えてもよい。 Here, the nonvolatile memory device according to the above aspect may further include a current suppressing element electrically connected to each of the nonvolatile memory elements.
　また、本発明の他の態様の不揮発性記憶装置は、半導体基板と、前記半導体基板上に形成された、複数のワード線及び複数のビット線、前記複数のワード線及び複数のビット線にそれぞれ接続された複数のトランジスタ、並びに前記複数のトランジスタに一対一で対応して設けられた複数の上記態様に係る不揮発性記憶素子とを具備するメモリセルアレイと、前記メモリセルアレイが具備する不揮発性記憶素子から、少なくとも一つの不揮発性記憶素子を選択する選択回路と、前記選択回路で選択された不揮発性記憶素子に電圧を印加することでデータを書き込む書き込み回路と、前記選択回路で選択された不揮発性記憶素子の抵抗値を検出することでデータを読み出す読み出し回路とを備えることを特徴とする。 In addition, a nonvolatile memory device according to another aspect of the present invention includes a semiconductor substrate, a plurality of word lines and a plurality of bit lines formed on the semiconductor substrate, and the plurality of word lines and the plurality of bit lines, respectively. A memory cell array including a plurality of connected transistors, and a plurality of nonvolatile memory elements according to the above-described aspect provided in one-to-one correspondence with the plurality of transistors, and a nonvolatile memory element included in the memory cell array A selection circuit for selecting at least one nonvolatile memory element, a writing circuit for writing data by applying a voltage to the nonvolatile memory element selected by the selection circuit, and a nonvolatile circuit selected by the selection circuit And a reading circuit that reads data by detecting a resistance value of the memory element.
　これにより、上記態様に係る不揮発性記憶装置は、上述した特徴を有する本発明に係る不揮発性記憶素子を備えるので、初期状態が高抵抗状態にある不揮発性記憶素子の初期ブレイクにおけるブレイク電圧が低減される。 Thereby, since the nonvolatile memory device according to the above aspect includes the nonvolatile memory element according to the present invention having the above-described characteristics, the break voltage in the initial break of the nonvolatile memory element in which the initial state is in the high resistance state is reduced. Is done.
　本発明に係る不揮発性記憶素子及び不揮発性記憶装置によれば、不揮発性記憶素子の初期ブレイクにおけるブレイク電圧が低減され、不揮発性記憶素子の抵抗値を確実に変化させることができるため、安定した動作を実現することができる。 According to the nonvolatile memory element and the nonvolatile memory device according to the present invention, the break voltage in the initial break of the nonvolatile memory element is reduced, and the resistance value of the nonvolatile memory element can be changed reliably. Operation can be realized.
図１は、本発明の実施の形態１に係る不揮発性記憶素子の構成を示す断面図である。FIG. 1 is a cross-sectional view showing a configuration of a nonvolatile memory element according to Embodiment 1 of the present invention. 図２は、本発明の実施の形態１に係る不揮発性記憶素子の製造工程を示す断面図である。FIG. 2 is a cross-sectional view showing a manufacturing process of the nonvolatile memory element according to Embodiment 1 of the present invention. 図３は、情報を書き込む場合における本発明の実施の形態１に係る不揮発性記憶素子の動作例を示す図である。FIG. 3 is a diagram showing an operation example of the nonvolatile memory element according to Embodiment 1 of the present invention when information is written. 図４は、情報を読み出す場合における本発明の実施の形態１に係る不揮発性記憶素子の動作例を示す図である。FIG. 4 is a diagram illustrating an operation example of the nonvolatile memory element according to Embodiment 1 of the present invention when reading information. 図５は、酸素不足型遷移金属酸化物を構成する遷移金属の標準電極電位と電極材料の標準電極電位との差異と、酸素不足型金属酸化物の抵抗変化との相関を示すグラフである。FIG. 5 is a graph showing the correlation between the difference between the standard electrode potential of the transition metal constituting the oxygen-deficient transition metal oxide and the standard electrode potential of the electrode material, and the resistance change of the oxygen-deficient metal oxide. 図６は、酸素不足型タンタル酸化物を用いた不揮発性記憶素子において、第２電極にＰｔを用いたときの、電気パルスの印加回数に対する抵抗変化を示す図である。FIG. 6 is a diagram showing a change in resistance with respect to the number of electric pulses applied when Pt is used for the second electrode in a nonvolatile memory element using an oxygen-deficient tantalum oxide. 図７は、酸素不足型タンタル酸化物を用いた不揮発性記憶素子において、第２電極にＩｒを用いたときの、電気パルスの印加回数に対する抵抗変化を示す図である。FIG. 7 is a diagram showing a change in resistance with respect to the number of electric pulses applied when Ir is used for the second electrode in a nonvolatile memory element using an oxygen-deficient tantalum oxide. 図８は、酸素不足型タンタル酸化物を用いた不揮発性記憶素子において、第２電極にＡｇを用いたときの、電気パルスの印加回数に対する抵抗変化を示す図である。FIG. 8 is a diagram showing a change in resistance with respect to the number of electric pulses applied when Ag is used for the second electrode in a nonvolatile memory element using an oxygen-deficient tantalum oxide. 図９は、酸素不足型タンタル酸化物を用いた不揮発性記憶素子において、第２電極にＣｕを用いたときの、電気パルスの印加回数に対する抵抗変化を示す図である。FIG. 9 is a diagram showing a change in resistance with respect to the number of electric pulses applied when Cu is used for the second electrode in a nonvolatile memory element using an oxygen-deficient tantalum oxide. 図１０は、酸素不足型タンタル酸化物を用いた不揮発性記憶素子において、第２電極にＮｉを用いたときの、電気パルスの印加回数に対する抵抗変化を示す図である。FIG. 10 is a diagram showing a change in resistance with respect to the number of electric pulses applied when Ni is used for the second electrode in a nonvolatile memory element using an oxygen-deficient tantalum oxide. 図１１は、酸素不足型タンタル酸化物を用いた不揮発性記憶素子において、第２電極にＷを用いたときの、電気パルスの印加回数に対する抵抗変化を示す図である。FIG. 11 is a diagram showing a change in resistance with respect to the number of electric pulses applied when W is used for the second electrode in a nonvolatile memory element using an oxygen-deficient tantalum oxide. 図１２は、酸素不足型タンタル酸化物を用いた不揮発性記憶素子において、第２電極にＴａを用いたときの、電気パルスの印加回数に対する抵抗変化を示す図である。FIG. 12 is a diagram showing a change in resistance with respect to the number of electric pulses applied when Ta is used for the second electrode in a nonvolatile memory element using an oxygen-deficient tantalum oxide. 図１３は、酸素不足型タンタル酸化物を用いた不揮発性記憶素子において、第２電極にＴｉを用いたときの、電気パルスの印加回数に対する抵抗変化を示す図である。FIG. 13 is a diagram showing a change in resistance with respect to the number of electric pulses applied when Ti is used for the second electrode in a nonvolatile memory element using an oxygen-deficient tantalum oxide. 図１４は、酸素不足型タンタル酸化物を用いた不揮発性記憶素子において、第２電極にＡｌを用いたときの、電気パルスの印加回数に対する抵抗変化を示す図である。FIG. 14 is a diagram showing a change in resistance with respect to the number of electric pulses applied when Al is used for the second electrode in a nonvolatile memory element using an oxygen-deficient tantalum oxide. 図１５は、酸素不足型ハフニウム酸化物を用いた不揮発性記憶素子において、第２電極にＰｔを用いたときの、電気パルスの印加回数に対する抵抗変化を示す図である。FIG. 15 is a diagram showing a change in resistance with respect to the number of electric pulses applied when Pt is used for the second electrode in a nonvolatile memory element using oxygen-deficient hafnium oxide. 図１６は、酸素不足型ハフニウム酸化物を用いた不揮発性記憶素子において、第２電極にＣｕを用いたときの、電気パルスの印加回数に対する抵抗変化を示す図である。FIG. 16 is a diagram showing a change in resistance with respect to the number of electric pulses applied when Cu is used for the second electrode in a nonvolatile memory element using an oxygen-deficient hafnium oxide. 図１７は、酸素不足型ハフニウム酸化物を用いた不揮発性記憶素子において、第２電極にＷを用いたときの、電気パルスの印加回数に対する抵抗変化を示す図である。FIG. 17 is a diagram showing a change in resistance with respect to the number of electric pulses applied when W is used for the second electrode in a nonvolatile memory element using oxygen-deficient hafnium oxide. 図１８は、酸素不足型ハフニウム酸化物を用いた不揮発性記憶素子において、第２電極にＴａを用いたときの、電気パルスの印加回数に対する抵抗変化を示す図である。FIG. 18 is a diagram showing a change in resistance with respect to the number of electric pulses applied when Ta is used for the second electrode in a nonvolatile memory element using oxygen-deficient hafnium oxide. 図１９は、酸素不足型ハフニウム酸化物を用いた不揮発性記憶素子において、第２電極にＨｆを用いたときの、電気パルスの印加回数に対する抵抗変化を示す図である。FIG. 19 is a diagram showing a change in resistance with respect to the number of electric pulses applied when Hf is used for the second electrode in a nonvolatile memory element using oxygen-deficient hafnium oxide. 図２０は、酸素不足型ハフニウム酸化物を用いた不揮発性記憶素子において、第２電極にＴｉを用いたときの、電気パルスの印加回数に対する抵抗変化を示す図である。FIG. 20 is a diagram showing a change in resistance with respect to the number of electric pulses applied when Ti is used for the second electrode in a nonvolatile memory element using oxygen-deficient hafnium oxide. 図２１は、酸素不足型ハフニウム酸化物を用いた不揮発性記憶素子において、第２電極にＡｌを用いたときの、電気パルスの印加回数に対する抵抗変化を示す図である。FIG. 21 is a diagram showing a change in resistance with respect to the number of electric pulses applied when Al is used for the second electrode in a nonvolatile memory element using oxygen-deficient hafnium oxide. 図２２は、第２のタンタル酸化物層の厚みを３ｎｍとした場合の実験用の不揮発性記憶素子単体の電気的特性を示すグラフである。FIG. 22 is a graph showing the electrical characteristics of a single nonvolatile memory element for experiment when the thickness of the second tantalum oxide layer is 3 nm. 図２３は、第２のタンタル酸化物層の厚みを３ｎｍとした場合であって負荷素子が接続されているときの実験用の不揮発性記憶素子の電気的特性を示すグラフである。FIG. 23 is a graph showing the electrical characteristics of the experimental nonvolatile memory element when the thickness of the second tantalum oxide layer is 3 nm and the load element is connected. 図２４は、第２のタンタル酸化物層の厚みδを変化させたときの抵抗変化層の初期抵抗値とブレイク電圧との関係、及び当該初期抵抗値とリーク電流との関係を示すグラフである。FIG. 24 is a graph showing the relationship between the initial resistance value of the variable resistance layer and the break voltage when the thickness δ of the second tantalum oxide layer is changed, and the relationship between the initial resistance value and the leakage current. . 図２５は、本発明の実施の形態２に係る不揮発性記憶装置の構成を示すブロック図である。FIG. 25 is a block diagram showing a configuration of the nonvolatile memory device according to Embodiment 2 of the present invention. 図２６は、図２５におけるＡ部の構成（４ビット分の構成）を示す斜視図である。FIG. 26 is a perspective view showing the configuration (configuration corresponding to 4 bits) of part A in FIG. 図２７は、本発明の実施の形態２に係る不揮発性記憶装置が備える不揮発性記憶素子の構成を示す断面図である。FIG. 27 is a cross-sectional view showing a configuration of a nonvolatile memory element included in the nonvolatile memory device according to Embodiment 2 of the present invention. 図２８は、本発明の実施の形態２に係る不揮発性記憶装置の動作例を示すタイミングチャートである。FIG. 28 is a timing chart showing an operation example of the nonvolatile memory device according to Embodiment 2 of the present invention. 図２９は、本発明の実施の形態３に係る不揮発性記憶装置の構成を示すブロック図である。FIG. 29 is a block diagram showing a configuration of the nonvolatile memory device according to Embodiment 3 of the present invention. 図３０は、図２９におけるＣ部の構成（２ビット分の構成）を示す断面図である。FIG. 30 is a cross-sectional view showing the configuration (configuration corresponding to 2 bits) of part C in FIG. 図３１は、本発明の実施の形態３に係る不揮発性記憶装置の動作例を示すタイミングチャートである。FIG. 31 is a timing chart showing an operation example of the nonvolatile memory device according to Embodiment 3 of the present invention.
　以下、本発明の好ましい実施の形態を、図面を参照しながら説明する。 Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.
　（実施の形態１）
　まず、本発明の実施の形態１に係る不揮発性記憶素子について説明する。 (Embodiment 1)
First, the nonvolatile memory element according to Embodiment 1 of the present invention will be described.
　［不揮発性記憶素子の構成］
　図１は、本発明の実施の形態１に係る不揮発性記憶素子１００の構成を示す断面図である。図１に示すように、この不揮発性記憶素子１００は、抵抗変化型の不揮発性記憶素子であり、基板１０１と、基板１０１の上に形成された酸化物層１０２と、酸化物層１０２の上に形成された第１電極層１０３と、第２電極層１０５と、第１電極層１０３及び第２電極層１０５に挟まれた抵抗変化層１０４とを備えている。第１電極層１０３及び第２電極層１０５は、抵抗変化層１０４と電気的に接続されている。 [Configuration of Nonvolatile Memory Element]
FIG. 1 is a cross-sectional view showing a configuration of a nonvolatile memory element 100 according to Embodiment 1 of the present invention. As shown in FIG. 1, the nonvolatile memory element 100 is a variable resistance nonvolatile memory element, and includes a substrate 101, an oxide layer 102 formed on the substrate 101, and an oxide layer 102. The first electrode layer 103, the second electrode layer 105, and the variable resistance layer 104 sandwiched between the first electrode layer 103 and the second electrode layer 105 are provided. The first electrode layer 103 and the second electrode layer 105 are electrically connected to the resistance change layer 104.
　抵抗変化層１０４は、第１電極層１０３及び第２電極層１０５間に与えられる電圧の極性に基づいて可逆的に高抵抗状態と低抵抗状態とを遷移するバイポーラ型の抵抗変化層であり、ＴａＯｘで表される組成を有するタンタル酸化物で構成されている第１の酸化物層１０４ａと、その第１の酸化物層１０４ａ上に形成され、ＴｉＯ２で表される組成を有するチタン酸化物で構成されている第２の酸化物層１０４ｂとで構成されている。 The resistance change layer 104 is a bipolar resistance change layer that reversibly transitions between a high resistance state and a low resistance state based on the polarity of the voltage applied between the first electrode layer 103 and the second electrode layer 105. A first oxide layer 104a made of tantalum oxide having a composition represented by TaO x , and titanium oxide formed on the first oxide layer 104a and having a composition represented by TiO 2 And the second oxide layer 104b made of a material.
　これら第１の酸化物層１０４ａ（本実施の形態では、ＴａＯｘ）と第２の酸化物層１０４ｂ（本実施の形態では、ＴｉＯ２）とは、以下の関係を満たしている。つまり、第２の酸化物層１０４ｂに含まれる遷移金属（第２の遷移金属）の標準電極電位が第１の酸化物層１０４ａに含まれる遷移金属（第１の遷移金属）の標準電極電位よりも小さい。さらに、（１）第２の酸化物層１０４ｂの誘電率が第１の酸化物層１０４ａの誘電率よりも大きい、及び、（２）第２の酸化物層１０４ｂのバンドギャップが第１の酸化物層１０４ａのバンドギャップよりも小さい、の少なくとも一方が満たされている。なお、本実施の形態では、（１）及び（２）の両方が満たされている。この意義については後述する。 The first oxide layer 104a (TaO x in this embodiment) and the second oxide layer 104b (TiO 2 in this embodiment) satisfy the following relationship. That is, the standard electrode potential of the transition metal (second transition metal) included in the second oxide layer 104b is greater than the standard electrode potential of the transition metal (first transition metal) included in the first oxide layer 104a. Is also small. Further, (1) the dielectric constant of the second oxide layer 104b is larger than the dielectric constant of the first oxide layer 104a, and (2) the band gap of the second oxide layer 104b is the first oxidation. At least one of smaller than the band gap of the material layer 104a is satisfied. In the present embodiment, both (1) and (2) are satisfied. This significance will be described later.
　なお、この不揮発性記憶素子１００は、抵抗変化層１０４が高抵抗状態にあるときの当該不揮発性記憶素子１００の抵抗値よりも高い抵抗値をもつ初期状態にあるときに、負荷素子が接続された状態で電圧を印加する初期ブレイクが行われることよって高抵抗状態と低抵抗状態との遷移が可能な状態に変化する特性を有する。 The nonvolatile memory element 100 is connected to the load element when it is in an initial state having a resistance value higher than the resistance value of the nonvolatile memory element 100 when the resistance change layer 104 is in the high resistance state. When the initial break is applied in which the voltage is applied, the high-resistance state and the low-resistance state can be changed to a state capable of transition.
　この不揮発性記憶素子１００を駆動する場合、外部の電源によって所定の条件を満たすパルス電圧を第１電極層１０３と第２電極層１０５との間に印加する。ここでは、第１電極層１０３に対する第２電極層１０５の相対的電位（電圧）を第１電極層１０３と第２電極層１０５との間に印加する電圧と定義する。したがって、第１電極層１０３より第２電極層１０５の電位が高くなる印加電圧が正の印加電圧であり、他方、第１電極層１０３より第２電極層１０５の電位が低くなる印加電圧が負の印加電圧である。 When driving the nonvolatile memory element 100, a pulse voltage satisfying a predetermined condition is applied between the first electrode layer 103 and the second electrode layer 105 by an external power source. Here, the relative potential (voltage) of the second electrode layer 105 with respect to the first electrode layer 103 is defined as a voltage applied between the first electrode layer 103 and the second electrode layer 105. Therefore, the applied voltage at which the potential of the second electrode layer 105 is higher than that of the first electrode layer 103 is a positive applied voltage, while the applied voltage at which the potential of the second electrode layer 105 is lower than that of the first electrode layer 103 is negative. Applied voltage.
　基板１０１としては、例えばシリコン単結晶基板または半導体基板を用いることができる。しかし、本発明はこれに限定されるわけではない。抵抗変化層１０４は、比較的低い基板温度で形成することが可能であるため、樹脂材料などの上に抵抗変化層１０４を形成することも可能である。 As the substrate 101, for example, a silicon single crystal substrate or a semiconductor substrate can be used. However, the present invention is not limited to this. Since the resistance change layer 104 can be formed at a relatively low substrate temperature, the resistance change layer 104 can be formed on a resin material or the like.
　また、第１電極層１０３及び第２電極層１０５は、それぞれ、本発明に係る第１電極及び第２電極に対応し、例えば、Ａｕ（金）、Ｐｔ（白金）、Ｉｒ（イリジウム）、Ｐｄ（パラジウム）、Ａｇ（銀）、Ｎｉ（ニッケル）、Ｗ（タングステン）、Ｃｕ（銅）及びＴａＮ（窒化タンタル）等のうちの１つまたは複数の材料を用いて構成される。なお、第２電極層１０５の好適な材料については後述する。 The first electrode layer 103 and the second electrode layer 105 correspond to the first electrode and the second electrode according to the present invention, respectively. For example, Au (gold), Pt (platinum), Ir (iridium), Pd (Palladium), Ag (silver), Ni (nickel), W (tungsten), Cu (copper), TaN (tantalum nitride), or the like. A suitable material for the second electrode layer 105 will be described later.
　［不揮発性記憶素子の製造方法］
　上記のように構成される不揮発性記憶素子は、次のようにして製造することが可能である。 [Method of Manufacturing Nonvolatile Memory Element]
The nonvolatile memory element configured as described above can be manufactured as follows.
　図２（ａ）～（ｃ）は、本発明の実施の形態１に係る不揮発性記憶素子の製造工程を示す断面図である。 2 (a) to 2 (c) are cross-sectional views showing manufacturing steps of the nonvolatile memory element according to Embodiment 1 of the present invention.
　まず、図２（ａ）に示すように、単結晶シリコンである基板１０１上に、厚さ２００ｎｍの酸化物層１０２を熱酸化法により形成する。そして、第１電極層１０３としての厚さ１００ｎｍのＴａＮ薄膜を、スパッタリング法により酸化物層１０２上に形成する。その後、第１電極層１０３上に、第１の酸化物層１０４ａを、Ｔａターゲットを用いた反応性スパッタリング法で形成する。 First, as shown in FIG. 2A, an oxide layer 102 having a thickness of 200 nm is formed on a substrate 101 made of single crystal silicon by a thermal oxidation method. Then, a TaN thin film having a thickness of 100 nm as the first electrode layer 103 is formed on the oxide layer 102 by a sputtering method. After that, a first oxide layer 104a is formed on the first electrode layer 103 by a reactive sputtering method using a Ta target.
　ここで、第１の酸化物層１０４ａの堆積は、以下に述べる条件で行った。すなわち、スパッタリング装置内に基板を設置した後、スパッタリング装置内を８×１０－６Ｐａ程度まで真空引きする。そして、タンタルをターゲットとして、パワーを１．６ｋＷとし、アルゴンガスを３４ｓｃｃｍ、酸素ガスを２１ｓｃｃｍ流して、スパッタリング装置内の圧力を０．１７Ｐａに保ち、２０秒間スパッタリングを行う。これにより、抵抗率が６ｍΩｃｍで酸素含有率が約６１ａｔ％（ＴａＯ１．６）の第１の酸化物層を３０ｎｍ堆積できる。なお、ＴａＯ１．６は、本発明に係る第１の酸化物層の一例であるが、本発明に係る第１の酸化物層としては、このような材料に限定されず、上述したように、（１）第２の酸化物層１０４ｂの誘電率が第１の酸化物層１０４ａの誘電率よりも大きい、及び、（２）第２の酸化物層１０４ｂのバンドギャップが第１の酸化物層１０４ａのバンドギャップよりも小さい、の少なくとも一方が満たされている限りいかなる酸化物層でもよく、例えば、ＴａＯｘ（０．８≦ｘ≦１．９）であってもよい。 Here, the first oxide layer 104a was deposited under the conditions described below. That is, after setting the substrate in the sputtering apparatus, the inside of the sputtering apparatus is evacuated to about 8 × 10 −6 Pa. Then, using tantalum as a target, the power is set to 1.6 kW, argon gas is supplied at 34 sccm, oxygen gas is supplied at 21 sccm, the pressure in the sputtering apparatus is maintained at 0.17 Pa, and sputtering is performed for 20 seconds. As a result, a first oxide layer having a resistivity of 6 mΩcm and an oxygen content of about 61 at% (TaO 1.6 ) can be deposited to 30 nm. Note that TaO 1.6 is an example of the first oxide layer according to the present invention, but the first oxide layer according to the present invention is not limited to such a material, and as described above. (1) the dielectric constant of the second oxide layer 104b is larger than the dielectric constant of the first oxide layer 104a; and (2) the band gap of the second oxide layer 104b is the first oxide. Any oxide layer may be used as long as at least one of the layers 104a smaller than the band gap is satisfied. For example, TaO x (0.8 ≦ x ≦ 1.9) may be used.
　次に、図２（ｂ）に示すように、第１の酸化物層１０４ａ上に、第２の酸化物層１０４ｂを、ＴｉＯ２をターゲットとして用いてスパッタリング法により形成する。本実施の形態では、厚さ３ｎｍの酸化物層を堆積して第２の酸化物層１０４ｂを形成する。 Next, as shown in FIG. 2B, a second oxide layer 104b is formed on the first oxide layer 104a by a sputtering method using TiO 2 as a target. In this embodiment, an oxide layer with a thickness of 3 nm is deposited to form the second oxide layer 104b.
　その後、第２の酸化物層１０４ｂ上に、第２電極層１０５としての厚さ１５０ｎｍのＩｒ薄膜をスパッタリング法により形成する。最後に、フォトレジスト工程によって、フォトレジストによるパターン１０６を形成し、ドライエッチングによって、素子領域１０７を形成する（図２（ｃ）参照）。ここで素子領域１０７は、一辺が０．５μｍの四角形状としている。 Thereafter, an Ir thin film having a thickness of 150 nm as the second electrode layer 105 is formed on the second oxide layer 104b by a sputtering method. Finally, a photoresist pattern 106 is formed by a photoresist process, and an element region 107 is formed by dry etching (see FIG. 2C). Here, the element region 107 has a square shape with a side of 0.5 μm.
　［不揮発性記憶素子の動作例］
　以下、上述したように構成される本実施の形態の不揮発性記憶素子の動作例、すなわち情報の書き込み及び読み出しを行う場合の動作例を説明する。 [Operation example of nonvolatile memory element]
Hereinafter, an operation example of the nonvolatile memory element according to this embodiment configured as described above, that is, an operation example in the case of writing and reading information will be described.
　図３は、情報を書き込む場合における本実施の形態の不揮発性記憶素子の動作例を示す図である。 FIG. 3 is a diagram illustrating an operation example of the nonvolatile memory element according to the present embodiment when information is written.
　不揮発性記憶素子１００の第１電極層１０３と第２電極層１０５との間に、例えばパルス幅が１００ｎｓの極性が異なる２種類の電圧パルスを交互に印加すると、図３に示すように抵抗変化層１０４の抵抗値が変化する。すなわち、負電圧パルス（電圧Ｅ１ボルト、パルス幅１００ｎｓ）を電極間に印加した場合、抵抗変化層１０４の抵抗値が高抵抗値Ｒｂから低抵抗値Ｒａへ減少する。つまり、高抵抗状態から低抵抗状態へ遷移する。他方、正電圧パルス（電圧Ｅ２ボルト、パルス幅１００ｎｓ）を電極間に印加した場合、抵抗変化層１０４の抵抗値が低抵抗値Ｒａから高抵抗値Ｒｂへ増加する。つまり、低抵抗状態から高抵抗状態へ遷移する。 When two types of voltage pulses having different polarities with a pulse width of 100 ns, for example, are alternately applied between the first electrode layer 103 and the second electrode layer 105 of the nonvolatile memory element 100, the resistance change as shown in FIG. The resistance value of the layer 104 changes. That is, when a negative voltage pulse (voltage E1 volt, pulse width 100 ns) is applied between the electrodes, the resistance value of the resistance change layer 104 decreases from the high resistance value Rb to the low resistance value Ra. That is, a transition from the high resistance state to the low resistance state. On the other hand, when a positive voltage pulse (voltage E2 volts, pulse width 100 ns) is applied between the electrodes, the resistance value of the resistance change layer 104 increases from the low resistance value Ra to the high resistance value Rb. That is, a transition from the low resistance state to the high resistance state.
　この図３に示す例では、高抵抗値Ｒｂを情報「０」に、低抵抗値Ｒａを情報「１」にそれぞれ割り当てている。したがって、本実施の形態においては、抵抗変化層１０４の抵抗値が高抵抗値Ｒｂになるように正電圧パルスを電極間に印加することによって情報「０」が書き込まれることになり、他方、抵抗変化層１０４の抵抗値が低抵抗値Ｒａになるように負電圧パルスを電極間に印加することによって情報「１」が書き込まれることになる。 In the example shown in FIG. 3, the high resistance value Rb is assigned to information “0”, and the low resistance value Ra is assigned to information “1”. Therefore, in the present embodiment, information “0” is written by applying a positive voltage pulse between the electrodes so that the resistance value of the resistance change layer 104 becomes the high resistance value Rb. Information “1” is written by applying a negative voltage pulse between the electrodes such that the resistance value of the change layer 104 becomes the low resistance value Ra.
　図４は、情報を読み出す場合における本実施の形態の不揮発性記憶素子１００の動作例を示す図である。 FIG. 4 is a diagram illustrating an operation example of the nonvolatile memory element 100 according to the present embodiment when information is read.
　情報の読み出しを行う場合は、抵抗変化層１０４の抵抗値を変化させるときに印加する電圧パルスよりも振幅の小さい読み出し用電圧Ｅ３ボルト（｜Ｅ３｜＜｜Ｅ１｜、｜Ｅ３｜＜｜Ｅ２｜）を電極間に印加する。その結果、抵抗変化層１０４の抵抗値に対応して電流が出力され、その出力電流値を検出することにより、書き込まれている情報（「０」又は「１」）の読み出しが可能となる。 When information is read, the read voltage E3 volts (| E3 | <| E1 |, | E3 | <| E2 |) having a smaller amplitude than the voltage pulse applied when the resistance value of the resistance change layer 104 is changed. ) Is applied between the electrodes. As a result, a current is output corresponding to the resistance value of the resistance change layer 104, and the written information (“0” or “1”) can be read by detecting the output current value.
　図４に示す例では、出力電流値Ｉａが低抵抗値Ｒａに、出力電流値Ｉｂが高抵抗値Ｒｂにそれぞれ対応しているので、出力電流値Ｉａが検出された場合は情報「１」が、出力電流値Ｉｂが検出された場合は情報「０」がそれぞれ読み出されることになる。 In the example shown in FIG. 4, the output current value Ia corresponds to the low resistance value Ra, and the output current value Ib corresponds to the high resistance value Rb. Therefore, when the output current value Ia is detected, the information “1” is displayed. When the output current value Ib is detected, the information “0” is read out.
　［第１の酸化物層及び第２の酸化物層の材料］
　上述したように、本実施の形態では、抵抗変化層１０４が第１の酸化物層１０４ａ及び第２の酸化物層１０４ｂの積層構造で構成されており、その第１の酸化物層１０４ａはＴａＯｘで、第２の酸化物層１０４ｂはＴｉＯ２でそれぞれ構成されている。しかし、第１の酸化物層１０４ａ及び第２の酸化物層１０４ｂの材料はこれに限定されるわけではない。以下、第１の酸化物層１０４ａ及び第２の酸化物層１０４ｂの材料としてどのようなものが適当であるのかについて説明する。 [Material of first oxide layer and second oxide layer]
As described above, in this embodiment, the resistance change layer 104 includes the stacked structure of the first oxide layer 104a and the second oxide layer 104b, and the first oxide layer 104a includes TaO. x , the second oxide layer 104b is composed of TiO 2 respectively. However, the materials of the first oxide layer 104a and the second oxide layer 104b are not limited to this. Hereinafter, what is suitable as a material of the 1st oxide layer 104a and the 2nd oxide layer 104b is demonstrated.
　まず、第２の酸化物層１０４ｂは、第１の酸化物層１０４ａよりも抵抗率が高いことが望ましい。なぜなら、不揮発性記憶素子における抵抗変化層の抵抗変化のメカニズムについて、以下のような推論が成立するからである。 First, it is desirable that the second oxide layer 104b has a higher resistivity than the first oxide layer 104a. This is because the following reasoning holds for the mechanism of resistance change of the resistance change layer in the nonvolatile memory element.
　不揮発性記憶素子における抵抗変化層の抵抗変化は、現時点では明確に分かっていないものの、電極と抵抗変化層との界面の酸素原子の移動によって起こっていると推測される。このことを考慮すると、本実施の形態における第２の酸化物層１０４ｂは、当該界面近傍に電圧を有効に印加する役割を果たすものと考えられる。より詳細について説明すると、抵抗変化現象は、第２電極層と抵抗変化層との界面付近に電界によって酸素原子が集まったり、拡散したりすることによって発現していると考えられる。具体的には、第２電極層に正の電圧（第１電極層を基準として正の電圧を印加する場合を、「正の電圧」とする）を印加すれば負に帯電している酸素原子が第２電極層側に集まり、その結果高抵抗層が形成されるため、抵抗変化層が高抵抗化する。反対に負の電圧（第１電極層を基準として負の電圧を印加する場合を、「負の電圧」とする）を印加すれば、酸素原子が抵抗変化層内に拡散して抵抗値が下がる。ここで、界面（正確には抵抗変化層側の界面）に高抵抗層が存在すれば、この層に大きな電圧がかかるため、酸素が当該高抵抗層に注入される。その結果、この高抵抗層が絶縁物に近づくことになる。そのため、抵抗変化層自体の抵抗が上昇し、高抵抗状態となる。しかし、このような高抵抗層が界面に存在しなければ、電圧は抵抗変化層に均等にかかり、当該界面近傍に絶縁物に近い層は形成されにくい。その結果、抵抗変化現象が起こりにくくなる。 Although the resistance change of the variable resistance layer in the nonvolatile memory element is not clearly understood at the present time, it is presumed that it is caused by the movement of oxygen atoms at the interface between the electrode and the variable resistance layer. Considering this, the second oxide layer 104b in this embodiment is considered to play a role of effectively applying a voltage in the vicinity of the interface. More specifically, it is considered that the resistance change phenomenon is caused by oxygen atoms gathering or diffusing due to an electric field near the interface between the second electrode layer and the resistance change layer. Specifically, when a positive voltage is applied to the second electrode layer (the case where a positive voltage is applied with reference to the first electrode layer is referred to as a “positive voltage”), the oxygen atoms are negatively charged. Gather on the second electrode layer side, and as a result a high resistance layer is formed, the resistance variable layer has a high resistance. On the contrary, if a negative voltage is applied (a negative voltage is applied with reference to the first electrode layer is referred to as a “negative voltage”), oxygen atoms diffuse into the resistance change layer and the resistance value decreases. . Here, if a high resistance layer exists at the interface (more precisely, the resistance change layer side interface), a large voltage is applied to this layer, so that oxygen is injected into the high resistance layer. As a result, this high resistance layer approaches the insulator. For this reason, the resistance of the resistance change layer itself increases, and a high resistance state is obtained. However, if such a high resistance layer does not exist at the interface, the voltage is evenly applied to the resistance change layer, and a layer close to an insulator is hardly formed near the interface. As a result, the resistance change phenomenon hardly occurs.
　以上を考慮すると、電極と抵抗変化層との界面に高抵抗層が存在することが望ましい。そのため、本実施の形態の不揮発性記憶素子１００において第２電極層１０５と抵抗変化層１０４との界面に、第１の酸化物層１０４ａよりも抵抗率が高い第２の酸化物層１０４ｂを設けることが望ましいといえる。 Considering the above, it is desirable that a high resistance layer exists at the interface between the electrode and the resistance change layer. Therefore, in the nonvolatile memory element 100 of this embodiment, the second oxide layer 104b having a higher resistivity than the first oxide layer 104a is provided at the interface between the second electrode layer 105 and the resistance change layer 104. Is desirable.
　また、上記の推論によれば、第１の酸化物層１０４ａに含まれる第１の遷移金属と比べて第２の酸化物層１０４ｂに含まれる第２の遷移金属の方が酸化されやすいことが望ましい。第１の遷移金属と比べて酸化されやすい第２の遷移金属で第２の酸化物層１０４ｂを構成した場合に、第１電極層１０３及び第２電極層１０５間に正の電圧を印加すると、第２の酸化物層１０４ｂが高抵抗化しやすくなるため、抵抗変化層１０４を容易に高抵抗状態とすることができる。 Further, according to the above reasoning, the second transition metal contained in the second oxide layer 104b is more likely to be oxidized than the first transition metal contained in the first oxide layer 104a. desirable. When the second oxide layer 104b is composed of a second transition metal that is more easily oxidized than the first transition metal, when a positive voltage is applied between the first electrode layer 103 and the second electrode layer 105, Since the resistance of the second oxide layer 104b is easily increased, the resistance change layer 104 can be easily in a high resistance state.
　ある材料が酸化されやすいか否かは、その材料の標準電極電位を基準にして判断することが可能である。すなわち、標準電極電位の値が大きければ当該材料は酸化されにくく、反対に小さければ当該材料は酸化されやすいといえる。そのため、本実施の形態においては、第２の酸化物層１０４ｂに含まれる第２の遷移金属の標準電極電位が、第１の酸化物層１０４ａに含まれる第１の遷移金属の標準電極電位よりも小さい（つまり、酸化されやすい）ことが望ましいといえる。また、同様の理由で、第２の酸化物層１０４ｂの酸素欠損度が、第１の酸化物層１０４ａの酸素欠損度よりも小さいことが望ましいといえる。なお、酸素欠損度とは、化学量論的組成における酸素欠損の程度（比）である。 It can be determined whether or not a material is easily oxidized based on the standard electrode potential of the material. That is, if the value of the standard electrode potential is large, it can be said that the material is less likely to be oxidized. Therefore, in this embodiment, the standard electrode potential of the second transition metal included in the second oxide layer 104b is higher than the standard electrode potential of the first transition metal included in the first oxide layer 104a. It is desirable that the particle size is small (that is, easily oxidized). For the same reason, it can be said that the oxygen deficiency of the second oxide layer 104b is preferably smaller than the oxygen deficiency of the first oxide layer 104a. The degree of oxygen deficiency is the degree (ratio) of oxygen deficiency in the stoichiometric composition.
　なお、上述したように第２の酸化物層１０４ｂに含まれる第２の遷移金属の標準電極電位が第１の酸化物層１０４ａに含まれる第１の遷移金属の標準電極電位よりも小さい場合、酸化度は自然と第２の酸化物層１０４ｂの方が第１の酸化物層１０４ａよりも大きくなる。そのため、例えば半導体製造プロセス時にサーマルバジェットが拡大しても、抵抗変化膜中の酸素濃度プロファイルの崩れを抑制することができるという利点もある。このことは、大容量化を目指した多層化構造のクロスポイント型の不揮発性記憶装置への適用を容易にする等の効果をもたらすことになる。 As described above, when the standard electrode potential of the second transition metal contained in the second oxide layer 104b is smaller than the standard electrode potential of the first transition metal contained in the first oxide layer 104a, The degree of oxidation is naturally higher in the second oxide layer 104b than in the first oxide layer 104a. Therefore, for example, even if the thermal budget is enlarged during the semiconductor manufacturing process, there is an advantage that the collapse of the oxygen concentration profile in the resistance change film can be suppressed. This brings about an effect of facilitating application to a cross-point type non-volatile memory device having a multi-layered structure aiming at large capacity.
　ところで、J.McPherson et al., IEDM 2002, p.633-636（非特許文献４）の図１に示されているように、酸化物層の絶縁破壊電界の強度（Breakdown Strength）と誘電率との間には、誘電率が大きいほど絶縁破壊電界の強度が小さくなるという相関関係が見られる。このことから、不揮発性記憶素子のブレイク電圧を減少させるためには、絶縁破壊電界の強度を小さくするために、第２の酸化物層１０４ｂの誘電率が、第１の酸化物層１０４ａの誘電率よりも大きいことが望ましいといえる。これにより、より低いブレイク電圧で、安定した抵抗変化動作を行うことが可能な不揮発性記憶素子を実現することができる。 By the way, as shown in FIG. 1 of J. McPherson et al., IEDM 2002, p. 633-636 (Non-patent Document 4), the breakdown field strength (Breakdown Strength) of the oxide layer and the dielectric constant There is a correlation that the strength of the dielectric breakdown field decreases as the dielectric constant increases. Therefore, in order to reduce the break voltage of the nonvolatile memory element, the dielectric constant of the second oxide layer 104b is set to be the dielectric constant of the first oxide layer 104a in order to reduce the strength of the breakdown electric field. It can be said that it is desirable to be larger than the rate. Thereby, a nonvolatile memory element capable of performing a stable resistance change operation with a lower break voltage can be realized.
　なお、第２の酸化物層１０４ｂの絶縁破壊電界の強度を小さくすることによってブレイク電圧が低くなる理由は、次の通りである。つまり、遷移金属酸化物層の積層構造からなる抵抗変化層をもつ不揮発性記憶素子の初期状態は、抵抗率の高い第２の酸化物層１０４ｂによって定まる、極めて高い抵抗値をもつ高抵抗状態にある。よって、この初期状態を破壊する初期ブレイクを行うためには、第２の酸化物層１０４ｂに対して絶縁破壊を行う必要がある。よって、第２の酸化物層１０４ｂの絶縁破壊電界の強度を小さくすることによって、初期ブレイクに要する電圧、つまり、ブレイク電圧が低くなる。 The reason why the break voltage is lowered by reducing the strength of the dielectric breakdown electric field of the second oxide layer 104b is as follows. That is, the initial state of the nonvolatile memory element having the variable resistance layer formed of the laminated structure of the transition metal oxide layer is a high resistance state having an extremely high resistance value determined by the second oxide layer 104b having a high resistivity. is there. Therefore, in order to perform the initial break that destroys the initial state, it is necessary to perform dielectric breakdown on the second oxide layer 104b. Therefore, by reducing the strength of the dielectric breakdown electric field of the second oxide layer 104b, the voltage required for the initial break, that is, the break voltage is lowered.
　また、同じく上記非特許文献４の図２に示されているように、酸化物層の絶縁破壊電界とバンドギャップとの間には、バンドギャップが大きいほど絶縁破壊電界の強度が大きくなるという相関関係が見られる。このことから、不揮発性記憶素子のブレイク電圧を減少させるためには、絶縁破壊電界の強度を小さくするために、第２の酸化物層１０４ｂのバンドギャップが、第１の酸化物層１０４ａのバンドギャップよりも小さいことが望ましいといえる。 Similarly, as shown in FIG. 2 of Non-Patent Document 4, the correlation between the breakdown electric field and the band gap of the oxide layer increases as the band gap increases. Relationship is seen. Therefore, in order to reduce the break voltage of the nonvolatile memory element, the band gap of the second oxide layer 104b is less than the band of the first oxide layer 104a in order to reduce the strength of the breakdown electric field. It can be said that it is desirable to be smaller than the gap.
　以上のことから、ブレイク電圧を低減させるために、本実施の形態における不揮発性記憶素子１００では、（１）第２の酸化物層１０４ｂの誘電率が第１の酸化物層１０４ａの誘電率よりも大きい、及び、（２）第２の酸化物層１０４ｂのバンドギャップが第１の酸化物層１０４ａのバンドギャップよりも小さい、の少なくとも一方が満たされているように、それぞれの材料が選択されている。 From the above, in order to reduce the break voltage, in the nonvolatile memory element 100 in this embodiment, (1) the dielectric constant of the second oxide layer 104b is higher than the dielectric constant of the first oxide layer 104a. And (2) at least one of the band gap of the second oxide layer 104b is smaller than the band gap of the first oxide layer 104a is selected. ing.
　以下の表１に、各種の遷移金属の物性値についてのデータをまとめる。 Table 1 below summarizes the data on physical properties of various transition metals.
Figure JPOXMLDOC01-appb-T000001
Figure JPOXMLDOC01-appb-T000001
　この表１における各遷移金属の標準電極電位に関するデータは、“Lange’s Handbook Of Chemistry”及び“CRC Handbook of Chemistry And Physics”に記載されているものである。また、Ｓｒ（ストロンチウム）、Ａｌ（アルミニウム）、Ｔｉ（チタン）、Ｈｆ（ハフニウム）、Ｚｒ（ジルコニウム）、Ｎｂ（ニオブ）、及びＴａ（タンタル）の酸化物の物性値についての参考文献は以下の表２に示すとおりである。 The data relating to the standard electrode potential of each transition metal in Table 1 are described in “Lange ’s Handbook” Of “Chemistry” and “CRC Handbook” of “Chemistry” And “Physics”. References on the physical property values of oxides of Sr (strontium), Al (aluminum), Ti (titanium), Hf (hafnium), Zr (zirconium), Nb (niobium), and Ta (tantalum) are as follows. As shown in Table 2.
Figure JPOXMLDOC01-appb-T000002
Figure JPOXMLDOC01-appb-T000002
　上記の標準電極電位、誘電率、及びバンドギャップに関する考察に基づけば、第１の酸化物層１０４ａがＴａＯｘ、ＮｉＯｘ、ＷＯｘ、ＣｏＯｘ又はＦｅＯｘ等の酸化物で構成され、第２の酸化物層１０４ｂがＴｉＯ２、ＳｒＴｉＯ３又はＮｂ２Ｏ５等の酸化物で構成されていることが望ましいといえる。 Based on the above consideration regarding the standard electrode potential, dielectric constant, and band gap, the first oxide layer 104a is composed of an oxide such as TaO x , NiO x , WO x , CoO x, or FeO x , and the second It can be said that the oxide layer 104b is preferably made of an oxide such as TiO 2 , SrTiO 3, or Nb 2 O 5 .
　特に、第１の酸化物層１０４ａがＴａＯｘ（０．８≦ｘ≦１．９）である場合には、第２の酸化物層１０４ｂとして、ＴｉＯ２、ＳｒＴｉＯ３及びＮｂ２Ｏ５が好ましい。これらの組み合わせでは、上記表１から分かるように、第２の酸化物層１０４ｂを構成する第２の遷移金属の標準電極電位が第１の酸化物層１０４ａを構成する第１の遷移金属の標準電極電位よりも小さく、しかも、（１）第２の酸化物層１０４ｂの誘電率が第１の酸化物層１０４ａの誘電率よりも大きい、及び、（２）第２の酸化物層１０４ｂのバンドギャップが第１の酸化物層１０４ａのバンドギャップよりも小さい、の両方が満たされるからである。なお、ＴａＯｘ（０．８≦ｘ≦１．９）の物性値は、上記表１におけるＴａ２Ｏ５の物性値と略同じ、あるいは、わずかに小さい値と予想される。 In particular, when the first oxide layer 104a is TaO x (0.8 ≦ x ≦ 1.9), TiO 2 , SrTiO 3 and Nb 2 O 5 are preferable as the second oxide layer 104b. . In these combinations, as can be seen from Table 1 above, the standard electrode potential of the second transition metal constituting the second oxide layer 104b is the standard of the first transition metal constituting the first oxide layer 104a. (1) the dielectric constant of the second oxide layer 104b is larger than the dielectric constant of the first oxide layer 104a, and (2) the band of the second oxide layer 104b. This is because the gap is smaller than the band gap of the first oxide layer 104a. The physical property value of TaO x (0.8 ≦ x ≦ 1.9) is expected to be substantially the same as or slightly smaller than the physical property value of Ta 2 O 5 in Table 1 above.
　［第１の酸化物層及び第２の酸化物層の厚み］
　本実施の形態においては、第１の酸化物層１０４ａ及び第２の酸化物層１０４ｂの厚みにより、抵抗変化層１０４全体の抵抗値を制御することが可能である。そこで、これらの厚みについて検討すると、高抵抗層である第２の酸化物層１０４ｂの厚みが大きすぎる場合、抵抗変化層１０４の初期抵抗値が高くなってしまうため、抵抗変化を開始させることが困難になったり、初期ブレイクが必須となったりする等の不都合が生じる。他方、その厚みが小さすぎると安定した抵抗変化動作が得られないという問題が生じ得る。以上を考慮すれば、少なくとも第２の酸化物層１０４ｂの厚みが第１の酸化物層１０４ａの厚みよりも小さいことが望ましいといえる。 [Thicknesses of the first oxide layer and the second oxide layer]
In this embodiment, the resistance value of the entire resistance change layer 104 can be controlled by the thicknesses of the first oxide layer 104a and the second oxide layer 104b. Therefore, when considering these thicknesses, if the thickness of the second oxide layer 104b, which is a high resistance layer, is too large, the initial resistance value of the resistance change layer 104 becomes high, so that the resistance change can be started. Inconveniences such as difficulty and initial break become essential. On the other hand, if the thickness is too small, there may be a problem that a stable resistance changing operation cannot be obtained. Considering the above, it can be said that at least the thickness of the second oxide layer 104b is desirably smaller than the thickness of the first oxide layer 104a.
　［電極の材料］
　次に、本実施の形態の不揮発性記憶素子１００における第２電極層１０５に用いられる好適な材料について検討する。 [Electrode material]
Next, a suitable material used for the second electrode layer 105 in the nonvolatile memory element 100 of this embodiment is examined.
　発明者等は、２種類の酸素不足型遷移金属酸化物を抵抗変化層として用いて、以下の実験を行った。なお、ここで酸素不足型遷移金属酸化物とは、遷移金属をＡとし、酸化物をＡＯｘと表したときに、ｘが非化学量論比で表され、酸素が化学量論比組成から不足している酸化物をいう。 The inventors conducted the following experiment using two types of oxygen-deficient transition metal oxides as a resistance change layer. Here, the oxygen-deficient transition metal oxide means that when the transition metal is A and the oxide is represented by AO x , x is represented by a non-stoichiometric ratio, and oxygen is derived from the stoichiometric composition. This refers to the missing oxide.
　まず、酸素不足型タンタル酸化物を下部電極（第１電極）及び上部電極（第２電極）で挟んで形成された第１サンプル素子と、酸素不足型ハフニウム酸化物を同じく挟んで形成された第２サンプル素子とを作製した。ここで、第１電極の材料はＷ（タングステン）に固定し、第２電極の材料を以下の表３及び表４に示す複数種類の材料に変化させた。表３は第１サンプル素子の構成を、表４は第２サンプル素子の構成をそれぞれ示している。なお、第１電極の材料をＷに固定したのは、Ｗが比較的酸化されにくく、安定した材料であり、しかも加工が比較的容易であることによる。 First, a first sample element formed by sandwiching an oxygen-deficient tantalum oxide between a lower electrode (first electrode) and an upper electrode (second electrode), and a second sample formed by sandwiching an oxygen-deficient hafnium oxide in the same manner. Two sample elements were produced. Here, the material of the first electrode was fixed to W (tungsten), and the material of the second electrode was changed to a plurality of types of materials shown in Tables 3 and 4 below. Table 3 shows the configuration of the first sample element, and Table 4 shows the configuration of the second sample element. The reason why the material of the first electrode is fixed to W is that W is relatively resistant to oxidation, is a stable material, and is relatively easy to process.
Figure JPOXMLDOC01-appb-T000003
Figure JPOXMLDOC01-appb-T000003
Figure JPOXMLDOC01-appb-T000004
Figure JPOXMLDOC01-appb-T000004
　本発明者等は、上記の第１及び第２サンプル素子の抵抗変化の様子を調べた。表３に示す第１サンプル素子における抵抗変化の測定では、試料においては多少の差異があるものの、高抵抗化させるときの電圧パルスを＋１．８乃至＋２．５Ｖ、１００ｎｓとし、低抵抗化させるときの電圧パルスを－１．３Ｖ乃至－１．６Ｖ、１００ｎｓとした。表４に示す第２サンプル素子の場合では、高抵抗化させるときの電圧パルスを＋１．６乃至＋１．９Ｖ、１００ｎｓとし、低抵抗化させるときの電圧パルスを－１．１Ｖ乃至－１．３Ｖ、１００ｎｓとした。 The inventors examined the state of resistance change of the first and second sample elements. In the measurement of the resistance change in the first sample element shown in Table 3, although there are some differences in the sample, the voltage pulse when increasing the resistance is +1.8 to +2.5 V, 100 ns and the resistance is decreased The voltage pulse of −1.3V to −1.6V was set to 100 ns. In the case of the second sample element shown in Table 4, the voltage pulse when the resistance is increased is +1.6 to +1.9 V and 100 ns, and the voltage pulse when the resistance is decreased is −1.1 V to −1.3 V. 100 ns.
　表３及び表４に示す素子における測定結果を図６乃至図２１に示す。また、これらの測定結果をまとめて図５に示す。つまり、図５には、図６乃至図２１に示された合計１６個のグラフが縮小化されて配置されている。 The measurement results for the elements shown in Tables 3 and 4 are shown in FIGS. These measurement results are collectively shown in FIG. That is, in FIG. 5, a total of 16 graphs shown in FIGS. 6 to 21 are reduced and arranged.
　図５は、酸素不足型遷移金属酸化物を構成する遷移金属の標準電極電位ＥＴと電極材料の標準電極電位ＥＥとの差異（ＥＥ－ＥＴ）と、酸素不足型金属酸化物の抵抗変化（配置されている小さい各グラフ）との相関を示すグラフである。図５の上段に配置された７個のグラフは、第２サンプル素子（ＨｆＯｘ）に関する相関を示し、図５の下段に配置された９個のグラフは、第１サンプル素子（ＴａＯｘ）に関する相関を示す。また、図６乃至図１４は、第１サンプル素子における電圧パルスの印加回数に応じた抵抗変化の様子を示すグラフである。より具体的に説明すると、図６乃至図１４は、Ｔａ－Ａ（白金）、Ｔａ－Ｂ（イリジウム）、Ｔａ－Ｃ（銀）、Ｔａ－Ｄ（銅）、Ｔａ－Ｅ（ニッケル）、Ｔａ－Ｆ（タングステン）、Ｔａ－Ｇ（タンタル）、Ｔａ－Ｈ（チタン）及びＴａ－Ｉ（アルミニウム）における測定結果をそれぞれ示している。さらに、図１５乃至図２１は、第２サンプル素子における電圧パルスの印加回数に応じた抵抗変化の様子を示すグラフである。より具体的に説明すると、図１５乃至図２１は、Ｈｆ－Ａ（白金）、Ｈｆ－Ｂ（銅）、Ｈｆ－Ｃ（タングステン）、Ｈｆ－Ｄ（タンタル）、Ｈｆ－Ｅ（ハフニウム）、Ｈｆ－Ｆ（チタン）及びＨｆ－Ｇ（アルミニウム）における測定結果をそれぞれ示している。なお、図６乃至図２１におけるグラフの上部には、第２電極材料と（ＥＥ－ＥＴ）とが示されている。 Figure 5 is a difference between the standard electrode potential E E standard electrode potential E T and the electrode material of a transition metal forming the oxygen-deficient transition metal oxide (E E -E T), an oxygen-deficient metal oxide It is a graph which shows a correlation with resistance change (small each graph arrange | positioned). The seven graphs arranged in the upper part of FIG. 5 show the correlation regarding the second sample element (HfO x ), and the nine graphs arranged in the lower part of FIG. 5 relate to the first sample element (TaO x ). Show correlation. FIGS. 6 to 14 are graphs showing the state of resistance change according to the number of voltage pulse applications in the first sample element. More specifically, FIGS. 6 to 14 show Ta-A (platinum), Ta-B (iridium), Ta-C (silver), Ta-D (copper), Ta-E (nickel), Ta The measurement results for -F (tungsten), Ta-G (tantalum), Ta-H (titanium), and Ta-I (aluminum) are shown. Further, FIG. 15 to FIG. 21 are graphs showing the state of resistance change according to the number of voltage pulse applications in the second sample element. More specifically, FIGS. 15 to 21 show Hf—A (platinum), Hf—B (copper), Hf—C (tungsten), Hf—D (tantalum), Hf—E (hafnium), Hf. The measurement results for -F (titanium) and Hf-G (aluminum) are shown. Note that the second electrode material and (E E -E T ) are shown at the top of the graphs in FIGS.
　図５の横軸における０ｅＶより左側に配置されたグラフから分かるように、電極材料の標準電極電位ＥＥと、酸素不足型遷移金属酸化物の遷移金属の標準電極電位ＥＴとの関係において、ＥＥ－ＥＴ≦０を満足する電極材料を用いた素子は抵抗変化現象を示さなかった。 As can be seen from the graph that is disposed on the left side of 0eV on the horizontal axis in FIG. 5, and the standard electrode potential E E of the electrode material in relation to the standard electrode potential E T of transition metal oxygen deficient transition metal oxide, The element using the electrode material satisfying E E −E T ≦ 0 did not show the resistance change phenomenon.
　すなわち、図５、図１２、図１３及び図１４に示すように、酸素不足型タンタル酸化物を用いた素子のうち、第２電極にＴａを用いた素子Ｔａ－Ｇ、同じくＴｉを用いたＴａ－Ｈ、同じくＡｌを用いたＴａ－Ｉでは、抵抗変化現象が全く観測されなかった。 That is, as shown in FIG. 5, FIG. 12, FIG. 13 and FIG. 14, among the elements using oxygen-deficient tantalum oxide, the element Ta-G using Ta for the second electrode, and Ta using Ti as well. In Ta-I using -H, also Al, no resistance change phenomenon was observed.
　同様にして、図５、図１９、図２０及び図２１に示すように、酸素不足型ハフニウム酸化物を用いた素子のうち、第２電極にＨｆを用いた素子Ｈｆ－Ｅ、同じくＴｉを用いた素子Ｈｆ－Ｆ、同じくＡｌを用いた素子Ｈｆ－Ｇでは、抵抗変化現象が全く観測されなかった。 Similarly, as shown in FIGS. 5, 19, 20, and 21, among elements using oxygen-deficient hafnium oxide, element Hf-E using Hf for the second electrode, and also using Ti. In the device Hf-F, and the device Hf-G using Al as well, no resistance change phenomenon was observed.
　反対に、図５の横軸における０より右側に配置されたグラフから分かるように、ＥＥ－ＥＴ＞０を満足する電極材料を用いた素子については、正負の電圧パルスを交互に繰り返し印加すると、それに応じて抵抗値が変化し、不揮発性記憶素子の機能を有していることを確認することができた。このことから、第２の酸化物層１０４ｂと接する第２電極層１０５の標準電極電位が第２の酸化物層１０４ｂを構成する第２の遷移金属の標準電極電位よりも大きいことが必要とされることが分かる。 On the other hand, as can be seen from the graph arranged on the right side of 0 on the horizontal axis in FIG. 5, positive and negative voltage pulses are alternately applied repeatedly to an element using an electrode material that satisfies E E −E T > 0. Then, the resistance value was changed accordingly, and it was confirmed that the nonvolatile memory element had a function. Therefore, the standard electrode potential of the second electrode layer 105 in contact with the second oxide layer 104b is required to be larger than the standard electrode potential of the second transition metal constituting the second oxide layer 104b. I understand that
　次に、これらの抵抗変化を示した素子の抵抗変化の安定性について考察する。 Next, the stability of the resistance change of the element showing these resistance changes will be considered.
　図５及び図１１に示すように、酸素不足型タンタル酸化物を用いた素子のうち、第２電極にＷを用いた素子Ｔａ－Ｆ（ＥＥ－ＥＴ＝０．７ｅＶ）では、抵抗変化が少し見られたものの、その変化幅は小さい。これに対し、図５及び図９に示すように、第２電極にＣｕを用いた素子Ｔａ－Ｄ（ＥＥ－ＥＴ＝１．１２ｅＶ）については、正負の電圧パルスを交互に繰り返し印加すると、変化幅で１桁以上、回数で２０回以上の抵抗値の変化が観測され、安定的に抵抗変化していることが分かる。同様にして、図５乃至図８に示すように、第２電極にＡｇを用いた素子Ｔａ－Ｃ（ＥＥ－ＥＴ＝１．４０ｅＶ）、同じくＰｔを用いた素子Ｔａ－Ａ（ＥＥ－ＥＴ＝1．７８ｅＶ）、同じくＩｒを用いた素子Ｔａ－Ｂ（ＥＥ－ＥＴ＝１．７７ｅＶ）についても、正負の電圧パルスを交互に繰り返し印加すると、変化幅で１桁以上、回数で２０回以上の抵抗値の変化が観測され、安定的に抵抗変化していることが分かる。 As shown in FIGS. 5 and 11, among the elements using the oxygen-deficient tantalum oxide, the resistance change is observed in the element Ta-F (E E -E T = 0.7 eV) using W as the second electrode. Although a little is seen, the change width is small. On the other hand, as shown in FIGS. 5 and 9, for the element Ta-D (E E -E T = 1.12 eV) using Cu as the second electrode, positive and negative voltage pulses are alternately applied repeatedly. The change in the resistance value is observed by one digit or more in the change width and 20 or more times in the number of times, and it can be seen that the resistance change is stable. Similarly, as shown in FIGS. 5 to 8, the element Ta—C (E E −E T = 1.40 eV) using Ag for the second electrode and the element Ta—A (E E ) using Pt as well. -E T = 1.78 eV), and also for the element Ta-B using the same Ir (E E -E T = 1.77 eV), when positive and negative voltage pulses are alternately applied, the change width is one digit or more. A change in resistance value of 20 times or more was observed, indicating that the resistance change was stable.
　また、図５及び図１８に示すように、酸素不足型ハフニウム酸化物を用いた素子のうち、第２電極にＴａを用いた素子Ｈｆ－Ｄ（ＥＥ－ＥＴ＝０．９５ｅＶ）では、抵抗変化が少し見られたものの、その変化幅は小さい。これに対し、図５及び図１７に示すように、第２電極にＷを用いた素子Ｈｆ－Ｃ（ＥＥ－ＥＴ＝１．６５ｅＶ）については、正負の電圧パルスを交互に繰り返し印加すると、変化幅で１桁以上、回数で２０回以上の抵抗値の変化が観測され、安定的に抵抗変化していることが分かる。同様にして、図５、図１５及び図１６に示すように、第２電極にＣｕを用いた素子Ｈｆ－Ｂ（ＥＥ－ＥＴ＝２．０７ｅＶ）、同じくＰｔを用いた素子Ｈｆ－Ａ（ＥＥ－ＥＴ＝２．７３ｅＶ）についても、正負の電圧パルスを交互に繰り返し印加すると、変化幅で１桁以上、回数で２０回以上の抵抗値の変化が観測され、安定的に抵抗変化していることが分かる。 Also, as shown in FIGS. 5 and 18, among the elements using oxygen-deficient hafnium oxide, the element Hf-D (E E -E T = 0.95 eV) using Ta for the second electrode: Although there was a slight change in resistance, the range of change was small. On the other hand, as shown in FIGS. 5 and 17, for the element Hf-C (E E -E T = 1.65 eV) using W for the second electrode, positive and negative voltage pulses are alternately applied repeatedly. The change in the resistance value is observed by one digit or more in the change width and 20 or more times in the number of times, and it can be seen that the resistance change is stable. Similarly, as shown in FIG. 5, FIG. 15 and FIG. 16, the element Hf-B (E E -E T = 2.07 eV) using Cu for the second electrode, and the element Hf-A also using Pt As for (E E -E T = 2.73 eV), when positive and negative voltage pulses are alternately applied repeatedly, a change in resistance value of one digit or more in change width and 20 or more times in change is observed, and stable resistance You can see that it is changing.
　ここで、図５及び図１２に示すように、酸素不足型タンタル酸化物を用いた素子のうち、第２電極にＴａを用いた素子Ｔａ－Ｇ（ＥＥ－ＥＴ＝０ｅＶ）では、抵抗変化現象が全く観測されなかったのに対し、図５及び図１０に示すように、第２電極にＮｉを用いた素子Ｔａ－Ｅ（ＥＥ－ＥＴ＝０．３４ｅＶ）では、若干の抵抗変化が見られたことから、酸素不足型タンタル酸化物を用いた素子が抵抗変化動作を行うためには、ＥＥ－ＥＴ＝０．３４ｅＶの条件（あるいは、ＥＥ－ＥＴ≧０．３４ｅＶの条件）を満足することが望ましいと考えられる。 Here, as shown in FIG. 5 and FIG. 12, among the elements using the oxygen-deficient tantalum oxide, the element Ta-G (E E -E T = 0 eV) using Ta for the second electrode has resistance. While no change phenomenon was observed, as shown in FIGS. 5 and 10, in the element Ta-E (E E -E T = 0.34 eV) using Ni for the second electrode, a slight resistance was observed. Since the change was observed, in order for the element using the oxygen-deficient tantalum oxide to perform the resistance change operation, the condition of E E −E T = 0.34 eV (or E E −E T ≧ 0. 34 eV) is considered desirable.
　また、図５及び図１１に示すように、第２電極にＷを用いた素子Ｔａ－Ｆ（ＥＥ－ＥＴ＝０．７ｅＶ）では、若干の抵抗変化が見られたもののその変化幅が小さいのに対し、図５及び図９に示すように、第２電極にＣｕを用いた素子Ｔａ－Ｄ（ＥＥ－ＥＴ＝１．１２ｅＶ）については、変化幅で１桁以上、回数で２０回以上の抵抗値の変化が確認されることから、酸素不足型タンタル酸化物を用いた素子が安定して抵抗変化動作を行うためには、ＥＥ－ＥＴ＝１．１２ｅＶの条件（あるいは、ＥＥ－ＥＴ≧１．１２ｅＶの条件）を満足することが望ましいと考えられる。 Further, as shown in FIG. 5 and FIG. 11, in the element Ta-F (E E -E T = 0.7 eV) using W for the second electrode, although a slight resistance change was observed, the change width was as follows. On the other hand, as shown in FIG. 5 and FIG. 9, the element Ta-D (E E -E T = 1.12 eV) using Cu for the second electrode has a change width of one digit or more and the number of times. Since the change of the resistance value is confirmed 20 times or more, in order for the element using the oxygen-deficient tantalum oxide to stably perform the resistance changing operation, the condition of E E −E T = 1.12 eV ( Alternatively, it may be desirable to satisfy the condition of E E −E T ≧ 1.12 eV.
　さらに、図５及び図１８に示すように、第２電極にＴａを用いた素子Ｈｆ－Ｄ（ＥＥ－ＥＴ＝０．９５ｅＶ）では、上述したように若干の抵抗変化が見られたもののその変化幅が小さいのに対し、図５及び図１７に示すように、第２電極にＷを用いた素子Ｈｆ－Ｃ（ＥＥ－ＥＴ＝１．６５ｅＶ）については、上述したように変化幅で１桁以上、回数で２０回以上の抵抗値の変化が確認されることから、酸素不足型ハフニウム酸化物を用いた素子が安定して抵抗変化動作を行うためには、ＥＥ－ＥＴ＝１．６５ｅＶの条件（あるいは、ＥＥ－ＥＴ≧１．６５ｅＶの条件）を満足することが望ましいと考えられる。 Further, as shown in FIGS. 5 and 18, in the element Hf-D (E E −E T = 0.95 eV) using Ta for the second electrode, a slight resistance change was observed as described above. While the change width is small, as shown in FIGS. 5 and 17, the element Hf-C using W for the second electrode (E E -E T = 1.65 eV) changes as described above. Since the change in the resistance value is confirmed by one digit or more in width and 20 or more times in number, in order for the element using the oxygen-deficient hafnium oxide to stably perform the resistance changing operation, E E -E It is considered desirable to satisfy the condition of T = 1.65 eV (or the condition of E E −E T ≧ 1.65 eV).
　このように、素子の安定した抵抗変化動作を実現するためには、酸素不足型遷移金属酸化物を構成する遷移金属の標準電極電位と電極材料の標準電極電位との関係が重要になってくる。 Thus, in order to realize stable resistance change operation of the element, the relationship between the standard electrode potential of the transition metal constituting the oxygen-deficient transition metal oxide and the standard electrode potential of the electrode material becomes important. .
　図５に示すように、酸素不足型遷移金属酸化物を構成する遷移金属の標準電極電位と電極材料の標準電極電位との差異に対して、酸素不足型遷移金属酸化物の抵抗変化をプロットすると、両者には良好な相関があることを確認することができる。すなわち、抵抗変化層を構成する遷移金属であるＴａ、Ｈｆよりも標準電極電位が大きい材料で電極を構成した場合には抵抗変化が起こっており、反対に小さい材料で電極を構成した場合には抵抗変化が起こりにくくなっていることが分かる。そして、遷移金属の標準電極電位と電極材料の標準電極電位との差異が大きいほど抵抗変化が起こりやすく、反対に小さいほど抵抗変化が起こりにくくなっていることが分かる。 As shown in FIG. 5, when the resistance change of the oxygen-deficient transition metal oxide is plotted against the difference between the standard electrode potential of the transition metal constituting the oxygen-deficient transition metal oxide and the standard electrode potential of the electrode material, It can be confirmed that there is a good correlation between the two. That is, when the electrode is made of a material whose standard electrode potential is larger than that of Ta and Hf which are transition metals constituting the resistance change layer, the resistance change occurs. On the other hand, when the electrode is made of a small material, It can be seen that resistance change is less likely to occur. It can be seen that the resistance change is more likely to occur as the difference between the standard electrode potential of the transition metal and the standard electrode potential of the electrode material is larger, and the resistance change is less likely to occur as the difference is smaller.
　このことは、上述した抵抗変化のメカニズムの推論と符合する。すなわち、上述したように、抵抗変化層に含まれる遷移金属が酸化されやすい場合に抵抗変化が起こりやすいと考えられるため、電極材料と比べて酸化されやすい（つまり、標準電極電位が小さい）遷移金属を含む酸化物層を抵抗変化層の電極側界面に用いることにより、安定した抵抗変化動作を実現することが可能になるといえる。よって、第２電極の標準電極電位は、第２の酸化物層を構成する遷移金属の標準電極電位よりも大きいことが望ましいだけでなく、第１の酸化物層を構成する遷移金属の標準電極電位よりも大きいことが望ましい。 This is consistent with the inference of the resistance change mechanism described above. That is, as described above, since the resistance change is likely to occur when the transition metal contained in the variable resistance layer is easily oxidized, the transition metal is easily oxidized (that is, the standard electrode potential is small) compared to the electrode material. It can be said that a stable resistance change operation can be realized by using an oxide layer containing a metal at the electrode side interface of the resistance change layer. Therefore, it is desirable that the standard electrode potential of the second electrode is larger than the standard electrode potential of the transition metal that constitutes the second oxide layer, and the standard electrode of the transition metal that constitutes the first oxide layer. It is desirable that it be greater than the potential.
　上記の内容から、本実施の形態の不揮発性記憶素子１００において、第２の酸化物層１０４ｂを構成する遷移金属と比較して標準電極電位が大きい材料を用いて第２電極層１０５を構成することが望ましいといえる。例えば、本実施の形態では、第２の酸化物層１０４ｂを構成する遷移金属はＴｉであるため、これよりも標準電極電位の大きい材料を用いることが望ましく、具体的にはＷ、Ｃｕ及びＮｉ等を用いることが可能である。これらのＷ、Ｃｕ及びＮｉ等は、Ａｕ、Ｐｔ及びＩｒ等の貴金属系の電極材料と比べると標準電極電位は大きくないが、Ｔｉの標準電極電位が比較的小さいため、第２電極層１０５の材料として用いることができる。Ｗ、Ｃｕ及びＮｉ等は半導体プロセスに親和性のある低コストの材料であるため、不揮発性記憶素子１００の製造コストの低減化を図ることが可能になる。 From the above contents, in the nonvolatile memory element 100 of this embodiment, the second electrode layer 105 is formed using a material having a higher standard electrode potential than the transition metal included in the second oxide layer 104b. Is desirable. For example, in this embodiment, since the transition metal constituting the second oxide layer 104b is Ti, it is desirable to use a material having a standard electrode potential larger than this, specifically W, Cu, and Ni. Etc. can be used. These W, Cu, Ni, and the like do not have a large standard electrode potential as compared with noble metal-based electrode materials such as Au, Pt, and Ir, but the standard electrode potential of Ti is relatively small. It can be used as a material. Since W, Cu, Ni, and the like are low-cost materials that are compatible with semiconductor processes, the manufacturing cost of the nonvolatile memory element 100 can be reduced.
　［負荷素子が接続される構成について］
　不揮発性記憶素子は、固定抵抗、トランジスタ及びダイオード等の負荷素子に直列に接続されて用いられる場合がある（後述する実施の形態２及び３には、その具体例が記載されている）。このように負荷素子が接続されている場合では、不揮発性記憶素子単体の場合と比べてブレイク電圧が高くなるという問題が生じる。これは、負荷素子に電圧降下が生じることにより、不揮発性記憶素子に実効的に印加される電圧が小さくなってしまうためである。 [Configuration with load elements connected]
The nonvolatile memory element may be used by being connected in series to a load element such as a fixed resistor, a transistor, and a diode (specific examples are described in Embodiments 2 and 3 to be described later). When the load element is connected in this way, there arises a problem that the break voltage becomes higher than that in the case of the nonvolatile memory element alone. This is because the voltage that is effectively applied to the non-volatile memory element is reduced due to a voltage drop in the load element.
　本発明者等は、上記の問題を確認すべく、以下の実験を行った。 The present inventors conducted the following experiment in order to confirm the above problem.
　なお、この実験用の不揮発性記憶素子（以下、実験素子という）は次のようにして作製された。まず、シリコン基板上に形成された酸化物層の上に、第１電極層としてのＴａＮ薄膜を形成し、さらにその上に、Ｔａターゲットを用いた反応性スパッタリング法で第１のタンタル酸化物層を形成した。次に、その第１のタンタル酸化物層の最表面を酸素プラズマにより酸化することにより、第１のタンタル酸化物層よりも酸素含有率の高い第２のタンタル酸化物層を形成した。そして、その第２のタンタル酸化物層上に、第２電極層としてのＩｒ薄膜をスパッタリング法により形成した。このような工程により、第１電極層、第１のタンタル酸化物層（ＴａＯ１．６）、第２のタンタル酸化物層（ＴａＯ２．４７）、及び第２電極層が積層されてなる実験素子を作製した。 This experimental nonvolatile memory element (hereinafter referred to as experimental element) was fabricated as follows. First, a TaN thin film as a first electrode layer is formed on an oxide layer formed on a silicon substrate, and a first tantalum oxide layer is formed thereon by reactive sputtering using a Ta target. Formed. Next, a second tantalum oxide layer having an oxygen content higher than that of the first tantalum oxide layer was formed by oxidizing the outermost surface of the first tantalum oxide layer with oxygen plasma. Then, an Ir thin film as a second electrode layer was formed on the second tantalum oxide layer by a sputtering method. Experiments in which the first electrode layer, the first tantalum oxide layer (TaO 1.6 ), the second tantalum oxide layer (TaO 2.47 ), and the second electrode layer are stacked through such a process. An element was produced.
　この実験素子では、第１のタンタル酸化物層と、この第１のタンタル酸化物層よりも高抵抗の第２のタンタル酸化物層とで、抵抗変化層が構成されていることになる。 In this experimental element, the variable resistance layer is composed of the first tantalum oxide layer and the second tantalum oxide layer having a higher resistance than the first tantalum oxide layer.
　図２２（ａ）及び（ｂ）は、第２のタンタル酸化物層の厚みを３ｎｍとした場合の実験素子単体（つまり、負荷素子が接続されていない場合）の電気的特性を示すグラフで、図２２（ａ）は電流（縦軸）－電圧（横軸）特性を、図２２（ｂ）は抵抗（縦軸）－電圧（横軸）特性をそれぞれ示している。また、図２３（ａ）及び（ｂ）は、同じく厚みを３ｎｍとした場合であって負荷素子が接続されているときの実験素子の電気的特性を示すグラフで、図２３（ａ）は電流（縦軸）－電圧（横軸）特性を、図２３（ｂ）は抵抗（縦軸）－電圧（横軸）特性をそれぞれ示している。なお、図２２（ｂ）及び図２３（ｂ）において、５０ｍＶで測定した抵抗値を示している。 22 (a) and 22 (b) are graphs showing electrical characteristics of the experimental element alone (that is, when no load element is connected) when the thickness of the second tantalum oxide layer is 3 nm. 22A shows current (vertical axis) -voltage (horizontal axis) characteristics, and FIG. 22B shows resistance (vertical axis) -voltage (horizontal axis) characteristics. 23 (a) and 23 (b) are graphs showing the electrical characteristics of the experimental element when the thickness is 3 nm and the load element is connected. FIG. 23 (a) shows the current. FIG. 23B shows the resistance (vertical axis) -voltage (horizontal axis) characteristics. In addition, in FIG.22 (b) and FIG.23 (b), the resistance value measured at 50 mV is shown.
　図２２（ａ）及び（ｂ）を参照すると分かるように、負荷素子が接続されていない実験素子単体の場合では、－１Ｖ程度の電圧の印加で抵抗変化を開始している。つまり、このケースでは、ブレイク電圧は－１Ｖ程度である。これに対して、図２３（ａ）及び（ｂ）を参照すると分かるように、実験素子に負荷素子（ここでは、１ｋΩの抵抗）が接続されている場合では、－３．５Ｖ程度まで印加電圧を上げないと抵抗変化が始まらない。つまり、このケースでは、ブレイク電圧は－３．５Ｖ程度になっている。図２２（ａ）に示されているように、抵抗変化を開始する－１Ｖ程度の電圧を印加すると２．５ｍＡ程度のリーク電流が流れている。一方、負荷抵抗が接続された状態では、リーク電流が大きい場合、負荷抵抗を流れる電流分だけ電圧降下が生じ、その結果実験素子に実効的に印加される電圧が小さくなってしまう。そのため、上述したように－３．５Ｖ程度まで印加電圧を上げないと抵抗変化が始まらないのである。 As can be seen from FIGS. 22 (a) and 22 (b), in the case of a single experimental element to which no load element is connected, the resistance change is started by applying a voltage of about −1V. That is, in this case, the break voltage is about −1V. On the other hand, as can be seen from FIGS. 23A and 23B, when a load element (here, 1 kΩ resistor) is connected to the experimental element, the applied voltage is up to about −3.5V. The resistance change will not start unless the value is raised. That is, in this case, the break voltage is about −3.5V. As shown in FIG. 22 (a), when a voltage of about −1 V for starting resistance change is applied, a leakage current of about 2.5 mA flows. On the other hand, in the state where the load resistance is connected, if the leakage current is large, a voltage drop is caused by the current flowing through the load resistance, and as a result, the voltage that is effectively applied to the experimental element is reduced. Therefore, as described above, the resistance change does not start unless the applied voltage is increased to about −3.5V.
　図２４は、第２のタンタル酸化物層の厚みｄを変化させたときの抵抗変化層の初期抵抗値とブレイク電圧との関係、及び当該初期抵抗値とリーク電流との関係を示すグラフである。横軸は印加電圧１００ｍＶで測定した抵抗変化層の初期抵抗値、縦軸は、ブレイク電圧あるいはブレイク時に流れるリーク電流を示す。なお、この図２４において、×のプロット点は実験素子に負荷素子が接続されている場合のブレイク電圧を、黒塗り四角のプロット点は実験素子単体の場合のブレイク電圧を、三角のプロット点はリーク電流の電流値（実験素子に負荷素子が接続されている場合、及び、実験素子単体の場合のいずれも共通）を、それぞれ示している。 FIG. 24 is a graph showing the relationship between the initial resistance value of the variable resistance layer and the break voltage when the thickness d of the second tantalum oxide layer is changed, and the relationship between the initial resistance value and the leakage current. . The horizontal axis represents the initial resistance value of the variable resistance layer measured at an applied voltage of 100 mV, and the vertical axis represents the break voltage or the leak current flowing during the break. In FIG. 24, the x plotted points indicate the break voltage when the load element is connected to the experimental element, the black square plot points indicate the break voltage when the experimental element alone, and the triangular plot points indicate The current values of the leak currents (both when the load element is connected to the experimental element and when the experimental element alone is common) are shown.
　図２４に示すように、実験素子単体の場合では（黒塗り四角のプロット点）、第２のタンタル酸化物層の厚みｄが薄いほどブレイク電圧が小さくなっている。これは、抵抗変化の開始が電界により支配されていることを示しているものと思われる。これに対し、実験素子に負荷素子が接続されている場合では（×のプロット点）、第２のタンタル酸化物層の厚みｄを薄くしていくと、４．５ｎｍ程度までは負荷素子が接続されていない実験素子単体のブレイク電圧とほぼ同じ値で小さくなっているが、４．５ｎｍよりもさらに薄くしていくと、リーク電流が大きくなり、実験素子単体に比べてブレイク電圧が大きくなっていることがわかる。このことは、リーク電流を小さくすることができれば、負荷素子が接続された状態でも、ブレイク電圧の上昇を抑制し低電圧で抵抗変化を開始させることが可能であることを示している。 As shown in FIG. 24, in the case of the experimental element alone (black square plot points), the break voltage decreases as the thickness d of the second tantalum oxide layer decreases. This seems to indicate that the onset of resistance change is dominated by the electric field. On the other hand, when the load element is connected to the experimental element (× plotted point), the load element is connected up to about 4.5 nm when the thickness d of the second tantalum oxide layer is decreased. The break voltage of the experimental element alone that has not been reduced is about the same value, but if it is made thinner than 4.5 nm, the leakage current increases and the break voltage becomes larger than that of the experimental element alone. I understand that. This indicates that if the leakage current can be reduced, it is possible to suppress the increase of the break voltage and start the resistance change at a low voltage even when the load element is connected.
　以上より、不揮発性記憶素子に負荷素子が接続されている構成では、不揮発性記憶素子単体の場合と比べて、ブレイク電圧を下げるという要請が高いといえる。本実施の形態の不揮発性記憶素子１００の場合、上述したようにして抵抗変化層及び電極の材料を選択することによってブレイク電圧を下げることができるため、このような要請に応えることが可能である。 From the above, it can be said that in the configuration in which the load element is connected to the nonvolatile memory element, there is a high demand for lowering the break voltage compared to the case of the nonvolatile memory element alone. In the case of the nonvolatile memory element 100 of the present embodiment, the break voltage can be lowered by selecting the material of the resistance change layer and the electrode as described above, so that such a request can be met. .
　［伝導帯オフセット］
　上記の表１には、材料の物性値の一つとして、Ｓｉに対する伝導帯オフセット（ｅＶ）が記載されている。上述したように、不揮発性記憶素子が負荷素子に接続されている場合ではリーク電流が発生するが、この伝導帯オフセットの値が大きい材料を用いて第２の酸化物層を構成することにより、そのリーク電流を低減することができる。 [Conduction band offset]
In Table 1 above, the conduction band offset (eV) with respect to Si is described as one of the physical property values of the material. As described above, when the nonvolatile memory element is connected to the load element, a leakage current is generated, but by configuring the second oxide layer using a material having a large conduction band offset value, The leakage current can be reduced.
　したがって、この観点から検討すると、伝導帯オフセットの値が比較的小さいＴａよりも、その値が比較的大きいＴｉ、Ｓｒ、及びＮｂ等によって第２の酸化物層１０４ｂを構成することが望ましいといえる。つまり、第２の酸化物層１０４ｂを構成する金属として、第２の酸化物層１０４ｂの誘電率及びバンドギャップの観点だけからでなく、伝導帯オフセットの観点からも、Ｔｉ、Ｓｒ、及びＮｂが好ましいことが分かる。 Therefore, from this point of view, it can be said that the second oxide layer 104b is preferably composed of Ti, Sr, Nb, or the like having a relatively large value rather than Ta having a relatively small conduction band offset. . That is, as a metal constituting the second oxide layer 104b, Ti, Sr, and Nb are not only from the viewpoint of the dielectric constant and band gap of the second oxide layer 104b but also from the viewpoint of the conduction band offset. It turns out that it is preferable.
　（実施の形態２）
　次に、本発明の実施の形態２に係る不揮発性記憶装置について説明する。 (Embodiment 2)
Next, a nonvolatile memory device according to Embodiment 2 of the present invention will be described.
　上述した実施の形態１に係る不揮発性記憶素子１００は、種々の形態の不揮発性記憶装置へ適用することが可能である。実施の形態２に係る不揮発性記憶装置は、実施の形態１に係る不揮発性記憶素子を備える不揮発性記憶装置であって、ワード線とビット線との交点（立体交差点）に実施の形態１に係る不揮発性記憶素子を介在させた所謂クロスポイント型のものである。 The nonvolatile memory element 100 according to Embodiment 1 described above can be applied to various types of nonvolatile memory devices. The non-volatile memory device according to the second embodiment is a non-volatile memory device including the non-volatile memory element according to the first embodiment. The non-volatile memory device according to the second embodiment is the same as that of the first embodiment at the intersection (three-dimensional intersection) between the word line and the bit line. This is a so-called cross-point type in which such a nonvolatile memory element is interposed.
　［不揮発性記憶装置の構成］
　図２５は、本発明の実施の形態２に係る不揮発性記憶装置２００の構成を示すブロック図である。また、図２６は、図２５におけるＡ部の構成（４ビット分のメモリセルの物理的な構成）を示す斜視図である。 [Configuration of non-volatile storage device]
FIG. 25 is a block diagram showing a configuration of the nonvolatile memory device 200 according to Embodiment 2 of the present invention. FIG. 26 is a perspective view showing the configuration of part A in FIG. 25 (physical configuration of memory cells for 4 bits).
　図２５に示すように、本実施の形態に係る不揮発性記憶装置２００は、半導体基板上にメモリ本体部２０１を備えており、このメモリ本体部２０１は、メモリセルアレイ２０２と、行選択回路・ドライバ２０３と、列選択回路・ドライバ２０４と、情報の書き込みを行うための書き込み回路２０５と、選択ビット線に流れる電流量を検出し、データ「１」または「０」の判別を行うセンスアンプ２０６と、端子ＤＱを介して入出力データの入出力処理を行うデータ入出力回路２０７とを具備している。 As shown in FIG. 25, the nonvolatile memory device 200 according to the present embodiment includes a memory main body 201 on a semiconductor substrate. The memory main body 201 includes a memory cell array 202, a row selection circuit / driver, and the like. 203, a column selection circuit / driver 204, a write circuit 205 for writing information, a sense amplifier 206 for detecting the amount of current flowing through the selected bit line and discriminating data “1” or “0”; And a data input / output circuit 207 for performing input / output processing of input / output data via a terminal DQ.
　また、不揮発性記憶装置２００は、外部から入力されるアドレス信号を受け取るアドレス入力回路２０８と、外部から入力されるコントロール信号に基づいて、メモリ本体部２０１の動作を制御する制御回路２０９とをさらに備えている。 The nonvolatile memory device 200 further includes an address input circuit 208 that receives an address signal input from the outside, and a control circuit 209 that controls the operation of the memory body 201 based on the control signal input from the outside. I have.
　メモリセルアレイ２０２は、図２５及び図２６に示すように、半導体基板上に互い平行に形成された複数のワード線ＷＬ０，ＷＬ１，ＷＬ２，…と、これらのワード線ＷＬ０，ＷＬ１，ＷＬ２，…の上方にその半導体基板の主面に平行な面内において互いに平行に、しかも複数のワード線ＷＬ０，ＷＬ１，ＷＬ２，…に立体交差するように形成された複数のビット線ＢＬ０，ＢＬ１，ＢＬ２，…とを備えている。 As shown in FIGS. 25 and 26, the memory cell array 202 includes a plurality of word lines WL0, WL1, WL2,... Formed in parallel with each other on a semiconductor substrate and these word lines WL0, WL1, WL2,. A plurality of bit lines BL0, BL1, BL2,... Formed above and parallel to each other in a plane parallel to the main surface of the semiconductor substrate and three-dimensionally intersecting the plurality of word lines WL0, WL1, WL2,. And.
　また、これらのワード線ＷＬ０，ＷＬ１，ＷＬ２，…及びビット線ＢＬ０，ＢＬ１，ＢＬ２，…の交点に対応してマトリクス状に設けられた複数のメモリセルＭ１１１，Ｍ１１２，Ｍ１１３，Ｍ１２１，Ｍ１２２，Ｍ１２３，Ｍ１３１，Ｍ１３２，Ｍ１３３，…（以下、「メモリセルＭ１１１，Ｍ１１２，…」と表す）が設けられている。 Further, a plurality of memory cells M111, M112, M113, M121, M122, M123 provided in a matrix corresponding to the intersections of these word lines WL0, WL1, WL2,... And bit lines BL0, BL1, BL2,. , M131, M132, M133,... (Hereinafter referred to as “memory cells M111, M112,...”).
　ここで、メモリセルＭ１１１，Ｍ１１２，…は、実施の形態１に係る不揮発性記憶素子１００に相当する。ただし、本実施の形態において、これらのメモリセルＭ１１１，Ｍ１１２，…は、後述するように、不揮発性記憶素子１００に直列に接続された電流抑制素子を備えている。 Here, the memory cells M111, M112,... Correspond to the nonvolatile memory element 100 according to the first embodiment. However, in the present embodiment, these memory cells M111, M112,... Have a current suppressing element connected in series to the nonvolatile memory element 100, as will be described later.
　なお、図２５におけるメモリセルＭ１１１，Ｍ１１２，…は、図２６において符号２１０で示されている。 Note that the memory cells M111, M112,... In FIG.
　アドレス入力回路２０８は、外部回路（図示せず）からアドレス信号を受け取り、このアドレス信号に基づいて行アドレス信号を行選択回路・ドライバ２０３へ出力するとともに、列アドレス信号を列選択回路・ドライバ２０４へ出力する。ここで、アドレス信号は、メモリセルアレイ２０２を構成する複数のメモリセルＭ１１１，Ｍ１１２，…のうちの選択される特定のメモリセルのアドレスを示す信号である。また、行アドレス信号はアドレス信号に示されたアドレスのうちの行のアドレスを示す信号であり、列アドレス信号は同じく列のアドレスを示す信号である。 The address input circuit 208 receives an address signal from an external circuit (not shown), outputs a row address signal to the row selection circuit / driver 203 based on the address signal, and outputs a column address signal to the column selection circuit / driver 204. Output to. Here, the address signal is a signal indicating the address of a specific memory cell selected from among the plurality of memory cells M111, M112,... Constituting the memory cell array 202. The row address signal is a signal indicating a row address among the addresses indicated by the address signal, and the column address signal is also a signal indicating a column address.
　制御回路２０９は、情報の書き込みサイクルにおいては、データ入出力回路２０７に入力された入力データＤｉｎに応じて、書き込み用電圧の印加を指示する書き込み信号を書き込み回路２０５へ出力する。他方、情報の読み出しサイクルにおいて、制御回路２０９は、読み出し動作を指示する読み出し信号を列選択回路・ドライバ２０４へ出力する。 In the information write cycle, the control circuit 209 outputs a write signal instructing application of a write voltage to the write circuit 205 according to the input data Din input to the data input / output circuit 207. On the other hand, in the information read cycle, the control circuit 209 outputs a read signal for instructing a read operation to the column selection circuit / driver 204.
　行選択回路・ドライバ２０３は、アドレス入力回路２０８から出力された行アドレス信号を受け取り、この行アドレス信号に応じて、複数のワード線ＷＬ０，ＷＬ１，ＷＬ２，…のうちの何れかを選択し、その選択されたワード線に対して、所定の電圧を印加する。つまり、行選択回路・ドライバ２０３は、メモリセルアレイ２０２が具備する不揮発性記憶素子から、少なくとも一つの不揮発性記憶素子を選択する選択回路の一例である。 The row selection circuit / driver 203 receives the row address signal output from the address input circuit 208, selects one of the plurality of word lines WL0, WL1, WL2,... According to the row address signal, A predetermined voltage is applied to the selected word line. That is, the row selection circuit / driver 203 is an example of a selection circuit that selects at least one nonvolatile memory element from the nonvolatile memory elements included in the memory cell array 202.
　また、列選択回路・ドライバ２０４は、アドレス入力回路２０８から出力された列アドレス信号を受け取り、この列アドレス信号に応じて、複数のビット線ＢＬ０，ＢＬ１，ＢＬ２，…のうちの何れかを選択し、その選択されたビット線に対して、書き込み用電圧または読み出し用電圧を印加する。つまり、列選択回路・ドライバ２０４は、メモリセルアレイ２０２が具備する不揮発性記憶素子から、少なくとも一つの不揮発性記憶素子を選択する選択回路の一例である。 Further, the column selection circuit / driver 204 receives the column address signal output from the address input circuit 208 and selects one of the plurality of bit lines BL0, BL1, BL2,... According to the column address signal. Then, a write voltage or a read voltage is applied to the selected bit line. That is, the column selection circuit / driver 204 is an example of a selection circuit that selects at least one nonvolatile memory element from the nonvolatile memory elements included in the memory cell array 202.
　書き込み回路２０５は、制御回路２０９から出力された書き込み信号を受け取った場合、行選択回路・ドライバ２０３に対して選択されたワード線に対する電圧の印加を指示する信号を出力するとともに、列選択回路・ドライバ２０４に対して選択されたビット線に対して書き込み用電圧の印加を指示する信号を出力する。つまり、書き込み回路２０５は、選択回路（行選択回路・ドライバ２０３及び列選択回路・ドライバ２０４）で選択された不揮発性記憶素子（ここでは、メモリセル）に電圧を印加することでデータを書き込む書き込み回路の一例である。 When the write circuit 205 receives the write signal output from the control circuit 209, the write circuit 205 outputs a signal instructing the row selection circuit / driver 203 to apply a voltage to the selected word line, and the column selection circuit / A signal instructing the driver 204 to apply a write voltage to the selected bit line is output. In other words, the writing circuit 205 writes data by applying a voltage to a nonvolatile memory element (here, a memory cell) selected by the selection circuit (row selection circuit / driver 203 and column selection circuit / driver 204). It is an example of a circuit.
　また、センスアンプ２０６は、情報の読み出しサイクルにおいて、読み出し対象となる選択ビット線に流れる電流量を検出し、データ「１」または「０」の判別を行う。その結果得られた出力データＤＯは、データ入出力回路２０７を介して、外部回路へ出力される。つまり、センスアンプ２０６は、選択回路（行選択回路・ドライバ２０３及び列選択回路・ドライバ２０４）で選択されたメモリセルを構成する不揮発性記憶素子の抵抗値を検出することでデータを読み出す読み出し回路の一例である。読み出し回路としては、上記センスアンプ２０６に変えて、不揮発性記憶素子の抵抗値と読み出し回路に形成された静電容量とでＲＣ回路を形成し、その時定数を測定するように構成されたセンスアンプを用いてもよい。 Also, the sense amplifier 206 detects the amount of current flowing through the selected bit line to be read in the information read cycle, and determines data “1” or “0”. The output data DO obtained as a result is output to an external circuit via the data input / output circuit 207. That is, the sense amplifier 206 is a read circuit that reads data by detecting the resistance value of the nonvolatile memory element that constitutes the memory cell selected by the selection circuit (row selection circuit / driver 203 and column selection circuit / driver 204). It is an example. As a read circuit, instead of the sense amplifier 206, a sense amplifier configured to form an RC circuit with the resistance value of the nonvolatile memory element and the capacitance formed in the read circuit and measure the time constant thereof. May be used.
　なお、図２５及び図２６に示す本実施の形態に係る不揮発性記憶装置２００におけるメモリセルアレイ２０２を、３次元に積み重ねることによって、多層化構造の不揮発性記憶装置を実現することも可能である。このように構成された多層化メモリセルアレイを設けることによって、超大容量不揮発性メモリを実現することが可能となる。 Note that it is also possible to realize a nonvolatile memory device having a multilayer structure by stacking the memory cell arrays 202 in the nonvolatile memory device 200 according to the present embodiment shown in FIGS. 25 and 26 three-dimensionally. By providing the multi-layered memory cell array configured as described above, it is possible to realize an ultra-large capacity nonvolatile memory.
　［不揮発性記憶素子の構成］
　図２７は、本発明の実施の形態２に係る不揮発性記憶装置２００が備えるメモリセル（ここでは、負荷素子としての電流抑制素子を備える不揮発性記憶素子２１０）の構成を示す断面図である。なお、図２７には、図２６のＢ部（一つのクロスポイント）における構成が示されている。 [Configuration of Nonvolatile Memory Element]
FIG. 27 is a cross-sectional view showing a configuration of a memory cell (here, a nonvolatile memory element 210 including a current suppressing element as a load element) included in the nonvolatile memory device 200 according to Embodiment 2 of the present invention. Note that FIG. 27 shows a configuration in B part (one cross point) in FIG.
　図２７に示すように、本実施の形態に係る不揮発性記憶装置が備える不揮発性記憶素子２１０は、銅配線である下部配線２１２（図２６におけるワード線ＷＬ１に相当する）と同じく上部配線２１１（図２６におけるビット線ＢＬ１に相当する）との間に介在しており、下部電極２１７と、電流抑制素子２１６と、内部電極２１５と、抵抗変化層２１４と、上部電極２１３とがこの順に積層されて構成されている。 As shown in FIG. 27, the nonvolatile memory element 210 included in the nonvolatile memory device according to the present embodiment includes an upper wiring 211 (corresponding to the lower wiring 212 (corresponding to the word line WL1 in FIG. 26) that is a copper wiring. The lower electrode 217, the current suppressing element 216, the internal electrode 215, the resistance change layer 214, and the upper electrode 213 are stacked in this order. Configured.
　ここで、内部電極２１５、抵抗変化層２１４、及び上部電極２１３は、図１に示した実施の形態１に係る不揮発性記憶素子１００における第１電極層１０３、抵抗変化層１０４、及び第２電極層１０５にそれぞれ相当する。したがって、抵抗変化層２１４は、実施の形態１における抵抗変化層１０４と同様にして形成される。 Here, the internal electrode 215, the resistance change layer 214, and the upper electrode 213 are the first electrode layer 103, the resistance change layer 104, and the second electrode in the nonvolatile memory element 100 according to Embodiment 1 shown in FIG. Each corresponds to the layer 105. Therefore, the resistance change layer 214 is formed in the same manner as the resistance change layer 104 in the first embodiment.
　電流抑制素子２１６は、内部電極２１５を介して、抵抗変化層２１４と直列接続される負荷素子の一例である。この電流抑制素子２１６は、ダイオードに代表される電流を抑制する機能を有する素子であり、電圧に対して非線形な電流特性を示すものである。また、この電流抑制素子２１６は、電圧に対して双方向性の電流特性を有しており、所定の閾値電圧Ｖｆ（一方の電極を基準にして例えば＋１Ｖ以上または－１Ｖ以下）で導通するように構成されている。 The current suppression element 216 is an example of a load element connected in series with the resistance change layer 214 via the internal electrode 215. The current suppressing element 216 is an element having a function of suppressing a current typified by a diode, and exhibits a nonlinear current characteristic with respect to a voltage. Further, the current suppressing element 216 has a bidirectional current characteristic with respect to the voltage, and conducts at a predetermined threshold voltage Vf (for example, +1 V or more or −1 V or less with respect to one electrode). It is configured.
　［不揮発性記憶装置の動作］
　次に、情報を書き込む場合の書き込みサイクル及び情報を読み出す場合の読み出しサイクルにおける本実施の形態に係る不揮発性記憶装置２００の動作例について、図２８に示すタイミングチャートを参照しながら説明する。 [Operation of non-volatile storage device]
Next, an operation example of the nonvolatile memory device 200 according to this embodiment in a writing cycle for writing information and a reading cycle for reading information will be described with reference to a timing chart shown in FIG.
　図２８は、本発明の実施の形態２に係る不揮発性記憶装置２００の動作例を示すタイミングチャートである。なお、ここでは、抵抗変化層２１４が高抵抗状態の場合を情報「１」に、低抵抗状態の場合を情報「０」にそれぞれ割り当てたときの動作例を示す。また、説明の便宜上、メモリセルＭ１１１およびＭ１２２について情報の書き込みおよび読み出しをする場合のみについて示す。 FIG. 28 is a timing chart showing an operation example of the nonvolatile memory device 200 according to Embodiment 2 of the present invention. Here, an example of operation when the resistance change layer 214 is assigned to the information “1” when the resistance change layer 214 is in the high resistance state and the information “0” is assigned to the information when the resistance change layer 214 is in the low resistance state. For convenience of explanation, only the case where information is written to and read from the memory cells M111 and M122 is shown.
　図２８における電圧値ＶＰは、不揮発性記憶素子と電流抑制素子とで構成されたメモリセルの抵抗変化に必要なパルス電圧を示している。ここでは、ＶＰ／２＜閾値電圧Ｖｆの関係が成り立つことが望ましい。なぜなら、非選択のメモリセルに回り込んで流れる漏れ電流を抑えることができるからである。その結果、情報を書き込む必要のないメモリセルへ供給される余分な電流を抑制することができ、低消費電流化をより一層図ることができる。また、非選択のメモリセルへの意図しない浅い書き込み（一般にディスターブと称される）が抑制されるなどの利点もある。 A voltage value VP in FIG. 28 indicates a pulse voltage necessary for resistance change of a memory cell formed of a nonvolatile memory element and a current suppressing element. Here, it is desirable that the relationship of VP / 2 <threshold voltage Vf is satisfied. This is because the leakage current flowing around the unselected memory cells can be suppressed. As a result, it is possible to suppress an excessive current supplied to the memory cell that does not need to write information, and to further reduce the current consumption. Further, there is an advantage that unintentional shallow writing (generally referred to as disturb) to unselected memory cells is suppressed.
　また、図２８において、１回の書き込みサイクルに要する時間である書き込みサイクル時間をｔＷで、１回の読み出しサイクルに要する時間である読み出しサイクル時間をｔＲでそれぞれ示している。 In FIG. 28, a write cycle time that is a time required for one write cycle is indicated by tW, and a read cycle time that is a time required for one read cycle is indicated by tR.
　メモリセルＭ１１１に対する書き込みサイクルにおいて、ワード線ＷＬ０にはパルス幅ｔＰのパルス電圧ＶＰが印加され、そのタイミングに応じて、ビット線ＢＬ０には同じく０Ｖの電圧が印加される。これにより、メモリセルＭ１１１に情報「１」を書き込む場合の書き込み用電圧が印加され、その結果、メモリセルＭ１１１の抵抗変化層が高抵抗化する。すなわち、メモリセルＭ１１１に情報「１」が書き込まれたことになる。 In a write cycle for the memory cell M111, a pulse voltage VP having a pulse width tP is applied to the word line WL0, and a voltage of 0V is similarly applied to the bit line BL0 according to the timing. As a result, a write voltage for writing information “1” to the memory cell M111 is applied, and as a result, the resistance change layer of the memory cell M111 has a high resistance. That is, information “1” is written in the memory cell M111.
　次に、メモリセルＭ１２２に対する書き込みサイクルにおいて、ワード線ＷＬ１にはパルス幅ｔＰの０Ｖの電圧が印加され、そのタイミングに応じて、ビット線ＢＬ１には同じくパルス電圧ＶＰが印加される。これにより、Ｍ１２２に情報「０」を書き込む場合の書き込み用電圧が印加され、その結果、メモリセルＭ１２２の抵抗変化層が低抵抗化する。すなわち、メモリセルＭ１２２に情報「０」が書き込まれたことになる。 Next, in the write cycle for the memory cell M122, a voltage of 0V having a pulse width tP is applied to the word line WL1, and the pulse voltage VP is similarly applied to the bit line BL1 according to the timing. As a result, a write voltage for writing information “0” to M122 is applied, and as a result, the resistance change layer of the memory cell M122 has a low resistance. That is, information “0” is written in the memory cell M122.
　メモリセルＭ１１１に対する読み出しサイクルにおいては、書き込み時のパルスよりも振幅が小さいパルス電圧であって、０Ｖよりも大きくＶＰ／２よりも小さい値の電圧が、ワード線ＷＬ０に印加される。また、このタイミングに応じて、書き込み時のパルスよりも振幅が小さいパルス電圧であって、ＶＰ／２よりも大きくＶＰよりも小さい値の電圧が、ビット線ＢＬ０に印加される。これにより、高抵抗化されたメモリセルＭ１１１の抵抗変化層２１４の抵抗値に対応した電流が出力され、その出力電流値を検出することにより、情報「１」が読み出される。 In the read cycle for the memory cell M111, a pulse voltage having a smaller amplitude than the pulse at the time of writing and having a value larger than 0V and smaller than VP / 2 is applied to the word line WL0. In accordance with this timing, a pulse voltage having a smaller amplitude than the pulse at the time of writing and having a value larger than VP / 2 and smaller than VP is applied to the bit line BL0. As a result, a current corresponding to the resistance value of the resistance change layer 214 of the memory cell M111 whose resistance is increased is output, and information “1” is read by detecting the output current value.
　次に、メモリセルＭ１２２に対する読み出しサイクルにおいて、先のメモリセルＭ１１１に対する読み出しサイクルと同様の電圧がワード線ＷＬ１およびビット線ＢＬ１に印加される。これにより、低抵抗化されたメモリセルＭ１２２の抵抗変化層２１４の抵抗値に対応した電流が出力され、その出力電流値を検出することにより、情報「０」が読み出される。 Next, in the read cycle for the memory cell M122, the same voltage as that for the read cycle for the previous memory cell M111 is applied to the word line WL1 and the bit line BL1. As a result, a current corresponding to the resistance value of the resistance change layer 214 of the memory cell M122 whose resistance has been reduced is output, and information “0” is read by detecting the output current value.
　本実施の形態の不揮発性記憶装置２００は、実施の形態１における不揮発性記憶素子１００のような、良好な抵抗変化動作が可能な不揮発性記憶素子２１０を備えているため、安定した動作を実現することができる。 The nonvolatile memory device 200 according to the present embodiment includes the nonvolatile memory element 210 that can perform a good resistance change operation like the nonvolatile memory element 100 according to the first embodiment, and thus realizes stable operation. can do.
　（実施の形態３）
　次に、本発明の実施の形態３に係る不揮発性記憶装置について説明する。 (Embodiment 3)
Next, a nonvolatile memory device according to Embodiment 3 of the present invention will be described.
　実施の形態３に係る不揮発性記憶装置は、実施の形態１に係る不揮発性記憶素子１００を備える不揮発性記憶装置であって、単位メモリセルを１つのトランジスタと１つの不揮発性記憶部とで構成した所謂１Ｔ１Ｒ型のものである。 The non-volatile memory device according to the third embodiment is a non-volatile memory device including the non-volatile memory element 100 according to the first embodiment, and the unit memory cell includes one transistor and one non-volatile memory unit. The so-called 1T1R type.
　［不揮発性記憶装置の構成］
　図２９は、本発明の実施の形態３に係る不揮発性記憶装置３００の構成を示すブロック図である。また、図３０は、図２９におけるＣ部の構成（２ビット分のメモリセルの物理的な構成）を示す断面図である。 [Configuration of non-volatile storage device]
FIG. 29 is a block diagram showing a configuration of the nonvolatile memory device 300 according to Embodiment 3 of the present invention. FIG. 30 is a cross-sectional view showing the configuration of part C in FIG. 29 (physical configuration of a memory cell for 2 bits).
　図２９に示すように、本実施の形態に係る不揮発性記憶装置３００は、半導体基板上に、メモリ本体部３０１を備えており、このメモリ本体部３０１は、メモリセルアレイ３０２と、行選択回路・ドライバ３０３と、列選択回路３０４と、情報の書き込みを行うための書き込み回路３０５と、選択ビット線に流れる電流量を検出し、データ「１」または「０」の判定を行うセンスアンプ３０６と、端子ＤＱを介して入出力データの入出力処理を行うデータ入出力回路３０７とを具備している。 As shown in FIG. 29, the nonvolatile memory device 300 according to the present embodiment includes a memory main body 301 on a semiconductor substrate. The memory main body 301 includes a memory cell array 302, a row selection circuit, A driver 303, a column selection circuit 304, a writing circuit 305 for writing information, a sense amplifier 306 for detecting the amount of current flowing through the selected bit line and determining data “1” or “0”; And a data input / output circuit 307 for performing input / output processing of input / output data via the terminal DQ.
　また、不揮発性記憶装置３００は、セルプレート電源（ＶＣＰ電源）３０８と、外部から入力されるアドレス信号を受け取るアドレス入力回路３０９と、外部から入力されるコントロール信号に基づいて、メモリ本体部３０１の動作を制御する制御回路３１０とをさらに備えている。 The nonvolatile memory device 300 includes a cell plate power supply (VCP power supply) 308, an address input circuit 309 that receives an address signal input from the outside, and a control signal input from the outside. And a control circuit 310 for controlling the operation.
　メモリセルアレイ３０２は、半導体基板の上に形成された、互いに交差するように配列された複数のワード線ＷＬ０，ＷＬ１，ＷＬ２，…およびビット線ＢＬ０，ＢＬ１，ＢＬ２，…と、これらのワード線ＷＬ０，ＷＬ１，ＷＬ２，…およびビット線ＢＬ０，ＢＬ１，ＢＬ２，…の交点に対応してそれぞれ設けられた複数のトランジスタ（例えば、ＮＭＯＳトランジスタ）Ｔ１１，Ｔ１２，Ｔ１３，Ｔ２１，Ｔ２２，Ｔ２３，Ｔ３１，Ｔ３２，Ｔ３３，…（以下、「トランジスタＴ１１，Ｔ１２，…」と表す）と、トランジスタＴ１１，Ｔ１２，…と１対１に設けられた複数のメモリセルＭ２１１，Ｍ２１２，Ｍ２１３，Ｍ２２１，Ｍ２２２，Ｍ２２３，Ｍ２３１，Ｍ２３２，Ｍ２３３（以下、「メモリセルＭ２１１，Ｍ２１２，…」と表す）とを備えている。 The memory cell array 302 includes a plurality of word lines WL0, WL1, WL2,... And bit lines BL0, BL1, BL2,... , WL1, WL2,... And bit lines BL0, BL1, BL2,..., And a plurality of transistors (for example, NMOS transistors) T11, T12, T13, T21, T22, T23, T31, T32, respectively. , T33,... (Hereinafter referred to as “transistors T11, T12,...”) And a plurality of memory cells M211, M212, M213, M221, M222, M223 provided one-to-one with the transistors T11, T12,. M231, M232, M233 (hereinafter referred to as “memory cells M211, M212,...”) ) And a.
　また、メモリセルアレイ３０２は、ワード線ＷＬ０，ＷＬ１，ＷＬ２，…に平行して配列されている複数のプレート線ＰＬ０，ＰＬ１，ＰＬ２，…を備えている。 The memory cell array 302 includes a plurality of plate lines PL0, PL1, PL2,... Arranged in parallel to the word lines WL0, WL1, WL2,.
　図３０に示すように、ワード線ＷＬ０，ＷＬ１の上方にビット線ＢＬ０が配され、そのワード線ＷＬ０，ＷＬ１とビット線ＢＬ０との間に、プレート線ＰＬ０，ＰＬ１が配されている。 As shown in FIG. 30, a bit line BL0 is arranged above the word lines WL0 and WL1, and plate lines PL0 and PL1 are arranged between the word lines WL0 and WL1 and the bit line BL0.
　ここで、メモリセルＭ２１１，Ｍ２１２，…は、実施の形態１に係る不揮発性記憶素子１００に相当する。より具体的には、図３０における不揮発性記憶素子３１３が、図２９におけるメモリセルＭ２１１，Ｍ２１２，…に相当し、この不揮発性記憶素子３１３は、上部電極３１４、抵抗変化層３１５、及び下部電極３１６から構成されている。そして、これらの上部電極３１４、抵抗変化層３１５、及び下部電極３１６は、図１に示した実施の形態１に係る不揮発性記憶素子１００における第１電極層１０３、抵抗変化層１０４、及び第２電極層１０５にそれぞれ相当する。したがって、抵抗変化層３１５は、実施の形態１における抵抗変化層１０４と同様にして形成される。 Here, the memory cells M211, M212,... Correspond to the nonvolatile memory element 100 according to the first embodiment. More specifically, the nonvolatile memory element 313 in FIG. 30 corresponds to the memory cells M211, M212,... In FIG. 29. The nonvolatile memory element 313 includes the upper electrode 314, the resistance change layer 315, and the lower electrode. 316. Then, the upper electrode 314, the resistance change layer 315, and the lower electrode 316 are the first electrode layer 103, the resistance change layer 104, and the second electrode in the nonvolatile memory element 100 according to Embodiment 1 shown in FIG. Each corresponds to the electrode layer 105. Therefore, resistance change layer 315 is formed in the same manner as resistance change layer 104 in the first embodiment.
　なお、図３０における符号３１７はプラグ層を、符号３１８は金属配線層を、符号３１９はソース及びドレイン領域をそれぞれ示している。 In FIG. 30, reference numeral 317 indicates a plug layer, reference numeral 318 indicates a metal wiring layer, and reference numeral 319 indicates a source and drain region.
　図２９に示すように、トランジスタＴ１１，Ｔ１２，Ｔ１３，…のドレインはビット線ＢＬ０に、トランジスタＴ２１，Ｔ２２，Ｔ２３，…のドレインはビット線ＢＬ１に、トランジスタＴ３１，Ｔ３２，Ｔ３３，…のドレインはビット線ＢＬ２に、それぞれ接続されている。 29, the drains of the transistors T11, T12, T13,... Are on the bit line BL0, the drains of the transistors T21, T22, T23,... Are on the bit line BL1, and the drains of the transistors T31, T32, T33,. Each is connected to the bit line BL2.
　また、トランジスタＴ１１，Ｔ２１，Ｔ３１，…のゲートはワード線ＷＬ０に、トランジスタＴ１２，Ｔ２２，Ｔ３２，…のゲートはワード線ＷＬ１に、トランジスタＴ１３，Ｔ２３，Ｔ３３，…のゲートはワード線ＷＬ２に、それぞれ接続されている。 In addition, the gates of the transistors T11, T21, T31,... Are on the word line WL0, the gates of the transistors T12, T22, T32, ... are on the word line WL1, and the gates of the transistors T13, T23, T33,. Each is connected.
　さらに、トランジスタＴ１１，Ｔ１２，…のソースはそれぞれ、メモリセルＭ２１１，Ｍ２１２，…と接続されている。 Further, the sources of the transistors T11, T12,... Are connected to the memory cells M211, M212,.
　また、メモリセルＭ２１１，Ｍ２２１，Ｍ２３１，…はプレート線ＰＬ０に、メモリセルＭ２１２，Ｍ２２２，Ｍ２３２，…はプレート線ＰＬ１に、メモリセルＭ２１３，Ｍ２２３，Ｍ２３３，…はプレート線ＰＬ２に、それぞれ接続されている。 Are connected to the plate line PL0, the memory cells M212, M222, M232,... Are connected to the plate line PL1, and the memory cells M213, M223, M233,. ing.
　アドレス入力回路３０９は、外部回路（図示せず）からアドレス信号を受け取り、このアドレス信号に基づいて行アドレス信号を行選択回路・ドライバ３０３へ出力するとともに、列アドレス信号を列選択回路３０４へ出力する。ここで、アドレス信号は、メモリセルアレイ３０２を構成する複数のメモリセルＭ２１１，Ｍ２１２，…のうちの選択される特定のメモリセルのアドレスを示す信号である。また、行アドレス信号は、アドレス信号に示されたアドレスのうちの行のアドレスを示す信号であり、列アドレス信号は、アドレス信号に示されたアドレスのうちの列のアドレスを示す信号である。 The address input circuit 309 receives an address signal from an external circuit (not shown), outputs a row address signal to the row selection circuit / driver 303 based on the address signal, and outputs a column address signal to the column selection circuit 304. To do. Here, the address signal is a signal indicating the address of a specific memory cell selected from among the plurality of memory cells M211, M212,... Constituting the memory cell array 302. The row address signal is a signal indicating a row address among the addresses indicated by the address signal, and the column address signal is a signal indicating a column address among the addresses indicated by the address signal.
　制御回路３１０は、情報の書き込みサイクルにおいては、データ入出力回路３０７に入力された入力データＤｉｎに応じて、書き込み用電圧の印加を指示する書き込み信号を書き込み回路３０５へ出力する。他方、情報の読み出しサイクルにおいて、制御回路３１０は、読み出し用電圧の印加を指示する読み出し信号を列選択回路３０４へ出力する。 In the information write cycle, the control circuit 310 outputs a write signal instructing application of a write voltage to the write circuit 305 in accordance with the input data Din input to the data input / output circuit 307. On the other hand, in the information read cycle, the control circuit 310 outputs a read signal instructing application of a read voltage to the column selection circuit 304.
　行選択回路・ドライバ３０３は、アドレス入力回路３０９から出力された行アドレス信号を受け取り、この行アドレス信号に応じて、複数のワード線ＷＬ０，ＷＬ１，ＷＬ２，…のうちの何れかを選択し、その選択されたワード線に対して、所定の電圧を印加する。つまり、行選択回路・ドライバ３０３は、メモリセルアレイ３０２が具備する不揮発性記憶素子から、少なくとも一つの不揮発性記憶素子を選択する選択回路の一例である。 The row selection circuit / driver 303 receives the row address signal output from the address input circuit 309, selects one of the plurality of word lines WL0, WL1, WL2,... According to the row address signal, A predetermined voltage is applied to the selected word line. That is, the row selection circuit / driver 303 is an example of a selection circuit that selects at least one nonvolatile memory element from the nonvolatile memory elements included in the memory cell array 302.
　また、列選択回路３０４は、アドレス入力回路３０９から出力された列アドレス信号を受け取り、この列アドレス信号に応じて、複数のビット線ＢＬ０，ＢＬ１，ＢＬ２，…のうちの何れかを選択し、その選択されたビット線に対して、書き込み用電圧または読み出し用電圧を印加する。つまり、列選択回路３０４は、メモリセルアレイ３０２が具備する不揮発性記憶素子から、少なくとも一つの不揮発性記憶素子を選択する選択回路の一例である。 The column selection circuit 304 receives the column address signal output from the address input circuit 309, selects one of the plurality of bit lines BL0, BL1, BL2,... According to the column address signal, A write voltage or a read voltage is applied to the selected bit line. That is, the column selection circuit 304 is an example of a selection circuit that selects at least one nonvolatile memory element from the nonvolatile memory elements included in the memory cell array 302.
　書き込み回路３０５は、制御回路３１０から出力された書き込み信号を受け取った場合、列選択回路３０４に対して選択されたビット線に対して書き込み用電圧の印加を指示する信号を出力する。つまり、書き込み回路３０５は、選択回路（行選択回路・ドライバ３０３及び列選択回路３０４）で選択された不揮発性記憶素子（ここでは、メモリセル）に電圧を印加することでデータを書き込む書き込み回路の一例である。 When the write circuit 305 receives the write signal output from the control circuit 310, the write circuit 305 outputs a signal instructing the column selection circuit 304 to apply the write voltage to the selected bit line. That is, the writing circuit 305 is a writing circuit that writes data by applying a voltage to a nonvolatile memory element (here, a memory cell) selected by a selection circuit (row selection circuit / driver 303 and column selection circuit 304). It is an example.
　また、センスアンプ３０６は、情報の読み出しサイクルにおいて、読み出し対象となる選択ビット線に流れる電流量を検出し、データ「１」または「０」と判定する。その結果得られた出力データＤＯは、データ入出力回路３０７を介して、外部回路へ出力される。つまり、センスアンプ３０６は、選択回路（行選択回路・ドライバ３０３及び列選択回路３０４）で選択されたメモリセルを構成する不揮発性記憶素子の抵抗値を検出することでデータを読み出す読み出し回路の一例である。 Also, the sense amplifier 306 detects the amount of current flowing through the selected bit line to be read in the information read cycle, and determines that the data is “1” or “0”. The output data DO obtained as a result is output to an external circuit via the data input / output circuit 307. In other words, the sense amplifier 306 is an example of a read circuit that reads data by detecting the resistance value of the nonvolatile memory element that constitutes the memory cell selected by the selection circuit (row selection circuit / driver 303 and column selection circuit 304). It is.
　なお、１トランジスタ・１不揮発性記憶部の構成である本実施の形態の場合、１個のメモリセルごとに１個のトランジスタが必要とされるために、実施の形態２のクロスポイント型の構成と比べて記憶容量は小さくなる。しかしながら、ダイオードのような電流抑制素子が不要であるため、ＣＭＯＳプロセスに容易に組み合わせることができ、また、動作の制御も容易であるという利点がある。 In the case of the present embodiment having a configuration of one transistor and one non-volatile memory portion, one transistor is required for each memory cell, so that the cross-point configuration of the second embodiment is used. Compared with the memory capacity. However, since a current suppressing element such as a diode is unnecessary, there is an advantage that it can be easily combined with a CMOS process and the operation can be easily controlled.
　［不揮発性記憶装置の動作例］
　次に、情報を書き込む場合の書き込みサイクルおよび情報を読み出す場合の読み出しサイクルにおける本実施の形態に係る不揮発性記憶装置３００の動作例について、図３１に示すタイミングチャートを参照しながら説明する。 [Example of operation of nonvolatile memory device]
Next, an operation example of the nonvolatile memory device 300 according to the present embodiment in a write cycle for writing information and a read cycle for reading information will be described with reference to a timing chart shown in FIG.
　図３１は、本発明の実施の形態３に係る不揮発性記憶装置３００の動作例を示すタイミングチャートである。なお、ここでは、抵抗変化層３１５が高抵抗状態の場合を情報「１」に、低抵抗状態の場合を情報「０」にそれぞれ割り当てたときの動作例を示す。また、説明の便宜上、メモリセルＭ２１１およびＭ２２２について情報の書き込みおよび読み出しをする場合のみについて示す。 FIG. 31 is a timing chart showing an operation example of the nonvolatile memory device 300 according to Embodiment 3 of the present invention. Here, an example of operation when the variable resistance layer 315 is assigned to the information “1” when the resistance change layer 315 is in the high resistance state and the information “0” is assigned to the case where the resistance change layer 315 is in the low resistance state is shown. For convenience of explanation, only the case where information is written to and read from the memory cells M211 and M222 is shown.
　図３１において、電圧値ＶＰは、可変抵抗素子の抵抗変化に必要なパルス電圧を示しており、電圧値ＶＴはトランジスタの閾値電圧を示している。また、プレート線には、常時電圧ＶＰが印加され、ビット線も、非選択の場合は電圧ＶＰにプリチャージされている。 In FIG. 31, a voltage value VP indicates a pulse voltage necessary for resistance change of the variable resistance element, and a voltage value VT indicates a threshold voltage of the transistor. Further, the voltage VP is constantly applied to the plate line, and the bit line is also precharged to the voltage VP when not selected.
　メモリセルＭ２１１に対する書き込みサイクルにおいて、ワード線ＷＬ０にはパルス幅ｔＰのパルス電圧（その電圧は、（２ＶＰ＋トランジスタの閾値電圧ＶＴ）よりも大きい電圧）が印加され、トランジスタＴ１１がＯＮ状態となる。そして、そのタイミングに応じて、ビット線ＢＬ０にはパルス電圧２ＶＰが印加される。これにより、メモリセルＭ２１１に情報「１」を書き込む場合の書き込み用電圧が印加され、その結果、メモリセルＭ２１１の抵抗変化層が高抵抗化する。すなわち、メモリセルＭ２１１に情報「１」が書き込まれたことになる。 In a write cycle for the memory cell M211, a pulse voltage having a pulse width tP (a voltage higher than (2VP + transistor threshold voltage VT)) is applied to the word line WL0, and the transistor T11 is turned on. Then, according to the timing, the pulse voltage 2VP is applied to the bit line BL0. As a result, a write voltage for writing information “1” to the memory cell M211 is applied, and as a result, the resistance change layer of the memory cell M211 has a high resistance. That is, information “1” is written in the memory cell M211.
　次に、メモリセルＭ２２２に対する書き込みサイクルにおいて、ワード線ＷＬ１にはパルス幅ｔＰのパルス電圧（その電圧は、（２ＶＰ＋トランジスタの閾値電圧ＶＴ）よりも大きい電圧）が印加され、トランジスタＴ２２がＯＮ状態となる。そのタイミングに応じて、ビット線ＢＬ１には０Ｖの電圧が印加される。これにより、メモリセルＭ２２２に情報「０」を書き込む場合の書き込み用電圧が印加され、その結果、メモリセルＭ２２２の抵抗変化層が低抵抗化する。すなわち、メモリセルＭ２２２に情報「０」が書き込まれたことになる。 Next, in a write cycle for the memory cell M222, a pulse voltage having a pulse width tP (a voltage higher than (2VP + transistor threshold voltage VT)) is applied to the word line WL1, and the transistor T22 is turned on. Become. Depending on the timing, a voltage of 0 V is applied to the bit line BL1. As a result, a write voltage for writing information “0” to the memory cell M222 is applied, and as a result, the resistance change layer of the memory cell M222 has a low resistance. That is, information “0” is written in the memory cell M222.
　メモリセルＭ２１１に対する読み出しサイクルにおいては、トランジスタＴ１１をＯＮ状態にするために所定の電圧がワード線ＷＬ０に印加され、そのタイミングに応じて、書き込みの際のパルス幅よりも振幅が小さいパルス電圧が、ビット線ＢＬ０に印加される。これにより、高抵抗化されたメモリセルＭ２１１の抵抗変化層の抵抗値に対応した電流が出力され、その出力電流値を検出することにより、情報「１」が読み出される。 In the read cycle for the memory cell M211, a predetermined voltage is applied to the word line WL0 in order to turn on the transistor T11. Depending on the timing, a pulse voltage having an amplitude smaller than the pulse width at the time of writing is Applied to the bit line BL0. As a result, a current corresponding to the resistance value of the resistance change layer of the memory cell M211 with the increased resistance is output, and information “1” is read by detecting the output current value.
　次に、メモリセルＭ２２２に対する読み出しサイクルにおいて、先のメモリセルＭ２１１に対する読み出しサイクルと同様の電圧がワード線ＷＬ１およびビット線ＢＬ１に印加される。これにより、低抵抗化されたメモリセルＭ２２２の抵抗変化層の抵抗値に対応した電流が出力され、その出力電流値を検出することにより、情報「０」が読み出される。 Next, in the read cycle for the memory cell M222, the same voltage as that for the previous read cycle for the memory cell M211 is applied to the word line WL1 and the bit line BL1. As a result, a current corresponding to the resistance value of the resistance change layer of the memory cell M222 whose resistance is reduced is output, and information “0” is read by detecting the output current value.
　実施の形態２の場合と同様、本実施の形態の不揮発性記憶装置３００においても、実施の形態１における不揮発性記憶素子１００のような、良好な抵抗変化動作が可能な不揮発性記憶素子３１３を備えているため、安定した動作を実現することができる。 Similarly to the case of the second embodiment, the non-volatile memory device 300 of the present embodiment also has a non-volatile memory element 313 that can perform a good resistance change operation like the non-volatile memory element 100 of the first embodiment. Therefore, stable operation can be realized.
　本発明の不揮発性記憶素子及び不揮発性記憶装置は、各種電子機に用いられる記憶素子として、特に、低いブレイク電圧で動作する記憶素子及び記憶装置、例えば、デジタル家電、メモリーカード、パーソナルコンピュータ及び携帯型電話機等の種々の電子機器に用いられる記憶素子及び記憶装置等として有用である。 The nonvolatile memory element and the nonvolatile memory device of the present invention are used as a memory element used in various electronic devices, in particular, a memory element and a memory device that operate at a low break voltage, such as a digital home appliance, a memory card, a personal computer, and a mobile phone. It is useful as a storage element and a storage device used in various electronic devices such as type telephones.
　１００　　不揮発性記憶素子
　１０１　　基板
　１０２　　酸化物層
　１０３　　第１電極層
　１０４　　抵抗変化層
　１０４ａ　　第１の酸化物層
　１０４ｂ　　第２の酸化物層
　１０５　　第２電極層
　１０６　　フォトレジストパターン
　１０７　　素子領域
　２００　　不揮発性記憶装置
　２０１　　メモリ本体部
　２０２　　メモリセルアレイ
　２０３　　行選択回路・ドライバ
　２０４　　列選択回路・ドライバ
　２０５　　書き込み回路
　２０６　　センスアンプ
　２０７　　データ入出力回路
　２０８　　アドレス入力回路
　２０９　　制御回路
　２１０　　不揮発性記憶素子
　２１１　　上部配線
　２１２　　下部配線
　２１３　　上部電極
　２１４　　抵抗変化層
　２１５　　内部電極
　２１６　　電流抑制素子
　２１７　　下部電極
　３００　　不揮発性記憶装置
　３０１　　メモリ本体部
　３０２　　メモリセルアレイ
　３０３　　行選択回路・ドライバ
　３０４　　列選択回路
　３０５　　書き込み回路
　３０６　　センスアンプ
　３０７　　データ入出力回路
　３０８　　ＶＣＰ電源
　３０９　　アドレス入力回路
　３１０　　制御回路
　３１３　　不揮発性記憶素子
　３１４　　上部電極
　３１５　　抵抗変化層
　３１６　　下部電極
　ＢＬ０，ＢＬ１，…　　ビット線
　Ｍ１１１，Ｍ１１２，…　　メモリセル
　Ｍ２１１，Ｍ２１２，…　　メモリセル
　ＰＬ０，ＰＬ１，…　　プレート線
　Ｔ１１，Ｔ１２，…　　トランジスタ
　ＷＬ０，ＷＬ１，…　　ワード線 DESCRIPTION OF SYMBOLS 100 Nonvolatile memory element 101 Substrate 102 Oxide layer 103 1st electrode layer 104 Resistance change layer 104a 1st oxide layer 104b 2nd oxide layer 105 2nd electrode layer 106 Photoresist pattern 107 Element area 200 Nonvolatile memory Device 201 Memory main body 202 Memory cell array 203 Row selection circuit / driver 204 Column selection circuit / driver 205 Write circuit 206 Sense amplifier 207 Data input / output circuit 208 Address input circuit 209 Control circuit 210 Non-volatile memory element 211 Upper wiring 212 Lower wiring 213 Upper electrode 214 Resistance change layer 215 Internal electrode 216 Current suppression element 217 Lower electrode 300 Non-volatile memory device 301 Memory main body 302 Memory cell array 303 Row selection circuit / driver 04 Column selection circuit 305 Write circuit 306 Sense amplifier 307 Data input / output circuit 308 VCP power supply 309 Address input circuit 310 Control circuit 313 Non-volatile memory element 314 Upper electrode 315 Resistance change layer 316 Lower electrode BL0, BL1,... Bit lines M111, M112 Memory cells M211, M212, ... Memory cells PL0, PL1, ... Plate lines T11, T12, ... Transistors WL0, WL1, ... Word lines

Claims (14)

  1. 　抵抗変化型の不揮発性記憶素子であって、
    　第１電極と、第２電極と、前記第１電極と前記第２電極との間に介在し、前記第１電極及び前記第２電極間に与えられる電圧の極性に基づいて可逆的に高抵抗状態と低抵抗状態とを遷移する抵抗変化層とを備え、
    　前記抵抗変化層が前記高抵抗状態にあるときの当該不揮発性記憶素子の抵抗値よりも高い抵抗値をもつ初期状態にあるときに、負荷素子が接続された状態で電圧を印加する初期ブレイクが行われることよって前記遷移が可能な状態に変化する特性を有し、
    　前記抵抗変化層は、少なくとも第１の遷移金属の酸化物を含む第１の酸化物層と、前記第１の遷移金属とは異なる第２の遷移金属の酸化物を含む第２の酸化物層との積層構造を含み、
    　前記第２の遷移金属の標準電極電位が前記第１の遷移金属の標準電極電位よりも小さく、
    かつ、
    　（１）前記第２の酸化物層の誘電率が前記第１の酸化物層の誘電率よりも大きい、
    　（２）前記第２の酸化物層のバンドギャップが前記第１の酸化物層のバンドギャップよりも小さい、
    　において、（１）と（２）の少なくとも一方が満たされている、不揮発性記憶素子。     A variable resistance nonvolatile memory element,
    A first electrode, a second electrode, a first electrode, and a second electrode interposed between the first electrode and the second electrode, and reversibly high resistance based on a polarity of a voltage applied between the first electrode and the second electrode. A resistance change layer that transitions between a state and a low resistance state,
    When the resistance change layer is in an initial state having a resistance value higher than the resistance value of the nonvolatile memory element when the resistance change layer is in the high resistance state, an initial break is applied to apply a voltage with the load element connected. Having the property of changing to a state where the transition is possible by being performed,
    The variable resistance layer includes at least a first oxide layer including an oxide of a first transition metal and a second oxide layer including an oxide of a second transition metal different from the first transition metal. Including a laminated structure,
    A standard electrode potential of the second transition metal is smaller than a standard electrode potential of the first transition metal;
    And,
    (1) The dielectric constant of the second oxide layer is larger than the dielectric constant of the first oxide layer.
    (2) The band gap of the second oxide layer is smaller than the band gap of the first oxide layer.
    (2) A nonvolatile memory element, wherein at least one of (1) and (2) is satisfied.
  2. 　（１）前記第２の酸化物層の誘電率が前記第１の酸化物層の誘電率よりも大きい、及び、（２）前記第２の酸化物層のバンドギャップが前記第１の酸化物層のバンドギャップよりも小さい、の両方が満たされている、請求項１に記載の不揮発性記憶素子。 (1) The dielectric constant of the second oxide layer is larger than the dielectric constant of the first oxide layer, and (2) the band gap of the second oxide layer is the first oxide. The nonvolatile memory element according to claim 1, wherein both are smaller than a band gap of the layer.
  3. 　前記第２電極は前記第２の酸化物層と接するように形成されており、
    　前記第２電極の標準電極電位が前記第２の遷移金属の標準電極電位よりも大きい、請求項１乃至請求項２の何れかに記載の不揮発性記憶素子。     The second electrode is formed in contact with the second oxide layer;
    The nonvolatile memory element according to claim 1, wherein a standard electrode potential of the second electrode is larger than a standard electrode potential of the second transition metal.
  4. 　前記第１の遷移金属の標準電極電位は、前記第２電極の標準電極電位より小さい、請求項３に記載の不揮発性記憶素子。 The nonvolatile memory element according to claim 3, wherein a standard electrode potential of the first transition metal is smaller than a standard electrode potential of the second electrode.
  5. 　前記第１の酸化物層の酸素欠損度が前記第２の酸化物層の酸素欠損度よりも大きい、請求項１乃至請求項４の何れかに記載の不揮発性記憶素子。 The nonvolatile memory element according to claim 1, wherein an oxygen deficiency degree of the first oxide layer is larger than an oxygen deficiency degree of the second oxide layer.
  6. 　前記第２の酸化物層の厚みが前記第１の酸化物層の厚みよりも薄い、請求項１乃至請求項５の何れかに記載の不揮発性記憶素子。 The nonvolatile memory element according to any one of claims 1 to 5, wherein a thickness of the second oxide layer is thinner than a thickness of the first oxide layer.
  7. 　前記第２の酸化物層の抵抗率が前記第１の酸化物層の抵抗率よりも大きい、請求項１乃至請求項６の何れかに記載の不揮発性記憶素子。 The nonvolatile memory element according to any one of claims 1 to 6, wherein a resistivity of the second oxide layer is larger than a resistivity of the first oxide layer.
  8. 　前記第２の遷移金属がＴｉ、Ｓｒ又はＮｂである、請求項１乃至請求項７の何れかに記載の不揮発性記憶素子。 The nonvolatile memory element according to any one of claims 1 to 7, wherein the second transition metal is Ti, Sr, or Nb.
  9. 　前記第１の遷移金属がＴａである、請求項８に記載の不揮発性記憶素子。 The nonvolatile memory element according to claim 8, wherein the first transition metal is Ta.
  10. 　さらに、当該不揮発性記憶素子に電気的に接続された負荷素子を備える、請求項１乃至請求項９の何れかに記載の不揮発性記憶素子。 Furthermore, the non-volatile memory element in any one of Claim 1 thru | or 9 provided with the load element electrically connected to the said non-volatile memory element.
  11. 　前記負荷素子は、固定抵抗、トランジスタ、またはダイオードである、請求項１０に記載の不揮発性記憶素子。 The nonvolatile memory element according to claim 10, wherein the load element is a fixed resistor, a transistor, or a diode.
  12. 　半導体基板と、前記半導体基板上に互いに平行に形成された複数の第１の配線と、前記複数の第１の配線の上方に前記半導体基板の主面に平行な面内において互いに平行に且つ前記複数の第１の配線と立体交差するように形成された複数の第２の配線と、前記複数の第１の配線と前記複数の第２の配線との立体交差点に対応して設けられた請求項１乃至請求項１１のいずれかに記載の不揮発性記憶素子とを具備するメモリセルアレイと、
    　前記メモリセルアレイが具備する不揮発性記憶素子から、少なくとも一つの不揮発性記憶素子を選択する選択回路と、
    　前記選択回路で選択された不揮発性記憶素子に電圧を印加することでデータを書き込む書き込み回路と、
    　前記選択回路で選択された不揮発性記憶素子の抵抗値を検出することでデータを読み出す読み出し回路とを備える、不揮発性記憶装置。     A semiconductor substrate, a plurality of first wirings formed in parallel to each other on the semiconductor substrate, and a plurality of first wirings parallel to each other in a plane parallel to a main surface of the semiconductor substrate above the plurality of first wirings A plurality of second wirings formed so as to three-dimensionally intersect with the plurality of first wirings, and the three-dimensional intersections of the plurality of first wirings and the plurality of second wirings. A memory cell array comprising the nonvolatile memory element according to any one of Items 1 to 11;
    A selection circuit for selecting at least one nonvolatile memory element from the nonvolatile memory elements included in the memory cell array;
    A writing circuit for writing data by applying a voltage to the nonvolatile memory element selected by the selection circuit;
    A non-volatile memory device comprising: a read circuit that reads data by detecting a resistance value of the non-volatile memory element selected by the selection circuit.
  13. 　さらに、前記不揮発性記憶素子のそれぞれに電気的に接続された電流抑制素子を備える、請求項１２に記載の不揮発性記憶装置。 The nonvolatile memory device according to claim 12, further comprising a current suppressing element electrically connected to each of the nonvolatile memory elements.
  14. 　半導体基板と、前記半導体基板上に形成された、複数のワード線及び複数のビット線、前記複数のワード線及び複数のビット線にそれぞれ接続された複数のトランジスタ、並びに前記複数のトランジスタに一対一で対応して設けられた複数の請求項１乃至請求項１１のいずれかに記載の不揮発性記憶素子とを具備するメモリセルアレイと、
    　前記メモリセルアレイが具備する不揮発性記憶素子から、少なくとも一つの不揮発性記憶素子を選択する選択回路と、
    　前記選択回路で選択された不揮発性記憶素子に電圧を印加することでデータを書き込む書き込み回路と、
    　前記選択回路で選択された不揮発性記憶素子の抵抗値を検出することでデータを読み出す読み出し回路とを備える、不揮発性記憶装置。     A semiconductor substrate, a plurality of word lines and a plurality of bit lines formed on the semiconductor substrate, a plurality of transistors respectively connected to the plurality of word lines and a plurality of bit lines, and a one-to-one correspondence to the plurality of transistors A memory cell array comprising a plurality of nonvolatile memory elements according to any one of claims 1 to 11 provided corresponding to
    A selection circuit for selecting at least one nonvolatile memory element from the nonvolatile memory elements included in the memory cell array;
    A writing circuit for writing data by applying a voltage to the nonvolatile memory element selected by the selection circuit;
    A non-volatile memory device comprising: a read circuit that reads data by detecting a resistance value of the non-volatile memory element selected by the selection circuit.
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