WO2010064346A1 - Semiconductor device and method for manufacturing same - Google Patents

Semiconductor device and method for manufacturing same Download PDF

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Publication number
WO2010064346A1
WO2010064346A1 PCT/JP2009/004507 JP2009004507W WO2010064346A1 WO 2010064346 A1 WO2010064346 A1 WO 2010064346A1 JP 2009004507 W JP2009004507 W JP 2009004507W WO 2010064346 A1 WO2010064346 A1 WO 2010064346A1
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WO
WIPO (PCT)
Prior art keywords
insulating film
interlayer insulating
wiring
film
semiconductor device
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PCT/JP2009/004507
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French (fr)
Japanese (ja)
Inventor
岩崎晃久
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パナソニック株式会社
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Publication of WO2010064346A1 publication Critical patent/WO2010064346A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02203—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being porous
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1005—Formation and after-treatment of dielectrics
    • H01L2221/1042—Formation and after-treatment of dielectrics the dielectric comprising air gaps
    • H01L2221/1047—Formation and after-treatment of dielectrics the dielectric comprising air gaps the air gaps being formed by pores in the dielectric

Definitions

  • the present invention relates to a semiconductor device having an interlayer insulating film in which wiring is formed and a method for manufacturing the same.
  • FIG. 7 is a cross-sectional view showing a configuration of a conventional semiconductor device.
  • a conventional semiconductor device includes an insulating film 100 formed on a semiconductor substrate (not shown), and an insulating film formed on the insulating film 100 and made porous by detachment of the porogen 101a.
  • 101 a coating insulating film 102 formed on the insulating film 101 and made of a non-porous insulating film, a via 103 formed in the insulating film 101, and formed in the coating insulating film 102 and connected to the via 103 Wiring 104 is provided.
  • the insulating film 101 has a non-porous region 101A where the porogen 101a remains.
  • the insulating film 101 has a dense region where the vias 103 are densely arranged and a sparse region where the vias 103 are arranged more sparsely than the dense region, and the non-porous region 101A is between the vias 103 in the sparse region. It is provided in the center.
  • the insulating film 101 has the non-porous region 101A in the center between the vias 103 in the sparse region, the insulating film 101, the insulating film 100, and the like are compared with the insulating film in which the entire region is made porous. The contact area becomes larger. Accordingly, a decrease in adhesion between the insulating film 101 and the insulating film 100 can be suppressed, and occurrence of separation at the interface between the insulating film 101 and the insulating film 100 can be suppressed.
  • the conventional semiconductor device has the following problems.
  • the non-porous region 101A is provided only at the center between the vias 103 in the sparse region of the insulating film 101, and in the region other than the non-porous region 101A in the insulating film 101.
  • the hole 101b exists. Therefore, a void 101b exists at the interface with the insulating film 100 in a region other than the non-porous region 101A in the insulating film 101, and the insulating film 101 (particularly, the insulating film 101 other than the non-porous region 101A). There is a possibility that peeling occurs at the interface between the region) and the insulating film 100.
  • the non-porous region 101A suppresses the occurrence of peeling at the interface between the insulating film 101 and the lower layer (that is, the insulating film 100) formed under the insulating film 101. Although it is possible, there still remains a problem that peeling occurs at the interface between the insulating film 101 and the insulating film 100.
  • an object of the present invention is to prevent peeling at the interface between an interlayer insulating film and a lower layer formed under the interlayer insulating film in a semiconductor device having an interlayer insulating film in which wiring is formed. It is to be.
  • a semiconductor device includes a first interlayer insulating film formed on a semiconductor substrate and a second interlayer formed on the first interlayer insulating film.
  • the porous region is formed in a region located around the first wiring in the second interlayer insulating film, and the non-porous region is at least between the first interlayer insulating film and the porous region. It is characterized by being formed in the middle.
  • a porous region is provided in a region located around the first wiring in the second interlayer insulating film, and a non-porous region is provided in a region other than the porous region.
  • the porous region in a region located around the first wiring in the second interlayer insulating film, it is effective in reducing the capacitance between the wirings in the second interlayer insulating film. Since the porous region can be provided in the contributing region, the inter-wiring capacitance can be effectively reduced and the speed of the semiconductor device can be increased.
  • the “upper layer” means a layer formed on the second interlayer insulating film in contact with the second interlayer insulating film.
  • the pores contained in the porous region are pores formed by desorption of porogen, and the non-porous region contains porogen remaining without being desorbed. It is preferable.
  • the porous region is within a range from the side surface of the first wiring to the first distance and within a range from the bottom surface of the first wiring to the second distance. Preferably it is formed.
  • the first distance is not less than a distance corresponding to the minimum wiring interval and not more than a distance corresponding to 1.5 times the minimum wiring interval
  • the second distance is It is preferable that the distance corresponds to about 0.5 times the bottom interface distance between the bottom surface of the first wiring and the interface between the first interlayer insulating film and the second interlayer insulating film.
  • the non-porous region includes an interface region formed in a range from the interface between the second interlayer insulating film and the first interlayer insulating film to the third distance.
  • An inter-wiring region formed in a central portion between the wirings having a spacing larger than a spacing corresponding to twice the first distance among the wirings of the first wirings adjacent to each other; The distance is preferably a distance corresponding to about 0.5 times the bottom interface distance between the bottom surface of the first wiring and the interface between the first interlayer insulating film and the second interlayer insulating film.
  • the semiconductor device further includes a via formed in a lower region of the second interlayer insulating film, the via penetrating the non-porous region and the upper region being porous. It is preferable to be formed through the region.
  • the lower region of the via is surrounded by the non-porous region, there is no hole in the bottom region of the via, for example, moisture trapped in the hole or remaining in the hole It is possible to prevent the reliability of the via from being deteriorated due to the etching of the etching gas or the like to oxidize the bottom area of the via or to corrode the bottom area of the via.
  • the semiconductor device further includes a second wiring formed in the first interlayer insulating film, and the first wiring is connected to the second wiring through the via. Is preferred.
  • a non-porous region having a film thickness substantially the same as the film thickness of the porous region is provided in a region located between the second wiring and the first wiring in the second interlayer insulating film. be able to. Therefore, the mechanical strength of the region located between the second wiring and the first wiring in the second interlayer insulating film is ensured (specifically, for example, the second interlayer insulating film includes the second interlayer insulating film.
  • the region located between the first wiring and the first wiring can secure a Young's modulus of 8 GPa or more), so that it is located between the second wiring and the first wiring in the second interlayer insulating film. It is possible to prevent cracks from occurring in the region.
  • the Young's modulus of a region located between the second wiring and the first wiring in the second interlayer insulating film is preferably 8 GPa or more.
  • the semiconductor device further includes a barrier film formed between the first interlayer insulating film and the second interlayer insulating film, and the via includes a lower region of the second interlayer insulating film, And it is preferable to be formed through the barrier film.
  • the semiconductor device further includes a cap film formed on the second interlayer insulating film, and the first wiring is formed in the upper region of the second interlayer insulating film and the cap film. It is preferable.
  • a method of manufacturing a semiconductor device includes a step (a) of forming a first interlayer insulating film on a semiconductor substrate, and a step on the first interlayer insulating film. And (b) forming a second interlayer insulating film forming film containing porogen, and forming a hard mask having a wiring groove forming groove formed on the second interlayer insulating film forming film. Step (c) and using the hard mask, the porogen present in the region located in the vicinity of the trench for forming the trench is desorbed from the second interlayer insulating film, and the porogen is desorbed.
  • the first wiring groove is porous. It is formed in a region.
  • a porous region can be provided in a region located around the first wiring, and a non-porous region can be provided in a region other than the porous region.
  • a non-porous region can be provided between the first interlayer insulating film and the porous region (in other words, a region located at the interface with the lower layer in the second interlayer insulating film). Therefore, there is no hole at the interface with the lower layer in the second interlayer insulating film, and the adhesion between the second interlayer insulating film and the lower layer is not reduced by the hole. Therefore, for example, it is possible to prevent peeling at the interface between the second interlayer insulating film and the lower layer during the CMP process or the like in the first wiring formation process.
  • the porous region in a region located around the first wiring in the second interlayer insulating film, it is effective in reducing the capacitance between the wirings in the second interlayer insulating film. Since the porous region can be provided in the contributing region, the inter-wiring capacitance can be effectively reduced and the speed of the semiconductor device can be increased.
  • a non-porous region can be provided in the central portion between the first wirings having a relatively large wiring interval.
  • the porogen contained in the second interlayer insulating film forming film is a porogen that is desorbed by irradiation with ultraviolet rays or electron beams.
  • the hard mask is made of a metal film that reflects ultraviolet rays or electron beams, and the step (d) is preferably a step of irradiating the semiconductor substrate with ultraviolet rays or electron beams.
  • ultraviolet rays or an electron beam with which an ultraviolet ray or an electron beam is irradiated to a hard mask will be reflected by a hard mask, and among the 2nd interlayer insulation film formation films, it will be a wiring groove formation groove. A region located in the vicinity is irradiated with ultraviolet rays or an electron beam.
  • the first ultraviolet ray or the first electron beam is applied on the semiconductor substrate in a direction perpendicular to the main surface of the semiconductor substrate. It is preferable to include a step (d1) of irradiating and a step (d2) of irradiating the second ultraviolet ray or the second electron beam on the semiconductor substrate in a direction inclined with respect to the main surface of the semiconductor substrate. .
  • the material of the metal film that reflects ultraviolet rays or electron beams is one type selected from the group consisting of Ti, TiN, Ta, TaN, W, and WN, Or it is preferable that they are a multiple types of metal material.
  • the porogen contained in the second interlayer insulating film forming film is a porogen that is desorbed by irradiation with ultraviolet rays or electron beams.
  • the hard mask is made of an insulating film that absorbs ultraviolet rays or electron beams, and the step (d) is preferably a step of irradiating the semiconductor substrate with ultraviolet rays or electron beams.
  • ultraviolet rays or an electron beam irradiated to a hard mask among ultraviolet rays or an electron beam will be absorbed by a hard mask, and it will become a groove
  • a region located in the vicinity is irradiated with ultraviolet rays or an electron beam.
  • the material of the insulating film that absorbs ultraviolet rays or electron beams is one type selected from the group consisting of SiCN, SiCO, SiCH, SiON, SiO 2 , and SiN. Or a plurality of types of insulating materials.
  • the porogen contained in the second interlayer insulating film forming film is a porogen that is desorbed by heat treatment
  • the step (c) The hard mask is made of a film having a higher density than the first interlayer insulating film containing no porogen, and the step (d) is preferably a step of performing heat treatment on the entire surface of the semiconductor substrate.
  • the hard mask material includes a metal material group consisting of Ti, TiN, Ta, TaN, W, and WN, and SiCN, SiCO, SiCH, SiON, SiO 2 , And one or more types of materials selected from the insulating material group consisting of SiN.
  • the step (e) further includes a step of forming a via hole in a lower region of the second interlayer insulating film, and the step (f) includes forming a via in the via hole.
  • the via hole is preferably formed so that the lower region penetrates the non-porous region and the upper region penetrates the porous region.
  • the lower region of the via is surrounded by the non-porous region, there is no hole in the bottom region of the via, for example, moisture trapped in the hole or remaining in the hole It is possible to prevent the reliability of the via from being deteriorated due to the etching of the etching gas or the like to oxidize the bottom area of the via or to corrode the bottom area of the via.
  • the second wiring trench is formed in the first interlayer insulating film, and then the second wiring is formed.
  • the method further includes a step (g) of forming the second wiring in the groove.
  • a non-porous region having a film thickness substantially the same as the film thickness of the porous region is provided in a region located between the second wiring and the first wiring in the second interlayer insulating film. be able to. Therefore, the mechanical strength of the region located between the second wiring and the first wiring in the second interlayer insulating film can be ensured.
  • the wire to be formed after the first wiring forming step In the bonding process, the probe inspection process, or the like it is possible to prevent a crack from occurring in a region located between the second wiring and the first wiring in the second interlayer insulating film.
  • a cap film having a groove and a hard mask having a groove for forming a wiring groove communicating with the groove are sequentially formed on the second interlayer insulating film forming film.
  • the first wiring trench is preferably formed in the upper region of the second interlayer insulating film and the cap film.
  • the step (c) includes a step (c1) of forming a hard mask on the cap film, and a trench for forming a wiring groove on the hard mask after the step (c1). And a step (c2) of forming a groove in the cap film.
  • a porous region is provided in a region located around the first wiring in the second interlayer insulating film, and the region other than the porous region is provided.
  • the non-porous region is provided between the first interlayer insulating film and the porous region (in other words, the region located at the interface with the lower layer in the second interlayer insulating film).
  • the porous region in a region located around the first wiring in the second interlayer insulating film, it is effective in reducing the capacitance between the wirings in the second interlayer insulating film. Since the porous region can be provided in the contributing region, the inter-wiring capacitance can be effectively reduced and the speed of the semiconductor device can be increased.
  • a non-porous region can be provided in the central portion between the first wirings having a relatively large wiring interval. Thereby, it is possible to prevent the occurrence of peeling at the interface between the second interlayer insulating film and the upper layer.
  • FIGS. 1A and 1B are diagrams showing a configuration of a semiconductor device according to an embodiment of the present invention.
  • FIG. 2 is a cross-sectional view showing a configuration of a semiconductor device according to an embodiment of the present invention.
  • FIGS. 3A to 3C are principal part process cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of processes.
  • FIGS. 4A to 4C are principal part process cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of processes.
  • FIGS. 5A to 5C are principal part process cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of processes.
  • FIGS. 6A and 6B are cross-sectional views showing a configuration of a semiconductor device according to a specific example of an embodiment of the present invention.
  • FIG. 7 is a cross-sectional view showing a configuration of a conventional semiconductor device
  • FIGS. 1A and 1B are diagrams showing a configuration of a semiconductor device according to an embodiment of the present invention. Specifically, FIG. 1A is a plan view, and FIG. FIG. 2 is a cross-sectional view taken along line Ib-Ib shown in FIG.
  • a first interlayer insulating film (see FIG. 1B: 10), a barrier film (see FIG. 1B: 13), A second interlayer insulating film (see FIG. 1B: 14) and a cap film 15 are sequentially formed.
  • a via 20 is formed in the lower region of the second interlayer insulating film, and a wiring 21 connected to the via 20 is formed in the upper region of the second interlayer insulating film and the cap film 15.
  • the semiconductor device is formed on the first interlayer insulating film 10 formed on the semiconductor substrate (not shown) and the first interlayer insulating film 10.
  • An upper layer wiring (first wiring) 21 formed in the upper region of the film 14 and the cap film 15 and connected to the via 20 is provided.
  • the lower layer wiring 12 includes a barrier metal film 12a formed on the bottom and side surfaces of the lower layer wiring groove 11, and a conductive film 12b embedded in the lower layer wiring groove 11 via the barrier metal film 12a.
  • the via 20 includes a barrier metal film 20a formed on the bottom and side surfaces of the via hole 18 and a conductive film 20b embedded in the via hole 18 via the barrier metal film 20a.
  • the upper layer wiring 21 includes a barrier metal film 21a formed on the bottom and side surfaces of the upper layer wiring groove 19 and a conductive film 21b embedded in the upper layer wiring groove 19 via the barrier metal film 21a.
  • the second interlayer insulating film 14 includes a porous region 14B containing pores 14b from which porogens 14a are desorbed and porogen 14a remaining without being desorbed. It is comprised with the non-porous area
  • the porous region 14B is formed in a region located around the upper layer wiring 21 in the second interlayer insulating film 14, as shown in FIG. Specifically, as shown in FIG. 2, the porous region 14 ⁇ / b> B is within the range from the side surface of the upper layer wiring 21 to the first distance Ds (see FIG. 2) and from the bottom surface of the upper layer wiring 21 to the second distance. It is formed within the range up to Db (see FIG. 2).
  • the first distance Ds is a distance along a direction perpendicular to the side surface of the upper layer wiring 21, and the second distance Db is a distance along a direction perpendicular to the bottom surface of the upper layer wiring 21. It is.
  • FIG. 2 is the same diagram as that shown in FIG.
  • the first distance Ds is not less than a distance corresponding to the minimum wiring interval Smin and not more than a distance corresponding to 1.5 times the minimum wiring interval Smin (Smin ⁇ Ds ⁇ Smin ⁇ 1.5).
  • the “minimum wiring interval Smin” corresponds to the smallest interval among the wiring intervals of the upper layer wirings 21 adjacent to each other.
  • the non-porous region 14A is not overlapped between the barrier film 13 and the porous region 14B and between the porous regions 14B adjacent to each other (particularly, the porous regions 14B adjacent to each other do not overlap each other). Between the spaced apart porous regions 14B). Specifically, as shown in FIG. 2, the non-porous region 14A is formed within a range from the interface between the second interlayer insulating film 14 and the barrier film 13 to the third distance Di (see FIG. 2).
  • the inter-wiring region 14As formed in the central portion between the interfacial region 14Ai and the wiring of the upper-layer wiring 21 adjacent to each other having a spacing larger than the spacing corresponding to twice the first distance Ds.
  • the inter-wiring region 14As of the non-porous region 14A is an inter-wiring region having an interval (> Ds ⁇ 2) larger than an interval corresponding to twice the first distance Ds among the wirings of the upper layer wirings 21 adjacent to each other. Is formed between the wirings having an interval ( ⁇ Ds ⁇ 2) that is equal to or less than an interval corresponding to twice the first distance Ds.
  • the via 20 has a lower region penetrating the interface region 14Ai of the non-porous region 14A and an upper region of the via 20 at the bottom surface of the porous region 14B, as shown in FIG. It is formed through the region.
  • the upper layer wiring 21 is formed in the porous region 14B.
  • the “bottom surface region” refers to a region formed in the range from the bottom surface of the upper layer wiring 21 to the second distance Db (see FIG. 2) in the porous region 14B.
  • the film thickness (see FIG. 2: Db) substantially the same as the film thickness of the bottom region of the porous region 14B (see FIG. 2).
  • the Young's modulus of the region located between the lower layer wiring 12 and the upper layer wiring 21 in the second interlayer insulating film 14 is 8 GPa or more.
  • FIGS. 3A to FIG. 5C are cross-sectional views of relevant steps showing a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps.
  • a first interlayer insulation made of, for example, a carbon-containing silicon oxide film (SiOC (H) film) having a relative dielectric constant of 3.0 on a semiconductor substrate (not shown).
  • a film 10 is formed.
  • the first interlayer insulating film is used using the resist pattern as a mask. 10 is dry-etched to form a lower wiring trench 11 in the first interlayer insulating film 10. Subsequently, the resist pattern is removed.
  • a seed film containing, for example, copper is formed on the barrier metal film by sputtering
  • a plating film containing, for example, copper is buried by embedding the lower wiring groove 11 on the seed film by electrolytic plating. To deposit.
  • the lower layer wiring 12 is formed in which the conductive film 12b containing copper is buried in the lower layer wiring trench 11 via the barrier metal film 12a.
  • the boundary line between the seed film and the plating film in the conductive film 12b is not shown because it is difficult to show.
  • a silicon carbonitride film (for example, having a film thickness of 40 nm) is formed on the first interlayer insulating film 10 and the lower layer wiring 12 by plasma CVD (Chemical Vapor Deposition).
  • a barrier film 13 made of SiCN film is deposited.
  • the deposition conditions of the barrier film 13 by the plasma CVD method the following conditions may be mentioned. For example, under a temperature of 400 ° C., tetramethylsilane (Si (CH 3 ) 4 ) gas and ammonia (NH 3 ) gas are used as the source gas, and helium (He) gas is used as the dilution gas.
  • the barrier film 13 is deposited by the CVD method.
  • the barrier film 13 preferably has a density of, for example, 1.8 g / cm 3 , and preferably has a refractive index of, for example, 1.8 to 2.2 (wavelength 633 nm).
  • a second interlayer insulating film forming film 14X is deposited.
  • a deposition method of the second interlayer insulating film forming film 14X it is more preferable to use a plasma CVD method.
  • a cap film 15 made of, for example, a SiOC (H) film having a thickness of 40 nm is deposited on the second interlayer insulating film forming film 14X by plasma CVD.
  • a resist pattern (not shown) having an upper wiring groove pattern is formed on the hard mask 16 by photolithography.
  • dry etching is sequentially performed on the hard mask 16 and the cap film 15 to form the upper wiring groove forming groove 16y in the hard mask 16 and the groove 15y in the cap film 15.
  • a groove 16Y that penetrates the hard mask 16 and the cap film 15 and exposes the upper surface of the second interlayer insulating film forming film 14X is formed.
  • the resist pattern is removed. In this manner, the cap film 15 in which the groove 15y is formed and the hard mask 16 in which the upper-layer wiring groove forming groove 16y communicating with the groove 15y is sequentially formed on the second interlayer insulating film forming film 14X.
  • the entire surface of the semiconductor substrate is irradiated with ultraviolet rays, for example, at an irradiation angle (that is, an angle inclined with respect to the normal of the main surface of the semiconductor substrate) of 0 °. That is, the entire surface of the semiconductor substrate is irradiated with ultraviolet rays in a direction perpendicular to the main surface of the semiconductor substrate (see UV1).
  • the ultraviolet ray irradiated to the hard mask 16 out of the ultraviolet rays is reflected by the hard mask 16, and the ultraviolet ray is irradiated to a region located in the vicinity of the groove 16Y in the second interlayer insulating film forming film 14X. Is done.
  • the ultraviolet rays are preferably irradiated with low energy of 150 nm to 380 nm, for example, for a short time of 10 seconds to 20 seconds.
  • the region located in the vicinity of the groove 16Y in the second interlayer insulating film forming film 14X appearing in this specification refers to the second interlayer insulating film forming film 14X. 1) A region located directly below the groove 16Y and 2) a region located below the outer periphery of the groove 16Y.
  • the entire surface of the semiconductor substrate is irradiated with ultraviolet rays at an irradiation angle of 45 °, that is, the entire surface of the semiconductor substrate is irradiated with ultraviolet rays in a direction inclined with respect to the main surface of the semiconductor substrate (UV2). reference).
  • the ultraviolet ray irradiated to the hard mask 16 out of the ultraviolet rays is reflected by the hard mask 16, and the ultraviolet ray is irradiated to a region located in the vicinity of the groove 16Y in the second interlayer insulating film forming film 14X.
  • the ultraviolet rays are preferably irradiated with low energy of 150 nm to 380 nm, for example, for a short time of 10 seconds to 20 seconds.
  • the porous region 14B is formed so as to expand outward with respect to the center point C of the bottom surface of the groove 16Y, and within a range from the center point C to the distance Dh (see FIG. 4 (c)), and It is formed within a range from the center point C to the distance Dv (see FIG. 4C).
  • the distance Dh is a distance along a direction parallel to the bottom surface of the groove 16Y
  • the distance Dv is a distance along a direction perpendicular to the bottom surface of the groove 16Y.
  • the groove 16Y is formed using the resist pattern as a mask.
  • the second interlayer insulating film 14 exposed inside is dry-etched to form a hole 17 that penetrates the second interlayer insulating film 14 and exposes the upper surface of the barrier film 13. Subsequently, the resist pattern is removed.
  • the barrier film 13 exposed in the holes 17 is removed by an etch-back method, and the lower layer wiring 12 is formed in the lower regions of the barrier film 13 and the second interlayer insulating film.
  • a via hole 18 is formed to expose the upper surface of.
  • the upper region of the second interlayer insulating film 14 exposed in the trench 16Y is removed using the hard mask 16, and the upper layer wiring trench is formed in the upper region of the second interlayer insulating film 14 and the cap film 15. 19 is formed.
  • the via hole 18 has a lower region penetrating the interface region of the non-porous region 14A (see FIG. 1B: 14Ai), and an upper region thereof being a porous region. It is formed through the bottom area of 14B.
  • the upper wiring groove 19 is formed in the porous region 14B as shown in FIG. 5 (b).
  • Ta layer is formed on the hard mask 16, the side surfaces of the upper wiring groove forming groove 16y, the bottom surface and side surfaces of the upper wiring groove 19, and the bottom surface and side surfaces of the via hole 18.
  • a barrier metal film in which a film and a TaN film are sequentially stacked is deposited.
  • a seed film containing copper is formed on the barrier metal film by a sputtering method, and then plating containing copper so as to bury the via hole 18 and the upper wiring groove 19 on the seed film by an electrolytic plating method. Deposit a film.
  • portions of the plating film, seed film, barrier metal film, and hard mask 16 formed outside the via hole 18 and the upper wiring groove 19 are sequentially removed by CMP.
  • vias 20 are formed in the via holes 18 by burying the conductive films 20b containing copper via the barrier metal films 20a.
  • an upper layer wiring 21 is formed in which a conductive film 21b containing copper is embedded through a barrier metal film 21a.
  • the via 20 has a lower region penetrating the interface region of the non-porous region 14A (see FIG. 1B: 14Ai), and an upper region of the via 20 is a porous region. It is formed through the bottom area of 14B.
  • the upper layer wiring 21 is formed in the porous region 14B as shown in FIG. 5 (c) (in other words, the porous region 14B is the upper layer wiring 21 in the second interlayer insulating film 14).
  • the boundary line between the seed film and the plating film in the conductive films 20b and 21b is not shown because it is difficult to show.
  • the semiconductor device according to this embodiment can be manufactured.
  • the resist having a via hole pattern in the step shown in FIG. A pattern (not shown) is formed, and subsequently, vias 20 are formed in the via holes 18 and upper wirings 21 are formed in the upper wiring grooves 19 in the step shown in FIG. That is, in this embodiment, the via 20 and the upper layer wiring 21 are formed by a trench first method in which a resist pattern having an upper layer wiring groove pattern is formed first and a via last dual damascene method in which a resist pattern having a via hole pattern is formed later. Is adopted.
  • a porous region 14B is provided in a region located around the upper-layer wiring 21 in the second interlayer insulating film 14, and the regions other than the porous region 14B are provided.
  • the interface region 14Ai of the non-porous region 14A can be provided in the region located in the interface with the barrier film 13 in the second interlayer insulating film 14. Therefore, there is no hole 14b at the interface between the second interlayer insulating film 14 and the barrier film 13, and the adhesion between the second interlayer insulating film 14 and the barrier film 13 is reduced by the hole 14b. There is no. Therefore, for example, a CMP step in the step shown in FIG.
  • a step of connecting a wire bond to a pad (not shown) formed on the upper layer wiring 21 (hereinafter referred to as “wire bonding step”), or a pad Prevents the occurrence of delamination at the interface between the second interlayer insulating film 14 and the barrier film 13 during an inspection process (hereinafter referred to as “probe inspection process”) in which an internal circuit is inspected by applying a probe needle to can do.
  • the second interlayer insulating film 14 is provided.
  • the porous region 14B can be provided in a region that effectively contributes to the reduction of the inter-wiring capacitance, so that the inter-wiring capacitance can be effectively reduced and the speed of the semiconductor device can be increased.
  • a relatively large wiring interval (specifically, a wiring interval larger than an interval corresponding to twice the first distance Ds in the second interlayer insulating film 14).
  • the inter-wiring region 14As of the non-porous region 14A can be provided in the center between the upper-layer wirings 21 having the
  • the area between the upper layer wirings 21 having a relatively large wiring interval has a relatively large contact area with the cap film 15, and the possibility that separation occurs at the interface with the cap film 15 is relatively high.
  • the inter-wiring region 14As of the non-porous region 14A in the center between the upper layer wirings 21 having a relatively large wiring interval, for example, in the CMP process, the second interlayer insulating film 14 and It is possible to prevent the peeling from occurring at the interface with the cap film 15.
  • the area between the upper layer wirings 21 having a relatively small wiring interval has a smaller contact area with the cap film 15 than the region between the upper layer wirings 21 having a relatively large wiring interval, and the interface with the cap film 15. Is less likely to peel. Therefore, it is not necessary to provide a non-porous region in a region between the upper layer wirings 21 having a relatively small wiring interval.
  • the thickness of the bottom region of the porous region 14B in the region located between the lower layer wiring 12 and the upper layer wiring 21 in the second interlayer insulating film 14 (FIG. 2). : Db) can be provided with the interface region 14Ai of the non-porous region 14A having substantially the same film thickness (see FIG. 2: Di). Therefore, the mechanical strength of a region located between the lower layer wiring 12 and the upper layer wiring 21 in the second interlayer insulating film 14 is ensured (specifically, for example, the lower layer wiring in the second interlayer insulating film 14). 12 and the upper layer wiring 21 can secure a Young's modulus of 8 GPa or more). Therefore, for example, in the wire bonding process or the probe inspection process, it is possible to prevent the second interlayer insulating film 14 from being cracked in a region located between the lower layer wiring 12 and the upper layer wiring 21. Can do.
  • the inter-wiring capacitance can be effectively reduced and the occurrence of peeling at the interface between the second interlayer insulating film 14 and the barrier film 13 can be prevented.
  • the porous region 14B contains only the pores 14b and does not contain the porogen 14a
  • the non-porous region 14A contains only the porogen 14a and does not contain the pores 14b
  • the porous region 14B contains not only the holes 14b but also a smaller number of porogens 14a than the number of the holes 14b
  • the non-porous region 14A includes not only the porogens 14a but also the number of porogens 14a.
  • a smaller number of holes 14b may be contained.
  • pores 14b and porogens 14a may be mixed in the boundary region between the porous region 14B and the non-porous region 14A.
  • the “porous region” in the present specification is a region mainly containing pores, while the “non-porous region” in the present specification is a region not mainly containing pores.
  • the “porous region” is a region having a higher pore density than the “non-porous region”, while the “non-porous region” is lower than the “porous region”. This is a region having a void density.
  • the case where TiN is used as the metal material of the hard mask 16 that reflects ultraviolet rays has been described as a specific example, but the present invention is not limited to this.
  • the metal material of the hard mask that reflects ultraviolet rays for example, one or more kinds of metal materials selected from the group consisting of Ti, Ta, TaN, W, WN, and the like may be used.
  • the entire surface of the semiconductor substrate is irradiated with ultraviolet rays in a direction perpendicular to the main surface of the semiconductor substrate (see UV1), and then on the semiconductor substrate.
  • ultraviolet rays are irradiated on the entire surface in a direction inclined with respect to the main surface of the semiconductor substrate (see UV2)
  • the present invention is not limited to this.
  • the entire surface of the semiconductor substrate is irradiated with ultraviolet rays only in a direction perpendicular to the main surface of the semiconductor substrate.
  • the entire surface of the semiconductor substrate is irradiated on the main surface of the semiconductor substrate.
  • the ultraviolet rays may be irradiated only in the direction inclined with respect to the surface.
  • the hard mask 16 is a metal that reflects ultraviolet rays.
  • a case where a film is used and a porogen that is desorbed by irradiation of ultraviolet rays is adopted as the porogen 14a and the entire surface of the semiconductor substrate is irradiated with ultraviolet rays has been described as a specific example, but the present invention is not limited thereto. It is not something.
  • an insulating film that absorbs ultraviolet rays may be employed as the hard mask, and porogen that is desorbed by ultraviolet irradiation may be employed as the porogen, and the entire surface of the semiconductor substrate may be irradiated with ultraviolet rays.
  • the cap film having the groove and the hard mask having the upper wiring groove forming groove are sequentially formed on the second interlayer insulating film forming film and then irradiated with ultraviolet rays.
  • the ultraviolet ray irradiated to the hard mask among the ultraviolet rays is absorbed by the hard mask, and in the second interlayer insulating film forming film, the region located in the vicinity of the groove and the upper wiring groove forming groove, Ultraviolet rays are irradiated.
  • the insulating material of the hard mask that absorbs ultraviolet rays for example, one type or a plurality of types of insulating materials selected from the group consisting of SiCN, SiCO, SiCH, SiON, SiO 2 , SiN, and the like can be given. .
  • a metal film that reflects an electron beam is used as a hard mask, and a porogen that is detached by irradiation with an electron beam is used as a porogen. Good.
  • an insulating film that absorbs an electron beam is used as a hard mask, and a porogen that is desorbed by irradiation with an electron beam is used as a porogen. Good.
  • a film having a relatively high density may be employed as the hard mask, and a porogen that is desorbed by heat treatment may be employed as the porogen, and the entire surface of the semiconductor substrate may be heat treated.
  • heat treatment is performed in a state in which the cap film in which the groove is formed and the hard mask in which the groove for forming the upper wiring groove is formed in order on the second interlayer insulating film forming film.
  • the porogen present in the region located in the vicinity of the groove and the upper wiring groove forming groove can be removed.
  • the heat treatment temperature is preferably a low temperature of 300 ° C., for example, and the heat treatment time is preferably a short time of about several tens of seconds to 3 minutes, for example.
  • the density of the hard mask is preferably about 2.21 g / cm 3 , for example.
  • the material of the hard mask for example, a metal material group made of Ti, TiN, Ta, TaN, W, WN, etc., and an insulation made of SiCN, SiCO, SiCH, SiON, SiO 2 , SiN, etc.
  • One type or a plurality of types of materials selected from the material group can be mentioned.
  • the density of the cap film is relatively high, without providing a hard mask on the cap film, only the cap film in which the groove is formed is formed on the second interlayer insulating film forming film. Heat treatment may be performed.
  • a SiCN film is used as the barrier film 13
  • the present invention is not limited to this.
  • a silicon carbonate film SiCO film
  • SiCO film instead of the SiCN film.
  • a stacked film in which a SiCN film and a SiCO film are sequentially stacked may be used.
  • tetramethylsilane (Si (CH 3 ) 4 ) gas and carbon dioxide (CO 2 ) gas are used as the source gas at a temperature of 400 ° C.
  • Examples include a method performed by plasma CVD using helium (He) gas.
  • FIGS. 6A and 6B are cross-sectional views showing the configuration of a semiconductor device according to a specific example of one embodiment of the present invention.
  • the interval of the wiring interval Sab between the adjacent wirings 41a and 41b is larger than the interval corresponding to three times the minimum wiring interval Smin (Sab> Smin ⁇ 3).
  • the inter-wiring region of the non-porous region 34A has a wiring interval Sab that is larger than an interval corresponding to twice the first distance Ds among the wirings of the upper layer wirings adjacent to each other. Formed in the center between the wirings having
  • FIG. 6 (b) is the same diagram as that shown in FIG. 6 (a).
  • the porous region 34B is provided in a region located around the upper wirings 41a to 41c in the second interlayer insulating film 34, and the non-porous region 34A is provided in a region other than the porous region 34B.
  • the invention is not limited to this, and the first distance may be not less than a distance corresponding to the minimum wiring interval Smin and not more than a distance corresponding to 1.5 times the minimum wiring interval Smin.
  • the present invention can prevent peeling at the interface between the interlayer insulating film in which the wiring is formed and the lower layer formed in contact with the interlayer insulating film under the interlayer insulating film, the wiring is formed.
  • the present invention is useful for a semiconductor device having an interlayer insulating film and a manufacturing method thereof.

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Abstract

A semiconductor device is provided with: a first interlayer insulating film (10) formed on a semiconductor substrate; a second interlayer insulating film (14) formed on the first interlayer insulating film (10); and first wiring (21) formed on an upper region of the second interlayer insulating film (14).  The second interlayer insulating film (14) is composed of a porous region (14B) including holes (14b), and a non-porous region (14A).  The porous region (14B) is formed at a region positioned on the circumference of the first wiring (21) on the second interlayer insulating film (14).  The non-porous region (14A) is formed at least between the first interlayer insulating film (10) and the porous region (14B).

Description

半導体装置及びその製造方法Semiconductor device and manufacturing method thereof
　本発明は、配線が形成された層間絶縁膜を有する半導体装置及びその製造方法に関する。 The present invention relates to a semiconductor device having an interlayer insulating film in which wiring is formed and a method for manufacturing the same.
　近年、銅を含む配線を有する半導体装置において、配線間容量を低減させて、半導体装置の高速化を図るため、層間絶縁膜の低誘電率化が要求されている。そこで、層間絶縁膜として、多孔質化された低誘電率膜を利用することが検討されている。 In recent years, in a semiconductor device having a wiring containing copper, a reduction in the dielectric constant of the interlayer insulating film is required in order to reduce the capacitance between the wirings and increase the speed of the semiconductor device. Therefore, it has been studied to use a porous low dielectric constant film as an interlayer insulating film.
　層間絶縁膜として、多孔質化された低誘電率膜を用いた半導体装置について、図７を参照しながら説明する（例えば特許文献１参照）。図７は、従来の半導体装置の構成を示す断面図である。 A semiconductor device using a porous low dielectric constant film as an interlayer insulating film will be described with reference to FIG. 7 (see, for example, Patent Document 1). FIG. 7 is a cross-sectional view showing a configuration of a conventional semiconductor device.
　図７に示すように、従来の半導体装置は、半導体基板（図示省略）上に形成された絶縁膜１００と、絶縁膜１００上に形成され、ポロジェン１０１ａの脱離により多孔質化された絶縁膜１０１と、絶縁膜１０１上に形成され、非多孔質性の絶縁膜からなる被覆絶縁膜１０２と、絶縁膜１０１に形成されたビア１０３と、被覆絶縁膜１０２に形成され、ビア１０３と接続する配線１０４とを備えている。絶縁膜１０１は、ポロジェン１０１ａが残存する非多孔質領域１０１Ａを有している。 As shown in FIG. 7, a conventional semiconductor device includes an insulating film 100 formed on a semiconductor substrate (not shown), and an insulating film formed on the insulating film 100 and made porous by detachment of the porogen 101a. 101, a coating insulating film 102 formed on the insulating film 101 and made of a non-porous insulating film, a via 103 formed in the insulating film 101, and formed in the coating insulating film 102 and connected to the via 103 Wiring 104 is provided. The insulating film 101 has a non-porous region 101A where the porogen 101a remains.
　絶縁膜１０１は、ビア１０３が密に配置された密領域と、密領域よりもビア１０３が疎に配置された疎領域とを有し、非多孔質領域１０１Ａは、疎領域におけるビア１０３間の中央部に設けられている。 The insulating film 101 has a dense region where the vias 103 are densely arranged and a sparse region where the vias 103 are arranged more sparsely than the dense region, and the non-porous region 101A is between the vias 103 in the sparse region. It is provided in the center.
　従来では、絶縁膜１０１が、疎領域におけるビア１０３間の中央部に非多孔質領域１０１Ａを有することにより、全領域が多孔質化された絶縁膜に比べて、絶縁膜１０１と絶縁膜１００との接触面積が大きくなる。これにより、絶縁膜１０１と絶縁膜１００との密着性の低下を抑制し、絶縁膜１０１と絶縁膜１００との界面に剥離が発生することを抑制することが可能である。 Conventionally, since the insulating film 101 has the non-porous region 101A in the center between the vias 103 in the sparse region, the insulating film 101, the insulating film 100, and the like are compared with the insulating film in which the entire region is made porous. The contact area becomes larger. Accordingly, a decrease in adhesion between the insulating film 101 and the insulating film 100 can be suppressed, and occurrence of separation at the interface between the insulating film 101 and the insulating film 100 can be suppressed.
特開２００８－６０４９８号公報Japanese Patent Laid-Open No. 2008-60498
　しかしながら、従来の半導体装置では、以下に示す問題がある。 However, the conventional semiconductor device has the following problems.
　従来では、図７に示すように、非多孔質領域１０１Ａは、絶縁膜１０１の疎領域におけるビア１０３間の中央部にのみ設けられ、絶縁膜１０１のうち非多孔質領域１０１Ａ以外の領域には、空孔１０１ｂが存在する。そのため、絶縁膜１０１のうち非多孔質領域１０１Ａ以外の領域における絶縁膜１００との界面には、空孔１０１ｂが存在し、絶縁膜１０１（特に、絶縁膜１０１のうち非多孔質領域１０１Ａ以外の領域）と絶縁膜１００との界面に、剥離が発生するおそれがある。 Conventionally, as shown in FIG. 7, the non-porous region 101A is provided only at the center between the vias 103 in the sparse region of the insulating film 101, and in the region other than the non-porous region 101A in the insulating film 101. The hole 101b exists. Therefore, a void 101b exists at the interface with the insulating film 100 in a region other than the non-porous region 101A in the insulating film 101, and the insulating film 101 (particularly, the insulating film 101 other than the non-porous region 101A). There is a possibility that peeling occurs at the interface between the region) and the insulating film 100.
　即ち、従来では、既述の通り、非多孔質領域１０１Ａにより、絶縁膜１０１と、絶縁膜１０１下に形成された下層（即ち、絶縁膜１００）との界面に、剥離が発生することを抑制することは可能なものの、絶縁膜１０１と絶縁膜１００との界面に剥離が発生する問題が依然として残る。 That is, conventionally, as described above, the non-porous region 101A suppresses the occurrence of peeling at the interface between the insulating film 101 and the lower layer (that is, the insulating film 100) formed under the insulating film 101. Although it is possible, there still remains a problem that peeling occurs at the interface between the insulating film 101 and the insulating film 100.
　前記に鑑み、本発明の目的は、配線が形成された層間絶縁膜を有する半導体装置において、層間絶縁膜と、層間絶縁膜下に形成された下層との界面に、剥離が発生することを防止することである。 In view of the foregoing, an object of the present invention is to prevent peeling at the interface between an interlayer insulating film and a lower layer formed under the interlayer insulating film in a semiconductor device having an interlayer insulating film in which wiring is formed. It is to be.
　前記の目的を達成するために、本発明の一側面に係る半導体装置は、半導体基板上に形成された第１の層間絶縁膜と、第１の層間絶縁膜上に形成された第２の層間絶縁膜と、第２の層間絶縁膜の上部領域に形成された第１の配線とを備え、第２の層間絶縁膜は、空孔を含有する多孔質領域と、非多孔質領域とで構成され、多孔質領域は、第２の層間絶縁膜のうち、第１の配線の周囲に位置する領域に形成され、非多孔質領域は、少なくとも第１の層間絶縁膜と多孔質領域との間に介在して形成されていることを特徴とする。 In order to achieve the above object, a semiconductor device according to one aspect of the present invention includes a first interlayer insulating film formed on a semiconductor substrate and a second interlayer formed on the first interlayer insulating film. An insulating film; and a first wiring formed in an upper region of the second interlayer insulating film, wherein the second interlayer insulating film includes a porous region containing pores and a non-porous region The porous region is formed in a region located around the first wiring in the second interlayer insulating film, and the non-porous region is at least between the first interlayer insulating film and the porous region. It is characterized by being formed in the middle.
　本発明の一側面に係る半導体装置によると、第２の層間絶縁膜のうち、第１の配線の周囲に位置する領域に多孔質領域を設けて、多孔質領域以外の領域に非多孔質領域を設けることにより、第１の層間絶縁膜と多孔質領域との間（言い換えれば、第２の層間絶縁膜のうち、下層との界面に位置する領域）に、非多孔質領域を設けることができる。そのため、第２の層間絶縁膜における下層との界面に空孔が存在することがなく、空孔により第２の層間絶縁膜と下層との密着性が低下することはないため、第２の層間絶縁膜と下層との界面に剥離が発生することを防止することができる。ここで、「下層」とは、第２の層間絶縁膜下に第２の層間絶縁膜と接して形成された層をいう。 According to the semiconductor device of one aspect of the present invention, a porous region is provided in a region located around the first wiring in the second interlayer insulating film, and a non-porous region is provided in a region other than the porous region. By providing the non-porous region between the first interlayer insulating film and the porous region (in other words, the region located at the interface with the lower layer in the second interlayer insulating film). it can. Therefore, there is no hole at the interface between the second interlayer insulating film and the lower layer, and the adhesion between the second interlayer insulating film and the lower layer is not reduced by the hole. Peeling can be prevented from occurring at the interface between the insulating film and the lower layer. Here, the “lower layer” means a layer formed in contact with the second interlayer insulating film under the second interlayer insulating film.
　それと共に、第２の層間絶縁膜のうち、第１の配線の周囲に位置する領域に、多孔質領域を設けることにより、第２の層間絶縁膜のうち、配線間容量の低減に効果的に貢献する領域に、多孔質領域を設けることができるため、配線間容量を効果的に低減させて、半導体装置の高速化を図ることができる。 At the same time, by providing a porous region in a region located around the first wiring in the second interlayer insulating film, it is effective in reducing the capacitance between the wirings in the second interlayer insulating film. Since the porous region can be provided in the contributing region, the inter-wiring capacitance can be effectively reduced and the speed of the semiconductor device can be increased.
　加えて、第２の層間絶縁膜のうち、比較的大きい配線間隔を有する第１の配線間の中央部に、非多孔質領域を設けることができる。これにより、第２の層間絶縁膜と上層との界面に剥離が発生することを防止することができる。ここで、「上層」とは、第２の層間絶縁膜上に第２の層間絶縁膜と接して形成された層をいう。 In addition, in the second interlayer insulating film, a non-porous region can be provided in the central portion between the first wirings having a relatively large wiring interval. Thereby, it is possible to prevent the occurrence of peeling at the interface between the second interlayer insulating film and the upper layer. Here, the “upper layer” means a layer formed on the second interlayer insulating film in contact with the second interlayer insulating film.
　本発明の一側面に係る半導体装置において、多孔質領域に含有される空孔は、ポロジェンが脱離されてなる空孔であり、非多孔質領域は、脱離されずに残存するポロジェンを含有していることが好ましい。 In the semiconductor device according to one aspect of the present invention, the pores contained in the porous region are pores formed by desorption of porogen, and the non-porous region contains porogen remaining without being desorbed. It is preferable.
　本発明の一側面に係る半導体装置において、多孔質領域は、第１の配線の側面から第１の距離までの範囲内で、且つ第１の配線の底面から第２の距離までの範囲内に形成されていることが好ましい。 In the semiconductor device according to one aspect of the present invention, the porous region is within a range from the side surface of the first wiring to the first distance and within a range from the bottom surface of the first wiring to the second distance. Preferably it is formed.
　本発明の一側面に係る半導体装置において、第１の距離は、最小配線間隔に相当する距離以上で、且つ最小配線間隔の１．５倍に相当する距離以下であり、第２の距離は、第１の配線の底面と第２の層間絶縁膜における第１の層間絶縁膜との界面との底面界面距離の約０．５倍に相当する距離であることが好ましい。 In the semiconductor device according to one aspect of the present invention, the first distance is not less than a distance corresponding to the minimum wiring interval and not more than a distance corresponding to 1.5 times the minimum wiring interval, and the second distance is It is preferable that the distance corresponds to about 0.5 times the bottom interface distance between the bottom surface of the first wiring and the interface between the first interlayer insulating film and the second interlayer insulating film.
　本発明の一側面に係る半導体装置において、非多孔質領域は、第２の層間絶縁膜における第１の層間絶縁膜との界面から、第３の距離までの範囲内に形成される界面領域と、互いに隣り合う第１の配線の配線間のうち、第１の距離の２倍に相当する間隔よりも大きい間隔を有する配線間の中央部に形成される配線間領域とを含み、第３の距離は、第１の配線の底面と第２の層間絶縁膜における第１の層間絶縁膜との界面との底面界面距離の約０．５倍に相当する距離であることが好ましい。 In the semiconductor device according to one aspect of the present invention, the non-porous region includes an interface region formed in a range from the interface between the second interlayer insulating film and the first interlayer insulating film to the third distance. An inter-wiring region formed in a central portion between the wirings having a spacing larger than a spacing corresponding to twice the first distance among the wirings of the first wirings adjacent to each other; The distance is preferably a distance corresponding to about 0.5 times the bottom interface distance between the bottom surface of the first wiring and the interface between the first interlayer insulating film and the second interlayer insulating film.
　このようにすると、非多孔質領域の界面領域により、既述の通り、第２の層間絶縁膜と下層との界面に剥離が発生することを防止すると共に、非多孔質領域の配線間領域により、既述の通り、第２の層間絶縁膜と上層との界面に剥離が発生することを防止することができる。 This prevents the occurrence of delamination at the interface between the second interlayer insulating film and the lower layer due to the interface region of the non-porous region, as described above, and the inter-wiring region of the non-porous region. As described above, it is possible to prevent peeling from occurring at the interface between the second interlayer insulating film and the upper layer.
　本発明の一側面に係る半導体装置において、第２の層間絶縁膜の下部領域に形成されたビアをさらに備え、ビアは、その下部領域が非多孔質領域を貫通し、その上部領域が多孔質領域を貫通して形成されていることが好ましい。 The semiconductor device according to one aspect of the present invention further includes a via formed in a lower region of the second interlayer insulating film, the via penetrating the non-porous region and the upper region being porous. It is preferable to be formed through the region.
　このようにすると、ビアの下部領域は非多孔質領域に囲まれるため、ビアの底面領域に空孔が存在することがなく、例えば、空孔内に捕獲される水分、又は空孔内に残留するエッチングガス等により、ビアの底面領域が酸化される、又はビアの底面領域が腐食されて、ビアの信頼性が低下することを防止することができる。 In this case, since the lower region of the via is surrounded by the non-porous region, there is no hole in the bottom region of the via, for example, moisture trapped in the hole or remaining in the hole It is possible to prevent the reliability of the via from being deteriorated due to the etching of the etching gas or the like to oxidize the bottom area of the via or to corrode the bottom area of the via.
　本発明の一側面に係る半導体装置において、第１の層間絶縁膜に形成された第２の配線をさらに備え、第１の配線は、ビアを介して、第２の配線と接続されていることが好ましい。 The semiconductor device according to one aspect of the present invention further includes a second wiring formed in the first interlayer insulating film, and the first wiring is connected to the second wiring through the via. Is preferred.
　このようにすると、第２の層間絶縁膜のうち、第２の配線と第１の配線間に位置する領域に、多孔質領域の膜厚と略同一の膜厚を有する非多孔質領域を設けることができる。そのため、第２の層間絶縁膜のうち、第２の配線と第１の配線間に位置する領域の機械的強度を確保する（具体的には例えば、第２の層間絶縁膜のうち、第２の配線と第１の配線間に位置する領域が、８ＧＰａ以上のヤング率を確保する）ことができるため、第２の層間絶縁膜のうち、第２の配線と第１の配線間に位置する領域に、割れが発生することを防止することができる。 In this case, a non-porous region having a film thickness substantially the same as the film thickness of the porous region is provided in a region located between the second wiring and the first wiring in the second interlayer insulating film. be able to. Therefore, the mechanical strength of the region located between the second wiring and the first wiring in the second interlayer insulating film is ensured (specifically, for example, the second interlayer insulating film includes the second interlayer insulating film. The region located between the first wiring and the first wiring can secure a Young's modulus of 8 GPa or more), so that it is located between the second wiring and the first wiring in the second interlayer insulating film. It is possible to prevent cracks from occurring in the region.
　本発明の一側面に係る半導体装置において、第２の層間絶縁膜のうち、第２の配線と第１の配線間に位置する領域のヤング率は、８ＧＰａ以上であることが好ましい。 In the semiconductor device according to one aspect of the present invention, the Young's modulus of a region located between the second wiring and the first wiring in the second interlayer insulating film is preferably 8 GPa or more.
　本発明の一側面に係る半導体装置において、第１の層間絶縁膜と第２の層間絶縁膜との間に形成されたバリア膜をさらに備え、ビアは、第２の層間絶縁膜の下部領域、及びバリア膜を貫通して形成されていることが好ましい。 The semiconductor device according to one aspect of the present invention further includes a barrier film formed between the first interlayer insulating film and the second interlayer insulating film, and the via includes a lower region of the second interlayer insulating film, And it is preferable to be formed through the barrier film.
　本発明の一側面に係る半導体装置において、第２の層間絶縁膜上に形成されたキャップ膜をさらに備え、第１の配線は、第２の層間絶縁膜の上部領域、及びキャップ膜に形成されていることが好ましい。 The semiconductor device according to one aspect of the present invention further includes a cap film formed on the second interlayer insulating film, and the first wiring is formed in the upper region of the second interlayer insulating film and the cap film. It is preferable.
　前記の目的を達成するために、本発明の一側面に係る半導体装置の製造方法は、半導体基板上に、第１の層間絶縁膜を形成する工程（ａ）と、第１の層間絶縁膜上に、ポロジェンを含有する第２の層間絶縁膜形成用膜を形成する工程（ｂ）と、第２の層間絶縁膜形成用膜上に、配線溝形成用溝が形成されたハードマスクを形成する工程（ｃ）と、ハードマスクを利用して、第２の層間絶縁膜形成用膜のうち、配線溝形成用溝の近傍に位置する領域に存在するポロジェンを脱離し、ポロジェンが脱離されてなる空孔を含有する多孔質領域と、脱離されずに残存するポロジェンを含有する非多孔質領域とで構成される第２の層間絶縁膜を形成する工程（ｄ）と、ハードマスクを利用して、第２の層間絶縁膜の上部領域に、第１の配線溝を形成する工程（ｅ）と、ハードマスクを除去した後、第１の配線溝内に第１の配線を形成する工程（ｆ）とを備え、工程（ｅ）において、第１の配線溝は、多孔質領域内に形成されることを特徴とする。 In order to achieve the above object, a method of manufacturing a semiconductor device according to one aspect of the present invention includes a step (a) of forming a first interlayer insulating film on a semiconductor substrate, and a step on the first interlayer insulating film. And (b) forming a second interlayer insulating film forming film containing porogen, and forming a hard mask having a wiring groove forming groove formed on the second interlayer insulating film forming film. Step (c) and using the hard mask, the porogen present in the region located in the vicinity of the trench for forming the trench is desorbed from the second interlayer insulating film, and the porogen is desorbed. A step (d) of forming a second interlayer insulating film composed of a porous region containing pores and a non-porous region containing porogen remaining without being desorbed, and using a hard mask Forming a first wiring trench in the upper region of the second interlayer insulating film. A step (e) and a step (f) of forming a first wiring in the first wiring groove after removing the hard mask. In the step (e), the first wiring groove is porous. It is formed in a region.
　本発明の一側面に係る半導体装置の製造方法によると、多孔質領域内に形成された第１の配線溝内に、第１の配線を形成することにより、第２の層間絶縁膜のうち、第１の配線の周囲に位置する領域に多孔質領域を設けて、多孔質領域以外の領域に非多孔質領域を設けることができる。これにより、第１の層間絶縁膜と多孔質領域との間（言い換えれば、第２の層間絶縁膜のうち、下層との界面に位置する領域）に、非多孔質領域を設けることができる。そのため、第２の層間絶縁膜における下層との界面に空孔が存在することがなく、空孔により第２の層間絶縁膜と下層との密着性が低下することはない。そのため、例えば、第１の配線の形成工程におけるＣＭＰ工程等の際に、第２の層間絶縁膜と下層との界面に剥離が発生することを防止することができる。 According to the method for manufacturing a semiconductor device according to one aspect of the present invention, by forming the first wiring in the first wiring groove formed in the porous region, the second interlayer insulating film, A porous region can be provided in a region located around the first wiring, and a non-porous region can be provided in a region other than the porous region. Thereby, a non-porous region can be provided between the first interlayer insulating film and the porous region (in other words, a region located at the interface with the lower layer in the second interlayer insulating film). Therefore, there is no hole at the interface with the lower layer in the second interlayer insulating film, and the adhesion between the second interlayer insulating film and the lower layer is not reduced by the hole. Therefore, for example, it is possible to prevent peeling at the interface between the second interlayer insulating film and the lower layer during the CMP process or the like in the first wiring formation process.
　それと共に、第２の層間絶縁膜のうち、第１の配線の周囲に位置する領域に、多孔質領域を設けることにより、第２の層間絶縁膜のうち、配線間容量の低減に効果的に貢献する領域に、多孔質領域を設けることができるため、配線間容量を効果的に低減させて、半導体装置の高速化を図ることができる。 At the same time, by providing a porous region in a region located around the first wiring in the second interlayer insulating film, it is effective in reducing the capacitance between the wirings in the second interlayer insulating film. Since the porous region can be provided in the contributing region, the inter-wiring capacitance can be effectively reduced and the speed of the semiconductor device can be increased.
　加えて、第２の層間絶縁膜のうち、比較的大きい配線間隔を有する第１の配線間の中央部に、非多孔質領域を設けることができる。これにより、例えば、第１の配線の形成工程におけるＣＭＰ工程等の際に、第２の層間絶縁膜と上層との界面に剥離が発生することを防止することができる。 In addition, in the second interlayer insulating film, a non-porous region can be provided in the central portion between the first wirings having a relatively large wiring interval. Thereby, for example, it is possible to prevent the separation at the interface between the second interlayer insulating film and the upper layer during the CMP process or the like in the first wiring formation process.
　本発明の一側面に係る半導体装置の製造方法において、工程（ｂ）において、第２の層間絶縁膜形成用膜に含有されるポロジェンは、紫外線、又は電子線の照射により脱離するポロジェンであり、工程（ｃ）において、ハードマスクは、紫外線、又は電子線を反射させる金属膜からなり、工程（ｄ）は、半導体基板上に、紫外線、又は電子線を照射する工程であることが好ましい。 In the method for manufacturing a semiconductor device according to one aspect of the present invention, in the step (b), the porogen contained in the second interlayer insulating film forming film is a porogen that is desorbed by irradiation with ultraviolet rays or electron beams. In the step (c), the hard mask is made of a metal film that reflects ultraviolet rays or electron beams, and the step (d) is preferably a step of irradiating the semiconductor substrate with ultraviolet rays or electron beams.
　このようにすると、紫外線、又は電子線のうちハードマスクに照射される紫外線、又は電子線は、ハードマスクにより反射されて、第２の層間絶縁膜形成用膜のうち、配線溝形成用溝の近傍に位置する領域に、紫外線、又は電子線が照射される。 If it does in this way, ultraviolet rays or an electron beam with which an ultraviolet ray or an electron beam is irradiated to a hard mask will be reflected by a hard mask, and among the 2nd interlayer insulation film formation films, it will be a wiring groove formation groove. A region located in the vicinity is irradiated with ultraviolet rays or an electron beam.
　本発明の一側面に係る半導体装置の製造方法において、工程（ｄ）は、半導体基板上に、半導体基板の主面に対して垂直な方向に、第１の紫外線、又は第１の電子線を照射する工程（ｄ１）と、半導体基板上に、半導体基板の主面に対して傾斜する方向に、第２の紫外線、又は第２の電子線を照射する工程（ｄ２）とを含むことが好ましい。 In the method for manufacturing a semiconductor device according to one aspect of the present invention, in the step (d), the first ultraviolet ray or the first electron beam is applied on the semiconductor substrate in a direction perpendicular to the main surface of the semiconductor substrate. It is preferable to include a step (d1) of irradiating and a step (d2) of irradiating the second ultraviolet ray or the second electron beam on the semiconductor substrate in a direction inclined with respect to the main surface of the semiconductor substrate. .
　本発明の一側面に係る半導体装置の製造方法において、紫外線、又は電子線を反射させる金属膜の材料は、Ｔｉ、ＴｉＮ、Ｔａ、ＴａＮ、Ｗ、及びＷＮからなる群から選択される１種類、又は複数種類の金属材料であることが好ましい。 In the method for manufacturing a semiconductor device according to one aspect of the present invention, the material of the metal film that reflects ultraviolet rays or electron beams is one type selected from the group consisting of Ti, TiN, Ta, TaN, W, and WN, Or it is preferable that they are a multiple types of metal material.
　本発明の一側面に係る半導体装置の製造方法において、工程（ｂ）において、第２の層間絶縁膜形成用膜に含有されるポロジェンは、紫外線、又は電子線の照射により脱離するポロジェンであり、工程（ｃ）において、ハードマスクは、紫外線、又は電子線を吸収する絶縁膜からなり、工程（ｄ）は、半導体基板上に、紫外線、又は電子線を照射する工程であることが好ましい。 In the method for manufacturing a semiconductor device according to one aspect of the present invention, in the step (b), the porogen contained in the second interlayer insulating film forming film is a porogen that is desorbed by irradiation with ultraviolet rays or electron beams. In the step (c), the hard mask is made of an insulating film that absorbs ultraviolet rays or electron beams, and the step (d) is preferably a step of irradiating the semiconductor substrate with ultraviolet rays or electron beams.
　このようにすると、紫外線、又は電子線のうちハードマスクに照射される紫外線、又は電子線は、ハードマスクに吸収されて、第２の層間絶縁膜形成用膜のうち、配線溝形成用溝の近傍に位置する領域に、紫外線、又は電子線が照射される。 If it does in this way, ultraviolet rays or an electron beam irradiated to a hard mask among ultraviolet rays or an electron beam will be absorbed by a hard mask, and it will become a groove | channel of wiring groove | channel formation groove | channel among 2nd interlayer insulation film formation films. A region located in the vicinity is irradiated with ultraviolet rays or an electron beam.
　本発明の一側面に係る半導体装置の製造方法において、紫外線、又は電子線を吸収する絶縁膜の材料は、ＳｉＣＮ、ＳｉＣＯ、ＳｉＣＨ、ＳｉＯＮ、ＳｉＯ2、及びＳｉＮからなる群から選択される１種類、又は複数種類の絶縁材料であることが好ましい。 In the method of manufacturing a semiconductor device according to one aspect of the present invention, the material of the insulating film that absorbs ultraviolet rays or electron beams is one type selected from the group consisting of SiCN, SiCO, SiCH, SiON, SiO 2 , and SiN. Or a plurality of types of insulating materials.
　本発明の一側面に係る半導体装置の製造方法において、工程（ｂ）において、第２の層間絶縁膜形成用膜に含有されるポロジェンは、熱処理により脱離するポロジェンであり、工程（ｃ）において、ハードマスクは、ポロジェンが含まれない第１の層間絶縁膜に比べて密度の高い膜からなり、工程（ｄ）は、半導体基板上の全面に対し、熱処理を施す工程であることが好ましい。 In the method for manufacturing a semiconductor device according to one aspect of the present invention, in the step (b), the porogen contained in the second interlayer insulating film forming film is a porogen that is desorbed by heat treatment, and in the step (c) The hard mask is made of a film having a higher density than the first interlayer insulating film containing no porogen, and the step (d) is preferably a step of performing heat treatment on the entire surface of the semiconductor substrate.
　本発明の一側面に係る半導体装置の製造方法において、ハードマスクの材料は、Ｔｉ、ＴｉＮ、Ｔａ、ＴａＮ、Ｗ、及びＷＮからなる金属材料群、並びにＳｉＣＮ、ＳｉＣＯ、ＳｉＣＨ、ＳｉＯＮ、ＳｉＯ2、及びＳｉＮからなる絶縁材料群から選択される１種類、又は複数種類の材料であることが好ましい。 In the method for manufacturing a semiconductor device according to one aspect of the present invention, the hard mask material includes a metal material group consisting of Ti, TiN, Ta, TaN, W, and WN, and SiCN, SiCO, SiCH, SiON, SiO 2 , And one or more types of materials selected from the insulating material group consisting of SiN.
　本発明の一側面に係る半導体装置の製造方法において、工程（ｅ）は、第２の層間絶縁膜の下部領域にビアホールを形成する工程をさらに含み、工程（ｆ）は、ビアホール内にビアを形成する工程をさらに含み、工程（ｅ）において、ビアホールは、その下部領域が非多孔質領域を貫通し、その上部領域が多孔質領域を貫通して形成されることが好ましい。 In the method for manufacturing a semiconductor device according to one aspect of the present invention, the step (e) further includes a step of forming a via hole in a lower region of the second interlayer insulating film, and the step (f) includes forming a via in the via hole. In the step (e), the via hole is preferably formed so that the lower region penetrates the non-porous region and the upper region penetrates the porous region.
　このようにすると、ビアの下部領域は非多孔質領域に囲まれるため、ビアの底面領域に空孔が存在することがなく、例えば、空孔内に捕獲される水分、又は空孔内に残留するエッチングガス等により、ビアの底面領域が酸化される、又はビアの底面領域が腐食されて、ビアの信頼性が低下することを防止することができる。 In this case, since the lower region of the via is surrounded by the non-porous region, there is no hole in the bottom region of the via, for example, moisture trapped in the hole or remaining in the hole It is possible to prevent the reliability of the via from being deteriorated due to the etching of the etching gas or the like to oxidize the bottom area of the via or to corrode the bottom area of the via.
　本発明の一側面に係る半導体装置の製造方法において、工程（ａ）の後で工程（ｂ）の前に、第１の層間絶縁膜に第２の配線溝を形成した後、第２の配線溝内に第２の配線を形成する工程（ｇ）をさらに備えていることが好ましい。 In the method for manufacturing a semiconductor device according to one aspect of the present invention, after the step (a) and before the step (b), the second wiring trench is formed in the first interlayer insulating film, and then the second wiring is formed. Preferably, the method further includes a step (g) of forming the second wiring in the groove.
　このようにすると、第２の層間絶縁膜のうち、第２の配線と第１の配線間に位置する領域に、多孔質領域の膜厚と略同一の膜厚を有する非多孔質領域を設けることができる。そのため、第２の層間絶縁膜のうち、第２の配線と第１の配線間に位置する領域の機械的強度を確保することができるため、例えば、第１の配線の形成工程の後に行うワイヤボンディング工程、又はプローブ検査工程等の際に、第２の層間絶縁膜のうち、第２の配線と第１の配線間に位置する領域に、割れが発生することを防止することができる。 In this case, a non-porous region having a film thickness substantially the same as the film thickness of the porous region is provided in a region located between the second wiring and the first wiring in the second interlayer insulating film. be able to. Therefore, the mechanical strength of the region located between the second wiring and the first wiring in the second interlayer insulating film can be ensured. For example, the wire to be formed after the first wiring forming step In the bonding process, the probe inspection process, or the like, it is possible to prevent a crack from occurring in a region located between the second wiring and the first wiring in the second interlayer insulating film.
　本発明の一側面に係る半導体装置の製造方法において、工程（ｇ）の後で工程（ｂ）の前に、第１の層間絶縁膜、及び第２の配線の上にバリア膜を形成する工程（ｈ）をさらに備え、工程（ｂ）において、第２の層間絶縁膜形成用膜は、バリア膜上に形成され、工程（ｅ）において、ビアホールは、第２の層間絶縁膜の下部領域、及びバリア膜を貫通して形成されることが好ましい。 In the method for manufacturing a semiconductor device according to one aspect of the present invention, a step of forming a barrier film on the first interlayer insulating film and the second wiring after the step (g) and before the step (b) (H), and in step (b), the second interlayer insulating film forming film is formed on the barrier film, and in step (e), the via hole is formed in a lower region of the second interlayer insulating film, And it is preferable to be formed through the barrier film.
　本発明の一側面に係る半導体装置の製造方法において、工程（ｂ）の後で工程（ｃ）の前に、第２の層間絶縁膜形成用膜上に、キャップ膜を形成する工程（ｉ）をさらに備え、工程（ｃ）において、第２の層間絶縁膜形成用膜上に、溝が形成されたキャップ膜、及び溝と連通する配線溝形成用溝が形成されたハードマスクが順次形成され、工程（ｅ）において、第１の配線溝は、第２の層間絶縁膜の上部領域、及びキャップ膜に形成されることが好ましい。 In the method for manufacturing a semiconductor device according to one aspect of the present invention, a step (i) of forming a cap film on the second interlayer insulating film formation film after the step (b) and before the step (c). In the step (c), a cap film having a groove and a hard mask having a groove for forming a wiring groove communicating with the groove are sequentially formed on the second interlayer insulating film forming film. In the step (e), the first wiring trench is preferably formed in the upper region of the second interlayer insulating film and the cap film.
　本発明の一側面に係る半導体装置の製造方法において、工程（ｃ）は、キャップ膜上にハードマスクを形成する工程（ｃ１）と、工程（ｃ１）の後に、ハードマスクに配線溝形成用溝を形成すると共に、キャップ膜に溝を形成する工程（ｃ２）とを含むことが好ましい。 In the method for manufacturing a semiconductor device according to one aspect of the present invention, the step (c) includes a step (c1) of forming a hard mask on the cap film, and a trench for forming a wiring groove on the hard mask after the step (c1). And a step (c2) of forming a groove in the cap film.
　本発明の一側面に係る半導体装置及びその製造方法によると、第２の層間絶縁膜のうち、第１の配線の周囲に位置する領域に多孔質領域を設けて、多孔質領域以外の領域に非多孔質領域を設けることにより、第１の層間絶縁膜と多孔質領域との間（言い換えれば、第２の層間絶縁膜のうち、下層との界面に位置する領域）に、非多孔質領域を設けることができる。そのため、第２の層間絶縁膜における下層との界面に空孔が存在することがなく、空孔により第２の層間絶縁膜と下層との密着性が低下することはないため、第２の層間絶縁膜と下層との界面に剥離が発生することを防止することができる。 According to the semiconductor device and the manufacturing method thereof according to one aspect of the present invention, a porous region is provided in a region located around the first wiring in the second interlayer insulating film, and the region other than the porous region is provided. By providing the non-porous region, the non-porous region is provided between the first interlayer insulating film and the porous region (in other words, the region located at the interface with the lower layer in the second interlayer insulating film). Can be provided. Therefore, there is no hole at the interface between the second interlayer insulating film and the lower layer, and the adhesion between the second interlayer insulating film and the lower layer is not reduced by the hole. Peeling can be prevented from occurring at the interface between the insulating film and the lower layer.
　それと共に、第２の層間絶縁膜のうち、第１の配線の周囲に位置する領域に、多孔質領域を設けることにより、第２の層間絶縁膜のうち、配線間容量の低減に効果的に貢献する領域に、多孔質領域を設けることができるため、配線間容量を効果的に低減させて、半導体装置の高速化を図ることができる。 At the same time, by providing a porous region in a region located around the first wiring in the second interlayer insulating film, it is effective in reducing the capacitance between the wirings in the second interlayer insulating film. Since the porous region can be provided in the contributing region, the inter-wiring capacitance can be effectively reduced and the speed of the semiconductor device can be increased.
　加えて、第２の層間絶縁膜のうち、比較的大きい配線間隔を有する第１の配線間の中央部に、非多孔質領域を設けることができる。これにより、第２の層間絶縁膜と上層との界面に剥離が発生することを防止することができる。 In addition, in the second interlayer insulating film, a non-porous region can be provided in the central portion between the first wirings having a relatively large wiring interval. Thereby, it is possible to prevent the occurrence of peeling at the interface between the second interlayer insulating film and the upper layer.
図１(a) 及び(b) は、本発明の一実施形態に係る半導体装置の構成を示す図である。FIGS. 1A and 1B are diagrams showing a configuration of a semiconductor device according to an embodiment of the present invention. 図２は、本発明の一実施形態に係る半導体装置の構成を示す断面図である。FIG. 2 is a cross-sectional view showing a configuration of a semiconductor device according to an embodiment of the present invention. 図３(a) ～(c) は、本発明の一実施形態に係る半導体装置の製造方法を工程順に示す要部工程断面図である。FIGS. 3A to 3C are principal part process cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of processes. 図４(a) ～(c) は、本発明の一実施形態に係る半導体装置の製造方法を工程順に示す要部工程断面図である。FIGS. 4A to 4C are principal part process cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of processes. 図５(a) ～(c) は、本発明の一実施形態に係る半導体装置の製造方法を工程順に示す要部工程断面図である。FIGS. 5A to 5C are principal part process cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of processes. 図６(a) 及び(b) は、本発明の一実施形態の具体例に係る半導体装置の構成を示す断面図である。FIGS. 6A and 6B are cross-sectional views showing a configuration of a semiconductor device according to a specific example of an embodiment of the present invention. 図７は、従来の半導体装置の構成を示す断面図である。FIG. 7 is a cross-sectional view showing a configuration of a conventional semiconductor device.
　以下に、本発明の実施形態について、図面を参照しながら説明する。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
　（一実施形態）
　以下に、本発明の一実施形態に係る半導体装置及びその製造方法について、図１(a) 及び(b) 、図２、図３(a) ～(c) 、図４(a) ～(c) 、及び図５(a) ～(c) を参照しながら説明する。 (One embodiment)
Hereinafter, a semiconductor device and a manufacturing method thereof according to an embodiment of the present invention will be described with reference to FIGS. 1 (a) and (b), FIG. 2, FIGS. 3 (a) to (c), and FIGS. ) And FIGS. 5 (a) to 5 (c).
　以下に、本発明の一実施形態に係る半導体装置の構成について、図１(a) 及び(b) を参照しながら説明する。図１(a) 及び(b) は、本発明の一実施形態に係る半導体装置の構成を示す図であり、具体的には、図１(a) は平面図であり、図１(b) は図１(a) に示すIb-Ib線における断面図である。 Hereinafter, the configuration of a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. 1 (a) and 1 (b). FIGS. 1A and 1B are diagrams showing a configuration of a semiconductor device according to an embodiment of the present invention. Specifically, FIG. 1A is a plan view, and FIG. FIG. 2 is a cross-sectional view taken along line Ib-Ib shown in FIG.
　図１(a) に示すように、半導体基板（図示省略）上には、第１の層間絶縁膜（図１(b)：１０参照）、バリア膜（図１(b)：１３参照）、第２の層間絶縁膜（図１(b)：１４参照）、及びキャップ膜１５が順次形成されている。第２の層間絶縁膜の下部領域には、ビア２０が形成され、第２の層間絶縁膜の上部領域、及びキャップ膜１５には、ビア２０と接続する配線２１が形成されている。 As shown in FIG. 1A, on the semiconductor substrate (not shown), a first interlayer insulating film (see FIG. 1B: 10), a barrier film (see FIG. 1B: 13), A second interlayer insulating film (see FIG. 1B: 14) and a cap film 15 are sequentially formed. A via 20 is formed in the lower region of the second interlayer insulating film, and a wiring 21 connected to the via 20 is formed in the upper region of the second interlayer insulating film and the cap film 15.
　図１(b) に示すように、本実施形態に係る半導体装置は、半導体基板（図示省略）上に形成された第１の層間絶縁膜１０と、第１の層間絶縁膜１０に形成された下層配線（第２の配線）１２と、第１の層間絶縁膜１０及び下層配線１２の上に形成されたバリア膜１３と、バリア膜１３上に形成された第２の層間絶縁膜１４と、第２の層間絶縁膜１４上に形成されたキャップ膜１５と、バリア膜１３及び第２の層間絶縁膜１４の下部領域に形成され、下層配線１２と接続するビア２０と、第２の層間絶縁膜１４の上部領域及びキャップ膜１５に形成され、ビア２０と接続する上層配線（第１の配線）２１とを備えている。 As shown in FIG. 1B, the semiconductor device according to this embodiment is formed on the first interlayer insulating film 10 formed on the semiconductor substrate (not shown) and the first interlayer insulating film 10. A lower layer wiring (second wiring) 12, a barrier film 13 formed on the first interlayer insulating film 10 and the lower layer wiring 12, a second interlayer insulating film 14 formed on the barrier film 13, A cap film 15 formed on the second interlayer insulating film 14, a barrier film 13, a via 20 connected to the lower layer wiring 12 formed in a lower region of the second interlayer insulating film 14, and a second interlayer insulating film An upper layer wiring (first wiring) 21 formed in the upper region of the film 14 and the cap film 15 and connected to the via 20 is provided.
　ここで、下層配線１２は、下層配線溝１１の底面及び側面に形成されたバリアメタル膜１２ａと、下層配線溝１１内にバリアメタル膜１２ａを介して埋め込まれた導電膜１２ｂとからなる。ビア２０は、ビアホール１８の底面及び側面に形成されたバリアメタル膜２０ａと、ビアホール１８内にバリアメタル膜２０ａを介して埋め込まれた導電膜２０ｂとからなる。上層配線２１は、上層配線溝１９の底面及び側面に形成されたバリアメタル膜２１ａと、上層配線溝１９内にバリアメタル膜２１ａを介して埋め込まれた導電膜２１ｂとからなる。 Here, the lower layer wiring 12 includes a barrier metal film 12a formed on the bottom and side surfaces of the lower layer wiring groove 11, and a conductive film 12b embedded in the lower layer wiring groove 11 via the barrier metal film 12a. The via 20 includes a barrier metal film 20a formed on the bottom and side surfaces of the via hole 18 and a conductive film 20b embedded in the via hole 18 via the barrier metal film 20a. The upper layer wiring 21 includes a barrier metal film 21a formed on the bottom and side surfaces of the upper layer wiring groove 19 and a conductive film 21b embedded in the upper layer wiring groove 19 via the barrier metal film 21a.
　第２の層間絶縁膜１４は、図１(b) に示すように、ポロジェン１４ａが脱離されてなる空孔１４ｂを含有する多孔質領域１４Ｂと、脱離されずに残存するポロジェン１４ａを含有する非多孔質領域１４Ａとで構成される。 As shown in FIG. 1B, the second interlayer insulating film 14 includes a porous region 14B containing pores 14b from which porogens 14a are desorbed and porogen 14a remaining without being desorbed. It is comprised with the non-porous area | region 14A.
　多孔質領域１４Ｂは、図１(b) に示すように、第２の層間絶縁膜１４のうち、上層配線２１の周囲に位置する領域に形成されている。詳細には、多孔質領域１４Ｂは、図２に示すように、上層配線２１の側面から第１の距離Ｄs（図２参照）までの範囲内で、且つ上層配線２１の底面から第２の距離Ｄb（図２参照）までの範囲内に形成される。ここで、第１の距離Ｄsは、上層配線２１の側面に対して垂直な方向に沿った距離であり、第２の距離Ｄbは、上層配線２１の底面に対して垂直な方向に沿った距離である。なお、図２は、図１(b) に示す図と同一の図である。 The porous region 14B is formed in a region located around the upper layer wiring 21 in the second interlayer insulating film 14, as shown in FIG. Specifically, as shown in FIG. 2, the porous region 14 </ b> B is within the range from the side surface of the upper layer wiring 21 to the first distance Ds (see FIG. 2) and from the bottom surface of the upper layer wiring 21 to the second distance. It is formed within the range up to Db (see FIG. 2). Here, the first distance Ds is a distance along a direction perpendicular to the side surface of the upper layer wiring 21, and the second distance Db is a distance along a direction perpendicular to the bottom surface of the upper layer wiring 21. It is. FIG. 2 is the same diagram as that shown in FIG.
　ここで、第１の距離Ｄｓは、最小配線間隔Ｓminに相当する距離以上で、且つ最小配線間隔Ｓminの１．５倍に相当する距離以下である（Ｓmin≦Ｄs≦Ｓmin×１．５）ことが好ましい。また、第２の距離Ｄbは、上層配線２１の底面と第２の層間絶縁膜１４におけるバリア膜１３との界面との底面界面距離Ｄbi（図２参照）の０．５倍に相当する距離である（Ｄb＝Ｄbi×０．５）ことが好ましい。ここで、「最小配線間隔Ｓmin」とは、互いに隣り合う上層配線２１の配線間隔のうち、最も小さい間隔に相当する。 Here, the first distance Ds is not less than a distance corresponding to the minimum wiring interval Smin and not more than a distance corresponding to 1.5 times the minimum wiring interval Smin (Smin ≦ Ds ≦ Smin × 1.5). Is preferred. The second distance Db is a distance corresponding to 0.5 times the bottom surface interface distance Dbi (see FIG. 2) between the bottom surface of the upper wiring 21 and the interface between the second interlayer insulating film 14 and the barrier film 13. It is preferable (Db = Dbi × 0.5). Here, the “minimum wiring interval Smin” corresponds to the smallest interval among the wiring intervals of the upper layer wirings 21 adjacent to each other.
　言い換えれば、非多孔質領域１４Ａは、バリア膜１３と多孔質領域１４Ｂとの間、及び互いに隣り合う多孔質領域１４Ｂの間（特に、互いに隣り合う多孔質領域１４Ｂのうち、互いに重なり合わずに離間する多孔質領域１４Ｂの間）に介在して形成されている。詳細には、非多孔質領域１４Ａは、図２に示すように、第２の層間絶縁膜１４におけるバリア膜１３との界面から、第３の距離Ｄi（図２参照）までの範囲内に形成される界面領域１４Ａiと、互いに隣り合う上層配線２１の配線間のうち、第１の距離Ｄsの２倍に相当する間隔よりも大きい間隔を有する配線間の中央部に形成される配線間領域１４Ａsとを含む。ここで、第３の距離Ｄiは、底面界面距離Ｄbiの０．５倍に相当する距離である（Ｄi＝Ｄbi×０．５）ことが好ましい。即ち、第３の距離Ｄiは、第２の距離Ｄbと略同一であることが好ましい。 In other words, the non-porous region 14A is not overlapped between the barrier film 13 and the porous region 14B and between the porous regions 14B adjacent to each other (particularly, the porous regions 14B adjacent to each other do not overlap each other). Between the spaced apart porous regions 14B). Specifically, as shown in FIG. 2, the non-porous region 14A is formed within a range from the interface between the second interlayer insulating film 14 and the barrier film 13 to the third distance Di (see FIG. 2). The inter-wiring region 14As formed in the central portion between the interfacial region 14Ai and the wiring of the upper-layer wiring 21 adjacent to each other having a spacing larger than the spacing corresponding to twice the first distance Ds. Including. Here, the third distance Di is preferably a distance corresponding to 0.5 times the bottom interface distance Dbi (Di = Dbi × 0.5). In other words, the third distance Di is preferably substantially the same as the second distance Db.
　非多孔質領域１４Ａの配線間領域１４Ａsは、互いに隣り合う上層配線２１の配線間のうち、第１の距離Ｄsの２倍に相当する間隔よりも大きい間隔（＞Ｄs×２）を有する配線間には形成される一方、第１の距離Ｄsの２倍に相当する間隔以下の間隔（≦Ｄs×２）を有する配線間には形成されない。 The inter-wiring region 14As of the non-porous region 14A is an inter-wiring region having an interval (> Ds × 2) larger than an interval corresponding to twice the first distance Ds among the wirings of the upper layer wirings 21 adjacent to each other. Is formed between the wirings having an interval (≦ Ds × 2) that is equal to or less than an interval corresponding to twice the first distance Ds.
　第２の層間絶縁膜１４において、ビア２０は、図１(b) に示すように、その下部領域が非多孔質領域１４Ａの界面領域１４Ａiを貫通し、その上部領域が多孔質領域１４Ｂの底面領域を貫通して形成される。また、第２の層間絶縁膜１４において、上層配線２１は、多孔質領域１４Ｂ内に形成される。ここで、「底面領域」とは、多孔質領域１４Ｂのうち、上層配線２１の底面から第２の距離Ｄb（図２参照）までの範囲内に形成される領域をいう。 In the second interlayer insulating film 14, the via 20 has a lower region penetrating the interface region 14Ai of the non-porous region 14A and an upper region of the via 20 at the bottom surface of the porous region 14B, as shown in FIG. It is formed through the region. In the second interlayer insulating film 14, the upper layer wiring 21 is formed in the porous region 14B. Here, the “bottom surface region” refers to a region formed in the range from the bottom surface of the upper layer wiring 21 to the second distance Db (see FIG. 2) in the porous region 14B.
　第２の層間絶縁膜１４のうち、下層配線１２と上層配線２１間に位置する領域には、多孔質領域１４Ｂの底面領域の膜厚（図２：Ｄb参照）と略同一の膜厚（図２：Ｄi参照）を有する非多孔質領域１４Ａの界面領域１４Ａiが形成されている。ここで、第２の層間絶縁膜１４のうち、下層配線１２と上層配線２１間に位置する領域のヤング率は、８ＧＰａ以上であることが好ましい。 In the region between the lower layer wiring 12 and the upper layer wiring 21 in the second interlayer insulating film 14, the film thickness (see FIG. 2: Db) substantially the same as the film thickness of the bottom region of the porous region 14B (see FIG. 2). 2: Refer to Di) to form an interface region 14Ai of the non-porous region 14A. Here, it is preferable that the Young's modulus of the region located between the lower layer wiring 12 and the upper layer wiring 21 in the second interlayer insulating film 14 is 8 GPa or more.
　以下に、本発明の一実施形態に係る半導体装置の製造方法について、図３(a) ～(c) 、図４(a) ～(c) 、及び図５(a) ～(c) を参照しながら説明する。図３(a) ～図５(c) は、本発明の一実施形態に係る半導体装置の製造方法を工程順に示す要部工程断面図である。 Hereinafter, with reference to FIGS. 3 (a) to (c), FIGS. 4 (a) to (c), and FIGS. 5 (a) to (c), with respect to a method for manufacturing a semiconductor device according to an embodiment of the present invention. While explaining. FIG. 3A to FIG. 5C are cross-sectional views of relevant steps showing a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps.
　まず、図３(a) に示すように、半導体基板（図示省略）上に、例えば、比誘電率が３．０の炭素含有シリコン酸化膜（ＳｉＯＣ（Ｈ）膜）からなる第１の層間絶縁膜１０を形成する。続いて、フォトリソグラフィー法により、第１の層間絶縁膜１０上に、下層配線溝パターンを持つレジストパターン（図示省略）を形成した後、該レジストパターンをマスクに用いて、第１の層間絶縁膜１０に対してドライエッチングを行い、第１の層間絶縁膜１０に下層配線溝１１を形成する。続いて、該レジストパターンを除去する。 First, as shown in FIG. 3A, a first interlayer insulation made of, for example, a carbon-containing silicon oxide film (SiOC (H) film) having a relative dielectric constant of 3.0 on a semiconductor substrate (not shown). A film 10 is formed. Subsequently, after a resist pattern (not shown) having a lower wiring groove pattern is formed on the first interlayer insulating film 10 by photolithography, the first interlayer insulating film is used using the resist pattern as a mask. 10 is dry-etched to form a lower wiring trench 11 in the first interlayer insulating film 10. Subsequently, the resist pattern is removed.
　次に、スパッタ法により、第１の層間絶縁膜１０上、並びに下層配線溝１１の底面及び側面に、例えばタンタル膜（Ｔａ膜）と窒化タンタル膜（ＴａＮ膜）とが順次積層されてなるバリアメタル膜を堆積する。続いて、スパッタ法により、バリアメタル膜上に、例えば銅を含むシード膜を形成した後、電解めっき法により、シード膜上に、下層配線溝１１内を埋め込むように、例えば銅を含むめっき膜を堆積する。続いて、ＣＭＰ（Ｃhemical Ｍechanical Ｐolishing）法により、めっき膜、シード膜、及びバリアメタル膜のうち、下層配線溝１１外に形成された部分を順次除去する。このようにして、下層配線溝１１内に、バリアメタル膜１２ａを介して、銅を含む導電膜１２ｂが埋め込まれてなる下層配線１２を形成する。ここで、図３(a) において、導電膜１２ｂのうち、シード膜とめっき膜との境界線は、図示が困難なため図示を省略する。 Next, a barrier in which, for example, a tantalum film (Ta film) and a tantalum nitride film (TaN film) are sequentially stacked on the first interlayer insulating film 10 and on the bottom and side surfaces of the lower wiring trench 11 by sputtering. Deposit metal film. Subsequently, after a seed film containing, for example, copper is formed on the barrier metal film by sputtering, a plating film containing, for example, copper is buried by embedding the lower wiring groove 11 on the seed film by electrolytic plating. To deposit. Subsequently, portions of the plating film, the seed film, and the barrier metal film formed outside the lower wiring trench 11 are sequentially removed by a CMP (Chemical-Mechanical-Polishing) method. In this way, the lower layer wiring 12 is formed in which the conductive film 12b containing copper is buried in the lower layer wiring trench 11 via the barrier metal film 12a. Here, in FIG. 3A, the boundary line between the seed film and the plating film in the conductive film 12b is not shown because it is difficult to show.
　次に、図３(b) に示すように、プラズマＣＶＤ（Ｃhemical Ｖapor Ｄeposition）法により、第１の層間絶縁膜１０、及び下層配線１２の上に、例えば膜厚が４０ｎｍのシリコン炭窒化膜（ＳｉＣＮ膜）からなるバリア膜１３を堆積する。ここで、プラズマＣＶＤ法によるバリア膜１３の堆積条件としては、次に示す条件が挙げられる。例えば、温度が４００℃の下、原料ガスとして、テトラメチルシラン（Ｓｉ(ＣＨ3)4）ガス、及びアンモニア（ＮＨ3）ガスを用い、希釈ガスとして、ヘリウム（Ｈｅ）ガスを用いて、プラズマＣＶＤ法によるバリア膜１３の堆積を行う。またここで、バリア膜１３は、その密度が、例えば１．８ｇ／ｃｍ3であることが好ましく、その屈折率が、例えば１．８～２．２（波長６３３ｎｍ）であることが好ましい。 Next, as shown in FIG. 3B, a silicon carbonitride film (for example, having a film thickness of 40 nm) is formed on the first interlayer insulating film 10 and the lower layer wiring 12 by plasma CVD (Chemical Vapor Deposition). A barrier film 13 made of SiCN film is deposited. Here, as the deposition conditions of the barrier film 13 by the plasma CVD method, the following conditions may be mentioned. For example, under a temperature of 400 ° C., tetramethylsilane (Si (CH 3 ) 4 ) gas and ammonia (NH 3 ) gas are used as the source gas, and helium (He) gas is used as the dilution gas. The barrier film 13 is deposited by the CVD method. Here, the barrier film 13 preferably has a density of, for example, 1.8 g / cm 3 , and preferably has a refractive index of, for example, 1.8 to 2.2 (wavelength 633 nm).
　続いて、プラズマＣＶＤ法、又はスピン塗布法により、バリア膜１３上に、例えば、紫外線（ＵＶ：ultraviolet）の照射により脱離するポロジェン１４ａを含有し、膜厚が２００ｎｍのＳｉＯＣ（Ｈ）膜からなる第２の層間絶縁膜形成用膜１４Ｘを堆積する。ここで、第２の層間絶縁膜形成用膜１４Ｘの堆積方法としては、プラズマＣＶＤ法を用いることがより好ましい。 Subsequently, from the SiOC (H) film having a film thickness of 200 nm containing the porogen 14a desorbed by, for example, ultraviolet (UV) irradiation on the barrier film 13 by the plasma CVD method or the spin coating method. A second interlayer insulating film forming film 14X is deposited. Here, as a deposition method of the second interlayer insulating film forming film 14X, it is more preferable to use a plasma CVD method.
　次に、図３(c) に示すように、プラズマＣＶＤ法により、第２の層間絶縁膜形成用膜１４Ｘ上に、例えば、膜厚が４０ｎｍのＳｉＯＣ（Ｈ）膜からなるキャップ膜１５を堆積した後、スパッタ法により、キャップ膜１５上に、例えば、膜厚が３０ｎｍのＴｉＮ膜等の紫外線を反射させる金属膜からなるハードマスク１６を堆積する。 Next, as shown in FIG. 3C, a cap film 15 made of, for example, a SiOC (H) film having a thickness of 40 nm is deposited on the second interlayer insulating film forming film 14X by plasma CVD. Thereafter, a hard mask 16 made of a metal film that reflects ultraviolet rays, such as a TiN film having a film thickness of 30 nm, is deposited on the cap film 15 by sputtering.
　次に、図４(a) に示すように、フォトリソグラフィー法により、ハードマスク１６上に、上層配線溝パターンを持つレジストパターン（図示省略）を形成する。続いて、該レジストパターンをマスクに用いて、ハードマスク１６、及びキャップ膜１５に対してドライエッチングを順次行い、ハードマスク１６に上層配線溝形成用溝１６ｙを形成すると共にキャップ膜１５に溝１５ｙを形成し、ハードマスク１６及びキャップ膜１５を貫通し、第２の層間絶縁膜形成用膜１４Ｘの上面を露出させる溝１６Ｙを形成する。続いて、該レジストパターンを除去する。このようにして、第２の層間絶縁膜形成用膜１４Ｘ上に、溝１５ｙが形成されたキャップ膜１５、及び溝１５ｙと連通する上層配線溝形成用溝１６ｙが形成されたハードマスク１６を順次形成する。 Next, as shown in FIG. 4A, a resist pattern (not shown) having an upper wiring groove pattern is formed on the hard mask 16 by photolithography. Subsequently, using the resist pattern as a mask, dry etching is sequentially performed on the hard mask 16 and the cap film 15 to form the upper wiring groove forming groove 16y in the hard mask 16 and the groove 15y in the cap film 15. Then, a groove 16Y that penetrates the hard mask 16 and the cap film 15 and exposes the upper surface of the second interlayer insulating film forming film 14X is formed. Subsequently, the resist pattern is removed. In this manner, the cap film 15 in which the groove 15y is formed and the hard mask 16 in which the upper-layer wiring groove forming groove 16y communicating with the groove 15y is sequentially formed on the second interlayer insulating film forming film 14X. Form.
　次に、図４(b) に示すように、半導体基板上の全面に、例えば、照射角度（即ち、半導体基板の主面の法線に対して傾斜する角度）が０°で紫外線を照射する、即ち、半導体基板上の全面に、半導体基板の主面に対して垂直な方向に紫外線を照射する（ＵＶ１参照）。このとき、紫外線のうちハードマスク１６に照射される紫外線は、ハードマスク１６により反射されて、第２の層間絶縁膜形成用膜１４Ｘのうち、溝１６Ｙの近傍に位置する領域に、紫外線が照射される。ここで、紫外線は、例えば１０秒～２０秒の短時間の間、１５０ｎｍ～３８０ｎｍの低エネルギーで照射されることが好ましい。またここで、本明細書中に登場する「第２の層間絶縁膜形成用膜１４Ｘのうち、溝１６Ｙの近傍に位置する領域」とは、第２の層間絶縁膜形成用膜１４Ｘのうち、１）溝１６Ｙの直下に位置する領域と、２）溝１６Ｙの外周下に位置する領域とを含む。 Next, as shown in FIG. 4B, the entire surface of the semiconductor substrate is irradiated with ultraviolet rays, for example, at an irradiation angle (that is, an angle inclined with respect to the normal of the main surface of the semiconductor substrate) of 0 °. That is, the entire surface of the semiconductor substrate is irradiated with ultraviolet rays in a direction perpendicular to the main surface of the semiconductor substrate (see UV1). At this time, the ultraviolet ray irradiated to the hard mask 16 out of the ultraviolet rays is reflected by the hard mask 16, and the ultraviolet ray is irradiated to a region located in the vicinity of the groove 16Y in the second interlayer insulating film forming film 14X. Is done. Here, the ultraviolet rays are preferably irradiated with low energy of 150 nm to 380 nm, for example, for a short time of 10 seconds to 20 seconds. Further, here, “the region located in the vicinity of the groove 16Y in the second interlayer insulating film forming film 14X” appearing in this specification refers to the second interlayer insulating film forming film 14X. 1) A region located directly below the groove 16Y and 2) a region located below the outer periphery of the groove 16Y.
　続いて、半導体基板上の全面に、例えば、照射角度が４５°で紫外線を照射する、即ち、半導体基板上の全面に、半導体基板の主面に対して傾斜する方向に紫外線を照射する（ＵＶ２参照）。このとき、紫外線のうちハードマスク１６に照射される紫外線は、ハードマスク１６により反射されて、第２の層間絶縁膜形成用膜１４Ｘのうち、溝１６Ｙの近傍に位置する領域に、紫外線が照射される。ここで、紫外線は、例えば１０秒～２０秒の短時間の間、１５０ｎｍ～３８０ｎｍの低エネルギーで照射されることが好ましい。 Subsequently, for example, the entire surface of the semiconductor substrate is irradiated with ultraviolet rays at an irradiation angle of 45 °, that is, the entire surface of the semiconductor substrate is irradiated with ultraviolet rays in a direction inclined with respect to the main surface of the semiconductor substrate (UV2). reference). At this time, the ultraviolet ray irradiated to the hard mask 16 out of the ultraviolet rays is reflected by the hard mask 16, and the ultraviolet ray is irradiated to a region located in the vicinity of the groove 16Y in the second interlayer insulating film forming film 14X. Is done. Here, the ultraviolet rays are preferably irradiated with low energy of 150 nm to 380 nm, for example, for a short time of 10 seconds to 20 seconds.
　これにより、図４(c) に示すように、ハードマスク１６を利用して、第２の層間絶縁膜形成用膜１４Ｘのうち、溝１６Ｙの近傍に位置する領域（即ち、紫外線が照射される領域）に存在するポロジェン１４ａを脱離し、ポロジェン１４ａが脱離されてなる空孔１４ｂを含有する多孔質領域１４Ｂと、脱離されずに残存するポロジェン１４ａを含有する非多孔質領域１４Ａとで構成される第２の層間絶縁膜１４を形成する。 As a result, as shown in FIG. 4C, using the hard mask 16, in the second interlayer insulating film forming film 14X, a region located near the groove 16Y (ie, irradiated with ultraviolet rays). The porogen 14a existing in the region) is desorbed, and a porous region 14B containing the pores 14b from which the porogen 14a is desorbed and a non-porous region 14A containing the porogen 14a remaining without being desorbed A second interlayer insulating film 14 is formed.
　ここで、多孔質領域１４Ｂは、溝１６Ｙの底面の中心点Ｃを基準に外方向に拡がるように形成され、中心点Ｃから距離Ｄh（図４(c) 参照）までの範囲内で、且つ中心点Ｃから距離Ｄv（図４(c) 参照）までの範囲内に形成される。ここで、距離Ｄhは、溝１６Ｙの底面に対して平行な方向に沿った距離であり、距離Ｄvは、溝１６Ｙの底面に対して垂直な方向に沿った距離である。なお、前述から判るように、距離Ｄhは、上層配線２１の配線幅Ｌの０．５倍に相当する距離と、第１の距離Ｄsとの総和に相当し（Ｄh＝Ｌ×０．５＋Ｄs）、距離Ｄvは、上層配線２１の配線高さＨに相当する距離と、第２の距離Ｄbとの総和に相当する（Ｄv＝Ｈ＋Ｄb）。 Here, the porous region 14B is formed so as to expand outward with respect to the center point C of the bottom surface of the groove 16Y, and within a range from the center point C to the distance Dh (see FIG. 4 (c)), and It is formed within a range from the center point C to the distance Dv (see FIG. 4C). Here, the distance Dh is a distance along a direction parallel to the bottom surface of the groove 16Y, and the distance Dv is a distance along a direction perpendicular to the bottom surface of the groove 16Y. As can be seen from the above, the distance Dh corresponds to the sum of the distance corresponding to 0.5 times the wiring width L of the upper wiring 21 and the first distance Ds (Dh = L × 0.5 + Ds). The distance Dv corresponds to the sum of the distance corresponding to the wiring height H of the upper layer wiring 21 and the second distance Db (Dv = H + Db).
　次に、図５(a) に示すように、フォトリソグラフィー法により、ハードマスク１６上に、ビアホールパターンを持つレジストパターン（図示省略）を形成した後、該レジストパターンをマスクに用いて、溝１６Ｙ内に露出する第２の層間絶縁膜１４に対してドライエッチングを行い、第２の層間絶縁膜１４を貫通し、バリア膜１３の上面を露出させるホール１７を形成する。続いて、該レジストパターンを除去する。 Next, as shown in FIG. 5A, after forming a resist pattern (not shown) having a via hole pattern on the hard mask 16 by photolithography, the groove 16Y is formed using the resist pattern as a mask. The second interlayer insulating film 14 exposed inside is dry-etched to form a hole 17 that penetrates the second interlayer insulating film 14 and exposes the upper surface of the barrier film 13. Subsequently, the resist pattern is removed.
　次に、図５(b) に示すように、エッチバック法により、ホール１７内に露出するバリア膜１３を除去し、バリア膜１３及び第２の層間絶縁膜１４の下部領域に、下層配線１２の上面を露出させるビアホール１８を形成する。それと共に、ハードマスク１６を利用して、溝１６Ｙ内に露出する第２の層間絶縁膜１４の上部領域を除去し、第２の層間絶縁膜１４の上部領域及びキャップ膜１５に、上層配線溝１９を形成する。このとき、ビアホール１８は、図５(b) に示すように、その下部領域が非多孔質領域１４Ａの界面領域（図１(b)：１４Ａi参照）を貫通し、その上部領域が多孔質領域１４Ｂの底面領域を貫通して形成される。それと共に、上層配線溝１９は、図５(b) に示すように、多孔質領域１４Ｂ内に形成される。 Next, as shown in FIG. 5B, the barrier film 13 exposed in the holes 17 is removed by an etch-back method, and the lower layer wiring 12 is formed in the lower regions of the barrier film 13 and the second interlayer insulating film. A via hole 18 is formed to expose the upper surface of. At the same time, the upper region of the second interlayer insulating film 14 exposed in the trench 16Y is removed using the hard mask 16, and the upper layer wiring trench is formed in the upper region of the second interlayer insulating film 14 and the cap film 15. 19 is formed. At this time, as shown in FIG. 5B, the via hole 18 has a lower region penetrating the interface region of the non-porous region 14A (see FIG. 1B: 14Ai), and an upper region thereof being a porous region. It is formed through the bottom area of 14B. At the same time, the upper wiring groove 19 is formed in the porous region 14B as shown in FIG. 5 (b).
　次に、図５(c) に示すように、スパッタ法により、ハードマスク１６上、上層配線溝形成用溝１６ｙの側面、上層配線溝１９の底面及び側面、ビアホール１８の底面及び側面に、Ｔａ膜とＴａＮ膜とが順次積層されてなるバリアメタル膜を堆積する。続いて、スパッタ法により、バリアメタル膜上に、銅を含むシード膜を形成した後、電解めっき法により、シード膜上に、ビアホール１８及び上層配線溝１９内を埋め込むように、銅を含むめっき膜を堆積する。 Next, as shown in FIG. 5C, by sputtering, Ta layer is formed on the hard mask 16, the side surfaces of the upper wiring groove forming groove 16y, the bottom surface and side surfaces of the upper wiring groove 19, and the bottom surface and side surfaces of the via hole 18. A barrier metal film in which a film and a TaN film are sequentially stacked is deposited. Subsequently, a seed film containing copper is formed on the barrier metal film by a sputtering method, and then plating containing copper so as to bury the via hole 18 and the upper wiring groove 19 on the seed film by an electrolytic plating method. Deposit a film.
　次に、ＣＭＰ法により、めっき膜、シード膜、バリアメタル膜、及びハードマスク１６のうち、ビアホール１８及び上層配線溝１９の外に形成された部分を順次除去する。このようにして、ハードマスク１６を除去した後、ビアホール１８内に、バリアメタル膜２０ａを介して、銅を含む導電膜２０ｂが埋め込まれてなるビア２０を形成すると共に、上層配線溝１９内に、バリアメタル膜２１ａを介して、銅を含む導電膜２１ｂが埋め込まれてなる上層配線２１を形成する。このとき、ビア２０は、図５(c) に示すように、その下部領域が非多孔質領域１４Ａの界面領域（図１(b)：１４Ａi参照）を貫通し、その上部領域が多孔質領域１４Ｂの底面領域を貫通して形成される。それと共に、上層配線２１は、図５(c) に示すように、多孔質領域１４Ｂ内に形成される（言い換えれば、多孔質領域１４Ｂは、第２の層間絶縁膜１４のうち、上層配線２１の周囲に位置する領域に形成される）。ここで、図５(c) において、導電膜２０ｂ，２１ｂのうち、シード膜とめっき膜との境界線は、図示が困難なため図示を省略する。 Next, portions of the plating film, seed film, barrier metal film, and hard mask 16 formed outside the via hole 18 and the upper wiring groove 19 are sequentially removed by CMP. After the hard mask 16 is removed in this way, vias 20 are formed in the via holes 18 by burying the conductive films 20b containing copper via the barrier metal films 20a. Then, an upper layer wiring 21 is formed in which a conductive film 21b containing copper is embedded through a barrier metal film 21a. At this time, as shown in FIG. 5C, the via 20 has a lower region penetrating the interface region of the non-porous region 14A (see FIG. 1B: 14Ai), and an upper region of the via 20 is a porous region. It is formed through the bottom area of 14B. At the same time, the upper layer wiring 21 is formed in the porous region 14B as shown in FIG. 5 (c) (in other words, the porous region 14B is the upper layer wiring 21 in the second interlayer insulating film 14). In the area located around the Here, in FIG. 5C, the boundary line between the seed film and the plating film in the conductive films 20b and 21b is not shown because it is difficult to show.
　以上のようにして、本実施形態に係る半導体装置を製造することができる。 As described above, the semiconductor device according to this embodiment can be manufactured.
　ここで、本実施形態では、図４(a) に示す工程において、上層配線溝パターンを持つレジストパターン（図示省略）を形成した後、図５(a) に示す工程において、ビアホールパターンを持つレジストパターン（図示省略）を形成し、続いて、図５(c) に示す工程において、ビアホール１８内にビア２０を形成すると共に、上層配線溝１９内に上層配線２１を形成する。即ち、本実施形態では、ビア２０、及び上層配線２１の形成方法として、上層配線溝パターンを持つレジストパターンを先に形成するトレンチファースト，ビアホールパターンを持つレジストパターンを後に形成するビアラストのデュアルダマシン法を採用する。 Here, in this embodiment, after forming a resist pattern (not shown) having an upper wiring groove pattern in the step shown in FIG. 4A, the resist having a via hole pattern in the step shown in FIG. A pattern (not shown) is formed, and subsequently, vias 20 are formed in the via holes 18 and upper wirings 21 are formed in the upper wiring grooves 19 in the step shown in FIG. That is, in this embodiment, the via 20 and the upper layer wiring 21 are formed by a trench first method in which a resist pattern having an upper layer wiring groove pattern is formed first and a via last dual damascene method in which a resist pattern having a via hole pattern is formed later. Is adopted.
　本実施形態によると、図１(b) に示すように、第２の層間絶縁膜１４のうち、上層配線２１の周囲に位置する領域に多孔質領域１４Ｂを設けて、多孔質領域１４Ｂ以外の領域に非多孔質領域１４Ａを設けることにより、第２の層間絶縁膜１４のうち、バリア膜１３との界面に位置する領域に、非多孔質領域１４Ａの界面領域１４Ａiを設けることができる。そのため、第２の層間絶縁膜１４におけるバリア膜１３との界面に空孔１４ｂが存在することがなく、空孔１４ｂにより第２の層間絶縁膜１４とバリア膜１３との密着性が低下することはない。そのため、例えば、図５(c) に示す工程におけるＣＭＰ工程、上層配線２１上に形成されるパッド（図示省略）にワイヤボンドを接続する工程（以下、「ワイヤボンディング工程」と称す）、又はパッドにプローブ針を当て内部回路を検査する検査工程（以下、「プローブ検査工程」と称す）等の際に、第２の層間絶縁膜１４とバリア膜１３との界面に剥離が発生することを防止することができる。 According to the present embodiment, as shown in FIG. 1B, a porous region 14B is provided in a region located around the upper-layer wiring 21 in the second interlayer insulating film 14, and the regions other than the porous region 14B are provided. By providing the non-porous region 14A in the region, the interface region 14Ai of the non-porous region 14A can be provided in the region located in the interface with the barrier film 13 in the second interlayer insulating film 14. Therefore, there is no hole 14b at the interface between the second interlayer insulating film 14 and the barrier film 13, and the adhesion between the second interlayer insulating film 14 and the barrier film 13 is reduced by the hole 14b. There is no. Therefore, for example, a CMP step in the step shown in FIG. 5C, a step of connecting a wire bond to a pad (not shown) formed on the upper layer wiring 21 (hereinafter referred to as “wire bonding step”), or a pad Prevents the occurrence of delamination at the interface between the second interlayer insulating film 14 and the barrier film 13 during an inspection process (hereinafter referred to as “probe inspection process”) in which an internal circuit is inspected by applying a probe needle to can do.
　それと共に、図１(b) に示すように、第２の層間絶縁膜１４のうち、上層配線２１の周囲に位置する領域に、多孔質領域１４Ｂを設けることにより、第２の層間絶縁膜１４のうち、配線間容量の低減に効果的に貢献する領域に、多孔質領域１４Ｂを設けることができるため、配線間容量を効果的に低減させて、半導体装置の高速化を図ることができる。 At the same time, as shown in FIG. 1B, by providing a porous region 14B in a region located around the upper wiring 21 in the second interlayer insulating film 14, the second interlayer insulating film 14 is provided. Among these, the porous region 14B can be provided in a region that effectively contributes to the reduction of the inter-wiring capacitance, so that the inter-wiring capacitance can be effectively reduced and the speed of the semiconductor device can be increased.
　加えて、図１(b) に示すように、第２の層間絶縁膜１４のうち、比較的大きい配線間隔（詳細には、第１の距離Ｄsの２倍に相当する間隔よりも大きい配線間隔）を有する上層配線２１間の中央部に、非多孔質領域１４Ａの配線間領域１４Ａsを設けることができる。ここで、比較的大きい配線間隔を有する上層配線２１間の領域は、キャップ膜１５との接触面積が比較的大きく、キャップ膜１５との界面に剥離が発生する可能性が比較的高い。そのため、比較的大きい配線間隔を有する上層配線２１間の中央部に、非多孔質領域１４Ａの配線間領域１４Ａsを設けることにより、例えば、ＣＭＰ工程等の際に、第２の層間絶縁膜１４とキャップ膜１５との界面に剥離が発生することを防止することができる。一方、比較的小さい配線間隔を有する上層配線２１間の領域は、比較的大きい配線間隔を有する上層配線２１間の領域に比べて、キャップ膜１５との接触面積が小さく、キャップ膜１５との界面に剥離が発生する可能性が低い。そのため、比較的小さい配線間隔を有する上層配線２１間の領域に、非多孔質領域を設ける必要はない。 In addition, as shown in FIG. 1B, a relatively large wiring interval (specifically, a wiring interval larger than an interval corresponding to twice the first distance Ds in the second interlayer insulating film 14). The inter-wiring region 14As of the non-porous region 14A can be provided in the center between the upper-layer wirings 21 having the Here, the area between the upper layer wirings 21 having a relatively large wiring interval has a relatively large contact area with the cap film 15, and the possibility that separation occurs at the interface with the cap film 15 is relatively high. Therefore, by providing the inter-wiring region 14As of the non-porous region 14A in the center between the upper layer wirings 21 having a relatively large wiring interval, for example, in the CMP process, the second interlayer insulating film 14 and It is possible to prevent the peeling from occurring at the interface with the cap film 15. On the other hand, the area between the upper layer wirings 21 having a relatively small wiring interval has a smaller contact area with the cap film 15 than the region between the upper layer wirings 21 having a relatively large wiring interval, and the interface with the cap film 15. Is less likely to peel. Therefore, it is not necessary to provide a non-porous region in a region between the upper layer wirings 21 having a relatively small wiring interval.
　加えて、図１(b) に示すように、第２の層間絶縁膜１４のうち、バリア膜１３との界面に位置する領域に、非多孔質領域１４Ａの界面領域１４Ａiを設けることにより、ビア２０の下部領域は非多孔質領域１４Ａの界面領域１４Ａiに囲まれるため、ビア２０の底面領域に空孔１４ｂが存在することがなく、例えば、空孔１４ｂ内に捕獲される水分、又は空孔１４ｂ内に残留するエッチングガス等により、ビア２０の底面領域が酸化される、又はビア２０の底面領域が腐食されて、ビア２０の信頼性が低下することを防止することができる。 In addition, as shown in FIG. 1B, by providing an interface region 14Ai of the non-porous region 14A in a region located at the interface with the barrier film 13 in the second interlayer insulating film 14, vias Since the lower region of 20 is surrounded by the interface region 14Ai of the non-porous region 14A, there is no hole 14b in the bottom region of the via 20, for example, moisture trapped in the hole 14b, or It can be prevented that the bottom surface region of the via 20 is oxidized or the bottom surface region of the via 20 is corroded by the etching gas or the like remaining in 14b and the reliability of the via 20 is lowered.
　加えて、図１(b) に示すように、第２の層間絶縁膜１４のうち、下層配線１２と上層配線２１間に位置する領域に、多孔質領域１４Ｂの底面領域の膜厚（図２：Ｄb参照）と略同一の膜厚（図２：Ｄi参照）を有する非多孔質領域１４Ａの界面領域１４Ａiを設けることができる。そのため、第２の層間絶縁膜１４のうち、下層配線１２と上層配線２１間に位置する領域の機械的強度を確保する（具体的には例えば、第２の層間絶縁膜１４のうち、下層配線１２と上層配線２１間に位置する領域が、８ＧＰａ以上のヤング率を確保する）ことができる。そのため、例えば、ワイヤボンディング工程、又はプローブ検査工程等の際に、第２の層間絶縁膜１４のうち、下層配線１２と上層配線２１間に位置する領域に、割れが発生することを防止することができる。 In addition, as shown in FIG. 1B, the thickness of the bottom region of the porous region 14B in the region located between the lower layer wiring 12 and the upper layer wiring 21 in the second interlayer insulating film 14 (FIG. 2). : Db) can be provided with the interface region 14Ai of the non-porous region 14A having substantially the same film thickness (see FIG. 2: Di). Therefore, the mechanical strength of a region located between the lower layer wiring 12 and the upper layer wiring 21 in the second interlayer insulating film 14 is ensured (specifically, for example, the lower layer wiring in the second interlayer insulating film 14). 12 and the upper layer wiring 21 can secure a Young's modulus of 8 GPa or more). Therefore, for example, in the wire bonding process or the probe inspection process, it is possible to prevent the second interlayer insulating film 14 from being cracked in a region located between the lower layer wiring 12 and the upper layer wiring 21. Can do.
　以上のように、第２の層間絶縁膜１４のうち、上層配線２１の周囲に位置する領域に多孔質領域１４Ｂを設けて、多孔質領域１４Ｂ以外の領域に非多孔質領域１４Ａを設けることにより、配線間容量を効果的に低減させると共に、第２の層間絶縁膜１４とバリア膜１３との界面に剥離が発生することを防止するとことができる。加えて、配線間容量を効果的に低減しながら、
１）第２の層間絶縁膜１４とキャップ膜１５との界面に剥離が発生することを防止する，
２）ビア２０の信頼性が低下することを防止する，
３）第２の層間絶縁膜１４のうち、下層配線１２と上層配線２１間に位置する領域に、割れが発生することを防止することができる。 As described above, by providing the porous region 14B in the region located around the upper wiring 21 in the second interlayer insulating film 14, and providing the nonporous region 14A in the region other than the porous region 14B. In addition, the inter-wiring capacitance can be effectively reduced and the occurrence of peeling at the interface between the second interlayer insulating film 14 and the barrier film 13 can be prevented. In addition, while effectively reducing the capacitance between wires,
1) Prevent peeling from occurring at the interface between the second interlayer insulating film 14 and the cap film 15;
2) Prevent the reliability of the via 20 from being lowered,
3) It is possible to prevent a crack from occurring in a region located between the lower layer wiring 12 and the upper layer wiring 21 in the second interlayer insulating film 14.
　なお、本実施形態では、本発明を容易に説明する為に、図１(b) に示すように、多孔質領域１４Ｂは、空孔１４ｂのみを含有し、ポロジェン１４ａを含有せず、一方、非多孔質領域１４Ａは、ポロジェン１４ａのみを含有し、空孔１４ｂを含有しない場合を具体例に挙げて説明したが、本発明はこれに限定されるものではない。例えば、多孔質領域１４Ｂが、空孔１４ｂだけでなく、空孔１４ｂの個数よりも少ない個数のポロジェン１４ａを含有し、一方、非多孔質領域１４Ａが、ポロジェン１４ａだけでなく、ポロジェン１４ａの個数よりも少ない個数の空孔１４ｂを含有してもよい。特に、多孔質領域１４Ｂと非多孔質領域１４Ａとの境界領域には、空孔１４ｂとポロジェン１４ａとが混在する場合がある。 In this embodiment, in order to easily explain the present invention, as shown in FIG. 1B, the porous region 14B contains only the pores 14b and does not contain the porogen 14a, Although the non-porous region 14A contains only the porogen 14a and does not contain the pores 14b, a specific example has been described, but the present invention is not limited to this. For example, the porous region 14B contains not only the holes 14b but also a smaller number of porogens 14a than the number of the holes 14b, while the non-porous region 14A includes not only the porogens 14a but also the number of porogens 14a. A smaller number of holes 14b may be contained. In particular, pores 14b and porogens 14a may be mixed in the boundary region between the porous region 14B and the non-porous region 14A.
　即ち、本明細書中の「多孔質領域」とは、空孔を主に含有する領域であり、一方、本明細書中の「非多孔質領域」とは、空孔を主に含有しない領域であり、「多孔質領域」は、「非多孔質領域」に比べて、高い空孔密度を有する領域であり、一方、「非多孔質領域」は、「多孔質領域」に比べて、低い空孔密度を有する領域である。 That is, the “porous region” in the present specification is a region mainly containing pores, while the “non-porous region” in the present specification is a region not mainly containing pores. The “porous region” is a region having a higher pore density than the “non-porous region”, while the “non-porous region” is lower than the “porous region”. This is a region having a void density.
　また、本実施形態では、紫外線を反射させるハードマスク１６の金属材料として、ＴｉＮを用いる場合を具体例に挙げて説明したが、本発明はこれに限定されるものではない。紫外線を反射させるハードマスクの金属材料として、例えば、Ｔｉ、Ｔａ、ＴａＮ、Ｗ、及びＷＮ等からなる群から選択される１種類、又は複数種類の金属材料を用いてもよい。 In the present embodiment, the case where TiN is used as the metal material of the hard mask 16 that reflects ultraviolet rays has been described as a specific example, but the present invention is not limited to this. As the metal material of the hard mask that reflects ultraviolet rays, for example, one or more kinds of metal materials selected from the group consisting of Ti, Ta, TaN, W, WN, and the like may be used.
　また、本実施形態では、図４(b) に示すように、半導体基板上の全面に、半導体基板の主面に対して垂直な方向に紫外線を照射した（ＵＶ１参照）後、半導体基板上の全面に、半導体基板の主面に対して傾斜する方向に紫外線を照射する（ＵＶ２参照）場合を具体例に挙げて説明したが、本発明はこれに限定されるものではない。第１に例えば、半導体基板上の全面に、半導体基板の主面に対して垂直な方向にのみ、紫外線を照射する、又は第２に例えば、半導体基板上の全面に、半導体基板の主面に対して傾斜する方向にのみ、紫外線を照射してもよい。 In the present embodiment, as shown in FIG. 4B, the entire surface of the semiconductor substrate is irradiated with ultraviolet rays in a direction perpendicular to the main surface of the semiconductor substrate (see UV1), and then on the semiconductor substrate. Although the case where ultraviolet rays are irradiated on the entire surface in a direction inclined with respect to the main surface of the semiconductor substrate (see UV2) has been described as a specific example, the present invention is not limited to this. First, for example, the entire surface of the semiconductor substrate is irradiated with ultraviolet rays only in a direction perpendicular to the main surface of the semiconductor substrate. Second, for example, the entire surface of the semiconductor substrate is irradiated on the main surface of the semiconductor substrate. The ultraviolet rays may be irradiated only in the direction inclined with respect to the surface.
　また、本実施形態では、第２の層間絶縁膜形成用膜１４のうち、溝１６Ｙの近傍に位置する領域に存在するポロジェン１４ａを脱離する方法として、ハードマスク１６として、紫外線を反射させる金属膜を採用し、ポロジェン１４ａとして、紫外線の照射により脱離するポロジェンを採用し、半導体基板上の全面に、紫外線を照射する場合を具体例に挙げて説明したが、本発明はこれに限定されるものではない。 Further, in the present embodiment, as a method of detaching the porogen 14a existing in the region located near the trench 16Y in the second interlayer insulating film forming film 14, the hard mask 16 is a metal that reflects ultraviolet rays. A case where a film is used and a porogen that is desorbed by irradiation of ultraviolet rays is adopted as the porogen 14a and the entire surface of the semiconductor substrate is irradiated with ultraviolet rays has been described as a specific example, but the present invention is not limited thereto. It is not something.
　第１に例えば、ハードマスクとして、紫外線を吸収する絶縁膜を採用し、ポロジェンとして、紫外線の照射により脱離するポロジェンを採用し、半導体基板上の全面に、紫外線を照射してもよい。このように、第２の層間絶縁膜形成用膜上に、溝が形成されたキャップ膜、及び上層配線溝形成用溝が形成されたハードマスクが順次形成された状態で、紫外線を照射することにより、紫外線のうちハードマスクに照射される紫外線は、ハードマスクに吸収されて、第２の層間絶縁膜形成用膜のうち、溝、及び上層配線溝形成用溝の近傍に位置する領域に、紫外線が照射される。ここで、紫外線を吸収するハードマスクの絶縁材料としては、例えば、ＳｉＣＮ、ＳｉＣＯ、ＳｉＣＨ、ＳｉＯＮ、ＳｉＯ2、及びＳｉＮ等からなる群から選択される１種類、又は複数種類の絶縁材料が挙げられる。 First, for example, an insulating film that absorbs ultraviolet rays may be employed as the hard mask, and porogen that is desorbed by ultraviolet irradiation may be employed as the porogen, and the entire surface of the semiconductor substrate may be irradiated with ultraviolet rays. As described above, the cap film having the groove and the hard mask having the upper wiring groove forming groove are sequentially formed on the second interlayer insulating film forming film and then irradiated with ultraviolet rays. Thus, the ultraviolet ray irradiated to the hard mask among the ultraviolet rays is absorbed by the hard mask, and in the second interlayer insulating film forming film, the region located in the vicinity of the groove and the upper wiring groove forming groove, Ultraviolet rays are irradiated. Here, as the insulating material of the hard mask that absorbs ultraviolet rays, for example, one type or a plurality of types of insulating materials selected from the group consisting of SiCN, SiCO, SiCH, SiON, SiO 2 , SiN, and the like can be given. .
　第２に例えば、ハードマスクとして、電子線を反射させる金属膜を採用し、ポロジェンとして、電子線の照射により脱離するポロジェンを採用し、半導体基板上の全面に、電子線を照射してもよい。 Second, for example, a metal film that reflects an electron beam is used as a hard mask, and a porogen that is detached by irradiation with an electron beam is used as a porogen. Good.
　第３に例えば、ハードマスクとして、電子線を吸収する絶縁膜を採用し、ポロジェンとして、電子線の照射により脱離するポロジェンを採用し、半導体基板上の全面に、電子線を照射してもよい。 Third, for example, an insulating film that absorbs an electron beam is used as a hard mask, and a porogen that is desorbed by irradiation with an electron beam is used as a porogen. Good.
　第４に例えば、ハードマスクとして、密度の比較的高い膜を採用し、ポロジェンとして、熱処理により脱離するポロジェンを採用し、半導体基板上の全面に対し、熱処理を施してもよい。このように、第２の層間絶縁膜形成用膜上に、溝が形成されたキャップ膜、及び上層配線溝形成用溝が形成されたハードマスクが順次形成された状態で、熱処理を施すことにより、第２の層間絶縁膜形成用膜のうち、溝、及び上層配線溝形成用溝の近傍に位置する領域に存在するポロジェンを脱離することができる。ここで、熱処理温度は、例えば、３００℃の低温であることが好ましく、熱処理時間は、例えば、数１０秒～３分程度の短時間であることが好ましい。またここで、ハードマスクの密度は、例えば、２．２１ｇ／ｃｍ3程度であることが好ましい。またここで、ハードマスクの材料としては、例えば、Ｔｉ、ＴｉＮ、Ｔａ、ＴａＮ、Ｗ、及びＷＮ等からなる金属材料群、並びにＳｉＣＮ、ＳｉＣＯ、ＳｉＣＨ、ＳｉＯＮ、ＳｉＯ2、及びＳｉＮ等からなる絶縁材料群から選択される１種類、又は複数種類の材料が挙げられる。但し、キャップ膜の密度が比較的高い場合、キャップ膜上にハードマスクを設けずに、第２の層間絶縁膜形成用膜上に、溝が形成されたキャップ膜のみが形成された状態で、熱処理を施してもよい。 Fourth, for example, a film having a relatively high density may be employed as the hard mask, and a porogen that is desorbed by heat treatment may be employed as the porogen, and the entire surface of the semiconductor substrate may be heat treated. In this way, heat treatment is performed in a state in which the cap film in which the groove is formed and the hard mask in which the groove for forming the upper wiring groove is formed in order on the second interlayer insulating film forming film. In the second interlayer insulating film forming film, the porogen present in the region located in the vicinity of the groove and the upper wiring groove forming groove can be removed. Here, the heat treatment temperature is preferably a low temperature of 300 ° C., for example, and the heat treatment time is preferably a short time of about several tens of seconds to 3 minutes, for example. Here, the density of the hard mask is preferably about 2.21 g / cm 3 , for example. Here, as the material of the hard mask, for example, a metal material group made of Ti, TiN, Ta, TaN, W, WN, etc., and an insulation made of SiCN, SiCO, SiCH, SiON, SiO 2 , SiN, etc. One type or a plurality of types of materials selected from the material group can be mentioned. However, when the density of the cap film is relatively high, without providing a hard mask on the cap film, only the cap film in which the groove is formed is formed on the second interlayer insulating film forming film. Heat treatment may be performed.
　また、本実施形態では、バリア膜１３として、ＳｉＣＮ膜を用いる場合を具体例に挙げて説明したが、本発明はこれに限定されるものではない。第１に例えば、ＳｉＣＮ膜の代わりに、シリコン炭酸化膜（ＳｉＣＯ膜）を用いてもよい。第２に例えば、ＳｉＣＮ膜の単層膜の代わりに、ＳｉＣＮ膜、及びＳｉＣＯ膜が順次積層されてなる積層膜を用いてもよい。ここで、ＳｉＣＯ膜の形成方法としては、温度が４００℃の下、原料ガスとして、テトラメチルシラン（Ｓｉ(ＣＨ3)4）ガス、及び二酸化炭素（ＣＯ2）ガスを用い、希釈ガスとして、ヘリウム（Ｈｅ）ガスを用いて、プラズマＣＶＤ法により行う方法等が挙げられる。 In the present embodiment, the case where a SiCN film is used as the barrier film 13 has been described as a specific example, but the present invention is not limited to this. First, for example, a silicon carbonate film (SiCO film) may be used instead of the SiCN film. Second, for example, instead of the single-layer film of the SiCN film, a stacked film in which a SiCN film and a SiCO film are sequentially stacked may be used. Here, as a method for forming the SiCO film, tetramethylsilane (Si (CH 3 ) 4 ) gas and carbon dioxide (CO 2 ) gas are used as the source gas at a temperature of 400 ° C., and as the dilution gas, Examples include a method performed by plasma CVD using helium (He) gas.
　＜具体例＞
　以下に、本発明の一実施形態の具体例に係る半導体装置の構成について、図６(a) 及び(b) を参照しながら説明する。図６(a) 及び(b) は、本発明の一実施形態の具体例に係る半導体装置の構成を示す断面図である。 <Specific example>
The configuration of the semiconductor device according to a specific example of one embodiment of the present invention will be described below with reference to FIGS. 6 (a) and 6 (b). FIGS. 6A and 6B are cross-sectional views showing the configuration of a semiconductor device according to a specific example of one embodiment of the present invention.
　図６(a) に示すように、本具体例に係る半導体装置として、
・配線４１ａ，４１ｂ，４１ｃの配線幅Ｌa，Ｌb，Ｌcが略同一で、配線幅Ｌa，Ｌb，Ｌcは、最小配線幅Ｌminに相当する幅であり（Ｌa，Ｌb，Ｌc＝Ｌmin）、
・配線４１ａ，４１ｂ，４１ｃの配線高さＨa，Ｈb，Ｈcが略同一で、配線高さＨa，Ｈb，Ｈcは、最小配線幅Ｌminの２倍に相当する高さであり（Ｈa，Ｈb，Ｈc＝Ｌmin×２）、
・互いに隣り合う配線４１ｂと配線４１ｃ間の配線間隔Ｓbcが最小配線間隔Ｓminであり（Ｓbc＝Ｓmin）、
・互いに隣り合う配線４１ａと配線４１ｂ間の配線間隔Ｓabの間隔が、最小配線間隔Ｓminの３倍に相当する間隔よりも大きく（Ｓab＞Ｓmin×３）、
・最小配線幅Ｌminの幅は、最小配線間隔Ｓminの間隔と略同一であり（Ｌmin＝Ｓmin）、
・第２の層間絶縁膜３４の膜厚とキャップ膜３５の膜厚との総和膜厚Ｔが、最小配線間隔Ｓminの４倍に相当する膜厚である（Ｔ＝Ｓmin×４）
場合の半導体装置を示す。 As shown in FIG. 6 (a), as a semiconductor device according to this example,
The wiring widths La, Lb, and Lc of the wirings 41a, 41b, and 41c are substantially the same, and the wiring widths La, Lb, and Lc are widths corresponding to the minimum wiring width Lmin (La, Lb, Lc = Lmin),
The wiring heights Ha, Hb, Hc of the wirings 41a, 41b, 41c are substantially the same, and the wiring heights Ha, Hb, Hc are equivalent to twice the minimum wiring width Lmin (Ha, Hb, Hc = Lmin × 2),
The wiring interval Sbc between the adjacent wirings 41b and 41c is the minimum wiring interval Smin (Sbc = Smin).
The interval of the wiring interval Sab between the adjacent wirings 41a and 41b is larger than the interval corresponding to three times the minimum wiring interval Smin (Sab> Smin × 3).
The width of the minimum wiring width Lmin is substantially the same as the minimum wiring interval Smin (Lmin = Smin)
The total film thickness T of the second interlayer insulating film 34 and the cap film 35 is equivalent to four times the minimum wiring interval Smin (T = Smin × 4).
The semiconductor device in the case is shown.
　多孔質領域３４Ｂは、図６(a) に示すように、上層配線４１ａ～４１ｃの側面から、最小配線間隔Ｓminの１．５倍に相当する第１の距離Ｄs（Ｄs＝Ｓmin×１．５）までの範囲内で、且つ上層配線４１ａ～４１ｃの底面から、底面界面距離Ｄbiの０．５倍に相当する第２の距離Ｄb（Ｄb＝Ｄbi×０．５）までの範囲内に形成されている。 As shown in FIG. 6A, the porous region 34B has a first distance Ds (Ds = Smin × 1.5) corresponding to 1.5 times the minimum wiring interval Smin from the side surfaces of the upper layer wirings 41a to 41c. ) And the second distance Db (Db = Dbi × 0.5) corresponding to 0.5 times the bottom interface distance Dbi from the bottom surface of the upper layer wirings 41a to 41c. ing.
　非多孔質領域３４Ａの界面領域は、図６(a) に示すように、第２の層間絶縁膜３４におけるバリア膜３３との界面から、底面界面距離Ｄbiの０．５倍に相当する第３の距離Ｄi（Ｄi＝Ｄbi×０．５，即ち、Ｄi＝Ｄb）までの範囲内に形成されている。 The interface region of the non-porous region 34A is a third region corresponding to 0.5 times the bottom interface distance Dbi from the interface with the barrier film 33 in the second interlayer insulating film 34, as shown in FIG. Is formed within a range up to a distance Di (Di = Dbi × 0.5, that is, Di = Db).
　非多孔質領域３４Ａの配線間領域は、図６(a) に示すように、互いに隣り合う上層配線の配線間のうち、第１の距離Ｄsの２倍に相当する間隔よりも大きい配線間隔Ｓabを有する配線間の中央部に形成されている。 As shown in FIG. 6A, the inter-wiring region of the non-porous region 34A has a wiring interval Sab that is larger than an interval corresponding to twice the first distance Ds among the wirings of the upper layer wirings adjacent to each other. Formed in the center between the wirings having
　本具体例に係る半導体装置において、最小配線間隔Ｓminを「１」とすると、図６(b) に示すように、
・配線幅Ｌa，Ｌb，Ｌcは「１」
・配線高さＨa，Ｈb，Ｈcは「２」
・配線間隔Ｓbcは「１」
・総和膜厚Ｔは「４」
・第１の距離Ｄsは「１．５」
・第２の距離Ｄbは「１」
・第３の距離Ｄiは「１」
・底面界面距離Ｄbiは「２」
・ビア４０のビア高さは「２」
となる。なお、図６(b) は、図６(a) に示す図と同一の図である。 In the semiconductor device according to this example, when the minimum wiring interval Smin is “1”, as shown in FIG.
・ Wiring widths La, Lb, and Lc are “1”.
・ Wiring heights Ha, Hb, Hc are “2”
-Wiring interval Sbc is "1"
・ Total film thickness T is "4"
The first distance Ds is “1.5”
・ The second distance Db is "1"
・ The third distance Di is "1"
-Bottom interface distance Dbi is "2"
・ The via height of via 40 is “2”
It becomes. FIG. 6 (b) is the same diagram as that shown in FIG. 6 (a).
　本具体例によると、第２の層間絶縁膜３４のうち、上層配線４１ａ～４１ｃの周囲に位置する領域に多孔質領域３４Ｂを設けて、多孔質領域３４Ｂ以外の領域に非多孔質領域３４Ａを設けることにより、配線間容量を効果的に低減させると共に、第２の層間絶縁膜３４とバリア膜３３との界面に剥離が発生することを防止するとことができる。加えて、配線間容量を効果的に低減しながら、
１）第２の層間絶縁膜３４とキャップ膜３５との界面に剥離が発生することを防止する，
２）ビア４０の信頼性が低下することを防止する，
３）第２の層間絶縁膜３４のうち、下層配線３２ａ～３２ｃと上層配線４１ａ～４１ｃ間に位置する領域に、割れが発生することを防止することができる。 According to this example, the porous region 34B is provided in a region located around the upper wirings 41a to 41c in the second interlayer insulating film 34, and the non-porous region 34A is provided in a region other than the porous region 34B. By providing, it is possible to effectively reduce the capacitance between the wirings and to prevent peeling at the interface between the second interlayer insulating film 34 and the barrier film 33. In addition, while effectively reducing the capacitance between wires,
1) Prevent peeling from occurring at the interface between the second interlayer insulating film 34 and the cap film 35;
2) Prevent the reliability of the via 40 from being lowered.
3) In the second interlayer insulating film 34, it is possible to prevent a crack from occurring in a region located between the lower layer wirings 32a to 32c and the upper layer wirings 41a to 41c.
　なお、本具体例では、第１の距離Ｄsが、最小配線間隔Ｓminの１．５倍に相当する距離（Ｄs＝Ｓmin×１．５）である場合を具体例に挙げて説明したが、本発明はこれに限定されるものではなく、第１の距離は、最小配線間隔Ｓminに相当する距離以上で、且つ最小配線間隔Ｓminの１．５倍に相当する距離以下であればよい。 In this specific example, the case where the first distance Ds is a distance corresponding to 1.5 times the minimum wiring interval Smin (Ds = Smin × 1.5) has been described as a specific example. The invention is not limited to this, and the first distance may be not less than a distance corresponding to the minimum wiring interval Smin and not more than a distance corresponding to 1.5 times the minimum wiring interval Smin.
　また、本具体例は、単なる一例に過ぎず、本発明は、本具体例に限定されるものではない。 Further, this specific example is merely an example, and the present invention is not limited to this specific example.
　本発明は、配線が形成された層間絶縁膜と、層間絶縁膜下に層間絶縁膜と接して形成された下層との界面に、剥離が発生することを防止することができるため、配線が形成された層間絶縁膜を有する半導体装置及びその製造方法に有用である。 Since the present invention can prevent peeling at the interface between the interlayer insulating film in which the wiring is formed and the lower layer formed in contact with the interlayer insulating film under the interlayer insulating film, the wiring is formed. The present invention is useful for a semiconductor device having an interlayer insulating film and a manufacturing method thereof.
　１０　　第１の層間絶縁膜
　１１　 下層配線溝
　１２ 　下層配線
　１２ａ　　バリアメタル膜
　１２ｂ　　導電膜
　１３　　バリア膜
　１４Ｘ　　第２の層間絶縁膜形成用膜
　１４　　第２の層間絶縁膜
　１４Ａ　　非多孔質領域
　１４Ａs　　配線間領域
　１４Ａi　　界面領域
　１４Ｂ　　多孔質領域
　１４ａ　　ポロジェン
　１４ｂ　　空孔
　１５　　キャップ膜
　１５ｙ　溝
　１６　　ハードマスク
　１６ｙ　　上層配線溝形成用溝
　１６Ｙ　　溝
　１７　　ホール
　１８　　ビアホール
　１９　　上層配線溝
　２０　　ビア
　２０ａ　　バリアメタル膜
　２０ｂ　　導電膜
　２１　　上層配線
　２１ａ　バリアメタル膜
　２１ｂ　導電膜
　Ｄs　　第１の距離
　Ｄb　　第２の距離
　Ｄi　　第３の距離
　Ｄbi　　底面界面距離
　ＵＶ１，ＵＶ２　　紫外線
　３２ａ，３２ｂ，３２ｃ　　下層配線
　３３　　バリア膜
　３４　　第２の層間絶縁膜
　３４Ａ　　非多孔質領域
　３４Ｂ　　多孔質領域
　３５　　キャップ膜
　４０　　ビア
　４１ａ，４１ｂ，４１ｃ　　上層配線
　Ｌa，Ｌb，Ｌc　　配線幅
　Ｈa，Ｈb，Ｈc　　配線高さ
　Ｓab，Ｓbc　　配線間隔
　Ｔ　　総和膜厚 DESCRIPTION OF SYMBOLS 10 1st interlayer insulation film 11 Lower layer wiring groove | channel 12 Lower layer wiring 12a Barrier metal film 12b Conductive film 13 Barrier film 14X 2nd interlayer insulation film formation film 14 2nd interlayer insulation film 14A Non-porous area | region 14As Between wiring area | region 14Ai interface region 14B porous region 14a porogen 14b hole 15 cap film 15y groove 16 hard mask 16y upper layer wiring groove forming groove 16Y groove 17 hole 18 via hole 19 upper layer wiring groove 20 via 20a barrier metal film 20b conductive film 21 upper layer wiring 21a Barrier metal film 21b Conductive film Ds First distance Db Second distance Di Third distance Dbi Bottom interface distance UV1, UV2 Ultraviolet light 32a, 32b, 32c Lower layer wiring 33 Barrier film 34 Second interlayer insulating film 34A Non-porous Region 34B Porous region 35 Cap film 40 Via 41a, 41b, 41c Upper layer wiring La, Lb, Lc Wiring width Ha, Hb, Hc Wiring height Sab, Sbc Wiring interval T Total film thickness

Claims (23)

  1. 　半導体基板上に形成された第１の層間絶縁膜と、
    　前記第１の層間絶縁膜上に形成された第２の層間絶縁膜と、
    　前記第２の層間絶縁膜の上部領域に形成された第１の配線とを備え、
    　前記第２の層間絶縁膜は、空孔を含有する多孔質領域と、非多孔質領域とで構成され、
    　前記多孔質領域は、前記第２の層間絶縁膜のうち、前記第１の配線の周囲に位置する領域に形成され、
    　前記非多孔質領域は、少なくとも前記第１の層間絶縁膜と前記多孔質領域との間に介在して形成されていることを特徴とする半導体装置。     A first interlayer insulating film formed on the semiconductor substrate;
    A second interlayer insulating film formed on the first interlayer insulating film;
    A first wiring formed in an upper region of the second interlayer insulating film,
    The second interlayer insulating film is composed of a porous region containing pores and a non-porous region,
    The porous region is formed in a region located around the first wiring in the second interlayer insulating film,
    The non-porous region is formed at least between the first interlayer insulating film and the porous region.
  2. 　請求項１に記載の半導体装置において、
    　前記多孔質領域に含有される空孔は、ポロジェンが脱離されてなる空孔であり、
    　前記非多孔質領域は、脱離されずに残存するポロジェンを含有していることを特徴とする半導体装置。     The semiconductor device according to claim 1,
    The pores contained in the porous region are pores formed by removing porogen,
    The non-porous region contains a porogen that remains without being desorbed.
  3. 　請求項１又は２に記載の半導体装置において、
    　前記多孔質領域は、前記第１の配線の側面から第１の距離までの範囲内で、且つ前記第１の配線の底面から第２の距離までの範囲内に形成されていることを特徴とする半導体装置。     The semiconductor device according to claim 1 or 2,
    The porous region is formed in a range from a side surface of the first wiring to a first distance and in a range from a bottom surface of the first wiring to a second distance. Semiconductor device.
  4. 　請求項３に記載の半導体装置において、
    　前記第１の距離は、最小配線間隔に相当する距離以上で、且つ前記最小配線間隔の１．５倍に相当する距離以下であり、
    　前記第２の距離は、前記第１の配線の底面と前記第２の層間絶縁膜における前記第１の層間絶縁膜との界面との底面界面距離の約０．５倍に相当する距離であることを特徴とする半導体装置。     The semiconductor device according to claim 3.
    The first distance is not less than a distance corresponding to the minimum wiring interval and not more than a distance corresponding to 1.5 times the minimum wiring interval.
    The second distance is a distance corresponding to about 0.5 times the bottom interface distance between the bottom surface of the first wiring and the interface between the first interlayer insulating film and the second interlayer insulating film. A semiconductor device.
  5. 　請求項３又は４に記載の半導体装置において、
    　前記非多孔質領域は、
    　　前記第２の層間絶縁膜における前記第１の層間絶縁膜との界面から、第３の距離までの範囲内に形成される界面領域と、
    　　互いに隣り合う前記第１の配線の配線間のうち、前記第１の距離の２倍に相当する間隔よりも大きい間隔を有する配線間の中央部に形成される配線間領域とを含み、
    　前記第３の距離は、前記第１の配線の底面と前記第２の層間絶縁膜における前記第１の層間絶縁膜との界面との底面界面距離の約０．５倍に相当する距離であることを特徴とする半導体装置。     The semiconductor device according to claim 3 or 4,
    The non-porous region is
    An interface region formed in a range from the interface between the second interlayer insulating film and the first interlayer insulating film to a third distance;
    An inter-wiring region formed at a central portion between wirings having a spacing larger than a spacing corresponding to twice the first distance among wirings of the first wirings adjacent to each other;
    The third distance is a distance corresponding to about 0.5 times the bottom interface distance between the bottom surface of the first wiring and the interface between the first interlayer insulating film and the second interlayer insulating film. A semiconductor device.
  6. 　請求項１～５のうちいずれか１項に記載の半導体装置において、
    　前記第２の層間絶縁膜の下部領域に形成されたビアをさらに備え、
    　前記ビアは、その下部領域が前記非多孔質領域を貫通し、その上部領域が前記多孔質領域を貫通して形成されていることを特徴とする半導体装置。     The semiconductor device according to any one of claims 1 to 5,
    A via formed in a lower region of the second interlayer insulating film;
    The semiconductor device according to claim 1, wherein a lower region of the via penetrates the non-porous region and an upper region penetrates the porous region.
  7. 　請求項６に記載の半導体装置において、
    　前記第１の層間絶縁膜に形成された第２の配線をさらに備え、
    　前記第１の配線は、前記ビアを介して、前記第２の配線と接続されていることを特徴とする半導体装置。     The semiconductor device according to claim 6.
    A second wiring formed in the first interlayer insulating film;
    The semiconductor device, wherein the first wiring is connected to the second wiring through the via.
  8. 　請求項７に記載の半導体装置において、
    　前記第２の層間絶縁膜のうち、前記第２の配線と前記第１の配線間に位置する領域のヤング率は、８ＧＰａ以上であることを特徴とする半導体装置。     The semiconductor device according to claim 7,
    A semiconductor device, wherein a Young's modulus of a region located between the second wiring and the first wiring in the second interlayer insulating film is 8 GPa or more.
  9. 　請求項６～８のうちいずれか１項に記載の半導体装置において、
    　前記第１の層間絶縁膜と前記第２の層間絶縁膜との間に形成されたバリア膜をさらに備え、
    　前記ビアは、前記第２の層間絶縁膜の下部領域、及び前記バリア膜を貫通して形成されていることを特徴とする半導体装置。     The semiconductor device according to any one of claims 6 to 8,
    A barrier film formed between the first interlayer insulating film and the second interlayer insulating film;
    The semiconductor device according to claim 1, wherein the via is formed so as to penetrate a lower region of the second interlayer insulating film and the barrier film.
  10. 　請求項６～９のうちいずれか１項に記載の半導体装置において、
    　前記第２の層間絶縁膜上に形成されたキャップ膜をさらに備え、
    　前記第１の配線は、前記第２の層間絶縁膜の上部領域、及び前記キャップ膜に形成されていることを特徴とする半導体装置。     The semiconductor device according to any one of claims 6 to 9,
    A cap film formed on the second interlayer insulating film;
    The semiconductor device according to claim 1, wherein the first wiring is formed in an upper region of the second interlayer insulating film and the cap film.
  11. 　半導体基板上に、第１の層間絶縁膜を形成する工程（ａ）と、
    　前記第１の層間絶縁膜上に、ポロジェンを含有する第２の層間絶縁膜形成用膜を形成する工程（ｂ）と、
    　前記第２の層間絶縁膜形成用膜上に、配線溝形成用溝が形成されたハードマスクを形成する工程（ｃ）と、
    　前記ハードマスクを利用して、前記第２の層間絶縁膜形成用膜のうち、前記配線溝形成用溝の近傍に位置する領域に存在するポロジェンを脱離し、ポロジェンが脱離されてなる空孔を含有する多孔質領域と、脱離されずに残存するポロジェンを含有する非多孔質領域とで構成される第２の層間絶縁膜を形成する工程（ｄ）と、
    　前記ハードマスクを利用して、前記第２の層間絶縁膜の上部領域に、第１の配線溝を形成する工程（ｅ）と、
    　前記ハードマスクを除去した後、前記第１の配線溝内に第１の配線を形成する工程（ｆ）とを備え、
    　前記工程（ｅ）において、前記第１の配線溝は、前記多孔質領域内に形成されることを特徴とする半導体装置の製造方法。     A step (a) of forming a first interlayer insulating film on the semiconductor substrate;
    Forming a second interlayer insulating film forming film containing porogen on the first interlayer insulating film (b);
    A step (c) of forming a hard mask having a wiring groove forming groove formed on the second interlayer insulating film forming film;
    Using the hard mask, the porogen formed by detaching the porogen present in the region located in the vicinity of the wiring groove forming groove in the second interlayer insulating film forming film is removed. A step (d) of forming a second interlayer insulating film composed of a porous region containing a non-porous region containing a porogen remaining without being desorbed;
    Forming a first wiring trench in an upper region of the second interlayer insulating film using the hard mask; and
    A step (f) of forming a first wiring in the first wiring groove after removing the hard mask;
    In the step (e), the first wiring groove is formed in the porous region.
  12. 　請求項１１に記載の半導体装置の製造方法において、
    　前記工程（ｂ）において、前記第２の層間絶縁膜形成用膜に含有されるポロジェンは、紫外線、又は電子線の照射により脱離するポロジェンであり、
    　前記工程（ｃ）において、前記ハードマスクは、紫外線、又は電子線を反射させる金属膜からなり、
    　前記工程（ｄ）は、前記半導体基板上に、紫外線、又は電子線を照射する工程であることを特徴とする半導体装置の製造方法。     In the manufacturing method of the semiconductor device according to claim 11,
    In the step (b), the porogen contained in the second interlayer insulating film forming film is a porogen that is desorbed by irradiation with ultraviolet rays or electron beams,
    In the step (c), the hard mask is made of a metal film that reflects ultraviolet rays or electron beams,
    The process (d) is a process for irradiating the semiconductor substrate with ultraviolet rays or an electron beam.
  13. 　請求項１２に記載の半導体装置の製造方法において、
    　前記工程（ｄ）は、
    　　前記半導体基板上に、前記半導体基板の主面に対して垂直な方向に、第１の紫外線、又は第１の電子線を照射する工程（ｄ１）と、
    　　前記半導体基板上に、前記半導体基板の主面に対して傾斜する方向に、第２の紫外線、又は第２の電子線を照射する工程（ｄ２）とを含むことを特徴とする半導体装置の製造方法。     In the manufacturing method of the semiconductor device according to claim 12,
    The step (d)
    Irradiating the semiconductor substrate with a first ultraviolet ray or a first electron beam in a direction perpendicular to the principal surface of the semiconductor substrate (d1);
    A step (d2) of irradiating the semiconductor substrate with a second ultraviolet ray or a second electron beam in a direction inclined with respect to the main surface of the semiconductor substrate. Method.
  14. 　請求項１２又は１３に記載の半導体装置の製造方法において、
    　紫外線、又は電子線を反射させる前記金属膜の材料は、Ｔｉ、ＴｉＮ、Ｔａ、ＴａＮ、Ｗ、及びＷＮからなる群から選択される１種類、又は複数種類の金属材料であることを特徴とする半導体装置の製造方法。     In the manufacturing method of the semiconductor device according to claim 12 or 13,
    The material of the metal film that reflects ultraviolet rays or electron beams is one or more kinds of metal materials selected from the group consisting of Ti, TiN, Ta, TaN, W, and WN. A method for manufacturing a semiconductor device.
  15. 　請求項１１に記載の半導体装置の製造方法において、
    　前記工程（ｂ）において、前記第２の層間絶縁膜形成用膜に含有されるポロジェンは、紫外線、又は電子線の照射により脱離するポロジェンであり、
    　前記工程（ｃ）において、前記ハードマスクは、紫外線、又は電子線を吸収する絶縁膜からなり、
    　前記工程（ｄ）は、前記半導体基板上に、紫外線、又は電子線を照射する工程であることを特徴とする半導体装置の製造方法。     In the manufacturing method of the semiconductor device according to claim 11,
    In the step (b), the porogen contained in the second interlayer insulating film forming film is a porogen that is desorbed by irradiation with ultraviolet rays or electron beams,
    In the step (c), the hard mask is made of an insulating film that absorbs ultraviolet rays or electron beams,
    The process (d) is a process for irradiating the semiconductor substrate with ultraviolet rays or an electron beam.
  16. 　請求項１５に記載の半導体装置の製造方法において、
    　紫外線、又は電子線を吸収する前記絶縁膜の材料は、ＳｉＣＮ、ＳｉＣＯ、ＳｉＣＨ、ＳｉＯＮ、ＳｉＯ2、及びＳｉＮからなる群から選択される１種類、又は複数種類の絶縁材料であることを特徴とする半導体装置の製造方法。     In the manufacturing method of the semiconductor device according to claim 15,
    The material of the insulating film that absorbs ultraviolet rays or electron beams is one or a plurality of types of insulating materials selected from the group consisting of SiCN, SiCO, SiCH, SiON, SiO 2 and SiN. A method for manufacturing a semiconductor device.
  17. 　請求項１１に記載の半導体装置の製造方法において、
    　前記工程（ｂ）において、前記第２の層間絶縁膜形成用膜に含有されるポロジェンは、熱処理により脱離するポロジェンであり、
    　前記工程（ｃ）において、前記ハードマスクは、ポロジェンが含まれない前記第１の層間絶縁膜に比べて密度の高い膜からなり、
    　前記工程（ｄ）は、前記半導体基板上の全面に対し、熱処理を施す工程であることを特徴とする半導体装置の製造方法。     In the manufacturing method of the semiconductor device according to claim 11,
    In the step (b), the porogen contained in the second interlayer insulating film forming film is a porogen desorbed by heat treatment,
    In the step (c), the hard mask is composed of a film having a higher density than the first interlayer insulating film not containing porogen,
    The method of manufacturing a semiconductor device, wherein the step (d) is a step of performing a heat treatment on the entire surface of the semiconductor substrate.
  18. 　請求項１７に記載の半導体装置の製造方法において、
    　前記ハードマスクの材料は、Ｔｉ、ＴｉＮ、Ｔａ、ＴａＮ、Ｗ、及びＷＮからなる金属材料群、並びにＳｉＣＮ、ＳｉＣＯ、ＳｉＣＨ、ＳｉＯＮ、ＳｉＯ2、及びＳｉＮからなる絶縁材料群から選択される１種類、又は複数種類の材料であることを特徴とする半導体装置の製造方法。     In the manufacturing method of the semiconductor device according to claim 17,
    The hard mask material is selected from a metal material group consisting of Ti, TiN, Ta, TaN, W, and WN, and an insulating material group consisting of SiCN, SiCO, SiCH, SiON, SiO 2 , and SiN. Or a method of manufacturing a semiconductor device, wherein the material is a plurality of types of materials.
  19. 　請求項１１～１８のうちいずれか１項に記載の半導体装置の製造方法において、
    　前記工程（ｅ）は、前記第２の層間絶縁膜の下部領域にビアホールを形成する工程をさらに含み、
    　前記工程（ｆ）は、前記ビアホール内にビアを形成する工程をさらに含み、
    　前記工程（ｅ）において、前記ビアホールは、その下部領域が前記非多孔質領域を貫通し、その上部領域が前記多孔質領域を貫通して形成されることを特徴とする半導体装置の製造方法。     The method for manufacturing a semiconductor device according to any one of claims 11 to 18,
    The step (e) further includes a step of forming a via hole in a lower region of the second interlayer insulating film,
    The step (f) further includes a step of forming a via in the via hole,
    In the step (e), the via hole is formed such that a lower region penetrates the non-porous region and an upper region penetrates the porous region.
  20. 　請求項１９に記載の半導体装置の製造方法において、
    　前記工程（ａ）の後で前記工程（ｂ）の前に、前記第１の層間絶縁膜に第２の配線溝を形成した後、前記第２の配線溝内に第２の配線を形成する工程（ｇ）をさらに備えていることを特徴とする半導体装置の製造方法。     In the manufacturing method of the semiconductor device according to claim 19,
    After the step (a) and before the step (b), a second wiring groove is formed in the first interlayer insulating film, and then a second wiring is formed in the second wiring groove. A method of manufacturing a semiconductor device, further comprising a step (g).
  21. 　請求項２０に記載の半導体装置の製造方法において、
    　前記工程（ｇ）の後で前記工程（ｂ）の前に、前記第１の層間絶縁膜、及び前記第２の配線の上にバリア膜を形成する工程（ｈ）をさらに備え、
    　前記工程（ｂ）において、前記第２の層間絶縁膜形成用膜は、前記バリア膜上に形成され、
    　前記工程（ｅ）において、前記ビアホールは、前記第２の層間絶縁膜の下部領域、及び前記バリア膜を貫通して形成されることを特徴とする半導体装置の製造方法。     In the manufacturing method of the semiconductor device according to claim 20,
    A step (h) of forming a barrier film on the first interlayer insulating film and the second wiring after the step (g) and before the step (b);
    In the step (b), the second interlayer insulating film forming film is formed on the barrier film,
    In the step (e), the via hole is formed so as to penetrate a lower region of the second interlayer insulating film and the barrier film.
  22. 　請求項２１に記載の半導体装置の製造方法において、
    　前記工程（ｂ）の後で前記工程（ｃ）の前に、前記第２の層間絶縁膜形成用膜上に、キャップ膜を形成する工程（ｉ）をさらに備え、
    　前記工程（ｃ）において、前記第２の層間絶縁膜形成用膜上に、溝が形成された前記キャップ膜、及び前記溝と連通する前記配線溝形成用溝が形成された前記ハードマスクが順次形成され、
    　前記工程（ｅ）において、前記第１の配線溝は、前記第２の層間絶縁膜の上部領域、及び前記キャップ膜に形成されることを特徴とする半導体装置の製造方法。     In the manufacturing method of the semiconductor device according to claim 21,
    A step (i) of forming a cap film on the second interlayer insulating film forming film after the step (b) and before the step (c);
    In the step (c), the hard mask in which the cap film in which the groove is formed and the wiring groove forming groove communicating with the groove are sequentially formed on the second interlayer insulating film forming film is sequentially formed. Formed,
    In the step (e), the first wiring trench is formed in an upper region of the second interlayer insulating film and in the cap film.
  23. 　請求項２２に記載の半導体装置の製造方法において、
    　前記工程（ｃ）は、
    　　前記キャップ膜上に前記ハードマスクを形成する工程（ｃ１）と、
    　　前記工程（ｃ１）の後に、前記ハードマスクに前記配線溝形成用溝を形成すると共に、前記キャップ膜に前記溝を形成する工程（ｃ２）とを含むことを特徴とする半導体装置の製造方法。     In the manufacturing method of the semiconductor device according to claim 22,
    The step (c)
    Forming the hard mask on the cap film (c1);
    After the step (c1), the method includes the step (c2) of forming the groove for forming the wiring groove in the hard mask and forming the groove in the cap film.
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