WO2010055619A1 - Frequency synthesizer, radio communication device, and radio communication device control method - Google Patents

Frequency synthesizer, radio communication device, and radio communication device control method Download PDF

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Publication number
WO2010055619A1
WO2010055619A1 PCT/JP2009/005639 JP2009005639W WO2010055619A1 WO 2010055619 A1 WO2010055619 A1 WO 2010055619A1 JP 2009005639 W JP2009005639 W JP 2009005639W WO 2010055619 A1 WO2010055619 A1 WO 2010055619A1
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Prior art keywords
signal
frequency
frequency synthesizer
amplitude
circuit
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PCT/JP2009/005639
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French (fr)
Japanese (ja)
Inventor
兒玉浩志
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日本電気株式会社
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Priority to JP2010537673A priority Critical patent/JPWO2010055619A1/en
Publication of WO2010055619A1 publication Critical patent/WO2010055619A1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/08—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
    • H03B5/12—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
    • H03B5/1206—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device using multiple transistors for amplification
    • H03B5/1212—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device using multiple transistors for amplification the amplifier comprising a pair of transistors, wherein an output terminal of each being connected to an input terminal of the other, e.g. a cross coupled pair
    • H03B5/1215—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device using multiple transistors for amplification the amplifier comprising a pair of transistors, wherein an output terminal of each being connected to an input terminal of the other, e.g. a cross coupled pair the current source or degeneration circuit being in common to both transistors of the pair, e.g. a cross-coupled long-tailed pair
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/08—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
    • H03B5/12—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
    • H03B5/1237—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device comprising means for varying the frequency of the generator
    • H03B5/124—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device comprising means for varying the frequency of the generator the means comprising a voltage dependent capacitance
    • H03B5/1246—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device comprising means for varying the frequency of the generator the means comprising a voltage dependent capacitance the means comprising transistors used to provide a variable capacitance
    • H03B5/1253—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device comprising means for varying the frequency of the generator the means comprising a voltage dependent capacitance the means comprising transistors used to provide a variable capacitance the transistors being field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/08—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
    • H03B5/12—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
    • H03B5/1237—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device comprising means for varying the frequency of the generator
    • H03B5/1262—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device comprising means for varying the frequency of the generator the means comprising switched elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K25/00—Pulse counters with step-by-step integration and static storage; Analogous frequency dividers
    • H03K25/02—Pulse counters with step-by-step integration and static storage; Analogous frequency dividers comprising charge storage, e.g. capacitor without polarisation hysteresis
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L5/00—Automatic control of voltage, current, or power
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/095—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using a lock detector

Definitions

  • the present invention relates to a PLL frequency synthesizer, and more particularly to control of an output signal amplitude of a voltage controlled oscillator (VCO) included in the PLL frequency synthesizer.
  • VCO voltage controlled oscillator
  • a PLL (Phase Locked Loop) frequency synthesizer (hereinafter simply referred to as a frequency synthesizer) is a voltage controlled oscillator (VCO) and a PLL (Phase Locked Loop) for locking the oscillation frequency of the VCO to a desired frequency.
  • VCO voltage controlled oscillator
  • PLL Phase Locked Loop
  • FIG. 24 is a block diagram illustrating a basic configuration example of a frequency synthesizer.
  • the frequency synthesizer 8 shown in FIG. 24 has a VCO 80 and a PLL circuit for locking the oscillation frequency of the VCO 80.
  • the PLL circuit includes a frequency divider 11, a phase / frequency comparator 12, a charge pump 13, and a low-pass filter (LPF: Low Pass Filter) 14.
  • LPF Low Pass Filter
  • the VCO 80 oscillates at a frequency according to the control voltage supplied from the LPF 14 driven by the charge pump 13.
  • the phase / frequency comparator 12 detects the phase difference between the signal obtained by dividing the oscillation frequency of the VCO 80 by the divider 11 and the reference clock signal F_REF.
  • the charge pump 13 converts the output of the phase / frequency comparator 12 into a direct current. That is, the charge pump 13 injects or extracts a current pulse from the LPF 14 in accordance with the detection result of the phase difference by the phase / frequency comparator 12. For example, when the phase of the reference clock signal F_REF is ahead of the phase of the output signal of the frequency divider 11, the charge pump pours current pulses.
  • control voltage of the VCO 80 and the oscillation frequency are in a monotonically increasing relationship.
  • the current pulse generated by the charge pump 13 is smoothed by the LPF 14 and supplied to the VCO 80 as an updated control voltage.
  • the phase difference between the output signal of the frequency divider 11 and the reference clock signal F_REF gradually approaches zero, and the output frequency of the VCO is locked.
  • the frequency synthesizer 8 shown in FIG. 24 uses a local (clock) signal for an up-converter and a down-converter in a wireless transceiver as a supply source.
  • the output signal of the VCO 80 is supplied to both converters via the buffer 15.
  • FIG. 25 is a diagram illustrating a transmission path of spurious generated from the frequency synthesizer 8 when the frequency synthesizer 8 is applied to a wireless transmitter.
  • the spurious transmission path from the frequency synthesizer 8 is broadly divided into a direct transmission path (dotted line in FIG. 25) and an indirect transmission path (dashed line in FIG. 25).
  • the direct transmission path is a path that is directly transmitted to the output of the transmission amplifier 84 supplied to the antenna 85.
  • the indirect transmission path is a path that is transmitted to a block preceding the input of the transmission amplifier 84, that is, the analog baseband unit 82 and the up converter (mixer) 83.
  • FIG. 26A shows a transmission spectrum when the wireless transmitter shown in FIG. 25 performs signal transmission at a transmission power of about ⁇ 40 dBm / MHz.
  • FIG. 26B shows a transmission spectrum when the radio transmitter shown in FIG. 25 performs signal transmission with extremely weak power of about ⁇ 70 dBm / MHz.
  • very weak power communication mode a communication mode in which signal transmission is performed with extremely weak power
  • a communication mode in which signal transmission is performed with a sufficiently high transmission power (for example, transmission power of about ⁇ 70 dBm / MHz) compared to the extremely weak power communication mode is referred to as a “normal power communication mode”.
  • transmission power is large, so long distance transmission is possible.
  • the extremely weak power communication mode since the transmission power is small, the communicable distance is limited to be short, but the frequency limitation by the Japanese radio law is relaxed.
  • the spurious level including the spurious via the direct transmission path can always be kept small.
  • the gains of the up-converter 83 and the reception down-converter (not shown) in the normal power communication mode are reduced, the transmission / reception performance is deteriorated.
  • the power of the VCO 80, which is the main spurious source is designed to be small, the spurious level can always be reduced similarly.
  • the phase noise caused by the VCO 80 is increased, the transmission / reception performance is also deteriorated.
  • An object of the present invention is to provide a frequency synthesizer capable of suppressing deterioration of transmission performance when applied to a wireless communication apparatus capable of switching transmission power and performing transmission with extremely weak power. To do.
  • the frequency synthesizer includes a voltage controlled oscillator, a PLL circuit, and a first control circuit.
  • the voltage controlled oscillator can change the oscillation frequency according to the frequency control voltage, and can change the output signal amplitude according to the amplitude control signal.
  • the PLL circuit generates the frequency control voltage according to a comparison result between an output signal of the voltage controlled oscillator or a signal obtained by dividing the output signal and a reference frequency signal.
  • the first control circuit supplies the amplitude control signal to the voltage controlled oscillator, and controls the voltage controlled oscillator so that the output signal amplitude has a magnitude corresponding to a mode switching signal supplied from the outside. .
  • the wireless communication apparatus includes the above-described frequency synthesizer according to the first aspect of the present invention. Further, the wireless communication apparatus includes a mixer that performs frequency conversion of a communication signal using an output signal of the frequency synthesizer as a local oscillation signal, and a control unit that supplies the mode switching signal to the frequency synthesizer. The said control part produces
  • a method is a control method for a wireless communication apparatus including a frequency synthesizer and a mixer that performs frequency conversion of a communication signal using an output signal of the frequency synthesizer as a local oscillation signal.
  • the method is (A) generating a mode switching signal in response to mode switching between a plurality of communication modes having different transmission powers of the communication signal; and (b) supplying the mode switching signal to the frequency synthesizer. Changing the magnitude of the output signal amplitude of the voltage controlled oscillator included in the synthesizer in accordance with the magnitude of the transmission power of the communication signal.
  • a frequency synthesizer capable of suppressing deterioration in transmission performance when applied to a wireless communication apparatus capable of switching transmission power and performing transmission with extremely weak power.
  • a wireless communication apparatus capable of switching transmission power performs transmission with extremely weak power.
  • FIG. 1 is a block diagram showing a configuration of a frequency synthesizer 1 according to the present embodiment.
  • the frequency synthesizer 1 includes a VCO 10 and a PLL circuit 18 for locking the oscillation frequency of the VCO 10.
  • the PLL circuit 18 includes a frequency divider 11, a phase / frequency comparator 12, a charge pump 13, and an LPF 14.
  • the configuration of the PLL circuit 18 is the same as that of the general frequency synthesizer 8 shown in FIG.
  • the frequency synthesizer 1 further has a feedback loop for controlling the output signal amplitude of the VCO 10.
  • the feedback loop includes an amplitude control circuit 16.
  • the amplitude control circuit 16 monitors the output signal amplitude of the VCO 10, repeatedly generates an amplitude control signal so that the output signal amplitude of the VCO 10 approaches a predetermined target value, and supplies the amplitude control signal to the VCO 10.
  • the VCO 10 has a configuration for changing the output signal amplitude according to the amplitude control signal from the amplitude control circuit 16 in addition to the configuration for changing the oscillation frequency according to the control voltage supplied from the LPF 14. .
  • the configuration example of FIG. 1 includes a reference signal generation circuit 17 in order to provide the amplitude control circuit 16 with a reference signal V_REF that defines a target level of the output signal amplitude.
  • the reference signal generation circuit 17 receives a control signal CODE_REF that specifies V_REF, and switches the magnitude of V_REF in accordance with the control signal CODE_REF.
  • the reference signal generation circuit 17 may be provided with two types of CODE_REF corresponding to the above-described normal power communication mode and extremely weak power transmission mode.
  • the reference signal generation circuit 17 may output V_REF corresponding to the normal power communication mode or V_REF corresponding to the extremely weak power transmission mode in accordance with CODE_REF. That is, the control signal CODE_REF is a signal indicating mode switching between a plurality of communication modes having different transmission powers.
  • FIG. 2 is a circuit diagram showing one specific example of the VCO 10.
  • Cross-coupled N-channel MOS transistors M1 and M2 and cross-coupled P-channel MOS transistors M3 and M4 operate as negative resistors, respectively.
  • Inductor 100, varactors 101 and 102, and capacitor array 103 form a resonant circuit.
  • the varactors 101 and 102 as variable capacitance elements change their capacitances according to the magnitude of the control voltage VCTRL supplied from the LPF 14 and change the oscillation frequency of the VCO 10.
  • the capacitor array 103 is used for offset adjustment with respect to the oscillation center frequency of the VCO 10.
  • Each switch included in the capacitor array 103 operates according to a control signal CODE_F0 supplied from the outside.
  • the control signal CODE_F0 may be generated by a control unit included in a wireless communication apparatus to which the frequency synthesizer 1 is applied.
  • the switch-equipped MOS array including the switches 104 to 106 and the N-channel MOS transistors M5 to M7 operates as a current source, and the amount of bias current can be changed according to the amplitude control signal CODE_AMP.
  • the switches 104 to 106 operate according to the amplitude control signal CODE_AMP generated by the amplitude control circuit 16 and control the supply of the bias voltage VBIAS to the gates of the transistors M5 to M7. For example, if the size of the transistor M6 is twice that of M5 and the size of M7 is 4 times that of M5, the amount of bias current is switched stepwise by the amplitude control signal CODE_AMP that is a binary code, and the output signal amplitude of the VCO 10 is also changed. Switch in stages. Note that the transistors M5 to M7 may have the same size and the amplitude control signal CODE_AMP may be a thermometer code.
  • the circuit configuration of the VCO 10 shown in FIG. 2 is merely an example.
  • the capacitor array 103 may be omitted.
  • the VCO 10 may be configured without including the P-channel MOS cross couples M3 and M4.
  • the number of transistors M5 to M7 for adjusting the bias current is an example.
  • FIG. 3 shows another circuit example of the VCO 10.
  • the P-channel MOS cross couples M3 and M4 are omitted.
  • the capacitor array 103 is composed of a plurality of varactors. Further, a transistor M8 and a switch 107 are added for adjusting the bias current.
  • FIG. 4 is a block diagram showing one specific configuration example of the amplitude control circuit 16.
  • the peak detection circuit 160 detects the peak level (that is, amplitude) of the reference signal V_REF that determines the target value of the output signal amplitude.
  • the peak detection circuit 161 detects the peak level of the output signal of the VCO 10.
  • the comparator 162 compares the amplitude of the reference signal V_REF with the amplitude of the output signal of the VCO.
  • the output signal of the comparator 162 is calculated by the control logic circuit 163 and then supplied to the VCO 10 as the amplitude control signal CODE_AMP.
  • each signal before the input to the comparator 162 is an analog signal
  • each signal after the output of the comparator 162 is a digital signal.
  • FIG. 4 is merely an example.
  • an operational amplifier 164 may be used instead of the comparator 162 as shown in FIG.
  • the output signal amplitude of the VCO 10 is controlled only with an analog signal.
  • FIG. 5A and 5B are waveform diagrams showing the operation of the amplitude control circuit 16 shown in FIG.
  • FIG. 5A shows a case where the output signal amplitude of the VCO 10 is larger than the reference signal V_REF. In this case, the comparator 162 outputs “1”.
  • FIG. 5B shows a case where the output signal amplitude of the VCO 10 is smaller than the reference signal V_REF. In this case, the comparator 162 outputs “0”.
  • Using a 1-bit comparator in this way is suitable for a fine CMOS process with a narrow dynamic range and low accuracy. In addition, it is suitable for a fine CMOS process because it can be processed with digital signals as much as possible.
  • An A / D converter may be used instead of the 1-bit comparator.
  • the output signal amplitude of the VCO 10 may be controlled by an analog signal as shown in FIG.
  • the control signal CODE_REF is switched from a value corresponding to the “very weak power mode” to a value corresponding to the “normal power mode”
  • the control signal CODE_REF indicates the extremely weak power mode.
  • the reference signal V_REF corresponding to the extremely weak power mode is generated by the reference signal generation circuit 17.
  • the amplitude control signal CODE_AMP is a 3-bit signal, and it is assumed that the output signal amplitude of the VCO 10 monotonously increases with respect to the value of CODE_AMP.
  • the output signal amplitude of the VCO 10 is the minimum value when the value of “CODE_AMP” is “000”, and the maximum value of “111.” Further, the current source (transistors M5 to M7) of the amplitude control signal CODE_AMP. Assume that the amount of current is controlled by a binary code.
  • the amplitude control signal CODE_AMP is set to “111”.
  • the comparison result of the comparator 162 is “1”.
  • the amplitude control signal CODE_AMP in the next cycle is changed to “110”.
  • the control logic circuit 163 can be realized by a subtraction circuit.
  • the output signal amplitude of the VCO 10 decreases by one step.
  • the comparison result of the comparator 162 converges to “0” when the amplitude control signal CODE_AMP is “100” (time T4).
  • the reference signal V_R is set high. Further, the value of the amplitude control signal CODE_AMP is initialized to “111” in accordance with the reset signal (FIG. 7G). Then, the operation as described above is performed.
  • the reset signal in FIG. 7G may be supplied to the amplitude control circuit 16 from an external circuit or the reference signal generation circuit 17. Further, the amplitude control circuit 16 may be configured to perform a reset operation in accordance with the change of the reference signal V_REF.
  • FIG. 7 shows an example in which the output signal amplitude of the VCO 10 is converged to a desired magnitude by setting the maximum value of the amplitude control signal CODE_AMP as an initial value and gradually decreasing the value of the amplitude control signal CODE_AMP from the initial value. It was. However, such a method is only an example. For example, the minimum value of the amplitude control signal CODE_AMP may be set to an initial value, and the value of the amplitude control signal CODE_AMP may be gradually increased from the initial value. Further, the convergence value of the amplitude control signal CODE_AMP may be searched using a known search method such as binary search. By using a search method such as binary search, the convergence time can be shortened.
  • a search method such as binary search
  • the magnitude of the reference signal V_REF serving as a reference for the output signal amplitude of the VCO 10 may be determined based on the allowable value of the phase noise of the VCO 10 and the allowable value of the spurious power.
  • the allowable value of the phase noise of the VCO 10 and the allowable value of the spurious power are determined in consideration of the transmission speed, occupied bandwidth, and desired CNR (Carrier to Noise Ratio) at the system design stage of the wireless communication apparatus to which the frequency synthesizer 1 is applied. It is determined.
  • FIG. 8 is a diagram showing a relationship between the allowable value L_PN of the phase noise of the VCO 10 and the output signal amplitude in the normal power communication mode. As shown in FIG. 8, it is known that the phase noise of the VCO 10 has a downwardly convex characteristic. At this time, in order to increase the gain of up-conversion and down-conversion, the amplitude of the VCO 10 should be as large as possible within the allowable amplitude range (V1 to V2).
  • FIG. 9 is a diagram showing the relationship between the phase noise allowable value L_PN of the VCO 10 and the output signal amplitude in the extremely weak power communication mode. Further, FIG. 9 shows the relationship between the spurious power caused by the VCO 10 and the output signal amplitude of the VCO 10 by a dotted line graph. In general, since the current and the output signal amplitude are in a proportional relationship, the amplitude of the VCO 10 and the spurious power are in a monotonically increasing relationship. In FIG. 9, it is assumed that the allowable value L_PN of the phase noise is the same as that in FIG.
  • the allowable amplitude range of the VCO 10 is limited not only by the allowable value L_PN of the phase noise but also by the allowable value L_SP of the spurious power.
  • the allowable amplitude range of the VCO 10 is a range of V1 to V3. Therefore, it is necessary to reduce the amplitude of the VCO 10 in the extremely weak power communication mode as compared with the signal transmission or reception in the normal power communication mode. If the amplitude of the VCO 10 is too small, the spurious power is reduced, but the phase noise is greatly deteriorated.
  • the output signal amplitude of the VCO 10 is set as large as possible within the allowable amplitude range V1 to V2, and in the extremely weak power communication mode, the output of the VCO 10 is set.
  • the signal amplitude may be limited within the amplitude range V1 to V3.
  • the frequency synthesizer 1 according to the present embodiment can easily change the output signal amplitude of the VCO 10 in accordance with the communication mode switching. Further, since the feedback loop including the amplitude control circuit 16 monitors the output signal amplitude of the VCO 10 and locks the output signal amplitude of the VCO 10 to a desired level, the frequency synthesizer 1 can stabilize the output signal amplitude of the VCO 10.
  • FIG. 10 is a block diagram showing a configuration example of a wireless communication apparatus to which the frequency synthesizer 1 according to the present embodiment is applied.
  • the frequency synthesizer 1 generates a local oscillation signal (local signal) supplied to the orthogonal mixers 183 and 190 for transmission and reception.
  • the control unit 180 supplies the frequency synthesizer 1 with a control signal CODE_F0 for designating an offset with respect to the oscillation center frequency F0 of the VCO 10 and a control signal CODE_REF for designating a communication mode.
  • the digital baseband processing unit 181 performs encoding processing, baseband modulation processing, and the like on the transmission signal.
  • the D / A converter 182 converts the transmission signal into an analog signal and supplies it to the orthogonal mixer 183.
  • the orthogonal mixer 183 generates a transmission signal in the carrier frequency band by multiplying the local signal generated by the frequency synthesizer 1 and the analog baseband signal.
  • the transmission signal in the carrier frequency band generated by the orthogonal mixer 183 is supplied to the transmission power amplifier 185 via the band pass filter 184.
  • the transmission power amplifier 185 amplifies the transmission signal and outputs it to the antenna 187 via the duplexer 186.
  • the signal received by the antenna 187 is supplied to the orthogonal mixer 190 via the low noise amplifier 188 and the band pass filter 189.
  • the orthogonal mixer 190 multiplies the local signal generated by the frequency synthesizer 1 and the received signal, thereby down-converting to the baseband.
  • the reception signal down-converted by the orthogonal mixer 190 is supplied to the A / D converter 192 via the low-pass filter 191.
  • the digital baseband processing unit 181 performs demodulation processing and decoding processing using the received signal data sequence sampled by the A / D converter 192.
  • the wireless communication apparatus of FIG. 10 is merely an example of an application destination of the frequency synthesizer 1.
  • the reception method of the apparatus of FIG. 10 is a direct conversion method, but may be a superheterodyne method or a low IF method.
  • the application destination of the frequency synthesizer 1 may be a radio communication device dedicated to transmission or a radio communication device dedicated to reception.
  • FIG. 11 is a block diagram showing the configuration of the frequency synthesizer 2 according to the present embodiment.
  • the frequency synthesizer 2 includes a register circuit 28 that captures and holds the amplitude control signal CODE_AMP output from the amplitude control circuit 26.
  • the control signal CODE_REF instructing switching of the communication mode is supplied to the register circuit 28, and the value of the amplitude control signal CODE_AMP corresponding to the communication mode specified by the control signal CODE_REF is output from the register circuit 28. Is done.
  • the amplitude control circuit 26 supplies the value of the amplitude control signal CODE_AMP output from the register circuit 28 to the VCO 10 in response to the control signal CODE_REF.
  • FIG. 12 is a diagram illustrating a specific circuit example of the amplitude control circuit 26.
  • the amplitude control circuit 26 shown in FIG. 12 has a switch 264 in addition to the configuration of the amplitude control circuit 16 shown in FIG.
  • the switch 264 has a first connection state for supplying the output of the control logic circuit 163 to the VCO 10, a second connection state for supplying the output of the control logic circuit 163 to the register circuit 28, and an output of the register circuit 28 to the VCO 10.
  • the connection state can be changed between the third connection states to be supplied.
  • the output of the control logic circuit 163 and the output of the register circuit 28 are complementarily supplied to the VCO 10 as an amplitude control signal.
  • the on / off operations of the peak detection circuits 160 and 161, the comparator 162, and the control logic circuit 163 are controlled by a switching signal EN_AAC instructing execution / stop of automatic amplitude control.
  • the signal for controlling the switching of the switch 264 and the switching signal EN_AAC may be supplied to the amplitude control circuit 26 from the control unit of the wireless communication apparatus to which the frequency synthesizer 2 is applied, for example.
  • FIG. 13 is a waveform diagram showing a specific example of the operation of the frequency synthesizer 2.
  • the automatic amplitude control switching signal EN_AAC is “1”
  • the optimum value of the amplitude control signal CODE_AMP for each communication mode is determined by the same procedure as described in the first embodiment.
  • the optimum amplitude control signal in the very weak power communication mode is determined to be “100” by the operation from time T1 to T4. Further, it is assumed that the normal power communication mode is already determined as “110”.
  • the value of the amplitude control control signal optimum for each communication mode is held in the register circuit 28.
  • the frequency synthesizer 2 can switch the amplitude of the VCO 10 at a higher speed than the frequency synthesizer 1 after the optimum amplitude control signal value is held in the register circuit 28. At this time, the power required for the operation of the amplitude control circuit 26 can be reduced.
  • FIG. 11 shows a configuration in which the control signal CODE_REF is supplied to the register circuit 28.
  • a circuit that generates an address signal for selecting one register element from the plurality of register elements included in the register circuit based on the control signal CODE_REF may be further provided.
  • the register circuit 28 has, for example, a plurality of register elements each capable of holding the value of one amplitude control signal CODE_AMP, and a decode circuit that decodes the address signal and selects one register element. That's fine. Even with such a configuration, the value of the amplitude control signal CODE_AMP held in one register element included in the register circuit 28 can be read by supplying the address signal to the register circuit 28.
  • FIG. 14 is a block diagram showing the configuration of the frequency synthesizer 3 according to the present embodiment.
  • the frequency synthesizer 3 includes a lock determination circuit 38 and a control logic circuit 39 in addition to the configuration of the frequency synthesizer 1 described above.
  • the lock determination circuit 38 compares and determines at least one of the frequency difference and the phase difference between the output signal from the frequency divider 31 and the reference clock signal F_REF.
  • the control logic circuit 39 outputs a sensitivity control signal CODE_SENS that calculates the determination result of the lock determination circuit 38 and controls the sensitivity characteristic of the frequency divider 31.
  • FIG. 15 is a circuit diagram showing a specific configuration example of the variable sensitivity frequency divider 31.
  • DFF D flip-flops
  • a switch capacitor array 312 is disposed between the DFFs 310 and 311.
  • the capacitance connected between the DFFs 310 and 311 is changed by turning on / off each switch in the switch capacitance array 312 according to the sensitivity control signal CODE_SENS. Thereby, the free run frequency of the frequency divider 31 is switched. Even in configurations other than the four-frequency divider, the free-run frequency of the frequency divider 31 can be switched by arranging the switch capacitor array 312 as in FIG.
  • FIG. 16 is a reference graph showing a general frequency characteristic of a fixed sensitivity frequency divider for comparison.
  • the amplitude of the VCO 10 is large, even if the sensitivity characteristic of the frequency divider is convex downward, the characteristic shown in FIG.
  • the frequency region in which the frequency dividing operation can be performed is narrowed.
  • the frequency region in which the frequency division operation is possible is limited between F11 and F12. For example, this is particularly a problem when the frequency must be generated over a wide range, such as a frequency synthesizer for UWB (Ultra Wide Band).
  • FIG. 17 is a graph showing the frequency characteristics of the variable sensitivity frequency divider 31 shown in FIG.
  • the frequency range is changed to an operable frequency region F21 to F22).
  • the frequency divider 31 can operate normally.
  • FIG. 18 is a circuit diagram showing another configuration example of the sensitivity variable frequency divider 31.
  • the connection relationship between the DFFs 310 and 311 is the same as in FIG. For this reason, the frequency of the output signal of the input VCO 10 is divided by four.
  • a variable gain amplifier 313 is arranged in front of the clock terminals of the DFFs 310 and 311.
  • the variable gain amplifier 313 amplifies the output signal of the VCO 10 input to the clock terminals of the DFFs 310 and 311.
  • the gain of the variable gain amplifier 313 is switched according to the sensitivity control signal CODE_SENS. According to the configuration of FIG. 17, even if the frequencies input to the clock terminals of the DFFs 310 and 311 are the same, the input sensitivity characteristic of the frequency divider 31 can be switched by adjusting the gain of the variable gain amplifier 313.
  • FIG. 19 is a graph showing the frequency characteristics of the variable sensitivity frequency divider 31 shown in FIG.
  • the variable gain amplifier 313 is changed to a high gain, the frequency characteristic (frequency division) indicated by the thick solid curve L5 from the frequency characteristic indicated by the broken curve L1 (frequency regions F11 to F12 in which frequency division operation is possible) in FIG.
  • the operating frequency range F31 to F32) is changed. Since the characteristic graph is lowered along the amplitude axis, the frequency divider 31 can operate normally even by the small amplitude output of the VCO 10 in the weak power communication mode.
  • FIG. 20 is a waveform diagram showing a specific example of the operation of the frequency synthesizer 3.
  • the process is executed until the amplitude control loop of the VCO 10 converges.
  • an input sensitivity control loop of the frequency divider 31 is started (time T5).
  • the initial setting value of the sensitivity control signal CODE_SENS is “000”.
  • the determination result LD of the lock determination circuit 38 is “0”.
  • the frequency divider 31 is not operating normally, and the value of the next sensitivity control signal CODE_SENS is changed to “001” (time T6). Also at time T6, since the determination result LD of the lock determination circuit 38 is “0”, the value of the next sensitivity control signal CODE_SENS is further changed to “010” (time T7). At time T7, the determination result LD of the lock determination circuit 38 is “1”. That is, it is determined that the frequency divider 31 is operating normally, and the input sensitivity control loop of the frequency divider 31 ends.
  • FIG. 20 shows an example in which the sensitivity adjustment of the frequency divider 31 is performed by setting the minimum value “000” of the sensitivity control signal CODE_SENS as an initial value and gradually increasing the value of the sensitivity control signal CODE_SENS from the initial value.
  • a method is only an example.
  • the maximum value of the sensitivity control signal CODE_SENS may be set to an initial value, and the value of the sensitivity control signal CODE_SENS may be gradually decreased from the initial value.
  • the convergence value of the sensitivity control signal CODE_SENS may be searched using a known search method such as binary search.
  • this embodiment can be combined with the second embodiment described above.
  • a register circuit capable of storing / reading the optimum value of the sensitivity control signal CODE_SENS by applying the configuration in which the register circuit 28 for storing the optimum value of the amplitude control signal CODE_AMP described in the second embodiment is applied. You may arrange. Thereby, high-speed communication mode switching becomes possible. This is particularly effective when a plurality of frequency synthesizer lock frequencies are required, such as UWB.
  • the frequency synthesizer 3 can operate in a wider oscillation frequency range than the frequency synthesizer 1 described above even when the output of the VCO 10 has a small amplitude in the extremely weak power communication mode.
  • FIG. 21 is a block diagram showing a configuration of the frequency synthesizer 4 according to the present embodiment.
  • the frequency synthesizer 4 includes amplitude control circuits 41 to 44 and reference signal generation circuits 45 to 48 for the frequency divider 11, the phase / frequency comparator 12, the charge pump 13, and the buffer 15. Have.
  • the output signal amplitude of each block is changed according to the control signal CODE_REF instructing switching of the communication mode. Note that the amplitudes of the blocks do not necessarily match.
  • FIG. 22 shows a configuration example of the amplitude control circuit 41 using a linear voltage regulator using the operational amplifier 410.
  • the circuit configuration of FIG. 22 can be applied to the other amplitude control circuits 42 to 44.
  • the frequency synthesizer 4 has an advantage that it can adjust spurious generated in a circuit block other than the VCO 10 as compared with the frequency synthesizer 1 described above.
  • FIG. 23 is a block diagram showing a configuration of the frequency synthesizer 5 according to the present embodiment.
  • the frequency synthesizer 5 includes, in addition to the configuration of the frequency synthesizer 3 described above, an amplitude control circuit 41 to 44 and a reference signal generation circuit 45 to 48 for the frequency divider 31, the phase / frequency comparator 12, the charge pump 13, and the buffer 15. Have.
  • the output signal amplitude of each block is changed according to the control signal CODE_REF instructing switching of the communication mode. Note that the amplitudes of the blocks do not necessarily match.
  • the frequency synthesizer 5 has an advantage that the spurious generated in the circuit block other than the VCO 10 can be adjusted as compared with the frequency synthesizer 3 described above.
  • the PLL circuit configuration for locking the oscillation frequency of the VCO 10 described in the above embodiments is merely an example. It is already well known that the PLL for locking the oscillation frequency of the VCO 10 can be variously modified. The present invention is applicable to frequency synthesizers having various known PLLs.

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Abstract

Provided is a frequency synthesizer which can suppress degradation of the transmission performance when applied to a radio communication device which can switch the transmission power from one to another and execute transmission with an ultra weak power.  The frequency synthesizer (1) includes a VCO (10), a PLL circuit (18), and a first control circuit (an amplification control circuit (16) and a reference signal generation circuit (17)).  The VCO (10) can modify the oscillation frequency in accordance with the frequency control voltage and modify the output signal width in accordance with an amplitude control signal.  The PLL circuit (18) generates a frequency control voltage in accordance with a result of comparison between a signal obtained by dividing the output signal of the VCO (10) and a reference frequency signal.  Moreover, the first control circuit (circuits 16 and 17) supplies the amplitude control signal to the VCO (10) and controls the VCO (10) so that the output signal amplitude has a value corresponding to a mode switching signal (control signal CODE_REF) to which the output signal amplitude is supplied from outside.

Description

周波数シンセサイザ、無線通信装置、及び無線通信装置の制御方法Frequency synthesizer, radio communication apparatus, and radio communication apparatus control method
　本発明は、ＰＬＬ周波数シンセサイザに関し、特にＰＬＬ周波数シンセサイザに含まれる電圧制御発振器（ＶＣＯ）の出力信号振幅の制御に関する。 The present invention relates to a PLL frequency synthesizer, and more particularly to control of an output signal amplitude of a voltage controlled oscillator (VCO) included in the PLL frequency synthesizer.
　ＰＬＬ（Phase Locked Loop）周波数シンセサイザ（以下、単に周波数シンセサイザと呼ぶ）は、電圧制御発振器（ＶＣＯ：voltage controlled oscillator）と、ＶＣＯの発振周波数を所望の周波数にロックするためのＰＬＬ（Phase Locked Loop）回路を有する（例えば特許文献１～３を参照）。図２４は、周波数シンセサイザの基本的な構成例を示すブロック図である。図２４に示す周波数シンセサイザ８は、ＶＣＯ８０と、ＶＣＯ８０の発振周波数をロックするためのＰＬＬ回路を有する。当該ＰＬＬ回路には、分周器１１、位相・周波数比較器１２、チャージポンプ１３及びローパスフィルタ（ＬＰＦ：Low Pass Filter）１４が含まれる。 A PLL (Phase Locked Loop) frequency synthesizer (hereinafter simply referred to as a frequency synthesizer) is a voltage controlled oscillator (VCO) and a PLL (Phase Locked Loop) for locking the oscillation frequency of the VCO to a desired frequency. A circuit (see, for example, Patent Documents 1 to 3). FIG. 24 is a block diagram illustrating a basic configuration example of a frequency synthesizer. The frequency synthesizer 8 shown in FIG. 24 has a VCO 80 and a PLL circuit for locking the oscillation frequency of the VCO 80. The PLL circuit includes a frequency divider 11, a phase / frequency comparator 12, a charge pump 13, and a low-pass filter (LPF: Low Pass Filter) 14.
　ＶＣＯ８０は、チャージポンプ１３によって駆動されるＬＰＦ１４から供給される制御電圧に従う周波数で発振する。位相・周波数比較器１２は、分周器１１によりＶＣＯ８０の発振周波数が分周された信号と参照クロック信号Ｆ＿ＲＥＦとの位相差を検出する。チャージポンプ１３は、位相・周波数比較器１２の出力を直流に変換する。つまり、チャージポンプ１３は、位相・周波数比較器１２による位相差の検出結果に応じて、ＬＰＦ１４に対する電流パルスの注ぎ込み又は引き抜きを行う。例えば、参照クロック信号Ｆ＿ＲＥＦの位相が分周器１１の出力信号の位相より進んでいる場合には、チャージポンプは電流パルスの注ぎ込みを行う。なお、ここでは、ＶＣＯ８０の制御電圧と発振周波数が単調増加の関係にあると仮定している。チャージポンプ１３により生成される電流パルスは、ＬＰＦ１４により平滑化され、更新された制御電圧としてＶＣＯ８０に供給される。このような処理過程が繰り返されることで、分周器１１の出力信号と参照クロック信号Ｆ＿ＲＥＦとの位相差がゼロに漸近し、ＶＣＯの出力周波数がロックされる。 The VCO 80 oscillates at a frequency according to the control voltage supplied from the LPF 14 driven by the charge pump 13. The phase / frequency comparator 12 detects the phase difference between the signal obtained by dividing the oscillation frequency of the VCO 80 by the divider 11 and the reference clock signal F_REF. The charge pump 13 converts the output of the phase / frequency comparator 12 into a direct current. That is, the charge pump 13 injects or extracts a current pulse from the LPF 14 in accordance with the detection result of the phase difference by the phase / frequency comparator 12. For example, when the phase of the reference clock signal F_REF is ahead of the phase of the output signal of the frequency divider 11, the charge pump pours current pulses. Here, it is assumed that the control voltage of the VCO 80 and the oscillation frequency are in a monotonically increasing relationship. The current pulse generated by the charge pump 13 is smoothed by the LPF 14 and supplied to the VCO 80 as an updated control voltage. By repeating such a process, the phase difference between the output signal of the frequency divider 11 and the reference clock signal F_REF gradually approaches zero, and the output frequency of the VCO is locked.
　図２４に示した周波数シンセサイザ８は、例えば、無線送受信器内のアップコンバータ及びダウンコンバータに対するローカル（クロック）信号を供給源として使用される。この場合、ＶＣＯ８０の出力信号は、バッファ１５を介して両コンバータに供給される。 For example, the frequency synthesizer 8 shown in FIG. 24 uses a local (clock) signal for an up-converter and a down-converter in a wireless transceiver as a supply source. In this case, the output signal of the VCO 80 is supplied to both converters via the buffer 15.
特開２００５－７２８７５号公報JP 2005-72875 A 特開２００７－４９２７７号公報JP 2007-49277 A 特開平７－１７７０２８号公報Japanese Patent Laid-Open No. 7-177028
　従来の周波数シンセサイザは、周波数シンセサイザから発生されるスプリアス信号の電力の調整が困難であるという問題を有する。図２５は、周波数シンセサイザ８を無線送信機に適用した場合に、周波数シンセサイザ８から発生されるスプリアスの伝達経路を示す図である。周波数シンセサイザ８からのスプリアスの伝達経路は、直接伝達経路（図２５の点線）と間接伝達経路（図２５の破線）の２つに大別される。直接伝達経路は、アンテナ８５に供給される送信アンプ８４の出力に直接伝達される経路である。一方、間接伝達経路は、送信アンプ８４の入力より前段のブロック、つまりアナログベースバンド部８２やアップコンバータ（ミキサ）８３に伝達される経路である。 The conventional frequency synthesizer has a problem that it is difficult to adjust the power of the spurious signal generated from the frequency synthesizer. FIG. 25 is a diagram illustrating a transmission path of spurious generated from the frequency synthesizer 8 when the frequency synthesizer 8 is applied to a wireless transmitter. The spurious transmission path from the frequency synthesizer 8 is broadly divided into a direct transmission path (dotted line in FIG. 25) and an indirect transmission path (dashed line in FIG. 25). The direct transmission path is a path that is directly transmitted to the output of the transmission amplifier 84 supplied to the antenna 85. On the other hand, the indirect transmission path is a path that is transmitted to a block preceding the input of the transmission amplifier 84, that is, the analog baseband unit 82 and the up converter (mixer) 83.
　図２５に示した無線送信機が、極微弱電力通信（例えば送信電力－７０ｄＢｍ／ＭＨｚ以下）を行う場合、上記の２つの主要な伝達経路のうち直接経路によるスプリアスが特に問題となる。図２６Ａは、図２５に示した無線送信機が、送信電力－４０ｄＢｍ／ＭＨｚ程度で信号送信を行う場合の送信スペクトラムを示している。一方、図２６Ｂは、図２５に示した無線送信機が、送信電力－７０ｄＢｍ／ＭＨｚ程度の極微弱電力で信号送信を行う場合の送信スペクトラムを示している。なお、以下では、極微弱電力で信号送信を行う通信モードを「極微弱電力通信モード」と呼ぶ。また、極微弱電力通信モードに比べて十分に大きい送信電力（例えば送信電力－７０ｄＢｍ／ＭＨｚ程度）で信号送信を行う通信モードを「通常電力通信モード」と呼ぶ。通常電力通信モードでは、送信電力が大きいために長距離伝送が可能となる。一方、極微弱電力通信モードでは、送信電力が小さいために通信可能距離は短く制限されるが、日本国の電波法による周波数制限が緩和される。 When the wireless transmitter shown in FIG. 25 performs extremely weak power communication (for example, transmission power of −70 dBm / MHz or less), spurious due to the direct path among the above two main transmission paths is particularly problematic. FIG. 26A shows a transmission spectrum when the wireless transmitter shown in FIG. 25 performs signal transmission at a transmission power of about −40 dBm / MHz. On the other hand, FIG. 26B shows a transmission spectrum when the radio transmitter shown in FIG. 25 performs signal transmission with extremely weak power of about −70 dBm / MHz. Hereinafter, a communication mode in which signal transmission is performed with extremely weak power will be referred to as “very weak power communication mode”. In addition, a communication mode in which signal transmission is performed with a sufficiently high transmission power (for example, transmission power of about −70 dBm / MHz) compared to the extremely weak power communication mode is referred to as a “normal power communication mode”. In the normal power communication mode, transmission power is large, so long distance transmission is possible. On the other hand, in the extremely weak power communication mode, since the transmission power is small, the communicable distance is limited to be short, but the frequency limitation by the Japanese radio law is relaxed.
　図２６Ａに示す通常電力通信モードから図２６Ｂに示す極微弱電力通信モードへ無線送信機の通信モードを切り替える場合を考える。極微弱電力通信モードでは、送信アンプ８４のゲインが低く設定される。このため、間接伝達経路を経由したスプリアスは減衰され、スプリアスの送信信号に対する比が維持されるため問題とならない。一方、直接伝達経路を経由したスプリアスは送信アンプ８４によって減衰されない。このため、直接伝達経路を経由したスプリアスの電力は相対的に大きくなり、伝送速度や伝送距離が制限されてしまう。また、直接伝達経路を経由したスプリアスの放射によって、日本国の電波法に照らして無線局免許が不要とされる許容値を超えて送信電力が大きくなる場合、いわゆる微弱無線局としての無線送信機の使用が違法なものとなる。 Consider a case where the wireless transmitter communication mode is switched from the normal power communication mode shown in FIG. 26A to the very weak power communication mode shown in FIG. 26B. In the extremely weak power communication mode, the gain of the transmission amplifier 84 is set low. For this reason, the spurious via the indirect transmission path is attenuated, and the ratio of the spurious to the transmission signal is maintained, so there is no problem. On the other hand, spurious signals that have passed through the direct transmission path are not attenuated by the transmission amplifier 84. For this reason, the power of the spurious via the direct transmission path becomes relatively large, and the transmission speed and transmission distance are limited. In addition, if the transmission power increases beyond the allowable value where a radio station license is not required in accordance with the Radio Law of Japan due to spurious radiation via the direct transmission path, a radio transmitter as a so-called weak radio station The use of is illegal.
　仮に、周波数シンセサイザ８の出力信号電力が十分に小さくなるよう設計した場合、直接伝達経路を経由したスプリアスを含めて、スプリアスレベルを常に小さく抑えることができる。しかしながら、通常電力通信モードでのアップコンバータ８３及び受信用のダウンコンバータ（不図示）のゲインが小さくなってしまうため、送受信性能が劣化してしまう。また、仮に、主要なスプリアス源であるＶＣＯ８０の電力が小さくなるよう設計することでも、同様にスプリアスレベルを常に小さくできる。しかしながら、ＶＣＯ８０に起因する位相雑音の増大を招くため、やはり送受信性能が劣化してしまう。 If the output signal power of the frequency synthesizer 8 is designed to be sufficiently small, the spurious level including the spurious via the direct transmission path can always be kept small. However, since the gains of the up-converter 83 and the reception down-converter (not shown) in the normal power communication mode are reduced, the transmission / reception performance is deteriorated. Also, if the power of the VCO 80, which is the main spurious source, is designed to be small, the spurious level can always be reduced similarly. However, since the phase noise caused by the VCO 80 is increased, the transmission / reception performance is also deteriorated.
　本発明は、送信電力を切り替え可能であり且つ極微弱電力での送信を行う無線通信装置に適用される場合に、送信性能の劣化を抑制することが可能な周波数シンセサイザを提供することを目的とする。 An object of the present invention is to provide a frequency synthesizer capable of suppressing deterioration of transmission performance when applied to a wireless communication apparatus capable of switching transmission power and performing transmission with extremely weak power. To do.
　本発明の第１の態様にかかる周波数シンセサイザは、電圧制御発振器、ＰＬＬ回路および第１の制御回路を含む。前記電圧制御発振器は、周波数制御電圧に応じて発振周波数を変更可能であり、振幅制御信号に応じて出力信号振幅を変更可能である。前記ＰＬＬ回路は、前記電圧制御発振器の出力信号又は前記出力信号を分周した信号と基準周波数信号との比較結果に応じて前記周波数制御電圧を生成する。また、前記第１の制御回路は、前記振幅制御信号を前記電圧制御発振器に供給し、前記出力信号振幅が外部から供給されるモード切り替え信号に対応した大きさとなるよう前記電圧制御発振器を制御する。 The frequency synthesizer according to the first aspect of the present invention includes a voltage controlled oscillator, a PLL circuit, and a first control circuit. The voltage controlled oscillator can change the oscillation frequency according to the frequency control voltage, and can change the output signal amplitude according to the amplitude control signal. The PLL circuit generates the frequency control voltage according to a comparison result between an output signal of the voltage controlled oscillator or a signal obtained by dividing the output signal and a reference frequency signal. The first control circuit supplies the amplitude control signal to the voltage controlled oscillator, and controls the voltage controlled oscillator so that the output signal amplitude has a magnitude corresponding to a mode switching signal supplied from the outside. .
　本発明の第２の態様にかかる無線通信装置は、上述した本発明の第１の態様にかかる周波数シンセサイザを含む。さらに、当該無線通信装置は、前記周波数シンセサイザの出力信号を局部発振信号として用いて通信信号の周波数変換を行うミキサと、前記モード切り替え信号を前記周波数シンセサイザに供給する制御部を含む。当該制御部は、前記通信信号の送信電力が異なる複数の通信モードの間でのモード切り替えに応じて前記モード切り替え信号を生成する。 The wireless communication apparatus according to the second aspect of the present invention includes the above-described frequency synthesizer according to the first aspect of the present invention. Further, the wireless communication apparatus includes a mixer that performs frequency conversion of a communication signal using an output signal of the frequency synthesizer as a local oscillation signal, and a control unit that supplies the mode switching signal to the frequency synthesizer. The said control part produces | generates the said mode switching signal according to mode switching between several communication modes from which transmission power of the said communication signal differs.
　本発明の第３の態様にかかる方法は、周波数シンセサイザと、前記周波数シンセサイザの出力信号を局部発振信号として用いて通信信号の周波数変換を行うミキサとを備える無線通信装置の制御方法である。当該方法は、
（ａ）前記通信信号の送信電力が異なる複数の通信モードの間でのモード切り替えに応じてモード切り替え信号を生成するステップ、及び
（ｂ）前記モード切り替え信号を前記周波数シンセサイザに供給し、前記周波数シンセサイザに含まれる電圧制御発振器の出力信号振幅の大きさを前記通信信号の送信電力の大きさに応じて変更するステップを含む。 A method according to a third aspect of the present invention is a control method for a wireless communication apparatus including a frequency synthesizer and a mixer that performs frequency conversion of a communication signal using an output signal of the frequency synthesizer as a local oscillation signal. The method is
(A) generating a mode switching signal in response to mode switching between a plurality of communication modes having different transmission powers of the communication signal; and (b) supplying the mode switching signal to the frequency synthesizer. Changing the magnitude of the output signal amplitude of the voltage controlled oscillator included in the synthesizer in accordance with the magnitude of the transmission power of the communication signal.
　本発明により、送信電力を切り替え可能であり且つ極微弱電力での送信を行う無線通信装置に適用される場合に、送信性能の劣化を抑制することが可能な周波数シンセサイザを提供できる。また、送信電力を切り替え可能な無線通信装置が極微弱電力での送信を行う際の送信性能の劣化を抑制できる。 According to the present invention, it is possible to provide a frequency synthesizer capable of suppressing deterioration in transmission performance when applied to a wireless communication apparatus capable of switching transmission power and performing transmission with extremely weak power. In addition, it is possible to suppress deterioration in transmission performance when a wireless communication apparatus capable of switching transmission power performs transmission with extremely weak power.
本発明の第１の実施形態にかかる周波数シンセサイザの構成を示すブロック図である。It is a block diagram which shows the structure of the frequency synthesizer concerning the 1st Embodiment of this invention. 第１の実施形態にかかる周波数シンセサイザに含まれるＶＣＯの具体的な回路例を示す図である。It is a figure which shows the specific circuit example of VCO contained in the frequency synthesizer concerning 1st Embodiment. 第１の実施形態にかかる周波数シンセサイザに含まれるＶＣＯの他の回路例を示す図である。It is a figure which shows the other circuit example of VCO contained in the frequency synthesizer concerning 1st Embodiment. 第１の実施形態にかかる周波数シンセサイザに含まれる振幅制御回路の具体的な回路例を示す図である。It is a figure which shows the specific circuit example of the amplitude control circuit contained in the frequency synthesizer concerning 1st Embodiment. 図２に示した振幅制御回路の動作を示す図である。It is a figure which shows operation | movement of the amplitude control circuit shown in FIG. 図２に示した振幅制御回路の動作を示す図である。It is a figure which shows operation | movement of the amplitude control circuit shown in FIG. 第１の実施形態にかかる周波数シンセサイザに含まれる振幅制御回路の他の回路例を示す図である。It is a figure which shows the other example of an amplitude control circuit contained in the frequency synthesizer concerning 1st Embodiment. 第１の実施形態にかかる周波数シンセサイザの動作を示す波形図である。It is a wave form diagram which shows operation | movement of the frequency synthesizer concerning 1st Embodiment. 通常電力通信モードで許容されるＶＣＯ振幅と位相雑音の関係を示す図である。It is a figure which shows the relationship between the VCO amplitude and phase noise which are accept | permitted in normal electric power communication mode. 極微弱電力送信モードで許容されるＶＣＯ振幅と位相雑音の関係及びＶＣＯ振幅とスプリアス電力の関係を示す図である。It is a figure which shows the relationship between the VCO amplitude and phase noise which are accept | permitted in a very weak power transmission mode, and the relationship between VCO amplitude and spurious power. 第１の実施形態にかかる周波数シンセサイザを適用した無線通信装置の構成例を示すブロック図である。It is a block diagram which shows the structural example of the radio | wireless communication apparatus to which the frequency synthesizer concerning 1st Embodiment is applied. 本発明の第２の実施形態にかかる周波数シンセサイザの構成を示すブロック図である。It is a block diagram which shows the structure of the frequency synthesizer concerning the 2nd Embodiment of this invention. 第２の実施形態にかかる周波数シンセサイザに含まれる振幅制御回路の具体的な回路例を示す図である。It is a figure which shows the specific circuit example of the amplitude control circuit contained in the frequency synthesizer concerning 2nd Embodiment. 第２の実施形態にかかる周波数シンセサイザの動作を示す波形図である。It is a wave form diagram which shows operation | movement of the frequency synthesizer concerning 2nd Embodiment. 本発明の第３の実施形態にかかる周波数シンセサイザの構成を示すブロック図である。It is a block diagram which shows the structure of the frequency synthesizer concerning the 3rd Embodiment of this invention. 第３の実施形態にかかる周波数シンセサイザに含まれる感度可変分周器の具体的な回路例を示す図である。It is a figure which shows the specific circuit example of the sensitivity variable frequency divider contained in the frequency synthesizer concerning 3rd Embodiment. 背景技術にかかる感度固定分周器の一般的な周波数特性を示す参考図である。It is a reference figure which shows the general frequency characteristic of the sensitivity fixed frequency divider concerning background art. 図１５に示した感度可変分周器の周波数特性を示す図である。It is a figure which shows the frequency characteristic of the sensitivity variable frequency divider shown in FIG. 第３の実施形態にかかる周波数シンセサイザに含まれる感度可変分周器の他の回路例を示す図である。It is a figure which shows the other circuit example of the sensitivity variable frequency divider contained in the frequency synthesizer concerning 3rd Embodiment. 図１８に示した感度可変分周器の周波数特性を示す図である。It is a figure which shows the frequency characteristic of the sensitivity variable frequency divider shown in FIG. 第３の実施形態にかかる周波数シンセサイザの動作を示す波形図である。It is a wave form diagram showing operation of a frequency synthesizer concerning a 3rd embodiment. 本発明の第４の実施形態にかかる周波数シンセサイザの構成を示すブロック図である。It is a block diagram which shows the structure of the frequency synthesizer concerning the 4th Embodiment of this invention. 第４の実施形態にかかる周波数シンセサイザに含まれる振幅制御回路の具体的な回路例を示す図である。It is a figure which shows the specific circuit example of the amplitude control circuit contained in the frequency synthesizer concerning 4th Embodiment. 本発明の第５の実施形態にかかる周波数シンセサイザの構成を示すブロック図である。It is a block diagram which shows the structure of the frequency synthesizer concerning the 5th Embodiment of this invention. 背景技術にかかる周波数シンセサイザの構成を示すブロック図である。It is a block diagram which shows the structure of the frequency synthesizer concerning background art. 無線送信器に適用された周波数シンセサイザから発生されるスプリアスの伝達経路を示す図である。It is a figure which shows the transmission path | route of the spurious generated from the frequency synthesizer applied to the wireless transmitter. 通常電力通信モードの周波数スペクトラム波形を示す概略図である。It is the schematic which shows the frequency spectrum waveform of normal electric power communication mode. 極微弱電力送信モードの周波数スペクトラム波形を示す概略図である。It is the schematic which shows the frequency spectrum waveform of a very weak electric power transmission mode.
　以下では、本発明を適用した具体的な実施の形態について、図面を参照しながら詳細に説明する。各図面において、同一要素には同一の符号が付されており、説明の明確化のため、必要に応じて重複説明は省略される。 Hereinafter, specific embodiments to which the present invention is applied will be described in detail with reference to the drawings. In the drawings, the same elements are denoted by the same reference numerals, and redundant description is omitted as necessary for the sake of clarity.
＜第１の実施の形態＞
　図１は、本実施形態にかかる周波数シンセサイザ１の構成を示すブロック図である。周波数シンセサイザ１は、ＶＣＯ１０、ＶＣＯ１０の発振周波数をロックするためのＰＬＬ回路１８を含む。当該ＰＬＬ回路１８は、分周器１１、位相・周波数比較器１２、チャージポンプ１３、及びＬＰＦ１４を含む。なお、ＰＬＬ回路１８の構成は、図２４に示した一般的な周波数シンセサイザ８と同様であるため、ここでは説明を省略する。 <First Embodiment>
FIG. 1 is a block diagram showing a configuration of a frequency synthesizer 1 according to the present embodiment. The frequency synthesizer 1 includes a VCO 10 and a PLL circuit 18 for locking the oscillation frequency of the VCO 10. The PLL circuit 18 includes a frequency divider 11, a phase / frequency comparator 12, a charge pump 13, and an LPF 14. The configuration of the PLL circuit 18 is the same as that of the general frequency synthesizer 8 shown in FIG.
　周波数シンセサイザ１は、さらに、ＶＣＯ１０の出力信号振幅を制御するためのフィードバックループを有する。当該フィードバックループは、振幅制御回路１６を含む。振幅制御回路１６は、ＶＣＯ１０の出力信号振幅を監視し、ＶＣＯ１０の出力信号振幅が所定の目標値に近づくように振幅制御信号を繰り返し生成してＶＣＯ１０に供給する。また、ＶＣＯ１０は、ＬＰＦ１４から供給される制御電圧に応じて発振周波数を変更するための構成に加えて、振幅制御回路１６からの振幅制御信号に応じて出力信号振幅を変更するための構成を有する。 The frequency synthesizer 1 further has a feedback loop for controlling the output signal amplitude of the VCO 10. The feedback loop includes an amplitude control circuit 16. The amplitude control circuit 16 monitors the output signal amplitude of the VCO 10, repeatedly generates an amplitude control signal so that the output signal amplitude of the VCO 10 approaches a predetermined target value, and supplies the amplitude control signal to the VCO 10. The VCO 10 has a configuration for changing the output signal amplitude according to the amplitude control signal from the amplitude control circuit 16 in addition to the configuration for changing the oscillation frequency according to the control voltage supplied from the LPF 14. .
　図１の構成例は、出力信号振幅の目標レベルを規定する参照信号Ｖ＿ＲＥＦを振幅制御回路１６に与えるために、参照信号発生回路１７を含む。参照信号発生回路１７は、Ｖ＿ＲＥＦを指定する制御信号ＣＯＤＥ＿ＲＥＦを入力し、制御信号ＣＯＤＥ＿ＲＥＦに応じてＶ＿ＲＥＦの大きさを切り替える。例えば、上述した通常電力通信モード及び極微弱電力送信モードにそれぞれ対応する２通りのＣＯＤＥ＿ＲＥＦを参照信号発生回路１７に与えればよい。この場合、参照信号発生回路１７は、ＣＯＤＥ＿ＲＥＦに応じて、通常電力通信モードに対応するＶ＿ＲＥＦ又は極微弱電力送信モードに対応するＶ＿ＲＥＦを出力すればよい。つまり、制御信号ＣＯＤＥ＿ＲＥＦは、送信電力が異なる複数の通信モード間でのモード切り替えを示す信号である。 The configuration example of FIG. 1 includes a reference signal generation circuit 17 in order to provide the amplitude control circuit 16 with a reference signal V_REF that defines a target level of the output signal amplitude. The reference signal generation circuit 17 receives a control signal CODE_REF that specifies V_REF, and switches the magnitude of V_REF in accordance with the control signal CODE_REF. For example, the reference signal generation circuit 17 may be provided with two types of CODE_REF corresponding to the above-described normal power communication mode and extremely weak power transmission mode. In this case, the reference signal generation circuit 17 may output V_REF corresponding to the normal power communication mode or V_REF corresponding to the extremely weak power transmission mode in accordance with CODE_REF. That is, the control signal CODE_REF is a signal indicating mode switching between a plurality of communication modes having different transmission powers.
　続いて以下では、ＶＣＯ１０及び振幅制御回路１６の具体的な回路構成例について順に説明する。図２は、ＶＣＯ１０の具体例の１つを示す回路図である。クロスカップルされたＮチャネルＭＯＳトランジスタＭ１及びＭ２と、クロスカップルされたＰチャネルＭＯＳトランジスタＭ３及びＭ４は、それぞれ負性抵抗として動作する。インダクタ１００、バラクタ１０１及び１０２、並びにキャパシタアレイ１０３は、共振回路を構成する。可変容量素子としてのバラクタ１０１及び１０２は、ＬＰＦ１４から供給される制御電圧ＶＣＴＲＬの大きさに応じてその容量が変化し、ＶＣＯ１０の発振周波数を変化させる。また、キャパシタアレイ１０３は、ＶＣＯ１０の発振中心周波数に対するオフセット調整のために使用される。キャパシタアレイ１０３に含まれる各スイッチは、外部から供給される制御信号ＣＯＤＥ＿Ｆ０に応じて動作する。例えば、制御信号ＣＯＤＥ＿Ｆ０は、周波数シンセサイザ１が適用される無線通信装置に含まれる制御部が生成すればよい。 Subsequently, specific circuit configuration examples of the VCO 10 and the amplitude control circuit 16 will be sequentially described below. FIG. 2 is a circuit diagram showing one specific example of the VCO 10. Cross-coupled N-channel MOS transistors M1 and M2 and cross-coupled P-channel MOS transistors M3 and M4 operate as negative resistors, respectively. Inductor 100, varactors 101 and 102, and capacitor array 103 form a resonant circuit. The varactors 101 and 102 as variable capacitance elements change their capacitances according to the magnitude of the control voltage VCTRL supplied from the LPF 14 and change the oscillation frequency of the VCO 10. The capacitor array 103 is used for offset adjustment with respect to the oscillation center frequency of the VCO 10. Each switch included in the capacitor array 103 operates according to a control signal CODE_F0 supplied from the outside. For example, the control signal CODE_F0 may be generated by a control unit included in a wireless communication apparatus to which the frequency synthesizer 1 is applied.
　また、スイッチ１０４～１０６及びＮチャネルＭＯＳトランジスタＭ５～Ｍ７を含むスイッチ付きＭＯＳアレイは電流源として動作し、振幅制御信号ＣＯＤＥ＿ＡＭＰに応じてバイアス電流量を変更可能である。スイッチ１０４～１０６は、振幅制御回路１６によって生成される振幅制御信号ＣＯＤＥ＿ＡＭＰに応じて動作し、トランジスタＭ５～Ｍ７のゲートに対するバイアス電圧ＶＢＩＡＳの供給を制御する。例えば、トランジスタＭ６のサイズをＭ５の２倍、Ｍ７のサイズをＭ５の４倍とすれば、バイナリコードとされた振幅制御信号ＣＯＤＥ＿ＡＭＰによってバイアス電流量が段階的に切り替えられ、ＶＣＯ１０の出力信号振幅も段階的に切り替えられる。なお、トランジスタＭ５～Ｍ７のサイズを同一とし、振幅制御信号ＣＯＤＥ＿ＡＭＰをサーモメータコードとしてもよい。 The switch-equipped MOS array including the switches 104 to 106 and the N-channel MOS transistors M5 to M7 operates as a current source, and the amount of bias current can be changed according to the amplitude control signal CODE_AMP. The switches 104 to 106 operate according to the amplitude control signal CODE_AMP generated by the amplitude control circuit 16 and control the supply of the bias voltage VBIAS to the gates of the transistors M5 to M7. For example, if the size of the transistor M6 is twice that of M5 and the size of M7 is 4 times that of M5, the amount of bias current is switched stepwise by the amplitude control signal CODE_AMP that is a binary code, and the output signal amplitude of the VCO 10 is also changed. Switch in stages. Note that the transistors M5 to M7 may have the same size and the amplitude control signal CODE_AMP may be a thermometer code.
　図２に示したＶＣＯ１０の回路構成が一例に過ぎないことは勿論である。例えば、周波数オフセットの調整が不要である場合には、キャパシタアレイ１０３は省略されてもよい。ＶＣＯ１０は、ＰチャネルＭＯＳクロスカップルＭ３及びＭ４を含まずに構成することも可能である。また、バイアス電流を調整するためのトランジスタＭ５～Ｍ７の数は一例である。 Of course, the circuit configuration of the VCO 10 shown in FIG. 2 is merely an example. For example, when adjustment of the frequency offset is unnecessary, the capacitor array 103 may be omitted. The VCO 10 may be configured without including the P-channel MOS cross couples M3 and M4. The number of transistors M5 to M7 for adjusting the bias current is an example.
　図３にＶＣＯ１０の他の回路例を示す。図３の例では、ＰチャネルＭＯＳクロスカップルＭ３及びＭ４が省略されている。また、キャパシタアレイ１０３が複数のバラクタによって構成されている。また、バイアス電流調整のために、トランジスタＭ８及びスイッチ１０７が追加されている。 FIG. 3 shows another circuit example of the VCO 10. In the example of FIG. 3, the P-channel MOS cross couples M3 and M4 are omitted. The capacitor array 103 is composed of a plurality of varactors. Further, a transistor M8 and a switch 107 are added for adjusting the bias current.
　図４は、振幅制御回路１６の具体的な構成例の１つを示すブロック図である。ピーク検出回路１６０は、出力信号振幅の目標値を定める参照信号Ｖ＿ＲＥＦのピークレベル（つまり振幅）を検出する。同様に、ピーク検出回路１６１は、ＶＣＯ１０の出力信号のピークレベルを検出する。コンパレータ１６２は、参照信号Ｖ＿ＲＥＦの振幅とＶＣＯの出力信号の振幅とを比較する。コンパレータ１６２の出力信号は、制御ロジック回路１６３により演算された後に、振幅制御信号ＣＯＤＥ＿ＡＭＰとしてＶＣＯ１０へ供給される。図４の構成例では、コンパレータ１６２に入力より前段の各信号はアナログ信号であり、コンパレータ１６２の出力以降の後段の各信号はデジタル信号である。 FIG. 4 is a block diagram showing one specific configuration example of the amplitude control circuit 16. The peak detection circuit 160 detects the peak level (that is, amplitude) of the reference signal V_REF that determines the target value of the output signal amplitude. Similarly, the peak detection circuit 161 detects the peak level of the output signal of the VCO 10. The comparator 162 compares the amplitude of the reference signal V_REF with the amplitude of the output signal of the VCO. The output signal of the comparator 162 is calculated by the control logic circuit 163 and then supplied to the VCO 10 as the amplitude control signal CODE_AMP. In the configuration example of FIG. 4, each signal before the input to the comparator 162 is an analog signal, and each signal after the output of the comparator 162 is a digital signal.
　なお、図４の構成が一例に過ぎないことは勿論である。例えば、図６に示すように、コンパレータ１６２の代わりにオペアンプ１６４を用いてもよい。図６の例では、ＶＣＯ１０の出力信号振幅がアナログ信号のみで制御される。 Of course, the configuration of FIG. 4 is merely an example. For example, an operational amplifier 164 may be used instead of the comparator 162 as shown in FIG. In the example of FIG. 6, the output signal amplitude of the VCO 10 is controlled only with an analog signal.
　図５Ａ及び図５Ｂは、図４に示した振幅制御回路１６の動作を示す波形図である。図５Ａは、ＶＣＯ１０の出力信号振幅が参照信号Ｖ＿ＲＥＦに比べて大きい場合を示している。この場合、コンパレータ１６２は、"１"を出力する。一方、図５Ｂは、ＶＣＯ１０の出力信号振幅が参照信号Ｖ＿ＲＥＦに比べて小さい場合を示している。この場合、コンパレータ１６２は、"０"を出力する。このように１ビットコンパレータを用いることは、ダイナミックレンジが狭く、精度が低い微細ＣＭＯＳプロセスに適している。また、できるだけデジタル信号で処理できる点も微細ＣＭＯＳプロセスに適している。なお、１ビットコンパレータの代わりにＡ／Ｄ変換器を用いてもよい。もちろん、図６に示すようにアナログ信号によってＶＣＯ１０の出力信号振幅を制御してもよい。 5A and 5B are waveform diagrams showing the operation of the amplitude control circuit 16 shown in FIG. FIG. 5A shows a case where the output signal amplitude of the VCO 10 is larger than the reference signal V_REF. In this case, the comparator 162 outputs “1”. On the other hand, FIG. 5B shows a case where the output signal amplitude of the VCO 10 is smaller than the reference signal V_REF. In this case, the comparator 162 outputs “0”. Using a 1-bit comparator in this way is suitable for a fine CMOS process with a narrow dynamic range and low accuracy. In addition, it is suitable for a fine CMOS process because it can be processed with digital signals as much as possible. An A / D converter may be used instead of the 1-bit comparator. Of course, the output signal amplitude of the VCO 10 may be controlled by an analog signal as shown in FIG.
　続いて以下では、周波数シンセサイザ１の全体的な動作について図７の波形図を用いて説明する。ここでは、制御信号ＣＯＤＥ＿ＲＥＦが「極微弱電力モード」に対応した値から「通常電力モード」に対応した値に切り替えられる場合を例にとって説明する。時間Ｔ１～Ｔ５の間は、制御信号ＣＯＤＥ＿ＲＥＦが極微弱電力モードを示している。この間は、極微弱電力モードに対応した参照信号Ｖ＿ＲＥＦが参照信号発生回路１７によって生成される。なお、振幅制御信号ＣＯＤＥ＿ＡＭＰは３ビット信号であり、ＣＯＤＥ＿ＡＭＰの値に対してＶＣＯ１０の出力信号振幅が単調増加すると仮定する。つまり、ＶＣＯ１０の出力信号振幅は、"ＣＯＤＥ＿ＡＭＰの値が"０００"のとき最小値となり、"１１１"の最大値になる。また、振幅制御信号ＣＯＤＥ＿ＡＭＰに対して電流源（トランジスタＭ５～Ｍ７）の電流量はバイナリコードで制御されると仮定する。 Subsequently, the overall operation of the frequency synthesizer 1 will be described below with reference to the waveform diagram of FIG. Here, a case where the control signal CODE_REF is switched from a value corresponding to the “very weak power mode” to a value corresponding to the “normal power mode” will be described as an example. During the time T1 to T5, the control signal CODE_REF indicates the extremely weak power mode. During this time, the reference signal V_REF corresponding to the extremely weak power mode is generated by the reference signal generation circuit 17. Note that the amplitude control signal CODE_AMP is a 3-bit signal, and it is assumed that the output signal amplitude of the VCO 10 monotonously increases with respect to the value of CODE_AMP. That is, the output signal amplitude of the VCO 10 is the minimum value when the value of “CODE_AMP” is “000”, and the maximum value of “111.” Further, the current source (transistors M5 to M7) of the amplitude control signal CODE_AMP. Assume that the amount of current is controlled by a binary code.
　最初のサイクルである時間Ｔ１において、振幅制御信号ＣＯＤＥ＿ＡＭＰは、"１１１"に設定されている。時間Ｔ１では、参照信号Ｖ＿ＲＥＦの振幅に比べてＶＣＯ１０の振幅が大きいために、コンパレータ１６２の比較結果は"１"となる。これにより、次サイクル（時間Ｔ２）での振幅制御信号ＣＯＤＥ＿ＡＭＰは"１１０"に変更される。この場合、制御ロジック回路１６３は減算回路で実現できる。そして、振幅制御信号ＣＯＤＥ＿ＡＭＰの値が減少して"１１０"となったことにより、ＶＣＯ１０の出力信号振幅が１段階小さくなる。この動作を繰り返していくと、振幅制御信号ＣＯＤＥ＿ＡＭＰが"１００"のときに、コンパレータ１６２の比較結果が "０"に収束する（時間Ｔ４）。 At time T1, which is the first cycle, the amplitude control signal CODE_AMP is set to “111”. At time T1, since the amplitude of the VCO 10 is larger than the amplitude of the reference signal V_REF, the comparison result of the comparator 162 is “1”. As a result, the amplitude control signal CODE_AMP in the next cycle (time T2) is changed to “110”. In this case, the control logic circuit 163 can be realized by a subtraction circuit. Then, as the value of the amplitude control signal CODE_AMP decreases to “110”, the output signal amplitude of the VCO 10 decreases by one step. When this operation is repeated, the comparison result of the comparator 162 converges to “0” when the amplitude control signal CODE_AMP is “100” (time T4).
　次に、時間Ｔ６において通常電力モードへ切り替えられた場合、参照信号Ｖ＿Ｒが高く設定される。また、リセット信号（図７（Ｇ））に従って振幅制御信号ＣＯＤＥ＿ＡＭＰの値は"１１１"へ初期設定される。そして、前述したような動作が実施される。図７（Ｇ）のリセット信号は、外部の回路または参照信号発生回路１７から振幅制御回路１６に供給すればよい。また、参照信号Ｖ＿ＲＥＦの変更に応じてリセット動作を行うよう、振幅制御回路１６を構成してもよい。 Next, when switching to the normal power mode at time T6, the reference signal V_R is set high. Further, the value of the amplitude control signal CODE_AMP is initialized to “111” in accordance with the reset signal (FIG. 7G). Then, the operation as described above is performed. The reset signal in FIG. 7G may be supplied to the amplitude control circuit 16 from an external circuit or the reference signal generation circuit 17. Further, the amplitude control circuit 16 may be configured to perform a reset operation in accordance with the change of the reference signal V_REF.
　図７には、振幅制御信号ＣＯＤＥ＿ＡＭＰの最大値を初期値とし、振幅制御信号ＣＯＤＥ＿ＡＭＰの値を初期値から徐々に減少させることで、ＶＣＯ１０の出力信号振幅を所望の大きさに収束させる例を示した。しかしながら、このような方法は一例に過ぎない。例えば、振幅制御信号ＣＯＤＥ＿ＡＭＰの最小値を初期値に設定し、振幅制御信号ＣＯＤＥ＿ＡＭＰの値を初期値から徐々に増大させてもよい。また、二分探索などの公知の探索手法を用いて振幅制御信号ＣＯＤＥ＿ＡＭＰの収束値を探索してもよい。二分探索などの探索手法を用いることで、収束時間を短縮できる。 FIG. 7 shows an example in which the output signal amplitude of the VCO 10 is converged to a desired magnitude by setting the maximum value of the amplitude control signal CODE_AMP as an initial value and gradually decreasing the value of the amplitude control signal CODE_AMP from the initial value. It was. However, such a method is only an example. For example, the minimum value of the amplitude control signal CODE_AMP may be set to an initial value, and the value of the amplitude control signal CODE_AMP may be gradually increased from the initial value. Further, the convergence value of the amplitude control signal CODE_AMP may be searched using a known search method such as binary search. By using a search method such as binary search, the convergence time can be shortened.
　ところで、ＶＣＯ１０の出力信号振幅の基準となる参照信号Ｖ＿ＲＥＦの大きさは、ＶＣＯ１０の位相雑音の許容値、スプリアス電力の許容値に基づいて決定すればよい。ＶＣＯ１０の位相雑音の許容値とスプリアス電力の許容値は、周波数シンセサイザ１が適用される無線通信装置のシステム設計の段階で、伝送速度、占有帯域幅、所望ＣＮＲ（Carrier to Noise Ratio）の考慮から決定される。 By the way, the magnitude of the reference signal V_REF serving as a reference for the output signal amplitude of the VCO 10 may be determined based on the allowable value of the phase noise of the VCO 10 and the allowable value of the spurious power. The allowable value of the phase noise of the VCO 10 and the allowable value of the spurious power are determined in consideration of the transmission speed, occupied bandwidth, and desired CNR (Carrier to Noise Ratio) at the system design stage of the wireless communication apparatus to which the frequency synthesizer 1 is applied. It is determined.
　図８は、通常電力通信モード時おけるＶＣＯ１０の位相雑音の許容値Ｌ＿ＰＮと出力信号振幅の関係を示す図である。図８に示すように、ＶＣＯ１０の位相雑音は下に凸の特性となることが知られている。このとき、アップコンバージョンおよびダウンコンバージョンのゲインを高くするためには、ＶＣＯ１０の振幅は、許容される振幅範囲（Ｖ１～Ｖ２）の中でできるだけ大きくしたほうがよい。 FIG. 8 is a diagram showing a relationship between the allowable value L_PN of the phase noise of the VCO 10 and the output signal amplitude in the normal power communication mode. As shown in FIG. 8, it is known that the phase noise of the VCO 10 has a downwardly convex characteristic. At this time, in order to increase the gain of up-conversion and down-conversion, the amplitude of the VCO 10 should be as large as possible within the allowable amplitude range (V1 to V2).
　一方、図９は、極微弱電力通信モード時おけるＶＣＯ１０の位相雑音の許容値Ｌ＿ＰＮと出力信号振幅の関係を示す図である。さらに、図９は、ＶＣＯ１０に起因するスプリアス電力とＶＣＯ１０の出力信号振幅の関係を点線のグラフによって示している。一般に、電流と出力信号振幅は比例関係にあるため、ＶＣＯ１０の振幅とスプリアス電力は単調増加の関係にある。なお、図９では、位相雑音の許容値Ｌ＿ＰＮが図８の場合と同じであると仮定している。極微弱電力通信モード時には、許容されるＶＣＯ１０の振幅範囲は、位相雑音の許容値Ｌ＿ＰＮだけでなく、スプリアス電力の許容値Ｌ＿ＳＰによっても制限される。図９では、許容されるＶＣＯ１０の振幅範囲はＶ１～Ｖ３の範囲となる。従って、通常電力通信モードによる信号送信時又は受信時に比べて、極微弱電力通信モードではＶＣＯ１０の振幅を小さくする必要がある。なお、ＶＣＯ１０の振幅を小さくしすぎると、スプリアス電力は小さくなるものの、位相雑音が大きく劣化する。 On the other hand, FIG. 9 is a diagram showing the relationship between the phase noise allowable value L_PN of the VCO 10 and the output signal amplitude in the extremely weak power communication mode. Further, FIG. 9 shows the relationship between the spurious power caused by the VCO 10 and the output signal amplitude of the VCO 10 by a dotted line graph. In general, since the current and the output signal amplitude are in a proportional relationship, the amplitude of the VCO 10 and the spurious power are in a monotonically increasing relationship. In FIG. 9, it is assumed that the allowable value L_PN of the phase noise is the same as that in FIG. In the extremely weak power communication mode, the allowable amplitude range of the VCO 10 is limited not only by the allowable value L_PN of the phase noise but also by the allowable value L_SP of the spurious power. In FIG. 9, the allowable amplitude range of the VCO 10 is a range of V1 to V3. Therefore, it is necessary to reduce the amplitude of the VCO 10 in the extremely weak power communication mode as compared with the signal transmission or reception in the normal power communication mode. If the amplitude of the VCO 10 is too small, the spurious power is reduced, but the phase noise is greatly deteriorated.
　図８及び図９を用いて説明したように、通常電力通信モードではＶＣＯ１０の出力信号振幅を許容される振幅範囲Ｖ１～Ｖ２内でなるべく大きな値に設定し、極微弱電力通信モードではＶＣＯ１０の出力信号振幅を振幅範囲Ｖ１～Ｖ３内に制限するとよい。本実施の形態にかかる周波数シンセサイザ１は、通信モード切り替えに応じて、ＶＣＯ１０の出力信号振幅を容易に変更可能である。また、振幅制御回路１６を含むフィードバックループがＶＣＯ１０の出力信号振幅を監視し、ＶＣＯ１０の出力信号振幅を所望のレベルにロックさせるため、周波数シンセサイザ１は、ＶＣＯ１０の出力信号振幅を安定化できる。 As described with reference to FIGS. 8 and 9, in the normal power communication mode, the output signal amplitude of the VCO 10 is set as large as possible within the allowable amplitude range V1 to V2, and in the extremely weak power communication mode, the output of the VCO 10 is set. The signal amplitude may be limited within the amplitude range V1 to V3. The frequency synthesizer 1 according to the present embodiment can easily change the output signal amplitude of the VCO 10 in accordance with the communication mode switching. Further, since the feedback loop including the amplitude control circuit 16 monitors the output signal amplitude of the VCO 10 and locks the output signal amplitude of the VCO 10 to a desired level, the frequency synthesizer 1 can stabilize the output signal amplitude of the VCO 10.
　図１０は、本実施の形態にかかる周波数シンセサイザ１を適用した無線通信装置の構成例を示すブロック図である。周波数シンセサイザ１は、送信用及び受信用の直交ミキサ１８３及び１９０に供給される局部発振信号（ローカル信号）を生成する。制御部１８０は、ＶＣＯ１０の発振中心周波数Ｆ０に対するオフセットを指定するための制御信号ＣＯＤＥ＿Ｆ０と、通信モードを指定するための制御信号ＣＯＤＥ＿ＲＥＦを周波数シンセサイザ１に供給する。 FIG. 10 is a block diagram showing a configuration example of a wireless communication apparatus to which the frequency synthesizer 1 according to the present embodiment is applied. The frequency synthesizer 1 generates a local oscillation signal (local signal) supplied to the orthogonal mixers 183 and 190 for transmission and reception. The control unit 180 supplies the frequency synthesizer 1 with a control signal CODE_F0 for designating an offset with respect to the oscillation center frequency F0 of the VCO 10 and a control signal CODE_REF for designating a communication mode.
　デジタルベースバンド処理部１８１は、送信信号に対する符号化処理、ベースバンド変調処理等を行う。Ｄ／Ａコンバータ１８２は、送信信号をアナログ信号に変換し、直交ミキサ１８３に供給する。直交ミキサ１８３は、周波数シンセサイザ１によって生成されるローカル信号とアナログベースバンド信号とを乗算することにより、キャリア周波数帯域の送信信号を生成する。直交ミキサ１８３によって生成されたキャリア周波数帯域の送信信号は、バンドパスフィルタ１８４を介して送信パワーアンプ１８５に供給される。送信パワーアンプ１８５は、送信信号を増幅し、デュプレクサ１８６を介してアンテナ１８７に出力する。 The digital baseband processing unit 181 performs encoding processing, baseband modulation processing, and the like on the transmission signal. The D / A converter 182 converts the transmission signal into an analog signal and supplies it to the orthogonal mixer 183. The orthogonal mixer 183 generates a transmission signal in the carrier frequency band by multiplying the local signal generated by the frequency synthesizer 1 and the analog baseband signal. The transmission signal in the carrier frequency band generated by the orthogonal mixer 183 is supplied to the transmission power amplifier 185 via the band pass filter 184. The transmission power amplifier 185 amplifies the transmission signal and outputs it to the antenna 187 via the duplexer 186.
　一方、アンテナ１８７によって受信された信号は、低雑音アンプ１８８、バンドパスフィルタ１８９を経由して直交ミキサ１９０に供給される。直交ミキサ１９０は、周波数シンセサイザ１によって生成されるローカル信号と受信信号とを乗算することにより、ベースバンド帯域にダウンコンバートする。直交ミキサ１９０によってダウンコンバートされた受信信号は、ローパスフィルタ１９１を経由してＡ／Ｄコンバータ１９２に供給される。デジタルベースバンド処理部１８１は、Ａ／Ｄコンバータ１９２によってサンプリングされた受信信号データ列を用いて復調処理、復号化処理を実行する。 On the other hand, the signal received by the antenna 187 is supplied to the orthogonal mixer 190 via the low noise amplifier 188 and the band pass filter 189. The orthogonal mixer 190 multiplies the local signal generated by the frequency synthesizer 1 and the received signal, thereby down-converting to the baseband. The reception signal down-converted by the orthogonal mixer 190 is supplied to the A / D converter 192 via the low-pass filter 191. The digital baseband processing unit 181 performs demodulation processing and decoding processing using the received signal data sequence sampled by the A / D converter 192.
　なお、図１０の無線通信装置が周波数シンセサイザ１の適用先の一例に過ぎないことは勿論である。例えば、図１０の装置の受信方式はダイレクトコンバージョン方式であるが、スーパーヘテロダイン方式であってもよいし、低ＩＦ方式であってもよい。また、周波数シンセサイザ１の適用先は、送信専用の無線通信装置でもよいし、受信専用の無線通信装置であってもよい。 Of course, the wireless communication apparatus of FIG. 10 is merely an example of an application destination of the frequency synthesizer 1. For example, the reception method of the apparatus of FIG. 10 is a direct conversion method, but may be a superheterodyne method or a low IF method. The application destination of the frequency synthesizer 1 may be a radio communication device dedicated to transmission or a radio communication device dedicated to reception.
＜第２の実施の形態＞
　図１１は、本実施形態にかかる周波数シンセサイザ２の構成を示すブロック図である。周波数シンセサイザ２は、上述した周波数シンセサイザ１の構成に加えて、振幅制御回路２６から出力される振幅制御信号ＣＯＤＥ＿ＡＭＰを取り込んで保持するレジスタ回路２８を有する。また、図１１の構成では、通信モードの切り替えを指示する制御信号ＣＯＤＥ＿ＲＥＦがレジスタ回路２８に供給され、制御信号ＣＯＤＥ＿ＲＥＦによって指定された通信モードに対応する振幅制御信号ＣＯＤＥ＿ＡＭＰの値がレジスタ回路２８から出力される。振幅制御回路２６は、制御信号ＣＯＤＥ＿ＲＥＦに応じてレジスタ回路２８から出力される振幅制御信号ＣＯＤＥ＿ＡＭＰの値をＶＣＯ１０に供給する。 <Second Embodiment>
FIG. 11 is a block diagram showing the configuration of the frequency synthesizer 2 according to the present embodiment. In addition to the configuration of the frequency synthesizer 1 described above, the frequency synthesizer 2 includes a register circuit 28 that captures and holds the amplitude control signal CODE_AMP output from the amplitude control circuit 26. In the configuration of FIG. 11, the control signal CODE_REF instructing switching of the communication mode is supplied to the register circuit 28, and the value of the amplitude control signal CODE_AMP corresponding to the communication mode specified by the control signal CODE_REF is output from the register circuit 28. Is done. The amplitude control circuit 26 supplies the value of the amplitude control signal CODE_AMP output from the register circuit 28 to the VCO 10 in response to the control signal CODE_REF.
　図１２は、振幅制御回路２６の具体的な回路例を示す図である。図１２に示す振幅制御回路２６は、図４に示した振幅制御回路１６の構成に加えてスイッチ２６４を有する。スイッチ２６４は、制御ロジック回路１６３の出力をＶＣＯ１０に供給する第１の接続状態、制御ロジック回路１６３の出力をレジスタ回路２８に供給する第２の接続状態、及び、レジスタ回路２８の出力をＶＣＯ１０に供給する第３の接続状態の間で接続状態を変更可能である。換言すれば、ＶＣＯ１０には、制御ロジック回路１６３の出力とレジスタ回路２８の出力とが相補的に振幅制御信号として供給される。ピーク検出回路１６０及び１６１、コンパレータ１６２、並びに制御ロジック回路１６３の動作のオン／オフは、自動振幅制御の実行／停止を指示する切替信号ＥＮ＿ＡＡＣによって制御される。スイッチ２６４の切り替えを制御する信号と切替信号ＥＮ＿ＡＡＣは、例えば、周波数シンセサイザ２が適用される無線通信装置の制御部から振幅制御回路２６に供給すればよい。 FIG. 12 is a diagram illustrating a specific circuit example of the amplitude control circuit 26. The amplitude control circuit 26 shown in FIG. 12 has a switch 264 in addition to the configuration of the amplitude control circuit 16 shown in FIG. The switch 264 has a first connection state for supplying the output of the control logic circuit 163 to the VCO 10, a second connection state for supplying the output of the control logic circuit 163 to the register circuit 28, and an output of the register circuit 28 to the VCO 10. The connection state can be changed between the third connection states to be supplied. In other words, the output of the control logic circuit 163 and the output of the register circuit 28 are complementarily supplied to the VCO 10 as an amplitude control signal. The on / off operations of the peak detection circuits 160 and 161, the comparator 162, and the control logic circuit 163 are controlled by a switching signal EN_AAC instructing execution / stop of automatic amplitude control. The signal for controlling the switching of the switch 264 and the switching signal EN_AAC may be supplied to the amplitude control circuit 26 from the control unit of the wireless communication apparatus to which the frequency synthesizer 2 is applied, for example.
　次に、周波数シンセサイザ２の動作について図１３を参照して説明する。図１３は、周波数シンセサイザ２の動作の具体例を示す波形図である。まず、自動振幅制御の切替信号ＥＮ＿ＡＡＣが"１"であるとき、第１の実施形態に述べたのと同様の手順で、各通信モードに最適な振幅制御信号ＣＯＤＥ＿ＡＭＰの値が決定される。ここでは、時間Ｔ１～Ｔ４までの動作によって、極微弱電力通信モードでの最適な振幅制御信号が"１００"に決定されている。また、通常電力通信モードのそれは、既に"１１０"と決定されていると仮定する。そして、各通信モードに最適な振幅制御制御信号の値はレジスタ回路２８に保持される。時間Ｔ５において自動振幅制御の切替信号ＥＮ＿ＡＡＣが"０"に変化すると、振幅制御回路２６の動作が停止するとともに、制御信号ＣＯＤＥ＿ＲＥＦに従ってレジスタ回路２８から対応する振幅制御信号ＣＯＤＥ＿ＡＭＰの値が読み出される。このように、レジスタ回路２８に保持された値によってＶＣＯ１０の出力信号振幅の制御が継続される。 Next, the operation of the frequency synthesizer 2 will be described with reference to FIG. FIG. 13 is a waveform diagram showing a specific example of the operation of the frequency synthesizer 2. First, when the automatic amplitude control switching signal EN_AAC is “1”, the optimum value of the amplitude control signal CODE_AMP for each communication mode is determined by the same procedure as described in the first embodiment. Here, the optimum amplitude control signal in the very weak power communication mode is determined to be “100” by the operation from time T1 to T4. Further, it is assumed that the normal power communication mode is already determined as “110”. The value of the amplitude control control signal optimum for each communication mode is held in the register circuit 28. When the automatic amplitude control switching signal EN_AAC changes to "0" at time T5, the operation of the amplitude control circuit 26 is stopped and the value of the corresponding amplitude control signal CODE_AMP is read from the register circuit 28 in accordance with the control signal CODE_REF. Thus, the control of the output signal amplitude of the VCO 10 is continued by the value held in the register circuit 28.
　周波数シンセサイザ２は、レジスタ回路２８に最適な振幅制御信号の値が保持された後は、周波数シンセサイザ１に比べて高速にＶＣＯ１０の振幅を切り替えることができる。またこの際、振幅制御回路２６の動作に必要とされる電力を削減できる。 The frequency synthesizer 2 can switch the amplitude of the VCO 10 at a higher speed than the frequency synthesizer 1 after the optimum amplitude control signal value is held in the register circuit 28. At this time, the power required for the operation of the amplitude control circuit 26 can be reduced.
　なお、図１１には、制御信号ＣＯＤＥ＿ＲＥＦをレジスタ回路２８に供給する構成を示した。しかしながら、レジスタ回路に含まれる複数のレジスタ要素の中から１のレジスタ要素を選択するためのアドレス信号を制御信号ＣＯＤＥ＿ＲＥＦに基づいて生成する回路をさらに備えてもよい。このとき、レジスタ回路２８は、例えば、各々が１つの振幅制御信号ＣＯＤＥ＿ＡＭＰの値を保持可能な複数のレジスタ要素と、アドレス信号をデコードして１つのレジスタ要素を選択するデコード回路を有していればよい。このような構成によっても、アドレス信号をレジスタ回路２８に供給することでレジスタ回路２８に含まれる１のレジスタ要素に保持された振幅制御信号ＣＯＤＥ＿ＡＭＰの値を読み出すことができる。 FIG. 11 shows a configuration in which the control signal CODE_REF is supplied to the register circuit 28. However, a circuit that generates an address signal for selecting one register element from the plurality of register elements included in the register circuit based on the control signal CODE_REF may be further provided. At this time, the register circuit 28 has, for example, a plurality of register elements each capable of holding the value of one amplitude control signal CODE_AMP, and a decode circuit that decodes the address signal and selects one register element. That's fine. Even with such a configuration, the value of the amplitude control signal CODE_AMP held in one register element included in the register circuit 28 can be read by supplying the address signal to the register circuit 28.
＜第３の実施の形態＞
　図１４は、本実施形態にかかる周波数シンセサイザ３の構成を示すブロック図である。周波数シンセサイザ３は、上述した周波数シンセサイザ１の構成に加えて、ロック判定回路３８及び制御ロジック回路３９を有する。ロック判定回路３８は、分周器３１からの出力信号および参照クロック信号Ｆ＿ＲＥＦとの周波数差及び位相差の少なくとも一方を比較判定する。制御ロジック回路３９は、ロック判定回路３８の判定結果を演算して分周器３１の感度特性を制御する感度制御信号ＣＯＤＥ＿ＳＥＮＳを出力する。 <Third Embodiment>
FIG. 14 is a block diagram showing the configuration of the frequency synthesizer 3 according to the present embodiment. The frequency synthesizer 3 includes a lock determination circuit 38 and a control logic circuit 39 in addition to the configuration of the frequency synthesizer 1 described above. The lock determination circuit 38 compares and determines at least one of the frequency difference and the phase difference between the output signal from the frequency divider 31 and the reference clock signal F_REF. The control logic circuit 39 outputs a sensitivity control signal CODE_SENS that calculates the determination result of the lock determination circuit 38 and controls the sensitivity characteristic of the frequency divider 31.
　図１５は、感度可変分周器３１の具体的な構成例を示す回路図である。２段のＤフリップフロップ（ＤＦＦ）３１０及び３１１が図１５のように接続されることで、クロック端子に入力されるＶＣＯ１０の出力信号の周波数が４分周される。具体的に述べると、前段のＤＦＦ３１０の出力端子（Ｑ端子）と後段のＤＦＦ３１１のデータ端子（Ｄ端子）が接続されている。また、後段のＤＦＦ３１１の反転出力端子（ＱＢ端子）と前段のＤＦＦ３１０のデータ端子（Ｄ端子）が接続されている。 FIG. 15 is a circuit diagram showing a specific configuration example of the variable sensitivity frequency divider 31. By connecting the two-stage D flip-flops (DFF) 310 and 311 as shown in FIG. 15, the frequency of the output signal of the VCO 10 input to the clock terminal is divided by four. More specifically, the output terminal (Q terminal) of the preceding DFF 310 and the data terminal (D terminal) of the subsequent DFF 311 are connected. Further, the inverting output terminal (QB terminal) of the subsequent stage DFF 311 and the data terminal (D terminal) of the preceding stage DFF 310 are connected.
　ＤＦＦ３１０と３１１の間には、スイッチ容量アレイ３１２が配置されている。感度制御信号ＣＯＤＥ＿ＳＥＮＳに応じてスイッチ容量アレイ３１２内の各スイッチのオン/オフが切り替えられることで、ＤＦＦ３１０と３１１の間に接続される容量が変更される。これにより、分周器３１のフリーラン周波数が切替えられる。４分周器以外の構成においても、図１５と同様にスイッチ容量アレイ３１２が配置されることで、分周器３１のフリーラン周波数の切替えが可能である。 A switch capacitor array 312 is disposed between the DFFs 310 and 311. The capacitance connected between the DFFs 310 and 311 is changed by turning on / off each switch in the switch capacitance array 312 according to the sensitivity control signal CODE_SENS. Thereby, the free run frequency of the frequency divider 31 is switched. Even in configurations other than the four-frequency divider, the free-run frequency of the frequency divider 31 can be switched by arranging the switch capacitor array 312 as in FIG.
　図１６は、比較のために感度固定分周器の一般的な周波数特性を示した参考グラフである。通常電力通信モードでは、ＶＣＯ１０の振幅が大きいため、分周器の感度特性が下に凸である図示される特性であっても、分周動作が可能な領域が広いため問題とはなりにくい。しかし、極微弱電力通信モードでは、ＶＣＯ１０の振幅を小さくしなければならないため、その分周動作可能な周波数領域が狭まる。図１６の例では、分周動作可能な周波数領域がＦ１１～Ｆ１２の間に制限される。例えば、ＵＷＢ（Ultra Wide Band）用の周波数シンセサイザのように、広範囲に渡って周波数を生成しなければならない場合には特に問題となる。 FIG. 16 is a reference graph showing a general frequency characteristic of a fixed sensitivity frequency divider for comparison. In the normal power communication mode, since the amplitude of the VCO 10 is large, even if the sensitivity characteristic of the frequency divider is convex downward, the characteristic shown in FIG. However, in the extremely weak power communication mode, since the amplitude of the VCO 10 must be reduced, the frequency region in which the frequency dividing operation can be performed is narrowed. In the example of FIG. 16, the frequency region in which the frequency division operation is possible is limited between F11 and F12. For example, this is particularly a problem when the frequency must be generated over a wide range, such as a frequency synthesizer for UWB (Ultra Wide Band).
　図１７は、図１５に示した感度可変分周器３１の周波数特性を示すグラフである。分周器３１のフリーラン周波数が切替えられることによって、図１７に破線の曲線Ｌ１で示す周波数特性（分周動作可能な周波数領域Ｆ１１～Ｆ１２）から太実線の曲線Ｌ３で示す周波数特性（分周動作可能な周波数領域Ｆ２１～Ｆ２２）に変化する。このように、分周動作可能な周波数領域Ｆ２１～Ｆ２２を、ＶＣＯ１０の動作周波数（つまり、ＰＬＬのロック周波数Ｆ＿ＬＯＣＫ）を含むように変化させることで、微弱電力通信モードにおけるＶＣＯ１０の小振幅出力によっても、分周器３１が正常に動作できる。 FIG. 17 is a graph showing the frequency characteristics of the variable sensitivity frequency divider 31 shown in FIG. When the free-run frequency of the frequency divider 31 is switched, the frequency characteristic (frequency division) shown by the thick solid line L3 from the frequency characteristic (frequency range F11 to F12 in which frequency division is possible) shown in FIG. The frequency range is changed to an operable frequency region F21 to F22). As described above, by changing the frequency region F21 to F22 in which the frequency division operation is possible so as to include the operation frequency of the VCO 10 (that is, the lock frequency F_LOCK of the PLL), even by the small amplitude output of the VCO 10 in the weak power communication mode. The frequency divider 31 can operate normally.
　図１８は、感度可変分周器３１の他の構成例を示す回路図である。ＤＦＦ３１０及び３１１の接続関係は図１５と同じである。このため、入力されたＶＣＯ１０の出力信号の周波数は４分周される。図１７の構成例では、ＤＦＦ３１０及び３１１のクロック端子の前段に利得可変アンプ３１３が配置されている。利得可変アンプ３１３は、ＤＦＦ３１０及び３１１のクロック端子に入力されるＶＣＯ１０の出力信号を増幅する。利得可変アンプ３１３のゲインは、感度制御信号ＣＯＤＥ＿ＳＥＮＳに応じて切替えられる。図１７の構成によれば、ＤＦＦ３１０及び３１１のクロック端子に入力される周波数が同じであっても、利得可変アンプ３１３のゲイン調整によって分周器３１の入力感度特性を切り替えることができる。 FIG. 18 is a circuit diagram showing another configuration example of the sensitivity variable frequency divider 31. The connection relationship between the DFFs 310 and 311 is the same as in FIG. For this reason, the frequency of the output signal of the input VCO 10 is divided by four. In the configuration example of FIG. 17, a variable gain amplifier 313 is arranged in front of the clock terminals of the DFFs 310 and 311. The variable gain amplifier 313 amplifies the output signal of the VCO 10 input to the clock terminals of the DFFs 310 and 311. The gain of the variable gain amplifier 313 is switched according to the sensitivity control signal CODE_SENS. According to the configuration of FIG. 17, even if the frequencies input to the clock terminals of the DFFs 310 and 311 are the same, the input sensitivity characteristic of the frequency divider 31 can be switched by adjusting the gain of the variable gain amplifier 313.
　図１９は、図１８に示した感度可変分周器３１の周波数特性を示すグラフである。利得可変アンプ３１３が高ゲインに変更されることで、図１９に破線の曲線Ｌ１で示す周波数特性（分周動作可能な周波数領域Ｆ１１～Ｆ１２）から太実線の曲線Ｌ５で示す周波数特性（分周動作可能な周波数領域Ｆ３１～Ｆ３２）に変化する。特性グラフが振幅軸に沿って下向きに下がっていくことで、微弱電力通信モードにおけるＶＣＯ１０の小振幅出力によっても、分周器３１が正常に動作できる。 FIG. 19 is a graph showing the frequency characteristics of the variable sensitivity frequency divider 31 shown in FIG. When the variable gain amplifier 313 is changed to a high gain, the frequency characteristic (frequency division) indicated by the thick solid curve L5 from the frequency characteristic indicated by the broken curve L1 (frequency regions F11 to F12 in which frequency division operation is possible) in FIG. The operating frequency range F31 to F32) is changed. Since the characteristic graph is lowered along the amplitude axis, the frequency divider 31 can operate normally even by the small amplitude output of the VCO 10 in the weak power communication mode.
　次に、周波数シンセサイザ３の動作について図２０を参照して説明する。図２０は、周波数シンセサイザ３の動作の具体例を示す波形図である。まず、時間Ｔ１～Ｔ４では、第１の実施の形態で述べたのと同様に、ＶＣＯ１０の振幅制御ループが収束するまで実行される。振幅制御ループが収束した後、分周器３１の入力感度制御のループが開始される（時間Ｔ５）。ここでは、感度制御信号ＣＯＤＥ＿ＳＥＮＳの初期設定値が"０００"であるとする。このとき、ロック判定回路３８の判定結果ＬＤは"０"である。このため、分周器３１が正常動作していないと判断されて、次の感度制御信号ＣＯＤＥ＿ＳＥＮＳの値が"００１"に変更される（時間Ｔ６）。時間Ｔ６においても、ロック判定回路３８の判定結果ＬＤが"０"であるため、さらに次の感度制御信号ＣＯＤＥ＿ＳＥＮＳの値が"０１０"へ変更される（時間Ｔ７）。時間Ｔ７では、ロック判定回路３８の判定結果ＬＤが"１"となる。つまり、分周器３１が正常動作していると判断され、分周器３１の入力感度制御ループが終了する。 Next, the operation of the frequency synthesizer 3 will be described with reference to FIG. FIG. 20 is a waveform diagram showing a specific example of the operation of the frequency synthesizer 3. First, at times T1 to T4, as described in the first embodiment, the process is executed until the amplitude control loop of the VCO 10 converges. After the amplitude control loop has converged, an input sensitivity control loop of the frequency divider 31 is started (time T5). Here, it is assumed that the initial setting value of the sensitivity control signal CODE_SENS is “000”. At this time, the determination result LD of the lock determination circuit 38 is “0”. Therefore, it is determined that the frequency divider 31 is not operating normally, and the value of the next sensitivity control signal CODE_SENS is changed to “001” (time T6). Also at time T6, since the determination result LD of the lock determination circuit 38 is “0”, the value of the next sensitivity control signal CODE_SENS is further changed to “010” (time T7). At time T7, the determination result LD of the lock determination circuit 38 is “1”. That is, it is determined that the frequency divider 31 is operating normally, and the input sensitivity control loop of the frequency divider 31 ends.
　図２０では、感度制御信号ＣＯＤＥ＿ＳＥＮＳの最小値"０００"を初期値とし、感度制御信号ＣＯＤＥ＿ＳＥＮＳの値を初期値から徐々に増大させることで、分周器３１の感度調整を行う例を示した。しかしながら、このような方法は一例に過ぎない。例えば、感度制御信号ＣＯＤＥ＿ＳＥＮＳの最大値を初期値に設定し、感度制御信号ＣＯＤＥ＿ＳＥＮＳの値を初期値から徐々に減少させてもよい。また、二分探索などの公知の探索手法を用いて感度制御信号ＣＯＤＥ＿ＳＥＮＳの収束値を探索してもよい。 FIG. 20 shows an example in which the sensitivity adjustment of the frequency divider 31 is performed by setting the minimum value “000” of the sensitivity control signal CODE_SENS as an initial value and gradually increasing the value of the sensitivity control signal CODE_SENS from the initial value. However, such a method is only an example. For example, the maximum value of the sensitivity control signal CODE_SENS may be set to an initial value, and the value of the sensitivity control signal CODE_SENS may be gradually decreased from the initial value. Further, the convergence value of the sensitivity control signal CODE_SENS may be searched using a known search method such as binary search.
　また、本実施の形態は、上述した第２の実施の形態と組み合わせることも可能である。また、第２の実施の形態で述べた振幅制御信号ＣＯＤＥ＿ＡＭＰの最適値を格納するレジスタ回路２８を配置する構成を応用して、感度制御信号ＣＯＤＥ＿ＳＥＮＳの最適値の格納・読み出しが可能なレジスタ回路を配置してもよい。これにより、高速な通信モード切り替えが可能となる。特に、ＵＷＢのように、周波数シンセサイザのロック周波数が複数必要とされる場合に有効である。 Also, this embodiment can be combined with the second embodiment described above. A register circuit capable of storing / reading the optimum value of the sensitivity control signal CODE_SENS by applying the configuration in which the register circuit 28 for storing the optimum value of the amplitude control signal CODE_AMP described in the second embodiment is applied. You may arrange. Thereby, high-speed communication mode switching becomes possible. This is particularly effective when a plurality of frequency synthesizer lock frequencies are required, such as UWB.
　本実施の形態にかかる周波数シンセサイザ３は、極微弱電力通信モードにおいてＶＣＯ１０の出力が小振幅となる場合であっても、上述した周波数シンセサイザ１に比べて広い発振周波数範囲で動作することができる。 The frequency synthesizer 3 according to the present embodiment can operate in a wider oscillation frequency range than the frequency synthesizer 1 described above even when the output of the VCO 10 has a small amplitude in the extremely weak power communication mode.
＜第４の実施の形態＞
　図２１は、本実施形態にかかる周波数シンセサイザ４の構成を示すブロック図である。周波数シンセサイザ４は、上述した周波数シンセサイザ１の構成に加えて、分周器１１、位相・周波数比較器１２、チャージポンプ１３、バッファ１５に対する振幅制御回路４１～４４及び参照信号発生回路４５～４８を有する。通信モードの切り替えを指示する制御信号ＣＯＤＥ＿ＲＥＦに応じて、これらの各ブロックの出力信号振幅が変更される。なお、各ブロックの振幅は必ずしも一致しなくてもよい。図２２は、オペアンプ４１０を用いたリニア電圧レギュレータによる振幅制御回路４１の構成例を示す。図２２の回路構成は、他の振幅制御回路４２～４４にも適用できる。 <Fourth embodiment>
FIG. 21 is a block diagram showing a configuration of the frequency synthesizer 4 according to the present embodiment. In addition to the configuration of the frequency synthesizer 1 described above, the frequency synthesizer 4 includes amplitude control circuits 41 to 44 and reference signal generation circuits 45 to 48 for the frequency divider 11, the phase / frequency comparator 12, the charge pump 13, and the buffer 15. Have. The output signal amplitude of each block is changed according to the control signal CODE_REF instructing switching of the communication mode. Note that the amplitudes of the blocks do not necessarily match. FIG. 22 shows a configuration example of the amplitude control circuit 41 using a linear voltage regulator using the operational amplifier 410. The circuit configuration of FIG. 22 can be applied to the other amplitude control circuits 42 to 44.
　周波数シンセサイザ４は、上述した周波数シンセサイザ１に比べて、ＶＣＯ１０以外の回路ブロックで発生されるスプリアスの調整ができるという利点がある。 The frequency synthesizer 4 has an advantage that it can adjust spurious generated in a circuit block other than the VCO 10 as compared with the frequency synthesizer 1 described above.
＜第５の実施の形態＞
　図２３は、本実施形態にかかる周波数シンセサイザ５の構成を示すブロック図である。周波数シンセサイザ５は、上述した周波数シンセサイザ３の構成に加えて、分周器３１、位相・周波数比較器１２、チャージポンプ１３、バッファ１５に対する振幅制御回路４１～４４及び参照信号発生回路４５～４８を有する。通信モードの切り替えを指示する制御信号ＣＯＤＥ＿ＲＥＦに応じて、これらの各ブロックの出力信号振幅が変更される。なお、各ブロックの振幅は必ずしも一致しなくてもよい。 <Fifth embodiment>
FIG. 23 is a block diagram showing a configuration of the frequency synthesizer 5 according to the present embodiment. The frequency synthesizer 5 includes, in addition to the configuration of the frequency synthesizer 3 described above, an amplitude control circuit 41 to 44 and a reference signal generation circuit 45 to 48 for the frequency divider 31, the phase / frequency comparator 12, the charge pump 13, and the buffer 15. Have. The output signal amplitude of each block is changed according to the control signal CODE_REF instructing switching of the communication mode. Note that the amplitudes of the blocks do not necessarily match.
　周波数シンセサイザ５は、上述した周波数シンセサイザ３に比べて、ＶＣＯ１０以外の回路ブロックで発生されるスプリアスの調整ができるという利点がある。 The frequency synthesizer 5 has an advantage that the spurious generated in the circuit block other than the VCO 10 can be adjusted as compared with the frequency synthesizer 3 described above.
＜その他の実施の形態＞
　上述した各実施の形態で述べたＶＣＯ１０の発振周波数をロックするためのＰＬＬの回路構成が一例に過ぎないことは勿論である。ＶＣＯ１０の発振周波数をロックするためのＰＬＬが様々に変形可能であることは既に良く知られている。本発明は、公知の様々なＰＬＬを有する周波数シンセサイザに対して適用可能である。 <Other embodiments>
Of course, the PLL circuit configuration for locking the oscillation frequency of the VCO 10 described in the above embodiments is merely an example. It is already well known that the PLL for locking the oscillation frequency of the VCO 10 can be variously modified. The present invention is applicable to frequency synthesizers having various known PLLs.
　以上、実施の形態を参照して本願発明を説明したが、本願発明は上記によって限定されるものではない。本願発明の構成や詳細には、発明のスコープ内で当業者が理解し得る様々な変更をすることができる。 The present invention has been described above with reference to the embodiment, but the present invention is not limited to the above. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the invention.
　この出願は、２００８年１１月１３日に出願された日本出願特願２００８－２９０９３３を基礎とする優先権を主張し、その開示の全てをここに取り込む。 This application claims priority based on Japanese Patent Application No. 2008-290933 filed on November 13, 2008, the entire disclosure of which is incorporated herein.
１、２、３、４、５　ＰＬＬ周波数シンセサイザ
１０　電圧制御発振器（ＶＣＯ）
１１　分周器
１２　位相・周波数比較器
１３　チャージポンプ
１４　ローパスフィルタ
１５　バッファ
１６、２６　振幅制御回路
１７　参照信号発生回路
１８　ＰＬＬ回路
２８　レジスタ
３１　感度可変分周器
３８　ロック判定回路
３９　制御ロジック回路
４１～４４　振幅制御回路
４５～４８　参照信号発生回路
１００　インダクタ
１０１、１０２　バラクタ（可変容量素子）
１０３　キャパシタアレイ
１０４、１０５、１０６、１０７　スイッチ
Ｍ１、Ｍ２、Ｍ５～Ｍ８　ＮチャネルＭＯＳトランジスタ
Ｍ３、Ｍ４　ＰチャネルＭＯＳトランジスタ
１６０、１６１　ピーク検出回路
１６２　コンパレータ
１６３　制御ロジック回路
１６４　オペアンプ
１８０　制御部
１８１　デジタルベースバンド処理部
１８２　Ｄ／Ａコンバータ
１８３　ミキサ
１８４　バンドパスフィルタ
１８５　送信パワーアンプ
１８６　デュプレクサ
１８７　アンテナ
１８８　低雑音アンプ
１８９　バンドパスフィルタ
１９０　直交ミキサ
１９１　ローパスフィルタ
１９２　Ａ／Ｄコンバータ
２６４　スイッチ
３１０、３１１　Ｄフリップフロップ（ＤＦＦ）
３１２　キャパシタアレイ
３１３　利得可変アンプ
４１０　オペアンプ
Ｍ４１　ＰチャネルＭＯＳトランジスタ 1, 2, 3, 4, 5 PLL frequency synthesizer 10 Voltage controlled oscillator (VCO)
11 Frequency Divider 12 Phase / Frequency Comparator 13 Charge Pump 14 Low Pass Filter 15 Buffer 16, 26 Amplitude Control Circuit 17 Reference Signal Generation Circuit 18 PLL Circuit 28 Register 31 Sensitivity Variable Frequency Divider 38 Lock Determination Circuit 39 Control Logic Circuit 41˜ 44 Amplitude control circuits 45 to 48 Reference signal generation circuit 100 Inductors 101 and 102 Varactors (variable capacitance elements)
103 Capacitor array 104, 105, 106, 107 Switch M1, M2, M5 to M8 N-channel MOS transistor M3, M4 P- channel MOS transistor 160, 161 Peak detection circuit 162 Comparator 163 Control logic circuit 164 Operational amplifier 180 Control unit 181 Digital baseband Processing unit 182 D / A converter 183 Mixer 184 Band pass filter 185 Transmission power amplifier 186 Duplexer 187 Antenna 188 Low noise amplifier 189 Band pass filter 190 Orthogonal mixer 191 Low pass filter 192 A / D converter 264 Switch 310, 311 D flip-flop (DFF) )
312 Capacitor array 313 Variable gain amplifier 410 Operational amplifier M41 P-channel MOS transistor

Claims (20)

  1. 　周波数制御電圧に応じて発振周波数を変更可能であり、振幅制御信号に応じて出力信号振幅を変更可能である電圧制御発振器と、
    　前記電圧制御発振器の出力信号又は前記出力信号を分周した信号と基準周波数信号との比較結果に応じて前記周波数制御電圧を生成するＰＬＬ回路と、
    　前記振幅制御信号を前記電圧制御発振器に供給し、前記出力信号振幅が外部から供給されるモード切り替え信号に対応した大きさとなるよう前記電圧制御発振器を制御する第１の制御回路と、
    を備える周波数シンセサイザ。     A voltage-controlled oscillator that can change the oscillation frequency according to the frequency control voltage, and that can change the output signal amplitude according to the amplitude control signal;
    A PLL circuit that generates the frequency control voltage according to a comparison result between an output signal of the voltage controlled oscillator or a signal obtained by dividing the output signal and a reference frequency signal;
    A first control circuit for supplying the amplitude control signal to the voltage controlled oscillator and controlling the voltage controlled oscillator so that the output signal amplitude has a magnitude corresponding to a mode switching signal supplied from the outside;
    A frequency synthesizer comprising:
  2. 　前記モード切り替え信号は、前記周波数シンセサイザが適用される無線通信装置における無線信号の送信電力が異なる複数の通信モードの間でのモード切り替えに応じて生成される請求項１に記載の周波数シンセサイザ。 The frequency synthesizer according to claim 1, wherein the mode switching signal is generated in accordance with mode switching between a plurality of communication modes having different radio signal transmission powers in a radio communication apparatus to which the frequency synthesizer is applied.
  3. 　前記第１の制御回路は、
    　前記モード切り替え信号に応じて参照信号を生成する参照信号生成回路と、
    　前記電圧制御発振器の出力信号及び前記参照信号を入力し、前記出力信号と前記電圧参照信号との比較結果に応じて前記振幅制御信号を生成する振幅制御回路と、
    を備える請求項１又は２に記載の周波数シンセサイザ。     The first control circuit includes:
    A reference signal generation circuit for generating a reference signal in response to the mode switching signal;
    An amplitude control circuit that receives the output signal of the voltage controlled oscillator and the reference signal and generates the amplitude control signal according to a comparison result between the output signal and the voltage reference signal;
    A frequency synthesizer according to claim 1 or 2.
  4. 　前記振幅制御回路は、
    　前記出力信号振幅と前記参照信号の信号レベルとを比較してデジタル信号を出力する比較器と、
    　前記デジタル信号に基づいて前記振幅制御信号を生成する第１の制御ロジック回路と、
    を備える請求項３に記載の周波数シンセサイザ。     The amplitude control circuit includes:
    A comparator that compares the output signal amplitude with the signal level of the reference signal and outputs a digital signal;
    A first control logic circuit for generating the amplitude control signal based on the digital signal;
    A frequency synthesizer according to claim 3.
  5. 　前記デジタル信号のビット数が１ビットである請求項４に記載の周波数シンセサイザ。 The frequency synthesizer according to claim 4, wherein the number of bits of the digital signal is one bit.
  6. 　前記第１の制御ロジック回路は、前記振幅制御信号の過去の値から前記デジタル信号の値を減算することで前記振幅制御信号の更新値を生成する減算回路を備える請求項４又は５に記載の周波数シンセサイザ。 The said 1st control logic circuit is provided with the subtraction circuit which produces | generates the update value of the said amplitude control signal by subtracting the value of the said digital signal from the past value of the said amplitude control signal. Frequency synthesizer.
  7. 　前記第１の制御ロジック回路は、前記デジタル信号が前記出力信号振幅と前記参照信号の信号レベルの不一致を示す場合に、複数の候補値の中から二分探索アルゴリズムに基づいて前記電圧参照信号の更新値を決定する二分探索回路を備える請求項４又は５に記載の周波数シンセサイザ。 The first control logic circuit updates the voltage reference signal based on a binary search algorithm from among a plurality of candidate values when the digital signal indicates a mismatch between the output signal amplitude and the signal level of the reference signal. 6. The frequency synthesizer according to claim 4, further comprising a binary search circuit for determining a value.
  8. 　前記電圧制御発振器は、
    　クロスカップルされた一対のＮチャネルトランジスタと、
    　前記一対のＮチャネルトランジスタの出力端子間および前記一対のＰチャネルトランジスタの出力端子間に接続され、前記制御電圧に応じて容量が変更される可変容量素子と、
    　前記一対のＮチャネルトランジスタのソースに共通接続され、前記振幅制御信号に応じてバイアス電流量を変化させる電流源回路と、
    を備える請求項１乃至７のいずれか１項に記載の周波数シンセサイザ。     The voltage controlled oscillator is:
    A pair of cross-coupled N-channel transistors;
    A variable capacitance element connected between the output terminals of the pair of N-channel transistors and between the output terminals of the pair of P-channel transistors, the capacitance of which is changed according to the control voltage;
    A current source circuit connected in common to the sources of the pair of N-channel transistors and changing a bias current amount in accordance with the amplitude control signal;
    A frequency synthesizer according to claim 1, comprising:
  9. 　前記モード切り替え信号に対応して前記第１の制御回路によって生成された前記振幅制御信号の値を格納するとともに、前記モード切り替え信号に基づいて自身が格納している前記振幅制御信号の値を出力するレジスタ回路をさらに備える請求項１乃至８のいずれか１項に記載の周波数シンセサイザ。 Stores the value of the amplitude control signal generated by the first control circuit in response to the mode switching signal, and outputs the value of the amplitude control signal stored by itself based on the mode switching signal The frequency synthesizer according to any one of claims 1 to 8, further comprising a register circuit.
  10. 　前記第１の制御回路と前記レジスタ回路とが相補的に前記電圧制御発振器へ前記振幅制御信号を供給する請求項９に記載の周波数シンセサイザ。 10. The frequency synthesizer according to claim 9, wherein the first control circuit and the register circuit supply the amplitude control signal to the voltage controlled oscillator in a complementary manner.
  11. 　前記レジスタ回路は、前記モード切り替え信号によって指定される複数のモードに対応して、前記振幅制御信号の複数の値を格納可能である請求項９又は１０に記載の周波数シンセサイザ。 The frequency synthesizer according to claim 9 or 10, wherein the register circuit can store a plurality of values of the amplitude control signal in correspondence with a plurality of modes specified by the mode switching signal.
  12. 　前記ＰＬＬ回路は、前記電圧制御発振器の出力信号を分周する分周器を含み、
    　前記周波数シンセサイザは、
    　前記分周器の出力信号と前記基準周波数信号との周波数差及び位相差の少なくとも一方を比較判定するロック判定回路と、
    　前記ロック判定回路の判定結果を演算して前記分周器の感度特性を制御する感度制御信号を生成して前記分周器に供給する第２の制御ロジック回路と
    を備える請求項１乃至１１のいずれか１項に記載の周波数シンセサイザ。     The PLL circuit includes a frequency divider that divides the output signal of the voltage controlled oscillator;
    The frequency synthesizer is
    A lock determination circuit for comparing and determining at least one of a frequency difference and a phase difference between the output signal of the frequency divider and the reference frequency signal;
    The control circuit according to claim 1, further comprising: a second control logic circuit that calculates a determination result of the lock determination circuit and generates a sensitivity control signal that controls sensitivity characteristics of the frequency divider and supplies the sensitivity control signal to the frequency divider. The frequency synthesizer of any one of Claims.
  13. 　前記分周器は、前記分周器の出力端に接続され、前記感度制御信号に応じて容量を変更可能なスイッチ容量アレイを備える請求項１２に記載の周波数シンセサイザ。 13. The frequency synthesizer according to claim 12, wherein the frequency divider includes a switch capacitor array connected to an output terminal of the frequency divider and capable of changing a capacitance according to the sensitivity control signal.
  14. 　前記分周器は、
    　前記電圧制御発振器の出力信号が各々のクロック端子に入力される一対のＤフリップフロップと、
    　各クロック端子に入力される前記電圧制御発振器の出力信号を増幅する増幅器と、
    を備える請求項１２に記載の周波数シンセサイザ。     The frequency divider is
    A pair of D flip-flops to which the output signal of the voltage controlled oscillator is input to each clock terminal;
    An amplifier for amplifying the output signal of the voltage controlled oscillator input to each clock terminal;
    A frequency synthesizer according to claim 12.
  15. 　前記振幅制御信号及び前記感度制御信号の一方の信号が変更される際に、他方の信号が固定される請求項１２乃至１４のいずれか１項に記載の周波数シンセサイザ。 The frequency synthesizer according to any one of claims 12 to 14, wherein when one of the amplitude control signal and the sensitivity control signal is changed, the other signal is fixed.
  16. 　前記ＰＬＬ回路は、前記電圧制御発振器の出力信号を分周する分周器と、前記分周器の出力信号と前記基準周波数信号との位相差を比較する位相比較器と、前記位相比較器の比較結果を直流信号に変換するチャージポンプとを含み、
    　前記周波数シンセサイザは、
    　前記電圧制御発振器の出力信号を増幅するバッファと、
    　前記モード切り替え信号に基づいて、前記分周器、前記位相比較器、前記チャージポンプ及び前記バッファの振幅をそれぞれ切り替える第２～第５の制御回路と、
    をさらに備える請求項１又は２に記載の周波数シンセサイザ。     The PLL circuit includes a frequency divider that divides the output signal of the voltage controlled oscillator, a phase comparator that compares a phase difference between the output signal of the divider and the reference frequency signal, and a phase comparator A charge pump for converting the comparison result into a DC signal,
    The frequency synthesizer is
    A buffer for amplifying the output signal of the voltage controlled oscillator;
    Second to fifth control circuits for switching amplitudes of the frequency divider, the phase comparator, the charge pump, and the buffer based on the mode switching signal;
    The frequency synthesizer according to claim 1, further comprising:
  17. 　前記ＰＬＬ回路は、前記分周器の出力信号と前記基準周波数信号との位相差を比較する位相比較器と、前記位相比較器の比較結果を直流信号に変換するチャージポンプとをさらに含み、
    　前記周波数シンセサイザは、
    　前記電圧制御発振器の出力信号を増幅するバッファと、
    　前記モード切り替え信号に基づいて、前記分周器、前記位相比較器、前記チャージポンプ及び前記バッファの振幅をそれぞれ切り替える第２～第５の制御回路と、
    をさらに備える請求項１２に記載の周波数シンセサイザ。     The PLL circuit further includes a phase comparator that compares a phase difference between the output signal of the frequency divider and the reference frequency signal, and a charge pump that converts a comparison result of the phase comparator into a DC signal.
    The frequency synthesizer is
    A buffer for amplifying the output signal of the voltage controlled oscillator;
    Second to fifth control circuits for switching amplitudes of the frequency divider, the phase comparator, the charge pump, and the buffer based on the mode switching signal;
    The frequency synthesizer of claim 12, further comprising:
  18. 　前記第２～第５の制御回路の各々は、記分周器、前記位相比較器、前記チャージポンプ又は前記バッファに対して制御電圧信号を供給する電圧レギュレータを備える請求項１６又は１７に記載の周波数シンセサイザ。 18. Each of the second to fifth control circuits includes a voltage regulator that supplies a control voltage signal to the frequency divider, the phase comparator, the charge pump, or the buffer. Frequency synthesizer.
  19. 　請求項１に記載の周波数シンセサイザと、
    　前記周波数シンセサイザの出力信号を局部発振信号として用いて通信信号の周波数変換を行うミキサと、
    　前記通信信号の送信電力が異なる複数の通信モードの間でのモード切り替えに応じて前記モード切り替え信号を生成し、前記周波数シンセサイザに供給する制御手段と、
    を備える無線通信装置。     A frequency synthesizer according to claim 1;
    A mixer that performs frequency conversion of a communication signal using an output signal of the frequency synthesizer as a local oscillation signal;
    Control means for generating the mode switching signal in response to mode switching between a plurality of communication modes having different transmission powers of the communication signal, and supplying the mode switching signal to the frequency synthesizer;
    A wireless communication device comprising:
  20. 　周波数シンセサイザと、前記周波数シンセサイザの出力信号を局部発振信号として用いて通信信号の周波数変換を行うミキサとを備える無線通信装置の制御方法であって、
    　前記通信信号の送信電力が異なる複数の通信モードの間でのモード切り替えに応じてモード切り替え信号を生成し、
    　前記モード切り替え信号を前記周波数シンセサイザに供給し、前記周波数シンセサイザに含まれる電圧制御発振器の出力信号振幅の大きさを前記通信信号の送信電力の大きさに応じて変更する、制御方法。     A control method of a wireless communication device comprising a frequency synthesizer and a mixer that performs frequency conversion of a communication signal using an output signal of the frequency synthesizer as a local oscillation signal,
    A mode switching signal is generated according to mode switching between a plurality of communication modes having different transmission powers of the communication signal,
    A control method, wherein the mode switching signal is supplied to the frequency synthesizer, and the magnitude of the output signal amplitude of the voltage controlled oscillator included in the frequency synthesizer is changed according to the magnitude of the transmission power of the communication signal.
PCT/JP2009/005639 2008-11-13 2009-10-26 Frequency synthesizer, radio communication device, and radio communication device control method WO2010055619A1 (en)

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JP2008205601A (en) * 2007-02-16 2008-09-04 Matsushita Electric Ind Co Ltd Pll circuit and radio device provided with the same

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JP2012060644A (en) * 2010-09-10 2012-03-22 Fujitsu Semiconductor Ltd Analog-digital converter, receiver, and radio communication apparatus
JP2016046607A (en) * 2014-08-21 2016-04-04 横河電機株式会社 Self-excited oscillation circuit
US9742417B1 (en) 2016-02-10 2017-08-22 Yokogawa Electric Corporation Self-oscillation circuit
KR20200008278A (en) * 2018-07-16 2020-01-28 삼성전자주식회사 RF integrated circuit including local oscillator and operating method thereof
KR102618561B1 (en) * 2018-07-16 2023-12-27 삼성전자주식회사 RF integrated circuit including local oscillator and operating method thereof
WO2020156647A1 (en) * 2019-01-30 2020-08-06 Telefonaktiebolaget Lm Ericsson (Publ) Tuning range enhancement by negative resistance
WO2023135919A1 (en) * 2022-01-12 2023-07-20 ソニーセミコンダクタソリューションズ株式会社 Calibration circuit

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