WO2010047474A2 - Source driver integrated circuit that enables multipaired data interface, and display panel driving system including the source driver integrated circuit - Google Patents

Source driver integrated circuit that enables multipaired data interface, and display panel driving system including the source driver integrated circuit Download PDF

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WO2010047474A2
WO2010047474A2 PCT/KR2009/005364 KR2009005364W WO2010047474A2 WO 2010047474 A2 WO2010047474 A2 WO 2010047474A2 KR 2009005364 W KR2009005364 W KR 2009005364W WO 2010047474 A2 WO2010047474 A2 WO 2010047474A2
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data
source driver
driver integrated
pair
integrated circuit
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PCT/KR2009/005364
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French (fr)
Korean (ko)
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WO2010047474A3 (en
WO2010047474A4 (en
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서정일
김언영
나준호
김대성
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(주)실리콘웍스
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G5/006—Details of the interface to the display terminal
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/30—Definitions, standards or architectural aspects of layered protocol stacks
    • H04L69/32—Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/08—Details of image data interface between the display device controller and the data line driver circuit

Definitions

  • the present invention relates to a source driver integrated circuit for driving a display panel, and more particularly, to a source driver integrated circuit capable of a multi-pair data interface and a display panel driving system including the integrated circuit.
  • the source driver integrated circuit performs a function of transferring image data received from a timing controller to a display panel.
  • the noise component introduced by the electrical characteristics of the transmission line may alter the logical value of the image data transmitted and received.
  • a recent display panel driving system does not transmit image data as it is, but converts the image data into differential image data signals and transmits and receives them as a single data signal by transmitting and receiving them through two transmission lines. Minimize transmission and reception errors that may occur. Therefore, differential image data driving one pixel is transferred to the source driver integrated circuit through two transmission lines.
  • the source driver IC processes the differential image data received from the timing control circuit, converts the image data into original image data, and transmits the first image data to the display panel.
  • the number of source driver integrated circuits used is determined according to the size of the display panel.
  • 1 is an embodiment of a display panel driving system including a source driver integrated circuit driving M pixels.
  • FIG. 2 is an embodiment of a display panel driving system having a source driver integrated circuit driving N pixels.
  • the timing control circuit 110 may also source M pairs of differential image data. Transfer to driver integrated circuit (120, 130).
  • the timing control circuit 210 may also store N pairs of differential image data. 220, 230).
  • the internal structure of the source driver integrated circuits 120 and 130 shown in FIG. 1 is shown in FIG.
  • the internal structure of the source driver integrated circuits 220 and 230 are different from each other. That is, the source driver integrated circuits 120 and 130 shown in FIG. 1 are all designed to receive M pairs of differential image data, and the source driver integrated circuits 220 and 230 shown in FIG. 2 are all N pairs.
  • the input terminal is designed to receive differential image data. Therefore, the two types of source driver integrated circuits cannot be used interchangeably due to the same function but different internal structures.
  • the source driver integrated circuit must be newly designed according to the number of pairs of differential image data output from the timing control circuit.
  • the present invention has been made in an effort to provide a display panel driving system capable of driving a display panel regardless of the number of differential image data pairs output from a timing control circuit.
  • Another technical problem to be solved by the present invention is to provide a source driver integrated circuit capable of driving a display panel regardless of the number of differential image data pairs output from the timing control circuit.
  • a display panel driving system including a timing control circuit for outputting data of M pairs (M is an integer) and data of N pairs (N is an integer less than M) and the data of the M pairs.
  • a driver block having a plurality of source driver integrated circuits for receiving the N pairs of data to drive the display panel.
  • a source driver integrated circuit may receive serial data of M (M is an integer) pair and serial data of N (N is an integer less than M) pair to receive M ⁇ K (K Outputs parallel data of an integer) bit, and receives the M pair of serial data and the N pair of serial data and converts the M pair of serial data into M ⁇ K bits of parallel data and the M ⁇ K bits of parallel data. And a data alignment circuit for sorting and outputting data.
  • a source driver integrated circuit may receive serial data of M (M is an integer) pair and serial data of N (N is an integer less than M) pair to receive M ⁇ K ( K outputs parallel data of an integer) bit and receives the M pair of serial data and the N pair of serial data, and converts the serial data into M ⁇ K bit parallel data or N ⁇ K bit parallel data.
  • a multi-pair data alignment circuit for sorting the parallel data of MxK bits and the parallel data of NxK bits and outputting the parallel data of MxK bits.
  • the present invention has an advantage that the source driver integrated circuit capable of processing M pairs of differential image data can simultaneously process fewer pairs of differential image data than M, so that the source driver integrated circuit can be used as it is without newly designing it. .
  • 1 is an embodiment of a display panel driving system including a source driver integrated circuit driving M pixels.
  • FIG. 2 is an embodiment of a display panel driving system including a source driver integrated circuit driving N pixels.
  • FIG 3 is an embodiment of a display panel driving system according to the present invention.
  • FIG. 4 is an embodiment of a source driver integrated circuit according to the present invention.
  • FIG 5 is another embodiment of a source driver integrated circuit according to the present invention.
  • FIG 3 is an embodiment of a display panel driving system according to the present invention.
  • the display panel driving system 300 may process differential image data of less than M (N is integer) pair as well as differential image data of M (M is integer) pair. That is, the timing control circuit 310 may output M pairs of differential image data to the source driver integrated circuits 320 and 330. In some cases, the timing control circuit 310 may output N pairs of differential image data to the source driver integrated circuits 320 and 330. You can also print to The source driver integrated circuit is commonly used regardless of the number of pairs of differential image data output from the timing control circuit 310.
  • the source driver integrated circuits 320 and 330 can process the data regardless of the number of pairs of differential image data.
  • Source driver integrated circuits 320 and 330 capable of processing the multi-pair differential image data will be described with reference to FIGS. 4 and 5.
  • FIG. 4 is an embodiment of a source driver integrated circuit according to the present invention.
  • the source driver integrated circuit 400 includes a multi-pair serial and parallel converter 410 and a data alignment circuit 420.
  • the multi-pair serial-parallel converter 410 converts not only M pairs of serial differential data but also N pairs of serial differential data smaller than M into parallel differential data of M ⁇ K (K is an integer) bits.
  • the data sorting circuit 420 sorts MxK bits of parallel differential data. K is the number of bits of the image data representing one pixel.
  • FIG 5 is another embodiment of a source driver integrated circuit according to the present invention.
  • the source driver integrated circuit 500 includes a serial and parallel converter 510 and a multi-pair data alignment circuit 520.
  • the serial-parallel converter 510 converts M pairs of serial differential data into M ⁇ K bits of parallel differential data, and N pairs of serial differential data less than M are converted into N ⁇ K bits of parallel differential data, respectively.
  • the multi-pair data alignment circuit 520 sorts not only MxK bits of parallel differential data but also NxK bits of parallel differential data into MxK bits of parallel differential data. K is the number of bits of the image data representing one pixel.
  • the source driver integrated circuit according to the present invention can process up to M pairs of differential image data, and when less than M pairs of differential image data are inputted, a serial-parallel converter or data alignment. This is preprocessed in one functional block of the circuit so that subsequent functional blocks can process this regardless of the number of pairs of differential image data received.
  • the above-described preprocessing is performed by the multi-pair serial-parallel converter 410, and in the case of the source driver integrated circuit 500 illustrated in FIG. 5, the multi-pair data alignment circuit. Perform at 520.
  • the source driver integrated circuits shown in FIGS. 4 and 5 are not composed of only the serial-parallel converter or data alignment circuit as described above, but there are many more functional blocks. However, this part is well known to those skilled in the art and does not affect the operation of the present invention. For this reason, this part has not been added to the drawings or described, but it does not matter for the technical idea of the present invention.
  • the source driver integrated circuit according to the present invention has the advantage that it is possible to use a general purpose irrespective of the pair of the differential image data received, it is possible to shorten the design convenience and development period.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

The present invention introduces a display panel driving system and source driver ICs (Integrated Circuits) to drive a display panel regardless of the amount of paired differential image data outputted from a timing control circuit. The display panel driving system according to the invention comprises a driver block that includes: the timing control circuit that outputs M paired data (M is an integer) and N paired data (N is an integer smaller than M), and the plural source driver ICs that receive the M or N paired data to drive a display panel. The source driver ICs receive the M or N paired serial data and output the parallel data of M×K bits (K is an integer). In addition, the source driver ICs comprise: multipaired serial-parallel converters that receive the M or N paired serial data and convert the received serial data into parallel data, and a data arrangement circuit that arranges and outputs the parallel data of M×K bits.

Description

멀티 페어 데이터 인터페이스가 가능한 소스 드라이버 집적회로 및 상기 소스 드라이버 집적회로를 구비하는 디스플레이 패널 구동시스템Display driver system including a source driver integrated circuit capable of a multi-pair data interface and the source driver integrated circuit
본 발명은 디스플레이 패널을 구동하는 소스 드라이버 집적회로에 관한 것으로, 특히 멀티 페어 데이터 인터페이스가 가능한 소스 드라이버 집적회로 및 상기 집적회로를 구비하는 디스플레이 패널 구동시스템에 관한 것이다. The present invention relates to a source driver integrated circuit for driving a display panel, and more particularly, to a source driver integrated circuit capable of a multi-pair data interface and a display panel driving system including the integrated circuit.
소스 드라이버 집적회로(source driver integrated circuit)는 타이밍 제어회로(timing controller)로부터 수신한 영상데이터를 디스플레이 패널에 전달하는 기능을 수행한다. 상기 영상데이터가 하나의 전송라인을 통해 송수신 될 때, 전송라인의 전기적 특성에 의해 유입되는 잡음성분이 송수신되는 영상데이터의 논리 값을 변질시킬 수 있다. The source driver integrated circuit performs a function of transferring image data received from a timing controller to a display panel. When the image data is transmitted and received through one transmission line, the noise component introduced by the electrical characteristics of the transmission line may alter the logical value of the image data transmitted and received.
최근의 디스플레이 패널 구동시스템은 상기와 같은 문제점을 해결하기 위하여, 영상데이터를 그대로 전송하는 것이 아니라, 영상데이터를 차동영상데이터신호로 변환하여 2개의 전송라인을 통해 송수신함으로써 단일데이터신호로 송수신될 때 발생할 수 있는 송수신 에러를 최소한으로 억제한다. 따라서 하나의 화소를 구동하는 차동영상데이터는 2개의 전송라인을 통해 소스 드라이버 집적회로에 전달된다. In order to solve the above problems, a recent display panel driving system does not transmit image data as it is, but converts the image data into differential image data signals and transmits and receives them as a single data signal by transmitting and receiving them through two transmission lines. Minimize transmission and reception errors that may occur. Therefore, differential image data driving one pixel is transferred to the source driver integrated circuit through two transmission lines.
소스 드라이버 집적회로는 타이밍 제어회로로부터 전달받은 차동영상데이터를 처리하여 최초의 영상데이터로 변환한 후 디스플레이 패널에 전달한다. 일반적으로 하나의 소스 드라이버 집적회로는 디스플레이 패널의 복수 개의 화소를 구동하게 되므로, 디스플레이 패널의 크기에 따라 사용되는 소스 드라이버 집적회로의 개수가 결정된다. The source driver IC processes the differential image data received from the timing control circuit, converts the image data into original image data, and transmits the first image data to the display panel. In general, since one source driver integrated circuit drives a plurality of pixels of the display panel, the number of source driver integrated circuits used is determined according to the size of the display panel.
도 1은 M개의 화소를 구동하는 소스 드라이버 집적회로를 구비하는 디스플레이 패널 구동시스템의 일실시예이다. 1 is an embodiment of a display panel driving system including a source driver integrated circuit driving M pixels.
도 2는 N개의 화소를 구동하는 소스 드라이버 집적회로를 구비하는 디스플레이 패널 구동시스템의 일실시예이다. 2 is an embodiment of a display panel driving system having a source driver integrated circuit driving N pixels.
도 1을 참조하면, 하나의 소스 드라이버 집적회로(120, 130)는 M(M은 정수)개의 화소(picture element)를 구동하게 되므로, 타이밍 제어회로(110)도 M쌍의 차동영상데이터를 소스 드라이버 집적회로(120, 130)에 전달한다. Referring to FIG. 1, since one source driver integrated circuit 120 and 130 drives M (M is an integer) picture elements, the timing control circuit 110 may also source M pairs of differential image data. Transfer to driver integrated circuit (120, 130).
도 2를 참조하면, 하나의 소스 드라이버 집적회로(220, 230)는 N(N은 정수)개의 화소를 구동하게 되므로, 타이밍 제어회로(210)도 N쌍의 차동영상데이터를 소스 드라이버 집적회로(220, 230)에 전달한다. Referring to FIG. 2, since one source driver integrated circuit 220 and 230 drives N pixels (where N is an integer), the timing control circuit 210 may also store N pairs of differential image data. 220, 230).
2개의 타이밍 제어회로(110, 210)가 M쌍 및 N쌍의 서로 다른 차동영상데이터를 출력하기 때문에, 도 1에 도시된 소스 드라이버 집적회로(120, 130)의 내부 구조는 도 2에 도시된 소스 드라이버 집적회로(220, 230)의 내부구조와 서로 다르게 설계된다. 즉 도 1에 도시된 소스 드라이버 집적회로(120, 130)는 모두 M쌍의 차동영상데이터를 수신하도록 입력단자가 설계되고, 도 2에 도시된 소스 드라이버 집적회로(220, 230)는 모두 N쌍의 차동영상데이터를 수신하도록 입력단자가 설계된다. 따라서 기능은 동일하지만 내부 구조의 차이 때문에 2종류의 소스 드라이버 집적회로는 호환하여 사용할 수 없다. Since the two timing control circuits 110 and 210 output M pairs and N pairs of different differential image data, the internal structure of the source driver integrated circuits 120 and 130 shown in FIG. 1 is shown in FIG. The internal structure of the source driver integrated circuits 220 and 230 are different from each other. That is, the source driver integrated circuits 120 and 130 shown in FIG. 1 are all designed to receive M pairs of differential image data, and the source driver integrated circuits 220 and 230 shown in FIG. 2 are all N pairs. The input terminal is designed to receive differential image data. Therefore, the two types of source driver integrated circuits cannot be used interchangeably due to the same function but different internal structures.
상기와 같은 이유로 타이밍 제어회로로부터 출력되는 차동영상데이터의 쌍의 개수에 따라 소스 드라이버 집적회로는 새롭게 설계되어야 한다는 불편함이 있다. For this reason, it is inconvenient that the source driver integrated circuit must be newly designed according to the number of pairs of differential image data output from the timing control circuit.
본 발명이 해결하고자 하는 기술적과제는, 타이밍 제어회로로부터 출력되는 차동영상데이터 쌍의 개수에 관계없이 디스플레이 패널을 구동할 수 있는 디스플레이 패널 구동시스템을 제공하는데 있다. The present invention has been made in an effort to provide a display panel driving system capable of driving a display panel regardless of the number of differential image data pairs output from a timing control circuit.
본 발명이 해결하고자 하는 다른 기술적과제는, 타이밍 제어회로로부터 출력되는 차동영상데이터 쌍의 개수에 관계없이 디스플레이 패널을 구동할 수 있는 소스 드라이버 집적회로를 제공하는데 있다. Another technical problem to be solved by the present invention is to provide a source driver integrated circuit capable of driving a display panel regardless of the number of differential image data pairs output from the timing control circuit.
상기 기술적과제를 이루기 위한 본 발명에 따른 디스플레이 패널 구동시스템은, M(M은 정수)쌍의 데이터 및 N(N은 M보다 작은 정수)쌍의 데이터를 출력하는 타이밍 제어회로 및 상기 M쌍의 데이터 또는 상기 N쌍의 데이터를 수신하여 디스플레이 패널을 구동하는 복수 개의 소스 드라이버 집적회로를 구비하는 드라이버블록을 구비한다. According to an aspect of the present invention, there is provided a display panel driving system including a timing control circuit for outputting data of M pairs (M is an integer) and data of N pairs (N is an integer less than M) and the data of the M pairs. Or a driver block having a plurality of source driver integrated circuits for receiving the N pairs of data to drive the display panel.
상기 다른 기술적과제를 이루기 위한 본 발명의 일면 따른 소스 드라이버 집적회로는, M(M은 정수)쌍의 직렬데이터 및 N(N은 M보다 작은 정수)쌍의 직렬데이터를 수신하여 M×K(K는 정수)비트의 병렬데이터를 출력하며, 상기 M쌍의 직렬데이터 및 상기 N쌍의 직렬데이터를 수신하여 M×K비트의 병렬데이터로 변환하는 멀티 페어 직렬병렬변환기 및 상기 M×K비트의 병렬데이터를 정렬하여 출력하는 데이터정렬회로를 구비한다. In accordance with another aspect of the present invention, a source driver integrated circuit may receive serial data of M (M is an integer) pair and serial data of N (N is an integer less than M) pair to receive M × K (K Outputs parallel data of an integer) bit, and receives the M pair of serial data and the N pair of serial data and converts the M pair of serial data into M × K bits of parallel data and the M × K bits of parallel data. And a data alignment circuit for sorting and outputting data.
상기 다른 기술적과제를 이루기 위한 본 발명의 다른 일면 따른 소스 드라이버 집적회로는, M(M은 정수)쌍의 직렬데이터 및 N(N은 M보다 작은 정수)쌍의 직렬데이터를 수신하여 M×K(K는 정수)비트의 병렬데이터를 출력하며, 상기 M쌍의 직렬데이터 및 상기 N쌍의 직렬데이터를 수신하여 M×K비트의 병렬데이터 또는 N×K비트의 병렬데이터로 변환하는 직렬병렬변환기 및 상기 M×K비트의 병렬데이터 및 상기 N×K비트의 병렬데이터를 정렬하여 M×K비트의 병렬데이터로 출력하는 멀티 페어 데이터정렬회로를 구비한다. In accordance with another aspect of the present invention, a source driver integrated circuit may receive serial data of M (M is an integer) pair and serial data of N (N is an integer less than M) pair to receive M × K ( K outputs parallel data of an integer) bit and receives the M pair of serial data and the N pair of serial data, and converts the serial data into M × K bit parallel data or N × K bit parallel data. And a multi-pair data alignment circuit for sorting the parallel data of MxK bits and the parallel data of NxK bits and outputting the parallel data of MxK bits.
본 발명은 M쌍의 차동영상데이터를 처리할 수 있는 소스 드라이버 집적회로는 M보다 적은 쌍의 차동영상데이터도 동시에 처리할 수 있기 때문에 소스 드라이버 집적회로를 새로 설계하지 않고 그대로 사용할 수 있는 장점이 있다. The present invention has an advantage that the source driver integrated circuit capable of processing M pairs of differential image data can simultaneously process fewer pairs of differential image data than M, so that the source driver integrated circuit can be used as it is without newly designing it. .
도 1은 M개의 화소를 구동하는 소스 드라이버 집적회로를 구비하는 디스플레이 패널 구동시스템의 일실시예이다. 1 is an embodiment of a display panel driving system including a source driver integrated circuit driving M pixels.
도 2는 N개의 화소를 구동하는 소스 드라이버 집적회로를 구비하는 디스플레이 패널 구동시스템의 일실시예이다. 2 is an embodiment of a display panel driving system including a source driver integrated circuit driving N pixels.
도 3은 본 발명에 따른 디스플레이 패널 구동시스템의 일실시예이다. 3 is an embodiment of a display panel driving system according to the present invention.
도 4는 본 발명에 따른 소스 드라이버 집적회로의 일실시예이다. 4 is an embodiment of a source driver integrated circuit according to the present invention.
도 5는 본 발명에 따른 소스 드라이버 집적회로의 다른 일실시예이다. 5 is another embodiment of a source driver integrated circuit according to the present invention.
이하에서는 본 발명의 구체적인 실시 예를 도면을 참조하여 상세히 설명하도록 한다. Hereinafter, specific embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 3은 본 발명에 따른 디스플레이 패널 구동시스템의 일실시예이다. 3 is an embodiment of a display panel driving system according to the present invention.
도 3을 참조하면, 디스플레이 패널 구동시스템(300)은 M(M은 정수)쌍의 차동영상데이터 뿐만 아니라 M보다 적은 N(N은 정수)쌍의 차동영상데이터도 처리할 수 있다. 즉 타이밍 제어회로(310)는 M쌍의 차동영상데이터를 소스 드라이버 집적회로(320, 330)에 출력할 수도 있고, 경우에 따라서는 N쌍의 차동영상데이터를 소스 드라이버 집적회로(320, 330)에 출력할 수도 있다. 타이밍 제어회로(310)로부터 출력되는 차동영상데이터의 쌍의 개수에 관계없이 소스 드라이버 집적회로는 공통으로 사용된다. Referring to FIG. 3, the display panel driving system 300 may process differential image data of less than M (N is integer) pair as well as differential image data of M (M is integer) pair. That is, the timing control circuit 310 may output M pairs of differential image data to the source driver integrated circuits 320 and 330. In some cases, the timing control circuit 310 may output N pairs of differential image data to the source driver integrated circuits 320 and 330. You can also print to The source driver integrated circuit is commonly used regardless of the number of pairs of differential image data output from the timing control circuit 310.
이는 소스 드라이버 집적회로(320, 330)가 차동영상데이터의 쌍의 개수에 관계없이 처리할 수 있기 때문이다. This is because the source driver integrated circuits 320 and 330 can process the data regardless of the number of pairs of differential image data.
이러한 멀티 페어 차동영상데이터를 처리할 수 있는 소스 드라이버 집적회로(320, 330)에 대해서는 도 4 및 도 5에 설명한다. Source driver integrated circuits 320 and 330 capable of processing the multi-pair differential image data will be described with reference to FIGS. 4 and 5.
도 4는 본 발명에 따른 소스 드라이버 집적회로의 일실시예이다. 4 is an embodiment of a source driver integrated circuit according to the present invention.
도 4를 참조하면, 소스 드라이버 집적회로(400)는 멀티 페어 직렬병렬변환기(410) 및 데이터정렬회로(420)를 구비한다. Referring to FIG. 4, the source driver integrated circuit 400 includes a multi-pair serial and parallel converter 410 and a data alignment circuit 420.
멀티 페어 직렬병렬변환기(410)는 M쌍의 직렬차동데이터 뿐만 아니라 M보다 적은 N쌍의 직렬차동데이터도 M×K(K는 정수)비트의 병렬차동데이터로 변환한다. 데이터정렬회로(420)는 M×K비트의 병렬차동데이터를 정렬한다. 여기서 K는 하나의 화소를 표현하는 영상데이터의 비트수이다. The multi-pair serial-parallel converter 410 converts not only M pairs of serial differential data but also N pairs of serial differential data smaller than M into parallel differential data of M × K (K is an integer) bits. The data sorting circuit 420 sorts MxK bits of parallel differential data. K is the number of bits of the image data representing one pixel.
도 5는 본 발명에 따른 소스 드라이버 집적회로의 다른 일실시예이다. 5 is another embodiment of a source driver integrated circuit according to the present invention.
도 5를 참조하면, 소스 드라이버 집적회로(500)는 직렬병렬변환기(510) 및 멀티 페어 데이터정렬회로(520)를 구비한다. Referring to FIG. 5, the source driver integrated circuit 500 includes a serial and parallel converter 510 and a multi-pair data alignment circuit 520.
직렬병렬변환기(510)는 M쌍의 직렬차동데이터는 M×K비트의 병렬차동데이터로 변환하고, M보다 적은 N쌍의 직렬차동데이터는 N×K비트의 병렬차동데이터로 각각 변환한다. 멀티 페어 데이터정렬회로(520)는 M×K비트의 병렬차동데이터 뿐만 아니라 N×K비트의 병렬차동데이터도 M×K비트의 병렬차동데이터로 정렬한다. 여기서 K는 하나의 화소를 표현하는 영상데이터의 비트수이다. The serial-parallel converter 510 converts M pairs of serial differential data into M × K bits of parallel differential data, and N pairs of serial differential data less than M are converted into N × K bits of parallel differential data, respectively. The multi-pair data alignment circuit 520 sorts not only MxK bits of parallel differential data but also NxK bits of parallel differential data into MxK bits of parallel differential data. K is the number of bits of the image data representing one pixel.
도 4 및 도 5에 도시된 본 발명에 따른 소스 드라이버 집적회로는, 최고 M쌍의 차동영상데이터를 처리할 수 있으며, M보다 적은 쌍의 차동영상데이터가 입력되는 경우, 직렬병렬변환기 또는 데이터정렬회로중 하나의 기능블록에서 이를 사전 처리하여, 이후의 기능블록에서는 수신되는 차동영상데이터의 쌍의 개수에 관계없이 이를 처리할 수 있도록 한다. 4 and 5, the source driver integrated circuit according to the present invention can process up to M pairs of differential image data, and when less than M pairs of differential image data are inputted, a serial-parallel converter or data alignment. This is preprocessed in one functional block of the circuit so that subsequent functional blocks can process this regardless of the number of pairs of differential image data received.
도 4에 도시된 소스 드라이버 집적회로(400)의 경우 상기의 사전처리를 멀티 페어 직렬병렬변환기(410)에서 수행하고, 도 5에 도시된 소스 드라이버 집적회로(500)의 경우 멀티 페어 데이터정렬회로(520)에서 수행한다. In the case of the source driver integrated circuit 400 illustrated in FIG. 4, the above-described preprocessing is performed by the multi-pair serial-parallel converter 410, and in the case of the source driver integrated circuit 500 illustrated in FIG. 5, the multi-pair data alignment circuit. Perform at 520.
도 4 및 도 5에 도시된 소스 드라이버 집적회로는 상술한 바와 같은 직렬병렬변환기 또는 데이터정렬회로만으로 구성되는 것은 아니고 이 외에도 더 많은 기능블록이 존재한다. 그러나 이 부분은 당업자에게 널리 알려져 있을 뿐만 아니라, 본 발명의 동작에 영향을 주는 것도 아니다. 이와 같은 이유로 이 부분에 대하여 도면에도 추가하지 않았고 설명도 하지 않았지만, 본 발명의 기술적 사상의 실현에 문제가 되지 않는다. The source driver integrated circuits shown in FIGS. 4 and 5 are not composed of only the serial-parallel converter or data alignment circuit as described above, but there are many more functional blocks. However, this part is well known to those skilled in the art and does not affect the operation of the present invention. For this reason, this part has not been added to the drawings or described, but it does not matter for the technical idea of the present invention.
상술한 바와 같이, 본 발명에 따른 소스 드라이버 집적회로는 수신되는 차동영상데이터의 쌍에 관계없이 범용으로 사용할 수 있게 함으로써, 설계의 편의와 개발 기간을 단축시킬 수 있는 장점이 있다. As described above, the source driver integrated circuit according to the present invention has the advantage that it is possible to use a general purpose irrespective of the pair of the differential image data received, it is possible to shorten the design convenience and development period.
이상에서는 본 발명에 대한 기술사상을 첨부 도면과 함께 서술하였지만 이는 본 발명의 바람직한 실시 예를 예시적으로 설명한 것이지 본 발명을 한정하는 것은 아니다. 또한 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 이라면 누구나 본 발명의 기술적 사상의 범주를 이탈하지 않는 범위 내에서 다양한 변형 및 모방이 가능함은 명백한 사실이다. In the above description, the technical idea of the present invention has been described with the accompanying drawings, which illustrate exemplary embodiments of the present invention by way of example and do not limit the present invention. In addition, it is apparent that any person having ordinary knowledge in the technical field to which the present invention belongs may make various modifications and imitations without departing from the scope of the technical idea of the present invention.

Claims (4)

  1. M(M은 정수)쌍의 데이터 및 N(N은 M보다 작은 정수)쌍의 데이터를 출력하는 타이밍 제어회로; 및 A timing control circuit for outputting data of M (M is an integer) pair and data of N (N is an integer smaller than M) pair; And
    상기 M쌍의 데이터 또는 상기 N쌍의 데이터를 수신하여 디스플레이 패널을 구동하는 복수 개의 소스 드라이버 집적회로를 구비하는 드라이버블록을 구비하는 것을 특징으로 하는 디스플레이 패널 구동시스템. And a driver block including a plurality of source driver integrated circuits for receiving the M pair of data or the N pair of data to drive the display panel.
  2. M(M은 정수)쌍의 직렬데이터 및 N(N은 M보다 작은 정수)쌍의 직렬데이터를 수신하여 M×K(K는 정수)비트의 병렬데이터를 출력하는 소스 드라이버 집적회로에 있어서, A source driver integrated circuit for receiving M (M is an integer) pair of serial data and N (N is an integer less than M) pair of serial data and outputting M × K (K is an integer) bits of parallel data,
    상기 M쌍의 직렬데이터 및 상기 N쌍의 직렬데이터를 수신하여 M×K(K는 정수)비트의 병렬데이터로 변환하는 멀티 페어 직렬병렬변환기; 및 A multi-pair serial-parallel converter for receiving the M-pair serial data and the N-pair serial data and converting the M-pair serial data into M × K (K is an integer) parallel data; And
    상기 M×K비트의 병렬데이터를 정렬하여 출력하는 데이터정렬회로를 구비하는 것을 특징으로 하는 소스 드라이버 집적회로. And a data alignment circuit for sorting and outputting the parallel data of MxK bits.
  3. M(M은 정수)쌍의 직렬데이터 및 N(N은 M보다 작은 정수)쌍의 직렬데이터를 수신하여 M×K(K는 정수)비트의 병렬데이터를 출력하는 소스 드라이버 집적회로에 있어서, In a source driver integrated circuit that receives serial data of M pairs (M is an integer) and serial data of N pairs (N is an integer less than M) and outputs M × K (K is an integer) bits of parallel data,
    상기 M쌍의 직렬데이터 및 상기 N쌍의 직렬데이터를 수신하여 M×K(K는 정수)비트의 병렬데이터 또는 N×K비트의 병렬데이터로 변환하는 직렬병렬변환기; 및 A serial and parallel converter for receiving the M pair of serial data and the N pair of serial data and converting the M pair of serial data into M × K (K is an integer) parallel data or N × K bit parallel data; And
    상기 M×K비트의 병렬데이터 및 상기 N×K비트의 병렬데이터를 정렬하여 M×K비트의 병렬데이터로 출력하는 멀티 페어 데이터정렬회로를 구비하는 것을 특징으로 하는 소스 드라이버 집적회로. And a multi-pair data alignment circuit for sorting the parallel data of M × K bits and the parallel data of N × K bits and outputting the parallel data of M × K bits.
  4. 제2항 또는 제3항에 있어서, The method according to claim 2 or 3,
    상기 K는 계조 비트 수인 것을 특징으로 하는 소스 드라이버 집적회로. And K is the number of gradation bits.
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WO2010047474A4 (en) 2010-09-23

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