WO2010047227A1 - Semiconductor device and method for manufacturing same - Google Patents
Semiconductor device and method for manufacturing same Download PDFInfo
- Publication number
- WO2010047227A1 WO2010047227A1 PCT/JP2009/067495 JP2009067495W WO2010047227A1 WO 2010047227 A1 WO2010047227 A1 WO 2010047227A1 JP 2009067495 W JP2009067495 W JP 2009067495W WO 2010047227 A1 WO2010047227 A1 WO 2010047227A1
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- layer
- wiring
- semiconductor device
- structure layer
- substrate
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Images
Classifications
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
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- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
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- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
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- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
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- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- H01—ELECTRIC ELEMENTS
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
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- H01L2924/1461—MEMS
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
- H01L2924/19104—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device on the semiconductor or solid-state device, i.e. passive-on-chip
Definitions
- the present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a multilayer wiring structure.
- WLP Wafer Level Package
- Patent Document 1 Japanese Patent Laid-Open No. 2004-274035 has a structure in which an electronic component such as a transistor or a capacitor is embedded in an insulating layer between a pair of wiring boards, and vias for connecting wirings between the boards are provided. An electronic component built-in module is disclosed.
- Patent Document 2 Japanese Unexamined Patent Application Publication No. 2007-096030 (Patent Document 2) and Japanese Unexamined Patent Application Publication No. 2008-103387 (Patent Document 3) disclose semiconductor devices based on CSP (Chip Size Package) technology.
- CSP Chip Size Package
- a semiconductor device described in Patent Document 2 includes an electronic circuit formed on a substrate surface, a pad electrode connected to the electronic circuit and formed on the substrate surface, a via hole penetrating the semiconductor substrate, and the pad electrode through the via hole. And a wiring layer on the back surface of the substrate connected to the substrate, and ball-like conductive terminals are provided on the back surface of the substrate so as to be electrically connected to the wiring layer. These via holes, pad electrodes, and wiring layers are arranged outside the formation area of the electronic circuit on the substrate plane.
- the semiconductor device described in Patent Document 3 includes a circuit unit formed on a substrate surface, a surface wiring connected to the circuit unit and formed on the substrate surface, a via hole penetrating the semiconductor substrate, and the surface wiring through the via hole. And external connection bumps are provided on the back surface of the substrate so as to be electrically connected to the back surface wiring. These via holes and backside wiring are arranged outside the circuit portion formation region on the substrate plane.
- connection points between the embedded electronic component and the wiring board are made finer and higher in density than the technique of directly forming the wiring layer on the wafer on which the semiconductor element is formed. It is difficult and the function of the semiconductor element included in the electronic component is limited. Moreover, since the difference in thermal expansion coefficient between the electronic component and the material used for the wiring board is large, the direction and amount of warpage differ between the portion where the electronic component is embedded and the portion where it is not embedded due to the thinning. Warping occurs.
- An object of the present invention has been made to solve the above-described problems, and is to provide a high-density semiconductor device.
- a substrate including an element; A first insulating layer and a first structure layer provided on one side of the substrate, including a first wiring electrically connected to the element; A second structure layer including a first insulating layer and a second wiring electrically connected to the first wiring, the second structure layer being stacked on the first structure layer and being thicker than the first structure layer; A semiconductor device is provided that includes a third insulating layer and a third wiring, and a third structural layer provided on a surface opposite to the surface on which the first structural layer of the substrate is provided.
- the first structural layer has a multilayer wiring structure in which the first insulating layer and the first wiring are alternately stacked
- the second structural layer includes the second insulating layer and the second insulating layer.
- any one of the above semiconductor devices wherein the second wiring is thicker than the first wiring.
- any one of the above semiconductor devices wherein the second insulating layer is thicker than the first insulating layer.
- any one of the above semiconductor devices wherein the third wiring is thicker than the first wiring.
- any one of the above semiconductor devices wherein the third insulating layer is thicker than the first insulating layer.
- the power supply system wiring is formed so that the number of terminals is reduced by combining a plurality of power supply system wirings in the first structure layer.
- a semiconductor device is provided.
- the ground wiring is formed so as to reduce the number of terminals by combining a plurality of ground wirings in the first structural layer.
- a semiconductor device is provided.
- any one of the above semiconductor devices having a through via that penetrates the substrate and electrically connects the first wiring or the second wiring to the third wiring.
- the power supply system wiring is formed so as to reduce the number of terminals by combining a plurality of power supply system wirings in the first structure layer.
- the ground wiring is formed so that the number of terminals is reduced by combining a plurality of ground wirings in the first structural layer.
- a semiconductor device is provided.
- any one of the above semiconductor devices wherein the number of the second wirings in the second structural layer is the same as the number of the third wirings in the third structural layer.
- the semiconductor device according to any one of the above, wherein the number of the second insulating layers of the second structural layer is the same as the number of the third insulating layers of the third structural layer. Provided.
- a semiconductor device characterized in that a plurality of the same or different semiconductor devices described above are stacked.
- a manufacturing method for manufacturing any one of the above semiconductor devices Preparing a substrate on which a plurality of elements are formed; Forming the first structure layer on one side of the substrate; Forming the second structure layer on the first structure layer; Forming a third structure layer on a surface opposite to the surface of the substrate on which the first structure layer is provided.
- the formation of the second wiring is performed simultaneously with the formation of the second insulation layer and the formation of the third insulation layer in the same process. And the method of manufacturing the semiconductor device, wherein the third wiring is simultaneously formed in the same process.
- the formation of the second structural layer and the third structural layer in the formation of the second structural layer and the third structural layer, the formation of the second insulating layer and the second wiring, the formation of the third insulating layer, and the third wiring
- a method for manufacturing the semiconductor device described above wherein the formation of the semiconductor device is alternately performed.
- a method for manufacturing any one of the above semiconductor devices wherein a via penetrating the substrate is formed before or after the step of forming the first structure layer.
- a method for manufacturing any one of the above semiconductor devices wherein a via penetrating the substrate is formed in the course of forming the second structural layer.
- the via of penetrating the substrate is formed after the step of forming the second structural layer and before the step of forming the third structural layer.
- a manufacturing method is provided.
- a method for manufacturing any one of the above semiconductor devices wherein a via penetrating the substrate is formed during the step of forming the third structure layer.
- the step of thinning the substrate is performed after the step of forming the first structural layer or the step of forming the second structural layer. It relates to a manufacturing method.
- a plurality of multilayer wiring structures including the first structural layer, the second structural layer, and the third structural layer are formed on a semiconductor wafer including the substrate, and then the multilayer wiring structures are respectively formed.
- a method of manufacturing any one of the above semiconductor devices is provided, which is divided into individual pieces.
- a method for manufacturing a semiconductor device including a step of forming a plurality of semiconductor devices of the same type or different types by any one of the methods described above, and a step of stacking these semiconductor devices.
- a high-density semiconductor device can be provided.
- FIG. 1 is a perspective view showing an example of a semiconductor device according to a first embodiment of the present invention. It is a fragmentary sectional view of the semiconductor device shown in FIG.
- FIG. 3 is a partial cross-sectional view showing a first structure layer of the semiconductor device shown in FIG. 2. It is a fragmentary sectional view showing other examples of the semiconductor device by a 1st embodiment of the present invention. It is a fragmentary sectional view showing an example of structure of an electrode part of a semiconductor device by a 1st embodiment of the present invention. It is a fragmentary sectional view showing an example of a semiconductor device by a 2nd embodiment of the present invention. It is a fragmentary sectional view which shows the other example of the semiconductor device by 2nd Embodiment of this invention.
- FIG. 12 is a diagram for further explaining the manufacturing method described with reference to FIG. 11. It is a fragmentary sectional view for explaining a manufacturing method of a semiconductor device by other embodiments of the present invention.
- a first structure layer and a second structure layer stacked on the first structure layer and thicker than the first structure layer are provided on one surface of a substrate including a plurality of elements.
- a third structure layer is provided on a surface opposite to the surface of the substrate on which the first structure layer is provided.
- the first structural layer includes a first insulating layer and a first wiring electrically connected to the element.
- the second structural layer includes a second wiring electrically connected to the second insulating layer and the first wiring.
- the third structure layer includes a third insulating layer and a third wiring.
- the first structure layer has a first via for connecting an upper layer side wiring and a lower layer side wiring when a plurality of first wirings are laminated via an interlayer insulating film.
- the second structure layer has a second via for connecting the upper layer side wiring and the lower layer side wiring when a plurality of second wirings are stacked via the interlayer insulating film.
- the third structure layer has a third via for connecting the upper layer side wiring and the lower layer side wiring when a plurality of third wirings are stacked via the interlayer insulating film.
- Wirings and vias in the first structural layer are collectively referred to as “first wiring” and “first via”, respectively, and wirings and vias in the second structural layer are collectively referred to as “second wiring” and “second via”, respectively.
- the wirings and vias in the third structure layer are collectively referred to as “third wiring” and “third via”, respectively.
- Such a semiconductor device has the second structure layer and the third structure layer, the wiring accommodation rate of the semiconductor device can be increased, and further, other semiconductor devices and chip components are provided on both sides of the substrate of the semiconductor device. It becomes possible to mount electronic parts such as high density.
- each insulating layer included in the second structure layer and the third structure layer due to the action of each insulating layer included in the second structure layer and the third structure layer, it is possible to prevent chipping and cracks caused by receiving an impact, and to improve impact resistance.
- stable power supply can be realized by making both or one of the wiring layer of the second structure layer and the wiring layer of the third structure layer thicker than the wiring layer of the first structure layer, and moreover than the first structure layer. Low-loss signal transmission can be achieved.
- the semiconductor device is connected to a mounting board or another component by making the insulating layer of the second structural layer and / or the insulating layer of the third structural layer thicker than the insulating layer of the first structural layer. Stress can be relaxed more sufficiently, and connection reliability can be improved.
- the stress on one side of the substrate and the stress on the opposite side can be made uniform. Even if the substrate is thin, the amount of warpage can be suppressed.
- the second structural layer on one side of the substrate and providing the third structural layer on the opposite side the stress generated on both sides of the substrate can be offset and warped.
- a semiconductor device with a small amount can be realized, and a thinner semiconductor device can be provided. From such a viewpoint, it is preferable that the thickness of the second structure layer and the third structure layer is sufficiently thicker than that of the first structure layer.
- the thicker the second structure layer and the third structure layer the greater the thickness of the first structure layer.
- the influence of stress can be made relatively small, and the stress can be made uniform by the second structure layer and the third structure layer without being greatly affected by the structure of the first structure layer.
- the thicknesses of the second structural layer and the third structural layer are not so large with respect to the thickness of the first structural layer, the balance between the total thickness of the first structural layer and the second structural layer and the third thickness It is desirable to set the thicknesses of the second structure layer and the third structure layer in consideration of the above.
- the effect of reducing the amount of warpage can be further increased by using the same number of wiring layers and / or insulating layers between the second structure layer and the third structure layer of the semiconductor device of the above embodiment.
- the thickness of the second structure layer and the third structure layer is preferably at least twice the thickness of the first structure layer, more preferably at least three times, and further suppress warpage. From the viewpoint, 5 times or more is preferable.
- the ratio (T2 / T3) of the thickness T2 of the second wiring layer and the thickness T3 of the third structure layer is preferably in the range of 0.7 to 1.3, and in the range of 0.8 to 1.2. It is more preferable.
- the thickness of the first wiring is preferably 0.1 to 1.6 ⁇ m, more preferably 0.2 to 1.2 ⁇ m, and the thickness of the second wiring and the third wiring is preferably 3 to 12 ⁇ m, more preferably 5 to 10 ⁇ m. preferable.
- the thickness of the first insulating layer is preferably 0.1 to 1.6 ⁇ m, more preferably 0.2 to 1.2 ⁇ m.
- the thickness of the second insulating layer and the third insulating layer is preferably 5 to 50 ⁇ m, preferably 10 to 30 ⁇ m is more preferable.
- the first structure layer corresponds to the insulating layer in contact with the substrate to the layer including the uppermost layer wiring
- the second structure layer is in contact with the uppermost layer wiring of the first structure layer. It corresponds to a layer (insulating layer or wiring) to an insulating layer in contact with the uppermost wiring of the second structural layer
- the third structural layer is from a layer (insulating layer or wiring) in contact with the opposite surface of the substrate. This corresponds to the insulating layer in contact with the uppermost wiring of the third structure layer.
- FIG. 1 is a perspective view showing a semiconductor device according to a first embodiment of the present invention
- FIG. 2 is a partial sectional view showing a part of the semiconductor device
- FIG. 3 is a first view of the semiconductor device shown in FIG. 3 is an enlarged cross-sectional view of a structural layer 13.
- FIG. 1 the first structure layer 13 is omitted.
- the second structure layer 14 is provided on one side of the semiconductor substrate 12, and the third structure layer 19 is provided on the opposite side.
- the first structure layer 13 is provided on one surface of the semiconductor substrate 12, and the second structure layer 14 is directly provided thereon.
- an element 30 is provided on the semiconductor substrate 12.
- the semiconductor substrate 12 is formed of, for example, Si, germanium, gallium arsenide (GaAs), gallium arsenide phosphorus, gallium nitride (GaN), silicon carbide (SiC), II-VI group compound, III-V group compound, diamond, or the like. Yes. You may use the board
- the second structure layer 14 includes second wirings 15, second insulating layers 16, and second vias 17, and the second wirings 15 and the second insulating layers 16 are alternately stacked.
- the second wiring on the upper layer side and the second wiring on the lower layer side are connected by a second via penetrating the second insulating layer between these wiring layers, and the second wiring on the lowermost layer side is connected to the lowermost layer side.
- the second structure layer is not limited to the structure shown in FIG.
- the number of layers may be greater than that shown in FIG.
- the second electrode 18 is provided on the surface side of the second structure layer 14 and is electrically connected to the second wiring 15.
- the third structure layer 19 is provided on the surface opposite to the surface on which the first structure layer 13 of the semiconductor substrate 12 is provided, and the third wiring 20, the third insulating layer 21, and the third via 22.
- the third wirings 20 and the third insulating layers 21 are alternately stacked.
- the third wiring on the upper layer side and the third wiring on the lower layer side are connected by a third via penetrating the third insulating layer between these wiring layers.
- the third structure layer is not limited to the structure shown in FIG. 2, and has at least a third insulating layer 21 provided on the semiconductor substrate and a third wiring 20 provided on the third insulating layer. It may be sufficient and it may be laminated more than the number of layers shown in FIG.
- the third electrode 23 is provided on the surface side of the third structure layer 19 and is electrically connected to the third wiring 20.
- the number of stacked layers of the second wiring 15 and the third wiring 20 is the same, and the number of stacked layers of the second insulating layer 16 and the third insulating layer 21 is the same.
- the number of layers may be different. However, from the viewpoint of reducing the amount of warpage, one or both of the number of stacked layers of the second wiring 15 and the third wiring 20 and the number of stacked layers of the second insulating layer 16 and the third insulating layer 21 are the same number of layers. It is desirable to be.
- the second electrode 18 and the third electrode 23 that are external terminals are each configured by wiring on the surface layer side, and the position may be changed according to the connection method, or on the second via 17 and the third via 22, respectively. You may provide directly.
- the first structure layer is provided on the semiconductor substrate 12 on which a plurality of semiconductor elements 30 are formed.
- a MOS transistor Metal Oxide Semiconductor: metal oxide semiconductor
- This MOS transistor includes a source region 25 and a drain region 26 provided on the surface of the semiconductor substrate 12, and a gate electrode 24 provided on a region sandwiched between these regions via a gate insulating film (not shown). It is configured.
- a planar MOS transistor a vertical transistor having a three-dimensional structure, a Fin-type FET, or a transistor using an organic material may be used.
- An interlayer insulating film 29 is provided on the semiconductor substrate 12 so as to cover these semiconductor elements 30, and a wiring 31 (first wiring) is provided on the interlayer insulating film 29.
- a space between the wirings 31 is filled with an insulating film 32, and a wiring layer 28 composed of the inter-wiring insulating film 32 and the wirings 31 is formed.
- Such a wiring layer 28 (first wiring 31 and inter-wiring insulating film 32) and interlayer insulating film 29 (first insulating layer) are alternately laminated to form a multilayer wiring structure.
- the lowermost wiring 31 is electrically connected to the source region 25 or the drain region 26 through a plug 27 formed in the lowermost interlayer insulating film 29.
- the upper layer side wiring 31 and the lower layer side wiring 31 in this multilayer wiring structure are electrically connected through a via 33 formed in the interlayer insulating film 29 between these wirings.
- Examples of the wiring material for the first structural layer 13 include copper and aluminum.
- the wiring of the first structure layer can be formed by, for example, a damascene method.
- the formation of wiring by the damascene method can be performed as follows, for example. First, an insulating film is formed, and a groove (trench) corresponding to a desired wiring pattern or a hole corresponding to a via pattern is formed in the insulating film using a lithography technique and a dry etching technique.
- a barrier metal layer is formed on the entire surface including the inside of the groove or hole by a sputtering method, a CVD (Chemical Vapor Deposition) method, an ALD (Atomic Layer Deposition) method, etc., and a power supply layer for electrolytic plating is formed by a sputtering method, Then, a copper film is formed so as to fill the groove or hole by electrolytic copper plating. Next, the copper film is polished by CMP (Chemical Mechanical Polishing) so that copper remains only in the groove or hole.
- CMP Chemical Mechanical Polishing
- the thickness of the interlayer insulating film 29 in the first structure layer 13 can be set in the range of 0.2 to 2 ⁇ m, for example, 0.2 to 1.6 ⁇ m.
- at least one interlayer insulating film provided near the semiconductor substrate 12 is preferably formed of a low-k material.
- the low-k material is a porous silicon oxide film, and it is desirable that the elastic modulus at 25 ° C. is in the range of 4 to 10 GPa.
- the second wiring 15 of the second structure layer 14 and the third wiring 20 of the third structure layer 19 can be formed using, for example, copper, and the thickness thereof is, for example, 5 ⁇ m.
- the second wiring 15 and the third wiring 20 can be formed by a wiring forming method different from the wiring of the first structure layer 13 such as a subtractive method, a semi-additive method, and a full additive method.
- a subtractive method for example, as described in JP-A-10-51105, a copper foil provided on a substrate or a resin is etched using a resist having a desired pattern as a mask, and then the resist is removed.
- a desired wiring pattern is obtained by removal.
- the semi-additive method is a resist in which a power supply layer is formed by electroless plating, sputtering, CVD, aerosol, or the like, and then opened in a desired pattern. Is formed, electrolytic plating is deposited in the resist opening, and after removing the resist, the power feeding layer is etched to obtain a desired wiring pattern.
- a resist having a desired pattern is formed after an electroless plating catalyst is adsorbed on the surface of a substrate or resin, and this resist is formed on an insulating layer. In this method, the catalyst is activated as it is, and a desired wiring pattern is obtained by depositing metal in the opening of the insulating layer by electroless plating.
- the second wiring 15 and the second electrode 18 of the second structure layer 14 and the third wiring 20 and the third electrode 23 of the third structure layer 19 are respectively connected to the semiconductor substrate 12 side via an adhesion layer via the second insulating layer. 16 and the third insulating layer 21 may be provided.
- the adhesion layer may be any material having adhesion to the material of the second insulating layer 16 or the third insulating layer 21.
- titanium, tungsten, nickel, tantalum, vanadium, chromium, molybdenum, copper, aluminum These alloys are mentioned, and among these, titanium, tungsten, tantalum, chromium, molybdenum, and alloys thereof are preferable, and titanium, tungsten, and alloys thereof are more preferable.
- the surface of the second insulating layer 16 or the third insulating layer 21 may be a roughened surface having fine irregularities, and in this case, good adhesion can be easily obtained even with copper or aluminum. Further, as a means for improving the adhesion, it is desirable to form a wiring material by sputtering.
- the second wiring 15 of the second structural layer 14 is thicker than the wiring layer 28 of the first structural layer 13, that is, thicker than the first wiring 31.
- the thickness of the second wiring 15 is, for example, 3 to 12 ⁇ m, and preferably 5 to 10 ⁇ m. If the second wiring is too thin, the wiring resistance increases and the electrical characteristics of the power supply circuit of the semiconductor device are degraded. If the thickness of the second wiring is too large, a large undulation reflecting the unevenness of the wiring layer is likely to occur on the surface of the insulating layer covering the wiring layer, the number of laminations is limited, or the thickness of the second structure layer 14 itself increases. However, warpage of the entire semiconductor device becomes large, and manufacturing becomes difficult due to process restrictions.
- the third wiring 20 of the third structural layer 19 is thicker than the wiring layer 28 of the first structural layer 13, that is, thicker than the first wiring 31.
- the thickness of the third wiring 20 is, for example, 3 to 12 ⁇ m, and preferably 5 to 10 ⁇ m. If the third wiring is too thin, the wiring resistance increases and the electrical characteristics of the power supply circuit of the semiconductor device deteriorate. If the third wiring is too thick, the surface of the insulating layer covering the wiring layer is liable to generate large undulations reflecting the irregularities of the wiring layer, limiting the number of layers, and increasing the thickness of the third structure layer 19 itself. However, warpage of the entire semiconductor device becomes large, and manufacturing becomes difficult due to process restrictions.
- the second insulating layer 16 of the second structure layer 14 and the third insulating layer 21 of the third structure layer 19 are made of, for example, an organic material.
- the organic material include epoxy resin, epoxy acrylate resin, urethane acrylate resin, polyester resin, phenol resin, polyimide resin, BCB (Benzocyclobutene), PBO (Polybenzoxole), and polynorbornene resin.
- polyimide resin and PBO have excellent mechanical properties such as film strength, tensile elastic modulus, and elongation at break, high reliability can be obtained.
- the organic material either a photosensitive material or a non-photosensitive material may be used.
- the opening to be the second via 17 or the third via 22 can be formed by a photolithography method.
- the opening can be formed by a laser method, a dry etching method, a blast method, or the like.
- the stress applied to the semiconductor device from the second electrode 18 or the third electrode 23 is mainly increased.
- the stress propagation to the first structure layer 13 can be effectively reduced by relaxing the deformation of the second insulating layer 16 and the third insulating layer 21.
- the elastic modulus at 25 ° C. of the material of the second insulating layer 16 and the third insulating layer 21 is preferably in the range of 0.15 to 8 GPa, for example.
- the elastic modulus of the insulating material is too low, the amount of deformation of the second insulating layer 16 and the third insulating layer 21 during stress relaxation is large, and most of the stress is applied to the second wiring 15 and the third wiring 20. The disconnection of the second wiring 15 and the third wiring 20 and the breakdown at the second wiring 15 / second via 17 interface and the third wiring 20 / third via 22 interface are likely to occur. If the elastic modulus of the insulating material is too high, the deformation amount of the second insulating layer 16 and the third insulating layer 21 is insufficient, and the stress relaxation in the second structural layer 14 and the third structural layer 19 becomes insufficient, and the first structural layer In FIG. 13, delamination, insulation film breakdown, etc. are likely to occur.
- the second insulating layer 16 and the second insulating layer 16 can be combined with an insulating material in which the elastic modulus of the second insulating layer 16 and the third insulating layer 21 is lower than the elastic modulus of the interlayer insulating film 29 of the first structural layer 13.
- the stress can be relaxed more effectively by the three insulating layers 21, and the protective effect of the first structure layer 13 can be enhanced.
- the second structure layer 14 is electrically connected to the first structure layer 13 through the second via 17, and the third structure layer 19 has the third insulating layer 21 in contact with the semiconductor substrate 12.
- the second structure layer 14 may be electrically connected to the first structure layer 13 through the second wiring 15, and the third structure layer 19 has its third structure.
- the wiring 20 may be provided on the semiconductor substrate 12.
- the third wiring 20 of the third structure layer 19 is provided on the semiconductor substrate 12, it is desirable that the surface of the semiconductor substrate 12 is insulative.
- the second electrode 18 of the second structure layer may have the structure shown in FIGS.
- FIG. 5A when the connection is made using a solder material, an opening through which the second electrode 18 is exposed is formed by the second insulating layer 16 on the surface side so that the solder is supplied only to the second electrode 18. Restricted. The restriction by the second insulating film 16 restricts the amount of solder flow, so that the mounting height when the semiconductor device is connected to the mounting substrate or another component can be stabilized.
- 5A shows a structure in which the second insulating layer 16 covers the periphery of the second electrode 18, but a structure that is not covered by the second insulating layer 16 may be used.
- FIG. 5B when connecting using wire bonding, the connection to the electrode portion can be made favorable.
- FIG. 5C the lower part of the electrode is provided in the opening of the second insulating layer 16 on the surface side, and according to this structure, when the connection by the solder material is performed at a narrow pitch, the connection Reliability can be improved.
- the second electrode 18 is made of, for example, a laminate, and in consideration of wettability of solder balls formed on the surface of the second electrode 18 and connectivity with bonding wires, the surface of the second electrode 18 is made of, for example, copper. And a layer of at least one metal or alloy selected from the group consisting of aluminum, gold, silver and solder materials.
- the second electrode 18 is, for example, a nickel layer and a gold layer laminated on a copper layer and having the gold layer as a surface.
- the nickel layer has a thickness of 3 ⁇ m, for example, and the gold layer has a thickness of 1 ⁇ m, for example.
- the third electrode 23 of the third structure layer 19 can have the same structure as the second electrode 18 of the second structure layer 14.
- the second electrode 18 and the third electrode 23 may be appropriately selected from structures having a desired effect on the connection, and need not have the same structure.
- FIG. 2 three layers of the second wiring 15 and four layers of the second insulating layer 16 are shown, but the present invention is not limited to this, and the number of layers can be set as necessary.
- FIG. 3 the eight wiring layers 28 and the eight interlayer insulating films (first insulating layers) 29 are shown, but the present invention is not limited to this, and the number of layers can be set as necessary.
- the first wiring 31, the second wiring 15, and the third wiring 20 are made of at least one kind of metal or alloy selected from the group consisting of copper, aluminum, nickel, gold and silver, for example.
- copper is preferable from the viewpoint of electrical resistance value and cost.
- Nickel can prevent an interfacial reaction with other materials such as an insulating material, can be used as a barrier film, has characteristics as a magnetic material, and can be used as an inductor or a resistance wiring.
- the second wiring 15 of the second structural layer 14 has a larger allowable current amount than the first wiring 31 because the thickness thereof is thicker than the first wiring 31 of the first structural layer 13.
- the third wiring 20 of the third structure layer 19 has a larger allowable current amount than the first wiring 31 because the thickness thereof is thicker than that of the first wiring 31 of the first structure layer 13.
- a plurality of power supply system wirings and ground system wirings using the same voltage can be bundled to reduce the number of wirings. By combining these plural wirings, the number of the second electrodes 18 and the third electrodes 23 can be reduced as compared with the case where they are not combined.
- the size and interval (pitch) of the second electrodes 18 and the third electrodes 23 can be increased, so that the connection area between the mounting substrate and the semiconductor device increases. Stable mounting and high connection reliability can be realized.
- the semiconductor substrate 12 and the layers stacked thereon are provided.
- the stress generated by the difference in thermal expansion can be offset, and the amount of warpage can be suppressed even if the semiconductor substrate 12 is thinned.
- both or one of the wiring layers and the insulating layers has the same number, so that the effect of reducing the warpage can be further enhanced.
- the second structural layer 14 and the third structural layer 19 provided on both sides of the semiconductor substrate can increase the wiring accommodation rate of the semiconductor device, and further, electronic components such as other semiconductor devices and chip components on the both sides of the substrate. Can be mounted at high density.
- each organic insulating layer included in the second structure layer 14 and the third structure layer 19 can soften the impact received by the semiconductor device, prevent chipping and cracks, and improve impact resistance. it can.
- the second wiring 15 of the second structural layer 14 and the third wiring 20 of the third structural layer 19 By making the thickness of the second wiring 15 of the second structural layer 14 and the third wiring 20 of the third structural layer 19 larger than the thickness of the wiring 31 of the first structural layer 13, the second wiring 15 and the third wiring 20. Can be prevented, and the wiring resistance of the second wiring 15 and the third wiring 20 can be made smaller than that of the first wiring 31. Further, as the thicknesses of the second wiring 15 and the third wiring 20 are increased, the thickness of each layer of the second insulating layer 16 and the third insulating layer 21 is also increased, so that the effect of relaxing the stress is enhanced.
- the wiring when provided in the semiconductor component is simply changed in the one-to-one relationship without reducing the number of connection terminals. is doing.
- a semiconductor component having about 500 or more external terminals, particularly 1500 or more about 60 to 80% of the number of terminals serves as a power supply system and a ground system in order to maintain device performance.
- the number of the second electrodes 18 of the second structure layer 14 can be greatly reduced as compared with the number of electrical connection points formed on the surface of the first structure layer 13. Can do. Furthermore, the number of the third electrodes 23 can be reduced also in the third structure layer 19. For this reason, since the size and interval (pitch) of the second electrode 18 and the third electrode 23 can be increased, stable mounting property and high connection reliability of the semiconductor device can be realized.
- the second structure layer 14 and the third structure layer 19 are thin and less warped, and the propagation of stress and impact to the first structure layer 13 is reduced, so that the connection reliability at the time of mounting is high.
- a high-density semiconductor device can be realized.
- FIG. 6 is a partial sectional view showing an example of a semiconductor device according to the second embodiment of the present invention.
- the semiconductor device according to the first embodiment is different in that a through via 34 is provided so as to penetrate the semiconductor substrate 12.
- a through via 34 is provided so as to penetrate the semiconductor substrate 12.
- the second electrode 18 and the third electrode 23 in FIG. 6 may have the structure shown in FIGS.
- the through via 34 allows the first structure layer 13 and the second structure layer 14 provided on one surface of the semiconductor substrate 12 and the third structure layer 19 provided on the other surface to be provided according to a required function. Connect them electrically. That is, one or both of the first structure layer 13 and the second structure layer 15 are electrically connected to the third structure layer 19 through the through via 34.
- the through via 34 can be formed as follows. First, a through hole is formed in the semiconductor substrate 12 by dry etching or wet etching. Next, an inorganic or organic insulating film is formed on the inner wall of the through hole by thermal oxidation, CVD, ALD, spin coating, laminating, or printing. If necessary, the insulating film may be processed by photolithography, laser, dry etching, or wet etching. Next, a through via 34 is formed in the through hole by forming a conductor by CVD, sputtering, electrolytic plating, electroless plating, printing, vapor deposition, ink jet, or the like.
- At least one conductive material selected from the group consisting of copper, aluminum, tungsten, gold, silver, nickel, and impurity-containing polysilicon, or an alloy containing any metal can be used. . From the viewpoint of cost and electrical characteristics, copper or a copper alloy is preferable.
- FIG. 7 is a partial cross-sectional view showing another example of the semiconductor device according to the second embodiment.
- the pitch of the through vias 34 is smaller than the pitch of the second electrode 18 and the third electrode 23.
- a plurality of through vias 34 are bundled by the second wiring 15 and the third wiring 20. This is because the second wiring and the third wiring are sufficiently thick and the wiring resistance is small, and thus such a wiring structure is possible.
- the wiring structure layers provided on both surfaces of the substrate are electrically connected through the through vias. Furthermore, the degree of freedom in wiring design is further improved, and a higher density than that of the semiconductor device according to the first embodiment can be realized. In addition, since the electronic components provided on one surface side and the other surface side of the substrate can be connected with a short distance, the performance of the semiconductor device can be improved.
- FIGS. 8 to 10 are partial sectional views showing specific examples of the semiconductor device according to the third embodiment of the present invention.
- the semiconductor device according to the first embodiment and the semiconductor device according to the second embodiment are stacked.
- the semiconductor device according to the first embodiment is stacked on the semiconductor device according to the second embodiment.
- two semiconductor devices according to the second embodiment are stacked.
- the stacked form of the semiconductor device is not limited to these.
- the second electrode 18 and the third electrode 23 in FIGS. 8 to 10 may have a structure shown in FIGS. 5B and 5C.
- the semiconductor device according to the third embodiment will be described below. Portions that are not particularly described are the same as those of the semiconductor device according to the first embodiment or the second embodiment.
- the semiconductor device shown in FIG. 2 is stacked on the semiconductor device shown in FIG.
- the second electrode 18 of the semiconductor device shown in FIG. 6 and the third electrode 23 of the semiconductor device shown in FIG. 2 are connected by a connection portion 35 provided between the two semiconductor devices.
- a solder ball 36 is provided on the third electrode 23 on the lower surface side.
- the connecting portion 35 can be formed of at least one material selected from the group consisting of solder material, tin, gold, silver, palladium, copper, and aluminum.
- an underfill resin may be injected between the semiconductor devices to increase the strength.
- FIG. 9 is different from the structure shown in FIG. 8 in that the second electrode 18 of the semiconductor device shown in FIG. 6 is connected to the second electrode 18 of the semiconductor device shown in FIG. Is different.
- the first structure layers of the two semiconductor devices are stacked so as to face each other. High-speed and high-speed data communication between semiconductor devices facing each other is possible, and high performance can be realized.
- an electronic component 37 is provided on the upper surface side, and a solder ball 36 is provided on the lower surface side.
- the electronic component is electrically connected to the second electrode 18 on the upper surface side via the connection portion 38.
- the solder ball 36 is directly connected to the third electrode 23 on the lower surface side.
- Examples of the electronic component 37 include other semiconductor devices, chip capacitors, chip resistors, discretes, diodes, LEDs, sensors, MEMS, and optical components.
- the connecting portion 38 can be formed of at least one material selected from the group consisting of solder material, tin, gold, silver, palladium, copper, and aluminum.
- the present invention is not limited to this, and three or more semiconductor devices may be stacked. Further, the structure having the solder ball 36 is shown in the lowermost layer of the stack, but the present invention is not limited to this, and pins, Au bumps, copper bumps, spare solder, metal pearls, ACF, NCF, etc. are used. A structure based on a connection method may be used.
- the footprint is increased by stacking a plurality of semiconductor devices and electronic components. It is possible to realize a high-density system with a minimum of.
- a circuit noise filter or the like is provided at a desired position of the laminated circuit including the semiconductor substrate 12, the first structural layer 13, the second structural layer 14, and the third structural layer 19.
- a capacitor that plays the role of decoupling may be provided.
- dielectric material constituting the capacitor examples include metal oxides such as titanium oxide, tantalum oxide, Al 2 O 3 , SiO 2 , ZrO 2 , HfO 2 , and Nb 2 O 5 ; BST (Ba x Sr 1-x TiO 3 ), PZT (PbZr x Ti 1 -x O 3), PLZT (Pb 1-y La y Zr x Ti 1-x O 3) perovskite such material (0 ⁇ x ⁇ 1,0 ⁇ y ⁇ 1); Bi-based layered compounds such as SrBi 2 Ta 2 O 9 are listed. Further, as a dielectric material constituting the capacitor, an organic material mixed with an inorganic material or a magnetic material may be used.
- the counter electrode is disposed at a desired position of one or more of the insulating layers in the second structural layer 14 and the third structural layer 19 on the upper and lower wiring layers via a dielectric having a dielectric constant of 9 or more.
- a capacitor that plays the role of a circuit noise filter or decoupling may be provided by forming.
- the dielectric material constituting the capacitor Al 2 O 3, ZrO 2 , HfO 2, Nb metal oxides such as 2 O 5; BST (Ba x Sr 1-x TiO 3), PZT (PbZr x Ti 1- x O 3 ), perovskite materials such as PLZT (Pb 1-y La y Zr x Ti 1-x O 3 ) (0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1); Bi such as SrBi 2 Ta 2 O 9 System layered compounds are mentioned. Further, as a dielectric material constituting the capacitor, an organic material mixed with an inorganic material or a magnetic material may be used.
- FIG. 11 is a partial cross-sectional view for explaining the present manufacturing example.
- the semiconductor substrate 12 may be ground to a thickness of less than 300 ⁇ m as necessary.
- a support member made of the same material or metal as that of the semiconductor substrate 12 may be used in order to improve handling properties.
- an element and a first structure layer 13 are formed on a semiconductor substrate 12.
- the first wiring 31 in the first structure layer 13 can be formed by the damascene method, and the insulating layers 28 and 29 can be formed by, for example, a CVD method or a spin coating method.
- the second structure layer 14 is formed so as to be in direct contact with the first structure layer 13 as described in the first embodiment.
- the second wiring 15 of the second structure layer 14 can be formed as described above, and is made of, for example, copper and has a thickness of, for example, 5 ⁇ m.
- the semi-additive method is preferable.
- the second insulating layer 16 of the second structure layer 14 can be formed by a CVD method or a spin coating method when an inorganic material is used as an insulating material.
- the opening serving as the second via 17 can be formed by dry etching.
- an organic material is used as the insulating material, either photosensitive or non-photosensitive can be used, and the second insulating layer can be formed by a spin coating method, a laminating method, a pressing method, or a printing method.
- the opening serving as the second via 17 can be formed by a photolithography method when a photosensitive resin is used, and a non-photosensitive organic material or an organic material having a low pattern resolution even when photosensitive is used.
- the second via 17 can be formed by filling the opening formed in this way with a conductive material.
- a metal post is formed in a portion to be the second via 17 by a plating method or a printing method, and after the second insulating layer 16 is formed, a second etching method, a CMP method, a grinding method, a lapping method, or the like is performed.
- the second via 17 can also be formed by removing a portion of the insulating layer 16 on the metal post and exposing the metal post.
- the opening of the second via 17 is indicated by a vertical wall, but a taper angle may be provided.
- a taper angle may be provided.
- the connection area between the second via 17 and the wiring of the first structural layer 13 can be reduced.
- the surface wiring density can be increased.
- connection reliability can be improved.
- the second via 17 has a taper angle, wiring formation is facilitated.
- the third structure layer 19 is placed on the opposite surface of the surface of the semiconductor substrate 12 on which the first structure layer 13 is formed. Form directly.
- the third wiring 20, the third insulating layer 21, and the third via 22 of the third structural layer 19 are formed in the same manner as the second wiring 15, the second insulating layer 16, and the second via 17 of the second structural layer described above. can do. If necessary, the aforementioned adhesion layer or roughened surface is formed.
- the manufacturing method described with reference to FIG. 11 has been described as an example of the manufacturing method of the structure shown in FIG. 2, the structure shown in FIG. 4 can be manufactured using a similar method.
- the second electrode 18 and the third electrode 23 may be manufactured to have the structure shown in FIG. 5B or 5C depending on the connection method employed.
- the semiconductor device according to the first embodiment can be efficiently formed. Also, as shown in FIG. 12A, a plurality of semiconductor devices 11 are formed on the wafer 39, and along the solid line in FIG. 12A and the broken line in FIG. 12B, blade dicing, laser dicing, The semiconductor device 11 may be cut into pieces by cutting with a water cutter, dry etching, wet etching, or the like.
- FIG. 13 is a partial cross-sectional view for explaining the present manufacturing example.
- the second manufacturing example is different from the first manufacturing example in that the second structural layer 14 and the third structural layer 19 are formed by being laminated simultaneously.
- differences from the first manufacturing example will be described. Parts not particularly described are the same as those in the first production example.
- the substrate side portion (wiring 15 and insulation) of the second structural layer 14 as shown in FIG. 13B are formed so as to be in direct contact with the first structural layer 13, and the substrate side portion (the wiring 20 and the insulating layer 21) of the third structural layer 19 is the substrate surface on which the first structural layer 13 is formed. Directly formed on the opposite surface. Subsequently, an upper layer side portion of the second structure layer and an upper layer side portion of the third structure layer are formed to form a desired structure shown in FIG.
- the insulating layer can be formed on both sides by attaching an insulating sheet on both sides and performing heat treatment.
- Wiring can be formed by forming electroless plating on both sides, forming a resist pattern on both sides, performing electrolytic plating on both sides simultaneously, and etching on both sides simultaneously.
- the manufacturing method described with reference to FIG. 13 has been described as an example of the manufacturing method of the structure illustrated in FIG. 2, the structure illustrated in FIG. 4 can be manufactured using a similar method.
- the second electrode 18 and the third electrode 23 may be manufactured to have the structure shown in FIG. 5B or 5C depending on the connection method employed.
- the semiconductor device according to the first embodiment can be efficiently formed.
- the semiconductor substrate 12 can be manufactured stably even if it is thin.
- FIG. 14 is a partial cross-sectional view for explaining the present manufacturing example.
- the third manufacturing example is different from the first manufacturing example in that the second structural layer 14 and the third structural layer 19 are alternately stacked in units of combinations of insulating layers and wirings. ing.
- differences from the first manufacturing example will be described. Parts not particularly described are the same as those in the first production example.
- the substrate side portion of the second structural layer 14 (wiring 15 and insulation).
- the layer 16 and the via 17) are formed so as to be in direct contact with the first structural layer 13.
- the substrate side portion (the wiring 20 and the insulating layer 21) of the third structure layer 19 is directly formed on the opposite surface of the substrate surface on which the first structure layer 13 is formed.
- an upper layer side portion of the second structure layer and an upper layer side portion of the third structure layer are formed to form a desired structure shown in FIG.
- the formation of the second insulating layer and the second wiring, and the formation of the third insulating layer and the formation of the third wiring are performed alternately.
- the manufacturing method described with reference to FIG. 14 has been described as an example of the manufacturing method of the structure illustrated in FIG. 2, but the structure illustrated in FIG. 4 can be manufactured using a similar method.
- the second electrode 18 and the third electrode 23 may be manufactured to have the structure shown in FIG. 5B or 5C depending on the connection method employed.
- the semiconductor device according to the first embodiment can be efficiently formed.
- the semiconductor substrate 12 can be stably manufactured even if it is thin, and the positional accuracy between the second structure layer 14 and the third structure layer 19 can be further increased.
- FIG. 15 is a partial cross-sectional view for explaining the present manufacturing example.
- the fourth manufacturing example is different from the first, second, and third manufacturing examples in that the through via 34 is formed in the semiconductor substrate 12.
- differences from the first, second, and third production examples will be described. Parts not particularly described are the same as those in the first, second, and third production examples.
- the element and the first structure layer 13 are formed on the semiconductor substrate 12, and the through via 34 is formed.
- the through via 34 can be formed by the method described in the second embodiment, and may be formed after the first structure layer 13 is formed, or may be formed before the first structure layer 13.
- the semiconductor substrate 12 is provided with a recess serving as a through via 34 and filled with a conductor, and then the first structure layer 13 is formed, and the surface of the semiconductor substrate 12 where the first structure layer 13 is not formed is ground.
- a method of exposing the through via 34 by etching may be performed.
- the through via 34 has a function necessary for the first structural layer 13 and the second structural layer 14 provided on one surface side of the semiconductor substrate 12 and the third structural layer 19 provided on the other surface side. It forms so that it may electrically connect according to. That is, one or both of the first structure layer 13 and the second structure layer 15 are electrically connected to the third structure layer 19.
- the second structure layer 14 and the third structure layer 19 can be formed by the steps described with reference to FIGS. 11, 13, and 14 after forming the structure shown in FIG.
- the semiconductor according to the second embodiment in addition to the effects of the first, second, and third manufacturing examples, the semiconductor according to the second embodiment in which the wiring on one surface side of the substrate and the wiring on the other surface side are connected.
- the apparatus can be manufactured efficiently.
- FIG. 16 is a partial cross-sectional view for explaining the present manufacturing example.
- the fifth manufacturing example is different from the fourth manufacturing example in that the through via 34 is formed in the semiconductor substrate 12 during the manufacturing process of the second structural layer 14. Below, a different point from the 4th manufacture example is explained. Parts not particularly described are the same as in the fourth production example.
- the substrate side portion (the wiring 15, the insulating layer 16, and the via 17) of the second structural layer 14 is formed on the first structural layer 13 in accordance with the manufacturing method described above.
- a through via 34 is formed in the semiconductor substrate 12.
- the through via 34 can be formed using the method described in the second embodiment.
- a recess is provided in a portion of the semiconductor substrate 12 where the through via 34 is formed, and after filling the conductor, a part of the first structure layer 13 and the second structure layer 14 is formed, and the first structure layer of the semiconductor substrate 12 is formed. You may perform the method of exposing the through-via 34 by grinding or etching the surface of the side in which 13 is not formed.
- the through via 34 has a function necessary for the first structure layer 13 and the second structure layer 14 provided on one surface side of the semiconductor substrate 12 and the third wiring structure 19 provided on the other surface side. It forms so that it may electrically connect according to. That is, one or both of the first structure layer 13 and the second structure layer 15 are electrically connected to the third structure layer 19.
- the remaining part of the second structure layer 14 and the third structure layer 19 are formed according to the above-described manufacturing method.
- the semiconductor according to the second embodiment in addition to the effects of the first, second, and third manufacturing examples, the semiconductor according to the second embodiment in which the wiring on one surface side of the substrate and the wiring on the other surface side are connected.
- the apparatus can be manufactured efficiently. Furthermore, it is easy to form the through via 34 that is directly connected to both the first structure layer 13 and the second structure layer 14, and a higher-density semiconductor device can be manufactured.
- FIG. 17 is a partial cross-sectional view for explaining the present manufacturing example.
- the sixth manufacturing example is different from the fifth manufacturing example in that the through via 34 is formed in the semiconductor substrate 12 after the formation process of the second structural layer 14 is completed.
- the through via 34 is formed in the semiconductor substrate 12 after the formation process of the second structural layer 14 is completed.
- the second structural layer 14 is formed on the first structural layer 13 in accordance with the manufacturing method described above.
- a through via 34 is formed in the semiconductor substrate 12.
- the through via 34 can be formed using the method described in the second embodiment.
- a recess is formed in a portion of the semiconductor substrate 12 where the through via 34 is formed, and after filling the conductor, the first structure layer 13 and the second structure layer 14 are formed, and the first structure layer 13 of the semiconductor substrate 12 is formed.
- the third wiring structure 19 is formed as shown in FIG.
- the second structure layer 14 and the third structure layer 19 shown in FIG. 17 are similar to the structure shown in FIG. 2, but the same method is used even if the structure is similar to the structure shown in FIG. It can be manufactured by a method. Moreover, you may produce the 2nd electrode 18 and the 3rd electrode 23 so that it may become a structure shown in FIG.5 (b) or (c) according to the connection method.
- the semiconductor according to the second embodiment in addition to the effects of the first, second, and third manufacturing examples, the semiconductor according to the second embodiment in which the wiring on one surface side of the substrate and the wiring on the other surface side are connected.
- the apparatus can be manufactured efficiently. Furthermore, it is easy to form the through via 34 that is directly connected to the second wiring 15 of the second structure layer 14, and a higher-density semiconductor device can be manufactured.
- FIG. 18 is a partial cross-sectional view for explaining the present manufacturing example.
- the through via 34 is formed in the semiconductor substrate 12 after the formation of the third insulating layer 21 on the substrate side in the step of forming the third structure layer 19 as compared with the sixth manufacturing example. Is different. Hereinafter, differences from the sixth production example will be described. Portions not particularly described are the same as in the sixth manufacturing method.
- the third insulation of the third structure layer 19 is formed on the other surface of the semiconductor substrate 12.
- the layer 21 is formed, and an opening corresponding to the through via 34 to be formed is provided.
- a through via 34 is formed in the semiconductor substrate 12 in accordance with the opening.
- the semiconductor according to the second embodiment in addition to the effects of the first, second, and third manufacturing examples, the semiconductor according to the second embodiment in which the wiring on one surface side of the substrate and the wiring on the other surface side are connected.
- the apparatus can be manufactured efficiently. Furthermore, the accuracy of the formation position of the through via 34 connected to the third structure layer 19 can be increased, and a higher density semiconductor device can be manufactured.
- FIG. 19 is a partial cross-sectional view for explaining the present manufacturing example.
- the eighth manufacturing example is different from the other manufacturing examples described above in that a plurality of semiconductor devices according to any of the above-described embodiments are stacked.
- the eighth production example will be described below. Portions that are not particularly described are the same as in the manufacturing method described above.
- a plurality of semiconductor devices are connected by a connecting portion 35.
- Connection of a plurality of semiconductor devices may be performed by connecting semiconductor device portions in a wafer state, connecting individual semiconductor devices, or connecting a semiconductor device portion in a wafer state and individual semiconductor devices. It doesn't matter.
- the semiconductor device portion in the wafer state can be divided after connection. From the viewpoint of yield, it is preferable that the semiconductor device as the lowermost layer is in a wafer state and the stacked semiconductor devices are connected as individual semiconductor devices.
- solder balls 36 as external terminals are formed on the lower surface side of the lowermost semiconductor device.
- solder balls 36 instead of such solder balls 36, a connection structure using pins, Au bumps, copper bumps, spare solder, metal pearls, ACF, NCF, or the like may be formed.
- the stacked semiconductor device shown in FIG. 19B corresponds to the stacked semiconductor device shown in FIG. 8, but the semiconductor device shown in FIGS. 9 and 10 can be manufactured by using a similar method. . Further, the present invention is not limited to the stacked structure of two semiconductor devices, and three or more semiconductor devices may be stacked.
- the semiconductor device according to the third embodiment can be efficiently manufactured.
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Abstract
The semiconductor device has a semiconductor substrate that includes an element, a first structural layer that includes a first insulating layer and first wiring electrically connected to the element and provided on one surface of the semiconductor substrate, a second structural layer that includes a second insulating layer and second wiring electrically connected to the first wiring, that is laminated on the first structural layer, and that is thicker than the first structural layer, and a third structural layer that includes a third insulating layer and third wiring and that is provided on the opposite surface of the semiconductor substrate from the surface where the first structural layer is provided.
Description
本発明は、半導体装置及びその製造方法に関し、特に多層配線構造を有する半導体装置に関する。
The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a multilayer wiring structure.
近年、電子機器の急激な小型化および薄型化の要求に伴い、半導体装置において特に薄型化と高密度化が求められている。また、電子機器の高性能化の要求に伴い、半導体素子の高速化、高機能化に従って、半導体装置における端子数の増加が必要となってきている。
In recent years, with the rapid demand for miniaturization and thinning of electronic devices, there has been a demand for thinning and high density especially in semiconductor devices. In addition, with the demand for higher performance of electronic devices, it is necessary to increase the number of terminals in a semiconductor device as the speed and functionality of semiconductor elements increase.
従来、半導体装置の薄型化と高密度化に対して、ＷＬＰ（Ｗａｆｅｒ Ｌｅｖｅｌ Ｐａｃｋａｇｅ）技術が用いられてきている。しかし、ＷＬＰ技術は、半導体装置の片面側にのみ配線層を設けるものであるため、コストや反りの面から、より一層の端子ピッチの拡張や、薄型化、高密度化が困難となってきている。
Conventionally, WLP (Wafer Level Package) technology has been used to reduce the thickness and increase the density of semiconductor devices. However, since the WLP technology provides a wiring layer only on one side of a semiconductor device, it is difficult to further expand the terminal pitch, to reduce the thickness, and to increase the density in terms of cost and warpage. Yes.
一方、半導体装置の両面側を利用する技術が検討されている。
On the other hand, technologies using both sides of the semiconductor device are being studied.
特開２００４－２７４０３５号公報（特許文献１）には、一対の配線基板間の絶縁層内部に、トランジスタやコンデンサ等の電子部品を埋設し、基板間で配線を接続するビアを設けた構造をもつ電子部品内蔵モジュールが開示されている。
Japanese Patent Laid-Open No. 2004-274035 (Patent Document 1) has a structure in which an electronic component such as a transistor or a capacitor is embedded in an insulating layer between a pair of wiring boards, and vias for connecting wirings between the boards are provided. An electronic component built-in module is disclosed.
特開２００７－０９６０３０号公報（特許文献２）及び特開２００８－１０３３８７号公報（特許文献３）には、ＣＳＰ（Ｃｈｉｐ Ｓｉｚｅ Ｐａｃｋａｇｅ）技術による半導体装置が開示されている。
Japanese Unexamined Patent Application Publication No. 2007-096030 (Patent Document 2) and Japanese Unexamined Patent Application Publication No. 2008-103387 (Patent Document 3) disclose semiconductor devices based on CSP (Chip Size Package) technology.
特許文献２に記載の半導体装置は、基板表面に形成された電子回路と、この電子回路に接続され基板表面に形成されたパッド電極と、半導体基板を貫通するビアホールと、このビアホールを通して前記パッド電極に接続する基板裏面上の配線層とを有し、この配線層に電気的に接続するように基板裏面上にボール状導電端子が設けられている。そして、これらのビアホール、パッド電極および配線層は、基板平面において、電子回路の形成領域の外側に配置されている。
A semiconductor device described in Patent Document 2 includes an electronic circuit formed on a substrate surface, a pad electrode connected to the electronic circuit and formed on the substrate surface, a via hole penetrating the semiconductor substrate, and the pad electrode through the via hole. And a wiring layer on the back surface of the substrate connected to the substrate, and ball-like conductive terminals are provided on the back surface of the substrate so as to be electrically connected to the wiring layer. These via holes, pad electrodes, and wiring layers are arranged outside the formation area of the electronic circuit on the substrate plane.
特許文献３に記載の半導体装置は、基板表面に形成された回路部と、この回路部に接続され基板表面に形成された表面配線と、半導体基板を貫通するビアホールと、このビアホールを通して前記表面配線に接続する基板裏面上の裏面配線とを有し、この裏面配線に電気的に接続するように基板裏面上に外部接続用バンプが設けられている。そして、これらのビアホールおよび裏面配線は、基板平面において、回路部の形成領域の外側に配置されている。
The semiconductor device described in Patent Document 3 includes a circuit unit formed on a substrate surface, a surface wiring connected to the circuit unit and formed on the substrate surface, a via hole penetrating the semiconductor substrate, and the surface wiring through the via hole. And external connection bumps are provided on the back surface of the substrate so as to be electrically connected to the back surface wiring. These via holes and backside wiring are arranged outside the circuit portion formation region on the substrate plane.
しかしながら、上述の特許文献に記載の技術には、以下に示すような問題点がある。
However, the techniques described in the above patent documents have the following problems.
特許文献１に記載の技術においては、半導体素子が形成されたウエハに直接配線層を形成する技術と比較して、埋設される電子部品と配線基板との接続点の微細化、高密度化が困難であり、電子部品に含まれる半導体素子の機能に制限が発生する。また、電子部品と配線基板に用いられる材料との熱膨張係数差が大きいため、薄型化によって、電子部品が埋設されている部分と埋設されていない部分との間において反りの方向と量が異なる反りが発生する。
In the technique described in Patent Document 1, the connection points between the embedded electronic component and the wiring board are made finer and higher in density than the technique of directly forming the wiring layer on the wafer on which the semiconductor element is formed. It is difficult and the function of the semiconductor element included in the electronic component is limited. Moreover, since the difference in thermal expansion coefficient between the electronic component and the material used for the wiring board is large, the direction and amount of warpage differ between the portion where the electronic component is embedded and the portion where it is not embedded due to the thinning. Warping occurs.
特許文献２及び３に記載の技術においては、半導体装置の表側と裏側との間で絶縁層や保護層の膜厚差や形成の有無があるため、半導体装置の表面側と裏面側との間で応力に偏りが生じ、反りが発生してしまう。特に、薄型化を達成するために半導体基板を薄くすると、応力の偏りによる反りが大きくなる。また、反り矯正と表面保護の目的で支持体を片面側に設けると、実効的な配線収容率が低くなってしまう。
In the techniques described in Patent Documents 2 and 3, since there is a difference in thickness or formation of an insulating layer or a protective layer between the front side and the back side of the semiconductor device, there is a gap between the front side and the back side of the semiconductor device. Therefore, stress is biased and warping occurs. In particular, when a semiconductor substrate is thinned in order to achieve a reduction in thickness, warping due to stress bias increases. Further, if the support is provided on one side for the purpose of warpage correction and surface protection, the effective wiring accommodation rate is lowered.
本発明の目的は、上述の課題を解決するためになされたものであり、高密度な半導体装置を提供することにある。
An object of the present invention has been made to solve the above-described problems, and is to provide a high-density semiconductor device.
本発明によれば、素子を含む基板と、
第１絶縁層、及び前記素子に電気的に接続された第１配線を含み、前記基板の片面に設けられた第１構造層と、
第１絶縁層、及び前記第１配線と電気的に接続された第２配線を含み、前記第１構造層上に積層された、前記第１構造層よりも厚い第２構造層と、
第３絶縁層および第３配線を含み、前記基板の前記第１構造層が設けられた面の反対面に設けられた第３構造層とを有する半導体装置が提供される。 According to the present invention, a substrate including an element;
A first insulating layer and a first structure layer provided on one side of the substrate, including a first wiring electrically connected to the element;
A second structure layer including a first insulating layer and a second wiring electrically connected to the first wiring, the second structure layer being stacked on the first structure layer and being thicker than the first structure layer;
A semiconductor device is provided that includes a third insulating layer and a third wiring, and a third structural layer provided on a surface opposite to the surface on which the first structural layer of the substrate is provided.
第１絶縁層、及び前記素子に電気的に接続された第１配線を含み、前記基板の片面に設けられた第１構造層と、
第１絶縁層、及び前記第１配線と電気的に接続された第２配線を含み、前記第１構造層上に積層された、前記第１構造層よりも厚い第２構造層と、
第３絶縁層および第３配線を含み、前記基板の前記第１構造層が設けられた面の反対面に設けられた第３構造層とを有する半導体装置が提供される。 According to the present invention, a substrate including an element;
A first insulating layer and a first structure layer provided on one side of the substrate, including a first wiring electrically connected to the element;
A second structure layer including a first insulating layer and a second wiring electrically connected to the first wiring, the second structure layer being stacked on the first structure layer and being thicker than the first structure layer;
A semiconductor device is provided that includes a third insulating layer and a third wiring, and a third structural layer provided on a surface opposite to the surface on which the first structural layer of the substrate is provided.
また本発明によれば、前記第１構造層が、前記第１絶縁層と前記第１配線が交互に積層された多層配線構造を有し、前記第２構造層が、前記第２絶縁層と前記第２配線が交互に積層された多層配線構造を有し、前記第３構造層が、前記第３絶縁層と前記第３配線が交互に積層された多層配線構造を有する、上記の半導体装置が提供される。
According to the invention, the first structural layer has a multilayer wiring structure in which the first insulating layer and the first wiring are alternately stacked, and the second structural layer includes the second insulating layer and the second insulating layer. The semiconductor device according to claim 1, wherein the semiconductor device has a multilayer wiring structure in which the second wirings are alternately stacked, and the third structure layer has a multilayer wiring structure in which the third insulating layers and the third wirings are alternately stacked. Is provided.
また本発明によれば、前記第２配線が、前記第１配線より厚い、上記のいずれかの半導体装置が提供される。
Also, according to the present invention, there is provided any one of the above semiconductor devices, wherein the second wiring is thicker than the first wiring.
また本発明によれば、前記第２絶縁層が、前記第１絶縁層より厚い、上記のいずれかの半導体装置が提供される。
Further, according to the present invention, there is provided any one of the above semiconductor devices, wherein the second insulating layer is thicker than the first insulating layer.
また本発明によれば、前記第３配線が、前記第１配線より厚い、上記のいずれかの半導体装置が提供される。
Also, according to the present invention, there is provided any one of the above semiconductor devices, wherein the third wiring is thicker than the first wiring.
また本発明によれば、前記第３絶縁層が、前記第１絶縁層より厚い、上記のいずれかの半導体装置が提供される。
Also, according to the present invention, there is provided any one of the above semiconductor devices, wherein the third insulating layer is thicker than the first insulating layer.
また本発明によれば、前記第２構造層において、前記第１構造層内の複数の電源系配線をまとめて端子数が低減するように電源系配線が形成されている、上記のいずれかの半導体装置が提供される。
According to the invention, in the second structural layer, the power supply system wiring is formed so that the number of terminals is reduced by combining a plurality of power supply system wirings in the first structure layer. A semiconductor device is provided.
また本発明によれば、前記第２構造層において、前記第１構造層内の複数のグランド系配線をまとめて端子数が低減するようにグランド系配線が形成されている、上記のいずれかの半導体装置が提供される。
According to the invention, in the second structural layer, the ground wiring is formed so as to reduce the number of terminals by combining a plurality of ground wirings in the first structural layer. A semiconductor device is provided.
また本発明によれば、前記基板を貫通し、前記第１配線または前記第２配線と前記第３配線とを電気的に接続する、貫通ビアを有する、上記のいずれかの半導体装置が提供される。
In addition, according to the present invention, there is provided any one of the above semiconductor devices having a through via that penetrates the substrate and electrically connects the first wiring or the second wiring to the third wiring. The
また本発明によれば、前記第３構造層において、前記第１構造層内の複数の電源系配線をまとめて端子数が低減するように電源系配線が形成されている、上記の半導体装置が提供される。
According to the present invention, there is provided the above semiconductor device, wherein in the third structure layer, the power supply system wiring is formed so as to reduce the number of terminals by combining a plurality of power supply system wirings in the first structure layer. Provided.
また本発明によれば、前記第３構造層において、前記第１構造層内の複数のグランド系配線をまとめて端子数が低減するようにグランド系配線が形成されている、上記のいずれかの半導体装置が提供される。
According to the invention, in the third structure layer, the ground wiring is formed so that the number of terminals is reduced by combining a plurality of ground wirings in the first structural layer. A semiconductor device is provided.
また本発明によれば、前記第２構造層の前記第２配線の層数と前記第３構造層の前記第３配線の層数とが同じである、上記のいずれかの半導体装置が提供される。
Furthermore, according to the present invention, there is provided any one of the above semiconductor devices, wherein the number of the second wirings in the second structural layer is the same as the number of the third wirings in the third structural layer. The
また本発明によれば、前記第２構造層の前記第２絶縁層の層数と前記第３構造層の前記第３絶縁層の層数とが同じである、上記のいずれかの半導体装置が提供される。
According to the invention, there is provided the semiconductor device according to any one of the above, wherein the number of the second insulating layers of the second structural layer is the same as the number of the third insulating layers of the third structural layer. Provided.
また本発明によれば、上記のいずれかの同種または異種の複数の半導体装置が積層されていることを特徴とする半導体装置が提供される。
Further, according to the present invention, there is provided a semiconductor device characterized in that a plurality of the same or different semiconductor devices described above are stacked.
また本発明によれば、上記のいずれかの半導体装置を製造する製造方法であって、
複数の素子が形成された基板を用意する工程と、
前記基板の片面側に、前記第１構造層を形成する工程と、
前記第１構造層上に、前記第２構造層を形成する工程と、
前記基板の前記第１構造層が設けられた面の反対面に第３構造層を形成する工程とを有する、半導体装置の製造方法が提供される。 According to the present invention, there is also provided a manufacturing method for manufacturing any one of the above semiconductor devices,
Preparing a substrate on which a plurality of elements are formed;
Forming the first structure layer on one side of the substrate;
Forming the second structure layer on the first structure layer;
Forming a third structure layer on a surface opposite to the surface of the substrate on which the first structure layer is provided.
複数の素子が形成された基板を用意する工程と、
前記基板の片面側に、前記第１構造層を形成する工程と、
前記第１構造層上に、前記第２構造層を形成する工程と、
前記基板の前記第１構造層が設けられた面の反対面に第３構造層を形成する工程とを有する、半導体装置の製造方法が提供される。 According to the present invention, there is also provided a manufacturing method for manufacturing any one of the above semiconductor devices,
Preparing a substrate on which a plurality of elements are formed;
Forming the first structure layer on one side of the substrate;
Forming the second structure layer on the first structure layer;
Forming a third structure layer on a surface opposite to the surface of the substrate on which the first structure layer is provided.
また本発明によれば、前記第２構造層および前記第３構造層の形成において、前記第２絶縁層の形成と前記第３絶縁層の形成を同じプロセスで同時に行い、前記第２配線の形成と前記第３配線の形成を同じプロセスで同時に行う、上記の半導体装置の製造方法が提供される。
According to the invention, in the formation of the second structure layer and the third structure layer, the formation of the second wiring is performed simultaneously with the formation of the second insulation layer and the formation of the third insulation layer in the same process. And the method of manufacturing the semiconductor device, wherein the third wiring is simultaneously formed in the same process.
また本発明によれば、前記第２構造層および前記第３構造層の形成において、前記第２絶縁層の形成および前記第２配線の形成と、前記第３絶縁層の形成および前記第３配線の形成とを交互に行う、上記の半導体装置の製造方法が提供される。
According to the invention, in the formation of the second structural layer and the third structural layer, the formation of the second insulating layer and the second wiring, the formation of the third insulating layer, and the third wiring There is provided a method for manufacturing the semiconductor device described above, wherein the formation of the semiconductor device is alternately performed.
また本発明によれば、前記第１構造層を形成する工程前又は後において、前記基板を貫通するビアを形成する、上記のいずれかの半導体装置の製造方法が提供される。
Also, according to the present invention, there is provided a method for manufacturing any one of the above semiconductor devices, wherein a via penetrating the substrate is formed before or after the step of forming the first structure layer.
また本発明によれば、前記第２構造層を形成する工程途中において、前記基板を貫通するビアを形成する、上記のいずれかの半導体装置の製造方法が提供される。
Further, according to the present invention, there is provided a method for manufacturing any one of the above semiconductor devices, wherein a via penetrating the substrate is formed in the course of forming the second structural layer.
また本発明によれば、前記第２構造層を形成する工程の後、前記第３構造層を形成する工程の前に、前記基板を貫通するビアを形成する、上記のいずれかの半導体装置の製造方法が提供される。
According to the invention, the via of penetrating the substrate is formed after the step of forming the second structural layer and before the step of forming the third structural layer. A manufacturing method is provided.
また本発明によれば、前記第３構造層を形成する工程途中において、前記基板を貫通するビアを形成する、上記のいずれかの半導体装置の製造方法が提供される。
Further, according to the present invention, there is provided a method for manufacturing any one of the above semiconductor devices, wherein a via penetrating the substrate is formed during the step of forming the third structure layer.
また本発明によれば、前記第１構造層を形成する工程の後、又は前記第２構造層を形成する工程の後に、前記基板を薄化する工程を行う、上記のいずれかの半導体装置の製造方法に関する。
According to the invention, in any one of the above semiconductor devices, the step of thinning the substrate is performed after the step of forming the first structural layer or the step of forming the second structural layer. It relates to a manufacturing method.
また本発明によれば、前記第１構造層と前記第２構造層と前記第３構造層を含む多層配線構造を、前記基板を含む半導体ウエハに複数形成し、その後、前記多層配線構造をそれぞれ含む各個片に分割する、上記のいずれかの半導体装置の製造方法が提供される。
According to the invention, a plurality of multilayer wiring structures including the first structural layer, the second structural layer, and the third structural layer are formed on a semiconductor wafer including the substrate, and then the multilayer wiring structures are respectively formed. A method of manufacturing any one of the above semiconductor devices is provided, which is divided into individual pieces.
また本発明によれば、上記のいずれかの方法により同種または異種の複数の半導体装置を形成する工程と、これらの半導体装置を積層する工程を含む、半導体装置の製造方法が提供される。
Further, according to the present invention, there is provided a method for manufacturing a semiconductor device, including a step of forming a plurality of semiconductor devices of the same type or different types by any one of the methods described above, and a step of stacking these semiconductor devices.
本発明によれば、高密度な半導体装置を提供することができる。
According to the present invention, a high-density semiconductor device can be provided.
本発明の一実施形態の半導体装置は、複数の素子を含む基板の片面に、第１構造層と、この第１構造層上に積層された、第１構造層より厚い第２構造層とが設けられ、前記基板の第１構造層が設けられた面の反対面に、第３構造層が設けられている。第１構造層は、第１絶縁層および前記素子に電気的に接続された第１配線を含む。第２構造層は、第２絶縁層および第１配線と電気的に接続された第２配線を含む。第３構造層は、第３絶縁層および第３配線を含む。
In the semiconductor device according to an embodiment of the present invention, a first structure layer and a second structure layer stacked on the first structure layer and thicker than the first structure layer are provided on one surface of a substrate including a plurality of elements. A third structure layer is provided on a surface opposite to the surface of the substrate on which the first structure layer is provided. The first structural layer includes a first insulating layer and a first wiring electrically connected to the element. The second structural layer includes a second wiring electrically connected to the second insulating layer and the first wiring. The third structure layer includes a third insulating layer and a third wiring.
第１構造層は、第１配線が層間絶縁膜を介して複数積層されている場合、上層側の配線と下層側の配線を接続するための第１ビアを有する。第２構造層は、第２配線が層間絶縁膜を介して複数積層されている場合、上層側の配線と下層側の配線を接続するための第２ビアを有する。第３構造層は、第３配線が層間絶縁膜を介して複数積層されている場合、上層側の配線と下層側の配線を接続するための第３ビアを有する。第１構造層中の配線およびビアをそれぞれ「第１配線」および「第１ビア」と総称し、第２構造層中の配線およびビアをそれぞれ「第２配線」および「第２ビア」と総称し、第３構造層中の配線およびビアをそれぞれ「第３配線」および「第３ビア」と総称する。
The first structure layer has a first via for connecting an upper layer side wiring and a lower layer side wiring when a plurality of first wirings are laminated via an interlayer insulating film. The second structure layer has a second via for connecting the upper layer side wiring and the lower layer side wiring when a plurality of second wirings are stacked via the interlayer insulating film. The third structure layer has a third via for connecting the upper layer side wiring and the lower layer side wiring when a plurality of third wirings are stacked via the interlayer insulating film. Wirings and vias in the first structural layer are collectively referred to as “first wiring” and “first via”, respectively, and wirings and vias in the second structural layer are collectively referred to as “second wiring” and “second via”, respectively. The wirings and vias in the third structure layer are collectively referred to as “third wiring” and “third via”, respectively.
このような半導体装置は、第２構造層と第３構造層を有しているため、半導体装置の配線収容率を高めることができ、さらに、半導体装置の基板両側に他の半導体装置やチップ部品などの電子部品を高密度で搭載することが可能になる。
Since such a semiconductor device has the second structure layer and the third structure layer, the wiring accommodation rate of the semiconductor device can be increased, and further, other semiconductor devices and chip components are provided on both sides of the substrate of the semiconductor device. It becomes possible to mount electronic parts such as high density.
また、第２構造層と第３構造層に含まれる各絶縁層の作用により、衝撃を受けることで発生する欠けやクラックを防止することができ、耐衝撃性を向上させることができる。
In addition, due to the action of each insulating layer included in the second structure layer and the third structure layer, it is possible to prevent chipping and cracks caused by receiving an impact, and to improve impact resistance.
また、第２構造層の配線層と第３構造層の配線層の両方又は一方を、第１構造層の配線層より厚くすることで安定した電源供給が実現でき、さらに第１構造層よりも低損失な信号伝送を達成することができる。
In addition, stable power supply can be realized by making both or one of the wiring layer of the second structure layer and the wiring layer of the third structure layer thicker than the wiring layer of the first structure layer, and moreover than the first structure layer. Low-loss signal transmission can be achieved.
また、第２構造層の絶縁層と第３構造層の絶縁層の両方又は一方を、第１構造層の絶縁層より厚くすることで、半導体装置を実装基板や別部品と接続した際に発生する応力をより十分に緩和することができ、接続信頼性を向上させることができる。
Also, it occurs when the semiconductor device is connected to a mounting board or another component by making the insulating layer of the second structural layer and / or the insulating layer of the third structural layer thicker than the insulating layer of the first structural layer. Stress can be relaxed more sufficiently, and connection reliability can be improved.
上記実施形態の半導体装置においては、基板の両面側に、絶縁層と配線層を含む構造層を設けていることにより、基板の片面側の応力と反対面側の応力との均一化を図ることができ、基板が薄い場合であっても反り量を抑えることができる。具体的には、上記のとおり、基板の片面側に第２構造層を設け、反対面側に第３構造層を設けることにより、基板の両面側に発生する応力を相殺することができ、反り量が少ない半導体装置を実現することができ、より薄型の半導体装置を提供できる。このような観点から、第２構造層および第３構造層の厚みは第１構造層より十分に厚いことが好ましく、第２構造層および第３構造層の厚みが厚いほど、第１構造層による応力の影響を相対的に小さくすることができ、第１構造層の構造に大きく影響されることなく、第２構造層と第３構造層とにより応力の均一化を図ることができる。第２構造層および第３構造層の厚みが第１構造層の厚みに対してそれほど大きくない場合は、第１の構造層と第２の構造層との合計厚みと第３の厚みとのバランスを考慮して第２構造層と第３構造層の厚みを設定することが望ましい。
In the semiconductor device of the above embodiment, by providing a structural layer including an insulating layer and a wiring layer on both sides of the substrate, the stress on one side of the substrate and the stress on the opposite side can be made uniform. Even if the substrate is thin, the amount of warpage can be suppressed. Specifically, as described above, by providing the second structural layer on one side of the substrate and providing the third structural layer on the opposite side, the stress generated on both sides of the substrate can be offset and warped. A semiconductor device with a small amount can be realized, and a thinner semiconductor device can be provided. From such a viewpoint, it is preferable that the thickness of the second structure layer and the third structure layer is sufficiently thicker than that of the first structure layer. The thicker the second structure layer and the third structure layer, the greater the thickness of the first structure layer. The influence of stress can be made relatively small, and the stress can be made uniform by the second structure layer and the third structure layer without being greatly affected by the structure of the first structure layer. When the thicknesses of the second structural layer and the third structural layer are not so large with respect to the thickness of the first structural layer, the balance between the total thickness of the first structural layer and the second structural layer and the third thickness It is desirable to set the thicknesses of the second structure layer and the third structure layer in consideration of the above.
上記実施形態の半導体装置の第２構造層と第３構造層との間において、配線層と絶縁層の両方もしくは片方を同数にすることによって、反り量低減効果をより高めることができる。
The effect of reducing the amount of warpage can be further increased by using the same number of wiring layers and / or insulating layers between the second structure layer and the third structure layer of the semiconductor device of the above embodiment.
上述の効果をより十分に得る点から、第２構造層および第３構造層の厚みは、第１構造層の厚みの２倍以上が好ましく、３倍以上がより好ましく、反りをより一層抑制する観点から５倍以上が好ましい。第２配線層の厚みＴ２と第３構造層の厚みＴ３の比（Ｔ２／Ｔ３）は、０．７～１．３の範囲にあることが好ましく、０．８～１．２の範囲にあることがより好ましい。第１配線の厚みは、０．１～１．６μｍが好ましく、０．２～１．２μｍがより好ましく、第２配線および第３配線の厚みは、３～１２μｍが好ましく、５～１０μｍがより好ましい。第１絶縁層の厚みは、０．１～１．６μｍが好ましく、０．２～１．２μｍがより好ましく、第２絶縁層および第３絶縁層の厚みは、５～５０μｍが好ましく、１０～３０μｍがより好ましい。
From the viewpoint of obtaining the above-described effect more sufficiently, the thickness of the second structure layer and the third structure layer is preferably at least twice the thickness of the first structure layer, more preferably at least three times, and further suppress warpage. From the viewpoint, 5 times or more is preferable. The ratio (T2 / T3) of the thickness T2 of the second wiring layer and the thickness T3 of the third structure layer is preferably in the range of 0.7 to 1.3, and in the range of 0.8 to 1.2. It is more preferable. The thickness of the first wiring is preferably 0.1 to 1.6 μm, more preferably 0.2 to 1.2 μm, and the thickness of the second wiring and the third wiring is preferably 3 to 12 μm, more preferably 5 to 10 μm. preferable. The thickness of the first insulating layer is preferably 0.1 to 1.6 μm, more preferably 0.2 to 1.2 μm. The thickness of the second insulating layer and the third insulating layer is preferably 5 to 50 μm, preferably 10 to 30 μm is more preferable.
なお、上述の実施形態において、第１構造層は、基板に接する絶縁層から最上層の配線を含む層までに相当し、第２構造層は、第１構造層の最上層の配線上に接する層（絶縁層または配線）から、第２構造層の最上層の配線上に接する絶縁層までに相当し、第３の構造層は、基板の反対面に接する層（絶縁層または配線）から、第３構造層の最上層の配線上に接する絶縁層までに相当する。
In the above-described embodiment, the first structure layer corresponds to the insulating layer in contact with the substrate to the layer including the uppermost layer wiring, and the second structure layer is in contact with the uppermost layer wiring of the first structure layer. It corresponds to a layer (insulating layer or wiring) to an insulating layer in contact with the uppermost wiring of the second structural layer, and the third structural layer is from a layer (insulating layer or wiring) in contact with the opposite surface of the substrate. This corresponds to the insulating layer in contact with the uppermost wiring of the third structure layer.
以下、本発明の好適な実施形態について図面を参照して具体的に説明する。
Hereinafter, preferred embodiments of the present invention will be specifically described with reference to the drawings.
第１の実施形態
まず、本発明の第１の実施形態について説明する。 First Embodiment First, a first embodiment of the present invention will be described.
まず、本発明の第１の実施形態について説明する。 First Embodiment First, a first embodiment of the present invention will be described.
図１は本発明の第１実施形態による半導体装置を示す斜視図であり、図２はこの半導体装置の一部を示す部分断面図であり、図３は図２に示される半導体装置の第１構造層１３の拡大断面図である。なお、図１においては第１構造層１３を省略している。
1 is a perspective view showing a semiconductor device according to a first embodiment of the present invention, FIG. 2 is a partial sectional view showing a part of the semiconductor device, and FIG. 3 is a first view of the semiconductor device shown in FIG. 3 is an enlarged cross-sectional view of a structural layer 13. FIG. In FIG. 1, the first structure layer 13 is omitted.
本実施形態の半導体装置１１は、図１に示すように、半導体基板１２の片面側に第２構造層１４が設けられ、反対側に第３構造層１９が設けられている。図２に示すように、半導体基板１２の片面に第１構造層１３が設けられ、この上に直接第２構造層１４が設けられている。図３に示すように、半導体基板１２には素子３０が設けられている。半導体基板１２は、例えばＳｉ、ゲルマニウム、ガリウム砒素（ＧａＡｓ）、ガリウム砒素リン、窒化ガリウム（ＧａＮ）、炭化珪素（ＳｉＣ）、II－VI族化合物、III－Ｖ族化合物、ダイアモンドなどにより形成されている。サファイア、ガラス等からなる支持基板上にこれらの半導体材料からなる半導体層が設けられた基板を用いてもよい。
In the semiconductor device 11 of this embodiment, as shown in FIG. 1, the second structure layer 14 is provided on one side of the semiconductor substrate 12, and the third structure layer 19 is provided on the opposite side. As shown in FIG. 2, the first structure layer 13 is provided on one surface of the semiconductor substrate 12, and the second structure layer 14 is directly provided thereon. As shown in FIG. 3, an element 30 is provided on the semiconductor substrate 12. The semiconductor substrate 12 is formed of, for example, Si, germanium, gallium arsenide (GaAs), gallium arsenide phosphorus, gallium nitride (GaN), silicon carbide (SiC), II-VI group compound, III-V group compound, diamond, or the like. Yes. You may use the board | substrate with which the semiconductor layer which consists of these semiconductor materials was provided on the support substrate which consists of sapphire, glass, etc.
第２構造層１４は、図２に示すように、第２配線１５、第２絶縁層１６、第２ビア１７を含み、第２配線１５及び第２絶縁層１６が交互に積層されている。この積層構造において、上層側の第２配線と下層側の第２配線は、これら配線層間の第２絶縁層を貫通する第２ビアにより接続され、最下層側の第２配線は、最下層側の第２絶縁層（第１構造層上の第２絶縁層）を貫通する第２ビアにより第１構造層表面側の配線層３１と接続されている。第２構造層は、図２に示す構造に限定されるものではなく、第１構造層上に設けられた第２絶縁層１６と、この第２絶縁層上に設けられた第２配線１５と、この第２配線と第１構造層の表面側の配線３１とを接続する第２ビア１７を少なくとも有していればよく、また、図２に示す層数以上に積層されていてもよい。
As shown in FIG. 2, the second structure layer 14 includes second wirings 15, second insulating layers 16, and second vias 17, and the second wirings 15 and the second insulating layers 16 are alternately stacked. In this laminated structure, the second wiring on the upper layer side and the second wiring on the lower layer side are connected by a second via penetrating the second insulating layer between these wiring layers, and the second wiring on the lowermost layer side is connected to the lowermost layer side. Are connected to the wiring layer 31 on the surface side of the first structural layer by a second via penetrating through the second insulating layer (second insulating layer on the first structural layer). The second structure layer is not limited to the structure shown in FIG. 2, and the second insulating layer 16 provided on the first structure layer, and the second wiring 15 provided on the second insulating layer, As long as it has at least the second via 17 that connects the second wiring and the wiring 31 on the surface side of the first structure layer, the number of layers may be greater than that shown in FIG.
第２構造層１４の表面側には、第２電極１８が設けられており、第２配線１５と電気的に接続されている。
The second electrode 18 is provided on the surface side of the second structure layer 14 and is electrically connected to the second wiring 15.
第３構造層１９は、図２に示すように、半導体基板１２の第１構造層１３が設けられた面の反対面に設けられ、第３配線２０、第３絶縁層２１、第３ビア２２を含み、第３配線２０及び第３絶縁層２１が交互に積層されている。この積層構造において、上層側の第３配線と下層側の第３配線は、これら配線層間の第３絶縁層を貫通する第３ビアにより接続されている。第３構造層は、図２に示す構造に制限されるものではなく、半導体基板上に設けられた第３絶縁層２１と、この第３絶縁層上に設けられた第３配線２０を少なくとも有していればよく、また、図２に示す層数以上に積層されていてもよい。
As shown in FIG. 2, the third structure layer 19 is provided on the surface opposite to the surface on which the first structure layer 13 of the semiconductor substrate 12 is provided, and the third wiring 20, the third insulating layer 21, and the third via 22. The third wirings 20 and the third insulating layers 21 are alternately stacked. In this laminated structure, the third wiring on the upper layer side and the third wiring on the lower layer side are connected by a third via penetrating the third insulating layer between these wiring layers. The third structure layer is not limited to the structure shown in FIG. 2, and has at least a third insulating layer 21 provided on the semiconductor substrate and a third wiring 20 provided on the third insulating layer. It may be sufficient and it may be laminated more than the number of layers shown in FIG.
第３構造層１９の表面側には、第３電極２３が設けられており、第３配線２０と電気的に接続されている。
The third electrode 23 is provided on the surface side of the third structure layer 19 and is electrically connected to the third wiring 20.
図２に示す構造では、第２配線１５と第３配線２０の積層数が同じであり、さらに、第２絶縁層１６と第３絶縁層２１の積層数が同じであるが、これに限らず、積層数が異なっていてもよい。ただし、反り量を少なくする観点から、第２配線１５と第３配線２０の積層数、および第２絶縁層１６と第３絶縁層２１の積層数のいずれか片方、もしくは両方が同じ層数であることが望ましい。
In the structure shown in FIG. 2, the number of stacked layers of the second wiring 15 and the third wiring 20 is the same, and the number of stacked layers of the second insulating layer 16 and the third insulating layer 21 is the same. The number of layers may be different. However, from the viewpoint of reducing the amount of warpage, one or both of the number of stacked layers of the second wiring 15 and the third wiring 20 and the number of stacked layers of the second insulating layer 16 and the third insulating layer 21 are the same number of layers. It is desirable to be.
外部端子となる第２電極１８と第３電極２３は、それぞれ表層側の配線で構成し、接続方法にあわせて位置変更を行ってもよいし、それぞれ第２ビア１７及び第３ビア２２上に直接設けてもよい。
The second electrode 18 and the third electrode 23 that are external terminals are each configured by wiring on the surface layer side, and the position may be changed according to the connection method, or on the second via 17 and the third via 22, respectively. You may provide directly.
第１構造層は、図３に示すように、複数の半導体素子３０が形成された半導体基板１２上に設けられている。本実施形態では、半導体素子３０として、ＭＯＳトランジスタ（Ｍｅｔａｌ Ｏｘｉｄｅ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ：金属酸化物半導体）が設けられている。このＭＯＳトランジスタは、半導体基板１２表面に設けられたソース領域２５及びドレイン領域２６と、これらの領域に挟まれた領域上にゲート絶縁膜（図示せず）を介して設けられたゲート電極２４から構成されている。このような平面型のＭＯＳトランジスタに代えて、３次元構造を持つ縦型トランジスタやＦｉｎ型ＦＥＴ、あるいは有機材料を用いたトランジスタであってもよい。
As shown in FIG. 3, the first structure layer is provided on the semiconductor substrate 12 on which a plurality of semiconductor elements 30 are formed. In the present embodiment, a MOS transistor (Metal Oxide Semiconductor: metal oxide semiconductor) is provided as the semiconductor element 30. This MOS transistor includes a source region 25 and a drain region 26 provided on the surface of the semiconductor substrate 12, and a gate electrode 24 provided on a region sandwiched between these regions via a gate insulating film (not shown). It is configured. Instead of such a planar MOS transistor, a vertical transistor having a three-dimensional structure, a Fin-type FET, or a transistor using an organic material may be used.
これらの半導体素子３０を覆うように半導体基板１２上に層間絶縁膜２９が設けられ、この層間絶縁膜２９上には配線３１（第１配線）が設けられている。配線３１間は絶縁膜３２で充填され、この配線間絶縁膜３２と配線３１からなる配線層２８が形成されている。このような配線層２８（第１配線３１と配線間絶縁膜３２）と層間絶縁膜２９（第１絶縁層）が交互に積層され多層配線構造が形成されている。最下層側の配線３１は、最下層側の層間絶縁膜２９に形成されたプラグ２７を介してソース領域２５又はドレイン領域２６と電気的に接続されている。この多層配線構造における上層側の配線３１と下層側の配線３１は、これら配線間の層間絶縁膜２９に形成されたビア３３を介して電気的に接続されている。
An interlayer insulating film 29 is provided on the semiconductor substrate 12 so as to cover these semiconductor elements 30, and a wiring 31 (first wiring) is provided on the interlayer insulating film 29. A space between the wirings 31 is filled with an insulating film 32, and a wiring layer 28 composed of the inter-wiring insulating film 32 and the wirings 31 is formed. Such a wiring layer 28 (first wiring 31 and inter-wiring insulating film 32) and interlayer insulating film 29 (first insulating layer) are alternately laminated to form a multilayer wiring structure. The lowermost wiring 31 is electrically connected to the source region 25 or the drain region 26 through a plug 27 formed in the lowermost interlayer insulating film 29. The upper layer side wiring 31 and the lower layer side wiring 31 in this multilayer wiring structure are electrically connected through a via 33 formed in the interlayer insulating film 29 between these wirings.
第１構造層１３の配線材料としては、例えば銅やアルミニウムが挙げられる。第１構造層の配線は、例えばダマシン法により形成できる。ダマシン法による配線の形成は、例えば次にようにして行うことができる。まず、絶縁膜の形成し、この絶縁膜に、リソグラフィ技術とドライエッチング技術を用いて所望の配線パターンに対応する溝（トレンチ）又はビアパターンに対応するホールを形成する。次に、この溝又はホール内を含む全面に、バリアメタル層をスパッタ法、ＣＶＤ（Ｃｈｅｍｉｃａｌ Ｖａｐｅｒ Ｄｅｐｏｓｉｔｉｏｎ）法、ＡＬＤ（Ａｔｏｍｉｃ Ｌａｙｅｒ Ｄｅｐｏｓｉｔｉｏｎ）法等で形成し、電解めっき用の給電層をスパッタ法等で形成し、電解銅めっき法にて溝又はホールを埋め込むように銅膜を形成する。次に、ＣＭＰ（Ｃｈｅｍｉｃａｌ Ｍｅｃｈａｎｉｃａｌ Ｐｏｌｉｓｈｉｎｇ）法により溝又はホール内のみに銅が残るように銅膜を研磨する。
Examples of the wiring material for the first structural layer 13 include copper and aluminum. The wiring of the first structure layer can be formed by, for example, a damascene method. The formation of wiring by the damascene method can be performed as follows, for example. First, an insulating film is formed, and a groove (trench) corresponding to a desired wiring pattern or a hole corresponding to a via pattern is formed in the insulating film using a lithography technique and a dry etching technique. Next, a barrier metal layer is formed on the entire surface including the inside of the groove or hole by a sputtering method, a CVD (Chemical Vapor Deposition) method, an ALD (Atomic Layer Deposition) method, etc., and a power supply layer for electrolytic plating is formed by a sputtering method, Then, a copper film is formed so as to fill the groove or hole by electrolytic copper plating. Next, the copper film is polished by CMP (Chemical Mechanical Polishing) so that copper remains only in the groove or hole.
第１構造層１３における層間絶縁膜２９は、その厚みを、０．２～２μｍの範囲に設定でき、例えば０．２～１．６μｍに設定できる。複数の層間絶縁膜２９のうち、半導体基板１２の近くに設けられている少なくとも１つの層間絶縁膜をｌｏｗ－ｋ材で形成することが望ましい。ｌｏｗ－ｋ材としては、例えば多孔質酸化シリコン膜が挙げられ、２５℃での弾性率が４～１０ＧＰａの範囲にあるものが望ましい。
The thickness of the interlayer insulating film 29 in the first structure layer 13 can be set in the range of 0.2 to 2 μm, for example, 0.2 to 1.6 μm. Of the plurality of interlayer insulating films 29, at least one interlayer insulating film provided near the semiconductor substrate 12 is preferably formed of a low-k material. An example of the low-k material is a porous silicon oxide film, and it is desirable that the elastic modulus at 25 ° C. is in the range of 4 to 10 GPa.
第２構造層１４の第２配線１５と第３構造層１９の第３配線２０は、例えば銅を用いて形成でき、その厚さは例えば５μｍである。第２配線１５と第３配線２０は、例えばサブトラクティブ法、セミアディティブ法、フルアディティブ法等の第１構造層１３の配線とは異なる配線形成法により形成することができる。サブトラクティブ法は、例えば特開平１０－５１１０５号公報に記載されているように、基板又は樹脂上に設けられた銅箔を、所望のパターンのレジストをマスクに用いてエッチングし、その後にレジストを除去して所望の配線パターンを得る方法である。セミアディティブ法は、例えば特開平９－６４４９３号公報に記載されているように、無電解めっき、スパッタ法、ＣＶＤ法、エアロゾル法等で給電層を形成した後、所望のパターンに開口されたレジストを形成し、レジスト開口部内に電解めっきを析出させ、レジストを除去後に給電層をエッチングして所望の配線パターンを得る方法である。フルアディティブ法は、例えば特開平６－３３４３３４号公報に記載されているように、基板又は樹脂の表面に無電解めっき触媒を吸着させた後に所望のパターンのレジストを形成し、このレジストを絶縁層として残したまま触媒を活性化し、無電解めっき法により絶縁層の開口部に金属を析出させることで所望の配線パターンを得る方法である。
The second wiring 15 of the second structure layer 14 and the third wiring 20 of the third structure layer 19 can be formed using, for example, copper, and the thickness thereof is, for example, 5 μm. The second wiring 15 and the third wiring 20 can be formed by a wiring forming method different from the wiring of the first structure layer 13 such as a subtractive method, a semi-additive method, and a full additive method. In the subtractive method, for example, as described in JP-A-10-51105, a copper foil provided on a substrate or a resin is etched using a resist having a desired pattern as a mask, and then the resist is removed. In this method, a desired wiring pattern is obtained by removal. For example, as described in Japanese Patent Laid-Open No. 9-64493, the semi-additive method is a resist in which a power supply layer is formed by electroless plating, sputtering, CVD, aerosol, or the like, and then opened in a desired pattern. Is formed, electrolytic plating is deposited in the resist opening, and after removing the resist, the power feeding layer is etched to obtain a desired wiring pattern. In the full additive method, as described in, for example, JP-A-6-334334, a resist having a desired pattern is formed after an electroless plating catalyst is adsorbed on the surface of a substrate or resin, and this resist is formed on an insulating layer. In this method, the catalyst is activated as it is, and a desired wiring pattern is obtained by depositing metal in the opening of the insulating layer by electroless plating.
第２構造層１４の第２配線１５及び第２電極１８、並びに第３構造層１９の第３配線２０及び第３電極２３は、それぞれ、半導体基板１２側に密着層を介して第２絶縁層１６及び第３絶縁層２１上に設けてもよい。密着層は、第２絶縁層１６もしくは第３絶縁層２１の材料に対して密着力を有する材料であればよく、例えば、チタン、タングステン、ニッケル、タンタル、バナジウム、クロム、モリブデン、銅、アルミニウム、これらの合金が挙げられ、中でもチタン、タングステン、タンタル、クロム、モリブデン、これらの合金が好適であり、さらにはチタン、タングステン、これらの合金がより好適である。第２絶縁層１６もしくは第３絶縁層２１の表面が細かな凹凸を有する粗化面であってもよく、この場合は、銅やアルミニウムでも良好な密着力が得られやすくなる。さらに密着力を高める手段として、配線材料をスパッタ法により成膜することが望ましい。
The second wiring 15 and the second electrode 18 of the second structure layer 14 and the third wiring 20 and the third electrode 23 of the third structure layer 19 are respectively connected to the semiconductor substrate 12 side via an adhesion layer via the second insulating layer. 16 and the third insulating layer 21 may be provided. The adhesion layer may be any material having adhesion to the material of the second insulating layer 16 or the third insulating layer 21. For example, titanium, tungsten, nickel, tantalum, vanadium, chromium, molybdenum, copper, aluminum, These alloys are mentioned, and among these, titanium, tungsten, tantalum, chromium, molybdenum, and alloys thereof are preferable, and titanium, tungsten, and alloys thereof are more preferable. The surface of the second insulating layer 16 or the third insulating layer 21 may be a roughened surface having fine irregularities, and in this case, good adhesion can be easily obtained even with copper or aluminum. Further, as a means for improving the adhesion, it is desirable to form a wiring material by sputtering.
第２構造層１４の第２配線１５は、第１構造層１３の配線層２８より厚く、すなわち第１配線３１より厚い。第２配線１５の厚さは、例えば３～１２μｍであり、５～１０μｍが望ましい。第２配線が薄すぎると、配線抵抗が高くなり半導体装置の電源回路における電気特性が低下してしまう。第２配線の厚すぎると、配線層を覆う絶縁層の表面に配線層の凹凸を反映した大きなうねりが発生しやすくなり積層数に制限が発生したり、第２構造層１４自体の厚みが増加し半導体装置全体の反りが大きくなったり、プロセス上の制約から製造が困難になったりする。
The second wiring 15 of the second structural layer 14 is thicker than the wiring layer 28 of the first structural layer 13, that is, thicker than the first wiring 31. The thickness of the second wiring 15 is, for example, 3 to 12 μm, and preferably 5 to 10 μm. If the second wiring is too thin, the wiring resistance increases and the electrical characteristics of the power supply circuit of the semiconductor device are degraded. If the thickness of the second wiring is too large, a large undulation reflecting the unevenness of the wiring layer is likely to occur on the surface of the insulating layer covering the wiring layer, the number of laminations is limited, or the thickness of the second structure layer 14 itself increases. However, warpage of the entire semiconductor device becomes large, and manufacturing becomes difficult due to process restrictions.
第３構造層１９の第３配線２０は、第１構造層１３の配線層２８より厚く、すなわち第１配線３１より厚い。第３配線２０の厚さは、例えば３～１２μｍであり、５～１０μｍが望ましい。第３配線が薄すぎると、配線抵抗が高くなり半導体装置の電源回路における電気特性が低下してしまう。第３配線の厚すぎると、配線層を覆う絶縁層の表面に配線層の凹凸を反映した大きなうねりが発生しやすくなり積層数に制限が発生したり、第３構造層１９自体の厚みが増加し半導体装置全体の反りが大きくなったり、プロセス上の制約から製造が困難になったりする。
The third wiring 20 of the third structural layer 19 is thicker than the wiring layer 28 of the first structural layer 13, that is, thicker than the first wiring 31. The thickness of the third wiring 20 is, for example, 3 to 12 μm, and preferably 5 to 10 μm. If the third wiring is too thin, the wiring resistance increases and the electrical characteristics of the power supply circuit of the semiconductor device deteriorate. If the third wiring is too thick, the surface of the insulating layer covering the wiring layer is liable to generate large undulations reflecting the irregularities of the wiring layer, limiting the number of layers, and increasing the thickness of the third structure layer 19 itself. However, warpage of the entire semiconductor device becomes large, and manufacturing becomes difficult due to process restrictions.
第２構造層１４の第２絶縁層１６及び第３構造層１９の第３絶縁層２１は、例えば有機材料で形成される。有機材料としては、例えば、エポキシ樹脂、エポキシアクリレート樹脂、ウレタンアクリレート樹脂、ポリエステル樹脂、フェノール樹脂、ポリイミド樹脂、ＢＣＢ（Ｂｅｎｚｏｃｙｃｌｏｂｕｔｅｎｅ）、ＰＢＯ（Ｐｏｌｙｂｅｎｚｏｘａｚｏｌｅ）、ポリノルボルネン樹脂が挙げられる。特に、ポリイミド樹脂及びＰＢＯは、膜強度、引張弾性率及び破断伸び率等の機械的特性が優れているため、高い信頼性を得ることができる。有機材料は、感光性のもの、非感光性のものいずれを用いても構わない。感光性の有機材料を用いた場合、フォトリソグラフィー法により第２ビア１７や第３ビア２２となる開口部を形成することができる。非感光性の有機材料や感光性であってもパターン解像度が低い有機材料を用いた場合、開口部はレーザ法、ドライエッチング法、ブラスト法などにより形成できる。
The second insulating layer 16 of the second structure layer 14 and the third insulating layer 21 of the third structure layer 19 are made of, for example, an organic material. Examples of the organic material include epoxy resin, epoxy acrylate resin, urethane acrylate resin, polyester resin, phenol resin, polyimide resin, BCB (Benzocyclobutene), PBO (Polybenzoxole), and polynorbornene resin. In particular, since polyimide resin and PBO have excellent mechanical properties such as film strength, tensile elastic modulus, and elongation at break, high reliability can be obtained. As the organic material, either a photosensitive material or a non-photosensitive material may be used. When a photosensitive organic material is used, the opening to be the second via 17 or the third via 22 can be formed by a photolithography method. When a non-photosensitive organic material or a photosensitive organic material having a low pattern resolution is used, the opening can be formed by a laser method, a dry etching method, a blast method, or the like.
第２絶縁層１６及び第３絶縁層２１に有機材料を用いることで、半導体装置を実装基板に搭載した際に、第２電極１８や第３電極２３から半導体装置にかかる応力を、主に第２絶縁層１６及び第３絶縁層２１の変形により緩和させ、第１構造層１３への応力伝搬を効果的に低減させることができる。第２絶縁層１６及び第３絶縁層２１の材料の２５℃における弾性率は、例えば０．１５～８ＧＰａの範囲にあることが望ましい。絶縁材料の弾性率が低すぎると、応力緩和時の第２絶縁層１６及び第３絶縁層２１の変形量が大きく第２配線１５及び第３配線２０に応力の殆どが印加されることとなり、第２配線１５及び第３配線２０の断線や、第２配線１５／第２ビア１７界面および第３配線２０／第３ビア２２界面での破壊が発生し易くなる。絶縁材料の弾性率が高すぎると、第２絶縁層１６及び第３絶縁層２１の変形量が乏しくなり第２構造層１４や第３構造層１９における応力緩和が不十分となり、第１構造層１３において層間剥離や絶縁膜破壊等が生じやすくなる。また、第１構造層１３の層間絶縁膜２９の弾性率より、第２絶縁層１６及び第３絶縁層２１の弾性率が低くなる絶縁材料の組み合わせとすることで、第２絶縁層１６及び第３絶縁層２１で応力をより効果的に緩和でき、第１構造層１３の保護効果を高めることができる。
By using an organic material for the second insulating layer 16 and the third insulating layer 21, when the semiconductor device is mounted on the mounting substrate, the stress applied to the semiconductor device from the second electrode 18 or the third electrode 23 is mainly increased. The stress propagation to the first structure layer 13 can be effectively reduced by relaxing the deformation of the second insulating layer 16 and the third insulating layer 21. The elastic modulus at 25 ° C. of the material of the second insulating layer 16 and the third insulating layer 21 is preferably in the range of 0.15 to 8 GPa, for example. If the elastic modulus of the insulating material is too low, the amount of deformation of the second insulating layer 16 and the third insulating layer 21 during stress relaxation is large, and most of the stress is applied to the second wiring 15 and the third wiring 20. The disconnection of the second wiring 15 and the third wiring 20 and the breakdown at the second wiring 15 / second via 17 interface and the third wiring 20 / third via 22 interface are likely to occur. If the elastic modulus of the insulating material is too high, the deformation amount of the second insulating layer 16 and the third insulating layer 21 is insufficient, and the stress relaxation in the second structural layer 14 and the third structural layer 19 becomes insufficient, and the first structural layer In FIG. 13, delamination, insulation film breakdown, etc. are likely to occur. Further, the second insulating layer 16 and the second insulating layer 16 can be combined with an insulating material in which the elastic modulus of the second insulating layer 16 and the third insulating layer 21 is lower than the elastic modulus of the interlayer insulating film 29 of the first structural layer 13. The stress can be relaxed more effectively by the three insulating layers 21, and the protective effect of the first structure layer 13 can be enhanced.
図２では、第２構造層１４は、第２ビア１７を介して第１構造層１３と電気的に接続され、第３構造層１９は、その第３絶縁層２１が半導体基板１２と接しているが、図４に示すように、第２構造層１４は、第２配線１５介して第１構造層１３と電気的に接続されてもよく、また、第３構造層１９は、その第３配線２０が半導体基板１２上へ設けられていてもよい。第３構造層１９の第３配線２０を半導体基板１２上へ設ける場合、半導体基板１２表面が絶縁性となっていることが望ましい。
In FIG. 2, the second structure layer 14 is electrically connected to the first structure layer 13 through the second via 17, and the third structure layer 19 has the third insulating layer 21 in contact with the semiconductor substrate 12. However, as shown in FIG. 4, the second structure layer 14 may be electrically connected to the first structure layer 13 through the second wiring 15, and the third structure layer 19 has its third structure. The wiring 20 may be provided on the semiconductor substrate 12. When the third wiring 20 of the third structure layer 19 is provided on the semiconductor substrate 12, it is desirable that the surface of the semiconductor substrate 12 is insulative.
第２構造層の第２電極１８は、図５（ａ）から（ｃ）に示した構造としてもよい。
The second electrode 18 of the second structure layer may have the structure shown in FIGS.
図５（ａ）では、ハンダ材料を用いて接続する場合に、第２電極１８のみにハンダが供給されるように、表面側の第２絶縁層１６によって、第２電極１８が露出する開口を制限している。この第２絶縁膜１６による制限により、ハンダの流れ量が制限されるため、半導体装置を実装基板や別部品と接続する際の取り付け高さを安定化させることができる。また、図５（ａ）には、第２電極１８の周囲を第２絶縁層１６が覆う構造が示されているが、第２絶縁層１６に覆われない構造としてもよい。図５（ｂ）に示される構造では、ワイヤーボンディングを用いて接続する場合に、電極部への接続を良好とすることができる。図５（ｃ）に示される構造では、電極の下方部が、表面側の第２絶縁層１６の開口内に設けられ、この構造によればハンダ材料による接続を狭ピッチで行う場合に、接続信頼性を向上させることができる。
In FIG. 5A, when the connection is made using a solder material, an opening through which the second electrode 18 is exposed is formed by the second insulating layer 16 on the surface side so that the solder is supplied only to the second electrode 18. Restricted. The restriction by the second insulating film 16 restricts the amount of solder flow, so that the mounting height when the semiconductor device is connected to the mounting substrate or another component can be stabilized. 5A shows a structure in which the second insulating layer 16 covers the periphery of the second electrode 18, but a structure that is not covered by the second insulating layer 16 may be used. In the structure shown in FIG. 5B, when connecting using wire bonding, the connection to the electrode portion can be made favorable. In the structure shown in FIG. 5C, the lower part of the electrode is provided in the opening of the second insulating layer 16 on the surface side, and according to this structure, when the connection by the solder material is performed at a narrow pitch, the connection Reliability can be improved.
第２電極１８は、例えば積層体からなり、第２電極１８の表面に形成されるハンダボールの濡れ性やボンディングワイヤーとの接続性を考慮して、第２電極１８の表面に、例えば、銅、アルミニウム、金、銀及びハンダ材料からなる群から選択された少なくとも一種の金属または合金からなる層が設けられる。第２電極１８は、例えば銅層上にニッケル層と金層が積層され、金層を表面としたものであり、ニッケル層の厚さは例えば３μｍ、金層の厚さは例えば１μｍである。
The second electrode 18 is made of, for example, a laminate, and in consideration of wettability of solder balls formed on the surface of the second electrode 18 and connectivity with bonding wires, the surface of the second electrode 18 is made of, for example, copper. And a layer of at least one metal or alloy selected from the group consisting of aluminum, gold, silver and solder materials. The second electrode 18 is, for example, a nickel layer and a gold layer laminated on a copper layer and having the gold layer as a surface. The nickel layer has a thickness of 3 μm, for example, and the gold layer has a thickness of 1 μm, for example.
第３構造層１９の第３電極２３は、第２構造層１４の第２電極１８と同様な構造をとることができる。第２電極１８と第３電極２３は、接続に対して所望の効果のある構造を適宜選択すればよく、同じ構造とする必要はない。
The third electrode 23 of the third structure layer 19 can have the same structure as the second electrode 18 of the second structure layer 14. The second electrode 18 and the third electrode 23 may be appropriately selected from structures having a desired effect on the connection, and need not have the same structure.
図２では、３層の第２配線１５及び４層の第２絶縁層１６が示されているが、これに限定されるものではなく、必要に応じて層数を設定できる。図３では、８層の配線層２８及び８層の層間絶縁膜（第１絶縁層）２９が示されているが、これに限定されるものではなく、必要に応じて層数を設定できる。
In FIG. 2, three layers of the second wiring 15 and four layers of the second insulating layer 16 are shown, but the present invention is not limited to this, and the number of layers can be set as necessary. In FIG. 3, the eight wiring layers 28 and the eight interlayer insulating films (first insulating layers) 29 are shown, but the present invention is not limited to this, and the number of layers can be set as necessary.
第１配線３１、第２配線１５、及び第３配線２０は、例えば銅、アルミニウム、ニッケル、金及び銀からなる群から選択された少なくとも一種の金属または合金から構成される。特に、電気抵抗値及びコストの観点から銅が好適である。ニッケルは、絶縁材料等の他の材料との界面反応を防止でき、バリア膜として使用でき、また磁性体としての特性を持ち、インダクタ又は抵抗配線として使用できる。
The first wiring 31, the second wiring 15, and the third wiring 20 are made of at least one kind of metal or alloy selected from the group consisting of copper, aluminum, nickel, gold and silver, for example. In particular, copper is preferable from the viewpoint of electrical resistance value and cost. Nickel can prevent an interfacial reaction with other materials such as an insulating material, can be used as a barrier film, has characteristics as a magnetic material, and can be used as an inductor or a resistance wiring.
第２構造層１４の第２配線１５は、その厚みが第１構造層１３の第１配線３１より厚いため、第１配線３１より大きい許容電流量を有している。また、第３構造層１９の第３配線２０は、その厚みが第１構造層１３の第１配線３１より厚いため、第１配線３１より大きい許容電流量を有している。このため、第２構造層１４及び第３構造層１９のいずれか一方もしくは両方において、複数の同じ電圧を用いている電源系配線やグランド系配線を束ねて配線本数を少なくすることができる。これらの複数配線をまとめることで、まとめなかった場合に比べ、第２電極１８や第３電極２３の数を低減させることができる。この第２電極１８や第３電極２３の数を低減することで、第２電極１８や第３電極２３のサイズや間隔（ピッチ）を大きくできるため、実装基板と半導体装置の接続面積が大きくなり、安定した実装性と高い接続信頼性を実現できる。
The second wiring 15 of the second structural layer 14 has a larger allowable current amount than the first wiring 31 because the thickness thereof is thicker than the first wiring 31 of the first structural layer 13. Further, the third wiring 20 of the third structure layer 19 has a larger allowable current amount than the first wiring 31 because the thickness thereof is thicker than that of the first wiring 31 of the first structure layer 13. For this reason, in one or both of the second structure layer 14 and the third structure layer 19, a plurality of power supply system wirings and ground system wirings using the same voltage can be bundled to reduce the number of wirings. By combining these plural wirings, the number of the second electrodes 18 and the third electrodes 23 can be reduced as compared with the case where they are not combined. By reducing the number of the second electrodes 18 and the third electrodes 23, the size and interval (pitch) of the second electrodes 18 and the third electrodes 23 can be increased, so that the connection area between the mounting substrate and the semiconductor device increases. Stable mounting and high connection reliability can be realized.
上述の通り、本実施形態の半導体装置においては、半導体基板１２の両側表面に第２構造層１４と第３構造層１９を設けているため、半導体基板１２とその上に積層された層との熱膨張差により発生する応力を相殺することができ、半導体基板１２を薄くしても反り量を抑えることができる。特に、第２構造層１４と第３構造層１９との間において、配線層と絶縁層の両方もしくは片方が同数であることにより、反り量低減効果をより高めることができる。
As described above, in the semiconductor device of this embodiment, since the second structure layer 14 and the third structure layer 19 are provided on both side surfaces of the semiconductor substrate 12, the semiconductor substrate 12 and the layers stacked thereon are provided. The stress generated by the difference in thermal expansion can be offset, and the amount of warpage can be suppressed even if the semiconductor substrate 12 is thinned. In particular, between the second structure layer 14 and the third structure layer 19, both or one of the wiring layers and the insulating layers has the same number, so that the effect of reducing the warpage can be further enhanced.
また、半導体基板両面に設けた第２構造層１４及び第３構造層１９により、半導体装置の配線収容率を高めることができ、さらに、基板両面側に他の半導体装置やチップ部品などの電子部品を高密度で搭載することが可能になる。
Further, the second structural layer 14 and the third structural layer 19 provided on both sides of the semiconductor substrate can increase the wiring accommodation rate of the semiconductor device, and further, electronic components such as other semiconductor devices and chip components on the both sides of the substrate. Can be mounted at high density.
また、第２構造層１４と第３構造層１９に含まれる各有機絶縁層の作用により、半導体装置が受ける衝撃を和らげ、欠けやクラックを防止することができ、耐衝撃性を向上させることができる。
Further, the action of each organic insulating layer included in the second structure layer 14 and the third structure layer 19 can soften the impact received by the semiconductor device, prevent chipping and cracks, and improve impact resistance. it can.
第２構造層１４の第２配線１５及び第３構造層１９の第３配線２０の厚さを第１構造層１３の配線３１の厚さより大きくすることで、第２配線１５や第３配線２０の破断を防止できるとともに、第２配線１５や第３配線２０の配線抵抗を第１配線３１より小さくすることができる。また、第２配線１５及び第３配線２０の厚さが大きくなるに従って、第２絶縁層１６や第３絶縁層２１の１層当たりの厚さも大きくなるため、応力を緩和する効果が高まる。
By making the thickness of the second wiring 15 of the second structural layer 14 and the third wiring 20 of the third structural layer 19 larger than the thickness of the wiring 31 of the first structural layer 13, the second wiring 15 and the third wiring 20. Can be prevented, and the wiring resistance of the second wiring 15 and the third wiring 20 can be made smaller than that of the first wiring 31. Further, as the thicknesses of the second wiring 15 and the third wiring 20 are increased, the thickness of each layer of the second insulating layer 16 and the third insulating layer 21 is also increased, so that the effect of relaxing the stress is enhanced.
さらに、第２配線１５及び第３配線２０が厚いと、それぞれ、第２構造層１４や第３構造層１９において、複数の同じ電圧を用いている電源系やグランド系の配線を一つの配線にまとめることができる。半導体素子表面に再配線を施しているウエハレベルＣＳＰにおいては、半導体部品に設けられた際の配線は、接続端子数を低減することなく、単純に１対１の関係のままで配置のみを変更している。外部端子数が約５００以上、特に１５００以上の半導体部品では、素子の性能維持のために端子数の約６０～８０％が電源系とグランド系の端子となる。この電源系配線やグランド系配線の集約により、第１構造層１３表面に形成される電気的接続点の数に比べて、第２構造層１４の第２電極１８の数を大幅に低減することができる。さらには、第３構造層１９でも第３電極２３の数を低減することができる。このため、第２電極１８や第３電極２３のサイズや間隔（ピッチ）を大きくできるため、半導体装置の安定した実装性と高い接続信頼性を実現できる。
Further, when the second wiring 15 and the third wiring 20 are thick, in the second structure layer 14 and the third structure layer 19, respectively, a plurality of power supply systems and ground wirings using the same voltage are combined into one wiring. Can be summarized. In the wafer level CSP in which rewiring is performed on the surface of the semiconductor element, the wiring when provided in the semiconductor component is simply changed in the one-to-one relationship without reducing the number of connection terminals. is doing. In the case of a semiconductor component having about 500 or more external terminals, particularly 1500 or more, about 60 to 80% of the number of terminals serves as a power supply system and a ground system in order to maintain device performance. By consolidating the power supply line and the ground line, the number of the second electrodes 18 of the second structure layer 14 can be greatly reduced as compared with the number of electrical connection points formed on the surface of the first structure layer 13. Can do. Furthermore, the number of the third electrodes 23 can be reduced also in the third structure layer 19. For this reason, since the size and interval (pitch) of the second electrode 18 and the third electrode 23 can be increased, stable mounting property and high connection reliability of the semiconductor device can be realized.
以上の通り、第２構造層１４及び第３構造層１９により、薄型で反りが抑えられ、また第１構造層１３への応力や衝撃の伝播が緩和された、実装時の接続信頼性の高い、高密度な半導体装置を実現できる。
As described above, the second structure layer 14 and the third structure layer 19 are thin and less warped, and the propagation of stress and impact to the first structure layer 13 is reduced, so that the connection reliability at the time of mounting is high. A high-density semiconductor device can be realized.
第２の実施形態
次に、本発明の第２の実施形態について説明する。 Second Embodiment Next, a second embodiment of the present invention will be described.
次に、本発明の第２の実施形態について説明する。 Second Embodiment Next, a second embodiment of the present invention will be described.
図６は本発明の第２の実施形態による半導体装置の一例を示す部分断面図である。第１の実施形態による半導体装置とは、半導体基板１２を貫通するように貫通ビア３４が設けられている点が異なっている。以下に、第１の実施形態による半導体装置と異なる部分について説明する。特に記載のない部分については、第１の実施形態による半導体装置と同じである。図６における第２電極１８と第３電極２３は、図５（ｂ）や（ｃ）に示す構造としてもよい。
FIG. 6 is a partial sectional view showing an example of a semiconductor device according to the second embodiment of the present invention. The semiconductor device according to the first embodiment is different in that a through via 34 is provided so as to penetrate the semiconductor substrate 12. Hereinafter, parts different from the semiconductor device according to the first embodiment will be described. Portions not specifically described are the same as those of the semiconductor device according to the first embodiment. The second electrode 18 and the third electrode 23 in FIG. 6 may have the structure shown in FIGS.
貫通ビア３４は、半導体基板１２の一方の面に設けられている第１構造層１３及び第２構造層１４、並びに他方の面に設けられている第３構造層１９を、必要な機能に応じて電気的に接続する。すなわち、貫通ビア３４を介して、第１構造層１３及び第２構造層１５のいずれかもしくは両方が第３構造層１９と電気的に接続される。
The through via 34 allows the first structure layer 13 and the second structure layer 14 provided on one surface of the semiconductor substrate 12 and the third structure layer 19 provided on the other surface to be provided according to a required function. Connect them electrically. That is, one or both of the first structure layer 13 and the second structure layer 15 are electrically connected to the third structure layer 19 through the through via 34.
貫通ビア３４は、次のようにして形成することができる。まず、ドライエッチングやウェットエッチングにより半導体基板１２に貫通孔を形成する。次いで、この貫通孔の内壁に無機や有機の絶縁膜を熱酸化、ＣＶＤ、ＡＬＤ、スピンコート法、ラミネート法、又は印刷法などにより形成する。必要に応じて、フォトリソグラフィー法や、レーザ法、ドライエッチング、ウェットエッチングにより絶縁膜を加工してもよい。次に、貫通孔内部に、ＣＶＤ、スパッタ法、電解めっき法、無電解めっき法、印刷法、蒸着法、インクジェット法等により導体を形成することで貫通ビア３４が形成される。貫通ビア３４の材料としては、銅、アルミニウム、タングステン、金、銀、ニッケル、及び不純物含有ポリシリコンからなる群から選ばれる少なくとも一種の導電性材料もしくはいずれかの金属を含む合金を用いることができる。コストや電気特性の面から、銅もしくは銅合金が好ましい。
The through via 34 can be formed as follows. First, a through hole is formed in the semiconductor substrate 12 by dry etching or wet etching. Next, an inorganic or organic insulating film is formed on the inner wall of the through hole by thermal oxidation, CVD, ALD, spin coating, laminating, or printing. If necessary, the insulating film may be processed by photolithography, laser, dry etching, or wet etching. Next, a through via 34 is formed in the through hole by forming a conductor by CVD, sputtering, electrolytic plating, electroless plating, printing, vapor deposition, ink jet, or the like. As the material of the through via 34, at least one conductive material selected from the group consisting of copper, aluminum, tungsten, gold, silver, nickel, and impurity-containing polysilicon, or an alloy containing any metal can be used. . From the viewpoint of cost and electrical characteristics, copper or a copper alloy is preferable.
図７は、第２実施形態による半導体装置の他の例を示す部分断面図である。図７では、貫通ビア３４のピッチが第２電極１８や第３電極２３のピッチより小さくなっている。また、第２配線１５と第３配線２０で複数の貫通ビア３４が束ねられている。これは、第２配線と第３配線が十分に厚く、配線抵抗が小さいため、このような配線構造が可能となる。
FIG. 7 is a partial cross-sectional view showing another example of the semiconductor device according to the second embodiment. In FIG. 7, the pitch of the through vias 34 is smaller than the pitch of the second electrode 18 and the third electrode 23. A plurality of through vias 34 are bundled by the second wiring 15 and the third wiring 20. This is because the second wiring and the third wiring are sufficiently thick and the wiring resistance is small, and thus such a wiring structure is possible.
第２の実施形態による半導体装置では、第１の実施形態による半導体装置の効果に加えて、基板の両面側に設けられている配線構造層が貫通ビアを介して電気的に接続されることにより、さらに配線設計の自由度が向上し、第１の実施形態による半導体装置より高密度化を実現することができる。また、基板の一方の面側と他方の面側に設けられた電子部品同士を短い距離で接続できるため、半導体装置の性能を向上させることができる。
In the semiconductor device according to the second embodiment, in addition to the effects of the semiconductor device according to the first embodiment, the wiring structure layers provided on both surfaces of the substrate are electrically connected through the through vias. Furthermore, the degree of freedom in wiring design is further improved, and a higher density than that of the semiconductor device according to the first embodiment can be realized. In addition, since the electronic components provided on one surface side and the other surface side of the substrate can be connected with a short distance, the performance of the semiconductor device can be improved.
第３の実施形態
次に本発明の第３の実施形態について説明する。 Third Embodiment Next, a third embodiment of the present invention will be described.
次に本発明の第３の実施形態について説明する。 Third Embodiment Next, a third embodiment of the present invention will be described.
図８～１０は本発明の第３の実施形態による半導体装置の具体例を示す部分断面図である。第３の実施形態では、第１の実施形態による半導体装置と第２の実施形態による半導体装置が積層されている。図８及び図９では、第２実施形態による半導体装置の上に第１の実施形態による半導体装置が積層され、図１０では、第２の実施形態による二つの半導体装置が積層されている。半導体装置の積層形態は、これらに限定されることはない。また、図８～１０の第２電極１８と第３電極２３は、図５（ｂ）や（ｃ）に示される構造としてもよい。以下に第３の実施形態による半導体装置について説明する。特に記載のない部分については、第１の実施形態もしくは第２の実施形態による半導体装置と同じである。
8 to 10 are partial sectional views showing specific examples of the semiconductor device according to the third embodiment of the present invention. In the third embodiment, the semiconductor device according to the first embodiment and the semiconductor device according to the second embodiment are stacked. 8 and 9, the semiconductor device according to the first embodiment is stacked on the semiconductor device according to the second embodiment. In FIG. 10, two semiconductor devices according to the second embodiment are stacked. The stacked form of the semiconductor device is not limited to these. Further, the second electrode 18 and the third electrode 23 in FIGS. 8 to 10 may have a structure shown in FIGS. 5B and 5C. The semiconductor device according to the third embodiment will be described below. Portions that are not particularly described are the same as those of the semiconductor device according to the first embodiment or the second embodiment.
図８に示す構造は、図６で示した半導体装置上に図２で示した半導体装置が積層されている。二つの半導体装置の間に設けられた接続部３５によって、図６で示した半導体装置の第２電極１８と図２で示した半導体装置の第３電極２３とが接続されている。下面側の第３電極２３上に半田ボール３６が設けられている。接続部３５は、ハンダ材料、錫、金、銀、パラジウム、銅、アルミニウムからなる群から選択される少なくとも一種の材料により形成できる。接続部３５における信頼性をより向上させるために、半導体装置間にアンダーフィル樹脂を注入して強度を高めてもよい。
In the structure shown in FIG. 8, the semiconductor device shown in FIG. 2 is stacked on the semiconductor device shown in FIG. The second electrode 18 of the semiconductor device shown in FIG. 6 and the third electrode 23 of the semiconductor device shown in FIG. 2 are connected by a connection portion 35 provided between the two semiconductor devices. A solder ball 36 is provided on the third electrode 23 on the lower surface side. The connecting portion 35 can be formed of at least one material selected from the group consisting of solder material, tin, gold, silver, palladium, copper, and aluminum. In order to further improve the reliability of the connecting portion 35, an underfill resin may be injected between the semiconductor devices to increase the strength.
図９に示す構造は、図８で示した構造と比較すると、図６で示した半導体装置の第２電極１８と図２で示した半導体装置の第２電極１８とが接続されている点が異なっている。つまり、二つの半導体装置の第１構造層が向かい合うように積層されている。対向している半導体装置間での高速且つ広いバンド幅を確保したデータ通信が可能となり、高性能化が実現できる。
9 is different from the structure shown in FIG. 8 in that the second electrode 18 of the semiconductor device shown in FIG. 6 is connected to the second electrode 18 of the semiconductor device shown in FIG. Is different. In other words, the first structure layers of the two semiconductor devices are stacked so as to face each other. High-speed and high-speed data communication between semiconductor devices facing each other is possible, and high performance can be realized.
図１０に示す構造は、二つの図６で示した半導体装置が積層され、その上面側に電子部品３７が設けられ、下面側に半田ボール３６が設けられている。電子部品は、上面側の第２電極１８に接続部３８を介して電気的に接続されている。半田ボール３６は、下面側の第３電極２３に直接接続している。電子部品３７としては、他の半導体装置、チップコンデンサ、チップ抵抗、ディスクリート、ダイオード、ＬＥＤ、センサ、ＭＥＭＳ、光学部品などが挙げられる。接続部３８は、ハンダ材料、錫、金、銀、パラジウム、銅、アルミニウムからなる群から選択される少なくとも一種の材料により形成できる。他の電子部品が設けられることで、回路動作が安定化し、システムとしての機能向上を実現することができる。
In the structure shown in FIG. 10, two semiconductor devices shown in FIG. 6 are stacked, an electronic component 37 is provided on the upper surface side, and a solder ball 36 is provided on the lower surface side. The electronic component is electrically connected to the second electrode 18 on the upper surface side via the connection portion 38. The solder ball 36 is directly connected to the third electrode 23 on the lower surface side. Examples of the electronic component 37 include other semiconductor devices, chip capacitors, chip resistors, discretes, diodes, LEDs, sensors, MEMS, and optical components. The connecting portion 38 can be formed of at least one material selected from the group consisting of solder material, tin, gold, silver, palladium, copper, and aluminum. By providing other electronic components, the circuit operation can be stabilized and the function of the system can be improved.
図８～１０では、二つの半導体装置が積層された構造を示したが、これに限定されることはなく、三つ以上の半導体装置を積層してもよい。また、積層の最下層となる部分においては、ハンダボール３６を有する構造を示したが、これに限定されず、ピン、Ａｕバンプ、銅バンプ、予備ハンダ、金属パール、ＡＣＦ、ＮＣＦなどを用いた接続方法による構造であってもよい。
8 to 10 show a structure in which two semiconductor devices are stacked, the present invention is not limited to this, and three or more semiconductor devices may be stacked. Further, the structure having the solder ball 36 is shown in the lowermost layer of the stack, but the present invention is not limited to this, and pins, Au bumps, copper bumps, spare solder, metal pearls, ACF, NCF, etc. are used. A structure based on a connection method may be used.
第３の実施形態による半導体装置では、第１の実施形態による半導体装置と第２の実施形態による半導体装置の効果に加えて、複数の半導体装置や電子部品を積層することで、フットプリントの拡大を最小限としてシステムを高密度に構成することが実現できる。
In the semiconductor device according to the third embodiment, in addition to the effects of the semiconductor device according to the first embodiment and the semiconductor device according to the second embodiment, the footprint is increased by stacking a plurality of semiconductor devices and electronic components. It is possible to realize a high-density system with a minimum of.
前述の第１～第３の実施形態において、半導体基板１２、第１構造層１３、第２構造層１４、第３構造層１９で構成される積層回路の所望の位置に、回路のノイズフィルターやデカップリングの役割を果たすコンデンサが設けられていてもよい。コンデンサを構成する誘電体材料としては、酸化チタン、酸化タンタル、Ａｌ２Ｏ３、ＳｉＯ２、ＺｒＯ２、ＨｆＯ２、Ｎｂ２Ｏ５等の金属酸化物；ＢＳＴ（ＢａｘＳｒ１－ｘＴｉＯ３）、ＰＺＴ（ＰｂＺｒｘＴｉ１－ｘＯ３）、ＰＬＺＴ（Ｐｂ１－ｙＬａｙＺｒｘＴｉ１－ｘＯ３）等のペロブスカイト系材料（０≦ｘ≦１、０＜ｙ＜１）；ＳｒＢｉ２Ｔａ２Ｏ９等のＢｉ系層状化合物が挙げられる。また、コンデンサを構成する誘電体材料として、無機材料や磁性材料を混合した有機材料等を使用してもよい。
In the first to third embodiments described above, a circuit noise filter or the like is provided at a desired position of the laminated circuit including the semiconductor substrate 12, the first structural layer 13, the second structural layer 14, and the third structural layer 19. A capacitor that plays the role of decoupling may be provided. Examples of the dielectric material constituting the capacitor include metal oxides such as titanium oxide, tantalum oxide, Al 2 O 3 , SiO 2 , ZrO 2 , HfO 2 , and Nb 2 O 5 ; BST (Ba x Sr 1-x TiO 3 ), PZT (PbZr x Ti 1 -x O 3), PLZT (Pb 1-y La y Zr x Ti 1-x O 3) perovskite such material (0 ≦ x ≦ 1,0 <y <1); Bi-based layered compounds such as SrBi 2 Ta 2 O 9 are listed. Further, as a dielectric material constituting the capacitor, an organic material mixed with an inorganic material or a magnetic material may be used.
また、第２構造層１４及び第３構造層１９における絶縁層のうちの一層もしくは複数層の上側および下側の配線層の所望の位置に、誘電率が９以上の誘電体を介して対向電極を形成することで回路のノイズフィルターやデカップリングの役割を果たすコンデンサを設けてもよい。コンデンサを構成する誘電体材料としては、Ａｌ２Ｏ３、ＺｒＯ２、ＨｆＯ２、Ｎｂ２Ｏ５等の金属酸化物；ＢＳＴ（ＢａｘＳｒ１－ｘＴｉＯ３）、ＰＺＴ（ＰｂＺｒｘＴｉ１－ｘＯ３）、ＰＬＺＴ（Ｐｂ１－ｙＬａｙＺｒｘＴｉ１－ｘＯ３）等のペロブスカイト系材料（０≦ｘ≦１、０＜ｙ＜１）；ＳｒＢｉ２Ｔａ２Ｏ９等のＢｉ系層状化合物が挙げられる。また、コンデンサを構成する誘電体材料として、無機材料や磁性材料を混合した有機材料等を使用してもよい。
In addition, the counter electrode is disposed at a desired position of one or more of the insulating layers in the second structural layer 14 and the third structural layer 19 on the upper and lower wiring layers via a dielectric having a dielectric constant of 9 or more. A capacitor that plays the role of a circuit noise filter or decoupling may be provided by forming. The dielectric material constituting the capacitor, Al 2 O 3, ZrO 2 , HfO 2, Nb metal oxides such as 2 O 5; BST (Ba x Sr 1-x TiO 3), PZT (PbZr x Ti 1- x O 3 ), perovskite materials such as PLZT (Pb 1-y La y Zr x Ti 1-x O 3 ) (0 ≦ x ≦ 1, 0 <y <1); Bi such as SrBi 2 Ta 2 O 9 System layered compounds are mentioned. Further, as a dielectric material constituting the capacitor, an organic material mixed with an inorganic material or a magnetic material may be used.
半導体装置の製造方法
以下、本発明の実施形態による半導体装置の製造例について図面を参照して具体的に説明する。 Semiconductor Device Manufacturing Method Hereinafter, a semiconductor device manufacturing example according to an embodiment of the present invention will be specifically described with reference to the drawings.
以下、本発明の実施形態による半導体装置の製造例について図面を参照して具体的に説明する。 Semiconductor Device Manufacturing Method Hereinafter, a semiconductor device manufacturing example according to an embodiment of the present invention will be specifically described with reference to the drawings.
第１の製造例
先ず、図１１を用いて第１の製造例について説明する。図１１は、本製造例を説明するための部分断面図である。 First Manufacturing Example First, a first manufacturing example will be described with reference to FIG. FIG. 11 is a partial cross-sectional view for explaining the present manufacturing example.
先ず、図１１を用いて第１の製造例について説明する。図１１は、本製造例を説明するための部分断面図である。 First Manufacturing Example First, a first manufacturing example will be described with reference to FIG. FIG. 11 is a partial cross-sectional view for explaining the present manufacturing example.
以下に説明する各工程においては適宜、洗浄や熱処理を行ってもよい。また、半導体基板１２は必要に応じて３００μｍ未満の厚みに研削してもよい。薄い半導体基板１２を用いる場合、ハンドリング性を向上させるために、半導体基板１２と同じ材料や金属で形成されたサポート部材を用いてもよい。
In each step described below, cleaning or heat treatment may be performed as appropriate. Further, the semiconductor substrate 12 may be ground to a thickness of less than 300 μm as necessary. When the thin semiconductor substrate 12 is used, a support member made of the same material or metal as that of the semiconductor substrate 12 may be used in order to improve handling properties.
まず、図１１（ａ）に示すように、前述の第１の実施形態において説明したとおり、半導体基板１２上に素子および第１構造層１３を形成する。第１構造層１３における第１配線３１は前述の通りダマシン法により形成でき、絶縁層２８、２９は例えばＣＶＤ法やスピンコート法により形成できる。
First, as shown in FIG. 11A, as described in the first embodiment, an element and a first structure layer 13 are formed on a semiconductor substrate 12. As described above, the first wiring 31 in the first structure layer 13 can be formed by the damascene method, and the insulating layers 28 and 29 can be formed by, for example, a CVD method or a spin coating method.
次に、図１１（ｂ）に示すように、前述の第１の実施形態において説明したとおり、第２構造層１４を第１構造層１３に直接接するように形成する。
Next, as shown in FIG. 11B, the second structure layer 14 is formed so as to be in direct contact with the first structure layer 13 as described in the first embodiment.
第２構造層１４の第２配線１５は、前述の通りに形成でき、例えば銅からなり、その厚さは例えば５μｍである。微細な配線を形成する場合は、セミアディティブ法が好ましい。
The second wiring 15 of the second structure layer 14 can be formed as described above, and is made of, for example, copper and has a thickness of, for example, 5 μm. When forming fine wiring, the semi-additive method is preferable.
第２構造層１４の第２絶縁層１６は、絶縁材料として無機材料を用いる場合は、ＣＶＤ法やスピンコート法により形成できる。第２ビア１７となる開口部はドライエッチングにより形成できる。絶縁材料として有機材料を用いる場合は、感光性、非感光性のいずれを用いてもよく、スピンコート法、ラミネート法、プレス法、又は印刷法により第２絶縁層を形成できる。第２ビア１７となる開口部は、前述の通り、感光性樹脂を用いた場合はフォトリソグラフィー法により形成でき、非感光性の有機材料や感光性であってもパターン解像度が低い有機材料を用いた場合は、レーザ法、ドライエッチング法、ブラスト法などにより形成できる。このようにして形成された開口部に導電材を充填することにより、第２ビア１７を形成することができる。また、第２ビア１７となる部分に金属ポストをめっき法や印刷法により形成しておき、第２絶縁層１６を形成した後に、ドライエッチング法、ＣＭＰ法、研削法、ラップ法などにより第２絶縁層１６の金属ポスト上の部分を除去し、その金属ポストを露出させることで第２ビア１７を形成することもできる。
The second insulating layer 16 of the second structure layer 14 can be formed by a CVD method or a spin coating method when an inorganic material is used as an insulating material. The opening serving as the second via 17 can be formed by dry etching. When an organic material is used as the insulating material, either photosensitive or non-photosensitive can be used, and the second insulating layer can be formed by a spin coating method, a laminating method, a pressing method, or a printing method. As described above, the opening serving as the second via 17 can be formed by a photolithography method when a photosensitive resin is used, and a non-photosensitive organic material or an organic material having a low pattern resolution even when photosensitive is used. In such a case, it can be formed by a laser method, a dry etching method, a blast method, or the like. The second via 17 can be formed by filling the opening formed in this way with a conductive material. In addition, a metal post is formed in a portion to be the second via 17 by a plating method or a printing method, and after the second insulating layer 16 is formed, a second etching method, a CMP method, a grinding method, a lapping method, or the like is performed. The second via 17 can also be formed by removing a portion of the insulating layer 16 on the metal post and exposing the metal post.
図１１に示す構造においては、第２ビア１７の開口部を垂直な壁で示しているが、テーパ角を付けても構わない。第１構造層の配線に接続する第２ビア１７にテーパ角を設けることにより、第２ビア１７と第１構造層１３の配線との接続面積を小さくすることができるため、第１構造層１３表面の配線密度を高めることができる。また、第２ビア１７と第２配線１５との接合面積を大きくできるため、接続信頼性を向上することができる。さらに、第２ビア１７がテーパ角を有することで配線形成が容易となる。
In the structure shown in FIG. 11, the opening of the second via 17 is indicated by a vertical wall, but a taper angle may be provided. By providing a taper angle to the second via 17 connected to the wiring of the first structural layer, the connection area between the second via 17 and the wiring of the first structural layer 13 can be reduced. The surface wiring density can be increased. In addition, since the junction area between the second via 17 and the second wiring 15 can be increased, connection reliability can be improved. Furthermore, since the second via 17 has a taper angle, wiring formation is facilitated.
次に、図１１（ｃ）に示すように、前述の第１の実施形態において説明したとおり、第３構造層１９を、半導体基板１２の第１構造層１３が形成された面の反対面に直接形成する。
Next, as shown in FIG. 11C, as described in the first embodiment, the third structure layer 19 is placed on the opposite surface of the surface of the semiconductor substrate 12 on which the first structure layer 13 is formed. Form directly.
第３構造層１９の第３配線２０、第３絶縁層２１及び第３ビア２２は、前述の第２構造層の第２配線１５、第２絶縁層１６及び第２ビア１７と同様にして形成することができる。必要に応じて、前述の密着層や粗化面を形成する。
The third wiring 20, the third insulating layer 21, and the third via 22 of the third structural layer 19 are formed in the same manner as the second wiring 15, the second insulating layer 16, and the second via 17 of the second structural layer described above. can do. If necessary, the aforementioned adhesion layer or roughened surface is formed.
図１１を用いて説明した製造方法は、図２に示す構造の製造方法の一例として説明したが、同様な方法を用いて、図４に示す構造を作製することができる。第２電極１８及び第３電極２３は、採用する接続方法に応じて図５（ｂ）又は（ｃ）に示した構造となるように作製してもよい。
Although the manufacturing method described with reference to FIG. 11 has been described as an example of the manufacturing method of the structure shown in FIG. 2, the structure shown in FIG. 4 can be manufactured using a similar method. The second electrode 18 and the third electrode 23 may be manufactured to have the structure shown in FIG. 5B or 5C depending on the connection method employed.
第１の製造例によれば、第１実施形態による半導体装置を効率よく形成することができる。また、図１２（ａ）に示すように、ウエハ３９上に複数の半導体装置１１を形成し、図１２（ａ）の実線や図１２（ｂ）の破線に沿って、ブレードダイシング、レーザダイシング、ウォータカッター、ドライエッチング、ウェットエッチングなどにより切断し、各半導体装置１１へ個片化してもよい。
According to the first manufacturing example, the semiconductor device according to the first embodiment can be efficiently formed. Also, as shown in FIG. 12A, a plurality of semiconductor devices 11 are formed on the wafer 39, and along the solid line in FIG. 12A and the broken line in FIG. 12B, blade dicing, laser dicing, The semiconductor device 11 may be cut into pieces by cutting with a water cutter, dry etching, wet etching, or the like.
第２の製造例
図１３を用いて第２の製造例について説明する。図１３は、本製造例を説明するための部分断面図である。 Second Manufacturing Example A second manufacturing example will be described with reference to FIG. FIG. 13 is a partial cross-sectional view for explaining the present manufacturing example.
図１３を用いて第２の製造例について説明する。図１３は、本製造例を説明するための部分断面図である。 Second Manufacturing Example A second manufacturing example will be described with reference to FIG. FIG. 13 is a partial cross-sectional view for explaining the present manufacturing example.
第２の製造例は、第１の製造例と比較して、第２構造層１４と第３構造層１９とが同時進行的に積層されて形成されている点が異なっている。以下に、第１の製造例と異なる点について説明する。特に記載のない部分については、第１の製造例と同じである。
The second manufacturing example is different from the first manufacturing example in that the second structural layer 14 and the third structural layer 19 are formed by being laminated simultaneously. Hereinafter, differences from the first manufacturing example will be described. Parts not particularly described are the same as those in the first production example.
図１３（ａ）に示すように半導体基板１２上に素子および第１構造層１３を形成した後、図１３（ｂ）に示すように、第２構造層１４の基板側部分（配線１５、絶縁層１６及びビア１７）を第１構造層１３に直接接するように形成するとともに、第３構造層１９の基板側部分（配線２０および絶縁層２１）を第１構造層１３が形成された基板面の反対面に直接形成する。続いて、第２構造層の上層側部分および第３構造層の上層側部分を形成して、図１３（ｃ）に示す所望の構造を形成する。その際、第２絶縁層の形成と第３絶縁層の形成を同じプロセスで同時に行い、第２配線の形成と第３配線の形成を同じプロセスで同時に行う。絶縁層の形成は、両面に絶縁シートを貼り付けて熱処理することで両面に絶縁層を形成できる。配線の形成は、無電解メッキを両面に形成した後、両面にレジストパターンを形成し、両面同時に電解メッキを行い、両面同時にエッチングを行うことで、両面に配線を形成できる。
After the elements and the first structural layer 13 are formed on the semiconductor substrate 12 as shown in FIG. 13A, the substrate side portion (wiring 15 and insulation) of the second structural layer 14 as shown in FIG. 13B. The layer 16 and the via 17) are formed so as to be in direct contact with the first structural layer 13, and the substrate side portion (the wiring 20 and the insulating layer 21) of the third structural layer 19 is the substrate surface on which the first structural layer 13 is formed. Directly formed on the opposite surface. Subsequently, an upper layer side portion of the second structure layer and an upper layer side portion of the third structure layer are formed to form a desired structure shown in FIG. At that time, the formation of the second insulating layer and the formation of the third insulating layer are simultaneously performed in the same process, and the formation of the second wiring and the formation of the third wiring are simultaneously performed in the same process. The insulating layer can be formed on both sides by attaching an insulating sheet on both sides and performing heat treatment. Wiring can be formed by forming electroless plating on both sides, forming a resist pattern on both sides, performing electrolytic plating on both sides simultaneously, and etching on both sides simultaneously.
図１３を用いて説明した製造方法は、図２に示す構造の製造方法の一例として説明したが、同様な方法を用いて、図４に示す構造を作製することができる。第２電極１８及び第３電極２３は、採用する接続方法に応じて図５（ｂ）又は（ｃ）に示した構造となるように作製してもよい。
Although the manufacturing method described with reference to FIG. 13 has been described as an example of the manufacturing method of the structure illustrated in FIG. 2, the structure illustrated in FIG. 4 can be manufactured using a similar method. The second electrode 18 and the third electrode 23 may be manufactured to have the structure shown in FIG. 5B or 5C depending on the connection method employed.
第２の製造例によれば、第１の実施形態による半導体装置を効率よく形成することができる。特に、第１の製造例に比べ、半導体基板１２が薄くても安定して製造できる。
According to the second manufacturing example, the semiconductor device according to the first embodiment can be efficiently formed. In particular, as compared with the first manufacturing example, the semiconductor substrate 12 can be manufactured stably even if it is thin.
第３の製造例
図１４を用いて第３の製造例について説明する。図１４は、本製造例を説明するための部分断面図である。 Third Manufacturing Example A third manufacturing example will be described with reference to FIG. FIG. 14 is a partial cross-sectional view for explaining the present manufacturing example.
図１４を用いて第３の製造例について説明する。図１４は、本製造例を説明するための部分断面図である。 Third Manufacturing Example A third manufacturing example will be described with reference to FIG. FIG. 14 is a partial cross-sectional view for explaining the present manufacturing example.
第３の製造例は、第１の製造例と比較して、第２構造層１４と第３構造層１９とが絶縁層と配線の組み合わせ単位で交互に積層されて形成されている点が異なっている。以下に、第１の製造例と異なる点について説明する。特に記載のない部分については、第１の製造例と同じである。
The third manufacturing example is different from the first manufacturing example in that the second structural layer 14 and the third structural layer 19 are alternately stacked in units of combinations of insulating layers and wirings. ing. Hereinafter, differences from the first manufacturing example will be described. Parts not particularly described are the same as those in the first production example.
図１４（ａ）に示すように半導体基板１２上に素子および第１構造層１３を形成した後、図１４（ｂ）に示すように、第２構造層１４の基板側部分（配線１５、絶縁層１６及びビア１７）を第１構造層１３に直接接するように形成する。
After forming the element and the first structural layer 13 on the semiconductor substrate 12 as shown in FIG. 14A, as shown in FIG. 14B, the substrate side portion of the second structural layer 14 (wiring 15 and insulation). The layer 16 and the via 17) are formed so as to be in direct contact with the first structural layer 13.
次に、図１４（ｃ）に示すように、第３構造層１９の基板側部分（配線２０および絶縁層２１）を第１構造層１３が形成された基板面の反対面に直接形成する。
Next, as shown in FIG. 14C, the substrate side portion (the wiring 20 and the insulating layer 21) of the third structure layer 19 is directly formed on the opposite surface of the substrate surface on which the first structure layer 13 is formed.
次に、第２構造層の上層側部分および第３構造層の上層側部分を形成して、図１４（ｄ）に示す所望の構造を形成する。その際、第２絶縁層の形成および第２配線の形成と、第３絶縁層の形成および第３配線の形成とを交互に行う。
Next, an upper layer side portion of the second structure layer and an upper layer side portion of the third structure layer are formed to form a desired structure shown in FIG. At that time, the formation of the second insulating layer and the second wiring, and the formation of the third insulating layer and the formation of the third wiring are performed alternately.
図１４を用いて説明した製造方法は、図２に示す構造の製造方法の一例として説明したが、同様な方法を用いて、図４に示す構造を作製することができる。第２電極１８及び第３電極２３は、採用する接続方法に応じて図５（ｂ）又は（ｃ）に示した構造となるように作製してもよい。
The manufacturing method described with reference to FIG. 14 has been described as an example of the manufacturing method of the structure illustrated in FIG. 2, but the structure illustrated in FIG. 4 can be manufactured using a similar method. The second electrode 18 and the third electrode 23 may be manufactured to have the structure shown in FIG. 5B or 5C depending on the connection method employed.
第３の製造例によれば、第１の実施形態による半導体装置を効率よく形成することができる。特に、第１の製造例に比べ、半導体基板１２が薄くても安定して製造でき、また、第２構造層１４と第３構造層１９との位置精度をより高めることができる。
According to the third manufacturing example, the semiconductor device according to the first embodiment can be efficiently formed. In particular, as compared with the first manufacturing example, the semiconductor substrate 12 can be stably manufactured even if it is thin, and the positional accuracy between the second structure layer 14 and the third structure layer 19 can be further increased.
第４の製造例
図１５を用いて第４の製造例について説明する。図１５は本製造例を説明するための部分断面図である。 Fourth Manufacturing Example A fourth manufacturing example will be described with reference to FIG. FIG. 15 is a partial cross-sectional view for explaining the present manufacturing example.
図１５を用いて第４の製造例について説明する。図１５は本製造例を説明するための部分断面図である。 Fourth Manufacturing Example A fourth manufacturing example will be described with reference to FIG. FIG. 15 is a partial cross-sectional view for explaining the present manufacturing example.
第４の製造例は、第１、第２及び第３の製造例と比較して、半導体基板１２に貫通ビア３４を形成することが異なっている。以下に、第１、第２及び第３の製造例と異なる点について説明する。特に記載のない部分については、第１、第２及び第３の製造例と同じである。
The fourth manufacturing example is different from the first, second, and third manufacturing examples in that the through via 34 is formed in the semiconductor substrate 12. Hereinafter, differences from the first, second, and third production examples will be described. Parts not particularly described are the same as those in the first, second, and third production examples.
図１５に示すように、半導体基板１２上に素子および第１構造層１３を形成し、貫通ビア３４を形成する。貫通ビア３４は、前述の第２の実施形態において説明した方法より形成でき、第１構造層１３を形成した後に形成してもよいし、第１構造層１３より先に形成してもよい。また、半導体基板１２に貫通ビア３４となる凹部を設け、導体を充填した後、第１構造層１３を形成し、半導体基板１２の第１構造層１３が形成されていない側の面を研削やエッチングすることにより貫通ビア３４を露出させる方法を行っても構わない。貫通ビア３４は、半導体基板１２の一方の面側に設けられている第１構造層１３及び第２構造層１４と、他方の面側に設けられている第３構造層１９とを必要な機能に応じて電気的に接続するように形成する。つまり、第１構造層１３と第２構造層１５のいずれかもしくは両方が第３構造層１９と電気的に接続される。
As shown in FIG. 15, the element and the first structure layer 13 are formed on the semiconductor substrate 12, and the through via 34 is formed. The through via 34 can be formed by the method described in the second embodiment, and may be formed after the first structure layer 13 is formed, or may be formed before the first structure layer 13. In addition, the semiconductor substrate 12 is provided with a recess serving as a through via 34 and filled with a conductor, and then the first structure layer 13 is formed, and the surface of the semiconductor substrate 12 where the first structure layer 13 is not formed is ground. A method of exposing the through via 34 by etching may be performed. The through via 34 has a function necessary for the first structural layer 13 and the second structural layer 14 provided on one surface side of the semiconductor substrate 12 and the third structural layer 19 provided on the other surface side. It forms so that it may electrically connect according to. That is, one or both of the first structure layer 13 and the second structure layer 15 are electrically connected to the third structure layer 19.
図１５に示した構造を形成した後の工程は、図１１、図１３、図１４を用いて説明した工程により、第２構造層１４と第３構造層１９を形成できる。
The second structure layer 14 and the third structure layer 19 can be formed by the steps described with reference to FIGS. 11, 13, and 14 after forming the structure shown in FIG.
第４の製造例によれば、第１、第２及び第３の製造例の効果に加え、基板の一方の面側の配線と他方の面側の配線が接続された第２実施形態による半導体装置を効率良く製造することができる。
According to the fourth manufacturing example, in addition to the effects of the first, second, and third manufacturing examples, the semiconductor according to the second embodiment in which the wiring on one surface side of the substrate and the wiring on the other surface side are connected. The apparatus can be manufactured efficiently.
第５の製造例
図１６を用いて第５の製造例について説明する。図１６は本製造例を説明するための部分断面図である。 Fifth Manufacturing Example A fifth manufacturing example will be described with reference to FIG. FIG. 16 is a partial cross-sectional view for explaining the present manufacturing example.
図１６を用いて第５の製造例について説明する。図１６は本製造例を説明するための部分断面図である。 Fifth Manufacturing Example A fifth manufacturing example will be described with reference to FIG. FIG. 16 is a partial cross-sectional view for explaining the present manufacturing example.
第５の製造例は、第４の製造例と比較して、第２構造層１４の製造工程途中で、半導体基板１２に貫通ビア３４を形成することが異なっている。以下に、第４の製造例と異なる点について説明する。特に記載のない部分については、第４の製造例と同じである。
The fifth manufacturing example is different from the fourth manufacturing example in that the through via 34 is formed in the semiconductor substrate 12 during the manufacturing process of the second structural layer 14. Below, a different point from the 4th manufacture example is explained. Parts not particularly described are the same as in the fourth production example.
図１６（ａ）に示すように、前述の製造方法に従って、第１構造層１３上に第２構造層１４の基板側部分（配線１５、絶縁層１６及びビア１７）を形成する。
As shown in FIG. 16A, the substrate side portion (the wiring 15, the insulating layer 16, and the via 17) of the second structural layer 14 is formed on the first structural layer 13 in accordance with the manufacturing method described above.
次に、図１６（ｂ）に示すように、半導体基板１２に貫通ビア３４を形成する。貫通ビア３４は、前述の第２の実施形態において説明した方法を利用して形成することができる。
Next, as shown in FIG. 16B, a through via 34 is formed in the semiconductor substrate 12. The through via 34 can be formed using the method described in the second embodiment.
また、半導体基板１２の貫通ビア３４を形成する部分に凹部を設け、導体を充填した後、第１構造層１３と第２構造層１４の一部を形成し、半導体基板１２の第１構造層１３が形成されていない側の面を研削やエッチングすることにより貫通ビア３４を露出させる方法を行っても構わない。
In addition, a recess is provided in a portion of the semiconductor substrate 12 where the through via 34 is formed, and after filling the conductor, a part of the first structure layer 13 and the second structure layer 14 is formed, and the first structure layer of the semiconductor substrate 12 is formed. You may perform the method of exposing the through-via 34 by grinding or etching the surface of the side in which 13 is not formed.
貫通ビア３４は、半導体基板１２の一方の面側に設けられている第１構造層１３及び第２構造層１４と、他方の面側に設けられている第３配線構造１９とを必要な機能に応じて電気的に接続するように形成する。つまり、第１構造層１３と第２構造層１５のいずれかもしくは両方が第３構造層１９と電気的に接続される。
The through via 34 has a function necessary for the first structure layer 13 and the second structure layer 14 provided on one surface side of the semiconductor substrate 12 and the third wiring structure 19 provided on the other surface side. It forms so that it may electrically connect according to. That is, one or both of the first structure layer 13 and the second structure layer 15 are electrically connected to the third structure layer 19.
貫通ビア３４を形成した後は、前述の製造方法に従って、第２構造層１４の残りの部分及び第３構造層１９を形成する。
After the through via 34 is formed, the remaining part of the second structure layer 14 and the third structure layer 19 are formed according to the above-described manufacturing method.
第５の製造例によれば、第１、第２及び第３の製造例の効果に加え、基板の一方の面側の配線と他方の面側の配線が接続された第２実施形態による半導体装置を効率良く製造することができる。さらに、第１構造層１３と第２構造層１４の両方に直接接続する貫通ビア３４を形成することが容易となり、より高密度な半導体装置を製造することができる。
According to the fifth manufacturing example, in addition to the effects of the first, second, and third manufacturing examples, the semiconductor according to the second embodiment in which the wiring on one surface side of the substrate and the wiring on the other surface side are connected. The apparatus can be manufactured efficiently. Furthermore, it is easy to form the through via 34 that is directly connected to both the first structure layer 13 and the second structure layer 14, and a higher-density semiconductor device can be manufactured.
第６の製造例
図１７を用いて第６の製造例について説明する。図１７は本製造例を説明するための部分断面図である。 Sixth Manufacturing Example A sixth manufacturing example will be described with reference to FIG. FIG. 17 is a partial cross-sectional view for explaining the present manufacturing example.
図１７を用いて第６の製造例について説明する。図１７は本製造例を説明するための部分断面図である。 Sixth Manufacturing Example A sixth manufacturing example will be described with reference to FIG. FIG. 17 is a partial cross-sectional view for explaining the present manufacturing example.
第６の製造例は、第５の製造例と比較して、第２構造層１４の形成工程完了後に、半導体基板１２に貫通ビア３４を形成することが異なっている。以下に、第５の製造例と異なる点について説明する。特に記載のない部分については、第５の製造例と同じである。
The sixth manufacturing example is different from the fifth manufacturing example in that the through via 34 is formed in the semiconductor substrate 12 after the formation process of the second structural layer 14 is completed. Hereinafter, differences from the fifth manufacturing example will be described. Parts not particularly described are the same as those in the fifth production example.
図１７（ａ）に示すように、前述の製造方法に従って、第１構造層１３上に第２構造層１４を形成する。
As shown in FIG. 17A, the second structural layer 14 is formed on the first structural layer 13 in accordance with the manufacturing method described above.
次に、図１７（ｂ）に示すように、半導体基板１２に貫通ビア３４を形成する。貫通ビア３４は、前述の第２の実施形態において説明した方法を利用して形成することができる。また、半導体基板１２の貫通ビア３４を形成する部分に凹部を設け、導体を充填した後、第１構造層１３と第２構造層１４を形成し、半導体基板１２の第１構造層１３が形成されていない側の面を研削やエッチングすることにより貫通ビア３４を露出させる方法を行っても構わない。
Next, as shown in FIG. 17B, a through via 34 is formed in the semiconductor substrate 12. The through via 34 can be formed using the method described in the second embodiment. In addition, a recess is formed in a portion of the semiconductor substrate 12 where the through via 34 is formed, and after filling the conductor, the first structure layer 13 and the second structure layer 14 are formed, and the first structure layer 13 of the semiconductor substrate 12 is formed. You may perform the method of exposing the penetration via 34 by grinding or etching the surface of the side which is not carried out.
貫通ビア３４を形成した後は、前述の製造方法に従って、図１７（ｃ）に示すように、第３配線構造１９を形成する。
After the through via 34 is formed, the third wiring structure 19 is formed as shown in FIG.
図１７に示す第２構造層１４と第３構造層１９は、図２に示す構造と同様であるが、同様な方法を用いて、図４に示す構造と同様な構造であっても同様な方法により製造できる。また、第２電極１８や第３電極２３は、接続方法に応じて図５（ｂ）又は（ｃ）に示した構造となるように作製してもよい。
The second structure layer 14 and the third structure layer 19 shown in FIG. 17 are similar to the structure shown in FIG. 2, but the same method is used even if the structure is similar to the structure shown in FIG. It can be manufactured by a method. Moreover, you may produce the 2nd electrode 18 and the 3rd electrode 23 so that it may become a structure shown in FIG.5 (b) or (c) according to the connection method.
第６の製造例によれば、第１、第２及び第３の製造例の効果に加え、基板の一方の面側の配線と他方の面側の配線が接続された第２実施形態による半導体装置を効率良く製造することができる。さらに、第２構造層１４の第２配線１５に直接接続する貫通ビア３４を形成することが容易となり、より高密度な半導体装置を製造することができる。
According to the sixth manufacturing example, in addition to the effects of the first, second, and third manufacturing examples, the semiconductor according to the second embodiment in which the wiring on one surface side of the substrate and the wiring on the other surface side are connected. The apparatus can be manufactured efficiently. Furthermore, it is easy to form the through via 34 that is directly connected to the second wiring 15 of the second structure layer 14, and a higher-density semiconductor device can be manufactured.
第７の製造例
図１８を用いて第７の製造例について説明する。図１８は本製造例を説明するための部分断面図である。 Seventh Manufacturing Example A seventh manufacturing example will be described with reference to FIG. FIG. 18 is a partial cross-sectional view for explaining the present manufacturing example.
図１８を用いて第７の製造例について説明する。図１８は本製造例を説明するための部分断面図である。 Seventh Manufacturing Example A seventh manufacturing example will be described with reference to FIG. FIG. 18 is a partial cross-sectional view for explaining the present manufacturing example.
第７の製造例は、第６の製造例と比較して、第３構造層１９の形成工程において、基板側の第３絶縁層２１の形成後に、半導体基板１２に貫通ビア３４を形成することが異なっている。以下に、第６の製造例と異なる点について説明する。特に記載のない部分については、第６の製造方法と同じである。
In the seventh manufacturing example, the through via 34 is formed in the semiconductor substrate 12 after the formation of the third insulating layer 21 on the substrate side in the step of forming the third structure layer 19 as compared with the sixth manufacturing example. Is different. Hereinafter, differences from the sixth production example will be described. Portions not particularly described are the same as in the sixth manufacturing method.
図１８（ａ）に示すように半導体基板１２の一方の面に第１構造層１３及び第２構造層１４を形成した後、半導体基板１２の他方の面に第３構造層１９の第３絶縁層２１を形成し、形成する貫通ビア３４に対応する開口部を設ける。次に、図１８（ｂ）に示すように、この開口部にあわせて半導体基板１２に貫通ビア３４を形成する。
As shown in FIG. 18A, after the first structure layer 13 and the second structure layer 14 are formed on one surface of the semiconductor substrate 12, the third insulation of the third structure layer 19 is formed on the other surface of the semiconductor substrate 12. The layer 21 is formed, and an opening corresponding to the through via 34 to be formed is provided. Next, as shown in FIG. 18B, a through via 34 is formed in the semiconductor substrate 12 in accordance with the opening.
貫通ビア３４を形成した後は、前述の製造方法に従って、図１８（ｃ）に示すように、第３構造層１９の残りの部分を形成する。
After the through via 34 is formed, the remaining part of the third structure layer 19 is formed as shown in FIG.
第７の製造例によれば、第１、第２及び第３の製造例の効果に加え、基板の一方の面側の配線と他方の面側の配線が接続された第２実施形態による半導体装置を効率良く製造することができる。さらに、第３構造層１９と接続する貫通ビア３４の形成位置の精度を高めることができ、より高密度な半導体装置を製造することができる。
According to the seventh manufacturing example, in addition to the effects of the first, second, and third manufacturing examples, the semiconductor according to the second embodiment in which the wiring on one surface side of the substrate and the wiring on the other surface side are connected. The apparatus can be manufactured efficiently. Furthermore, the accuracy of the formation position of the through via 34 connected to the third structure layer 19 can be increased, and a higher density semiconductor device can be manufactured.
第８の製造例
図１９を用いて第８の製造例について説明する。図１９は本製造例を説明するための部分断面図である。 Eighth Manufacturing Example An eighth manufacturing example will be described with reference to FIG. FIG. 19 is a partial cross-sectional view for explaining the present manufacturing example.
図１９を用いて第８の製造例について説明する。図１９は本製造例を説明するための部分断面図である。 Eighth Manufacturing Example An eighth manufacturing example will be described with reference to FIG. FIG. 19 is a partial cross-sectional view for explaining the present manufacturing example.
第８の製造例では、前述の他の製造例と比較して、前述のいずれかの実施形態による半導体装置を複数積層することが異なっている。以下に、第８の製造例について説明する。特に記載のない部分については、前述の製造方法と同じである。
The eighth manufacturing example is different from the other manufacturing examples described above in that a plurality of semiconductor devices according to any of the above-described embodiments are stacked. The eighth production example will be described below. Portions that are not particularly described are the same as in the manufacturing method described above.
まず、図１９（ａ）に示すように、複数の半導体装置を接続部３５により接続する。複数の半導体装置の接続は、ウエハ状態の半導体装置部分同士を接続してもよく、個別の半導体装置同士を接続してもよく、ウエハ状態の半導体装置部分と個別の半導体装置とを接続しても構わない。ウエハ状態の半導体装置部分は、接続後に分割することができる。歩留まりの観点からは、最下層となる半導体装置はウエハ状態で、積層される半導体装置は個別の半導体装置として接続することが好ましい。
First, as shown in FIG. 19A, a plurality of semiconductor devices are connected by a connecting portion 35. Connection of a plurality of semiconductor devices may be performed by connecting semiconductor device portions in a wafer state, connecting individual semiconductor devices, or connecting a semiconductor device portion in a wafer state and individual semiconductor devices. It doesn't matter. The semiconductor device portion in the wafer state can be divided after connection. From the viewpoint of yield, it is preferable that the semiconductor device as the lowermost layer is in a wafer state and the stacked semiconductor devices are connected as individual semiconductor devices.
次に、図１９（ｂ）に示すように、最下層の半導体装置の下面側には外部端子としてのハンダボール３６を形成する。このようなハンダボール３６に代えて、ピン、Ａｕバンプ、銅バンプ、予備ハンダ、金属パール、ＡＣＦ、ＮＣＦなどを用いた接続構造を形成してもよい。
Next, as shown in FIG. 19B, solder balls 36 as external terminals are formed on the lower surface side of the lowermost semiconductor device. Instead of such solder balls 36, a connection structure using pins, Au bumps, copper bumps, spare solder, metal pearls, ACF, NCF, or the like may be formed.
図１９（ｂ）に示す積層型の半導体装置は、図８に示す積層型の半導体装置に相当するが、同様な方法を用いることで、図９や図１０に示す半導体装置を製造することできる。また、二つの半導体装置の積層構造に限定されることはなく、三つ以上の半導体装置を積層しても構わない。
The stacked semiconductor device shown in FIG. 19B corresponds to the stacked semiconductor device shown in FIG. 8, but the semiconductor device shown in FIGS. 9 and 10 can be manufactured by using a similar method. . Further, the present invention is not limited to the stacked structure of two semiconductor devices, and three or more semiconductor devices may be stacked.
第８の製造例によれば、第３の実施形態による半導体装置を効率良く製造することができる。
According to the eighth manufacturing example, the semiconductor device according to the third embodiment can be efficiently manufactured.
以上、実施形態を参照して本発明を説明したが、本発明は上記実施形態に限定されるものではない。本発明の構成や詳細には、本発明の範囲内で当業者が理解し得る様々な変更をすることができる。
The present invention has been described above with reference to the embodiments, but the present invention is not limited to the above embodiments. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention.
この出願は、２００８年１０月２１日に出願された日本出願特願２００８－２７１１８７を基礎とする優先権を主張し、その開示の全てをここに取り込む。
This application claims priority based on Japanese Patent Application No. 2008-271187 filed on Oct. 21, 2008, the entire disclosure of which is incorporated herein.
Claims (24)
- 素子を含む基板と、
第１絶縁層、及び前記素子に電気的に接続された第１配線を含み、前記基板の片面に設けられた第１構造層と、
第２絶縁層、及び前記第１配線と電気的に接続された第２配線を含み、前記第１構造層上に積層された、前記第１構造層よりも厚い第２構造層と、
第３絶縁層および第３配線を含み、前記基板の前記第１構造層が設けられた面の反対面に設けられた第３構造層とを有する半導体装置。 A substrate including the element;
A first insulating layer and a first structure layer provided on one side of the substrate, including a first wiring electrically connected to the element;
A second structural layer including a second insulating layer and a second wiring electrically connected to the first wiring, the second structural layer being stacked on the first structural layer and being thicker than the first structural layer;
A semiconductor device comprising a third structure layer including a third insulating layer and a third wiring and provided on a surface opposite to the surface on which the first structure layer of the substrate is provided. - 前記第１構造層は、前記第１絶縁層と前記第１配線が交互に積層された多層配線構造を有し、前記第２構造層は、前記第２絶縁層と前記第２配線が交互に積層された多層配線構造を有し、前記第３構造層は、前記第３絶縁層と前記第３配線が交互に積層された多層配線構造を有する、請求項１に記載の半導体装置。 The first structural layer has a multilayer wiring structure in which the first insulating layer and the first wiring are alternately stacked, and the second structural layer has the second insulating layer and the second wiring alternately. 2. The semiconductor device according to claim 1, wherein the semiconductor device has a laminated multilayer wiring structure, and the third structural layer has a multilayer wiring structure in which the third insulating layer and the third wiring are alternately laminated.
- 前記第２配線が、前記第１配線より厚い、請求項１又は２に記載の半導体装置。 The semiconductor device according to claim 1, wherein the second wiring is thicker than the first wiring.
- 前記第２絶縁層が、前記第１絶縁層より厚い、請求項１から３のいずれか一項に記載の半導体装置。 The semiconductor device according to any one of claims 1 to 3, wherein the second insulating layer is thicker than the first insulating layer.
- 前記第３配線が、前記第１配線より厚い、請求項１から４のいずれか一項に記載の半導体装置。 The semiconductor device according to any one of claims 1 to 4, wherein the third wiring is thicker than the first wiring.
- 前記第３絶縁層が、前記第１絶縁層より厚い、請求項１から５のいずれか一項に記載の半導体装置。 The semiconductor device according to claim 1, wherein the third insulating layer is thicker than the first insulating layer.
- 前記第２構造層は、前記第１構造層内の複数の電源系配線をまとめて端子数が低減するように電源系配線が形成されている、請求項１から６のいずれか一項に記載の半導体装置。 7. The power supply system wiring according to claim 1, wherein the second structure layer is formed with a power supply system wiring so as to reduce the number of terminals by combining a plurality of power supply system wirings in the first structure layer. 8. Semiconductor device.
- 前記第２構造層は、前記第１構造層内の複数のグランド系配線をまとめて端子数が低減するようにグランド系配線が形成されている、請求項１から８のいずれか一項に記載の半導体装置。 9. The ground wiring is formed on the second structural layer so as to reduce the number of terminals by combining a plurality of ground wiring in the first structural layer. 9. Semiconductor device.
- 前記基板を貫通し、前記第１配線または前記第２配線と前記第３配線とを電気的に接続する、貫通ビアを有する、請求項１から８のいずれか一項に記載の半導体装置。 The semiconductor device according to claim 1, further comprising a through via that penetrates the substrate and electrically connects the first wiring or the second wiring and the third wiring.
- 前記第３構造層は、前記第１構造層内の複数の電源系配線をまとめて端子数が低減するように電源系配線が形成されている、請求項９に記載の半導体装置。 10. The semiconductor device according to claim 9, wherein the third structure layer is formed with a power supply system wiring so that a plurality of power supply system wirings in the first structure layer are combined to reduce the number of terminals.
- 前記第３構造層は、前記第１構造層内の複数のグランド系配線をまとめて端子数が低減するようにグランド系配線が形成されている、請求項９又は１０に記載の半導体装置。 11. The semiconductor device according to claim 9, wherein the third structure layer is formed with a ground wiring so as to reduce the number of terminals by combining a plurality of ground wirings in the first structural layer.
- 前記第２構造層の前記第２配線の層数と前記第３構造層の前記第３配線の層数とが同じである、請求項１から１１のいずれか一項に記載の半導体装置。 12. The semiconductor device according to claim 1, wherein the number of the second wirings in the second structural layer is the same as the number of the third wirings in the third structural layer.
- 前記第２構造層の前記第２絶縁層の層数と前記第３構造層の前記第３絶縁層の層数とが同じである、請求項１から１２のいずれか一項に記載の半導体装置。 13. The semiconductor device according to claim 1, wherein the number of the second insulating layers of the second structural layer is the same as the number of the third insulating layers of the third structural layer. .
- 請求項１から１３のいずれか一項に記載の同種または異種の複数の半導体装置が積層されていることを特徴とする半導体装置。 14. A semiconductor device, wherein a plurality of the same or different semiconductor devices according to claim 1 are stacked.
- 請求項１に記載の半導体装置を製造する製造方法であって、
複数の素子が形成された基板を用意する工程と、
前記基板の片面側に、前記第１構造層を形成する工程と、
前記第１構造層上に、前記第２構造層を形成する工程と、
前記基板の前記第１構造層が設けられた面の反対面に第３構造層を形成する工程とを有する、半導体装置の製造方法。 A manufacturing method for manufacturing the semiconductor device according to claim 1,
Preparing a substrate on which a plurality of elements are formed;
Forming the first structure layer on one side of the substrate;
Forming the second structure layer on the first structure layer;
Forming a third structure layer on a surface of the substrate opposite to the surface on which the first structure layer is provided. - 前記第２構造層および前記第３構造層の形成において、前記第２絶縁層の形成と前記第３絶縁層の形成を同じプロセスで同時に行い、前記第２配線の形成と前記第３配線の形成を同じプロセスで同時に行う、請求項１５に記載の半導体装置の製造方法。 In the formation of the second structure layer and the third structure layer, the formation of the second insulating layer and the formation of the third insulating layer are simultaneously performed in the same process, and the formation of the second wiring and the formation of the third wiring are performed. The method of manufacturing a semiconductor device according to claim 15, wherein the steps are performed simultaneously in the same process.
- 前記第２構造層および前記第３構造層の形成において、前記第２絶縁層の形成および前記第２配線の形成と、前記第３絶縁層の形成および前記第３配線の形成とを交互に行う、請求項１５に記載の半導体装置の製造方法。 In the formation of the second structure layer and the third structure layer, the formation of the second insulation layer and the formation of the second wiring, and the formation of the third insulation layer and the formation of the third wiring are performed alternately. A method for manufacturing a semiconductor device according to claim 15.
- 前記第１構造層を形成する工程前又は後において、前記基板を貫通するビアを形成する、請求項１５から１７のいずれか一項に記載の半導体装置の製造方法。 The method for manufacturing a semiconductor device according to any one of claims 15 to 17, wherein a via penetrating the substrate is formed before or after the step of forming the first structure layer.
- 前記第２構造層を形成する工程途中において、前記基板を貫通するビアを形成する、請求項１５から１８のいずれか一項に記載の半導体装置の製造方法。 19. The method of manufacturing a semiconductor device according to claim 15, wherein a via penetrating the substrate is formed during the step of forming the second structural layer.
- 前記第２構造層を形成する工程の後、前記第３構造層を形成する工程の前に、前記基板を貫通するビアを形成する、請求項１５から１９のいずれか一項に記載の半導体装置の製造方法。 20. The semiconductor device according to claim 15, wherein a via penetrating the substrate is formed after the step of forming the second structure layer and before the step of forming the third structure layer. Manufacturing method.
- 前記第３構造層を形成する工程途中において、前記基板を貫通するビアを形成する、請求項１５から２０のいずれか一項に記載の半導体装置の製造方法。 21. The method of manufacturing a semiconductor device according to claim 15, wherein a via penetrating the substrate is formed during the step of forming the third structure layer.
- 前記第１構造層を形成する工程の後、又は前記第２構造層を形成する工程の後に、前記基板を薄化する工程を行う、請求項１５から２１のいずれか一項に記載の半導体装置の製造方法。 The semiconductor device according to any one of claims 15 to 21, wherein a step of thinning the substrate is performed after the step of forming the first structure layer or the step of forming the second structure layer. Manufacturing method.
- 前記第１構造層と前記第２構造層と前記第３構造層を含む多層配線構造を、前記基板を含む半導体ウエハに複数形成し、その後、前記多層配線構造をそれぞれ含む各個片に分割する、請求項１５から２２のいずれか一項に記載の半導体装置の製造方法。 A plurality of multilayer wiring structures including the first structural layer, the second structural layer, and the third structural layer are formed on a semiconductor wafer including the substrate, and then divided into individual pieces each including the multilayer wiring structure; The method for manufacturing a semiconductor device according to claim 15.
- 請求項１５から２３のいずれか一項に記載の方法により同種又は異種の複数の半導体装置を形成する工程と、これらの半導体装置を積層する工程を含む、半導体装置の製造方法。 A method for manufacturing a semiconductor device, comprising: a step of forming a plurality of semiconductor devices of the same type or different types by the method according to any one of claims 15 to 23; and a step of stacking these semiconductor devices.
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| KR20170016325A (en) * | 2014-06-16 | 2017-02-13 | 인텔 코포레이션 | Metal on both sides with clock gated power and signal routing underneath |
| JP2017525129A (en) * | 2014-06-16 | 2017-08-31 | インテル・コーポレーション | Metal on both sides with clock gate power and signal routing below |
| KR102502496B1 (en) | 2014-06-16 | 2023-02-23 | 인텔 코포레이션 | Metal on both sides with clock gated power and signal routing underneath |
| KR20210125609A (en) * | 2014-06-16 | 2021-10-18 | 인텔 코포레이션 | Metal on both sides with clock gated power and signal routing underneath |
| CN106463530A (en) * | 2014-06-16 | 2017-02-22 | 英特尔公司 | Metal on both sides with clock gated power and signal routing underneath |
| EP3155666B1 (en) * | 2014-06-16 | 2021-05-12 | Intel IP Corporation | Metal on both sides with clock gated power and signal routing underneath |
| WO2016199437A1 (en) * | 2015-06-12 | 2016-12-15 | 株式会社ソシオネクスト | Semiconductor device |
| US10269774B2 (en) | 2015-06-12 | 2019-04-23 | Socionext Inc. | Semiconductor device |
| JPWO2016199437A1 (en) * | 2015-06-12 | 2018-03-29 | 株式会社ソシオネクスト | Semiconductor device |
| JP2018133586A (en) * | 2018-04-26 | 2018-08-23 | 大日本印刷株式会社 | Multilayer wiring line structure body |
| JP2021531048A (en) * | 2018-07-20 | 2021-11-18 | 京東方科技集團股▲ふん▼有限公司Boe Technology Group Co., Ltd. | Array substrate, its manufacturing method, and display device |
| JP7323521B2 (en) | 2018-07-20 | 2023-08-08 | 京東方科技集團股▲ふん▼有限公司 | ARRAY SUBSTRATE, MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE |
| JP2019153818A (en) * | 2019-06-20 | 2019-09-12 | 大日本印刷株式会社 | Multilayer wiring structure body |
Also Published As
| Publication number | Publication date |
|---|---|
| JP5413371B2 (en) | 2014-02-12 |
| JPWO2010047227A1 (en) | 2012-03-22 |
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