WO2010032659A1 - Disturbance detection circuit, semiconductor integrated circuit, disturbance detection method, and test method - Google Patents

Disturbance detection circuit, semiconductor integrated circuit, disturbance detection method, and test method Download PDF

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Publication number
WO2010032659A1
WO2010032659A1 PCT/JP2009/065703 JP2009065703W WO2010032659A1 WO 2010032659 A1 WO2010032659 A1 WO 2010032659A1 JP 2009065703 W JP2009065703 W JP 2009065703W WO 2010032659 A1 WO2010032659 A1 WO 2010032659A1
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Prior art keywords
disturbance detection
disturbance
circuit
output
detection circuit
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PCT/JP2009/065703
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French (fr)
Japanese (ja)
Inventor
義男 亀田
正之 水野
浩一 野瀬
宏一朗 野口
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日本電気株式会社
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Priority to JP2010529722A priority Critical patent/JPWO2010032659A1/en
Publication of WO2010032659A1 publication Critical patent/WO2010032659A1/en

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/001—Measuring interference from external sources to, or emission from, the device under test, e.g. EMC, EMI, EMP or ESD testing
    • G01R31/002—Measuring interference from external sources to, or emission from, the device under test, e.g. EMC, EMI, EMP or ESD testing where the device under test is an electronic circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/19—Monitoring patterns of pulse trains

Definitions

  • the present invention relates to a disturbance detection circuit, a semiconductor integrated circuit, a disturbance detection method, and a disturbance detection circuit test method for detecting a transient error caused by disturbance outside or inside the circuit.
  • External disturbances include radiation ( ⁇ rays, neutron rays, etc.) and electromagnetic waves, and internal disturbances include power supply noise.
  • transient errors due to disturbance have become a problem.
  • transient errors that occurred in memory have been a problem, but due to the recent reduction in power supply voltage and transistor size reduction due to miniaturization, transients caused by disturbances in flip-flops and combinational logic circuits other than memory
  • the probability of occurrence of errors is increasing.
  • the probability that an error occurs in a plurality of bits due to one cause is also increasing. Therefore, in order to improve the reliability of the semiconductor integrated circuit, it will be important in the future to detect transient errors due to disturbance and to measure the number of transient errors.
  • Patent Document 1 An example of a method using a memory as a method for detecting a transient error is disclosed in Japanese Patent Application Laid-Open No. 2007-293856 (hereinafter referred to as Patent Document 1). The method disclosed in Patent Document 1 will be briefly described.
  • FIG. 1 shows a configuration example of a detector that uses a memory to detect a transient error due to a disturbance.
  • the detector includes a plurality of detection circuits (memory cells) 101 arranged vertically and horizontally, a row decoder 102 and a column decoder 103 for selecting one detection circuit, and values from the detection circuits.
  • Read circuit 104 for reading, write circuit 105 for writing a value to the detection circuit, address generator 106 for designating the address of the detection circuit, write value generator 107, and comparator for comparing the value of the detection circuit with the write value 108 and a control circuit 109 that controls each unit.
  • the detection circuit 101 at the intersection is selected. Reading and writing of values stored in the selected detection circuit 101 are performed through the reading circuit 104 and the writing circuit 105, respectively.
  • the value generated by the write value generator 107 is written to each detection circuit 101 while changing the address by the address generator 106.
  • the address generator 106 changes the address, reads the value from each detection circuit 101, compares it with the value written by the write value generator 107, and detects a transient error due to disturbance due to a match / mismatch. To do.
  • each memory cell constituting the memory is selected one by one by address, and an operation of writing a certain value is repeated for all the memory cells.
  • the memory is then exposed to the test environment for a period of time. Thereafter, the memory cells constituting the memory are selected one by one again by the address, and the operation of reading the stored value is repeated for all the memory cells. Since it is necessary to repeat the selection of such memory cells, it takes time to do so. Further, an additional circuit such as an address decoder for selecting a memory cell is required.
  • An example of an object of the present invention is to provide a disturbance detection circuit, a semiconductor integrated circuit, a disturbance detection method, and a test method for the disturbance detection circuit that can easily detect the occurrence of a disturbance without using a memory. .
  • a disturbance detection circuit is configured to change a logical value of an output by occurrence of a disturbance in its own circuit, and to change a logical value of an output to a subsequent stage by changing a logical value of an input from the previous stage.
  • the disturbance detection logic gates of the plurality of disturbance detection logic gates are connected in series, and a constant logic value is input to the first stage of the disturbance detection logic gates among the plurality of disturbance detection logic gates.
  • the occurrence of the disturbance is detected by the change in the logic value of the output of the disturbance detection logic gate in the second stage.
  • a semiconductor integrated circuit has the above-described disturbance detection circuit.
  • the disturbance detection method starts the disturbance detection operation after the disturbance detection circuit is initialized by the initialization signal.
  • test method for the disturbance detection circuit tests the detection operation of the disturbance detection circuit by a test signal even if no disturbance occurs.
  • FIG. 1 is a diagram illustrating a configuration example of a detector that detects a transient error due to a disturbance using a memory.
  • FIG. 2 is a block diagram illustrating a configuration example of the disturbance detection circuit according to the first embodiment.
  • FIG. 3 is a timing chart showing the operation of the disturbance detection circuit according to the first embodiment.
  • FIG. 4 is a block diagram illustrating a configuration example of the disturbance detection circuit according to the second embodiment.
  • FIG. 5 is a timing chart showing the operation of the disturbance detection circuit according to the second embodiment.
  • FIG. 6 is a block diagram illustrating a configuration example of the disturbance detection circuit according to the third embodiment.
  • FIG. 7 is a timing chart showing the operation of the disturbance detection circuit according to the third embodiment.
  • FIG. 1 is a diagram illustrating a configuration example of a detector that detects a transient error due to a disturbance using a memory.
  • FIG. 2 is a block diagram illustrating a configuration example of the disturbance detection circuit according to the first embodiment.
  • FIG. 8 is a block diagram illustrating a configuration example of the disturbance detection circuit according to the fourth embodiment.
  • FIG. 9 is a block diagram illustrating a configuration example of the disturbance detection circuit according to the fifth embodiment.
  • FIG. 10 is a block diagram illustrating a configuration example of the disturbance detection circuit according to the sixth embodiment.
  • FIG. 11 is a block diagram illustrating a configuration example of the disturbance detection circuit according to the seventh embodiment.
  • FIG. 12 is a block diagram illustrating a configuration example of the disturbance detection circuit according to the eighth embodiment.
  • FIG. 13 is a circuit diagram showing a configuration example of the disturbance detection logic gate according to the ninth embodiment.
  • FIG. 14 is a timing chart showing the operation of the disturbance detection logic gate according to the ninth embodiment.
  • FIG. 15 is a timing chart showing another operation of the disturbance detection logic gate according to the ninth embodiment.
  • FIG. 16 is a circuit diagram showing an example of the configuration of the disturbance detection logic gate of the tenth embodiment.
  • FIG. 17 is a circuit diagram showing a configuration example of the disturbance detection logic gate of the eleventh embodiment.
  • FIG. 18 is a circuit diagram showing a configuration example of the disturbance detection logic gate of the twelfth embodiment.
  • FIG. 19 is a circuit diagram showing one configuration example of the disturbance detection logic gate of the thirteenth embodiment.
  • FIG. 2 is a block diagram showing a configuration example of the disturbance detection circuit of the present embodiment.
  • the disturbance detection circuit of the present embodiment has a plurality of disturbance detection logic gates G1 to Gn.
  • the output line of the first disturbance detection logic gate G1 is connected to the second disturbance detection logic gate G2, and the output line of the second disturbance detection logic gate G2 is connected to the third disturbance detection logic gate G3.
  • the same structure is repeated, and the output line of the (n-1) th disturbance detection logic gate Gn-1 is connected to the nth disturbance detection logic gate Gn.
  • the output (OUT) of the nth disturbance detection logic gate Gn is sent from the output line 201 of the disturbance detection circuit.
  • n is an integer of 2 or more.
  • the input of the disturbance detection logic gate G1 that is not connected to other disturbance detection logic gates is fixed to a certain logic value and is constant.
  • the disturbance detection logic gates G1 to Gn change the output logic value due to the occurrence of the disturbance, and change the output logic value when the input logic value changes.
  • the logical value is, for example, 1 or 0.
  • a specific configuration example of the disturbance detection logic gates G1 to Gn will be described in another embodiment.
  • FIG. 3 is a timing chart showing the operation of the disturbance detection circuit of this embodiment.
  • the change in the output value of the first disturbance detection logic gate G1 in which a transient error has occurred due to the disturbance changes the output value of the second disturbance detection logic gate G2, which is the third disturbance.
  • the output value of the detection logic gate G3 is changed, and thereafter, the same change is repeated to change the output value of the (n-1) th disturbance detection logic gate Gn-1, which is the output of the nth disturbance detection logic gate Gn.
  • the logic value of the output (OUT) of the output line 201 of the disturbance detection circuit is changed. Due to the change in the output of the disturbance detection circuit, it is possible to immediately detect a transient error due to the disturbance generated in one of the disturbance detection logic gates.
  • the disturbance detection circuit of this embodiment has a configuration in which the disturbance detection circuit described in the first embodiment is provided in parallel in two systems.
  • FIG. 4 is a block diagram illustrating a configuration example of the disturbance detection circuit according to the present embodiment.
  • the disturbance detection circuit of this embodiment includes a plurality of disturbance detection logic gates G11 to G1n and G21 to G2n.
  • the output line of the eleventh disturbance detection logic gate G11 of one system is connected to the twelfth disturbance detection logic gate G12, and the output line of the twelfth disturbance detection logic gate G12 is the thirteenth disturbance.
  • the output line of the 1n-1th disturbance detection logic gate G1n-1 is connected to the 1nth disturbance detection logic gate G1n.
  • the output (OUT1) of the 1nth disturbance detection logic gate G1n is sent from the output line 211 of the disturbance detection circuit.
  • a twelfth disturbance detection logic gate G12 is arranged immediately after the eleventh disturbance detection logic gate G11, a thirteenth disturbance detection logic gate G13 is arranged immediately after the twelfth disturbance detection logic gate G12, and so on. The arrangement is repeated, and the 1nth disturbance detection logic gate G1n is arranged immediately after the 1n-1th disturbance detection logic gate G1n-1.
  • the output line of the 21st disturbance detection logic gate G21 of another independent system is connected to the 22nd disturbance detection logic gate G22, and the output line of the 22nd disturbance detection logic gate G22 is connected to the 23rd disturbance. Thereafter, the same structure is repeated, and the output line of the 2n-1th disturbance detection logic gate G2n-1 is connected to the 2nth disturbance detection logic gate G2n.
  • the output (OUT2) of the 2nth disturbance detection logic gate G2n is sent from the output line 212 of the disturbance detection circuit.
  • FIG. 5 is a timing chart showing the operation of the disturbance detection circuit of this embodiment.
  • the change in the output value of the eleventh disturbance detection logic gate G11 in which a transient error has occurred due to the disturbance changes the output value of the twelfth disturbance detection logic gate G12, which is the thirteenth disturbance.
  • the output value of the detection logic gate G13 is changed. Thereafter, the same change is repeated, and the output value of the 1n-1th disturbance detection logic gate G1n-1 is changed to become the output of the 1nth disturbance detection logic gate G1n.
  • the logic value of the output (OUT1) of the output line 211 of the disturbance detection circuit is changed.
  • a change in the output value of the twenty-first disturbance detection logic gate G21 in which a transient error has occurred due to the same disturbance causes a change in the output value of the twenty-second disturbance detection logic gate G22, which is the twenty-third disturbance detection logic gate.
  • the output value of G23 is changed, and thereafter, the same change is repeated, and the output value of the 2n-1th disturbance detection logic gate G2n-1 is changed to output the 2nth disturbance detection logic gate G2n.
  • the logic value of the output (OUT2) of the output line 212 of the circuit is changed.
  • one disturbance causes two transient detection logic gates adjacent to each other to be transiently affected by the disturbance. Can detect that an error has occurred. That is, in the present embodiment, it is possible to detect a transient error that occurs in two bits in one disturbance.
  • the disturbance detection circuit of the present embodiment is provided with two systems with a configuration different from that of the second embodiment.
  • FIG. 6 is a block diagram showing a configuration example of the disturbance detection circuit of the present embodiment.
  • the connection between the disturbance detection logic gates is the same as in the second embodiment.
  • the 22nd disturbance detection logic gate G22 is arranged immediately after the 11th disturbance detection logic gate G11
  • the 13th disturbance detection logic gate G13 is arranged immediately after the 22nd disturbance detection logic gate G22, and so on.
  • the arrangement is repeated, and the 1nth disturbance detection logic gate G1n is arranged immediately after the 2n-1th disturbance detection logic gate G2n-1.
  • a twelfth disturbance detection logic gate G12 is arranged immediately after the twenty-first disturbance detection logic gate G21, a twenty-third disturbance detection logic gate G23 is arranged immediately after the twelfth disturbance detection logic gate G12, and The same arrangement is repeated, and the 2nth disturbance detection logic gate G2n is arranged immediately after the 1n-1th disturbance detection logic gate G1n-1.
  • the connections of the disturbance detection logic gates G11 to G1n and G21 to G2n are the same as in the second embodiment.
  • the output line of the eleventh disturbance detection logic gate G11 is connected to the twelfth disturbance detection logic gate G12
  • the output line of the twelfth disturbance detection logic gate G12 is connected to the thirteenth disturbance detection logic gate G13.
  • FIG. 7 is a timing chart showing the operation of the disturbance detection circuit of this embodiment.
  • the change in the output value of the eleventh disturbance detection logic gate G11 in which a transient error has occurred due to the disturbance changes the output value of the twelfth disturbance detection logic gate G12, which is the thirteenth disturbance.
  • the output value of the detection logic gate G13 is changed. Thereafter, the same change is repeated, and the output value of the 1n-1th disturbance detection logic gate G1n-1 is changed to be the output of the 1nth disturbance detection logic gate G1n.
  • the logic value of the output (OUT1) of the output line 211 of the disturbance detection circuit is changed.
  • a change in the output value of the 22nd disturbance detection logic gate G22 in which a transient error has occurred due to the same disturbance causes a change in the output value of the 23rd disturbance detection logic gate G23.
  • the output value of the 2n-1th disturbance detection logic gate G2n-1 is changed, and the logic value of the output (OUT2) of the output line 212 of the disturbance detection circuit, which is the output of the 2nth disturbance detection logic gate G2n, is changed. .
  • FIG. 8 is a block diagram illustrating a configuration example of the disturbance detection circuit according to the present embodiment.
  • the disturbance detection circuit of this embodiment has a plurality of disturbance detection circuits SG1 to SGn and an output selection circuit S1.
  • the disturbance detection circuits SG1 to SGn are any of the disturbance detection circuits of the first to third embodiments.
  • the output line of the first disturbance detection circuit SG1 is connected to the second disturbance detection circuit SG2 and the output selection circuit S1, and the output line of the second disturbance detection circuit SG2 is connected to the third disturbance detection circuit.
  • SG3 is connected to the output selection circuit S1, and in the same manner, the output line of the nth disturbance detection circuit (SGn) is connected to the output selection circuit Sn.
  • the output of the first disturbance detection circuit SG1 is input to the second disturbance detection circuit SG2 and the output selection circuit S1, and the output of the second disturbance detection circuit SG2 is output to the third disturbance detection circuit SG3.
  • the output of the nth disturbance detection circuit SGn is input to the output selection circuit Sn, and the output of the output selection circuit Sn is connected to the output (OUT) of the output line 221 of the disturbance detection circuit.
  • the output selection circuit S1 selects the output of the designated disturbance detection circuit and sends it out from the output line 221. .
  • the output of the i-th disturbance detection circuit SGi when the output of the i-th disturbance detection circuit SGi is selected, a transient error due to the disturbance generated in any of the first disturbance detection circuit SG1 to the i-th disturbance detection circuit SGi can be detected. . That is, the larger the value of i, the higher the detection sensitivity, and the detection sensitivity can be changed by the output selection circuit S1.
  • the disturbance detection circuit of the present embodiment is configured to output the detection of the disturbance detection circuit via an output control circuit.
  • FIG. 9 is a block diagram showing a configuration example of the disturbance detection circuit of the present embodiment.
  • the disturbance detection circuit of this embodiment includes a plurality of disturbance detection circuits SG1 to SGn, output control circuits OC1 to OCn, and a merge circuit M1.
  • the disturbance detection circuits SG1 to SGn are any of the disturbance detection circuits of the first to third embodiments.
  • the output of the first disturbance detection circuit SG1 is input to the first output control circuit OC1, and the output of the first output control circuit OC1 is input to the merge circuit M1. Further, the output of the second disturbance detection circuit SG2 is input to the second output control circuit OC2, and the output of the second output control circuit OC2 is input to the merging circuit M1. Similarly, the output of the nth disturbance detection circuit SGn is input to the nth output control circuit OCn, and the output of the nth output control circuit OCn is input to the merging circuit M1. The output of the merging circuit M1 becomes the output (OUT) of the output line 222 of the disturbance detection circuit of this embodiment.
  • Output control circuits OC1, OC2,..., OCn each switch whether to output signals input from disturbance detection circuits SG1 to SGn when a control signal is input.
  • the merging circuit M1 changes the output value compared to before the change.
  • the operation of the disturbance detection circuit of this embodiment will be briefly described.
  • the change in the output is input to the output control circuit, and the merging circuit M1 is caused by the change in any one of the output control circuits OC1 to OCn. Change the output value.
  • a transient error due to a disturbance generated in any of a plurality of disturbance detection circuits can be detected via the output control circuit. That is, the greater the number of disturbance detection circuits connected by the output control circuit, the higher the detection sensitivity, and the detection sensitivity can be changed by the output control circuit.
  • the disturbance detection circuit of the fourth embodiment can also be used as the disturbance detection circuit (SG1, SG2,..., SGn) of the present embodiment.
  • the disturbance detection circuit of this embodiment can be used as the disturbance detection circuit (SG1, SG2,..., SGn) of the fourth embodiment.
  • the disturbance detection circuit of this embodiment has a configuration in which the disturbance detection circuit can be initialized.
  • FIG. 10 is a block diagram illustrating a configuration example of the disturbance detection circuit according to the present embodiment.
  • the disturbance detection circuit of the present embodiment includes a disturbance detection circuit SG and an initialization circuit ITC.
  • the disturbance detection circuit SG is obtained by adding the following configuration to any of the disturbance detection circuits of the first to third embodiments.
  • the disturbance detection circuit according to the present embodiment has a configuration in which the disturbance detection circuit according to the sixth embodiment can be initialized when a disturbance occurs.
  • FIG. 11 is a block diagram showing a configuration example of the disturbance detection circuit of the present embodiment.
  • the disturbance detection circuit according to this embodiment includes the disturbance detection circuit SG described in the sixth embodiment and an initialization circuit ITC.
  • the disturbance detection circuit SG is not only connected to the initialization circuit ITC as in the sixth embodiment, but also its output line is connected to the initialization circuit ITC.
  • the initialization circuit ITC generates an initialization signal upon detection of a transient error. This makes it possible to repeatedly detect a transient error due to disturbance.
  • FIG. 12 is a block diagram showing a configuration example of the disturbance detection circuit of the present embodiment.
  • the disturbance detection circuit of the present embodiment includes the disturbance detection circuit SG and the initialization circuit ITC described in the seventh embodiment, and an output processing circuit OP.
  • the output line of the disturbance detection circuit SG is connected to the output processing circuit OP.
  • the output processing circuit OP has a function as a measuring instrument that measures a change in the output value of the disturbance detection circuit SG, and counts the number of transient errors that have occurred.
  • the number of disturbances generated per unit time can be measured by the output processing circuit measuring the number of transient errors for a certain period of time.
  • This embodiment is a configuration example of a disturbance detection logic gate applicable to the disturbance detection circuit according to any one of the first to third embodiments.
  • the source electrodes of the first and second PMOS transistors P1, P2 are connected to the power supply line VDD, and the respective substrate electrodes are connected to the P substrate line PSUB.
  • the source electrodes of the first and second NMOS transistors N1, N2 are connected to the ground line GND, and the respective substrate electrodes are connected to the N substrate line NSUB.
  • the gate electrode of the first PMOS transistor P1 is connected to the negative initialization signal line PCB, and the gate electrode of the second NMOS transistor N2 is connected to the initialization signal line PC.
  • the initialization signal line is a signal line for transmitting an initialization signal for causing the disturbance detection logic gate to transition to the initialization state.
  • the negative initialization signal line is a signal line for transmitting an inverted signal of the initialization signal.
  • the P substrate line PSUB is preferably maintained at the same potential as the power supply line VDD, and the N substrate line NSUB is preferably maintained at the same potential as the ground line GND. However, by changing the potential as necessary, the threshold voltage of the transistor is changed. The disturbance occurrence probability or disturbance detection sensitivity may be changed.
  • FIG. 14 is a timing chart showing the operation of the disturbance detection logic gate of this embodiment.
  • initialization is performed by setting the initialization signal line PC to the high level and the negative initialization signal line PCB to the low level.
  • the input line 301 is not connected to another disturbance detection logic gate, the input line 301 is set to a low level.
  • the initialization charges are accumulated in the internal node XN and become the high level, and the output line 302 is discharged and becomes the low level.
  • the initialization signal line PC is set to the low level and the negative initialization signal line PCB is set to the high level to end the initialization period, and the detection period starts.
  • the charge of the internal node XN is released due to disturbance during the detection period, and the internal node XN becomes low level.
  • the second PMOS transistor P2 is turned on, the output line 302 is connected to the power supply line VDD, and changes to the high level.
  • the output OUT of the disturbance detection logic gate changes from low level to high level. In this way, transient errors due to disturbances are detected.
  • FIG. 15 is a timing chart showing another operation of the disturbance detection logic gate of the present embodiment. Referring to FIG. 15, the initialization period is the same as the operation described with reference to FIG.
  • the input line 301 When the input line 301 is not connected to another disturbance detection logic gate, the input line 301 can be used as a test input line for inputting a test signal. By intentionally setting the input line 301 to the high level after the initialization period, it is possible to test whether the disturbance detection logic gate for detection functions normally.
  • This embodiment is another configuration example of the disturbance detection logic gate.
  • FIG. 16 is a circuit diagram showing a configuration example of the disturbance detection logic gate of the present embodiment.
  • the first PMOS transistor P1 and the second PMOS transistor P2 are interchanged, and the first NMOS transistor N1 and the second NMOS transistor N2 are interchanged. It is a configuration.
  • the gate electrode of the PMOS transistor connected to the internal node XN in the ninth embodiment is connected to the input line 301, and is connected to the input line 301 in the ninth embodiment.
  • the gate electrode of the NMOS transistor is connected to the internal node XN.
  • This embodiment is another configuration example of the disturbance detection logic gate.
  • FIG. 17 is a circuit diagram showing a configuration example of the disturbance detection logic gate of this embodiment.
  • the third and fourth PMOS transistors P3 and P4 are connected in parallel to the first and second PMOS transistors P1 and P2, respectively, in the ninth embodiment.
  • the third and fourth NMOS transistors N3 and N4 are connected in parallel to the first and second NMOS transistors N1 and N2, respectively, in the ninth embodiment.
  • the output value changes when at least one of the transistors is turned on, so that the sensitivity can be increased.
  • the number of parallel transistors is two, but more transistors can be arranged in parallel. It is also possible to select a different parallel number for each transistor.
  • This embodiment is another configuration example of the disturbance detection logic gate.
  • FIG. 18 is a circuit diagram showing a configuration example of the disturbance detection logic gate of the present embodiment.
  • the first and second PMOS transistors P1, P2 and the third and fourth PMOS transistors P3, P4 in the ninth embodiment are connected in series.
  • the first and second NMOS transistors N1 and N2 in the ninth embodiment and the third and fourth NMOS transistors N3 and N4 are connected in series, respectively.
  • the output value does not change unless both transistors are turned on, so the sensitivity can be weakened.
  • the number of series transistors is two, but more transistors can be arranged in series. It is also possible to select a different series number for each transistor.
  • This embodiment is another configuration example of the disturbance detection logic gate.
  • FIG. 19 is a circuit diagram showing a configuration example of the disturbance detection logic gate of the present embodiment.
  • first and second PMOS transistors P1, P2 and first and second NMOS transistors N1, N2 are provided, and their connection relation is also the ninth embodiment. It is the same.
  • the input line 311 is connected to the gate electrode of the first NMOS transistor N1, and the output line 321 is connected to the connection point between the second PMOS transistor P2 and the second NMOS transistor N2.
  • third and fourth PMOS transistors P3, P4 and third and fourth NMOS transistors N3, N4 are provided, and the connection relationship is the first and second PMOS transistors P1, P2 and the first and second. This is the same as the connection relationship of the NMOS transistors N1 and N2.
  • the input line 312 is connected to the gate electrode of the third NMOS transistor N3, and the output line 322 is connected to the connection point of the fourth PMOS transistor P4 and the fourth NMOS transistor N4.
  • the disturbance detection logic gate is a domino logic circuit, but a part thereof may be a domino logic circuit. Further, some or all of the disturbance detection logic gates are not limited to the Domino logic circuit but may be a combinational circuit or a sequential circuit. Further, which of the domino logic circuit, the combinational circuit, and the sequential circuit is included in the disturbance detection circuit may be determined according to the circuit to be evaluated.
  • the disturbance detection logic gate is made of a semiconductor integrated circuit.
  • the disturbance detection circuit described in the first to twelfth embodiments is also a semiconductor integrated circuit. It may be produced. Further, not only the integrated circuit to be evaluated, but also other integrated circuits may be formed on the same semiconductor substrate in parallel with the disturbance detection circuit.
  • the first to thirteenth embodiments are not limited to being implemented individually, and a plurality of combinations may be combined as long as they can be combined.
  • a transient error due to a disturbance can be easily detected only by monitoring the output of the final stage of the disturbance detection logic gate connected in series.
  • transient error detection is performed by comparing the value written before the test with the value read after the test, it takes time for the comparison operation. Further, in the detection method using a memory, it is necessary to provide an additional circuit for comparison or to provide a comparison device such as a tester outside. In addition, since the detector described in FIG. 1 repeatedly performs operations such as writing, testing, reading, and comparing at certain time intervals, it takes time from the occurrence of a transient error to the comparison, and a transient error is detected. The occurrence cannot be detected immediately. As an example of the effect of the present invention with respect to such a problem, since transient errors are successively transmitted through the disturbance detection logic gates connected in series, transient errors due to disturbance can be detected immediately. Further, there is no need to provide a comparison device such as an additional circuit for comparison or a tester outside.
  • the detection circuit is a memory cell
  • a transient error cannot be detected for flip-flops and combinational logic circuits other than the memory.
  • G1 to Gn G11 to G1n, G21 to G2n Disturbance detection logic gate SG, SG1 to SGn Disturbance detection circuit
  • S1 Output selection circuit OC1, OC2, OCn Output control circuit M1 merging circuit
  • ITC initialization circuit OP output processing circuit P1, P2, P3, P4 PMOS transistor N1, N2, N3, N4 NMOS transistor

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  • Tests Of Electronic Circuits (AREA)

Abstract

A disturbance detection circuit is provided with a system in which a plurality of disturbance detection logic gates (G1 to Gn) each of which changes the logic value of the output in response to occurrence of a disturbance within the circuit and changes the logic value of the output to the next stage in response to a change in the logic value of the input from the previous stage are connected in series.  The disturbance detection circuit is configured in such a manner that a constant logic value is inputted to the first-stage disturbance detection logic gate (G1) among the disturbance detection logic gates and that the occurrence of a disturbance is detected by the change in the logic value of the output of the disturbance detection logic gate (Gn) in the last-stage among the disturbance detection logic gates.

Description

擾乱検出回路、半導体集積回路、擾乱検出方法および試験方法Disturbance detection circuit, semiconductor integrated circuit, disturbance detection method and test method
　本発明は、回路の外部または内部の擾乱に起因する一過性のエラーを検出するための擾乱検出回路、半導体集積回路、擾乱検出方法、および擾乱検出回路の試験方法に関する。 The present invention relates to a disturbance detection circuit, a semiconductor integrated circuit, a disturbance detection method, and a disturbance detection circuit test method for detecting a transient error caused by disturbance outside or inside the circuit.
　半導体集積回路の外部または内部の擾乱により、半導体集積回路の信号電位が乱されたり、蓄積されていた電荷が減少したりするなどして、本来の値とは異なる値を出力するエラーが発生する。このエラーは一過性のもので、継続的に起こるハードエラーに対して、ソフトエラーと呼ばれる。 Due to disturbances outside or inside the semiconductor integrated circuit, the signal potential of the semiconductor integrated circuit is disturbed, or the accumulated charge is reduced, and an error occurs that outputs a value different from the original value. . This error is transient and is called a soft error for a continuous hard error.
　外部の擾乱として放射線（α線、中性子線等）や電磁波があり、内部の擾乱として電源ノイズなどがある。近年の、半導体プロセスの微細化が進むにつれて、擾乱に起因する一過性のエラーが問題となってきている。これまで、メモリに発生する一過性のエラーが問題となっていたが、近年の電源電圧の低下や微細化によるトランジスタサイズ縮小により、メモリ以外のフリップフロップや組み合わせ論理回路でも擾乱による一過性のエラーが発生する確率が高まっている。さらに、一つの原因で複数のビットにエラーが発生する確率も高まっている。そのため、半導体集積回路の信頼性を高めるために、擾乱による一過性のエラーを検出すること、一過性のエラーの数を測定することは今後重要になる。 External disturbances include radiation (α rays, neutron rays, etc.) and electromagnetic waves, and internal disturbances include power supply noise. In recent years, with the progress of miniaturization of semiconductor processes, transient errors due to disturbance have become a problem. Until now, transient errors that occurred in memory have been a problem, but due to the recent reduction in power supply voltage and transistor size reduction due to miniaturization, transients caused by disturbances in flip-flops and combinational logic circuits other than memory The probability of occurrence of errors is increasing. Furthermore, the probability that an error occurs in a plurality of bits due to one cause is also increasing. Therefore, in order to improve the reliability of the semiconductor integrated circuit, it will be important in the future to detect transient errors due to disturbance and to measure the number of transient errors.
　一過性のエラーを検出する方法として、メモリを用いる方法の一例が、特開２００７－２９３８５６号公報（以下では、特許文献１と称する）に開示されている。特許文献１に開示された方法を簡単に説明する。 An example of a method using a memory as a method for detecting a transient error is disclosed in Japanese Patent Application Laid-Open No. 2007-293856 (hereinafter referred to as Patent Document 1). The method disclosed in Patent Document 1 will be briefly described.
　はじめに、メモリを構成するメモリセルを一つ一つ選択し、それぞれにある値を書き込み、試験環境に一定期間さらす。その後、再びメモリセルを一つ一つ選択し、記憶されている値を読み出す。試験前に書き込んだ値と、試験後に読み出した値を比較し、一致・不一致で擾乱による一過性のエラーを検出する。 First, select the memory cells that make up the memory one by one, write a value to each, and expose it to the test environment for a certain period of time. Thereafter, the memory cells are selected one by one again, and the stored value is read out. The value written before the test and the value read after the test are compared, and a transient error due to a disturbance is detected with a match / mismatch.
　図１は、メモリを用いた、擾乱による一過性のエラーを検出する検出器の一構成例を示す。図１に示すように、検出器は、縦横に配置された複数の検出回路（メモリセル）１０１と、１つの検出回路を選択するための行デコーダ１０２および列デコーダ１０３と、検出回路から値を読みだす読み出し回路１０４と、検出回路に値を書き込む書き込み回路１０５と、検出回路のアドレスを指定するアドレス発生器１０６と、書き込み値発生器１０７と、検出回路の値と書き込み値を比較する比較器１０８と、各部を制御する制御回路１０９と、を有する構成である。 FIG. 1 shows a configuration example of a detector that uses a memory to detect a transient error due to a disturbance. As shown in FIG. 1, the detector includes a plurality of detection circuits (memory cells) 101 arranged vertically and horizontally, a row decoder 102 and a column decoder 103 for selecting one detection circuit, and values from the detection circuits. Read circuit 104 for reading, write circuit 105 for writing a value to the detection circuit, address generator 106 for designating the address of the detection circuit, write value generator 107, and comparator for comparing the value of the detection circuit with the write value 108 and a control circuit 109 that controls each unit.
　図１に示した検出器の動作を簡単に説明する。外部からのアドレス指定により、行レコーダ１０２を通して一つの行を選び、また同様に列レコーダ１０３を通して一つの列を選ぶことで、その交点の検出回路１０１が選択される。選択された検出回路１０１に記憶されている値の読み出しと書き込みとは、それぞれ読み出し回路１０４と書き込み回路１０５を通して行われる。試験前にアドレス発生器１０６によりアドレスを変化させながら、書き込み値発生器１０７で発生した値を各検出回路１０１に書き込む。試験後は、アドレス発生器１０６によりアドレスを変化させながら、各検出回路１０１から値を読み出し、書き込み値発生器１０７で書き込んだ値と比較し、一致・不一致で擾乱による一過性のエラーを検出する。 The operation of the detector shown in FIG. 1 will be briefly described. By selecting one row through the row recorder 102 and similarly selecting one column through the column recorder 103 by external addressing, the detection circuit 101 at the intersection is selected. Reading and writing of values stored in the selected detection circuit 101 are performed through the reading circuit 104 and the writing circuit 105, respectively. Before the test, the value generated by the write value generator 107 is written to each detection circuit 101 while changing the address by the address generator 106. After the test, the address generator 106 changes the address, reads the value from each detection circuit 101, compares it with the value written by the write value generator 107, and detects a transient error due to disturbance due to a match / mismatch. To do.
　上述した、メモリを用いた検出方法では、まず、アドレスによりメモリを構成するメモリセルを一つ一つ選択し、ある値を書き込む操作をすべてのメモリセルに対して繰り返す。次に、メモリを試験環境に一定期間さらす。その後、再びアドレスによりメモリを構成するメモリセルを一つ一つ選択し、記憶されている値を読み出す操作をすべてのメモリセルに対して繰り返す。このようなメモリセルの選択を繰り返す操作が必要であるため、そのための時間がかかってしまう。また、メモリセルを選択するためのアドレスデコーダなどの付加回路が必要である。 In the above-described detection method using a memory, first, each memory cell constituting the memory is selected one by one by address, and an operation of writing a certain value is repeated for all the memory cells. The memory is then exposed to the test environment for a period of time. Thereafter, the memory cells constituting the memory are selected one by one again by the address, and the operation of reading the stored value is repeated for all the memory cells. Since it is necessary to repeat the selection of such memory cells, it takes time to do so. Further, an additional circuit such as an address decoder for selecting a memory cell is required.
　本発明の目的の一例は、メモリを用いずに擾乱発生を容易に検出することを可能にした擾乱検出回路、半導体集積回路、擾乱検出方法、および擾乱検出回路の試験方法を提供することである。 An example of an object of the present invention is to provide a disturbance detection circuit, a semiconductor integrated circuit, a disturbance detection method, and a test method for the disturbance detection circuit that can easily detect the occurrence of a disturbance without using a memory. .
　本発明の一側面の擾乱検出回路は、自回路内の擾乱の発生により出力の論理値を変化させ、かつ、前段からの入力の論理値の変化によって後段への出力の論理値を変化させる複数の擾乱検出論理ゲートが直列に接続された系を有し、複数の擾乱検出論理ゲートのうち最初の段の擾乱検出論理ゲートに一定の論理値が入力され、複数の擾乱検出論理ゲートのうち最終の段の擾乱検出論理ゲートの出力の論理値の変化により擾乱の発生が検出される構成である。 A disturbance detection circuit according to one aspect of the present invention is configured to change a logical value of an output by occurrence of a disturbance in its own circuit, and to change a logical value of an output to a subsequent stage by changing a logical value of an input from the previous stage. The disturbance detection logic gates of the plurality of disturbance detection logic gates are connected in series, and a constant logic value is input to the first stage of the disturbance detection logic gates among the plurality of disturbance detection logic gates. The occurrence of the disturbance is detected by the change in the logic value of the output of the disturbance detection logic gate in the second stage.
　また、本発明の一側面の半導体集積回路は、上記擾乱検出回路を有する構成である。 Also, a semiconductor integrated circuit according to one aspect of the present invention has the above-described disturbance detection circuit.
　また、本発明の一側面の擾乱検出方法は、初期化信号により上記擾乱検出回路が初期化された後に擾乱検出動作を開始させるものである。 The disturbance detection method according to one aspect of the present invention starts the disturbance detection operation after the disturbance detection circuit is initialized by the initialization signal.
　さらに、本発明の一側面の擾乱検出回路の試験方法は、試験信号により、擾乱の発生がなくても上記擾乱検出回路の検出動作を試験するものである。 Furthermore, the test method for the disturbance detection circuit according to one aspect of the present invention tests the detection operation of the disturbance detection circuit by a test signal even if no disturbance occurs.
図１は、メモリを用いた、擾乱による一過性のエラーを検出する検出器の一構成例を示す図である。FIG. 1 is a diagram illustrating a configuration example of a detector that detects a transient error due to a disturbance using a memory. 図２は第１の実施形態の擾乱検出回路の一構成例を示すブロック図である。FIG. 2 is a block diagram illustrating a configuration example of the disturbance detection circuit according to the first embodiment. 図３は第１の実施形態の擾乱検出回路の動作を示すタイミング図である。FIG. 3 is a timing chart showing the operation of the disturbance detection circuit according to the first embodiment. 図４は第２の実施形態の擾乱検出回路の一構成例を示すブロック図である。FIG. 4 is a block diagram illustrating a configuration example of the disturbance detection circuit according to the second embodiment. 図５は第２の実施形態の擾乱検出回路の動作を示すタイミング図である。FIG. 5 is a timing chart showing the operation of the disturbance detection circuit according to the second embodiment. 図６は第３の実施形態の擾乱検出回路の一構成例を示すブロック図である。FIG. 6 is a block diagram illustrating a configuration example of the disturbance detection circuit according to the third embodiment. 図７は第３の実施形態の擾乱検出回路の動作を示すタイミング図である。FIG. 7 is a timing chart showing the operation of the disturbance detection circuit according to the third embodiment. 図８は第４の実施形態の擾乱検出回路の一構成例を示すブロック図である。FIG. 8 is a block diagram illustrating a configuration example of the disturbance detection circuit according to the fourth embodiment. 図９は第５の実施形態の擾乱検出回路の一構成例を示すブロック図である。FIG. 9 is a block diagram illustrating a configuration example of the disturbance detection circuit according to the fifth embodiment. 図１０は第６の実施形態の擾乱検出回路の一構成例を示すブロック図である。FIG. 10 is a block diagram illustrating a configuration example of the disturbance detection circuit according to the sixth embodiment. 図１１は第７の実施形態の擾乱検出回路の一構成例を示すブロック図である。FIG. 11 is a block diagram illustrating a configuration example of the disturbance detection circuit according to the seventh embodiment. 図１２は第８の実施形態の擾乱検出回路の一構成例を示すブロック図である。FIG. 12 is a block diagram illustrating a configuration example of the disturbance detection circuit according to the eighth embodiment. 図１３は第９の実施形態の擾乱検出論理ゲートの一構成例を示す回路図である。FIG. 13 is a circuit diagram showing a configuration example of the disturbance detection logic gate according to the ninth embodiment. 図１４は第９の実施形態の擾乱検出論理ゲートの動作を示すタイミング図である。FIG. 14 is a timing chart showing the operation of the disturbance detection logic gate according to the ninth embodiment. 図１５は第９の実施形態の擾乱検出論理ゲートの別の動作を示すタイミング図である。FIG. 15 is a timing chart showing another operation of the disturbance detection logic gate according to the ninth embodiment. 図１６は第１０の実施形態の擾乱検出論理ゲートの一構成例を示す回路図である。FIG. 16 is a circuit diagram showing an example of the configuration of the disturbance detection logic gate of the tenth embodiment. 図１７は第１１の実施形態の擾乱検出論理ゲートの一構成例を示す回路図である。FIG. 17 is a circuit diagram showing a configuration example of the disturbance detection logic gate of the eleventh embodiment. 図１８は第１２の実施形態の擾乱検出論理ゲートの一構成例を示す回路図である。FIG. 18 is a circuit diagram showing a configuration example of the disturbance detection logic gate of the twelfth embodiment. 図１９は第１３の実施形態の擾乱検出論理ゲートの一構成例を示す回路図である。FIG. 19 is a circuit diagram showing one configuration example of the disturbance detection logic gate of the thirteenth embodiment.
　（第１の実施形態）
　本実施形態の擾乱検出回路の構成を図面に基づいて詳細に説明する。図２は本実施形態の擾乱検出回路の一構成例を示すブロック図である。 (First embodiment)
The configuration of the disturbance detection circuit of this embodiment will be described in detail with reference to the drawings. FIG. 2 is a block diagram showing a configuration example of the disturbance detection circuit of the present embodiment.
　本実施形態の擾乱検出回路は、複数の擾乱検出論理ゲートG1～Gnを有する。図２を参照すると、第１の擾乱検出論理ゲートG1の出力線が第２の擾乱検出論理ゲートG2に接続され、第２の擾乱検出論理ゲートG2の出力線が第３の擾乱検出論理ゲートG3に接続され、以下、同様の構造を繰り返し、第ｎ－１の擾乱検出論理ゲートGn-1の出力線が第ｎの擾乱検出論理ゲートGnに接続されている。第ｎの擾乱検出論理ゲートGnの出力（OUT）は擾乱検出回路の出力線201から送出される。ただし、ｎは２以上の整数である。また、他の擾乱検出論理ゲートに接続されない擾乱検出論理ゲートG1の入力は、ある論理値に固定され、一定である。 The disturbance detection circuit of the present embodiment has a plurality of disturbance detection logic gates G1 to Gn. Referring to FIG. 2, the output line of the first disturbance detection logic gate G1 is connected to the second disturbance detection logic gate G2, and the output line of the second disturbance detection logic gate G2 is connected to the third disturbance detection logic gate G3. Thereafter, the same structure is repeated, and the output line of the (n-1) th disturbance detection logic gate Gn-1 is connected to the nth disturbance detection logic gate Gn. The output (OUT) of the nth disturbance detection logic gate Gn is sent from the output line 201 of the disturbance detection circuit. However, n is an integer of 2 or more. The input of the disturbance detection logic gate G1 that is not connected to other disturbance detection logic gates is fixed to a certain logic value and is constant.
　なお、各擾乱検出論理ゲートは、前段の擾乱検出論理ゲートの出力以外にも入力が考えられることから、図２には、前段からの入力を示す矢印以外の入力も矢印で表現している。図２では、前段以外からの入力数は、擾乱検出論理ゲートG2が２つ、擾乱検出論理ゲートG3が１つなどの場合を示しているが、入力数はこの図の場合に限らない。このことは、図４および図６に示す矢印についても同様である。 Since each disturbance detection logic gate can be input in addition to the output of the previous-stage disturbance detection logic gate, in FIG. 2, inputs other than the arrow indicating the input from the previous stage are also represented by arrows. In FIG. 2, the number of inputs from other than the previous stage shows a case where there are two disturbance detection logic gates G2 and one disturbance detection logic gate G3, but the number of inputs is not limited to this figure. The same applies to the arrows shown in FIGS. 4 and 6.
　擾乱検出論理ゲートG1～Gnは、擾乱の発生により出力の論理値を変化させ、また、入力の論理値が変化すると出力の論理値を変化させる。論理値は、例えば、１または０である。擾乱検出論理ゲートG1～Gnの具体的な構成例は他の実施形態で説明する。 The disturbance detection logic gates G1 to Gn change the output logic value due to the occurrence of the disturbance, and change the output logic value when the input logic value changes. The logical value is, for example, 1 or 0. A specific configuration example of the disturbance detection logic gates G1 to Gn will be described in another embodiment.
　次に、本実施形態の擾乱検出回路の動作を説明する。図３は本実施形態の擾乱検出回路の動作を示すタイミング図である。 Next, the operation of the disturbance detection circuit of this embodiment will be described. FIG. 3 is a timing chart showing the operation of the disturbance detection circuit of this embodiment.
　図３を参照すると、擾乱によって一過性のエラーが発生した第１の擾乱検出論理ゲートG1の出力値の変化が第２の擾乱検出論理ゲートG2の出力値を変化させ、これが第３の擾乱検出論理ゲートG3の出力値を変化させ、以下、同様の変化を繰り返し、第ｎ－１の擾乱検出論理ゲートGn-1の出力値を変化させ、第ｎの擾乱検出論理ゲートGnの出力である、擾乱検出回路の出力線201の出力（OUT）の論理値を変化させる。擾乱検出回路の出力の変化により、擾乱検出論理ゲートのいずれかで発生した擾乱による一過性のエラーを直ちに検出可能である。 Referring to FIG. 3, the change in the output value of the first disturbance detection logic gate G1 in which a transient error has occurred due to the disturbance changes the output value of the second disturbance detection logic gate G2, which is the third disturbance. The output value of the detection logic gate G3 is changed, and thereafter, the same change is repeated to change the output value of the (n-1) th disturbance detection logic gate Gn-1, which is the output of the nth disturbance detection logic gate Gn. The logic value of the output (OUT) of the output line 201 of the disturbance detection circuit is changed. Due to the change in the output of the disturbance detection circuit, it is possible to immediately detect a transient error due to the disturbance generated in one of the disturbance detection logic gates.
　（第２の実施形態）
　本実施形態の擾乱検出回路は、第１の実施形態で説明した擾乱検出回路が２系統並列に設けられた構成である。 (Second Embodiment)
The disturbance detection circuit of this embodiment has a configuration in which the disturbance detection circuit described in the first embodiment is provided in parallel in two systems.
　本実施形態の擾乱検出回路の構成を説明する。図４は本実施形態の擾乱検出回路の一構成例を示すブロック図である。本実施形態の擾乱検出回路は、複数の擾乱検出論理ゲートG11～G1n，G21～G2nを有する。 The configuration of the disturbance detection circuit of this embodiment will be described. FIG. 4 is a block diagram illustrating a configuration example of the disturbance detection circuit according to the present embodiment. The disturbance detection circuit of this embodiment includes a plurality of disturbance detection logic gates G11 to G1n and G21 to G2n.
　図４を参照すると、一つの系統の第１１の擾乱検出論理ゲートG11の出力線が第１２の擾乱検出論理ゲートG12に接続され、第１２の擾乱検出論理ゲートG12の出力線が第１３の擾乱検出論理ゲートG13に接続され、以下、同様の構造を繰り返し、第１ｎ－１の擾乱検出論理ゲートG1n-1の出力線が第１ｎの擾乱検出論理ゲートG1nに接続されている。第１ｎの擾乱検出論理ゲートG1nの出力（OUT1）は擾乱検出回路の出力線211から送出される。 Referring to FIG. 4, the output line of the eleventh disturbance detection logic gate G11 of one system is connected to the twelfth disturbance detection logic gate G12, and the output line of the twelfth disturbance detection logic gate G12 is the thirteenth disturbance. The same structure is repeated thereafter, and the output line of the 1n-1th disturbance detection logic gate G1n-1 is connected to the 1nth disturbance detection logic gate G1n. The output (OUT1) of the 1nth disturbance detection logic gate G1n is sent from the output line 211 of the disturbance detection circuit.
　第１１の擾乱検出論理ゲートG11の直後に第１２の擾乱検出論理ゲートG12が配置され、第１２の擾乱検出論理ゲートG12の直後に第１３の擾乱検出論理ゲートG13が配置され、以下、同様の配置を繰り返し、第１ｎ－１の擾乱検出論理ゲートG1n-1の直後に第１ｎの擾乱検出論理ゲートG1nが配置されている。 A twelfth disturbance detection logic gate G12 is arranged immediately after the eleventh disturbance detection logic gate G11, a thirteenth disturbance detection logic gate G13 is arranged immediately after the twelfth disturbance detection logic gate G12, and so on. The arrangement is repeated, and the 1nth disturbance detection logic gate G1n is arranged immediately after the 1n-1th disturbance detection logic gate G1n-1.
　これと同様に独立した別の系統の第２１の擾乱検出論理ゲートG21の出力線が第２２の擾乱検出論理ゲートG22に接続され、第２２の擾乱検出論理ゲートG22の出力線が第２３の擾乱検出論理ゲートG23に接続され、以下、同様の構造を繰り返し、第２ｎ－１の擾乱検出論理ゲートG2n-1の出力線が第２ｎの擾乱検出論理ゲートG2nに接続されている。第２ｎの擾乱検出論理ゲートG2nの出力（OUT2）は擾乱検出回路の出力線212から送出される。 Similarly, the output line of the 21st disturbance detection logic gate G21 of another independent system is connected to the 22nd disturbance detection logic gate G22, and the output line of the 22nd disturbance detection logic gate G22 is connected to the 23rd disturbance. Thereafter, the same structure is repeated, and the output line of the 2n-1th disturbance detection logic gate G2n-1 is connected to the 2nth disturbance detection logic gate G2n. The output (OUT2) of the 2nth disturbance detection logic gate G2n is sent from the output line 212 of the disturbance detection circuit.
　第２１の擾乱検出論理ゲートG21の直後に第２２の擾乱検出論理ゲートG22が配置され、第２２の擾乱検出論理ゲートG22の直後に第２３の擾乱検出論理ゲートG23が配置され、以下、同様の配置を繰り返し、第２ｎ－１の擾乱検出論理ゲートG2n-1の直後に第２ｎの擾乱検出論理ゲートG2nが配置されている。 The twenty-second disturbance detection logic gate G22 is arranged immediately after the twenty-first disturbance detection logic gate G21, the twenty-third disturbance detection logic gate G23 is arranged immediately after the twenty-second disturbance detection logic gate G22, and so on. The arrangement is repeated, and a 2nth disturbance detection logic gate G2n is arranged immediately after the 2n-1th disturbance detection logic gate G2n-1.
　次に、本実施形態の擾乱検出回路の動作を説明する。図５は本実施形態の擾乱検出回路の動作を示すタイミング図である。 Next, the operation of the disturbance detection circuit of this embodiment will be described. FIG. 5 is a timing chart showing the operation of the disturbance detection circuit of this embodiment.
　図５を参照すると、擾乱によって一過性のエラーが発生した第１１の擾乱検出論理ゲートG11の出力値の変化が第１２の擾乱検出論理ゲートG12の出力値を変化させ、これが第１３の擾乱検出論理ゲートG13の出力値を変化させ、以下、同様の変化を繰り返し、第１ｎ－１の擾乱検出論理ゲートG1n-1の出力値を変化させ、第１ｎの擾乱検出論理ゲートG1nの出力となる、擾乱検出回路の出力線211の出力（OUT1）の論理値を変化させる。 Referring to FIG. 5, the change in the output value of the eleventh disturbance detection logic gate G11 in which a transient error has occurred due to the disturbance changes the output value of the twelfth disturbance detection logic gate G12, which is the thirteenth disturbance. The output value of the detection logic gate G13 is changed. Thereafter, the same change is repeated, and the output value of the 1n-1th disturbance detection logic gate G1n-1 is changed to become the output of the 1nth disturbance detection logic gate G1n. The logic value of the output (OUT1) of the output line 211 of the disturbance detection circuit is changed.
　原因が同じ擾乱によって一過性のエラーが発生した第２１の擾乱検出論理ゲートG21の出力値の変化が第２２の擾乱検出論理ゲートG22の出力値を変化させ、これが第２３の擾乱検出論理ゲートG23の出力値を変化させ、以下、同様の変化を繰り返し、第２ｎ－１の擾乱検出論理ゲートG2n-1の出力値を変化させ、第２ｎの擾乱検出論理ゲートG2nの出力である、擾乱検出回路の出力線212の出力(OUT2)の論理値を変化させる。 A change in the output value of the twenty-first disturbance detection logic gate G21 in which a transient error has occurred due to the same disturbance causes a change in the output value of the twenty-second disturbance detection logic gate G22, which is the twenty-third disturbance detection logic gate. The output value of G23 is changed, and thereafter, the same change is repeated, and the output value of the 2n-1th disturbance detection logic gate G2n-1 is changed to output the 2nth disturbance detection logic gate G2n. The logic value of the output (OUT2) of the output line 212 of the circuit is changed.
　このようにして、二つの擾乱検出回路の出力線の出力値（OUT1,　OUT2）が共に変化したことで、一つの擾乱によって、上下に隣接する二つの擾乱検出論理ゲートに擾乱による一過性のエラーが発生したことを検出できる。すなわち、本実施形態では、一つの擾乱で二つのビットに発生する一過性のエラーを検出できる。 In this way, since the output values (OUT1, OUT2) of the output lines of the two disturbance detection circuits have both changed, one disturbance causes two transient detection logic gates adjacent to each other to be transiently affected by the disturbance. Can detect that an error has occurred. That is, in the present embodiment, it is possible to detect a transient error that occurs in two bits in one disturbance.
　（第３の実施形態）
　本実施形態の擾乱検出回路は、第２の実施形態とは異なる構成で２系統設けられたものである。 (Third embodiment)
The disturbance detection circuit of the present embodiment is provided with two systems with a configuration different from that of the second embodiment.
　本実施形態の擾乱検出回路の構成を説明する。図６は本実施形態の擾乱検出回路の一構成例を示すブロック図である。 The configuration of the disturbance detection circuit of this embodiment will be described. FIG. 6 is a block diagram showing a configuration example of the disturbance detection circuit of the present embodiment.
　図６を参照すると、擾乱検出論理ゲート間の接続は第２の実施形態と同様である。第1１の擾乱検出論理ゲートG11の直後に第２２の擾乱検出論理ゲートG22が配置され、第２２の擾乱検出論理ゲートG22の直後に第１３の擾乱検出論理ゲートG13が配置され、以下、同様の配置を繰り返し、第２ｎ－１の擾乱検出論理ゲートG2n-1の直後に第１ｎの擾乱検出論理ゲートG1nが配置されている。 Referring to FIG. 6, the connection between the disturbance detection logic gates is the same as in the second embodiment. The 22nd disturbance detection logic gate G22 is arranged immediately after the 11th disturbance detection logic gate G11, the 13th disturbance detection logic gate G13 is arranged immediately after the 22nd disturbance detection logic gate G22, and so on. The arrangement is repeated, and the 1nth disturbance detection logic gate G1n is arranged immediately after the 2n-1th disturbance detection logic gate G2n-1.
　また、第２１の擾乱検出論理ゲートG21の直後に第１２の擾乱検出論理ゲートG12が配置され、第１２の擾乱検出論理ゲートG12の直後に第２３の擾乱検出論理ゲートG23が配置され、以下、同様の配置を繰り返し、第１ｎ－１の擾乱検出論理ゲートG1n-1の直後に第２ｎの擾乱検出論理ゲートG2nが配置されている。 A twelfth disturbance detection logic gate G12 is arranged immediately after the twenty-first disturbance detection logic gate G21, a twenty-third disturbance detection logic gate G23 is arranged immediately after the twelfth disturbance detection logic gate G12, and The same arrangement is repeated, and the 2nth disturbance detection logic gate G2n is arranged immediately after the 1n-1th disturbance detection logic gate G1n-1.
　上述のように配置されているが、図６に示すように、擾乱検出論理ゲートG11～G1n，G21～G2nのそれぞれの接続は第２の実施形態と同様である。例えば、第１１の擾乱検出論理ゲートG11の出力線が第１２の擾乱検出論理ゲートG12に接続され、第１２の擾乱検出論理ゲートG12の出力線が第１３の擾乱検出論理ゲートG13に接続されている。 Although arranged as described above, as shown in FIG. 6, the connections of the disturbance detection logic gates G11 to G1n and G21 to G2n are the same as in the second embodiment. For example, the output line of the eleventh disturbance detection logic gate G11 is connected to the twelfth disturbance detection logic gate G12, and the output line of the twelfth disturbance detection logic gate G12 is connected to the thirteenth disturbance detection logic gate G13. Yes.
　次に、本実施形態の擾乱検出回路の動作を説明する。図７は本実施形態の擾乱検出回路の動作を示すタイミング図である。 Next, the operation of the disturbance detection circuit of this embodiment will be described. FIG. 7 is a timing chart showing the operation of the disturbance detection circuit of this embodiment.
　図７を参照すると、擾乱によって一過性のエラーが発生した第１１の擾乱検出論理ゲートG11の出力値の変化が第１２の擾乱検出論理ゲートG12の出力値を変化させ、これが第１３の擾乱検出論理ゲートG13の出力値を変化させ、以下、同様の変化を繰り返し、第１ｎ－１の擾乱検出論理ゲートG1n-1の出力値を変化させ、第１ｎの擾乱検出論理ゲートG1nの出力である、擾乱検出回路の出力線211の出力(OUT1)の論理値を変化させる。 Referring to FIG. 7, the change in the output value of the eleventh disturbance detection logic gate G11 in which a transient error has occurred due to the disturbance changes the output value of the twelfth disturbance detection logic gate G12, which is the thirteenth disturbance. The output value of the detection logic gate G13 is changed. Thereafter, the same change is repeated, and the output value of the 1n-1th disturbance detection logic gate G1n-1 is changed to be the output of the 1nth disturbance detection logic gate G1n. The logic value of the output (OUT1) of the output line 211 of the disturbance detection circuit is changed.
　原因が同じ擾乱によって一過性のエラーが発生した第２２の擾乱検出論理ゲートG22の出力値の変化が第２３の擾乱検出論理ゲートG23の出力値を変化させ、以下、同様の変化を繰り返し、第２ｎ－１の擾乱検出論理ゲートG2n-1の出力値を変化させ、第２ｎの擾乱検出論理ゲートG2nの出力である、擾乱検出回路の出力線212の出力(OUT2)の論理値を変化させる。 A change in the output value of the 22nd disturbance detection logic gate G22 in which a transient error has occurred due to the same disturbance causes a change in the output value of the 23rd disturbance detection logic gate G23. The output value of the 2n-1th disturbance detection logic gate G2n-1 is changed, and the logic value of the output (OUT2) of the output line 212 of the disturbance detection circuit, which is the output of the 2nth disturbance detection logic gate G2n, is changed. .
　このようにして、二つの擾乱検出回路の出力線の出力値（OUT1,　OUT2）が共に変化したことで、一つの擾乱によって、前後に隣接する二つの擾乱検出論理ゲートに一過性のエラーが発生したことを検出できる。また、本実施形態では、第２の実施形態と同様に上下に隣接する二つの擾乱検出論理ゲートに一過性のエラーが発生したことも検出できる。 In this way, because the output values (OUT1, OUT2) of the output lines of the two disturbance detection circuits have both changed, one disturbance causes a transient error in the two adjacent disturbance detection logic gates. You can detect what happened. In this embodiment, it is also possible to detect that a transient error has occurred in two disturbance detection logic gates adjacent in the vertical direction as in the second embodiment.
　（第４の実施形態）
　本実施形態の擾乱検出回路は、直列に接続された複数の擾乱検出回路のうちいずれか１つの出力を選択する構成である。 (Fourth embodiment)
The disturbance detection circuit of this embodiment is configured to select any one output from among a plurality of disturbance detection circuits connected in series.
　本実施形態の擾乱検出回路の構成を説明する。図８は本実施形態の擾乱検出回路の一構成例を示すブロック図である。本実施形態の擾乱検出回路は、複数の擾乱検出回路SG1～SGnと、出力選択回路S1とを有する。擾乱検出回路SG1～SGnは、第１から第３の実施形態の擾乱検出回路のいずれかである。 The configuration of the disturbance detection circuit of this embodiment will be described. FIG. 8 is a block diagram illustrating a configuration example of the disturbance detection circuit according to the present embodiment. The disturbance detection circuit of this embodiment has a plurality of disturbance detection circuits SG1 to SGn and an output selection circuit S1. The disturbance detection circuits SG1 to SGn are any of the disturbance detection circuits of the first to third embodiments.
　図８を参照すると、第１の擾乱検出回路SG1の出力線が第２の擾乱検出回路SG2と出力選択回路S1に接続され、第２の擾乱検出回路SG2の出力線が第３の擾乱検出回路SG3と出力選択回路S1に接続され、以下同様にして、第ｎの擾乱検出回路(SGn)の出力線が出力選択回路Snに接続されている。 Referring to FIG. 8, the output line of the first disturbance detection circuit SG1 is connected to the second disturbance detection circuit SG2 and the output selection circuit S1, and the output line of the second disturbance detection circuit SG2 is connected to the third disturbance detection circuit. SG3 is connected to the output selection circuit S1, and in the same manner, the output line of the nth disturbance detection circuit (SGn) is connected to the output selection circuit Sn.
　上述の構成により、第１の擾乱検出回路SG1の出力が第２の擾乱検出回路SG2と出力選択回路S1に入力され、第２の擾乱検出回路SG2の出力が第３の擾乱検出回路SG3と出力選択回路S1に入力され、以下同様にして、第ｎの擾乱検出回路SGnの出力が出力選択回路Snに入力され、出力選択回路Snの出力が擾乱検出回路の出力線221の出力(OUT)となる。 With the configuration described above, the output of the first disturbance detection circuit SG1 is input to the second disturbance detection circuit SG2 and the output selection circuit S1, and the output of the second disturbance detection circuit SG2 is output to the third disturbance detection circuit SG3. In the same manner, the output of the nth disturbance detection circuit SGn is input to the output selection circuit Sn, and the output of the output selection circuit Sn is connected to the output (OUT) of the output line 221 of the disturbance detection circuit. Become.
　出力選択回路S1は、第１から第ｎの擾乱検出回路のうち一つを指定する旨の制御信号の入力があると、指定された擾乱検出回路の出力を選択して出力線221から送出する。 When there is an input of a control signal for designating one of the first to nth disturbance detection circuits, the output selection circuit S1 selects the output of the designated disturbance detection circuit and sends it out from the output line 221. .
　本実施形態の擾乱検出回路の動作を簡単に説明する。出力選択回路S1は、第ｉ（ｉは１からｎの整数）の擾乱検出回路SGiを指定する旨の制御信号の入力があると、第ｉの擾乱検出回路SGiからの入力値を出力する。 The operation of the disturbance detection circuit of this embodiment will be briefly described. When there is an input of a control signal for designating the i-th (i is an integer from 1 to n) disturbance detection circuit SGi, the output selection circuit S1 outputs an input value from the i-th disturbance detection circuit SGi.
　本実施形態では、第ｉの擾乱検出回路SGiの出力を選択した場合、第１の擾乱検出回路SG1から第ｉの擾乱検出回路SGiのいずれかで発生した擾乱による一過性のエラーを検出できる。すなわち、ｉの値が大きいほど検出感度が高く、出力選択回路S1で検出感度を変えることができる。 In the present embodiment, when the output of the i-th disturbance detection circuit SGi is selected, a transient error due to the disturbance generated in any of the first disturbance detection circuit SG1 to the i-th disturbance detection circuit SGi can be detected. . That is, the larger the value of i, the higher the detection sensitivity, and the detection sensitivity can be changed by the output selection circuit S1.
　（第５の実施形態）
　本実施形態の擾乱検出回路は、擾乱検出回路の検出を出力制御回路を介して出力する構成である。 (Fifth embodiment)
The disturbance detection circuit of the present embodiment is configured to output the detection of the disturbance detection circuit via an output control circuit.
　本実施形態の擾乱検出回路の構成を説明する。図９は本実施形態の擾乱検出回路の一構成例を示すブロック図である。本実施形態の擾乱検出回路は、複数の擾乱検出回路SG1～SGnと、出力制御回路OC1～OCnと、併合回路M1とを有する。擾乱検出回路SG1～SGnは、第１から第３の実施形態の擾乱検出回路のいずれかである。 The configuration of the disturbance detection circuit of this embodiment will be described. FIG. 9 is a block diagram showing a configuration example of the disturbance detection circuit of the present embodiment. The disturbance detection circuit of this embodiment includes a plurality of disturbance detection circuits SG1 to SGn, output control circuits OC1 to OCn, and a merge circuit M1. The disturbance detection circuits SG1 to SGn are any of the disturbance detection circuits of the first to third embodiments.
　図９を参照すると、第１の擾乱検出回路SG1の出力線が第１の出力制御回路OC1に接続され、第１の出力制御回路OC1の出力線が併合回路M1に接続されている。また、第２の擾乱検出回路SG2の出力線が第２の出力制御回路OC2に接続され、第２の出力制御回路OC2の出力線が併合回路M1に接続されている。以下同様にして、第ｎの擾乱検出回路SGnの出力線が第ｎの出力制御回路OCnに接続され、第ｎの出力制御回路OCnの出力線が併合回路M1に接続されている。 Referring to FIG. 9, the output line of the first disturbance detection circuit SG1 is connected to the first output control circuit OC1, and the output line of the first output control circuit OC1 is connected to the merge circuit M1. Further, the output line of the second disturbance detection circuit SG2 is connected to the second output control circuit OC2, and the output line of the second output control circuit OC2 is connected to the merging circuit M1. Similarly, the output line of the nth disturbance detection circuit SGn is connected to the nth output control circuit OCn, and the output line of the nth output control circuit OCn is connected to the merging circuit M1.
　上述の構成により、第１の擾乱検出回路SG1の出力が第１の出力制御回路OC1に入力され、第１の出力制御回路OC1の出力が併合回路M1に入力される。また、第２の擾乱検出回路SG2の出力が第２の出力制御回路OC2に入力され、第２の出力制御回路OC2の出力が併合回路M1に入力される。以下同様にして、第ｎの擾乱検出回路SGnの出力が第ｎの出力制御回路OCnに入力され、第ｎの出力制御回路OCnの出力が併合回路M1に入力される。併合回路M1の出力が、本実施形態の擾乱検出回路の出力線222の出力(OUT)となる。 With the configuration described above, the output of the first disturbance detection circuit SG1 is input to the first output control circuit OC1, and the output of the first output control circuit OC1 is input to the merge circuit M1. Further, the output of the second disturbance detection circuit SG2 is input to the second output control circuit OC2, and the output of the second output control circuit OC2 is input to the merging circuit M1. Similarly, the output of the nth disturbance detection circuit SGn is input to the nth output control circuit OCn, and the output of the nth output control circuit OCn is input to the merging circuit M1. The output of the merging circuit M1 becomes the output (OUT) of the output line 222 of the disturbance detection circuit of this embodiment.
　出力制御回路OC1,　OC2,　...,　OCnのそれぞれは、制御信号の入力があると、擾乱検出回路SG1～SGnのそれぞれから入力される信号を出力するか否かを切り替える。併合回路M1は、出力制御回路OC1,　OC2,　...,　OCnからの入力のうち少なくとも一つの信号値に変化があった場合、その変化の前と比べて出力値を変化させる。 Output control circuits OC1, OC2,..., OCn each switch whether to output signals input from disturbance detection circuits SG1 to SGn when a control signal is input. When there is a change in at least one signal value among the inputs from the output control circuits OC1, OC2,..., OCn, the merging circuit M1 changes the output value compared to before the change.
　本実施形態の擾乱検出回路の動作を簡単に説明する。複数の擾乱検出回路SG1～SGnのうちいずれかが擾乱を検出すると、その出力の変化が出力制御回路に入力され、併合回路M1は、出力制御回路OC1～OCnのうちいずれかの入力の変化により、出力値を変更する。 The operation of the disturbance detection circuit of this embodiment will be briefly described. When any one of the plurality of disturbance detection circuits SG1 to SGn detects a disturbance, the change in the output is input to the output control circuit, and the merging circuit M1 is caused by the change in any one of the output control circuits OC1 to OCn. Change the output value.
　本実施形態では、複数の擾乱検出回路のいずれかで発生した擾乱による一過性のエラーを出力制御回路を介して検出できる。すなわち、出力制御回路によって接続された擾乱検出回路の数が多いほど検出感度が高く、出力制御回路で検出感度を変えることができる。 In the present embodiment, a transient error due to a disturbance generated in any of a plurality of disturbance detection circuits can be detected via the output control circuit. That is, the greater the number of disturbance detection circuits connected by the output control circuit, the higher the detection sensitivity, and the detection sensitivity can be changed by the output control circuit.
　なお、第４の実施形態の擾乱検出回路を本実施形態の擾乱検出回路（SG1,　SG2,　...,　SGn）として用いることも可能である。また、その反対に、本実施形態の擾乱検出回路を第４の実施形態の擾乱検出回路（SG1,　SG2,　...,　SGn）として用いることも可能である。 Note that the disturbance detection circuit of the fourth embodiment can also be used as the disturbance detection circuit (SG1, SG2,..., SGn) of the present embodiment. On the contrary, the disturbance detection circuit of this embodiment can be used as the disturbance detection circuit (SG1, SG2,..., SGn) of the fourth embodiment.
　（第６の実施形態）
　本実施形態の擾乱検出回路は、擾乱検出回路を初期化可能にした構成である。 (Sixth embodiment)
The disturbance detection circuit of this embodiment has a configuration in which the disturbance detection circuit can be initialized.
　本実施形態の擾乱検出回路の構成を説明する。図１０は本実施形態の擾乱検出回路の一構成例を示すブロック図である。本実施形態の擾乱検出回路は、擾乱検出回路SGと、初期化回路ITCとを有する。擾乱検出回路SGは、第１から第３の実施形態の擾乱検出回路のいずれかに、以下の構成が追加されたものである。 The configuration of the disturbance detection circuit of this embodiment will be described. FIG. 10 is a block diagram illustrating a configuration example of the disturbance detection circuit according to the present embodiment. The disturbance detection circuit of the present embodiment includes a disturbance detection circuit SG and an initialization circuit ITC. The disturbance detection circuit SG is obtained by adding the following configuration to any of the disturbance detection circuits of the first to third embodiments.
　図１０を参照すると、擾乱検出回路SGは、初期化信号を受信するための初期化入力線で初期化回路ITCと接続されている。擾乱検出回路SGは、初期化信号が入力されると初期状態に遷移し、擾乱を検出可能な状態になる。 Referring to FIG. 10, the disturbance detection circuit SG is connected to the initialization circuit ITC via an initialization input line for receiving an initialization signal. The disturbance detection circuit SG transitions to an initial state when an initialization signal is input, and enters a state in which the disturbance can be detected.
　本実施形態では、擾乱検出回路に順序回路が含まれる場合、検出前に初期状態に遷移させることで確定的な動作をさせることができる。擾乱検出回路にドミノ論理回路が含まれている場合、初期化によって自然放電による電荷の放出を補うことができる。なお、初期化回路は定期的に初期化信号を発生し、擾乱検出回路を初期化してもよい。 In this embodiment, when the disturbance detection circuit includes a sequential circuit, a definite operation can be performed by making a transition to the initial state before detection. When the disturbance detection circuit includes a domino logic circuit, the discharge can be compensated for by spontaneous discharge by initialization. Note that the initialization circuit may periodically generate an initialization signal to initialize the disturbance detection circuit.
　（第７の実施形態）
　本実施形態の擾乱検出回路は、第６の実施形態の擾乱検出回路の初期化を擾乱発生時に実行可能にした構成である。 (Seventh embodiment)
The disturbance detection circuit according to the present embodiment has a configuration in which the disturbance detection circuit according to the sixth embodiment can be initialized when a disturbance occurs.
　本実施形態の擾乱検出回路の構成を説明する。図１１は本実施形態の擾乱検出回路の一構成例を示すブロック図である。本実施形態の擾乱検出回路は、第６の実施形態で説明した擾乱検出回路SGと、初期化回路ITCとを有する。 The configuration of the disturbance detection circuit of this embodiment will be described. FIG. 11 is a block diagram showing a configuration example of the disturbance detection circuit of the present embodiment. The disturbance detection circuit according to this embodiment includes the disturbance detection circuit SG described in the sixth embodiment and an initialization circuit ITC.
　図１１を参照すると、擾乱検出回路SGは、第６の実施形態と同様に初期化回路ITCと接続されているだけでなく、その出力線が初期化回路ITCと接続されている。初期化回路ITCは、一過性のエラーの検出によって初期化信号を発生する。これにより、擾乱による一過性のエラーの検出を繰り返し行うことができる。 Referring to FIG. 11, the disturbance detection circuit SG is not only connected to the initialization circuit ITC as in the sixth embodiment, but also its output line is connected to the initialization circuit ITC. The initialization circuit ITC generates an initialization signal upon detection of a transient error. This makes it possible to repeatedly detect a transient error due to disturbance.
　（第８の実施形態）
　本実施形態の擾乱検出回路は、第６または第７の実施形態の擾乱検出回路の出力の論理値の変化に所定の演算を実行するものである。 (Eighth embodiment)
The disturbance detection circuit according to the present embodiment performs a predetermined operation on the change in the logical value of the output of the disturbance detection circuit according to the sixth or seventh embodiment.
　本実施形態の擾乱検出回路の構成を説明する。図１２は本実施形態の擾乱検出回路の一構成例を示すブロック図である。本実施形態の擾乱検出回路は、第７の実施形態で説明した擾乱検出回路SGおよび初期化回路ITCと、出力処理回路OPとを有する。 The configuration of the disturbance detection circuit of this embodiment will be described. FIG. 12 is a block diagram showing a configuration example of the disturbance detection circuit of the present embodiment. The disturbance detection circuit of the present embodiment includes the disturbance detection circuit SG and the initialization circuit ITC described in the seventh embodiment, and an output processing circuit OP.
　図１２を参照すると、第７の実施形態で説明した構成で、擾乱検出回路SGの出力線が出力処理回路OPに接続されている。出力処理回路OPは、擾乱検出回路SGの出力値の変化を計測する計測器としての機能を有し、発生した一過性のエラーの数をカウントする。 Referring to FIG. 12, in the configuration described in the seventh embodiment, the output line of the disturbance detection circuit SG is connected to the output processing circuit OP. The output processing circuit OP has a function as a measuring instrument that measures a change in the output value of the disturbance detection circuit SG, and counts the number of transient errors that have occurred.
　本実施形態では、出力処理回路が一定時間の一過性のエラーの数を計測することで単位時間当たりの擾乱発生数を計測することができる。 In the present embodiment, the number of disturbances generated per unit time can be measured by the output processing circuit measuring the number of transient errors for a certain period of time.
　また、出力処理回路OPは、擾乱検出回路SGの出力変化のサンプリング機能を有していてもよい。一過性のエラーであって、直ちに出力値が元の値に戻るエラーは、出力値がエラーとなっている間に記憶されない限り、悪影響を及ぼさない。出力処理回路OPが同期式論理回路であれば、同期式論理回路のクロック信号はサンプリングの作用をし、クロック周波数が高くなるほどサンプリングする頻度が高くなるため、エラー出力を記憶する確率が高まる。サンプリングにより、同期式論理回路で実際に悪影響を及ぼす擾乱による一過性のエラーを評価することができる。 Further, the output processing circuit OP may have a function of sampling the output change of the disturbance detection circuit SG. A transient error that immediately returns the output value to the original value will not have an adverse effect unless it is stored while the output value is in error. If the output processing circuit OP is a synchronous logic circuit, the clock signal of the synchronous logic circuit performs a sampling operation, and the higher the clock frequency, the higher the frequency of sampling, thus increasing the probability of storing an error output. Sampling makes it possible to evaluate transient errors due to disturbances that actually have an adverse effect on the synchronous logic circuit.
　（第９の実施形態）
　本実施形態は、第１から第３の実施形態のいずれかの擾乱検出回路に適用可能な擾乱検出論理ゲートの一構成例である。 (Ninth embodiment)
This embodiment is a configuration example of a disturbance detection logic gate applicable to the disturbance detection circuit according to any one of the first to third embodiments.
　図１３は本実施形態の擾乱検出論理ゲートの一構成例を示す回路図である。図１３を参照すると、本実施形態の擾乱検出論理ゲートは、第１および第２のＰＭＯＳトランジスタP1,　P2と、第１および第２のＮＭＯＳトランジスタN1,　N2とを有する。以下では、Ｐ基板またはＰウェル拡散層を総称してＰ基板とし、Ｎ基板またはＮウェル拡散層を総称してＮ基板とする。 FIG. 13 is a circuit diagram showing a configuration example of the disturbance detection logic gate of the present embodiment. Referring to FIG. 13, the disturbance detection logic gate of the present embodiment includes first and second PMOS transistors P1, P2, and first and second NMOS transistors N1, N2. Hereinafter, the P substrate or P well diffusion layer is generically referred to as a P substrate, and the N substrate or N well diffusion layer is generically referred to as an N substrate.
　図１３に示すように、第１および第２のＰＭＯＳトランジスタP1,P2のそれぞれのソース電極が電源線VDDに接続され、それぞれの基板電極がＰ基板線PSUBに接続されている。第１および第２のＮＭＯＳトランジスタN1,N2のそれぞれのソース電極が接地線GNDに接続され、それぞれの基板電極がＮ基板線NSUBに接続されている。 As shown in FIG. 13, the source electrodes of the first and second PMOS transistors P1, P2 are connected to the power supply line VDD, and the respective substrate electrodes are connected to the P substrate line PSUB. The source electrodes of the first and second NMOS transistors N1, N2 are connected to the ground line GND, and the respective substrate electrodes are connected to the N substrate line NSUB.
　第１のＰＭＯＳトランジスタP1のゲート電極が否定初期化信号線PCBに接続され、第２のＮＭＯＳトランジスタN2のゲート電極が初期化信号線PCに接続されている。初期化信号線は、擾乱検出論理ゲートを初期化状態に遷移させるための初期化信号を伝送するための信号線である。否定初期化信号線は、初期化信号の反転信号を伝送するための信号線である。 The gate electrode of the first PMOS transistor P1 is connected to the negative initialization signal line PCB, and the gate electrode of the second NMOS transistor N2 is connected to the initialization signal line PC. The initialization signal line is a signal line for transmitting an initialization signal for causing the disturbance detection logic gate to transition to the initialization state. The negative initialization signal line is a signal line for transmitting an inverted signal of the initialization signal.
　第１のＮＭＯＳトランジスタN1のゲート電極が入力線301に接続されている。第２のＰＭＯＳトランジスタP2のゲート電極が第１のＰＭＯＳトランジスタP1のドレイン電極と第１のＮＭＯＳトランジスタN1のドレイン電極とに接続されている。その接続点を図１３に内部ノードXNで示す。第２のＰＭＯＳトランジスタP2のドレイン電極と第２のＮＭＯＳトランジスタN2のドレイン電極とが出力線302に接続されている。 The gate electrode of the first NMOS transistor N1 is connected to the input line 301. The gate electrode of the second PMOS transistor P2 is connected to the drain electrode of the first PMOS transistor P1 and the drain electrode of the first NMOS transistor N1. The connection point is indicated by an internal node XN in FIG. The drain electrode of the second PMOS transistor P2 and the drain electrode of the second NMOS transistor N2 are connected to the output line 302.
　なお、Ｐ基板線PSUBは電源線VDDと同電位に、Ｎ基板線NSUBは接地線GNDと同電位に保つのが望ましいが、必要に応じて電位を変化させてトランジスタの閾値電圧を変えることで擾乱発生確率または擾乱検出感度を変化させてもよい。 The P substrate line PSUB is preferably maintained at the same potential as the power supply line VDD, and the N substrate line NSUB is preferably maintained at the same potential as the ground line GND. However, by changing the potential as necessary, the threshold voltage of the transistor is changed. The disturbance occurrence probability or disturbance detection sensitivity may be changed.
　次に、本実施形態の擾乱検出論理ゲートの動作を説明する。図１４は本実施形態の擾乱検出論理ゲートの動作を示すタイミング図である。 Next, the operation of the disturbance detection logic gate of this embodiment will be described. FIG. 14 is a timing chart showing the operation of the disturbance detection logic gate of this embodiment.
　図１４を参照すると、初期化信号線PCをハイレベルに、否定初期化信号線PCBをローレベルにして初期化を行う。また、入力線301が他の擾乱検出論理ゲートに接続されない場合は、入力線301をローレベルに設定する。初期化によって、内部ノードXNは電荷が蓄積されてハイレベルになり、出力線302は電荷が放出されてローレベルになる。その後、初期化信号線PCをローレベルに、否定初期化信号線PCBをハイレベルにして初期化期間を終了し、検出期間が始まる。 Referring to FIG. 14, initialization is performed by setting the initialization signal line PC to the high level and the negative initialization signal line PCB to the low level. When the input line 301 is not connected to another disturbance detection logic gate, the input line 301 is set to a low level. As a result of the initialization, charges are accumulated in the internal node XN and become the high level, and the output line 302 is discharged and becomes the low level. Thereafter, the initialization signal line PC is set to the low level and the negative initialization signal line PCB is set to the high level to end the initialization period, and the detection period starts.
　検出期間中に擾乱により内部ノードXNの電荷が放出され、内部ノードXNがローレベルになったとする。この結果、第２のＰＭＯＳトランジスタP2がオンし、出力線302が電源線VDDに接続されてハイレベルに変化する。擾乱検出論理ゲートの出力OUTはローレベルからハイレベルに変化する。このようにして、擾乱による一過性のエラーが検出される。 Suppose that the charge of the internal node XN is released due to disturbance during the detection period, and the internal node XN becomes low level. As a result, the second PMOS transistor P2 is turned on, the output line 302 is connected to the power supply line VDD, and changes to the high level. The output OUT of the disturbance detection logic gate changes from low level to high level. In this way, transient errors due to disturbances are detected.
　図１５は、本実施形態の擾乱検出論理ゲートの別の動作を示すタイミング図である。図１５を参照すると、初期化期間に関しては図１４で説明した動作と同様であるため、その詳細な説明を省略する。 FIG. 15 is a timing chart showing another operation of the disturbance detection logic gate of the present embodiment. Referring to FIG. 15, the initialization period is the same as the operation described with reference to FIG.
　検出期間中に擾乱により入力線301に電荷が蓄積され、入力線301がハイレベルになった、あるいは前段の擾乱検出論理ゲートの出力が擾乱の検出によって入力線301がハイレベルになったとする。この結果、第１のＮＭＯＳトランジスタN1がオンし、内部ノードXNが接地線GNDに接続されてローレベルに変化する。このため、内部ノードXNに接続された第２のＰＭＯＳトランジスタP2がオンし、出力線302が電源線VDDに接続されてハイレベルに変化する。擾乱検出論理ゲートの出力OUTはローレベルからハイレベルに変化する。このようにして、擾乱による一過性のエラーが検出され、または、信号変化が伝搬する。 It is assumed that charges are accumulated in the input line 301 due to disturbance during the detection period, and the input line 301 becomes high level, or the output of the disturbance detection logic gate in the previous stage becomes high level due to detection of disturbance. As a result, the first NMOS transistor N1 is turned on, the internal node XN is connected to the ground line GND, and changes to the low level. Therefore, the second PMOS transistor P2 connected to the internal node XN is turned on, and the output line 302 is connected to the power supply line VDD and changes to the high level. The output OUT of the disturbance detection logic gate changes from low level to high level. In this way, transient errors due to disturbances are detected or signal changes propagate.
　なお、入力線301が他の擾乱検出論理ゲートに接続されていない場合、入力線301を試験信号を入力するための試験入力線として使うことが可能である。初期化期間終了後に故意に入力線301をハイレベルにすることで、検出のための擾乱検出論理ゲートが正常に機能するかどうかを試験することができる。 When the input line 301 is not connected to another disturbance detection logic gate, the input line 301 can be used as a test input line for inputting a test signal. By intentionally setting the input line 301 to the high level after the initialization period, it is possible to test whether the disturbance detection logic gate for detection functions normally.
　（第１０の実施形態）
　本実施形態は、擾乱検出論理ゲートの別の構成例である。 (Tenth embodiment)
This embodiment is another configuration example of the disturbance detection logic gate.
　図１６は本実施形態の擾乱検出論理ゲートの一構成例を示す回路図である。図１６を参照すると、第９の実施形態で説明した回路において、第１のＰＭＯＳトランジスタP1と第２のＰＭＯＳトランジスタP2とを入れ替え、第１のＮＭＯＳトランジスタN1と第２のＮＭＯＳトランジスタN2とを入れ替えた構成である。なお、これらの入れ替えにより、第９の実施形態では内部ノードXNに接続されていた、ＰＭＯＳトランジスタのゲート電極は入力線301に接続され、第９の実施形態では入力線301に接続されていた、ＮＭＯＳトランジスタのゲート電極は内部ノードXNに接続されている。 FIG. 16 is a circuit diagram showing a configuration example of the disturbance detection logic gate of the present embodiment. Referring to FIG. 16, in the circuit described in the ninth embodiment, the first PMOS transistor P1 and the second PMOS transistor P2 are interchanged, and the first NMOS transistor N1 and the second NMOS transistor N2 are interchanged. It is a configuration. As a result of the replacement, the gate electrode of the PMOS transistor connected to the internal node XN in the ninth embodiment is connected to the input line 301, and is connected to the input line 301 in the ninth embodiment. The gate electrode of the NMOS transistor is connected to the internal node XN.
　本実施形態の擾乱検出論理ゲートの動作は、第９の実施形態と同様であるため、その詳細な説明を省略する。 Since the operation of the disturbance detection logic gate of this embodiment is the same as that of the ninth embodiment, its detailed description is omitted.
　（第１１の実施形態）
　本実施形態は、擾乱検出論理ゲートの別の構成例である。 (Eleventh embodiment)
This embodiment is another configuration example of the disturbance detection logic gate.
　図１７は本実施形態の擾乱検出論理ゲートの一構成例を示す回路図である。図１７を参照すると、第９の実施形態における第１および第２のＰＭＯＳトランジスタP1,　P2のそれぞれに、第３および第４のＰＭＯＳトランジスタP3,　P4のそれぞれが並列に接続されている。また、第９の実施形態における第１および第２のＮＭＯＳトランジスタN1,　N2のそれぞれに、第３および第４のＮＭＯＳトランジスタN3,　N4のそれぞれが並列に接続されている。 FIG. 17 is a circuit diagram showing a configuration example of the disturbance detection logic gate of this embodiment. Referring to FIG. 17, the third and fourth PMOS transistors P3 and P4 are connected in parallel to the first and second PMOS transistors P1 and P2, respectively, in the ninth embodiment. Further, the third and fourth NMOS transistors N3 and N4 are connected in parallel to the first and second NMOS transistors N1 and N2, respectively, in the ninth embodiment.
　本実施形態では、トランジスタを並列に配置することで、少なくともどちらか一方のトランジスタがオンすることで出力値が変化するので感度を高めることができる。 In this embodiment, by arranging the transistors in parallel, the output value changes when at least one of the transistors is turned on, so that the sensitivity can be increased.
　なお、本実施形態では、並列トランジスタ数が２つの場合であるが、それ以上のトランジスタを並列に配置することも可能である。また、トランジスタ毎に異なる並列数を選択することも可能である。 In this embodiment, the number of parallel transistors is two, but more transistors can be arranged in parallel. It is also possible to select a different parallel number for each transistor.
　(第１２の実施形態)
　本実施形態は、擾乱検出論理ゲートの別の構成例である。 (Twelfth embodiment)
This embodiment is another configuration example of the disturbance detection logic gate.
　図１８は本実施形態の擾乱検出論理ゲートの一構成例を示す回路図である。図１８を参照すると、第９の実施形態における第１および第２のＰＭＯＳトランジスタP1,　P2のそれぞれと第３および第４のＰＭＯＳトランジスタP3,　P4のそれぞれとが直列に接続されている。また、第９の実施形態における第１および第２のＮＭＯＳトランジスタN1,　N2のそれぞれと第３および第４のＮＭＯＳトランジスタN3,　N4のそれぞれとが直列に接続されている。 FIG. 18 is a circuit diagram showing a configuration example of the disturbance detection logic gate of the present embodiment. Referring to FIG. 18, the first and second PMOS transistors P1, P2 and the third and fourth PMOS transistors P3, P4 in the ninth embodiment are connected in series. Further, the first and second NMOS transistors N1 and N2 in the ninth embodiment and the third and fourth NMOS transistors N3 and N4 are connected in series, respectively.
　本実施形態では、トランジスタを直列に配置することで、両方のトランジスタがオンしない限り出力値が変化しないので感度を弱めることができる。 In this embodiment, by arranging the transistors in series, the output value does not change unless both transistors are turned on, so the sensitivity can be weakened.
　なお、本実施形態では、直列トランジスタ数が２つの場合であるが、それ以上のトランジスタを直列に配置することも可能である。また、トランジスタ毎に異なる直列数を選択することも可能である。 In the present embodiment, the number of series transistors is two, but more transistors can be arranged in series. It is also possible to select a different series number for each transistor.
　(第１３の実施形態)
　本実施形態は、擾乱検出論理ゲートの別の構成例である。 (Thirteenth embodiment)
This embodiment is another configuration example of the disturbance detection logic gate.
　図１９は本実施形態の擾乱検出論理ゲートの一構成例を示す回路図である。図１９を参照すると、第９の実施形態と同様に第１および第２のＰＭＯＳトランジスタP1,　P2と第１および第２のＮＭＯＳトランジスタN1,　N2が設けられ、その接続関係も第９の実施形態と同様である。入力線311が第１のＮＭＯＳトランジスタN1のゲート電極に接続され、出力線321が第２のＰＭＯＳトランジスタP2および第２のＮＭＯＳトランジスタN2の接続点に接続されている。 FIG. 19 is a circuit diagram showing a configuration example of the disturbance detection logic gate of the present embodiment. Referring to FIG. 19, similarly to the ninth embodiment, first and second PMOS transistors P1, P2 and first and second NMOS transistors N1, N2 are provided, and their connection relation is also the ninth embodiment. It is the same. The input line 311 is connected to the gate electrode of the first NMOS transistor N1, and the output line 321 is connected to the connection point between the second PMOS transistor P2 and the second NMOS transistor N2.
　また、第３および第４のＰＭＯＳトランジスタP3,　P4と第３および第４のＮＭＯＳトランジスタN3,　N4が設けられ、その接続関係は第１および第２のＰＭＯＳトランジスタP1,　P2と第１および第２のＮＭＯＳトランジスタN1,　N2の接続関係と同様である。入力線312が第３のＮＭＯＳトランジスタN3のゲート電極に接続され、出力線322が第４のＰＭＯＳトランジスタP4および第４のＮＭＯＳトランジスタN4の接続点に接続されている。 In addition, third and fourth PMOS transistors P3, P4 and third and fourth NMOS transistors N3, N4 are provided, and the connection relationship is the first and second PMOS transistors P1, P2 and the first and second. This is the same as the connection relationship of the NMOS transistors N1 and N2. The input line 312 is connected to the gate electrode of the third NMOS transistor N3, and the output line 322 is connected to the connection point of the fourth PMOS transistor P4 and the fourth NMOS transistor N4.
　本実施形態では、一つの擾乱により二つの内部ノードX1,　X2のうち一方に蓄えられた電荷が放出された場合、出力線321の出力値OUT1と出力線322の出力値OUT2のうちいずれか一方のみが変化する。一方、一つの擾乱により二つの内部ノードX1,X2のうち両方に蓄えられた電荷が放出された場合、出力値OUT1,OUT2の両方が変化する。すなわち、本実施例で、一つの擾乱により二つのビットに発生する一過性のエラーを検出できる。 In this embodiment, when the electric charge stored in one of the two internal nodes X1 and X2 is released by one disturbance, one of the output value OUT1 of the output line 321 and the output value OUT2 of the output line 322 Only changes. On the other hand, when the electric charge stored in both of the two internal nodes X1 and X2 is released by one disturbance, both the output values OUT1 and OUT2 change. That is, in this embodiment, it is possible to detect a transient error that occurs in two bits due to one disturbance.
　なお、第９から第１３の実施形態では、擾乱検出論理ゲートがドミノ論理回路の場合で説明したが、その一部がドミノ論理回路であってもよい。また、擾乱検出論理ゲートの一部または全部が、ドミノ論理回路の場合に限らず、組み合わせ回路または順序回路であってもよい。また、ドミノ論理回路、組み合わせ回路および順序回路のうちいずれを擾乱検出回路に含めるかを、評価対象の回路に合わせて決めてもよい。 In the ninth to thirteenth embodiments, the disturbance detection logic gate is a domino logic circuit, but a part thereof may be a domino logic circuit. Further, some or all of the disturbance detection logic gates are not limited to the Domino logic circuit but may be a combinational circuit or a sequential circuit. Further, which of the domino logic circuit, the combinational circuit, and the sequential circuit is included in the disturbance detection circuit may be determined according to the circuit to be evaluated.
　また、第９から第１３の実施形態のそれぞれにおいて、擾乱検出論理ゲートを半導体集積回路で作製した場合を説明したが、第１から第１２の実施形態で説明した擾乱検出回路も半導体集積回路で作製してもよい。また、評価対象の集積回路に限らず、他の集積回路を擾乱検出回路に並置して同じ半導体基板に作製してもよい。さらに、第１から第１３の実施形態をそれぞれ単独で実施する場合に限らず、組み合わせ可能であれば、複数組み合わせてもよい。 In each of the ninth to thirteenth embodiments, the case where the disturbance detection logic gate is made of a semiconductor integrated circuit has been described. However, the disturbance detection circuit described in the first to twelfth embodiments is also a semiconductor integrated circuit. It may be produced. Further, not only the integrated circuit to be evaluated, but also other integrated circuits may be formed on the same semiconductor substrate in parallel with the disturbance detection circuit. Furthermore, the first to thirteenth embodiments are not limited to being implemented individually, and a plurality of combinations may be combined as long as they can be combined.
　本発明の効果の一例として、直列に接続された擾乱検出論理ゲートの最終段の出力を監視するだけで、擾乱による一過性のエラーを容易に検出することができる。 As an example of the effect of the present invention, a transient error due to a disturbance can be easily detected only by monitoring the output of the final stage of the disturbance detection logic gate connected in series.
　また、一過性のエラーの検出は、試験前に書き込んだ値と、試験後に読み出した値の比較で行うので、比較操作のための時間がかかってしまう。また、メモリを用いた検出方法では、比較のための付加回路を設けるか、テスタなどの比較装置を外部に設ける必要がある。また、図１で説明した検出器では、書き込み、試験、読み出し、比較という操作をある時間間隔で繰り返して行うため、一過性のエラー発生から比較までに時間がかかり、一過性のエラーの発生を直ちに検出できない。このような問題に対し、本発明の効果の一例として、一過性のエラーは直列に接続された擾乱検出論理ゲートを次々と伝わるので擾乱による一過性のエラーを直ちに検出できる。また、比較のための付加回路やテスタなどの比較装置を外部に設ける必要がない。 Also, since transient error detection is performed by comparing the value written before the test with the value read after the test, it takes time for the comparison operation. Further, in the detection method using a memory, it is necessary to provide an additional circuit for comparison or to provide a comparison device such as a tester outside. In addition, since the detector described in FIG. 1 repeatedly performs operations such as writing, testing, reading, and comparing at certain time intervals, it takes time from the occurrence of a transient error to the comparison, and a transient error is detected. The occurrence cannot be detected immediately. As an example of the effect of the present invention with respect to such a problem, since transient errors are successively transmitted through the disturbance detection logic gates connected in series, transient errors due to disturbance can be detected immediately. Further, there is no need to provide a comparison device such as an additional circuit for comparison or a tester outside.
　さらに、図１で説明したように、検出回路がメモリセルであると、メモリ以外のフリップフロップや組み合わせ論理回路を対象に一過性のエラーの検出ができない。この問題に対し、本発明の効果の一例では、擾乱検出論理ゲートの一部または全部に、組み合わせ論理回路、ドミノ論理回路および順序回路のうちいずれかを用いることが可能であり、メモリ以外の回路を対象に擾乱による一過性のエラーを検出できる。 Furthermore, as described with reference to FIG. 1, if the detection circuit is a memory cell, a transient error cannot be detected for flip-flops and combinational logic circuits other than the memory. In order to solve this problem, in one example of the effect of the present invention, it is possible to use any one of a combinational logic circuit, a domino logic circuit, and a sequential circuit for a part or all of the disturbance detection logic gate. It is possible to detect transient errors due to disturbances.
　以上、実施形態を参照して本願発明を説明したが、本願発明は上記実施形態に限定されるものではない。本願発明の構成や詳細には、本願発明のスコープ内で当業者が理解し得る様々な変更をすることができる。 The present invention has been described above with reference to the embodiments, but the present invention is not limited to the above embodiments. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention.
　なお、この出願は、２００８年９月１９日に出願された日本出願の特願２００８－２４１３７１の内容が全て取り込まれており、この日本出願を基礎として優先権を主張するものである。 Note that this application incorporates all the contents of Japanese Patent Application No. 2008-241371 filed on September 19, 2008, and claims priority based on this Japanese application.
　Ｇ１～Ｇｎ，Ｇ１１～Ｇ１ｎ，Ｇ２１～Ｇ２ｎ　　擾乱検出論理ゲート
　ＳＧ，ＳＧ１～ＳＧｎ　　擾乱検出回路
　Ｓ１　　出力選択回路
　ＯＣ１，ＯＣ２，ＯＣｎ　　出力制御回路
　Ｍ１　　併合回路
　ＩＴＣ　　初期化回路
　ＯＰ　　出力処理回路
　Ｐ１，Ｐ２，Ｐ３，Ｐ４　　ＰＭＯＳトランジスタ
　Ｎ１，Ｎ２，Ｎ３，Ｎ４　　ＮＭＯＳトランジスタ G1 to Gn, G11 to G1n, G21 to G2n Disturbance detection logic gate SG, SG1 to SGn Disturbance detection circuit S1 Output selection circuit OC1, OC2, OCn Output control circuit M1 merging circuit ITC initialization circuit OP output processing circuit P1, P2, P3, P4 PMOS transistor N1, N2, N3, N4 NMOS transistor

Claims (20)

  1. 　自回路内の擾乱の発生により出力の論理値を変化させ、かつ、前段からの入力の論理値の変化によって後段への出力の論理値を変化させる複数の擾乱検出論理ゲートが直列に接続された系を有し、
    　前記複数の擾乱検出論理ゲートのうち最初の段の擾乱検出論理ゲートに一定の論理値が入力され、
    　前記複数の擾乱検出論理ゲートのうち最終の段の擾乱検出論理ゲートの出力の論理値の変化により前記擾乱の発生が検出される、擾乱検出回路。     Multiple disturbance detection logic gates that change the logic value of the output due to the occurrence of a disturbance in its own circuit and change the logic value of the output to the subsequent stage by changing the logic value of the input from the previous stage are connected in series Have a system,
    A constant logic value is input to the first stage of the plurality of disturbance detection logic gates,
    A disturbance detection circuit, wherein the occurrence of the disturbance is detected by a change in a logical value of an output of a disturbance detection logic gate at a final stage among the plurality of disturbance detection logic gates.
  2. 　前記複数の擾乱検出論理ゲートが直列に接続された系が複数設けられた、請求項１記載の擾乱検出回路。 The disturbance detection circuit according to claim 1, wherein a plurality of systems in which the plurality of disturbance detection logic gates are connected in series are provided.
  3. 　請求項１または２記載の擾乱検出回路が複数直列に接続され、
    　複数の前記擾乱検出回路のそれぞれの出力線が接続され、制御信号にしたがって複数の前記擾乱検出回路の出力のうち一つを選択して外部に出力する出力選択回路を有する擾乱検出回路。     A plurality of the disturbance detection circuits according to claim 1 or 2 are connected in series,
    A disturbance detection circuit having an output selection circuit that is connected to each output line of the plurality of disturbance detection circuits and selects one of the outputs of the plurality of disturbance detection circuits according to a control signal and outputs the selected one to the outside.
  4. 　請求項１または２記載の擾乱検出回路が複数直列に接続された系が複数設けられ、
    　前記系の最終段に接続され、制御信号にしたがって、該最終段の出力の論理値の変化の伝搬の可否を切り替える出力制御回路と、
    　前記系毎に設けられた前記出力制御回路と接続され、複数の該出力制御回路の出力のうち少なくとも一つの出力の論理値の変化を出力する併合回路と、
    を有する擾乱検出回路。     A plurality of systems in which a plurality of disturbance detection circuits according to claim 1 or 2 are connected in series are provided,
    An output control circuit connected to the final stage of the system, and switching the propriety of the propagation of the change in the logical value of the output of the final stage according to the control signal;
    A merge circuit connected to the output control circuit provided for each of the systems, and outputting a change in the logical value of at least one of the outputs of the plurality of output control circuits;
    A disturbance detection circuit comprising:
  5. 　擾乱発生の検出のための出力線が接続され、該出力線から入力される論理値の変化に所定の演算処理を実行して出力する出力処理回路が設けられた請求項１から４のいずれか１項に記載の擾乱検出回路。 5. The output processing circuit according to claim 1, further comprising: an output processing circuit that is connected to an output line for detecting the occurrence of a disturbance, and that executes a predetermined arithmetic process on a change in a logical value input from the output line and outputs the result. The disturbance detection circuit according to Item 1.
  6. 　前記出力処理回路は、前記論理値の変化の数を計測する計測器を含む構成である請求項５に記載の擾乱検出回路。 The disturbance detection circuit according to claim 5, wherein the output processing circuit includes a measuring instrument that measures the number of changes in the logical value.
  7. 　前記出力処理回路は、前記論理値の変化のうちある一定期間に起きた変化の数のみを計測する計測器を含む構成である請求項５に記載の擾乱検出回路。 6. The disturbance detection circuit according to claim 5, wherein the output processing circuit includes a measuring instrument that measures only the number of changes that occur in a certain period of the change in the logical value.
  8. 　前記擾乱検出論理ゲートは初期化信号が入力されると、所定の状態に遷移し、
    　前記擾乱検出論理ゲートの全てに対して初期化信号を入力するための初期化入力線が設けられた請求項１から７のいずれか１項に記載の擾乱検出回路。     The disturbance detection logic gate transitions to a predetermined state when an initialization signal is input,
    8. The disturbance detection circuit according to claim 1, further comprising an initialization input line for inputting an initialization signal to all of the disturbance detection logic gates.
  9. 　前記擾乱検出論理ゲートの全てに対して前記初期化入力線を介して前記初期化信号を送信するための初期化回路が設けられた請求項８に記載の擾乱検出回路。 The disturbance detection circuit according to claim 8, wherein an initialization circuit is provided for transmitting the initialization signal to all of the disturbance detection logic gates via the initialization input line.
  10. 　擾乱発生の検出のための出力線が前記初期化回路と接続され、
    　前記初期化回路は、該出力線から入力される論理値が変化すると前記初期化信号を発生する、請求項９に記載の擾乱検出回路。     An output line for detecting the occurrence of disturbance is connected to the initialization circuit,
    The disturbance detection circuit according to claim 9, wherein the initialization circuit generates the initialization signal when a logical value input from the output line changes.
  11. 　少なくとも一つの前記擾乱検出論理ゲートの出力の論理値を変化させる試験信号を入力するための試験入力線が設けられた請求項１から１０のいずれか１項に記載の擾乱検出回路。 11. The disturbance detection circuit according to claim 1, further comprising a test input line for inputting a test signal for changing a logical value of an output of at least one of the disturbance detection logic gates.
  12. 　前記擾乱検出論理ゲートの一部または全てが組み合わせ論理回路である、請求項１から１１のいずれか１項に記載の擾乱検出回路。 The disturbance detection circuit according to any one of claims 1 to 11, wherein a part or all of the disturbance detection logic gate is a combinational logic circuit.
  13. 　前記擾乱検出論理ゲートの一部または全てが順序回路である、請求項１から１１のいずれか１項に記載の擾乱検出回路。 The disturbance detection circuit according to any one of claims 1 to 11, wherein a part or all of the disturbance detection logic gate is a sequential circuit.
  14. 　前記擾乱検出論理ゲートの一部または全てがドミノ論理回路である、請求項１から１１のいずれか１項に記載の擾乱検出回路。 12. The disturbance detection circuit according to claim 1, wherein a part or all of the disturbance detection logic gate is a domino logic circuit.
  15. 　前記ドミノ論理回路は、第１および第２のＮＭＯＳトランジスタと、第１および第２のＰＭＯＳトランジスタとを有し、
    　前記第１のＮＭＯＳトランジスタは、ソース電極が接地線に接続され、ゲート電極が入力線に接続され、ドレイン電極が前記第１のＰＭＯＳトランジスタのドレイン電極に接続され、
    　前記第２のＮＭＯＳトランジスタは、ソース電極が前記接地線に接続され、ゲート電極は、初期化状態に遷移させるための初期化信号が伝送される初期化信号線に接続され、ドレイン電極が前記第２のＰＭＯＳトランジスタのドレイン電極に接続され、
    　前記第１のＰＭＯＳトランジスタは、ソース電極が電源線に接続され、ゲート電極が前記初期化信号の反転信号が伝送される否定初期化信号線に接続され、
    　前記第２のＰＭＯＳトランジスタは、ソース電極が前記電源線に接続され、ゲート電極が前記第１のＰＭＯＳトランジスタおよび前記第１のＮＭＯＳトランジスタのそれぞれのドレイン電極に接続され、
    　擾乱検出のための出力線が、前記第２のＰＭＯＳトランジスタおよび第２のＮＭＯＳトランジスタのそれぞれのドレイン電極に接続されている、請求項１４に記載の擾乱検出回路。     The domino logic circuit includes first and second NMOS transistors, and first and second PMOS transistors,
    The first NMOS transistor has a source electrode connected to a ground line, a gate electrode connected to an input line, a drain electrode connected to a drain electrode of the first PMOS transistor,
    The second NMOS transistor has a source electrode connected to the ground line, a gate electrode connected to an initialization signal line for transmitting an initialization signal for transitioning to an initialization state, and a drain electrode connected to the first NMOS transistor. Connected to the drain electrode of two PMOS transistors,
    The first PMOS transistor has a source electrode connected to a power supply line, a gate electrode connected to a negative initialization signal line through which an inverted signal of the initialization signal is transmitted,
    The second PMOS transistor has a source electrode connected to the power supply line, a gate electrode connected to the respective drain electrodes of the first PMOS transistor and the first NMOS transistor,
    The disturbance detection circuit according to claim 14, wherein an output line for disturbance detection is connected to each drain electrode of the second PMOS transistor and the second NMOS transistor.
  16. 　請求項１から１５のいずれか１項に記載の擾乱検出回路を有する半導体集積回路。 A semiconductor integrated circuit having the disturbance detection circuit according to any one of claims 1 to 15.
  17. 　請求項１から１５のいずれか１項に記載の擾乱検出回路と、
    　前記擾乱検出回路に並置された集積回路と、
    を有する半導体集積回路。     The disturbance detection circuit according to any one of claims 1 to 15,
    An integrated circuit juxtaposed to the disturbance detection circuit;
    A semiconductor integrated circuit.
  18. 　請求項９記載の擾乱検出回路を用いた擾乱検出方法であって、
    　前記初期化信号により前記擾乱検出回路が初期化された後に擾乱検出動作を開始させる、擾乱検出方法。     A disturbance detection method using the disturbance detection circuit according to claim 9,
    A disturbance detection method, wherein a disturbance detection operation is started after the disturbance detection circuit is initialized by the initialization signal.
  19. 　請求項１０記載の擾乱検出回路を用いた擾乱検出方法であって、
    　前記出力線の論理値の変化により前記擾乱検出動作を停止させ、前記擾乱検出回路を初期化した後、擾乱検出動作を再開させる、擾乱検出方法。     A disturbance detection method using the disturbance detection circuit according to claim 10,
    A disturbance detection method in which the disturbance detection operation is stopped by a change in the logical value of the output line, the disturbance detection circuit is initialized, and then the disturbance detection operation is restarted.
  20. 　請求項１１記載の擾乱検出回路を用いた試験方法であって、
    　前記試験信号により、前記擾乱の発生がなくても前記擾乱検出回路の検出動作を試験する、擾乱検出回路の試験方法。     A test method using the disturbance detection circuit according to claim 11,
    A test method for a disturbance detection circuit, wherein the detection operation of the disturbance detection circuit is tested by the test signal even if the disturbance is not generated.
PCT/JP2009/065703 2008-09-19 2009-09-09 Disturbance detection circuit, semiconductor integrated circuit, disturbance detection method, and test method WO2010032659A1 (en)

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JPS61206308A (en) * 1985-03-11 1986-09-12 Seiko Instr & Electronics Ltd Voltage controlled oscillator
JPH10111674A (en) * 1996-04-17 1998-04-28 Toshiba Corp Timing signal generation circuit and display device containing it
JPH10261943A (en) * 1997-03-17 1998-09-29 Sony Corp Delay circuit and oscillation circuit using the same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61206308A (en) * 1985-03-11 1986-09-12 Seiko Instr & Electronics Ltd Voltage controlled oscillator
JPH10111674A (en) * 1996-04-17 1998-04-28 Toshiba Corp Timing signal generation circuit and display device containing it
JPH10261943A (en) * 1997-03-17 1998-09-29 Sony Corp Delay circuit and oscillation circuit using the same

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