WO2010032468A1 - Storage element and storage device - Google Patents

Storage element and storage device Download PDF

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Publication number
WO2010032468A1
WO2010032468A1 PCT/JP2009/004681 JP2009004681W WO2010032468A1 WO 2010032468 A1 WO2010032468 A1 WO 2010032468A1 JP 2009004681 W JP2009004681 W JP 2009004681W WO 2010032468 A1 WO2010032468 A1 WO 2010032468A1
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WO
WIPO (PCT)
Prior art keywords
current
conductor layer
resistance
voltage
semiconductor layer
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PCT/JP2009/004681
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French (fr)
Japanese (ja)
Inventor
岡田崇志
飯島光輝
有田浩二
三河巧
富永健司
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パナソニック株式会社
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Publication of WO2010032468A1 publication Critical patent/WO2010032468A1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/20—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides
    • H10N70/8833—Binary metal oxides, e.g. TaOx
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides
    • H10N70/8836—Complex metal oxides, e.g. perovskites, spinels

Definitions

  • the present invention relates to a current suppressing element used in a nonvolatile memory element suitable for high integration and high speed. More specifically, the present invention relates to a current suppressing element (MSM diode) composed of a conductor / semiconductor / conductor. And a memory device using the memory element.
  • MSM diode current suppressing element
  • This resistance change element has a thin film composed mainly of a metal oxide material between two electrodes.
  • the resistance value is changed, and the changed resistance value is preserved even after the application of the electric pulse is stopped. Therefore, when the high resistance state and the low resistance state of the thin film are associated with, for example, “1” and “0” of the binary data, the binary data can be stored in the variable resistance element.
  • the amplitude and pulse width of the electric pulse applied to the thin film of the resistance change element are sufficient to change the physical state of the thin film, and may be any level that does not destroy the thin film. Moreover, you may apply an electrical pulse to the thin film of this resistance change element in multiple times.
  • a storage device (a so-called cross-point storage device) in which a plurality of such variable resistance elements are arranged at each three-dimensional intersection of a plurality of word lines and a plurality of bit lines, a selected resistance
  • write disturb a failure in which the resistance value of the non-selected resistance change element changes due to the bypass current. Therefore, when configuring such a cross-point type storage device, it is necessary to provide a special configuration for preventing the occurrence of write disturb.
  • a detour current to the non-selected resistance change element causes a reverse bias or a zero bias to the diode of the non-selected memory element. It is blocked by adjusting the voltage of the selected / unselected bit lines and word lines to apply. As a result, it is expected to prevent occurrence of write disturb in the cross-point type storage device.
  • data is written to the variable resistance element by applying pulses of the same polarity and different voltages to the variable resistance element. That is, the variable resistance element is a unipolar type.
  • a unipolar diode connected in series with the selected variable resistance element (when a voltage higher than a certain threshold value is applied to the diode, the diode is turned on by forward bias, causing a large current to flow, and the opposite polarity. When the voltage is applied, the diode is turned off by reverse bias and the current hardly flows)) is written with forward bias, and when not selected, it is turned off with reverse bias or zero bias. Disturbance can be prevented.
  • variable resistance element described in Patent Document 1 was a unipolar type as described above, writing disturbance could be prevented by connecting a unipolar diode in series with the variable resistance element.
  • the variable resistance element is formed by applying binary data “1” and “0” and voltage pulses having different polarities to the thin film due to the material constituting the thin film having the resistance changing function.
  • variable resistance element (bipolar type) for writing.
  • a unipolar variable resistance element has a characteristic that, when changing from a low resistance state to a high resistance state (so-called resetting), an electric pulse ( ⁇ 1 ⁇ sec) having a longer pulse width than that in the reverse setting is required. There are many things.
  • bipolar resistance change elements can change resistance with electric pulses having a short pulse width (100 nsec or less) both at the time of setting and resetting, and some are superior to the unipolar type in terms of writing speed.
  • a resistance change element if a diode is connected in series with the resistance change element, a voltage pulse of one polarity can be used for writing data, but a voltage pulse of the other polarity can be used for writing data. It cannot be used. Therefore, in a cross-point memory device including such a bipolar variable resistance element, a unipolar diode such as a Schottky diode cannot be connected in series to the variable resistance element. There is a problem that the occurrence cannot be prevented.
  • This problem can be solved by using a diode that is connected in series with the variable resistance element that has a non-linear electrical resistance characteristic and whose current-voltage characteristic is substantially symmetric with respect to the polarity of the applied voltage.
  • a diode that is connected in series with the variable resistance element that has a non-linear electrical resistance characteristic and whose current-voltage characteristic is substantially symmetric with respect to the polarity of the applied voltage.
  • an element having such characteristics for example, an MIM diode (Metal-Insulator-Metal; meaning metal-insulator-metal), an MSM diode (Metal-Semiconductor-Metal; meaning metal-semiconductor-metal), or Two-terminal elements such as varistors are known.
  • These diodes are referred to as bipolar diodes as opposed to unipolar diodes such as Schottky diodes.
  • FIG. 6 is a characteristic diagram schematically showing the voltage-current characteristics of the current suppressing element.
  • FIG. 6 (a) is a voltage-current characteristic diagram of a bipolar diode
  • FIG. 6 (b) is a Schottky diode or the like. It is a voltage-current characteristic view of a unipolar diode.
  • the unipolar diode exhibits nonlinear electrical resistance characteristics, but its voltage-current characteristics are not symmetrical at all with respect to the polarity of the applied voltage.
  • bipolar diodes such as MIM diodes, MSM diodes, and varistors exhibit non-linear electrical resistance characteristics, and their voltage-current characteristics depend on the polarity of the applied voltage. It is substantially symmetric with respect to it. That is, the change in current with respect to the positive applied voltage and the change in current with respect to the negative applied voltage are substantially point-symmetric with respect to the origin 0.
  • the applied voltage is not more than the first critical voltage (lower limit voltage of range A) and not less than the second critical voltage (upper limit voltage of range B) (that is, range C). Then, the electrical resistance is very high, and when the first critical voltage is exceeded or the second critical voltage is lowered, the electrical resistance rapidly decreases. That is, these two-terminal elements have non-linear electrical resistance characteristics such that a large current flows when the applied voltage exceeds the first critical voltage or falls below the second critical voltage.
  • bipolar diodes with a bipolar memory element and using it as a current suppressing element, it is possible to avoid the occurrence of write disturbance in a cross-point memory device using a bipolar variable resistance element. Can be expected.
  • the resistance value is changed by applying a voltage pulse to the resistance change element, so that the resistance change element is in a high resistance state or a low resistance state.
  • a voltage pulse to the resistance change element, so that the resistance change element is in a high resistance state or a low resistance state.
  • it is necessary to pass a large current through the resistance change element although it greatly depends on the material of the change element and its configuration.
  • a metal oxide material specifically, a Pr—Ca—Mn—O-based material, titanium dioxide, nickel oxide, copper oxide, etc.
  • the variable resistance layer of the variable resistance element at least 1000 ⁇ A.
  • the resistance change characteristic of the resistance change element cannot be obtained unless a current is passed at a current density of / ⁇ m 2 or more.
  • a storage element that does not write data by applying an on-voltage to a storage element in which data is to be written (hereinafter referred to as a selected storage element).
  • an off-voltage is applied to the non-selected memory element.
  • a metal oxide material specifically, PRPr—Ca—Mn—O-based material, titanium dioxide, nickel oxide, copper oxide, etc.
  • selective memory is used as the resistance change layer of the resistance change element.
  • the element requires an applied voltage of 2.0 V, that is, an on voltage of 2.0 V
  • the non-selected memory element requires an applied voltage of 1.0 V, that is, an off voltage of 1.0 V.
  • the current flowing at this on-voltage is large.
  • the ratio of the on-current to the off-current that is, the on-off current ratio obtained by dividing the on-current by the off-current (hereinafter, this ratio is referred to as “on / off-current ratio”) is defined as The larger it is, the better.
  • the on / off current ratio is at least 50 or more.
  • the present invention has been made to solve the above-described conventional problems, and is a current suppressing element connected in series to a bipolar variable resistance element, and is necessary for the resistance change of the variable resistance element, 1000 ⁇ A / ⁇ m 2.
  • a non-volatile memory element capable of flowing the above current and realizing an on / off current ratio of at least 50 to prevent occurrence of a write disturbance and increase a read margin, and a memory device including the same It is intended to provide.
  • a memory element includes a resistance change element that changes its electrical resistance value by applying a positive or negative electric pulse, and maintains the electric resistance value after the change. And a current suppressing element that suppresses a current that flows when the electric pulse is applied to the variable resistance element, wherein the current suppressing element includes a first conductor layer and the first conductor.
  • a tantalum nitride comprising a semiconductor layer provided on the layer and a second conductor layer provided on the semiconductor layer, wherein the first conductor layer or the second conductor layer contains tantalum and nitrogen And the semiconductor layer is made of silicon nitride containing silicon and nitrogen, and the tantalum nitride forming the first or second conductor layer is expressed as TaN X. ⁇ x ⁇ 1.67 Features.
  • the tantalum nitride used for the conductor layer of the current suppressing element is a material that has been used as a barrier layer for copper wiring in the semiconductor field, and the silicon nitride used for the semiconductor layer of the current suppressing element is also It is a material with a track record of use.
  • a current suppressing element is constructed using these materials, it is easy to maintain and maintain the semiconductor production line for producing the current suppressing element, and to divert existing equipment or processing conditions relating to film formation or etching. It is possible to provide a memory element that is excellent in performance.
  • the tantalum nitride used for the first conductor layer or the second conductor layer is more preferably Ta 2 N or Ta 3 N 5 .
  • a storage device includes a plurality of the above-described storage elements according to the present invention, and includes a plurality of bit lines and a plurality of word lines that three-dimensionally intersect the plurality of bit lines, A series circuit of a resistance change element and the current suppressing element, wherein the plurality of storage elements are disposed in each portion where the bit line and the word line intersect three-dimensionally; One end of the circuit is connected to the corresponding bit line, and the other end of the series circuit is connected to the corresponding word line.
  • the configuration of the memory element and the memory device according to the present invention includes a bipolar resistance change element that causes a resistance change by applying electric pulses having different polarities, and combines an MSM type current suppression element according to the present invention with a resistance.
  • a current of 1000 ⁇ A / ⁇ m 2 or more necessary to change the resistance of the change element is allowed to flow, a breakdown is suppressed, and an on / off current ratio of at least 50 can be realized, thereby preventing a write disturbance.
  • FIG. 1 is a block diagram schematically showing a configuration of a memory device of the present invention including a resistance change element as a memory element.
  • FIG. 2 is a cross-sectional view schematically showing a configuration according to the embodiment of the current suppressing element of the present invention.
  • FIG. 3 is a diagram showing voltage-current characteristics of the current suppressing element according to the embodiment of the present invention. 4 shows the ratio x of N to Ta of tantalum nitride, which is the first and second conductor layers according to the embodiment of the present invention, and the breakdown current derived from the voltage-current characteristics of FIG. It is a figure which shows the relationship.
  • FIG. 1 is a block diagram schematically showing a configuration of a memory device of the present invention including a resistance change element as a memory element.
  • FIG. 2 is a cross-sectional view schematically showing a configuration according to the embodiment of the current suppressing element of the present invention.
  • FIG. 3 is a diagram showing voltage-current characteristics of the current suppressing element according to
  • FIG. 5 shows the ratio of N to Ta of tantalum nitride, which is the first and second conductor layers according to the embodiment of the present invention, and the on / off current derived from the voltage-current characteristics of FIG. It is a figure which shows the relationship with ratio.
  • FIG. 6 is a characteristic diagram schematically showing the voltage-current characteristics of the current suppressing element, (a) a characteristic chart of a two-terminal element such as a varistor, and (b) a characteristic chart of a Schottky diode.
  • FIG. 1 is a block diagram schematically showing a configuration of a storage device including storage elements arranged in series with bipolar current suppressing elements and bipolar variable resistance elements according to an embodiment of the present invention. .
  • FIG. 1 only the components necessary for explaining the present invention are shown, and the other components are not shown.
  • the storage device 21 is a so-called cross-point storage device.
  • the storage device 21 configures a storage element array 20 and peripheral circuits (a bit line decoder 4, a read circuit 5, and word line decoders 6 and 7 described later) for driving the storage element array 20. ing.
  • An actual storage element array usually has a plurality of bit lines and a plurality of word lines, but in this specification, as shown in FIG. 1, the configuration of the storage element array can be easily understood.
  • the storage element array 20 including four bit lines BL0 to BL3 and four word lines WL0 to WL3 is illustrated.
  • the four bit lines BL0 to BL3 and the four word lines WL0 to WL3 are arranged so as to three-dimensionally intersect each other at right angles.
  • a storage element 3 (so-called cell) is disposed in each of the three-dimensional intersections 11 between the four bit lines BL0 to BL3 and the four word lines WL0 to WL3.
  • the memory elements 3 are arranged in a matrix of 4 rows and 4 columns.
  • each of the memory elements 3 is constituted by a series circuit of a resistance change element 1 and a current suppression element 2 connected in series to the resistance change element 1.
  • One end and the other end of the series circuit are connected to the bit lines BL0 to BL3 and the word lines WL0 to WL3 corresponding to the solid intersection 11 respectively.
  • bit line decoder 4 As shown in FIG. 1, one end of each of the four bit lines BL0 to BL3 is connected to the bit line decoder 4. The other ends of the bit lines BL0 to BL3 are connected to the read circuit 5. On the other hand, both ends of the four word lines WL0 to WL3 are connected to the word line decoders 6 and 7, respectively.
  • the two word line decoders 6 and 7 are disposed at both ends of the word lines WL0 to WL3, for example, the even-numbered word lines are connected to the word line decoder 6 and the odd-numbered word lines are connected to the word lines.
  • the word lines WL0 to WL3 can be alternately connected to the word line decoder 6 and the word line decoder 7 so as to be connected to the line decoder 7.
  • such a connection form is adopted. With this configuration, the interval between the word lines WL0 to WL3 can be reduced, and the degree of freedom regarding the circuit arrangement of the word line decoders 6 and 7 can be increased.
  • the bit line decoder 4 selects the bit lines BL0 to BL3 in response to a command from a controller (not shown). Further, the word line decoders 6 and 7 select the word lines WL0 to WL3 in accordance with a command from the controller. The bit line decoder 4 and the word line decoders 6 and 7 select the selected bit on the bit lines BL0 to BL3 depending on whether the command from the controller is data writing or data reading. An electric pulse whose voltage is a predetermined write voltage Vw (more precisely, a voltage pulse) or a predetermined read voltage Vr between the line and a selected word line in the word lines WL0 to WL3 An electric pulse (more precisely, a voltage pulse) is applied.
  • Vw more precisely, a voltage pulse
  • Vr predetermined read voltage
  • the reading circuit 5 detects the current value flowing through the selected bit line in the bit lines BL0 to BL3, reads the data stored in the selected storage element 3, and directs this to the controller. Output.
  • peripheral circuits such as the bit line decoder 4, the read circuit 5, and the word line decoders 6 and 7 shown in FIG.
  • the storage device 21 is usually manufactured by a semiconductor manufacturing process.
  • variable resistance element According to the present embodiment, the configuration of the variable resistance element according to the present embodiment will be described in detail.
  • a resistance change element 1 shown in FIG. 1 includes a thin film made of a resistance change material (hereinafter referred to as a “resistance change thin film”) between a pair of opposed electrode layers (not shown). Yes.
  • a predetermined electric pulse is applied to the resistance change thin film from the pair of counter electrodes, the resistance value between the pair of counter electrodes transitions between a low resistance state and a high resistance state.
  • this resistance change thin film maintains the state after the transition unless a predetermined electric pulse is applied.
  • one of the binary data “0” and “1” and the other is assigned to the low resistance state and the high resistance state, respectively, and the state of the resistance change thin film is set to the low resistance state.
  • a resistance change material for constituting the resistance change thin film a perovskite type transition metal oxide, a typical metal or an oxide of a transition metal, or the like can be used.
  • the resistance change material for forming the resistance change thin film Pr (1-x) Ca x MnO 3 (0 ⁇ x ⁇ 1), TiO 2 , NiO x (x> 0), Cu x O (x> 0) or the like, substitution products thereof, a mixture or a laminated structure thereof, or the like can be given.
  • the resistance change material is not limited to these resistance change materials.
  • the current suppressing element is configured by disposing a semiconductor layer between a pair of opposing conductor layers.
  • This configuration is the same as the MSM diode described above, exhibits nonlinear electrical resistance characteristics, and the current-voltage characteristics are substantially symmetric with respect to the polarity of the applied voltage. Even when it is applied, it is possible to prevent the occurrence of write disturb.
  • the current-voltage characteristic of the current suppression element depends greatly on the potential barrier formed between the conductor layer and the semiconductor layer adjacent to the conductor layer, and the potential barrier exhibits a rectifying property. In addition, by controlling the height of the potential barrier, the current suppressing element can pass a large current.
  • FIG. 2 is a cross-sectional view schematically showing the configuration of the current suppressing element according to the embodiment of the present invention.
  • the current suppressing element 2 is disposed between the first conductor layer 31, the second conductor layer 32, and the first and second conductor layers 31 and 32.
  • the semiconductor layer 33 is formed.
  • the first and second conductor layers 31 and 32 include tantalum nitride containing tantalum (Ta) and nitrogen (N), and the semiconductor layer 33 includes silicon (Si) and nitrogen (N). Contains silicon nitride.
  • an intermediate value of each crystal phase can be realized by mixing a plurality of TaN X phases having different X values. .
  • the material containing Si and N which is the semiconductor layer 33 indicates so-called silicon nitride.
  • Silicon nitride forms a tetrahedral amorphous semiconductor that forms a four-coordinate bond, and the tetrahedral amorphous semiconductor basically has a structure close to single crystal silicon or germanium, so elements other than Si must be introduced. It has the feature that the difference in structure due to is easily reflected in the physical properties. Therefore, if silicon nitride is applied to the semiconductor layer 33, it is easy to control the physical properties of the semiconductor layer 33 by controlling the structure of the silicon nitride, and accordingly, the first and second conductor layers 31 and 32 are thereby controlled. There is an advantage that the control of the potential barrier formed between the two becomes easier.
  • the tantalum nitride applied in the first and second conductor layers 31 and 32 is applied as a barrier layer for copper wiring
  • the silicon nitride applied in the semiconductor layer 33 is a semiconductor layer.
  • tantalum nitride and silicon nitride do not cause new impurity contamination due to the introduction of the semiconductor manufacturing line, and maintenance and maintenance of the semiconductor manufacturing line It is a preferable material.
  • the existing equipment can be easily transferred with respect to film formation or etching, and the processing conditions can be accommodated by using the existing film formation or etching conditions.
  • the inventors of the present application can control the composition of the tantalum nitride that is the first and second conductor layers 31 and 32 to allow a large current to flow through the resistance change element, that is, 1000 ⁇ A / It has been found that a current can flow at a current density of ⁇ m 2 or more (breakdown current is 1000 ⁇ A / ⁇ m 2 or more), and an on / off current ratio of at least 50 can be realized.
  • the first and second conductor layers 31 and 32 are composed of four types of metal Ta and tantalum nitride TaN 0.1 , Ta 2 N, Ta 3 N 5 having a film thickness of 50 nm.
  • the semiconductor layer 33 was made of silicon nitride SiN 0.3 having a thickness of 10 nm, and the current suppressing element 2 was produced.
  • the tantalum nitride film forming the first and second conductor layers 31 and 32 uses reactive sputtering, and an inert gas Ar used in sputtering and a reactive gas N 2 in nitride formation are simultaneously vacuumed.
  • the film was formed at room temperature while flowing through.
  • each tantalum nitride which is the conductor layers 31 and 32 of the present embodiment derived the composition and crystal structure in X-ray diffraction, and the film thickness and film surface shape were confirmed with a scanning electron microscope. .
  • the electrical resistivity of each tantalum nitride was derived from the value measured from the sheet resistance measuring machine.
  • the film formation of silicon nitride which is the semiconductor layer 33 of the present embodiment, uses reactive sputtering, and the inert gas Ar used for sputtering and the reactive gas N 2 for forming nitride are simultaneously supplied to the vacuum apparatus. Film formation was performed at room temperature. Further, the ratio of N to Si of silicon nitride, SiN 0.3 , which is the semiconductor layer of the present embodiment, was obtained by Rutherford backscattering spectroscopy. The film thickness of the silicon nitride layer was confirmed using ellipsometry spectroscopy. The surface shape of the silicon nitride film was confirmed with a scanning electron microscope.
  • a tantalum nitride film having a thickness of 50 nm as the first conductor layer 31 is formed on the substrate by reactive sputtering, and a silicon nitride film having a thickness of 10 nm as the semiconductor layer 33 is formed thereon by reactive sputtering.
  • the current suppression element 2 having an area of 0.46 ⁇ m ⁇ 0.46 ⁇ m was produced.
  • the first and second conductor layers 31 and 32 are made of Ta, TaN 0.1 , Ta 2 N, and Ta 3 N 5 tantalum nitride having a film thickness of 50 nm, and the semiconductor layer 33 is formed as a film.
  • the current-voltage characteristics of the four types of current suppressing elements 2 that were made of silicon nitride having a thickness of SiN 0.3 of 10 nm and whose conductor layer area was 0.46 ⁇ m ⁇ 0.46 ⁇ m were experimentally obtained. Is.
  • the current suppressing element 2 in which the first and second conductor layers 31 and 32 are made of tantalum nitride and the semiconductor layer 33 is made of silicon nitride has nonlinear electrical resistance characteristics. Further, it can be confirmed that a large amount of current flows in any voltage range as the ratio x of N to Ta of the tantalum nitride which is the first and second conductor layers 31 and 32 increases.
  • the current suppressing element 2 in which the ratio x of N to Ta is 0.5 and 1.67, and the so-called Ta 2 N and Ta 3 N 5 are the first and second conductor layers 31 and 32 is Ta
  • FIG. 4 shows that the first and second conductor layers 31 and 32 shown in FIG. 3 are made of tantalum nitrides of Ta, TaN 0.1 , Ta 2 N, and Ta 3 N 5 with a film thickness of 50 nm. From the current-voltage characteristics of the four types of current suppressing elements 2 in which the semiconductor layer 33 is made of silicon nitride of SiN 0.3 having a thickness of 10 nm and the area of the conductor layer is 0.46 ⁇ m ⁇ 0.46 ⁇ m. The relationship between the obtained ratio of N to Ta x and the breakdown current is shown.
  • the breakdown current increases as the ratio x of N to Ta of the tantalum nitride which is the first and second conductor layers 31 and 32 increases.
  • the breakdown current in each tantalum nitride of so-called Ta 2 N and Ta 3 N 5 in which the ratio of N to Ta is 0.5 and 1.67 is at least 1000 ⁇ A / ⁇ m 2 or more, and the resistance change It can be confirmed that a current can be passed through the element at a current density of 1000 ⁇ A / ⁇ m 2 or more.
  • FIG. 5 shows that the first and second conductor layers 31 and 32 shown in FIG. 3 are made of tantalum nitrides of Ta, TaN 0.1 , Ta 2 N, and Ta 3 N 5 with a thickness of 50 nm, From the current-voltage characteristics of the four types of current suppressing elements 2 in which the semiconductor layer 33 is made of silicon nitride of SiN 0.3 having a thickness of 10 nm and the area of the conductor layer is 0.46 ⁇ m ⁇ 0.46 ⁇ m. It is the graph which calculated
  • the breakdown current of the current suppressing element 2 is set to 1000 ⁇ A. / ⁇ m 2 or more, and an on / off current ratio of 50 or more can be secured.
  • the tantalum nitride of the first and second conductor layers 31 and 32 has a higher ratio of nitriding to Ta as the ratio of N to Ta increases.
  • the rate tends to be high and current tends to hardly flow.
  • the factor governing the flow of current is not the electrical resistivity of the conductor layers 31 and 32 (tantalum nitride) but the first and second conductor layers 31 constituting the MSM diode. , 32 and the semiconductor layer 33, it can be presumed that the height of the potential barrier is reduced, so that current easily flows at the interface.
  • the on / off ratio is improved because the off-region leakage current increases as the ratio x of N of Ta to tantalum nitride increases, but the increase in the on-region current exceeds the increase in the off-region current. It is thought that.
  • the current suppressing element 2 As described above, by configuring the current suppressing element 2, a non-linear electrical resistance characteristic is exhibited, the current-voltage characteristic is substantially symmetric with respect to the polarity of the applied voltage, and the resistance change element is large. It is possible to obtain the current suppressing element 2 capable of flowing a current. Therefore, even when electrical pulses having different polarities are applied, it is possible to prevent the occurrence of write disturbance and to allow a large current to flow through the resistance change element 1 and the storage device 21 including the storage element 3. It becomes possible to provide. From the foregoing description, many modifications and other embodiments of the present invention are obvious to one skilled in the art.
  • the memory element and the memory device according to the present invention can prevent the occurrence of write disturbance even when electric pulses having different polarities are applied, and even when a resistance change element is configured using a metal oxide material. Since data can be written without any problem, for example, it is suitable for use in a storage device including a current suppressing element that controls a current flowing through a resistance change storage element.

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Abstract

Disclosed is a storage element provided with a resistance variable element (1) wherein an electrical resistance value of each of the storage elements (3) arranged in matrix in a storage device (21) changes when an electrical pulse having the positive or negative polarity is applied, and the changed electrical resistance value is maintained; and a current suppressing element (2) which suppresses a current that flows when the electrical pulse is applied to the resistance variable element.  The current suppressing element is composed of a first conductor layer containing tantalum and a tantalum nitride containing nitrogen, a semiconductor layer containing silicon and a silicon nitride containing nitrogen on the first conductor layer, and a second conductor layer containing tantalum and a tantalum nitride containing nitrogen on the semiconductor layer.

Description

記憶素子及び記憶装置Storage element and storage device

　本発明は、高集積化および高速化に適した不揮発性記憶素子に用いる電流抑制素子に関するものであり、より詳細に述べると、導電体／半導体／導電体から構成される電流抑制素子（ＭＳＭダイオード）を用いた抵抗変化型不揮発性記憶素子、ならびに前記記憶素子を用いた記憶装置に関するものである。
The present invention relates to a current suppressing element used in a nonvolatile memory element suitable for high integration and high speed. More specifically, the present invention relates to a current suppressing element (MSM diode) composed of a conductor / semiconductor / conductor. And a memory device using the memory element.

　近年、抵抗変化素子を不揮発性記憶素子として利用する形態が提案されている。
In recent years, a form in which a resistance change element is used as a nonvolatile memory element has been proposed.
　この抵抗変化素子は、２つの電極間に、主として金属酸化物からなる材料により構成される薄膜を有している。この薄膜に、各電極より電気パルスを印加すると、その抵抗値が変化し、またその変化した後の抵抗値が電気パルスの印加をやめた後も保存される。よって、この薄膜の高抵抗状態と低抵抗状態とを、それぞれ、例えば２値データの“１”と“０”とに対応させると、抵抗変化素子に２値データを記憶させることが可能になる。また、抵抗変化素子の薄膜に印加する電気パルスの振幅やパルス幅は、薄膜の物理的な状態を変化させるには十分であり、薄膜を破壊しない程度であればよい。また、この抵抗変化素子の薄膜には、電気パルスを複数回印加してもよい。 This resistance change element has a thin film composed mainly of a metal oxide material between two electrodes. When an electric pulse is applied to the thin film from each electrode, the resistance value is changed, and the changed resistance value is preserved even after the application of the electric pulse is stopped. Therefore, when the high resistance state and the low resistance state of the thin film are associated with, for example, “1” and “0” of the binary data, the binary data can be stored in the variable resistance element. . Further, the amplitude and pulse width of the electric pulse applied to the thin film of the resistance change element are sufficient to change the physical state of the thin film, and may be any level that does not destroy the thin film. Moreover, you may apply an electrical pulse to the thin film of this resistance change element in multiple times.
　このような抵抗変化素子が、複数のワード線と複数のビット線との各々の立体交差部に複数配設されて構成する記憶装置（いわゆるクロスポイント型の記憶装置）においては、選択された抵抗変化素子にデータを書き込む際に、迂回電流により非選択の抵抗変化素子の抵抗値が変化してしまうという障害（以下、この障害を「書き込みディスターブ」という）が発生する場合がある。従って、このようなクロスポイント型の記憶装置を構成する場合には、書き込みディスターブの発生を防止するための格別な構成を設ける必要がある。 In a storage device (a so-called cross-point storage device) in which a plurality of such variable resistance elements are arranged at each three-dimensional intersection of a plurality of word lines and a plurality of bit lines, a selected resistance When writing data to the change element, there may occur a failure (hereinafter, this failure is referred to as “write disturb”) in which the resistance value of the non-selected resistance change element changes due to the bypass current. Therefore, when configuring such a cross-point type storage device, it is necessary to provide a special configuration for preventing the occurrence of write disturb.
　そこで、このような書き込みディスターブの発生を防止することが期待できる記憶装置として、記憶素子が抵抗変化素子とダイオード（電流抑制素子）との直列回路により構成されている記憶装置が提案されている（例えば、特許文献１参照）。 Therefore, as a memory device that can be expected to prevent the occurrence of such write disturbance, a memory device in which the memory element is configured by a series circuit of a resistance change element and a diode (current suppression element) has been proposed ( For example, see Patent Document 1).
　かかる提案された記憶装置では、データを書き込むべき記憶素子（選択記憶素子）以外の記憶素子において、非選択の抵抗変化素子への迂回電流が、非選択記憶素子のダイオードに逆バイアスまたはゼロバイアスを印加するよう、選択／非選択のビット線およびワード線の電圧を調整することにより阻止される。これにより、クロスポイント型の記憶装置において、書き込みディスターブ発生の防止が期待される。ここで、この提案された記憶装置では、抵抗変化素子へのデータの書き込みは、同じ極性の異なる電圧のパルスを抵抗変化素子に印加することにより行われる。すなわち、抵抗変化素子はユニポーラ型である。従って、選択された抵抗変化素子に対して直列に接続された単極性のダイオード（ある極性の閾値以上の電圧をダイオードに印加すると、順バイアスによりダイオードがオンして大電流が流れ、反対の極性の電圧を印加すると、逆バイアスによりダイオードがオフしてほとんど電流が流れない特性を有する）を順バイアスでオンさせてデータの書き込みを行い、非選択時は逆バイアスまたはゼロバイアスでオフさせて、ディスターブを防止できる。
In such a proposed memory device, in a memory element other than the memory element (selected memory element) to which data is to be written, a detour current to the non-selected resistance change element causes a reverse bias or a zero bias to the diode of the non-selected memory element. It is blocked by adjusting the voltage of the selected / unselected bit lines and word lines to apply. As a result, it is expected to prevent occurrence of write disturb in the cross-point type storage device. Here, in the proposed memory device, data is written to the variable resistance element by applying pulses of the same polarity and different voltages to the variable resistance element. That is, the variable resistance element is a unipolar type. Therefore, a unipolar diode connected in series with the selected variable resistance element (when a voltage higher than a certain threshold value is applied to the diode, the diode is turned on by forward bias, causing a large current to flow, and the opposite polarity. When the voltage is applied, the diode is turned off by reverse bias and the current hardly flows)) is written with forward bias, and when not selected, it is turned off with reverse bias or zero bias. Disturbance can be prevented.

特開２００４－３１９５８７号公報JP 2004-319587 A

　特許文献１に記載の抵抗変化素子は、上述のようにユニポーラ型であったので、単極性のダイオードを抵抗変化素子に直列に接続することにより、書き込みディスターブを防止することができた。しかしながら、抵抗変化素子には、その抵抗変化機能を有する薄膜を構成する材料に起因して、２値データの“１”と“０”とを、異なる極性の電圧パルスを薄膜に印加することにより書き込むタイプの抵抗変化素子（バイポーラ型）もある。ユニポーラ型の抵抗変化素子は、低抵抗状態から高抵抗状態に変化させる時（いわゆるリセット時）に、逆のセット時よりも長いパルス幅の電気パルス（～１μｓｅｃ）が必要であるという特性を有するものが多い。一方、バイポーラ型の抵抗変化素子は、セット・リセット時ともに短いパルス幅の電気パルス（１００ｎｓｅｃ以下）で抵抗変化が可能であり、書き込み速度の点でユニポーラ型より優れるものがある。かかる抵抗変化素子を用いる場合、抵抗変化素子に対してダイオードを直列に接続すると、一方の極性の電圧パルスはデータの書き込みに利用することができるが、他方の極性の電圧パルスはデータの書き込みに利用することはできない。従って、このようなバイポーラ型の抵抗変化素子を備えるクロスポイント型の記憶装置では、抵抗変化素子に対してショットキーダイオードのような単極性のダイオードを直列に接続することができないため、書き込みディスターブの発生を防止することができないという課題がある。
Since the variable resistance element described in Patent Document 1 was a unipolar type as described above, writing disturbance could be prevented by connecting a unipolar diode in series with the variable resistance element. However, the variable resistance element is formed by applying binary data “1” and “0” and voltage pulses having different polarities to the thin film due to the material constituting the thin film having the resistance changing function. There is also a variable resistance element (bipolar type) for writing. A unipolar variable resistance element has a characteristic that, when changing from a low resistance state to a high resistance state (so-called resetting), an electric pulse (˜1 μsec) having a longer pulse width than that in the reverse setting is required. There are many things. On the other hand, bipolar resistance change elements can change resistance with electric pulses having a short pulse width (100 nsec or less) both at the time of setting and resetting, and some are superior to the unipolar type in terms of writing speed. When such a resistance change element is used, if a diode is connected in series with the resistance change element, a voltage pulse of one polarity can be used for writing data, but a voltage pulse of the other polarity can be used for writing data. It cannot be used. Therefore, in a cross-point memory device including such a bipolar variable resistance element, a unipolar diode such as a Schottky diode cannot be connected in series to the variable resistance element. There is a problem that the occurrence cannot be prevented.
　この課題は、抵抗変化素子に対して直列に接続するダイオードに「非線形の電気抵抗特性を示し、かつ電流－電圧特性が印加電圧の極性に対して実質的に対称な素子」を用いれば解決することができる。このような特性を備える素子としては、例えば、ＭＩＭダイオード（Ｍｅｔａｌ－Ｉｎｓｕｌａｔｏｒ－Ｍｅｔａｌ；金属－絶縁体－金属の意味）、ＭＳＭダイオード（Ｍｅｔａｌ－Ｓｅｍｉｃｏｎｄｕｃｔｏｒ－Ｍｅｔａｌ；金属－半導体－金属の意味）、あるいはバリスタ等の二端子素子が知られている。これらのダイオードを、ショットキーダイオード等の単極性ダイオードに対して、双極性ダイオードと呼ぶことにする。 This problem can be solved by using a diode that is connected in series with the variable resistance element that has a non-linear electrical resistance characteristic and whose current-voltage characteristic is substantially symmetric with respect to the polarity of the applied voltage. be able to. As an element having such characteristics, for example, an MIM diode (Metal-Insulator-Metal; meaning metal-insulator-metal), an MSM diode (Metal-Semiconductor-Metal; meaning metal-semiconductor-metal), or Two-terminal elements such as varistors are known. These diodes are referred to as bipolar diodes as opposed to unipolar diodes such as Schottky diodes.
　図６は電流抑制素子の電圧－電流特性を模式的に示す特性図であって、図６（ａ）は双極性ダイオードの電圧－電流特性図であり、図６（ｂ）はショットキーダイオード等の単極性ダイオードの電圧－電流特性図である。 FIG. 6 is a characteristic diagram schematically showing the voltage-current characteristics of the current suppressing element. FIG. 6 (a) is a voltage-current characteristic diagram of a bipolar diode, and FIG. 6 (b) is a Schottky diode or the like. It is a voltage-current characteristic view of a unipolar diode.
　図６（ｂ）に示すように、単極性ダイオードは、非線形の電気抵抗特性を示すものの、その電圧－電流特性は印加電圧の極性に対して全く対称ではない。これに対して、図６（ａ）に示すように、ＭＩＭダイオード、ＭＳＭダイオード、バリスタ等の双極性ダイオードは、非線形の電気抵抗特性を示し、かつ、その電圧－電流特性は印加電圧の極性に対して実質的に対称となる。すなわち、正の印加電圧に対する電流の変化と、負の印加電圧に対する電流の変化とが、原点０に対して実質的に点対称となる。 As shown in FIG. 6B, the unipolar diode exhibits nonlinear electrical resistance characteristics, but its voltage-current characteristics are not symmetrical at all with respect to the polarity of the applied voltage. On the other hand, as shown in FIG. 6A, bipolar diodes such as MIM diodes, MSM diodes, and varistors exhibit non-linear electrical resistance characteristics, and their voltage-current characteristics depend on the polarity of the applied voltage. It is substantially symmetric with respect to it. That is, the change in current with respect to the positive applied voltage and the change in current with respect to the negative applied voltage are substantially point-symmetric with respect to the origin 0.
　また、これらの双極性ダイオードでは、印加電圧が第１の臨界電圧（範囲Ａの下限電圧）以下でありかつ第２の臨界電圧（範囲Ｂの上限電圧）以上である範囲（つまり、範囲Ｃ）では電気抵抗が非常に高く、第１の臨界電圧を超えるか、又は、第２の臨界電圧を下回ると、電気抵抗が急激に低下する。即ち、これらの二端子素子は、印加電圧が第１の臨界電圧を超えるか第２の臨界電圧を下回る場合に大電流が流れるという、非線形の電気抵抗特性を有している。 Further, in these bipolar diodes, the applied voltage is not more than the first critical voltage (lower limit voltage of range A) and not less than the second critical voltage (upper limit voltage of range B) (that is, range C). Then, the electrical resistance is very high, and when the first critical voltage is exceeded or the second critical voltage is lowered, the electrical resistance rapidly decreases. That is, these two-terminal elements have non-linear electrical resistance characteristics such that a large current flows when the applied voltage exceeds the first critical voltage or falls below the second critical voltage.
　よって、これらの双極性ダイオードをバイポーラ型の記憶素子と組み合わせ、電流抑制素子として利用することにより、バイポーラ型の抵抗変化素子を用いたクロスポイント型の記憶装置において、書き込みディスターブの発生を回避することが期待できると考えられる。 Therefore, by combining these bipolar diodes with a bipolar memory element and using it as a current suppressing element, it is possible to avoid the occurrence of write disturbance in a cross-point memory device using a bipolar variable resistance element. Can be expected.
　次に、抵抗変化素子へデータを書き込む時、抵抗変化素子に電圧パルスを印加することによりその抵抗値を変化させ、抵抗変化素子の状態を高抵抗状態或いは低抵抗状態とするためには、抵抗変化素子の材料やその構成等にも大きく依存するが、通常、抵抗変化素子に大電流を流す必要がある。例えば、抵抗変化素子の抵抗変化層として金属酸化物材料（具体的には、Ｐｒ－Ｃａ－Ｍｎ－Ｏ系材料、二酸化チタン、酸化ニッケル、酸化銅、等）を使用する場合には、少なくとも１０００μＡ／μｍ２以上の電流密度で電流を流さないと、抵抗変化素子の抵抗変化特性を得ることができない課題がある。しかし、１０００μＡ／μｍ２以上の電流密度の電流をダイオードに流そうとした場合、発熱等の影響によりダイオードがブレークダウン（所定以上の電流が流れることによって極性の異なる電圧パルスをかけても電流抑制素子が非線形の電気抵抗特性を示さなくなる現象）しやすいという課題もあらたに発生する。 Next, when data is written to the resistance change element, the resistance value is changed by applying a voltage pulse to the resistance change element, so that the resistance change element is in a high resistance state or a low resistance state. Usually, it is necessary to pass a large current through the resistance change element, although it greatly depends on the material of the change element and its configuration. For example, when a metal oxide material (specifically, a Pr—Ca—Mn—O-based material, titanium dioxide, nickel oxide, copper oxide, etc.) is used as the variable resistance layer of the variable resistance element, at least 1000 μA. There is a problem that the resistance change characteristic of the resistance change element cannot be obtained unless a current is passed at a current density of / μm 2 or more. However, when an electric current with a current density of 1000 μA / μm 2 or more is applied to the diode, the diode breaks down due to the influence of heat generation or the like. There is a new problem that the device is more likely to have a non-linear electrical resistance characteristic.
　また、クロスポイント構造を有する抵抗変化素子へデータを書き込むとき、記憶素子において、データを書き込むべき記憶素子（以下、選択記憶素子という）には、オン電圧を印加し、データを書き込まない記憶素子（以下、非選択記憶素子という）には、オフ電圧を印加する。例えば、抵抗変化素子の抵抗変化層として金属酸化物材料（具体的には、ＰＲＰｒ－Ｃａ－Ｍｎ－Ｏ系材料、二酸化チタン、酸化ニッケル、酸化銅、等）を使用する場合には、選択記憶素子には２．０Ｖの印加電圧、すなわちオン電圧が２．０Ｖが必要であり、非選択記憶素子には１．０Ｖの印加電圧、すなわちオフ電圧が１．０Ｖが必要である。バイポーラ型の抵抗変化素子を用いたクロスポイント型の記憶装置において、書き込みディスターブの発生を確実に回避し、さらにセンスアンプによる読み出し時の、読み出しマージンを大きくするためには、このオン電圧時に流れる電流（以下、この電流を「オン電流」という）とオフ電圧時に流れる電流（以下、この電流を「オフ電流」という）の差が大きい方が好ましい。ここで、オフ電流に対するオン電流の比、すなわちオン電流をオフ電流で割ったオン／オフ電流比（以下、この比を「オン／オフ電流比」という）を定義すると、オン／オフ電流比が大きければ大きい程よく、実デバイスの動作上は、オン／オフ電流比は少なくとも５０以上必要である課題がある。 In addition, when data is written to a resistance change element having a cross-point structure, a storage element that does not write data by applying an on-voltage to a storage element in which data is to be written (hereinafter referred to as a selected storage element). Hereinafter, an off-voltage is applied to the non-selected memory element. For example, when a metal oxide material (specifically, PRPr—Ca—Mn—O-based material, titanium dioxide, nickel oxide, copper oxide, etc.) is used as the resistance change layer of the resistance change element, selective memory is used. The element requires an applied voltage of 2.0 V, that is, an on voltage of 2.0 V, and the non-selected memory element requires an applied voltage of 1.0 V, that is, an off voltage of 1.0 V. In a cross-point type memory device using a bipolar variable resistance element, in order to reliably avoid the occurrence of write disturb and to increase the read margin when reading by the sense amplifier, the current flowing at this on-voltage It is preferable that the difference between the current that flows during the off-voltage (hereinafter, this current is referred to as “off-current”) is large. Here, the ratio of the on-current to the off-current, that is, the on-off current ratio obtained by dividing the on-current by the off-current (hereinafter, this ratio is referred to as “on / off-current ratio”) is defined as The larger it is, the better. In the operation of an actual device, there is a problem that the on / off current ratio is at least 50 or more.
　本発明は、上記従来の課題を解決するためになされたものであって、バイポーラ型の抵抗変化素子に直列に接続させる電流抑制素子において、抵抗変化素子の抵抗変化に必要である１０００μＡ／μｍ２以上の電流を流すと共に、オン／オフ電流比が少なくとも５０以上となることを実現して、書き込みディスターブの発生の防止と読み出しマージンの拡大が期待できる不揮発性記憶素子、およびそれを備える記憶装置を提供することを目的とするものである。
The present invention has been made to solve the above-described conventional problems, and is a current suppressing element connected in series to a bipolar variable resistance element, and is necessary for the resistance change of the variable resistance element, 1000 μA / μm 2. A non-volatile memory element capable of flowing the above current and realizing an on / off current ratio of at least 50 to prevent occurrence of a write disturbance and increase a read margin, and a memory device including the same It is intended to provide.

　上記課題を解決するために、本発明に係る記憶素子は、極性が正又は負の電気パルスの印加によりその電気抵抗値が変化し、また変化した後の電気抵抗値を維持する抵抗変化素子と、前記抵抗変化素子に前記電気パルスの印加時に流れる電流を抑制する電流抑制素子と、を備える記憶素子であって、前記電流抑制素子は、第１の導電体層と、前記第１の導電体層の上に備える半導体層と、前記半導体層の上に構える第２の導電体層とを備え、前記第１の導電体層または第２の導電体層がタンタルと窒素を含有するタンタル窒化物で構成され、また前記半導体層がシリコンと窒素を含有するシリコン窒化物で構成され、前記第１または第２の導電体層を形成するタンタル窒化物をＴａＮＸと表記した場合に、０．５≦ｘ≦１．６７であることを特徴とする。

　前記電流抑制素子の導電体層に用いられるタンタル窒化物は、半導体分野において、銅配線のバリア層として使用実績のある材料であり、また、前記電流抑制素子の半導体層に用いられるシリコン窒化物も使用実績のある材料である。したがって、これらの材料を用いて電流抑制素子を構成すれば、電流抑制素子を作製する半導体製造ラインの保守保全や、成膜あるいはエッチング等に関する既存の設備あるいは処理条件の転用が容易であり、生産性に優れた記憶素子を提供することが可能になる。
In order to solve the above problems, a memory element according to the present invention includes a resistance change element that changes its electrical resistance value by applying a positive or negative electric pulse, and maintains the electric resistance value after the change. And a current suppressing element that suppresses a current that flows when the electric pulse is applied to the variable resistance element, wherein the current suppressing element includes a first conductor layer and the first conductor. A tantalum nitride comprising a semiconductor layer provided on the layer and a second conductor layer provided on the semiconductor layer, wherein the first conductor layer or the second conductor layer contains tantalum and nitrogen And the semiconductor layer is made of silicon nitride containing silicon and nitrogen, and the tantalum nitride forming the first or second conductor layer is expressed as TaN X. ≦ x ≦ 1.67 Features.

The tantalum nitride used for the conductor layer of the current suppressing element is a material that has been used as a barrier layer for copper wiring in the semiconductor field, and the silicon nitride used for the semiconductor layer of the current suppressing element is also It is a material with a track record of use. Therefore, if a current suppressing element is constructed using these materials, it is easy to maintain and maintain the semiconductor production line for producing the current suppressing element, and to divert existing equipment or processing conditions relating to film formation or etching. It is possible to provide a memory element that is excellent in performance.
　さらには、第１の導電体層または第２の導電体層に用いられるタンタル窒化物は、Ｔａ２Ｎ，あるいはＴａ３Ｎ５であることが、より好ましい。 Further, the tantalum nitride used for the first conductor layer or the second conductor layer is more preferably Ta 2 N or Ta 3 N 5 .
　本発明に係る記憶装置は、本発明に係る上述した記憶素子を複数備え、複数のビット線と、前記複数のビット線に各々立体交差する複数のワード線と、を備え、前記記憶素子は前記抵抗変化素子と前記電流抑制素子との直列回路を備え、前記複数の記憶素子が、前記ビット線と前記ワード線とが立体交差する各々の部分に配設され、前記各々の部分において、前記直列回路の一端がその対応する前記ビット線に、前記直列回路の他端がその対応する前記ワード線に、各々接続されている。 A storage device according to the present invention includes a plurality of the above-described storage elements according to the present invention, and includes a plurality of bit lines and a plurality of word lines that three-dimensionally intersect the plurality of bit lines, A series circuit of a resistance change element and the current suppressing element, wherein the plurality of storage elements are disposed in each portion where the bit line and the word line intersect three-dimensionally; One end of the circuit is connected to the corresponding bit line, and the other end of the series circuit is connected to the corresponding word line.
　かかる構成とすることにより、上述した本発明に係る記憶素子を備えているので、記憶装置における電子回路、あるいは、記憶素子の動作方法に追加回路や追加動作を加えることなく、書き込みディスターブがなく、読み出しマージンの広い好適な記憶装置を提供することが可能になる。

　本発明の上記目的、他の目的、特徴、及び利点は、添付図面参照の下、以下の好適な実施態様の詳細な説明から明らかにされる。
With such a configuration, since the memory element according to the present invention described above is provided, there is no write disturb without adding an additional circuit or an additional operation to the electronic circuit in the memory device or the operation method of the memory element, A suitable storage device with a wide read margin can be provided.

The above object, other objects, features, and advantages of the present invention will become apparent from the following detailed description of the preferred embodiments with reference to the accompanying drawings.

　本発明における記憶素子及び記憶装置の構成は、極性の異なる電気パルスを印加して抵抗変化を起こさせるバイポーラ型の抵抗変化素子に、本発明にかかるＭＳＭ型の電流抑制素子を組み合わせることにより、抵抗変化素子の抵抗変化に必要である１０００μＡ／μｍ２以上の電流を流すと共にブレークダウンの発生を抑制し、かつオン／オフ電流比が少なくとも５０以上となることを実現でき、書き込みディスターブの発生を防止と読み出しマージンの拡大が期待できる電流抑制素子を有する記憶素子、及び、それを備える記憶装置を提供することができるという効果を奏する。
The configuration of the memory element and the memory device according to the present invention includes a bipolar resistance change element that causes a resistance change by applying electric pulses having different polarities, and combines an MSM type current suppression element according to the present invention with a resistance. A current of 1000 μA / μm 2 or more necessary to change the resistance of the change element is allowed to flow, a breakdown is suppressed, and an on / off current ratio of at least 50 can be realized, thereby preventing a write disturbance. As a result, it is possible to provide a memory element having a current suppressing element that can be expected to increase a read margin, and a memory device including the memory element.

図１は、抵抗変化素子を記憶素子として備える本発明の記憶装置の構成を模式的に示すブロック図である。FIG. 1 is a block diagram schematically showing a configuration of a memory device of the present invention including a resistance change element as a memory element. 図２は、本発明の電流抑制素子の実施形態に係る構成を模式的に示す断面図である。FIG. 2 is a cross-sectional view schematically showing a configuration according to the embodiment of the current suppressing element of the present invention. 図３は、本発明の実施の形態に係る電流抑制素子の電圧－電流特性を示す図である。FIG. 3 is a diagram showing voltage-current characteristics of the current suppressing element according to the embodiment of the present invention. 図４は、本発明の実施の形態に係る第１および第２の導電体層であるタンタル窒化物のＴａに対するＮの比ｘと、図３の電圧－電流特性から導出されたブレークダウン電流との関係を示す図である。4 shows the ratio x of N to Ta of tantalum nitride, which is the first and second conductor layers according to the embodiment of the present invention, and the breakdown current derived from the voltage-current characteristics of FIG. It is a figure which shows the relationship. 図５は、本発明の実施の形態に係る第１および第２の導電体層であるタンタル窒化物のＴａに対するＮの比ｘと、図３の電圧－電流特性から導出されたオン／オフ電流比との関係を示す図である。FIG. 5 shows the ratio of N to Ta of tantalum nitride, which is the first and second conductor layers according to the embodiment of the present invention, and the on / off current derived from the voltage-current characteristics of FIG. It is a figure which shows the relationship with ratio. 図６は、電流抑制素子の電圧－電流特性を模式的に示す特性図であり、（ａ）バリスタ等の二端子素子の特性図（ｂ）ショットキーダイオードの特性図である。FIG. 6 is a characteristic diagram schematically showing the voltage-current characteristics of the current suppressing element, (a) a characteristic chart of a two-terminal element such as a varistor, and (b) a characteristic chart of a Schottky diode.

　以下、本発明を実施するための最良の形態について、図面を参照しながら詳細に説明する。
Hereinafter, the best mode for carrying out the present invention will be described in detail with reference to the drawings.
　図１は、本発明の実施の形態に係る双極性の電流抑制素子とバイポーラ型抵抗変化素子を直列に配設した記憶素子をアレイ状に備える記憶装置の構成を模式的に示すブロック図である。尚、図１では、本発明を説明するために必要となる構成要素のみを図示し、その他の構成要素については図示を省略している。 FIG. 1 is a block diagram schematically showing a configuration of a storage device including storage elements arranged in series with bipolar current suppressing elements and bipolar variable resistance elements according to an embodiment of the present invention. . In FIG. 1, only the components necessary for explaining the present invention are shown, and the other components are not shown.
　図１に示すように、本実施の形態に係る記憶装置２１は、いわゆるクロスポイント型の記憶装置である。そして、この記憶装置２１は、記憶素子アレイ２０と、この記憶素子アレイ２０を駆動するための周辺回路（後述する、ビット線デコーダ４、読み出し回路５、ワード線デコーダ６，７）とを構成している。 As shown in FIG. 1, the storage device 21 according to the present embodiment is a so-called cross-point storage device. The storage device 21 configures a storage element array 20 and peripheral circuits (a bit line decoder 4, a read circuit 5, and word line decoders 6 and 7 described later) for driving the storage element array 20. ing.
　実際の記憶素子アレイは、通常、複数のビット線と複数のワード線とを有しているが、本明細書では、図１に示すように、記憶素子アレイの構成を容易に理解可能とするために、４本のビット線ＢＬ０～ＢＬ３と４本のワード線ＷＬ０～ＷＬ３とを備える記憶素子アレイ２０を例示している。 An actual storage element array usually has a plurality of bit lines and a plurality of word lines, but in this specification, as shown in FIG. 1, the configuration of the storage element array can be easily understood. For this purpose, the storage element array 20 including four bit lines BL0 to BL3 and four word lines WL0 to WL3 is illustrated.
　本実施の形態に係る記憶素子アレイ２０では、４本のビット線ＢＬ０～ＢＬ３と、４本のワード線ＷＬ０～ＷＬ３とが、互いに直角に立体交差するように配設されている。そして、これらの４本のビット線ＢＬ０～ＢＬ３と４本のワード線ＷＬ０～ＷＬ３との立体交差部１１の各々には、記憶素子３（所謂、セル）が配設されている。 In the memory element array 20 according to the present embodiment, the four bit lines BL0 to BL3 and the four word lines WL0 to WL3 are arranged so as to three-dimensionally intersect each other at right angles. A storage element 3 (so-called cell) is disposed in each of the three-dimensional intersections 11 between the four bit lines BL0 to BL3 and the four word lines WL0 to WL3.
　言い換えれば、本実施の形態に係る記憶素子アレイ２０では、記憶素子３が４行４列のマトリクス状に配設されている。ここで、記憶素子３の各々は、抵抗変化素子１と、この抵抗変化素子１に対して直列に接続された電流抑制素子２との直列回路により構成されている。そして、この直列回路の一端及び他端が、各々、その立体交差部１１に対応するビット線ＢＬ０～ＢＬ３及びワード線ＷＬ０～ＷＬ３に接続されている。 In other words, in the memory element array 20 according to the present embodiment, the memory elements 3 are arranged in a matrix of 4 rows and 4 columns. Here, each of the memory elements 3 is constituted by a series circuit of a resistance change element 1 and a current suppression element 2 connected in series to the resistance change element 1. One end and the other end of the series circuit are connected to the bit lines BL0 to BL3 and the word lines WL0 to WL3 corresponding to the solid intersection 11 respectively.
　そして、図１に示すように、４本のビット線ＢＬ０～ＢＬ３の一端が、ビット線デコーダ４に接続されている。又、ビット線ＢＬ０～ＢＬ３の他端が、読み出し回路５に接続されている。一方、４本のワード線ＷＬ０～ＷＬ３の両端が、ワード線デコーダ６，７に接続されている。 As shown in FIG. 1, one end of each of the four bit lines BL0 to BL3 is connected to the bit line decoder 4. The other ends of the bit lines BL0 to BL3 are connected to the read circuit 5. On the other hand, both ends of the four word lines WL0 to WL3 are connected to the word line decoders 6 and 7, respectively.
　このように、２つのワード線デコーダ６，７をワード線ＷＬ０～ＷＬ３の両端に配設することにより、例えば、偶数番目のワード線をワード線デコーダ６に接続し、奇数番目のワード線をワード線デコーダ７に接続するというように、ワード線ＷＬ０～ＷＬ３をワード線デコーダ６とワード線デコーダ７とに交互に接続することができる。本実施の形態では、図１では具体的には図示してはいないが、このような接続形態が採用されている。かかる構成とすることにより、ワード線ＷＬ０～ＷＬ３の間隔を小さくすることができると共に、ワード線デコーダ６，７の回路配置に関する自由度を大きくすることができる。 Thus, by disposing the two word line decoders 6 and 7 at both ends of the word lines WL0 to WL3, for example, the even-numbered word lines are connected to the word line decoder 6 and the odd-numbered word lines are connected to the word lines. The word lines WL0 to WL3 can be alternately connected to the word line decoder 6 and the word line decoder 7 so as to be connected to the line decoder 7. In the present embodiment, although not specifically shown in FIG. 1, such a connection form is adopted. With this configuration, the interval between the word lines WL0 to WL3 can be reduced, and the degree of freedom regarding the circuit arrangement of the word line decoders 6 and 7 can be increased.
　かかる記憶装置２１では、ビット線デコーダ４が、制御器（図示せず）からの指令に応じて、ビット線ＢＬ０～ＢＬ３を選択する。又、ワード線デコーダ６，７は、制御器からの指令に応じて、ワード線ＷＬ０～ＷＬ３を選択する。そして、ビット線デコーダ４とワード線デコーダ６，７とは、制御器からの指令がデータの書き込みであるか、またはデータの読み出しであるかに応じて、ビット線ＢＬ０～ＢＬ３における選択されたビット線とワード線ＷＬ０～ＷＬ３における選択されたワード線との間に、その電圧が所定の書き込み電圧Ｖｗである電気パルス（正確には、電圧パルス）、またはその電圧が所定の読み出し電圧Ｖｒである電気パルス（正確には、電圧パルス）を印加する。一方、読み出し時、読み出し回路５は、ビット線ＢＬ０～ＢＬ３における選択されたビット線に流れる電流値を検出して、選択された記憶素子３に記憶されたデータを読み出し、これを制御器に向けて出力する。ここで、図２に示すビット線デコーダ４、読み出し回路５、ワード線デコーダ６，７等の周辺回路は、例えば、ＭＯＳＦＥＴにより構成される。又、記憶装置２１は、通常、半導体の製造プロセスにより作製される。 In such a storage device 21, the bit line decoder 4 selects the bit lines BL0 to BL3 in response to a command from a controller (not shown). Further, the word line decoders 6 and 7 select the word lines WL0 to WL3 in accordance with a command from the controller. The bit line decoder 4 and the word line decoders 6 and 7 select the selected bit on the bit lines BL0 to BL3 depending on whether the command from the controller is data writing or data reading. An electric pulse whose voltage is a predetermined write voltage Vw (more precisely, a voltage pulse) or a predetermined read voltage Vr between the line and a selected word line in the word lines WL0 to WL3 An electric pulse (more precisely, a voltage pulse) is applied. On the other hand, at the time of reading, the reading circuit 5 detects the current value flowing through the selected bit line in the bit lines BL0 to BL3, reads the data stored in the selected storage element 3, and directs this to the controller. Output. Here, peripheral circuits such as the bit line decoder 4, the read circuit 5, and the word line decoders 6 and 7 shown in FIG. The storage device 21 is usually manufactured by a semiconductor manufacturing process.
　次に、本実施の形態に係る抵抗変化素子の構成について詳細に説明する。 Next, the configuration of the variable resistance element according to the present embodiment will be described in detail.
　図１に示す抵抗変化素子１は、対向する一対の電極層（図示せず）の間に抵抗変化材料からなる薄膜（以下、この薄膜を「抵抗変化薄膜」という）が配設され構成されている。この抵抗変化薄膜に、前記一対の対抗電極より所定の電気パルスを印加すると、低抵抗状態と高抵抗状態との間で、前記一対の対抗電極間の抵抗値が遷移する。ここで、この抵抗変化薄膜は、所定の電気パルスを印加しない限り、その遷移した後の状態を維持する。本実施の形態では、この低抵抗状態と高抵抗状態とに、各々、２値データの“０”及び“１”の何れか一方及び他方が割り当てられており、抵抗変化薄膜の状態を低抵抗状態と高抵抗状態との間で遷移させるために、極性の異なる電気パルスを印加する。このような、抵抗変化薄膜を構成するための抵抗変化材料としては、ペロブスカイト型遷移金属酸化物や、典型金属又は遷移金属の酸化物等を用いることができる。 A resistance change element 1 shown in FIG. 1 includes a thin film made of a resistance change material (hereinafter referred to as a “resistance change thin film”) between a pair of opposed electrode layers (not shown). Yes. When a predetermined electric pulse is applied to the resistance change thin film from the pair of counter electrodes, the resistance value between the pair of counter electrodes transitions between a low resistance state and a high resistance state. Here, this resistance change thin film maintains the state after the transition unless a predetermined electric pulse is applied. In this embodiment, one of the binary data “0” and “1” and the other is assigned to the low resistance state and the high resistance state, respectively, and the state of the resistance change thin film is set to the low resistance state. In order to transition between the state and the high resistance state, electric pulses having different polarities are applied. As such a resistance change material for constituting the resistance change thin film, a perovskite type transition metal oxide, a typical metal or an oxide of a transition metal, or the like can be used.
　具体的には、抵抗変化薄膜を構成するための抵抗変化材料としては、Ｐｒ（１－ｘ）ＣａｘＭｎＯ３（０＜ｘ＜１）、ＴｉＯ２、ＮｉＯｘ（ｘ＞０）、ＣｕｘＯ（ｘ＞０）等や、これらの置換体、又は、これらの混合物や積層構造物等が挙げられる。また抵抗変化材料は、これらの抵抗変化材料に限定されることはない。 Specifically, as the resistance change material for forming the resistance change thin film, Pr (1-x) Ca x MnO 3 (0 <x <1), TiO 2 , NiO x (x> 0), Cu x O (x> 0) or the like, substitution products thereof, a mixture or a laminated structure thereof, or the like can be given. The resistance change material is not limited to these resistance change materials.
　次に、本実施の形態に係る電流抑制素子の構成について詳細に説明する。電流抑制素子は、対向する一対の導電体層の間に半導体層を配設することにより構成している。この構成は先に述べたＭＳＭダイオードと同じ構成であり、非線形の電気抵抗特性を示し、かつ電流－電圧特性が印加電圧の極性に対して実質的に対称となるため、極性の異なる電気パルスを印加する場合でも書き込みディスターブの発生を防止することが可能である。電流抑制素子の電流－電圧特性は、導電体層と導電体層に隣接する半導体層との間に形成される電位障壁に大きく依存し、電位障壁が整流性を示すことにより非線形の電気抵抗特性が得られ、また電位障壁の高さを制御することにより、電流抑制素子が大電流を流すことができるようになるものである。 Next, the configuration of the current suppressing element according to the present embodiment will be described in detail. The current suppressing element is configured by disposing a semiconductor layer between a pair of opposing conductor layers. This configuration is the same as the MSM diode described above, exhibits nonlinear electrical resistance characteristics, and the current-voltage characteristics are substantially symmetric with respect to the polarity of the applied voltage. Even when it is applied, it is possible to prevent the occurrence of write disturb. The current-voltage characteristic of the current suppression element depends greatly on the potential barrier formed between the conductor layer and the semiconductor layer adjacent to the conductor layer, and the potential barrier exhibits a rectifying property. In addition, by controlling the height of the potential barrier, the current suppressing element can pass a large current.
　以下、本実施の形態に係る電流抑制素子の具体的な構成について、図面を参照しながら詳細に説明する。 Hereinafter, a specific configuration of the current suppressing element according to the present embodiment will be described in detail with reference to the drawings.
　図２は、本発明の実施の形態に係る電流抑制素子の構成を模式的に示す断面図である。 FIG. 2 is a cross-sectional view schematically showing the configuration of the current suppressing element according to the embodiment of the present invention.
　図２に示すように、電流抑制素子２は、第１の導電体層３１と、第２の導電体層３２と、これらの第１及び第２の導電体層３１，３２の間に配設された半導体層３３とにより構成されている。ここで、第１および第２の導電体層３１，３２は、タンタル（Ｔａ）と窒素（Ｎ）を含有するタンタル窒化物を含み、半導体層３３は、シリコン（Ｓｉ）と窒素（Ｎ）を含有するシリコン窒化物を含む。 As shown in FIG. 2, the current suppressing element 2 is disposed between the first conductor layer 31, the second conductor layer 32, and the first and second conductor layers 31 and 32. The semiconductor layer 33 is formed. Here, the first and second conductor layers 31 and 32 include tantalum nitride containing tantalum (Ta) and nitrogen (N), and the semiconductor layer 33 includes silicon (Si) and nitrogen (N). Contains silicon nitride.
　タンタル窒化物は、Ｔａに対するＮの比（以下、この組成比を「ｘ」という）の小さい順から、ＴａＮ０．１（ｘ＝０．１）、Ｔａ２Ｎ（ｘ＝０．５）、ＴａＮ（ｘ＝１）、Ｔａ５Ｎ６（ｘ＝１．２）、Ｔａ４Ｎ５（ｘ＝１．２５）、Ｔａ３Ｎ５（ｘ＝１．６７）、ＴａＮ２（ｘ＝２）が挙げられる。タンタル窒化物は、前記７種類の様に、Ｔａに対するＮの比が異なった組成を持つ化合物を有することから、仕事関数の制御が容易であり、半導体層３３との間に形成される電位障壁の制御が容易であるといった利点を有する。特に、タンタル窒化物を第１および第２の導電体層３１，３２として使用することは、化合物中のＮの組成を変化させることにより、その物性を連続的に変化させることが可能であるため、より好ましい。 The tantalum nitride is composed of TaN 0.1 (x = 0.1), Ta 2 N (x = 0.5), in ascending order of the ratio of N to Ta (hereinafter, this composition ratio is referred to as “x”). TaN (x = 1), Ta 5 N 6 (x = 1.2), Ta 4 N 5 (x = 1.25), Ta 3 N 5 (x = 1.67), TaN 2 (x = 2) Is mentioned. Since the tantalum nitride has a compound having a composition in which the ratio of N to Ta is different as in the above seven types, the work function can be easily controlled and the potential barrier formed between the semiconductor layer 33 and the tantalum nitride. There is an advantage that the control of is easy. In particular, the use of tantalum nitride as the first and second conductor layers 31 and 32 allows the physical properties to be continuously changed by changing the composition of N in the compound. More preferable.
　第１および第２の導電体層３１，３２を構成するタンタル窒化物ＴａＮＸにおいて、Ｘの値が互いに異なる複数のＴａＮＸの相が混在することによりそれぞれの結晶相の中間の値を実現できる。 In the tantalum nitride TaN X constituting the first and second conductor layers 31 and 32, an intermediate value of each crystal phase can be realized by mixing a plurality of TaN X phases having different X values. .
　半導体層３３であるＳｉとＮを含有する材料は、いわゆるシリコン窒化物のことを示す。シリコン窒化物は、四配位の結合を形成するテトラヘドラル系アモルファス半導体を形成し、テトラヘドラル系アモルファス半導体は基本的には単結晶シリコンやゲルマニウムに近い構造をもっているため、Ｓｉ以外の元素を導入することによる構造の違いが物性に反映されやすいという特徴を有する。このため、シリコン窒化物を半導体層３３に適用すれば、シリコン窒化物の構造制御により半導体層３３の物性を制御することが容易で、従ってこれにより第１及び第２の導電体層３１，３２との間に形成される電位障壁の制御がより容易となるといった利点を有する。 The material containing Si and N which is the semiconductor layer 33 indicates so-called silicon nitride. Silicon nitride forms a tetrahedral amorphous semiconductor that forms a four-coordinate bond, and the tetrahedral amorphous semiconductor basically has a structure close to single crystal silicon or germanium, so elements other than Si must be introduced. It has the feature that the difference in structure due to is easily reflected in the physical properties. Therefore, if silicon nitride is applied to the semiconductor layer 33, it is easy to control the physical properties of the semiconductor layer 33 by controlling the structure of the silicon nitride, and accordingly, the first and second conductor layers 31 and 32 are thereby controlled. There is an advantage that the control of the potential barrier formed between the two becomes easier.
　さらに、第１および第２の導電体層３１，３２で適用されているタンタル窒化物は銅配線のバリア層として適用されていることや、半導体層３３で適用されているシリコン窒化物は半導体の製造工程において極一般的に使用される材料であることを踏まえると、タンタル窒化物およびシリコン窒化物は、半導体製造ラインの導入に起因する新たな不純物汚染の発生はなく、半導体製造ラインの保守保全上好ましい材料である。又、加工面では、成膜あるいはエッチング等に関して既存の設備の転用が容易であり、加工条件についても既存の成膜あるいはエッチング条件の転用で対応可能である、という利点を有する。 Furthermore, the tantalum nitride applied in the first and second conductor layers 31 and 32 is applied as a barrier layer for copper wiring, and the silicon nitride applied in the semiconductor layer 33 is a semiconductor layer. Considering that it is a material that is very commonly used in the manufacturing process, tantalum nitride and silicon nitride do not cause new impurity contamination due to the introduction of the semiconductor manufacturing line, and maintenance and maintenance of the semiconductor manufacturing line It is a preferable material. In addition, on the processing surface, there is an advantage that the existing equipment can be easily transferred with respect to film formation or etching, and the processing conditions can be accommodated by using the existing film formation or etching conditions.
　本願の発明者らは、第１および第２の導電体層３１，３２であるタンタル窒化物の組成を制御することにより、電流抑制素子２に、抵抗変化素子に大電流を流せる、すなわち１０００μＡ／μｍ２以上の電流密度で電流を流すことが可能であり（ブレークダウン電流が１０００μＡ／μｍ２以上）、オン／オフ電流比を少なくとも５０以上を実現すること
が可能であることを見い出した。 The inventors of the present application can control the composition of the tantalum nitride that is the first and second conductor layers 31 and 32 to allow a large current to flow through the resistance change element, that is, 1000 μA / It has been found that a current can flow at a current density of μm 2 or more (breakdown current is 1000 μA / μm 2 or more), and an on / off current ratio of at least 50 can be realized.
　本実施の形態において、第１および第２の導電体層３１，３２を、膜厚５０ｎｍである金属Ｔａとタンタル窒化物ＴａＮ０．１、Ｔａ２Ｎ、Ｔａ３Ｎ５の４種で構成し、半導体層３３を膜厚１０ｎｍであるシリコン窒化物ＳｉＮ０．３に構成し、電流抑制素子２を作製した。このとき、Ｔａ、ＴａＮ０．１、Ｔａ２Ｎ、Ｔａ３Ｎ５のＴａに対するＮの比、いわゆるＴａＮＸにおけるｘは、順にｘ＝０、０．１、０．５、１．６７である。 In the present embodiment, the first and second conductor layers 31 and 32 are composed of four types of metal Ta and tantalum nitride TaN 0.1 , Ta 2 N, Ta 3 N 5 having a film thickness of 50 nm. The semiconductor layer 33 was made of silicon nitride SiN 0.3 having a thickness of 10 nm, and the current suppressing element 2 was produced. At this time, the ratio of N to Ta of Ta, TaN 0.1 , Ta 2 N, Ta 3 N 5 , so-called TaN X , is x = 0, 0.1, 0.5, 1.67 in order. .
　第１および第２の導電体層３１，３２であるタンタル窒化物成膜は、反応性スパッタリングを用いており、スパッタリングで用いる不活性ガスＡｒと、窒化物形成における反応ガスＮ２を同時に真空装置に流しながら、室温にて成膜を行なった。本実施の形態では、不活性ガスＡｒと反応ガスＮ２を、ＴａではＡｒ／Ｎ２＝４５／０ｓｃｃｍ、ＴａＮ０．１ではＡｒ／Ｎ２＝４５／７ｓｃｃｍ、Ｔａ２ＮではＡｒ／Ｎ２＝４５／１８ｓｃｃｍ、Ｔａ３Ｎ５ではＡｒ／Ｎ２＝４５／２４ｓｃｃｍを各適用し、５０ｎｍ膜厚の成膜を実施した。また反応ガスＮ２を２５ｓｃｃｍ以上に適用しスパッタリングを試みたが、装置上のスペックにおいて放電せず、成膜が不可能であった。そのため、Ｔａに対するＮの比ｘが１．６７以上である（ｘ＞１．６７）タンタル窒化膜の作製は困難であった。 The tantalum nitride film forming the first and second conductor layers 31 and 32 uses reactive sputtering, and an inert gas Ar used in sputtering and a reactive gas N 2 in nitride formation are simultaneously vacuumed. The film was formed at room temperature while flowing through. In this embodiment, the inert gas Ar and the reaction gas N 2, the Ta Ar / N 2 = 45 / 0sccm, the TaN 0.1 Ar / N 2 = 45 / 7sccm, Ta 2 in N Ar / N 2 = 45/18 sccm, and for Ta 3 N 5 , Ar / N 2 = 45/24 sccm was applied, and a film having a thickness of 50 nm was formed. Sputtering was attempted by applying the reactive gas N 2 to 25 sccm or more, but discharge did not occur in the specifications on the apparatus, and film formation was impossible. Therefore, it is difficult to produce a tantalum nitride film in which the ratio x of N to Ta is 1.67 or more (x> 1.67).
　また、本実施の形態の導電体層３１，３２である各タンタル窒化物は、Ｘ線回折において組成およびその結晶構造を導出し、膜厚や膜表面形状は、走査型電子顕微鏡にて確認した。各タンタル窒化物の電気抵抗率は、シート抵抗値測定機から測定された値から、電気抵抗率を導出した。 In addition, each tantalum nitride which is the conductor layers 31 and 32 of the present embodiment derived the composition and crystal structure in X-ray diffraction, and the film thickness and film surface shape were confirmed with a scanning electron microscope. . The electrical resistivity of each tantalum nitride was derived from the value measured from the sheet resistance measuring machine.
　本実施の形態の半導体層３３であるシリコン窒化物の成膜は、反応性スパッタリングを用いており、スパッタリングで用いる不活性ガスＡｒと、窒化物形成における反応ガスＮ２を同時に真空装置に流しながら、室温にて成膜を行なった。また本実施の形態の半導体層であるシリコン窒化物、ＳｉＮ０．３の、Ｓｉに対するＮの比は、ラザフォード後方散乱分光により求めた。シリコン窒化物層の膜厚はエリプソメトリー分光法を用いて確認した。またシリコン窒化物膜の表面形状は、走査型電子顕微鏡にて確認した。 The film formation of silicon nitride, which is the semiconductor layer 33 of the present embodiment, uses reactive sputtering, and the inert gas Ar used for sputtering and the reactive gas N 2 for forming nitride are simultaneously supplied to the vacuum apparatus. Film formation was performed at room temperature. Further, the ratio of N to Si of silicon nitride, SiN 0.3 , which is the semiconductor layer of the present embodiment, was obtained by Rutherford backscattering spectroscopy. The film thickness of the silicon nitride layer was confirmed using ellipsometry spectroscopy. The surface shape of the silicon nitride film was confirmed with a scanning electron microscope.
　以上により、基板上に第１の導電体層３１である膜厚５０ｎｍのタンタル窒化物を反応性スパッタリングで成膜し、その上に半導体層３３である膜厚１０ｎｍのシリコン窒化物を反応性スパッタリングで成膜し、その上に第２の導電体層３２である膜厚５０ｎｍのタンタル窒化物を反応性スパッタリングで成膜し、その後に通常のリソグラフィおよびドライエッチを適用することにより、導電体層の面積が０．４６μｍ×０．４６μｍである電流抑制素子２を作製した。 As described above, a tantalum nitride film having a thickness of 50 nm as the first conductor layer 31 is formed on the substrate by reactive sputtering, and a silicon nitride film having a thickness of 10 nm as the semiconductor layer 33 is formed thereon by reactive sputtering. A film of tantalum nitride having a thickness of 50 nm, which is the second conductor layer 32, is formed thereon by reactive sputtering, and then a normal lithography and dry etching are applied to the conductor layer. The current suppression element 2 having an area of 0.46 μm × 0.46 μm was produced.
　図３は、第１および第２の導電体層３１，３２を膜厚５０ｎｍのＴａ、ＴａＮ０．１、Ｔａ２Ｎ、Ｔａ３Ｎ５の各タンタル窒化物で構成し、半導体層３３を膜厚１０ｎｍのＳｉＮ０．３であるシリコン窒化物で構成し、導電体層の面積が０．４６μｍ×０．４６μｍである、４種類の電流抑制素子２の電流－電圧特性を実験的に求めたものである。 In FIG. 3, the first and second conductor layers 31 and 32 are made of Ta, TaN 0.1 , Ta 2 N, and Ta 3 N 5 tantalum nitride having a film thickness of 50 nm, and the semiconductor layer 33 is formed as a film. The current-voltage characteristics of the four types of current suppressing elements 2 that were made of silicon nitride having a thickness of SiN 0.3 of 10 nm and whose conductor layer area was 0.46 μm × 0.46 μm were experimentally obtained. Is.
　図３より、第１及び第２の導電体層３１，３２をタンタル窒化物で構成し、半導体層３３をシリコン窒化物で構成した電流抑制素子２は、非線形の電気抵抗特性を示している。また、第１および第２の導電体層３１，３２であるタンタル窒化物の、Ｔａに対するＮの比ｘが大きくなるにつれ、どの電圧範囲においても、電流が多く流れていることが確認できる。特に、Ｔａに対するＮの比ｘが０．５および１．６７である、いわゆるＴａ２ＮおよびＴａ３Ｎ５を第１および第２の導電体層３１，３２とする電流抑制素子２は、Ｔａに対するＮの比ｘが０および０．１である、いわゆるＴａおよびＴａＮ０．１を第１および第２の導電体層３１，３２とする電流抑制素子２よりも、格別に電流が多く流れていることが確認できる。この事実から、Ｔａに対するＮの比ｘが、０．５≦ｘ≦１．６７であるタンタル窒化物を第１および第２の導電体層３１，３２とすることが望ましいことがわかる。また図３を見ると、第１および第２の導電体層３１，３２であるタンタル窒化物の、Ｔａに対するＮの比ｘが大きくなるにつれ、ブレークダウン（所定以上の電流が流れることによって極性の異なる電圧パルスをかけても電流抑制素子が非線形の電気抵抗特性を示さない現象）しない上限の電流、いわゆるブレークダウン電流が増加し、ｘ＝０．５およびＸ＝１．６７では１０００μＡ／μｍ２を上回っていることが確認できる。 As shown in FIG. 3, the current suppressing element 2 in which the first and second conductor layers 31 and 32 are made of tantalum nitride and the semiconductor layer 33 is made of silicon nitride has nonlinear electrical resistance characteristics. Further, it can be confirmed that a large amount of current flows in any voltage range as the ratio x of N to Ta of the tantalum nitride which is the first and second conductor layers 31 and 32 increases. In particular, the current suppressing element 2 in which the ratio x of N to Ta is 0.5 and 1.67, and the so-called Ta 2 N and Ta 3 N 5 are the first and second conductor layers 31 and 32 is Ta In particular, a larger amount of current flows than the current suppressing element 2 in which the so-called Ta and TaN 0.1 are the first and second conductive layers 31 and 32 in which the ratio x of N to 0 is 0.1 . It can be confirmed. From this fact, it can be seen that it is desirable to use the tantalum nitride in which the ratio x of N to Ta is 0.5 ≦ x ≦ 1.67 as the first and second conductor layers 31 and 32. Further, as shown in FIG. 3, as the ratio x of N to Ta of the tantalum nitride which is the first and second conductor layers 31 and 32 becomes larger, the breakdown (the polarity of The upper limit current that does not cause the current suppression element to exhibit non-linear electrical resistance characteristics even when different voltage pulses are applied, the so-called breakdown current increases, and 1000 μA / μm 2 at x = 0.5 and X = 1.67. Can be confirmed.
　図４は、図３に示す、第１および第２の導電体層３１，３２を膜厚５０ｎｍのＴａ、ＴａＮ０．１、Ｔａ２Ｎ、Ｔａ３Ｎ５の各タンタル窒化物で構成し、半導体層３３を膜厚１０ｎｍのＳｉＮ０．３であるシリコン窒化物で構成し、導電体層の面積が０．４６μｍ×０．４６μｍである、４種類の電流抑制素子２の電流－電圧特性から求めた、Ｔａに対するＮの比ｘとブレークダウン電流との関係を示したものである。 FIG. 4 shows that the first and second conductor layers 31 and 32 shown in FIG. 3 are made of tantalum nitrides of Ta, TaN 0.1 , Ta 2 N, and Ta 3 N 5 with a film thickness of 50 nm. From the current-voltage characteristics of the four types of current suppressing elements 2 in which the semiconductor layer 33 is made of silicon nitride of SiN 0.3 having a thickness of 10 nm and the area of the conductor layer is 0.46 μm × 0.46 μm. The relationship between the obtained ratio of N to Ta x and the breakdown current is shown.
　図４を見ると、第１および第２の導電体層３１，３２であるタンタル窒化物の、Ｔａに対するＮの比ｘが大きくなるにつれ、ブレークダウン電流が増加していることが確認できる。また、Ｔａに対するＮの比ｘが０．５、１．６７であるいわゆるＴａ２Ｎ、Ｔａ３Ｎ５の各タンタル窒化物でのブレークダウン電流は、少なくとも１０００μＡ／μｍ２以上であり、抵抗変化素子に１０００μＡ／μｍ２以上の電流密度で電流を流すことが可能であることが確認できる。 Referring to FIG. 4, it can be confirmed that the breakdown current increases as the ratio x of N to Ta of the tantalum nitride which is the first and second conductor layers 31 and 32 increases. In addition, the breakdown current in each tantalum nitride of so-called Ta 2 N and Ta 3 N 5 in which the ratio of N to Ta is 0.5 and 1.67 is at least 1000 μA / μm 2 or more, and the resistance change It can be confirmed that a current can be passed through the element at a current density of 1000 μA / μm 2 or more.
　Ｔａ２ＮおよびＴａ３Ｎ５の場合は、発明の解決課題で挙げている１０００μＡ／μｍ２を超えているので、Ｔａに対するＮの比ｘが、０．５≦ｘ≦１．６７であるタンタル窒化物を第１および第２の導電体層３１，３２とすることが望ましい。 In the case of Ta 2 N and Ta 3 N 5 , it exceeds the 1000 μA / μm 2 mentioned in the solution of the invention, so that the ratio x of N to Ta is 0.5 ≦ x ≦ 1.67 It is desirable to use nitride as the first and second conductor layers 31 and 32.
　図５は、図３に示す、第１および第２の導電体層３１，３２を膜厚５０ｎｍのＴａ、ＴａＮ０．１、Ｔａ２Ｎ、Ｔａ３Ｎ５の各タンタル窒化物で構成し、半導体層３３を膜厚１０ｎｍのＳｉＮ０．３であるシリコン窒化物で構成し、導電体層の面積が０．４６μｍ×０．４６μｍである、４種類の電流抑制素子２の電流－電圧特性から求めた、Ｔａに対するＮの比ｘとオン／オフ電流比の関係を実験的に求めたグラフである。 FIG. 5 shows that the first and second conductor layers 31 and 32 shown in FIG. 3 are made of tantalum nitrides of Ta, TaN 0.1 , Ta 2 N, and Ta 3 N 5 with a thickness of 50 nm, From the current-voltage characteristics of the four types of current suppressing elements 2 in which the semiconductor layer 33 is made of silicon nitride of SiN 0.3 having a thickness of 10 nm and the area of the conductor layer is 0.46 μm × 0.46 μm. It is the graph which calculated | required experimentally the relationship between the ratio of N with respect to Ta, and the on / off current ratio.
　図５を見ると、第１および第２の導電体層３１，３２であるタンタル窒化物の、Ｔａに対するＮの比ｘが、ｘ=０およびｘ＝０．１の場合には、オン／オフ電流比が５０未満であるが、ｘ＝０．５およびｘ＝１．６７では、オン／オフ電流比が９０以上となり大幅に改善していることがわかる。 Referring to FIG. 5, in the case where the ratio x of Ta to Ta of the tantalum nitride which is the first and second conductor layers 31 and 32 is x = 0 and x = 0.1, it is turned on / off. Although the current ratio is less than 50, it can be seen that when x = 0.5 and x = 1.67, the on / off current ratio is 90 or more, which is greatly improved.
　以上により、第１および第２の導電体層３１，３２であるタンタル窒化物（ＴａＯｘ）のｘの値を０．５乃至１．６７とすることにより、電流抑制素子２のブレークダウン電流を１０００μＡ／μｍ２以上にすることができ、かつオン／オフ電流比が５０以上確保できることがわかった。 As described above, by setting the value of x of the tantalum nitride (TaOx) that is the first and second conductor layers 31 and 32 to 0.5 to 1.67, the breakdown current of the current suppressing element 2 is set to 1000 μA. / Μm 2 or more, and an on / off current ratio of 50 or more can be secured.
　次に、本実施の形態にて確認された事項である、第１および第２の導電体層３１，３２であるタンタル窒化物のＴａに対するＮの比ｘが大きくなるにつれて、電流抑制素子２に流れる電流が増加する点、ブレークダウン電流が増加する点、オン／オフ電流比が増加する点、の３点の発現した理由について説明する。 Next, as the ratio x of N to Ta of tantalum nitride, which is the first and second conductor layers 31 and 32, which is a matter confirmed in the present embodiment, increases, The reasons why the flowing current increases, the breakdown current increases, and the on / off current ratio increases will be described.
　本実施の形態にて、第１および第２の導電体層３１，３２のタンタル窒化物は、Ｔａに対するＮの比ｘが高くなるほど、窒化の、Ｔａに対する割合が高くなっているために電気抵抗率が高くなり、電流が流れにくくなる傾向を有する。しかしながら、図３によれば、ｘの値を増加させると、逆に同じ電圧に対する電流の大きさは増大している。このことから、電流の流れを支配している因子は、導電体層３１，３２（タンタル窒化物）の電気抵抗率ではなく、ＭＳＭダイオードを構成している第１および第２の導電体層３１，３２と半導体層３３の界面に形成される電位障壁の高さが低下することにより、界面において電流が流れやすくなったのではないかと推測できる。また、第１および第２の導電体層３１，３２と半導体層３３の界面において、電流が流れやすくなっていることから、界面に発生する抵抗が小さくなり、ブレークダウンという一種の絶縁破壊のような現象が起こりにくくなったのではないかと推測できる。また、タンタル窒化物のＴａに対するＮの比ｘが大きいほうが、半導体層との界面状態がより平滑になることも考えられる。 In the present embodiment, the tantalum nitride of the first and second conductor layers 31 and 32 has a higher ratio of nitriding to Ta as the ratio of N to Ta increases. The rate tends to be high and current tends to hardly flow. However, according to FIG. 3, when the value of x is increased, the magnitude of the current for the same voltage is increased. From this, the factor governing the flow of current is not the electrical resistivity of the conductor layers 31 and 32 (tantalum nitride) but the first and second conductor layers 31 constituting the MSM diode. , 32 and the semiconductor layer 33, it can be presumed that the height of the potential barrier is reduced, so that current easily flows at the interface. In addition, since current easily flows at the interface between the first and second conductor layers 31 and 32 and the semiconductor layer 33, resistance generated at the interface is reduced, which is a kind of breakdown such as breakdown. It can be inferred that this phenomenon has become difficult to occur. It is also conceivable that the interface state with the semiconductor layer becomes smoother when the ratio x of N of tantalum nitride to Ta is larger.
　オン・オフ比は、タンタル窒化物のＴａに対するＮの比ｘが大きくなるにつれて、オフ領域のリーク電流も増加しているが、オン領域の電流増加がオフ領域の電流増加を上回ったために、改善したと考えられる。 The on / off ratio is improved because the off-region leakage current increases as the ratio x of N of Ta to tantalum nitride increases, but the increase in the on-region current exceeds the increase in the off-region current. It is thought that.
　以上のように、電流抑制素子２を構成することにより、非線形の電気抵抗特性を示し、かつ電流－電圧特性が印加電圧の極性に対して実質的に対称であり、かつ、抵抗変化素子に大電流を流すことが可能な電流抑制素子２を得ることができる。よって、極性の異なる電気パルスを印加する場合でも書き込みディスターブの発生を防止することが可能であり、かつ抵抗変化素子１に大電流を流すことが可能である記憶素子３及びそれを備える記憶装置２１を提供することが可能になる。

　上記説明から、当業者にとっては、本発明の多くの改良や他の実施形態が明らかである。従って、上記説明は、例示としてのみ解釈されるべきであり、本発明を実行する最良の態様を当業者に教示する目的で提供されたものである。本発明の精神を逸脱することなく、その構造及び／又は機能の詳細を実質的に変更できる。
As described above, by configuring the current suppressing element 2, a non-linear electrical resistance characteristic is exhibited, the current-voltage characteristic is substantially symmetric with respect to the polarity of the applied voltage, and the resistance change element is large. It is possible to obtain the current suppressing element 2 capable of flowing a current. Therefore, even when electrical pulses having different polarities are applied, it is possible to prevent the occurrence of write disturbance and to allow a large current to flow through the resistance change element 1 and the storage device 21 including the storage element 3. It becomes possible to provide.

From the foregoing description, many modifications and other embodiments of the present invention are obvious to one skilled in the art. Accordingly, the foregoing description should be construed as illustrative only and is provided for the purpose of teaching those skilled in the art the best mode of carrying out the invention. The details of the structure and / or function may be substantially changed without departing from the spirit of the invention.

　本発明に係る記憶素子および記憶装置は、極性の異なる電気パルスを印加する場合でも書き込みディスターブの発生を防止することが可能であり、かつ金属酸化物材料を用いて抵抗変化素子を構成する場合でも問題無くデータを書き込むことが可能であるため、例えば、抵抗変化記憶素子に流れる電流を制御する電流抑制素子を備えた記憶装置などに用いれば好適である。
The memory element and the memory device according to the present invention can prevent the occurrence of write disturbance even when electric pulses having different polarities are applied, and even when a resistance change element is configured using a metal oxide material. Since data can be written without any problem, for example, it is suitable for use in a storage device including a current suppressing element that controls a current flowing through a resistance change storage element.

　１　　抵抗変化素子
　２　　電流抑制素子
　３　　記憶素子
　３ａ　　記憶素子（選択記憶素子）
　４　　ビット線デコーダ
　５　　読み出し回路
　６，７　　ワード線デコーダ
　１１　　立体交差部
　２０　　記憶素子アレイ
　２１　　記憶装置
　３１　　第１の導電体層
　３２　　第２の導電体層
　３３　　半導体層
　ＷＬ０～ＷＬ３　　ワード線
　ＢＬ０～ＢＬ３　　ビット線
DESCRIPTION OF SYMBOLS 1 Resistance change element 2 Current suppression element 3 Memory element 3a Memory element (selection memory element)
4 bit line decoder 5 read circuit 6, 7 word line decoder 11 three-dimensional intersection 20 storage element array 21 storage device 31 first conductor layer 32 second conductor layer 33 semiconductor layer WL0 to WL3 word lines BL0 to BL3 bits line

Claims (3)

  1. 　極性が正または負の電気パルスの印加によってその抵抗値が変化し、前記変化した抵抗値を維持する抵抗変化素子と、
    　前記抵抗変化素子に流れる電流を抑制する電流抑制素子とを備え、
    　前記電流抑制素子は、第１の導電体層と、前記第１の導電体層の上に形成される半導体層と、前記半導体層の上に形成される第２の導電体層とを備え、
    　前記第１または第２の導電体層は、タンタルと窒素を含有するタンタル窒化物で構成され、
    　前記半導体層は、シリコンと窒素を含有するシリコン窒化物で構成され、

    　前記第１または第２の導電体層を形成するタンタル窒化物をＴａＮＸと表記した場合に、
    　０．５≦ｘ≦１．６７
    であることを特徴とする、

    　記憶素子。     A resistance change element that changes its resistance value by applying a positive or negative electric pulse, and maintains the changed resistance value;
    A current suppressing element that suppresses a current flowing through the variable resistance element;
    The current suppression element includes a first conductor layer, a semiconductor layer formed on the first conductor layer, and a second conductor layer formed on the semiconductor layer,
    The first or second conductor layer is made of tantalum nitride containing tantalum and nitrogen,
    The semiconductor layer is made of silicon nitride containing silicon and nitrogen,

    When the tantalum nitride forming the first or second conductor layer is expressed as TaN X ,
    0.5 ≦ x ≦ 1.67
    It is characterized by

    Memory element.
  2. 　前記第１または第２の導電体層がＴａ２ＮまたはＴａ３Ｎ５であることを特徴とする、請求項１に記載の記憶素子。 The memory element according to claim 1, wherein the first or second conductor layer is Ta 2 N or Ta 3 N 5 .
  3. 　複数の請求項１記載の記憶素子と、
    　複数のビット線と、
    　前記複数のビット線に各々立体交差する複数のワード線と、を備え、
    　前記記憶素子は前記抵抗変化素子と前記電流抑制素子との直列回路を備え、
    　前記複数の記憶素子が、前記ビット線と前記ワード線とが立体交差する各々の部分に配設され、前記各々の部分において、前記直列回路の一端がその対応する前記ビット線に、前記直列回路の他端がその対応する前記ワード線に、各々接続されている記憶装置。     A plurality of storage elements according to claim 1;
    Multiple bit lines,
    A plurality of word lines that three-dimensionally intersect each of the plurality of bit lines,
    The memory element includes a series circuit of the variable resistance element and the current suppressing element,
    The plurality of storage elements are disposed in respective portions where the bit line and the word line are three-dimensionally crossed, and in each of the portions, one end of the series circuit is connected to the corresponding bit line, and the series circuit The other end of each memory device is connected to the corresponding word line.
PCT/JP2009/004681 2008-09-19 2009-09-17 Storage element and storage device WO2010032468A1 (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001329367A (en) * 2000-02-16 2001-11-27 Applied Materials Inc Chemical vapor deposition for barrier from new precursor
JP2005133217A (en) * 2003-10-31 2005-05-26 Internatl Business Mach Corp <Ibm> Plasma enhanced ald of tantalum nitride and bilayer
JP2007158325A (en) * 2005-12-07 2007-06-21 Sharp Corp Crosspoint resistor memory device with bidirectional schottky diode
JP2008184688A (en) * 2007-01-26 2008-08-14 Asm America Inc Plasma ald of tantalum nitride film
JP4137994B2 (en) * 2006-11-20 2008-08-20 松下電器産業株式会社 Nonvolatile memory element, nonvolatile memory element array, and manufacturing method thereof

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001329367A (en) * 2000-02-16 2001-11-27 Applied Materials Inc Chemical vapor deposition for barrier from new precursor
JP2005133217A (en) * 2003-10-31 2005-05-26 Internatl Business Mach Corp <Ibm> Plasma enhanced ald of tantalum nitride and bilayer
JP2007158325A (en) * 2005-12-07 2007-06-21 Sharp Corp Crosspoint resistor memory device with bidirectional schottky diode
JP4137994B2 (en) * 2006-11-20 2008-08-20 松下電器産業株式会社 Nonvolatile memory element, nonvolatile memory element array, and manufacturing method thereof
JP2008184688A (en) * 2007-01-26 2008-08-14 Asm America Inc Plasma ald of tantalum nitride film

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