WO2010026681A1 - Differential amplifier, and method for constituting the same - Google Patents

Differential amplifier, and method for constituting the same Download PDF

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Publication number
WO2010026681A1
WO2010026681A1 PCT/JP2009/002795 JP2009002795W WO2010026681A1 WO 2010026681 A1 WO2010026681 A1 WO 2010026681A1 JP 2009002795 W JP2009002795 W JP 2009002795W WO 2010026681 A1 WO2010026681 A1 WO 2010026681A1
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Prior art keywords
terminal
output
drain
transistor
differential amplifier
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PCT/JP2009/002795
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French (fr)
Japanese (ja)
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沼田圭市
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日本電気株式会社
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Priority to JP2010527653A priority Critical patent/JP5445458B2/en
Publication of WO2010026681A1 publication Critical patent/WO2010026681A1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/42—Modifications of amplifiers to extend the bandwidth
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H03F3/45183—Long tailed pairs
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H03F3/45183—Long tailed pairs
    • H03F3/45188—Non-folded cascode stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45475—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using IC blocks as the active amplifying circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45134—Indexing scheme relating to differential amplifiers the whole differential amplifier together with other coupled stages being fully differential realised
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45318—Indexing scheme relating to differential amplifiers the AAC comprising a cross coupling circuit, e.g. two extra transistors cross coupled

Definitions

  • the present invention relates to a semiconductor amplifier circuit, and more particularly to a wideband differential amplifier circuit.
  • FIG. 22 is a diagram showing a differential amplifier 700 having the simplest circuit configuration generally known.
  • One method of widening the differential amplifier 700 is to adopt a cascode configuration (see, for example, the description in FIG. 7 and paragraphs 17 to 18 of Patent Document 1).
  • FIG. 23 is a circuit diagram showing a differential amplifier 800 having a cascode configuration.
  • the differential amplifier 800 can reduce the mirror effect by adopting the cascode configuration, and can widen the frequency band that can be amplified.
  • FIG. 24 is a circuit diagram showing a differential level shift circuit disclosed in Patent Document 2.
  • an input signal supplied to the input terminals IN and IN_B (the gates of the transistors J1 and J3 constituting the source follower) is supplied into the circuit (current source) via the capacitive elements C G1 and C G2. Feed forward to the transistors J4 and J2).
  • the high-frequency component of the input signal having the opposite phase is supplied to the bases of the current source transistors J2 and J4.
  • the transistors J2 and J4 are actively driven so as to increase or decrease the current of the circuit, and the reduction in the driving capability of the transistors J1 and J3 is compensated, thereby realizing a wide band of the level shift circuit 900.
  • Patent Document 3 discloses a multistage amplifying device in which a plurality of amplifiers including differential amplifiers are cascade-connected.
  • the multistage amplifying device disclosed in Patent Document 3 feeds an input signal supplied to an input terminal of a differential amplifier of an input stage (first stage) to an input terminal of a second stage voltage amplifier via a high-pass filter. To do.
  • Patent Document 4 two outputs of a differential amplifier are respectively connected to opposite-phase side input terminals (that is, capacitive elements connected to gate terminals of a pair of transistors having a source commonly connected to a current source and constituting a differential pair).
  • opposite-phase side input terminals that is, capacitive elements connected to gate terminals of a pair of transistors having a source commonly connected to a current source and constituting a differential pair.
  • JP 2007-6484 (FIG. 7, paragraphs 17 and 18) Japanese Unexamined Patent Publication No. 5-67933 (FIG. 1, 11th paragraph) JP-A-9-148850 JP 2006-191350 A
  • the differential amplifier 700 shown in FIG. 22 has a problem that high-frequency characteristics cannot be sufficiently obtained due to the mirror effect (see FIG. 19A).
  • a cascode configuration is adopted.
  • the cascode transistors 13 and 14 are connected to the input transistors 11 and 12 as shown in FIG.
  • the capacitance that the input terminals 1 and 2 are affected by the cascode transistors 13 and 14 through the gate capacitance is the capacitance of the cascode transistors 13 and 14. Therefore, high-frequency performance can be enhanced by designing the cascode transistors 13 and 14 so that the capacitance of the cascode transistors 13 and 14 is smaller than the load capacitance.
  • the cascode transistors 13 and 14 a transistor having a size as small as possible is desired in order to reduce the influence on the input terminals 1 and 2, while a current necessary for the differential amplifier 800 can flow. It needs to be big. Because of this trade-off relationship, the cascode transistor cannot be reduced freely. Therefore, even with the differential amplifier 800 having the cascode configuration, the band can be expanded only to about 1.5 to 2 times that of the differential amplifier 700.
  • the multistage amplifier disclosed in Patent Document 3 feeds an input signal applied to an input stage to a second stage amplifier via a high-pass filter. That is, it does not improve the operating band of the input stage differential amplifier itself, and it is essential to provide an amplifier for amplifying high frequency separately from the input stage differential amplifier.
  • the amplifying device disclosed in Patent Document 4 since a capacitive element is added to the input terminal of the differential amplifier, the input terminal is more easily affected by the output load C L (see FIG. 19A). Depending on the situation, the operating band of the amplifying device may be conversely narrowed. In addition, in order to compensate for this, it is necessary to improve the driving capability of the amplifier arranged in the previous stage of the amplifying device of Patent Document 4, which leads to an increase in the size of the entire circuit and an increase in current consumption.
  • the present invention has been made on the basis of the above-mentioned knowledge by the inventor of the present application, and an object of the present invention is to provide a wideband differential amplifier with a simple circuit configuration.
  • the differential amplifier circuit includes a first and second drive transistors that form a differential pair, and a first differential output signal that is amplified by the differential pair. And a second output terminal, first and second circuits, and first and second high-pass filters. One of the differential input signals is supplied to the gates of the first and second drive transistors.
  • the first circuit is disposed on a wiring connected to the source / drain path of the first driving transistor and the first output terminal, and is capable of adjusting a drain current flowing through the first driving transistor. 1 control terminal.
  • the second circuit is disposed on a wiring connected to the source / drain path of the second driving transistor and the second output terminal, and adjusts the drain current flowing through the second driving transistor. It has a possible second control terminal.
  • the first high-pass filter is connected between the second output terminal and the first control terminal, and inputs one of the differential output signals to selectively transmit a high-frequency component and transmit the same.
  • the later signal is fed back as the control potential of the first control terminal.
  • the second high-pass filter is connected between the first output terminal and the second control terminal, and inputs the other of the differential output signals to selectively transmit high-frequency components.
  • the transmitted signal is fed back as the control potential of the second control terminal.
  • the second aspect of the present invention is a method for configuring a differential amplifier.
  • the method includes the following steps (a) to (f).
  • (E) One of differential output signals after being amplified by the differential pair is input to selectively transmit high-frequency components, and the transmitted signal is fed back as the control potential of the first
  • a first high-pass filter between the second output terminal of the first and second output terminals from which the differential output signal is output and the first control terminal; and (f A second high-pass filter that inputs the other of the differential output signals and selectively transmits a high-frequency component, and feeds back the transmitted signal as a control potential of the second control terminal. Connecting between the output terminal and the second control terminal.
  • the above-described differential amplifier according to the first aspect of the present invention and the differential amplifier obtained by the method according to the second aspect can suppress a decrease in gain and extend an operating frequency band with a simple circuit configuration.
  • FIG. 1 is a block diagram showing a differential amplifier according to a first embodiment of the present invention.
  • FIG. 2 is a circuit diagram showing a specific configuration example (cascode differential amplifier) of the differential amplifier according to the first embodiment of the present invention. It is a block diagram which shows the differential amplifier which concerns on the 2nd Embodiment of this invention. It is a circuit diagram which shows the specific structural example of the differential amplifier which concerns on the 2nd Embodiment of this invention. It is a block diagram which shows the differential amplifier which concerns on the 3rd Embodiment of this invention.
  • FIG. 5 is a conceptual diagram illustrating an operation of the differential amplifier according to the first embodiment. It is a graph which shows an example of the numerical calculation result regarding the high frequency characteristic of the differential amplifier which concerns on 1st Embodiment in contrast with the thing of background art. It is a graph which shows an example of the numerical calculation result regarding the high frequency characteristic of the differential amplifier which concerns on 2nd Embodiment in contrast with the thing of background art. It is a figure which shows the differential amplifier circuit concerning background art. It is a figure which shows the cascode type
  • FIG. 1 is a block diagram showing a schematic configuration of a differential amplifier 100 according to the first embodiment of the present invention.
  • the differential amplifier 100 includes a basic element 120 for differential amplification.
  • the basic element 120 has two input terminals 1 and 2 and two output terminals 3 and 4.
  • the basic element 120 has a differential pair, amplifies the differential signal supplied to the input terminals 1 and 2 by the differential pair, and supplies the amplified differential signal to the output terminals 3 and 4.
  • the input terminal 1 is a positive phase input terminal IN
  • the input terminal 2 is a negative phase input terminal IN_B
  • the output terminal 3 is a positive phase output terminal OUT
  • the output terminal 4 is a negative phase output terminal OUT_B.
  • the differential amplifier 100 includes high pass filters (HPFs) 111 and 112. One end of the HPF 111 is connected to the output terminal 4, and the other end is connected to the circuit of the basic element 120 excluding the input terminals 1 and 2. Similar to the HPF 111, the HPF 112 is connected between the output terminal 3 and the circuit of the basic element 120. That is, the HPFs 11 and 112 feed back the two output signals (differential output signals S OUT and S OUTB ) of the differential amplifier 100 to the potential in the basic element 120 of the differential amplifier 100 excluding the differential input signal.
  • HPFs high pass filters
  • FIG. 2 is a circuit diagram showing an example of a specific configuration of the differential amplifier 100.
  • the other components excluding the input terminals 1 and 2, the output terminals 3 and 4, and the HPFs 111 and 112 correspond to the basic element 120 described above.
  • the differential amplifier 100 of FIG. 2 has a cascode configuration. Below, each component shown by FIG. 2 is demonstrated in order.
  • the drive transistors 11 and 12 constitute a differential pair for amplification. Specifically, the gate of the drive transistor 11 is connected to the input terminal 1, and the gate of the drive transistor 12 is connected to the input terminal 2. The sources of the commonly connected transistors 11 and 12 are grounded via the constant current source 10. The drain of the drive transistor 11 is connected to the power supply terminal 5 (drain potential V DD ) via the cascode transistor 13 and the output load 101. Similarly, the drain of the drive transistor 12 is connected to the power supply terminal 5 (drain potential V DD ) via the cascode transistor 14 and the output load 102.
  • the source of the cascode transistor 13 is connected to the drain of the drive transistor 11, and the drain is connected to the output load 101.
  • the source of the cascode transistor 14 is connected to the drain of the drive transistor 12, and the drain is connected to the output load 102.
  • One end of the output load 101 is connected to the source of the cascode transistor 13 and the other end is connected to the power supply terminal 5.
  • a common connection point between the output load 101 and the cascode transistor 13 is connected to the output terminal 4.
  • one end of the output load 102 is connected to the source of the cascode transistor 14, and the other end is connected to the power supply terminal 5.
  • a common connection point between the output load 102 and the cascode transistor 14 is connected to the output terminal 3.
  • the HPF 111 is disposed between the output terminal 4, that is, the drain of the cascode transistor 13 and the gate of the other cascode transistor 14. That is, the HPF 111 supplies the high-frequency component of the negative phase output signal S OUTB appearing at the output terminal 4 to the cascode transistor 14 on the negative phase input IN_B side as a bias voltage.
  • the HPF 112 is disposed between the output terminal 3, that is, the drain of the cascode transistor 14 and the gate of the other cascode transistor 13.
  • the HPF 112 supplies a high frequency component of the positive phase output signal S OUT appearing at the output terminal 3 as a bias voltage to the cascode transistor 13 on the positive phase input IN side.
  • the differential input signals input to the gates of the drive transistors 11 and 12 constituting the differential pair are amplified by the drive transistors 11 and 12, the cascode transistors 13 and 14, and the output loads 101 and 102.
  • a differential output signal is obtained from the terminals 4 and 3 which are the drains of the cascode transistors 13 and 14.
  • FIG. 3 is a circuit diagram of the differential amplifier 100 including specific circuit configurations of the constant current source 10, the HPFs 111 and 112, and the output loads 101 and 102.
  • the constant current source 10 includes a current source transistor 15.
  • the gate of the current source transistor 15 is connected to a bias terminal 7 to which a constant current source bias voltage is input, and the source of the current source transistor is grounded.
  • the drain of the transistor 15 is commonly connected to the sources of the drive transistors 11 and 12.
  • the output load 101 includes a resistance element 21.
  • the output load 102 includes a resistance element 22.
  • the HPF 111 includes a resistance element 23 and a capacitance element 41.
  • the resistive element 23 and the capacitive element 41 are connected in series, the other terminal of the capacitive element 41 is connected to the output terminal 4, and the other terminal of the resistive element 23 is connected to the bias terminal 6.
  • the contact point between the resistance element 23 and the capacitive element 41 is connected to the gate of the cascode transistor 14 as an output of the HPF 111.
  • the HPF 112 includes a resistance element 24 and a capacitance element 42.
  • the resistive element 24 and the capacitive element 42 are connected in series, the other terminal of the capacitive element 42 is connected to the output terminal 3, and the other terminal of the resistive element 24 is connected to the bias terminal 6.
  • the contact point between the resistance element 24 and the capacitive element 42 is connected to the gate of the cascode transistor 13 as an output of the HPF 112.
  • the pass frequencies of the HPFs 111 and 112 are determined by the capacitance values of the capacitive elements 41 and 42 and the resistance values of the resistive elements 23 and 24. For example, this passing frequency may be set so that the gain of the basic element 120 of the differential amplifier 100 begins to decrease and the gain fluctuation range is within about 3 dB.
  • FIGS. 19A to 19C are schematic diagrams showing one transistor 11 of a differential pair and its peripheral circuit elements.
  • 19C is a diagram related to the differential amplifier 100
  • FIGS. 19A and 19B are diagrams related to the background art shown for comparison.
  • FIG. 19A shows the case of the differential amplifier 700 shown in FIG.
  • the load capacitance C L connected to the output terminal 4 through the gate capacitance C GD of the drive transistor 11 is affected. For this reason, the transistor 11 cannot be driven at a high frequency, the gain is reduced, and the frequency band that can be amplified by the differential amplifier 700 is narrowed.
  • FIG. 19B shows the case of the differential amplifier 800 having the cascode configuration shown in FIG.
  • the influence of the load capacitance C L is blocked by the cascode transistor 13. Therefore, from the input terminal 1 does not receive only the influence of the C GS of the cascode transistor 13 through C GD of the driving transistor 11. Since C GS of the cascode transistor 13 is smaller than the load capacitance C L , the differential amplifier 800 can be driven to a higher frequency than the differential amplifier 700, and the frequency band that can be amplified is expanded.
  • FIG. 19C is a schematic diagram of the differential amplifier 100 according to the present embodiment.
  • the positive-phase output signal S OUT is fed back to the gate of the cascode transistor 13, whereby a signal in phase with the gate of the drive transistor 11 that is the signal input terminal 1 is supplied to the gate of the cascode transistor 13.
  • the differential amplifier 100 eliminates the effects of the C GD of the drive transistor 11 and the C GS of the cascode transistor 13 as viewed from the input terminal 1 as much as possible. Can be approached.
  • This effect is produced by the HPF 112 from the vicinity of the frequency at which the gain of the cascode-configured amplifier 700 starts to decrease, so that the gain starting to decrease can be increased to obtain a gain up to a higher frequency.
  • the feedback effect starts to occur after the gain starts to decrease, there is also an effect of suppressing oscillation.
  • the differential amplifier 100 can expand the operating band to a higher frequency.
  • the differential amplifier 100 does not require a new current to flow in order to obtain an effect of suppressing a gain reduction in a high frequency band, and the added elements (HPFs 111 and 112) are also small. For this reason, high frequency characteristics can be improved while suppressing an increase in power consumption and a significant increase in area.
  • FIG. 20 is a graph showing an example of the calculation result of the frequency characteristics of the gain of the differential amplifier 100.
  • the 1 dB gain reduction frequency is about 200 MHz (graph L11 in FIG. 20).
  • a band of 400 MHz or more which is about twice that of the amplifier 700, is obtained (graph L21 in FIG. 20).
  • the output load 101 is not limited to the resistance element 21 (FIG. 11), but includes an inductor element 31 (FIG. 12), a parallel circuit of the resistance element 21 and the inductor element 31 (FIG. 13), and a series of the resistance element 21 and the inductor element 31.
  • the same effect can be obtained even with a circuit (FIG. 14), or a series circuit of the resistive element 21 and the inductor element 31 and a parallel circuit of the capacitive element 45.
  • the HPF 111 is not limited to a circuit (FIG. 17) configured by the resistance element 24 and the capacitive element 41, but is a circuit configured by the capacitive element 41 and the inductor element 32, or a series of the resistive element 23 and the inductor element 32. The same effect can be obtained even in a circuit (FIG. 18) in which the capacitive element 41 is connected to the connection.
  • FIG. 4 is a circuit diagram showing a configuration of the differential amplifier 200 according to the present embodiment.
  • the other components excluding the input terminals 1 and 2, the output terminals 3 and 4, and the HPFs 113 and 114 correspond to the basic element 120 of the differential amplifier 200. 4 is compared with FIG. 2 described above, (a) the differential amplifier 200 of FIG. 4 does not have a cascode configuration, and (b) the differential output signal S OUT in which the HPFs 113 and 114 appear at the output terminals 3 and 4. And S OUTB are fed back to the output loads 101 and 103 in two points.
  • FIG. 5 is a circuit diagram of the differential amplifier 200 including specific circuit configurations of the output loads 101 and 102 and the HPFs 113 and 114.
  • the output load 101 includes a resistance element 21 and a load transistor 16 connected in parallel thereto.
  • the drain of the load transistor 16 which is a P-channel transistor is connected to the drain of the driving transistor 11 together with one end of the resistance element 21.
  • the source of the load transistor 16 is connected to the power supply terminal 5.
  • the output load 102 includes a resistance element 22 and a load transistor 17 connected in parallel thereto.
  • the drain of the load transistor 17 which is a P-channel transistor is connected to the drain of the driving transistor 12 together with one end of the resistance element 22.
  • the source of the load transistor 17 is connected to the power supply terminal 5.
  • the HPF 113 includes a resistance element 25 and a capacitance element 43.
  • the resistive element 25 and the capacitive element 43 are connected in series, the other terminal of the capacitive element 43 is connected to the output terminal 3, and the other terminal of the resistive element 25 is connected to the bias terminal 8.
  • the contact point between the resistance element 25 and the capacitive element 43 is connected to the gate of the load transistor 16 as an output of the HPF 113.
  • the HPF 114 includes the resistance element 26 and the capacitance element 44.
  • the resistive element 26 and the capacitive element 44 are connected in series, the other terminal of the capacitive element 44 is connected to the output terminal 4, and the other terminal of the resistive element 26 is connected to the bias terminal 8.
  • the contact point between the resistor element 26 and the capacitor element 44 is connected to the gate of the load transistor 17 as an output of the HPF 114.
  • the pass frequencies of the HPFs 113 and 114 are determined by the capacitance values of the capacitive elements 43 and 44 and the resistance values of the resistive elements 25 and 26.
  • the passing frequency may be set to be around the frequency at which the gain reduction of the basic element 120 of the differential amplifier 200 starts and the gain fluctuation range is within about 3 dB.
  • the output load 101 in the present embodiment has the load transistor 16 as an active element, and functions as an active load when a signal fed back via the HPF 113 is supplied to the gate of the load transistor 16.
  • the other circuit elements shown in FIGS. 4 and 5 and their connection relations are the same as those of the differential amplifier 100 described above, and therefore, redundant description is omitted here.
  • the differential amplifier 200 can expand the operating band to a higher frequency.
  • the differential amplifier 200 does not require a new current to flow in order to obtain an effect of suppressing a gain reduction in a high frequency band, and the added elements (HPFs 113 and 114) are small. For this reason, high frequency characteristics can be improved while suppressing an increase in power consumption and a significant increase in area.
  • FIG. 21 is a graph showing an example of the calculation result of the frequency characteristics of the gain of the differential amplifier 200.
  • a graph L12 in FIG. 21 shows frequency characteristics of the gain of the amplifier 700 shown in FIG.
  • the graph 32 in FIG. 21 is an example of the frequency characteristic of the gain of the differential amplifier 200. Calculations also show that the differential amplifier 200 according to the present embodiment can greatly expand the operating band from the differential amplifier 700.
  • the output load 102 is not limited to the parallel connection circuit (FIG. 9) of the resistance element 21 and the load transistor 16, but includes the load transistor 16 (FIG. 8) or the parallel circuit of the inductor element 31 and the load transistor 16 (FIG. 10). Even when used, the same effect can be obtained.
  • FIG. 6 is a circuit diagram of a cascode differential amplifier 300 according to this embodiment.
  • FIG. 7 is a circuit diagram of the differential amplifier 300 including specific circuit configurations of the output loads 101 and 102 and the HPFs 111, 112, 113, and 114.
  • the differential amplifier 300 is a combination of the feedback configurations of the differential amplifiers 100 and 200 described above. That is, the HPFs 111 and 112 feed back the differential output signal to the gates of the cascode transistors 13 and 14.
  • the HPFs 113 and 114 feed back the differential output signals to control terminals (gates of the load transistors 16 and 17) for controlling the impedances of the output loads 101 and 102.
  • the circuit elements shown in FIGS. 6 and 7 and their connection relations are as already described with respect to the first and second embodiments.
  • the differential amplifier 300 improves the driving force at a high frequency by feedback to the control terminals of the output loads 101 and 102, and mirrors the input terminals by feedback to the control terminals of the output loads 101 and 102. The effect is reduced. Therefore, the differential amplifier 300 can expand the operation band to a higher frequency.
  • the differential output signal passes through the first and second high-pass filters (eg, HPFs 111 and 112). To pass. That is, as the operating frequency of the differential amplifier increases, the gains of the first and second drive transistors (for example, the transistors 11 and 12) constituting the differential pair begin to decrease, and at the same time, the operating frequency increases.
  • the high-frequency component of the differential output signal that has passed through the second high-pass filter is ford-backed into the differential amplifier.
  • the differential amplifier acts to increase the output in the high frequency band. As a result, the differential amplifier can suppress the decrease in gain and extend the operating frequency band with a simple circuit configuration.
  • the output of a single-ended amplifier is generally in the opposite phase to the input, but a signal in phase with the input signal is required for feedback via the HPF 111, 113, etc. Therefore, a circuit that generates an in-phase signal from the output signal of the single-ended amplifier may be arranged, and the output of the circuit may be fed back into the single-ended amplifier via the HPFs 111 and 113.
  • two single-ended amplifiers are arranged in parallel, two signals having a phase difference of ⁇ radians are input to the two single-ended amplifiers, and the two output signals are respectively supplied to the HPF 111 or 113 in the other single-ended amplifier. You can feed back through.
  • the feedback destination into the single-ended amplifier may be the control terminal of the cascode transistor or the control terminal of the output load that can control the drain current of the driving transistor.

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Abstract

Provided is a wide-band differential amplifier in a simple circuit constitution.  A first high-pass filter (112 or 114) is connected between a control terminal of a first circuit (e.g., a transistor (13) or an output load (101)) mounted on a wiring line containing the source-drain path of a drive transistor (11), and an output terminal (3), so that the first high-pass filter (112 or 114) inputs one of differential output signals and transmits a high-frequency component selectively, and feeds back the same as a control potential of the control terminal of the first circuit for adjusting the drain current of the drive transistor (11).  On the other hand, a second high-pass filter (111 or 113) is connected between a control terminal of a second circuit (e.g., a transistor (14) or an output load (102)) mounted on a wiring line containing the source-drain path of a drive transistor (12), and an output terminal (4), so that the second high-pass filter (111 or 113) inputs the other of differential output signals and transmits a high-frequency component selectively, and feeds back the transmitted signal as a control potential of the control terminal of the second circuit.

Description

差動増幅器及びその構成方法Differential amplifier and configuration method thereof
　本発明は、半導体増幅回路に関し、特に広帯域な差動増幅回路に関する。 The present invention relates to a semiconductor amplifier circuit, and more particularly to a wideband differential amplifier circuit.
　近年、無線通信技術の進歩と普及は目覚しく、より高速通な通信速度を低消費電力かつ低価格に実現するために、最新ＣＭＯＳプロセスを用いた無線ＬＳＩ開発が進んでいる。より高速な通信速度を実現するために、通信に用いられる周波数帯域も広がってきている。このため、広帯域な差動増幅器の実現は、ＣＭＯＳ無線ＬＳＩの分野におけるキーテクノロジーの１つである。 In recent years, the progress and spread of wireless communication technology has been remarkable, and wireless LSI development using the latest CMOS process is progressing in order to realize a higher communication speed with lower power consumption and lower price. In order to realize a higher communication speed, the frequency band used for communication is also expanding. Therefore, the realization of a wideband differential amplifier is one of the key technologies in the field of CMOS wireless LSI.
　図２２は、一般的に知られている最も単純な回路構成を有する差動増幅器７００を示す図である。この差動増幅器７００の広帯域化の手法の１つには、カスコード構成の採用がある（例えば特許文献１の図７及び第１７～１８段落の記載を参照）。図２３は、カスコード構成を有する差動増幅器８００を示す回路図である。差動増幅器７００では、出力負荷容量のミラー効果がゲート容量を介して入力端子に生じるため、高周波ゲインが十分に得られない。しかしながら、差動増幅器８００は、カスコード構成の採用によってミラー効果を軽減でき、増幅可能な周波数帯域を広げることができる。 FIG. 22 is a diagram showing a differential amplifier 700 having the simplest circuit configuration generally known. One method of widening the differential amplifier 700 is to adopt a cascode configuration (see, for example, the description in FIG. 7 and paragraphs 17 to 18 of Patent Document 1). FIG. 23 is a circuit diagram showing a differential amplifier 800 having a cascode configuration. In the differential amplifier 700, since the mirror effect of the output load capacitance is generated at the input terminal via the gate capacitance, a sufficient high frequency gain cannot be obtained. However, the differential amplifier 800 can reduce the mirror effect by adopting the cascode configuration, and can widen the frequency band that can be amplified.
　また、図２４は、特許文献２に開示された差動構成のレベルシフト回路を示す回路図である。図２４のレベルシフト回路９００では、入力端子ＩＮ及びＩＮ＿Ｂ（ソースフォロワを構成するトランジスタＪ１及びＪ３のゲート）に供給される入力信号が、容量素子ＣＧ１及びＣＧ２を介して回路内部（電流源用のトランジスタＪ４及びＪ２のゲート）へフィードフォワードされている。つまり、電流源用のトランジスタＪ２及びＪ４のベースに対して、直流バイアスに加えて、逆相の入力信号の高周波成分が供給される。これにより、トランジスタＪ２及びＪ４が積極的に回路の電流の増減が生じるように駆動し、トランジスタＪ１及びＪ３の駆動能力低下を補償することで、レベルシフト回路９００の広帯域化を実現している。 FIG. 24 is a circuit diagram showing a differential level shift circuit disclosed in Patent Document 2. In FIG. In the level shift circuit 900 of FIG. 24, an input signal supplied to the input terminals IN and IN_B (the gates of the transistors J1 and J3 constituting the source follower) is supplied into the circuit (current source) via the capacitive elements C G1 and C G2. Feed forward to the transistors J4 and J2). In other words, in addition to the DC bias, the high-frequency component of the input signal having the opposite phase is supplied to the bases of the current source transistors J2 and J4. As a result, the transistors J2 and J4 are actively driven so as to increase or decrease the current of the circuit, and the reduction in the driving capability of the transistors J1 and J3 is compensated, thereby realizing a wide band of the level shift circuit 900.
　また、特許文献３は、差動増幅器を含む複数の増幅器が従属接続された多段増幅装置を開示している。特許文献３に開示された多段増幅装置は、入力段（第１段）の差動増幅器の入力端子に供給される入力信号をハイパスフィルタを介して第２段の電圧増幅器の入力端子にフィードフォワードする。 Patent Document 3 discloses a multistage amplifying device in which a plurality of amplifiers including differential amplifiers are cascade-connected. The multistage amplifying device disclosed in Patent Document 3 feeds an input signal supplied to an input terminal of a differential amplifier of an input stage (first stage) to an input terminal of a second stage voltage amplifier via a high-pass filter. To do.
　また、特許文献４は、差動増幅器の２つの出力をそれぞれ逆相側の入力端子（つまり、ソースが電流源に共通接続され、差動対を構成する一対のトランジスタのゲート端子）に容量素子を介して帰還する構成を開示している。 Further, in Patent Document 4, two outputs of a differential amplifier are respectively connected to opposite-phase side input terminals (that is, capacitive elements connected to gate terminals of a pair of transistors having a source commonly connected to a current source and constituting a differential pair). The structure which returns via is disclosed.
特開２００７－６４８４号公報（図７、第１７及び１８段落）JP 2007-6484 (FIG. 7, paragraphs 17 and 18) 特開平５－６７９３３号公報（図１、第１１段落）Japanese Unexamined Patent Publication No. 5-67933 (FIG. 1, 11th paragraph) 特開平９－１４８８５０号公報JP-A-9-148850 特開２００６－１９１３５０号公報JP 2006-191350 A
　上述したように、図２２に示す差動増幅器７００では、ミラー効果のために高周波特性を十分に引き出せない問題がある（図１９Ａを参照）。この問題の軽減方法には、カスコード構成の採用がある。カスコード構成では、図２３に示したように、カスコードトランジスタ１３及び１４が入力トランジスタ１１及び１２に接続される。カスコードトランジスタ１３及び１４によって、ゲート容量を介して入力端子１及び２が影響を受ける容量はカスコードトランジスタ１３及び１４の容量となる。よって、カスコードトランジスタ１３及び１４の容量が負荷容量より小さくなるように設計することで、高周波性能を引きすことができる。しかしながら、カスコードトランジスタ１３及び１４としては、入力端子１及び２への影響を小さくするためにできる限り小さいサイズのトランジスタが望まれる一方で、差動増幅器８００に必要な電流を流すことができる程度の大さである必要がある。このトレードオフの関係が存在するために、カスコードトランジスタを自由に小さくすることは出来ない。よって、カスコード構成を有する差動増幅器８００でも、差動増幅器７００の１．５～２倍程度までしか帯域を広げることはできない。 As described above, the differential amplifier 700 shown in FIG. 22 has a problem that high-frequency characteristics cannot be sufficiently obtained due to the mirror effect (see FIG. 19A). As a method for reducing this problem, a cascode configuration is adopted. In the cascode configuration, the cascode transistors 13 and 14 are connected to the input transistors 11 and 12 as shown in FIG. The capacitance that the input terminals 1 and 2 are affected by the cascode transistors 13 and 14 through the gate capacitance is the capacitance of the cascode transistors 13 and 14. Therefore, high-frequency performance can be enhanced by designing the cascode transistors 13 and 14 so that the capacitance of the cascode transistors 13 and 14 is smaller than the load capacitance. However, as the cascode transistors 13 and 14, a transistor having a size as small as possible is desired in order to reduce the influence on the input terminals 1 and 2, while a current necessary for the differential amplifier 800 can flow. It needs to be big. Because of this trade-off relationship, the cascode transistor cannot be reduced freely. Therefore, even with the differential amplifier 800 having the cascode configuration, the band can be expanded only to about 1.5 to 2 times that of the differential amplifier 700.
　また、図２４のレベルシフト回路９００のように、入力信号そのものを容量素子（ＣＧ１及びＣＧ２）を介して入力トランジスタ（Ｊ１及びＪ３）以外の回路内部へフィードフォワードする手法もある。しかしながら、前段のトランジスタＪ１及びＪ３から見ると駆動する負荷が増えたこととなるため、トランジスタＪ１及びＪ３の駆動力向上や帯域拡張などの対策が必要になる。しかしながら、一般的に、差動増幅器は、弱い信号を増幅するために多段増幅回路の前段に配置される回路であるため、入力信号の駆動力や帯域はすでに決まっているものであることが多く、より大きな駆動力が新たに必要となるフィードフォワード構成は、回路全体を縮小化して、さらに増幅器を多段化するなどの対策が必要となるため、設計の難しさや面積の増大を招く問題がある。 In addition, there is a method of feeding forward the input signal itself into a circuit other than the input transistors (J1 and J3) through the capacitive elements (C G1 and C G2 ) as in the level shift circuit 900 of FIG. However, when viewed from the transistors J1 and J3 in the previous stage, the driving load increases, so measures such as improvement of the driving power of the transistors J1 and J3 and band expansion are required. However, in general, a differential amplifier is a circuit that is arranged in front of a multistage amplifier circuit in order to amplify a weak signal. Therefore, in many cases, the driving power and bandwidth of an input signal are already determined. The feedforward configuration that newly requires a larger driving force requires measures such as downsizing the entire circuit and further increasing the number of amplifiers, resulting in a difficulty in design and an increase in area. .
　ところで特許文献３に開示された多段増幅装置は、入力段に与えられる入力信号をハイパスフィルタを介して第２段の増幅器にフィードフォワードするものである。つまり、入力段の差動増幅器自体の動作帯域を向上させるものではなく、高周波を増幅するための増幅器を入力段の差動増幅器とは別途に設けることが必須である。 Incidentally, the multistage amplifier disclosed in Patent Document 3 feeds an input signal applied to an input stage to a second stage amplifier via a high-pass filter. That is, it does not improve the operating band of the input stage differential amplifier itself, and it is essential to provide an amplifier for amplifying high frequency separately from the input stage differential amplifier.
　また、特許文献４に開示された増幅装置は、差動増幅器の入力端子に容量素子が追加されるため、入力端子が出力負荷ＣＬ（図１９Ａを参照）の影響をより受けやすくなるという問題があり、状況によっては増幅装置の動作帯域を逆に狭くしてしまうおそれがある。また、これを補おうとする場合、特許文献４の増幅装置の前段に配置される増幅器の駆動能力の向上が必要となり、回路全体の大型化、消費電流の増加を招いてしまう。 Further, in the amplifying device disclosed in Patent Document 4, since a capacitive element is added to the input terminal of the differential amplifier, the input terminal is more easily affected by the output load C L (see FIG. 19A). Depending on the situation, the operating band of the amplifying device may be conversely narrowed. In addition, in order to compensate for this, it is necessary to improve the driving capability of the amplifier arranged in the previous stage of the amplifying device of Patent Document 4, which leads to an increase in the size of the entire circuit and an increase in current consumption.
　本発明は本願の発明者による上述した知見に基づいてなされたものであって、本発明の目的は、広帯域な差動増幅器を簡易な回路構成で提供することである。 The present invention has been made on the basis of the above-mentioned knowledge by the inventor of the present application, and an object of the present invention is to provide a wideband differential amplifier with a simple circuit configuration.
　本発明の第１の態様にかかる差動増幅回路は、差動対を構成する第１及び第２の駆動トランジスタ、前記差動対によって増幅された後の差動出力信号が出力される第１及び第２の出力端子、第１及び第２の回路、並びに第１及び第２のハイパスフィルタを備える。前記第１及び第２の駆動トランジスタの各々のゲートには、差動入力信号のそれぞれ一方が供給される。 The differential amplifier circuit according to the first aspect of the present invention includes a first and second drive transistors that form a differential pair, and a first differential output signal that is amplified by the differential pair. And a second output terminal, first and second circuits, and first and second high-pass filters. One of the differential input signals is supplied to the gates of the first and second drive transistors.
　前記第１の回路は、前記第１の駆動トランジスタのソース・ドレイン経路及び前記第１の出力端子が接続された配線上に配置され、前記第１の駆動トランジスタを流れるドレイン電流を調整可能な第１の制御端子を有する。同様に、前記第２の回路は、前記第２の駆動トランジスタのソース・ドレイン経路及び前記第２の出力端子が接続された配線上に配置され、前記第２の駆動トランジスタを流れるドレイン電流を調整可能な第２の制御端子を有する。 The first circuit is disposed on a wiring connected to the source / drain path of the first driving transistor and the first output terminal, and is capable of adjusting a drain current flowing through the first driving transistor. 1 control terminal. Similarly, the second circuit is disposed on a wiring connected to the source / drain path of the second driving transistor and the second output terminal, and adjusts the drain current flowing through the second driving transistor. It has a possible second control terminal.
　前記第１のハイパスフィルタは、前記第２の出力端子と前記第１の制御端子の間に接続され、前記差動出力信号のうち一方を入力して高周波成分を選択的に透過させるとともに、透過後の信号を前記第１の制御端子の制御電位としてフィードバックする。同様に、前記第２のハイパスフィルタは、前記第１の出力端子と前記第２の制御端子の間に接続され、前記差動出力信号のうち他方を入力して高周波成分を選択的に透過させるとともに、透過後の信号を前記第２の制御端子の制御電位としてフィードバックする。 The first high-pass filter is connected between the second output terminal and the first control terminal, and inputs one of the differential output signals to selectively transmit a high-frequency component and transmit the same. The later signal is fed back as the control potential of the first control terminal. Similarly, the second high-pass filter is connected between the first output terminal and the second control terminal, and inputs the other of the differential output signals to selectively transmit high-frequency components. At the same time, the transmitted signal is fed back as the control potential of the second control terminal.
　本発明の第２の態様は、差動増幅器の構成方法である。当該方法は、以下の工程（ａ）～（ｆ）を含む。
（ａ）差動入力信号のうち一方が供給されるゲートを有する第１の駆動トランジスタを配置する工程；
（ｂ）前記差動入力信号のうち他方が供給されるゲートを有し、前記第１の駆動トランジスタと共に差動対を構成する第２の駆動トランジスタを配置する工程；
（ｃ）前記第１の駆動トランジスタを流れるドレイン電流を調整するための第１の制御端子を有する第１の回路を、前記第１の駆動トランジスタのソース・ドレイン経路及び前記第１の出力端子が接続された配線上に配置する工程；
（ｄ）前記第２の駆動トランジスタを流れるドレイン電流を調整するための第２の制御端子を有する第２の回路を、前記第２の駆動トランジスタのソース・ドレイン経路及び前記第２の出力端子が接続された配線上に配置する工程；
（ｅ）前記差動対によって増幅された後の差動出力信号のうち一方を入力して高周波成分を選択的に透過させるとともに、透過後の信号を前記第１の制御端子の制御電位としてフィードバックする第１のハイパスフィルタを、前記差動出力信号が出力される第１及び第２の出力端子のうち前記第２の出力端子と前記第１の制御端子の間に接続する工程；及び
（ｆ）前記差動出力信号のうち他方を入力して高周波成分を選択的に透過させるとともに、透過後の信号を前記第２の制御端子の制御電位としてフィードバックする第２のハイパスフィルタを、前記第１の出力端子と前記第２の制御端子の間に接続する工程。 The second aspect of the present invention is a method for configuring a differential amplifier. The method includes the following steps (a) to (f).
(A) disposing a first driving transistor having a gate to which one of the differential input signals is supplied;
(B) arranging a second drive transistor having a gate to which the other of the differential input signals is supplied and constituting a differential pair together with the first drive transistor;
(C) a first circuit having a first control terminal for adjusting a drain current flowing through the first drive transistor, wherein a source / drain path of the first drive transistor and the first output terminal are Placing on connected wiring;
(D) a second circuit having a second control terminal for adjusting a drain current flowing through the second drive transistor, wherein a source / drain path of the second drive transistor and the second output terminal are Placing on connected wiring;
(E) One of differential output signals after being amplified by the differential pair is input to selectively transmit high-frequency components, and the transmitted signal is fed back as the control potential of the first control terminal. Connecting a first high-pass filter between the second output terminal of the first and second output terminals from which the differential output signal is output and the first control terminal; and (f A second high-pass filter that inputs the other of the differential output signals and selectively transmits a high-frequency component, and feeds back the transmitted signal as a control potential of the second control terminal. Connecting between the output terminal and the second control terminal.
　上述した本発明の第１の態様にかかる差動増幅器および第２態様にかかる方法によって得られる差動増幅器は、簡易な回路構成によって、利得の低下を抑制し、動作周波数帯域を拡張できる。 The above-described differential amplifier according to the first aspect of the present invention and the differential amplifier obtained by the method according to the second aspect can suppress a decrease in gain and extend an operating frequency band with a simple circuit configuration.
本発明の第１の実施形態に係る差動増幅器のフィードバックの概念を示すブロック図である。It is a block diagram which shows the concept of the feedback of the differential amplifier which concerns on the 1st Embodiment of this invention. 本発明の第１の実施形態に係る差動増幅器を示すブロック図である。1 is a block diagram showing a differential amplifier according to a first embodiment of the present invention. 本発明の第１の実施形態に係る差動増幅器の具体的な構成例（カスコード型差動増幅器）を示す回路図である。FIG. 2 is a circuit diagram showing a specific configuration example (cascode differential amplifier) of the differential amplifier according to the first embodiment of the present invention. 本発明の第２の実施形態に係る差動増幅器を示すブロック図である。It is a block diagram which shows the differential amplifier which concerns on the 2nd Embodiment of this invention. 本発明の第２の実施形態に係る差動増幅器の具体的な構成例を示す回路図である。It is a circuit diagram which shows the specific structural example of the differential amplifier which concerns on the 2nd Embodiment of this invention. 本発明の第３の実施形態に係る差動増幅器を示すブロック図である。It is a block diagram which shows the differential amplifier which concerns on the 3rd Embodiment of this invention. 本発明の第３の実施形態に係る差動増幅器の具体的な構成例（カスコード型差動増幅器）を示す回路図である。It is a circuit diagram which shows the specific structural example (cascode type | mold differential amplifier) of the differential amplifier which concerns on the 3rd Embodiment of this invention. 本発明の各実施形態に係る差動増幅器に用いる三端子出力負荷の一例を示す回路図である。It is a circuit diagram which shows an example of the 3 terminal output load used for the differential amplifier which concerns on each embodiment of this invention. 本発明の各実施形態に係る差動増幅器に用いる三端子出力負荷の一例を示す回路図である。It is a circuit diagram which shows an example of the 3 terminal output load used for the differential amplifier which concerns on each embodiment of this invention. 本発明の各実施形態に係る差動増幅器に用いる三端子出力負荷の一例を示す回路図である。It is a circuit diagram which shows an example of the 3 terminal output load used for the differential amplifier which concerns on each embodiment of this invention. 本発明の各実施形態に係る差動増幅器に用いる二端子出力負荷の一例を示す回路図である。It is a circuit diagram which shows an example of the two-terminal output load used for the differential amplifier which concerns on each embodiment of this invention. 本発明の各実施形態に係る差動増幅器に用いる二端子出力負荷の一例を示す回路図である。It is a circuit diagram which shows an example of the two-terminal output load used for the differential amplifier which concerns on each embodiment of this invention. 本発明の各実施形態に係る差動増幅器に用いる二端子出力負荷の一例を示す回路図である。It is a circuit diagram which shows an example of the two-terminal output load used for the differential amplifier which concerns on each embodiment of this invention. 本発明の各実施形態に係る差動増幅器に用いる二端子出力負荷の一例を示す回路図である。It is a circuit diagram which shows an example of the two-terminal output load used for the differential amplifier which concerns on each embodiment of this invention. 本発明の各実施形態に係る差動増幅器に用いる二端子出力負荷の一例を示す回路図である。It is a circuit diagram which shows an example of the two-terminal output load used for the differential amplifier which concerns on each embodiment of this invention. 本発明の各実施形態に係る差動増幅器に用いるハイパスフィルタの一例を示す回路図である。It is a circuit diagram which shows an example of the high pass filter used for the differential amplifier which concerns on each embodiment of this invention. 本発明の各実施形態に係る差動増幅器に用いるハイパスフィルタの一例を示す回路図である。It is a circuit diagram which shows an example of the high pass filter used for the differential amplifier which concerns on each embodiment of this invention. 本発明の各実施形態に係る差動増幅器に用いるハイパスフィルタの一例を示す回路図である。It is a circuit diagram which shows an example of the high pass filter used for the differential amplifier which concerns on each embodiment of this invention. 背景技術に係る差動増幅器の動作を示す概念図である。It is a conceptual diagram which shows operation | movement of the differential amplifier which concerns on background art. 背景技術に係る差動増幅器の動作を示す概念図である。It is a conceptual diagram which shows operation | movement of the differential amplifier which concerns on background art. 第１の実施形態に係る差動増幅器の動作を示す概念図である。FIG. 5 is a conceptual diagram illustrating an operation of the differential amplifier according to the first embodiment. 第１の実施形態に係る差動増幅器の高周波特性に関する数値計算結果の一例を背景技術のものと対比して示すグラフである。It is a graph which shows an example of the numerical calculation result regarding the high frequency characteristic of the differential amplifier which concerns on 1st Embodiment in contrast with the thing of background art. 第２の実施形態に係る差動増幅器の高周波特性に関する数値計算結果の一例を背景技術のものと対比して示すグラフである。It is a graph which shows an example of the numerical calculation result regarding the high frequency characteristic of the differential amplifier which concerns on 2nd Embodiment in contrast with the thing of background art. 背景技術にかかる差動増幅回路を示す図である。It is a figure which shows the differential amplifier circuit concerning background art. 背景技術にかかるカスコード型の差動増幅回路を示す図である。It is a figure which shows the cascode type | mold differential amplifier circuit concerning a background art. 背景技術にかかるフィードフォワードを用いたレベルシフト回路を示す図である。It is a figure which shows the level shift circuit using the feedforward concerning background art.
　以下では、本発明を適用した具体的な実施の形態について、図面を参照しながら詳細に説明する。各図面において、同一要素には同一の符号が付されており、説明の明確化のため、必要に応じて重複説明は省略される。 Hereinafter, specific embodiments to which the present invention is applied will be described in detail with reference to the drawings. In the drawings, the same elements are denoted by the same reference numerals, and redundant description is omitted as necessary for the sake of clarity.
＜第１の実施形態＞
　図１は、本発明の第１の実施形態に係る差動増幅器１００の概略構成を示すブロック図である。差動増幅器１００は、差動増幅の基本要素１２０を有する。基本要素１２０は、２つの入力端子１及び２と、２つの出力端子３及び４を有する。基本要素１２０は、差動対を有しており、入力端子１及び２に供給される差動信号を差動対によって増幅し、増幅後の差動信号を出力端子３及び４に供給する。なお、ここでは、入力端子１を正相入力端子ＩＮ、入力端子２を逆相入力端子ＩＮ＿Ｂ、出力端子３を正相出力端子ＯＵＴ、出力端子４を逆相出力端子ＯＵＴ＿Ｂとする。 <First Embodiment>
FIG. 1 is a block diagram showing a schematic configuration of a differential amplifier 100 according to the first embodiment of the present invention. The differential amplifier 100 includes a basic element 120 for differential amplification. The basic element 120 has two input terminals 1 and 2 and two output terminals 3 and 4. The basic element 120 has a differential pair, amplifies the differential signal supplied to the input terminals 1 and 2 by the differential pair, and supplies the amplified differential signal to the output terminals 3 and 4. Here, the input terminal 1 is a positive phase input terminal IN, the input terminal 2 is a negative phase input terminal IN_B, the output terminal 3 is a positive phase output terminal OUT, and the output terminal 4 is a negative phase output terminal OUT_B.
　また、差動増幅器１００は、ハイパスフィルタ（ＨＰＦ:High Pass Filter）１１１及び１１２を有する。ＨＰＦ１１１は、一端が出力端子４に接続され、多端が入力端子１及び２を除く基本要素１２０の回路内に接続されている。ＨＰＦ１１１と同様に、ＨＰＦ１１２は、出力端子３と基本要素１２０の回路内との間に接続されている。つまり、ＨＰＦ１１及び１１２は、差動増幅器１００の２つの出力信号（差動出力信号ＳＯＵＴ及びＳＯＵＴＢ）を、差動入力信号を除く差動増幅器１００の基本要素１２０内の電位にフィードバックする。 The differential amplifier 100 includes high pass filters (HPFs) 111 and 112. One end of the HPF 111 is connected to the output terminal 4, and the other end is connected to the circuit of the basic element 120 excluding the input terminals 1 and 2. Similar to the HPF 111, the HPF 112 is connected between the output terminal 3 and the circuit of the basic element 120. That is, the HPFs 11 and 112 feed back the two output signals (differential output signals S OUT and S OUTB ) of the differential amplifier 100 to the potential in the basic element 120 of the differential amplifier 100 excluding the differential input signal.
　図２は、差動増幅器１００の具体的構成の一例を示す回路図である。図２において、入力端子１及び２、出力端子３及び４並びにＨＰＦ１１１及び１１２を除くその他の構成要素が、上述した基本要素１２０に対応する。図２の差動増幅器１００は、カスコード構成を有している。以下では、図２に示された各構成要素について順に説明する。 FIG. 2 is a circuit diagram showing an example of a specific configuration of the differential amplifier 100. In FIG. 2, the other components excluding the input terminals 1 and 2, the output terminals 3 and 4, and the HPFs 111 and 112 correspond to the basic element 120 described above. The differential amplifier 100 of FIG. 2 has a cascode configuration. Below, each component shown by FIG. 2 is demonstrated in order.
　駆動トランジスタ１１及び１２は増幅用の差動対を構成する。具体的に述べると、駆動トランジスタ１１のゲートは入力端子１に接続され、駆動トランジスタ１２のゲートは入力端子２に接続されている。また、共通接続されたトランジスタ１１及び１２のソースは、定電流源１０を介して接地されている。また、駆動トランジスタ１１のドレインは、カスコードトランジスタ１３及び出力負荷１０１を介して電源端子５（ドレイン電位ＶＤＤ）に接続されている。同様に、駆動トランジスタ１２のドレインは、カスコードトランジスタ１４及び出力負荷１０２を介して電源端子５（ドレイン電位ＶＤＤ）に接続されている。 The drive transistors 11 and 12 constitute a differential pair for amplification. Specifically, the gate of the drive transistor 11 is connected to the input terminal 1, and the gate of the drive transistor 12 is connected to the input terminal 2. The sources of the commonly connected transistors 11 and 12 are grounded via the constant current source 10. The drain of the drive transistor 11 is connected to the power supply terminal 5 (drain potential V DD ) via the cascode transistor 13 and the output load 101. Similarly, the drain of the drive transistor 12 is connected to the power supply terminal 5 (drain potential V DD ) via the cascode transistor 14 and the output load 102.
　カスコードトランジスタ１３のソースは駆動トランジスタ１１のドレインに接続され、ドレインは出力負荷１０１に接続されている。また、カスコードトランジスタ１４のソースは駆動トランジスタ１２のドレインに接続され、ドレインは出力負荷１０２に接続されている。 The source of the cascode transistor 13 is connected to the drain of the drive transistor 11, and the drain is connected to the output load 101. The source of the cascode transistor 14 is connected to the drain of the drive transistor 12, and the drain is connected to the output load 102.
　出力負荷１０１の一端はカスコードトランジスタ１３のソースに接続され、他端は電源端子５に接続されている。出力負荷１０１とカスコードトランジスタ１３の共通接続点は出力端子４に接続されている。同様に、出力負荷１０２の一端はカスコードトランジスタ１４のソースに接続され、他端は電源端子５に接続されている。出力負荷１０２とカスコードトランジスタ１４の共通接続点は出力端子３に接続されている。 One end of the output load 101 is connected to the source of the cascode transistor 13 and the other end is connected to the power supply terminal 5. A common connection point between the output load 101 and the cascode transistor 13 is connected to the output terminal 4. Similarly, one end of the output load 102 is connected to the source of the cascode transistor 14, and the other end is connected to the power supply terminal 5. A common connection point between the output load 102 and the cascode transistor 14 is connected to the output terminal 3.
　ＨＰＦ１１１は、出力端子４つまりカスコードトランジスタ１３のドレインと、もう一方のカスコードトランジスタ１４のゲートの間に配置されている。つまり、ＨＰＦ１１１は、出力端子４に現れる逆相出力信号ＳＯＵＴＢの高周波成分を、逆相入力ＩＮ＿Ｂ側のカスコードトランジスタ１４にバイアス電圧として供給する。 The HPF 111 is disposed between the output terminal 4, that is, the drain of the cascode transistor 13 and the gate of the other cascode transistor 14. That is, the HPF 111 supplies the high-frequency component of the negative phase output signal S OUTB appearing at the output terminal 4 to the cascode transistor 14 on the negative phase input IN_B side as a bias voltage.
　同様に、ＨＰＦ１１２は、出力端子３つまりカスコードトランジスタ１４のドレインと、もう一方のカスコードトランジスタ１３のゲートの間に配置されている。ＨＰＦ１１２は、出力端子３に現れる正相出力信号ＳＯＵＴの高周波成分を、正相入力ＩＮ側のカスコードトランジスタ１３にバイアス電圧として供給する。 Similarly, the HPF 112 is disposed between the output terminal 3, that is, the drain of the cascode transistor 14 and the gate of the other cascode transistor 13. The HPF 112 supplies a high frequency component of the positive phase output signal S OUT appearing at the output terminal 3 as a bias voltage to the cascode transistor 13 on the positive phase input IN side.
　差動対を構成する駆動トランジスタ１１及び１２のゲートに入力された差動入力信号は、駆動トランジスタ１１及び１２、カスコードトランジスタ１３及び１４、並びに出力負荷１０１及び１０２によって増幅される。そして、カスコードトランジスタ１３及び１４のドレインである端子４及び３から差動出力信号が得られる。 The differential input signals input to the gates of the drive transistors 11 and 12 constituting the differential pair are amplified by the drive transistors 11 and 12, the cascode transistors 13 and 14, and the output loads 101 and 102. A differential output signal is obtained from the terminals 4 and 3 which are the drains of the cascode transistors 13 and 14.
　続いて以下では、定電流源１０、ＨＰＦ１１１及び１１２、並びに出力負荷１０１及び１０２の具体的な構成例について図３を参照して説明する。図３は、定電流源１０、ＨＰＦ１１１及び１１２並びに出力負荷１０１及び１０２の具体的な回路構成を含む差動増幅器１００の回路図である。 Subsequently, specific configuration examples of the constant current source 10, the HPFs 111 and 112, and the output loads 101 and 102 will be described below with reference to FIG. FIG. 3 is a circuit diagram of the differential amplifier 100 including specific circuit configurations of the constant current source 10, the HPFs 111 and 112, and the output loads 101 and 102.
　図３の構成例では、定電流源１０は電流源トランジスタ１５を含む。電流源トランジスタ１５のゲートは定電流源用バイアス電圧が入力されるバイアス端子７に接続され、電流源トランジスタのソースはグランドに接地される。また、トランジスタ１５のドレインは駆動トランジスタ１１及び１２のソースに共通接続されている。 3, the constant current source 10 includes a current source transistor 15. The gate of the current source transistor 15 is connected to a bias terminal 7 to which a constant current source bias voltage is input, and the source of the current source transistor is grounded. The drain of the transistor 15 is commonly connected to the sources of the drive transistors 11 and 12.
　また、図３の構成例では、出力負荷１０１は抵抗素子２１を含む。同様に、出力負荷１０２は抵抗素子２２を含む。 Further, in the configuration example of FIG. 3, the output load 101 includes a resistance element 21. Similarly, the output load 102 includes a resistance element 22.
　また、図３の構成例では、ＨＰＦ１１１は抵抗素子２３及び容量素子４１を含む。抵抗素子２３と容量素子４１は直列に接続され、容量素子４１の他方の端子は出力端子４に接続され、抵抗素子２３の他方の端子はバイアス端子６に接続される。また、抵抗素子２３と容量素子４１の接点はＨＰＦ１１１の出力としてカスコードトランジスタ１４のゲートに接続される。同様に、図３の構成例では、ＨＰＦ１１２は抵抗素子２４及び容量素子４２を含む。抵抗素子２４と容量素子４２は直列に接続され、容量素子４２の他方の端子は出力端子３に接続され、抵抗素子２４の他方の端子はバイアス端子６に接続される。また、抵抗素子２４と容量素子４２の接点はＨＰＦ１１２の出力としてカスコードトランジスタ１３のゲートに接続される。このときＨＰＦ１１１及び１１２の通過周波数は容量素子４１及び４２の容量値と抵抗素子２３及び２４の抵抗値によって決まる。例えば、この通過周波数は、差動増幅器１００の基本要素１２０の利得低下の始まる周波数付近であり、かつ利得変動幅が３ｄＢ程度に収まるように設定するとよい。 Further, in the configuration example of FIG. 3, the HPF 111 includes a resistance element 23 and a capacitance element 41. The resistive element 23 and the capacitive element 41 are connected in series, the other terminal of the capacitive element 41 is connected to the output terminal 4, and the other terminal of the resistive element 23 is connected to the bias terminal 6. The contact point between the resistance element 23 and the capacitive element 41 is connected to the gate of the cascode transistor 14 as an output of the HPF 111. Similarly, in the configuration example of FIG. 3, the HPF 112 includes a resistance element 24 and a capacitance element 42. The resistive element 24 and the capacitive element 42 are connected in series, the other terminal of the capacitive element 42 is connected to the output terminal 3, and the other terminal of the resistive element 24 is connected to the bias terminal 6. The contact point between the resistance element 24 and the capacitive element 42 is connected to the gate of the cascode transistor 13 as an output of the HPF 112. At this time, the pass frequencies of the HPFs 111 and 112 are determined by the capacitance values of the capacitive elements 41 and 42 and the resistance values of the resistive elements 23 and 24. For example, this passing frequency may be set so that the gain of the basic element 120 of the differential amplifier 100 begins to decrease and the gain fluctuation range is within about 3 dB.
［動作の説明］
　次に図１９Ａ～１９Ｃを用いて、差動増幅器１００の動作について説明する。図１９Ａ～１９Ｃは、差動対の一方のトランジスタ１１とその周辺の回路要素を抜き出して示す模式図である。なお、図１９Ｃは、差動増幅器１００に関する図であり、図１９Ａ及び１９Ｂは対比のために示す背景技術に関する図である。 [Description of operation]
Next, the operation of the differential amplifier 100 will be described with reference to FIGS. 19A to 19C. FIGS. 19A to 19C are schematic diagrams showing one transistor 11 of a differential pair and its peripheral circuit elements. 19C is a diagram related to the differential amplifier 100, and FIGS. 19A and 19B are diagrams related to the background art shown for comparison.
　図１９Ａは、図２２に示した差動増幅器７００の場合を示している。この場合、信号入力端子１から見ると、駆動トランジスタ１１のゲート容量ＣＧＤを介して出力端子４につながる負荷容量ＣＬの影響を受けてしまう。このため、高い周波数ではトランジスタ１１を駆動できなくなり利得が低下し、差動増幅器７００の増幅可能な周波数帯域は狭くなってしまう。 FIG. 19A shows the case of the differential amplifier 700 shown in FIG. In this case, when viewed from the signal input terminal 1, the load capacitance C L connected to the output terminal 4 through the gate capacitance C GD of the drive transistor 11 is affected. For this reason, the transistor 11 cannot be driven at a high frequency, the gain is reduced, and the frequency band that can be amplified by the differential amplifier 700 is narrowed.
　また、図１９Ｂは、図２３に示したカスコード構成の差動増幅器８００の場合を示している。この場合、負荷容量ＣＬの影響はカスコードトランジスタ１３で遮られている。したがって、入力端子１からは駆動トランジスタ１１のＣＧＤを介してカスコードトランジスタ１３のＣＧＳの影響しか受けない。カスコードトランジスタ１３のＣＧＳは負荷容量ＣＬに比べて小さいので、差動増幅器８００は差動増幅器７００に比べて高い周波数まで駆動でき、増幅可能な周波数帯域が広がる。 FIG. 19B shows the case of the differential amplifier 800 having the cascode configuration shown in FIG. In this case, the influence of the load capacitance C L is blocked by the cascode transistor 13. Therefore, from the input terminal 1 does not receive only the influence of the C GS of the cascode transistor 13 through C GD of the driving transistor 11. Since C GS of the cascode transistor 13 is smaller than the load capacitance C L , the differential amplifier 800 can be driven to a higher frequency than the differential amplifier 700, and the frequency band that can be amplified is expanded.
　図１９Ｃは、本実施形態にかかる差動増幅器１００の模式図である。図１９Ｃに示すように、カスコードトランジスタ１３のゲートに正相出力信号ＳＯＵＴがフィードバックされることにより、信号入力端子１である駆動トランジスタ１１のゲートと同相の信号がカスコードトランジスタ１３のゲートに供給される。よって、差動増幅器１００は、カスコードトランジスタ１３及び１４を配置したことによる上記の効果に加えて、入力端子１から見た駆動トランジスタ１１のＣＧＤとカスコードトランジスタ１３のＣＧＳの影響を限りなくゼロに近づけることができる。 FIG. 19C is a schematic diagram of the differential amplifier 100 according to the present embodiment. As shown in FIG. 19C, the positive-phase output signal S OUT is fed back to the gate of the cascode transistor 13, whereby a signal in phase with the gate of the drive transistor 11 that is the signal input terminal 1 is supplied to the gate of the cascode transistor 13. The Therefore, in addition to the above-described effect due to the arrangement of the cascode transistors 13 and 14, the differential amplifier 100 eliminates the effects of the C GD of the drive transistor 11 and the C GS of the cascode transistor 13 as viewed from the input terminal 1 as much as possible. Can be approached.
　この作用は、ＨＰＦ１１２によって、カスコード構成の増幅器７００の利得が落ち始める周波数付近から効果が発生するので、低下し始める利得を押し上げてより高い周波数まで利得を得ることができる。また、利得が落ち始めてからフィードバックの効果が生じ始めるので、発振の抑制効果もある。以上のような理由から、差動増幅器１００は、より高い周波数まで動作帯域を広げることができる。 This effect is produced by the HPF 112 from the vicinity of the frequency at which the gain of the cascode-configured amplifier 700 starts to decrease, so that the gain starting to decrease can be increased to obtain a gain up to a higher frequency. In addition, since the feedback effect starts to occur after the gain starts to decrease, there is also an effect of suppressing oscillation. For the reasons described above, the differential amplifier 100 can expand the operating band to a higher frequency.
　また、差動増幅器１００は、高周波帯域での利得低下を抑制する効果を得るために新たに電流を流す必要がなく、また加えられる素子（ＨＰＦ１１１及び１１２）も小さいものである。このため、消費電力の増大や著しい面積の増加を抑制しながら高周波特性を向上させることができる。 Further, the differential amplifier 100 does not require a new current to flow in order to obtain an effect of suppressing a gain reduction in a high frequency band, and the added elements (HPFs 111 and 112) are also small. For this reason, high frequency characteristics can be improved while suppressing an increase in power consumption and a significant increase in area.
　図２０は、差動増幅器１００の利得の周波数特性の計算結果の一例を示すグラフである。差動増幅器７００では、１ｄＢ利得低下周波数が２００ＭＨｚ程度である（図２０のグラフＬ１１）。また、カスコード構成の差動増幅器８００では、増幅器７００に比べて２倍程度の４００ＭＨｚ以上の帯域が得られている（図２０のグラフＬ２１）。これらに対して、本実施形態に係る差動増幅器１００では、増幅器７００に比べて５倍以上の１ＧＨｚを越える帯域が得られる（図２０のグラフＬ３１）。 FIG. 20 is a graph showing an example of the calculation result of the frequency characteristics of the gain of the differential amplifier 100. In the differential amplifier 700, the 1 dB gain reduction frequency is about 200 MHz (graph L11 in FIG. 20). Further, in the differential amplifier 800 having a cascode configuration, a band of 400 MHz or more, which is about twice that of the amplifier 700, is obtained (graph L21 in FIG. 20). On the other hand, in the differential amplifier 100 according to the present embodiment, a band exceeding 1 GHz, which is five times or more that of the amplifier 700, is obtained (graph L31 in FIG. 20).
　ところで、図３に示した回路構成が一例にすぎないことは勿論である。例えば、出力負荷１０１は、抵抗素子２１（図１１）に限られず、インダクタ素子３１（図１２）、抵抗素子２１とインダクタ素子３１の並列回路（図１３）、抵抗素子２１とインダクタ素子３１の直列回路（図１４）、又は抵抗素子２１とインダクタ素子３１の直列回路と容量素子４５の並列回路であっても同様の効果を得ることができる。 Of course, the circuit configuration shown in FIG. 3 is merely an example. For example, the output load 101 is not limited to the resistance element 21 (FIG. 11), but includes an inductor element 31 (FIG. 12), a parallel circuit of the resistance element 21 and the inductor element 31 (FIG. 13), and a series of the resistance element 21 and the inductor element 31. The same effect can be obtained even with a circuit (FIG. 14), or a series circuit of the resistive element 21 and the inductor element 31 and a parallel circuit of the capacitive element 45.
　また、例えば、ＨＰＦ１１１は、抵抗素子２４と容量素子４１で構成される回路（図１７）に限られず、容量素子４１とインダクタ素子３２で構成される回路、又は抵抗素子２３とインダクタ素子３２の直列接続に容量素子４１を接続した回路（図１８）であっても同様の効果を得ることができる。 Further, for example, the HPF 111 is not limited to a circuit (FIG. 17) configured by the resistance element 24 and the capacitive element 41, but is a circuit configured by the capacitive element 41 and the inductor element 32, or a series of the resistive element 23 and the inductor element 32. The same effect can be obtained even in a circuit (FIG. 18) in which the capacitive element 41 is connected to the connection.
＜第２の実施形態＞
　図４は本実施形態に係る差動増幅器２００の構成を示す回路図である。図４において、入力端子１及び２、出力端子３及び４並びにＨＰＦ１１３及び１１４を除くその他の構成要素は、差動増幅器２００の基本要素１２０に対応する。図４の構成と上述した図２を比べると、（ａ）図４の差動増幅器２００がカスコード構成出ない点、（ｂ）ＨＰＦ１１３及び１１４が出力端子３及び４に現れる差動出力信号ＳＯＵＴ及びＳＯＵＴＢを出力負荷１０１及び１０３にフィードバックしている点の２点が相違している。 <Second Embodiment>
FIG. 4 is a circuit diagram showing a configuration of the differential amplifier 200 according to the present embodiment. In FIG. 4, the other components excluding the input terminals 1 and 2, the output terminals 3 and 4, and the HPFs 113 and 114 correspond to the basic element 120 of the differential amplifier 200. 4 is compared with FIG. 2 described above, (a) the differential amplifier 200 of FIG. 4 does not have a cascode configuration, and (b) the differential output signal S OUT in which the HPFs 113 and 114 appear at the output terminals 3 and 4. And S OUTB are fed back to the output loads 101 and 103 in two points.
　図５は、出力負荷１０１及び１０２並びにＨＰＦ１１３及び１１４の具体的な回路構成を含む差動増幅器２００の回路図である。 FIG. 5 is a circuit diagram of the differential amplifier 200 including specific circuit configurations of the output loads 101 and 102 and the HPFs 113 and 114.
　図５の例では、出力負荷１０１は、抵抗素子２１とこれに並列接続された負荷トランジスタ１６を含む。Ｐチャネル・トランジスタである負荷トランジスタ１６のドレインは、抵抗素子２１の一端と共に駆動トランジスタ１１のドレインに接続されている。負荷トランジスタ１６のソースは、電源端子５に接続されている。同様に、出力負荷１０２は、抵抗素子２２とこれに並列接続された負荷トランジスタ１７を含む。Ｐチャネル・トランジスタである負荷トランジスタ１７のドレインは、抵抗素子２２の一端と共に駆動トランジスタ１２のドレインに接続されている。負荷トランジスタ１７のソースは、電源端子５に接続されている。 In the example of FIG. 5, the output load 101 includes a resistance element 21 and a load transistor 16 connected in parallel thereto. The drain of the load transistor 16 which is a P-channel transistor is connected to the drain of the driving transistor 11 together with one end of the resistance element 21. The source of the load transistor 16 is connected to the power supply terminal 5. Similarly, the output load 102 includes a resistance element 22 and a load transistor 17 connected in parallel thereto. The drain of the load transistor 17 which is a P-channel transistor is connected to the drain of the driving transistor 12 together with one end of the resistance element 22. The source of the load transistor 17 is connected to the power supply terminal 5.
　図５の例では、ＨＰＦ１１３は、抵抗素子２５及び容量素子４３を含む。抵抗素子２５と容量素子４３は直列に接続され、容量素子４３の他方の端子は出力端子３に接続され、抵抗素子２５の他方の端子はバイアス端子８に接続される。また、抵抗素子２５と容量素子４３の接点はＨＰＦ１１３の出力として負荷トランジスタ１６のゲートに接続される。同様に、図５の構成例では、ＨＰＦ１１４は抵抗素子２６及び容量素子４４を含む。抵抗素子２６と容量素子４４は直列に接続され、容量素子４４の他方の端子は出力端子４に接続され、抵抗素子２６の他方の端子はバイアス端子８に接続される。また、抵抗素子２６と容量素子４４の接点はＨＰＦ１１４の出力として負荷トランジスタ１７のゲートに接続される。このときＨＰＦ１１３及び１１４の通過周波数は容量素子４３及び４４の容量値と抵抗素子２５及び２６の抵抗値によって決まる。例えば、この通過周波数は、差動増幅器２００の基本要素１２０の利得低下の始まる周波数付近であり、かつ利得変動幅が３ｄＢ程度に収まるように設定するとよい。 In the example of FIG. 5, the HPF 113 includes a resistance element 25 and a capacitance element 43. The resistive element 25 and the capacitive element 43 are connected in series, the other terminal of the capacitive element 43 is connected to the output terminal 3, and the other terminal of the resistive element 25 is connected to the bias terminal 8. The contact point between the resistance element 25 and the capacitive element 43 is connected to the gate of the load transistor 16 as an output of the HPF 113. Similarly, in the configuration example of FIG. 5, the HPF 114 includes the resistance element 26 and the capacitance element 44. The resistive element 26 and the capacitive element 44 are connected in series, the other terminal of the capacitive element 44 is connected to the output terminal 4, and the other terminal of the resistive element 26 is connected to the bias terminal 8. The contact point between the resistor element 26 and the capacitor element 44 is connected to the gate of the load transistor 17 as an output of the HPF 114. At this time, the pass frequencies of the HPFs 113 and 114 are determined by the capacitance values of the capacitive elements 43 and 44 and the resistance values of the resistive elements 25 and 26. For example, the passing frequency may be set to be around the frequency at which the gain reduction of the basic element 120 of the differential amplifier 200 starts and the gain fluctuation range is within about 3 dB.
　つまり、本実施形態における出力負荷１０１は、能動素子としての負荷トランジスタ１６を有しており、ＨＰＦ１１３を介してフィードバックされた信号が負荷トランジスタ１６のゲートに供給されることで能動負荷として機能する。なお、図４及び５に示した他の回路要素及びこれらの接続関係は、上述した差動増幅器１００と同様であるため、ここでは重複説明を省略する。 That is, the output load 101 in the present embodiment has the load transistor 16 as an active element, and functions as an active load when a signal fed back via the HPF 113 is supplied to the gate of the load transistor 16. The other circuit elements shown in FIGS. 4 and 5 and their connection relations are the same as those of the differential amplifier 100 described above, and therefore, redundant description is omitted here.
［動作の説明］
　以下では、差動増幅器２００の動作について説明する。差動増幅器２００の信号入力端子１及び２に差動信号が入力されると、出力端子３及び４から増幅された信号が出力される。このとき、差動入力信号の周波数が低い状態では、負荷トランジスタ１６及び１７のゲートにはバイアス端子８から直流バイアスがかかっているだけある。つまり、ＨＰＦ１１３及び１１４の遮断特性が働くために、出力端子４及び３からのフィードバック信号は負荷トランジスタ１６及び１７のゲートに入力されない。 [Description of operation]
Hereinafter, the operation of the differential amplifier 200 will be described. When differential signals are input to the signal input terminals 1 and 2 of the differential amplifier 200, amplified signals are output from the output terminals 3 and 4. At this time, when the frequency of the differential input signal is low, the gates of the load transistors 16 and 17 are only DC biased from the bias terminal 8. That is, since the cutoff characteristics of the HPFs 113 and 114 work, the feedback signals from the output terminals 4 and 3 are not input to the gates of the load transistors 16 and 17.
　次に、差動入力信号の周波数が上がった場合を説明する。図１９Ａに示すように、信号入力端子１及び２から見ると、駆動トランジスタ１１及び１２のゲート容量ＣＧＤを介して増幅器出力につながる負荷容量ＣＬの影響を受けてしまい、高い周波数では駆動できなくなり利得が低下する。しかしながら、本実施の形態では、信号周波数が上がったことにより、差動出力信号がＨＰＦ１１３及び１１４を通過し、通過後の信号が負荷トランジスタ１６及び１７のゲートに入力される。これによって出力信号と同相でトランジスタ１１及び１２を流れるドレイン電流が増減するため、増幅器２００の利得が上がる。また、この作用は、ＨＰＦ１１３及び１１４によって、駆動トランジスタ１１及び１２による利得が落ち始める周波数付近から効果が発生するので、低下し始める利得を押し上げてより高い周波数まで利得を得ることができる。また、利得が落ち始めてからフィードバックの効果が生じ始めるので、発振の抑制効果もある。以上のような理由から、差動増幅器２００は、より高い周波数まで動作帯域を広げることができる。 Next, a case where the frequency of the differential input signal is increased will be described. As shown in FIG. 19A, when viewed from the signal input terminal 1 and 2, via the gate capacitance C GD of the driving transistor 11 and 12 will under the influence of the load capacitance C L connected to the amplifier output can be driven at high frequency The gain is reduced. However, in the present embodiment, as the signal frequency increases, the differential output signal passes through the HPFs 113 and 114, and the signal after passing is input to the gates of the load transistors 16 and 17. As a result, the drain current flowing through the transistors 11 and 12 in phase with the output signal increases and decreases, and the gain of the amplifier 200 increases. In addition, since this effect is produced by the HPFs 113 and 114 from the vicinity of the frequency at which the gain by the driving transistors 11 and 12 starts to decrease, the gain that starts to decrease can be boosted to obtain a gain up to a higher frequency. In addition, since the feedback effect starts to occur after the gain starts to decrease, there is also an effect of suppressing oscillation. For the reasons described above, the differential amplifier 200 can expand the operating band to a higher frequency.
　また、差動増幅器２００は、高周波帯域での利得低下を抑制する効果を得るために新たに電流を流す必要がなく、また加えられる素子（ＨＰＦ１１３及び１１４）も小さいものである。このため、消費電力の増大や著しい面積の増加を抑制しながら高周波特性を向上させることができる。 Further, the differential amplifier 200 does not require a new current to flow in order to obtain an effect of suppressing a gain reduction in a high frequency band, and the added elements (HPFs 113 and 114) are small. For this reason, high frequency characteristics can be improved while suppressing an increase in power consumption and a significant increase in area.
　図２１は、差動増幅器２００の利得の周波数特性の計算結果の一例を示すグラフである。図２１のグラフＬ１２は図２２に示した増幅器７００の利得の周波数特性を示している。一方、図２１のグラフ３２は、差動増幅器２００の利得の周波数特性の一例である。本実施形態にかかる差動増幅器２００は、差動増幅器７００から動作帯域を大きく広げられることが計算でも示されている。 FIG. 21 is a graph showing an example of the calculation result of the frequency characteristics of the gain of the differential amplifier 200. A graph L12 in FIG. 21 shows frequency characteristics of the gain of the amplifier 700 shown in FIG. On the other hand, the graph 32 in FIG. 21 is an example of the frequency characteristic of the gain of the differential amplifier 200. Calculations also show that the differential amplifier 200 according to the present embodiment can greatly expand the operating band from the differential amplifier 700.
　ところで、図５に示した回路構成が一例にすぎないことは勿論である。例えば、出力負荷１０２は、抵抗素子２１と負荷トランジスタ１６の並列接続回路（図９）に限られず、負荷トランジスタ１６（図８）、又はインダクタ素子３１と負荷トランジスタ１６の並列回路（図１０）を用いた場合でも同様の効果を得ることができる。 Of course, the circuit configuration shown in FIG. 5 is merely an example. For example, the output load 102 is not limited to the parallel connection circuit (FIG. 9) of the resistance element 21 and the load transistor 16, but includes the load transistor 16 (FIG. 8) or the parallel circuit of the inductor element 31 and the load transistor 16 (FIG. 10). Even when used, the same effect can be obtained.
＜第３の実施形態＞
　図６は本実施形態にかかるカスコード型の差動増幅器３００の回路図である。また、図７は、出力負荷１０１及び１０２並びにＨＰＦ１１１、１１２、１１３及び１１４の具体的な回路構成を含む差動増幅器３００の回路図である。図６及び図７から明らかであるように、差動増幅器３００は、上述した差動増幅器１００及び２００が有するフィードバック構成を組み合わせたものである。つまり、ＨＰＦ１１１及び１１２は、差動出力信号をカスコードトランジスタ１３及び１４のゲートにフィードバックする。また、ＨＰＦ１１３及び１１４は、差動出力信号を出力負荷１０１及び１０２のインピーダンスを制御するための制御端子（負荷トランジスタ１６及び１７のゲート）にフィードバックする。なお、図６及び７に示す各回路要素およびこれらの接続関係は、発明の実施形態１及び２に関して既に説明した通りである。 <Third Embodiment>
FIG. 6 is a circuit diagram of a cascode differential amplifier 300 according to this embodiment. FIG. 7 is a circuit diagram of the differential amplifier 300 including specific circuit configurations of the output loads 101 and 102 and the HPFs 111, 112, 113, and 114. As is clear from FIGS. 6 and 7, the differential amplifier 300 is a combination of the feedback configurations of the differential amplifiers 100 and 200 described above. That is, the HPFs 111 and 112 feed back the differential output signal to the gates of the cascode transistors 13 and 14. The HPFs 113 and 114 feed back the differential output signals to control terminals (gates of the load transistors 16 and 17) for controlling the impedances of the output loads 101 and 102. The circuit elements shown in FIGS. 6 and 7 and their connection relations are as already described with respect to the first and second embodiments.
　本実施の形態にかかる差動増幅器３００は、出力負荷１０１及び１０２の制御端子へのフィードバックによって高周波での駆動力を向上させるとともに、出力負荷１０１及び１０２の制御端子へのフィードバックにより入力端子に対するミラー効果が軽減される。よって、差動増幅器３００は、より高い周波数まで動作帯域を広げることができる。 The differential amplifier 300 according to the present embodiment improves the driving force at a high frequency by feedback to the control terminals of the output loads 101 and 102, and mirrors the input terminals by feedback to the control terminals of the output loads 101 and 102. The effect is reduced. Therefore, the differential amplifier 300 can expand the operation band to a higher frequency.
　上述した本発明の各実施の形態によれば、以下に述べる効果が得られる。すなわち、差動入力信号の周波数が差動増幅器（例えば増幅器１００）の利得低下が生じ始めるような高い周波数になると、差動出力信号が第１及び第２のハイパスフィルタ（例えばＨＰＦ１１１及び１１２）を通過するようになる。つまり、差動増幅器の動作周波数の上昇によって差動対を構成する第１及び第２の駆動トランジスタ（例えばトランジスタ１１及び１２）の利得が低下し始めると同時に、動作周波数が上がったことで第１及び第２のハイパスフィルタを通過した差動出力信号の高周波成分が差動増幅器内にフォードバックされる。このフィードバックによって、当該差動増幅器は高周波帯域での出力を上昇させるように作用する。これにより、当該差動増幅器は、簡易な回路構成によって、利得の低下を抑制し、動作周波数帯域を拡張できる。 According to each embodiment of the present invention described above, the following effects can be obtained. That is, when the frequency of the differential input signal becomes a high frequency at which the gain of the differential amplifier (eg, amplifier 100) starts to decrease, the differential output signal passes through the first and second high-pass filters (eg, HPFs 111 and 112). To pass. That is, as the operating frequency of the differential amplifier increases, the gains of the first and second drive transistors (for example, the transistors 11 and 12) constituting the differential pair begin to decrease, and at the same time, the operating frequency increases. The high-frequency component of the differential output signal that has passed through the second high-pass filter is ford-backed into the differential amplifier. By this feedback, the differential amplifier acts to increase the output in the high frequency band. As a result, the differential amplifier can suppress the decrease in gain and extend the operating frequency band with a simple circuit configuration.
　上述した第１～第３の実施形態では、単純な差動増幅器に関する例を述べたが、折り返し型差動増幅器やシングルエンド増幅器でも同様にハイパスフィルタを用いたフィードバックで動作帯域を広げることができる。 In the above-described first to third embodiments, examples related to simple differential amplifiers have been described. However, in the case of folded differential amplifiers and single-ended amplifiers as well, the operating band can be expanded by feedback using a high-pass filter. .
　シングルエンド増幅器に適用する場合以下のように構成すればよい。シングルエンド増幅器の出力は一般的に入力と反対位相になるが、ＨＰＦ１１１、１１３等を介したフィードバックには入力信号と同相の信号が必要である。よって、シングルエンド増幅器の出力信号から同相信号を生成する回路を配置し、当該回路の出力をＨＰＦ１１１、１１３等を介してシングルエンド増幅器内にフィードバックすればよい。例えば、２つのシングルエンド増幅器を並列配置し、位相差がπラジアンである２つの信号を２つのシングルエンド増幅器に入力し、２つの出力信号をそれぞれ他の一方のシングルエンド増幅器内にＨＰＦ１１１又は１１３を介してフィードバックすればよい。シングルエンド増幅器内へのフィードバック先は、駆動トランジスタのドレイン電流を制御することが可能なカスコードトランジスタの制御端子又は出力負荷の制御端子とすればよい。 When applied to a single-ended amplifier, the following configuration may be used. The output of a single-ended amplifier is generally in the opposite phase to the input, but a signal in phase with the input signal is required for feedback via the HPF 111, 113, etc. Therefore, a circuit that generates an in-phase signal from the output signal of the single-ended amplifier may be arranged, and the output of the circuit may be fed back into the single-ended amplifier via the HPFs 111 and 113. For example, two single-ended amplifiers are arranged in parallel, two signals having a phase difference of π radians are input to the two single-ended amplifiers, and the two output signals are respectively supplied to the HPF 111 or 113 in the other single-ended amplifier. You can feed back through. The feedback destination into the single-ended amplifier may be the control terminal of the cascode transistor or the control terminal of the output load that can control the drain current of the driving transistor.
　さらに、本発明は上述した実施の形態のみに限定されるものではなく、既に述べた本発明の要旨を逸脱しない範囲において種々の変更が可能であることは勿論である。 Furthermore, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the present invention already described.
　この出願は、２００８年９月２日に出願された日本出願 特願２００８－２２５０８７を基礎とする優先権を主張し、その開示の全てをここに取り込む。 This application claims priority based on Japanese Patent Application No. 2008-225087 filed on September 2, 2008, the entire disclosure of which is incorporated herein.
１、２　入力端子
３、４　出力端子
５、６、７、８　バイアス端子
１０　電流源
１１～１７　トランジスタ
２１～２６　抵抗素子
３１、３２　インダクタ素子
４１～４４　容量素子
１００、２００、３００　差動増幅器
１０１、１０２　出力負荷
１１１～１１４　ハイパスフィルタ（ＨＰＦ） 1, 2 Input terminal 3, 4 Output terminal 5, 6, 7, 8 Bias terminal 10 Current source 11-17 Transistor 21-26 Resistor element 31, 32 Inductor element 41-44 Capacitance element 100, 200, 300 Differential amplifier 101 , 102 Output load 111 to 114 High pass filter (HPF)

Claims (18)

  1. 　差動入力信号のうち一方が供給されるゲートを有する第１の駆動トランジスタと、
    　前記差動入力信号のうち他方が供給されるゲートを有し、前記第１の駆動トランジスタと共に差動対を構成する第２の駆動トランジスタと、
    　前記差動対によって増幅された後の差動出力信号が出力される第１及び第２の出力端子と、
    　前記第１の駆動トランジスタのソース・ドレイン経路及び前記第１の出力端子が接続された配線上に配置され、前記第１の駆動トランジスタを流れるドレイン電流を調整可能な第１の制御端子を有する第１の回路と、
    　前記第２の駆動トランジスタのソース・ドレイン経路及び前記第２の出力端子が接続された配線上に配置され、前記第２の駆動トランジスタを流れるドレイン電流を調整可能な第２の制御端子を有する第２の回路と、
    　前記第２の出力端子と前記第１の制御端子の間に接続され、前記差動出力信号のうち一方を入力して高周波成分を選択的に透過させるとともに、透過後の信号を前記第１の制御端子の制御電位としてフィードバックする第１のハイパスフィルタと、
    　前記第１の出力端子と前記第２の制御端子の間に接続され、前記差動出力信号のうち他方を入力して高周波成分を選択的に透過させるとともに、透過後の信号を前記第２の制御端子の制御電位としてフィードバックする第２のハイパスフィルタと、
    を備える差動増幅器。     A first drive transistor having a gate to which one of the differential input signals is supplied;
    A second drive transistor having a gate to which the other one of the differential input signals is supplied and constituting a differential pair together with the first drive transistor;
    First and second output terminals from which a differential output signal amplified by the differential pair is output;
    A first control terminal is provided on the wiring connected to the source / drain path of the first driving transistor and the first output terminal, and has a first control terminal capable of adjusting a drain current flowing through the first driving transistor. 1 circuit,
    A second control terminal disposed on a wiring to which the source / drain path of the second drive transistor and the second output terminal are connected, and having a second control terminal capable of adjusting a drain current flowing through the second drive transistor; 2 circuits,
    Connected between the second output terminal and the first control terminal, one of the differential output signals is input to selectively transmit a high frequency component, and the transmitted signal is transmitted to the first output terminal. A first high-pass filter that feeds back as a control potential of the control terminal;
    Connected between the first output terminal and the second control terminal, the other of the differential output signals is input to selectively transmit a high-frequency component, and the signal after transmission is transmitted to the second output terminal. A second high-pass filter that feeds back as a control potential of the control terminal;
    A differential amplifier.
  2. 　前記第１の回路は、前記第１の駆動トランジスタのドレイン及び電源電位の間に接続される一対の端子と、前記第１の制御端子とを有する三端子の第１の出力負荷を含み、
    　前記第２の回路は、前記第２の駆動トランジスタのドレイン及び前記電源電位の間に接続される一対の端子と、前記第２の制御端子とを有する三端子の第２の出力負荷を含む、請求項１記載の差動増幅器。     The first circuit includes a three-terminal first output load having a pair of terminals connected between a drain of the first driving transistor and a power supply potential, and the first control terminal,
    The second circuit includes a three-terminal second output load having a pair of terminals connected between the drain of the second driving transistor and the power supply potential, and the second control terminal. The differential amplifier according to claim 1.
  3. 　前記第１の回路は、
    　ドレインが前記第１の制御端子であり、ソースが前記第１の駆動トランジスタのドレインに接続され、ドレインが前記第１の出力端子に接続される第１のカスコードトランジスタと、
    　一方の端子が前記第１のカスコードトランジスタのドレインに接続され、他方の端子が電源電位に接続される二端子の出力負荷とを備え、
    　前記第２の回路は、
    　ドレインが前記第２の制御端子であり、ソースが前記第２の駆動トランジスタのドレインに接続され、ドレインが前記第２の出力端子に接続される第２のカスコードトランジスタと、
    　一方の端子が前記第２のカスコードトランジスタのドレインに接続され、他方の端子が前記電源電位に接続される二端子の出力負荷とを備える、請求項１記載の差動増幅器。     The first circuit includes:
    A first cascode transistor having a drain connected to the first control terminal, a source connected to the drain of the first drive transistor, and a drain connected to the first output terminal;
    A two-terminal output load having one terminal connected to the drain of the first cascode transistor and the other terminal connected to a power supply potential;
    The second circuit includes:
    A second cascode transistor having a drain connected to the second control terminal, a source connected to the drain of the second drive transistor, and a drain connected to the second output terminal;
    The differential amplifier according to claim 1, further comprising: a two-terminal output load having one terminal connected to the drain of the second cascode transistor and the other terminal connected to the power supply potential.
  4. 　ソースが前記第１の駆動トランジスタのドレインに接続され、ドレインが前記第１の出力端子及び前記第１の出力負荷に接続される第１のカスコードトランジスタと、
    　ソースが前記第２の駆動トランジスタのドレインに接続され、ドレインが前記第２の出力端子及び前記第２の出力負荷に接続される第２のカスコードトランジスタと、
    　前記第１のカスコードトランジスタのゲートと前記第２の出力端子との間に接続され、前記差動出力信号のうち一方を入力して高周波成分を選択的に透過させるとともに、透過後の信号を前記第１のカスコードトランジスタのゲートの制御電位としてフィードバックする第３のハイパスフィルタと、
    　前記第２のカスコードトランジスタのゲートと前記第１の出力端子との間に接続され、前記差動出力信号のうち一方を入力して高周波成分を選択的に透過させるとともに、透過後の信号を前記第２のカスコードトランジスタのゲートの制御電位としてフィードバックする第４のハイパスフィルタと、
    をさらに備える、請求項２記載の差動増幅器。     A first cascode transistor having a source connected to the drain of the first drive transistor and a drain connected to the first output terminal and the first output load;
    A second cascode transistor having a source connected to the drain of the second drive transistor and a drain connected to the second output terminal and the second output load;
    The first cascode transistor is connected between the gate and the second output terminal, and one of the differential output signals is input to selectively transmit a high-frequency component, and the transmitted signal is transmitted through the first cascode transistor. A third high-pass filter that feeds back as a control potential of the gate of the first cascode transistor;
    The second cascode transistor is connected between the gate and the first output terminal, and one of the differential output signals is input to selectively transmit high-frequency components, and the signal after transmission is transmitted to the first cascode transistor. A fourth high-pass filter that feeds back as a control potential of the gate of the second cascode transistor;
    The differential amplifier according to claim 2, further comprising:
  5. 　前記第１の出力負荷は、前記一対の端子の一方に接続されたドレインと、前記一対の端子の他方に接続されたソースと、前記第１の制御端子に接続されたゲートを有する第１の負荷トランジスタを含み、
    　前記第２の出力負荷は、前記一対の端子の一方に接続されたドレインと、前記一対の端子の他方に接続されたソースと、前記第２の制御端子に接続されたゲートを有する第２の負荷トランジスタを含む、請求項２又は４記載の差動増幅器。     The first output load includes a drain connected to one of the pair of terminals, a source connected to the other of the pair of terminals, and a gate connected to the first control terminal. Including a load transistor,
    The second output load includes a drain connected to one of the pair of terminals, a source connected to the other of the pair of terminals, and a gate connected to the second control terminal. The differential amplifier according to claim 2, comprising a load transistor.
  6. 　前記第１の出力負荷は、前記第１の負荷トランジスタのソース・ドレイン間に並列に接続された抵抗素子をさらに含み、
    　前記第２の出力負荷は、前記第２の負荷トランジスタのソース・ドレイン間に並列に接続された抵抗素子をさらに含む、請求項５記載の差動増幅器。     The first output load further includes a resistance element connected in parallel between the source and drain of the first load transistor,
    The differential amplifier according to claim 5, wherein the second output load further includes a resistance element connected in parallel between a source and a drain of the second load transistor.
  7. 　前記第１の出力負荷は、前記第１の負荷トランジスタのソース・ドレイン間に並列に接続されたインダクタ素子をさらに含み、
    　前記第２の出力負荷は、前記第２の負荷トランジスタのソース・ドレイン間に並列に接続されたインダクタ素子をさらに含む、請求項５記載の差動増幅器。     The first output load further includes an inductor element connected in parallel between the source and drain of the first load transistor,
    The differential amplifier according to claim 5, wherein the second output load further includes an inductor element connected in parallel between a source and a drain of the second load transistor.
  8. 　前記第１及び第２の出力負荷の各々は抵抗素子である、請求項３記載の差動増幅器。 The differential amplifier according to claim 3, wherein each of the first and second output loads is a resistance element.
  9. 　前記第１及び第２の出力負荷の各々はインダクタ素子である、請求項３記載の差動増幅器。 The differential amplifier according to claim 3, wherein each of the first and second output loads is an inductor element.
  10. 　前記第１及び第２の出力負荷の各々は、抵抗素子とインダクタ素子の並列接続回路である、請求項３記載の差動増幅器。 The differential amplifier according to claim 3, wherein each of the first and second output loads is a parallel connection circuit of a resistance element and an inductor element.
  11. 　前記第１及び第２の出力負荷の各々は、抵抗素子とインダクタ素子の直列接続回路である、請求項３記載の差動増幅器。 The differential amplifier according to claim 3, wherein each of the first and second output loads is a series connection circuit of a resistance element and an inductor element.
  12. 　前記第１及び第２の出力負荷の各々は、抵抗素子とインダクタ素子の直列接続回路とそれに並列接続された容量素子からなる回路である、請求項３記載の差動増幅器。 4. The differential amplifier according to claim 3, wherein each of the first and second output loads is a circuit including a series connection circuit of a resistance element and an inductor element and a capacitance element connected in parallel thereto.
  13. 　前記第１のハイパスフィルタは、
    　一方の端子が前記第２の出力端子に接続され、他方の端子が第１の制御端子に接続される第１の容量素子と、
    　前記第１の容量素子の前記他方の端子と前記第１の制御端子に供給されるバイアス電圧の供給端子との間に接続される抵抗素子を含み、
    　前記第２のハイパスフィルタは、
    　一方の端子が前記第１の出力端子に接続され、他方の端子が第２の制御端子に接続される第２の容量素子と、
    　前記第２の容量素子の前記他方の端子と前記第２の制御端子に供給されるバイアス電圧の供給端子との間に接続される抵抗素子を含む、請求項１乃至１２のいずれか１項に記載の差動増幅器。     The first high-pass filter is
    A first capacitive element having one terminal connected to the second output terminal and the other terminal connected to the first control terminal;
    A resistance element connected between the other terminal of the first capacitive element and a supply terminal of a bias voltage supplied to the first control terminal;
    The second high pass filter is:
    A second capacitive element having one terminal connected to the first output terminal and the other terminal connected to a second control terminal;
    The resistor element connected between the other terminal of the second capacitor element and a supply terminal of a bias voltage supplied to the second control terminal, according to any one of claims 1 to 12. The differential amplifier described.
  14. 　前記第１のハイパスフィルタは、
    　一方の端子が前記第２の出力端子に接続され、他方の端子が第１の制御端子に接続される第１の容量素子と、
    　前記第１の容量素子の前記他方の端子と前記第１の制御端子に供給されるバイアス電圧の供給端子との間に接続されるインダクタ素子を含み、
    　前記第２のハイパスフィルタは、
    　一方の端子が前記第１の出力端子に接続され、他方の端子が第２の制御端子に接続される第２の容量素子と、
    　前記第２の容量素子の前記他方の端子と前記第２の制御端子に供給されるバイアス電圧の供給端子との間に接続されるインダクタ素子を含む、請求項１乃至１２のいずれか１項に記載の差動増幅器。     The first high-pass filter is
    A first capacitive element having one terminal connected to the second output terminal and the other terminal connected to the first control terminal;
    An inductor element connected between the other terminal of the first capacitive element and a supply terminal of a bias voltage supplied to the first control terminal;
    The second high pass filter is:
    A second capacitive element having one terminal connected to the first output terminal and the other terminal connected to a second control terminal;
    13. The inductor element according to claim 1, further comprising an inductor element connected between the other terminal of the second capacitor element and a supply terminal of a bias voltage supplied to the second control terminal. The differential amplifier described.
  15. 　前記第１のハイパスフィルタは、
    　一方の端子が前記第２の出力端子に接続され、他方の端子が第１の制御端子に接続される第１の容量素子と、
    　前記第１の容量素子の前記他方の端子と前記第１の制御端子に供給されるバイアス電圧の供給端子との間に直列に接続された抵抗素子及びインダクタ素子を含み、
    　前記第２のハイパスフィルタは、
    　一方の端子が前記第１の出力端子に接続され、他方の端子が第２の制御端子に接続される第２の容量素子と、
    　前記第２の容量素子の前記他方の端子と前記第２の制御端子に供給されるバイアス電圧の供給端子との間に直列に接続された抵抗素子及びインダクタ素子を含む、請求項１乃至１２のいずれか１項に記載の差動増幅器。     The first high-pass filter is
    A first capacitive element having one terminal connected to the second output terminal and the other terminal connected to the first control terminal;
    A resistor element and an inductor element connected in series between the other terminal of the first capacitive element and a supply terminal of a bias voltage supplied to the first control terminal;
    The second high pass filter is:
    A second capacitive element having one terminal connected to the first output terminal and the other terminal connected to a second control terminal;
    13. The device according to claim 1, further comprising a resistor element and an inductor element connected in series between the other terminal of the second capacitor element and a supply terminal of a bias voltage supplied to the second control terminal. The differential amplifier according to any one of the above.
  16. 　差動入力信号のうち一方が供給されるゲートを有する第１の駆動トランジスタを配置し、
    　前記差動入力信号のうち他方が供給されるゲートを有し、前記第１の駆動トランジスタと共に差動対を構成する第２の駆動トランジスタを配置し、
    　前記第１の駆動トランジスタを流れるドレイン電流を調整するための第１の制御端子を有する第１の回路を、前記第１の駆動トランジスタのソース・ドレイン経路及び前記第１の出力端子が接続された配線上に配置し、
    　前記第２の駆動トランジスタを流れるドレイン電流を調整するための第２の制御端子を有する第２の回路を、前記第２の駆動トランジスタのソース・ドレイン経路及び前記第２の出力端子が接続された配線上に配置し、
    　前記差動対によって増幅された後の差動出力信号のうち一方を入力して高周波成分を選択的に透過させるとともに、透過後の信号を前記第１の制御端子の制御電位としてフィードバックする第１のハイパスフィルタを、前記差動出力信号が出力される第１及び第２の出力端子のうち前記第２の出力端子と前記第１の制御端子の間に接続し、
    　前記差動出力信号のうち他方を入力して高周波成分を選択的に透過させるとともに、透過後の信号を前記第２の制御端子の制御電位としてフィードバックする第２のハイパスフィルタを、前記第１の出力端子と前記第２の制御端子の間に接続する、
    差動増幅器の構成方法。     A first driving transistor having a gate to which one of the differential input signals is supplied;
    A second driving transistor having a gate to which the other one of the differential input signals is supplied and constituting a differential pair together with the first driving transistor;
    A first circuit having a first control terminal for adjusting a drain current flowing through the first driving transistor is connected to a source / drain path of the first driving transistor and the first output terminal. Place on the wiring,
    A second circuit having a second control terminal for adjusting a drain current flowing through the second drive transistor is connected to a source / drain path of the second drive transistor and the second output terminal. Place on the wiring,
    A first one of the differential output signals amplified by the differential pair is input to selectively transmit a high-frequency component, and the transmitted signal is fed back as a control potential of the first control terminal. The high pass filter is connected between the second output terminal and the first control terminal among the first and second output terminals from which the differential output signal is output,
    A second high-pass filter that inputs the other of the differential output signals and selectively transmits a high-frequency component, and feeds back the signal after transmission as a control potential of the second control terminal; Connecting between an output terminal and the second control terminal;
    Configuration method of differential amplifier.
  17. 　前記第１の回路は、前記第１の駆動トランジスタのドレイン及び電源電位の間に接続される一対の端子と、前記第１の制御端子とを有する三端子の第１の出力負荷を含み、
    　前記第２の回路は、前記第２の駆動トランジスタのドレイン及び前記電源電位の間に接続される一対の端子と、前記第２の制御端子とを有する三端子の第２の出力負荷を含む、請求項１６記載の差動増幅器の構成方法。     The first circuit includes a three-terminal first output load having a pair of terminals connected between a drain of the first driving transistor and a power supply potential, and the first control terminal,
    The second circuit includes a three-terminal second output load having a pair of terminals connected between the drain of the second driving transistor and the power supply potential, and the second control terminal. The method of configuring a differential amplifier according to claim 16.
  18. 　前記第１の回路は、
    　ドレインが前記第１の制御端子であり、ソースが前記第１の駆動トランジスタのドレインに接続され、ドレインが前記第１の出力端子に接続される第１のカスコードトランジスタと、
    　一方の端子が前記第１のカスコードトランジスタのドレインに接続され、他方の端子が電源電位に接続される二端子の出力負荷とを備え、
    　前記第２の回路は、
    　ドレインが前記第２の制御端子であり、ソースが前記第２の駆動トランジスタのドレインに接続され、ドレインが前記第２の出力端子に接続される第２のカスコードトランジスタと、
    　一方の端子が前記第２のカスコードトランジスタのドレインに接続され、他方の端子が前記電源電位に接続される二端子の出力負荷とを備える、請求項１６記載の差動増幅器の構成方法。     The first circuit includes:
    A first cascode transistor having a drain connected to the first control terminal, a source connected to the drain of the first drive transistor, and a drain connected to the first output terminal;
    A two-terminal output load having one terminal connected to the drain of the first cascode transistor and the other terminal connected to a power supply potential;
    The second circuit includes:
    A second cascode transistor having a drain connected to the second control terminal, a source connected to the drain of the second drive transistor, and a drain connected to the second output terminal;
    17. The method of configuring a differential amplifier according to claim 16, further comprising: a two-terminal output load having one terminal connected to the drain of the second cascode transistor and the other terminal connected to the power supply potential.
PCT/JP2009/002795 2008-09-02 2009-06-19 Differential amplifier, and method for constituting the same WO2010026681A1 (en)

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CN109716647A (en) * 2016-08-22 2019-05-03 帝瓦雷公司 Amplifying device including compensation circuit
EP3170257B1 (en) * 2014-07-18 2019-12-04 Qualcomm Incorporated Wideband low-power amplifier
JPWO2020031016A1 (en) * 2018-08-10 2021-08-26 株式会社半導体エネルギー研究所 Amplifier circuit, latch circuit, and detector
CN113489462A (en) * 2021-07-29 2021-10-08 北京京东方传感技术有限公司 Voltage amplification circuit, sensor and electronic equipment

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JPH07321572A (en) * 1994-05-24 1995-12-08 Nec Ic Microcomput Syst Ltd Differential amplifier circuit
JP2006254419A (en) * 2005-02-08 2006-09-21 Sony Corp Differential amplifier, two-step amplifier, and analog/digital convertor

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JP2006254419A (en) * 2005-02-08 2006-09-21 Sony Corp Differential amplifier, two-step amplifier, and analog/digital convertor

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EP3170257B1 (en) * 2014-07-18 2019-12-04 Qualcomm Incorporated Wideband low-power amplifier
CN109716647A (en) * 2016-08-22 2019-05-03 帝瓦雷公司 Amplifying device including compensation circuit
CN109716647B (en) * 2016-08-22 2023-07-07 帝瓦雷公司 Amplifying device comprising compensation circuit
JPWO2020031016A1 (en) * 2018-08-10 2021-08-26 株式会社半導体エネルギー研究所 Amplifier circuit, latch circuit, and detector
JP7273043B2 (en) 2018-08-10 2023-05-12 株式会社半導体エネルギー研究所 amplifier circuit
CN113489462A (en) * 2021-07-29 2021-10-08 北京京东方传感技术有限公司 Voltage amplification circuit, sensor and electronic equipment

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