WO2010026624A1 - Method for fabricating nonvolatile semiconductor memory device - Google Patents

Method for fabricating nonvolatile semiconductor memory device Download PDF

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Publication number
WO2010026624A1
WO2010026624A1 PCT/JP2008/065774 JP2008065774W WO2010026624A1 WO 2010026624 A1 WO2010026624 A1 WO 2010026624A1 JP 2008065774 W JP2008065774 W JP 2008065774W WO 2010026624 A1 WO2010026624 A1 WO 2010026624A1
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Prior art keywords
layer
insulating film
memory device
semiconductor memory
nonvolatile semiconductor
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PCT/JP2008/065774
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French (fr)
Japanese (ja)
Inventor
浩一 村岡
宏行 永嶋
淳二 古賀
裕文 井上
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株式会社 東芝
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Priority to PCT/JP2008/065774 priority Critical patent/WO2010026624A1/en
Publication of WO2010026624A1 publication Critical patent/WO2010026624A1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0007—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising metal oxide memory material, e.g. perovskites
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/30—Resistive cell, memory material aspects
    • G11C2213/32—Material having simple binary metal oxide structure
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/30—Resistive cell, memory material aspects
    • G11C2213/34—Material includes an oxide or a nitride
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/71—Three dimensional array
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/72—Array wherein the access device being a diode

Definitions

  • the present invention relates to a method for manufacturing a nonvolatile semiconductor memory device configured by laminating a variable resistance element and a non-ohmic element at a cross point of a wiring layer.
  • phase change memory Phase-change Random Access Memory: PCRAM
  • resistance change memory Resistive-change Random Access Memory: ReRAM
  • a characteristic of the cross-point structure is a recording method that reads resistance change by flowing current, and a cell in which a non-ohmic element is connected in series to a variable resistance element in order to suppress stray current flowing through the non-selected cell when reading a selected cell It has a structure. This makes it possible to suppress reverse current (prevent current backflow) in the case of unipolar operation and to suppress low electric field leakage current (prevent leakage current) in the case of bipolar operation.
  • this type of solid-state memory has the following problems. That is, as cell miniaturization proceeds, the peripheral leak of the non-ohmic element caused by damage during processing increases, and particularly when a diode is used as the non-ohmic element, the peripheral leak becomes a level that cannot be ignored. For this reason, the current suppression effect described above is reduced, and problems such as deterioration of read characteristics / switching characteristics, variation in cell resistance change, increase in operating current, and increase in power consumption occur.
  • the present invention has been made in view of the above circumstances, and the object of the present invention is to suppress leakage due to damage during processing of a non-ohmic element, variation in cell resistance variation, and switching characteristics.
  • An object of the present invention is to provide a method for manufacturing a nonvolatile semiconductor memory device that can contribute to improvement.
  • a method for manufacturing a semiconductor memory device including a step of forming a first metal layer serving as a first wiring layer over a first insulating film, A step of laminating a variable resistance element layer and a non-ohmic element layer to be a memory cell, and a first deposited layer comprising the first metal layer, the variable resistance element layer, and the non-ohmic element layer are selectively etched.
  • a first line and space pattern forming step and a first side surface of the non-ohmic element layer that is exposed in a space portion by the first line and space pattern formation are selectively oxidized.
  • An oxidation step a step of embedding and forming a second insulating film in a space portion of the pattern of the first line and space after the first oxidation step, the first deposited layer, and the second Forming a second metal layer serving as a second wiring layer on the insulating film; and a second layer comprising the variable resistance element layer, the non-ohmic element layer, the second insulating film, and the second metal layer.
  • FIG. 1 is a block diagram showing a circuit configuration of a memory core unit of ReRAM.
  • FIG. 2 is a perspective view showing the structure of the cross point portion of the ReRAM.
  • FIG. 3 is a sectional view schematically showing the memory plug structure of the ReRAM.
  • FIG. 4 is a cross-sectional view schematically showing the structure of a non-ohmic element used in ReRAM.
  • FIG. 5 is a cross-sectional view showing the memory element structure of the ReRAM.
  • FIG. 6 is a diagram showing a process flow of ReRAM.
  • FIG. 7 is a cross-sectional view showing the manufacturing process of the ReRAM.
  • FIG. 8 is a perspective view showing the manufacturing process of the ReRAM.
  • FIG. 9 is a diagram for explaining the first embodiment of the present invention, and shows a process flow of ReRAM to which selective oxidation is added.
  • FIG. 10 is a cross-sectional view showing the manufacturing process in the first embodiment.
  • FIG. 11 is a characteristic diagram for explaining selective oxidation conditions using hydrogen / water vapor.
  • ReRAM ReRAM
  • the present invention can also be applied to other nonvolatile semiconductor memories, in particular, resistance change type memories.
  • the configuration method of the memory array may not be particularly described here.
  • a 1T / 1R type array or a 1D / 1R type memory array may be used.
  • FIG. 1 shows a basic configuration of a nonvolatile semiconductor memory according to a reference example of the present invention.
  • the memory cell array 1 is configured by providing ReRAM memory cells at cross points of wiring.
  • a plurality of memory cell layers are formed by stacking memory cells in multiple stages.
  • the cross-point type memory cell array 1 can be formed in a wiring layer, this structure is not necessarily required.
  • the WL and BL wirings as shown in FIG. 2 need not all be connected by a vertical memory cell array, and can also be applied to a separate structure without the 165 and 155 memory cell arrays.
  • a structure in which a memory cell is inserted into a contact region with a lower device may be used.
  • a column control circuit 2 is provided for controlling the bit line BL of the memory cell array 1 and erasing data in the memory cell, writing data to the memory cell, and further reading data from the memory cell.
  • the column control circuit 2 may be provided for each MAT (Memory Allocation Table), for each sector, or for each memory cell layer, or may be shared (shared). Furthermore, a plurality of BLs may be shared in order to reduce the area.
  • a row control circuit 3 is provided to select a word line WL of the memory cell array 1 and apply a voltage necessary for erasing, writing, and reading.
  • the row control circuit 3 may be provided for each memory cell layer or may be common for reducing the area.
  • the memory cell array 1 can be divided into MATs of a certain memory cell group. At this time, the control circuit may be provided by each MAT or may be shared by a plurality of MATs. Further, the memory cell array 1 may have a global BL and a global WL, or may have a sector that is partitioned by selection transistors.
  • a data input / output buffer 6 is provided which is connected to an external host 9 via an I / O line and receives write data, receives an erase command, outputs read data, and receives address data and command data. Yes.
  • the buffer 6 sends the received write data to the column control circuit 2 and receives data read from the column control circuit 2. It is also possible to latch the read data in the column control circuit 2 and output the data to the outside through the input / output buffer 6 from the I / O line.
  • a command interface 7 that receives command data from the host 9 and a state machine 8 for selecting a memory cell are provided.
  • the command interface 7 receives a control signal from the host 9 and determines whether the data input to the data input / output buffer 6 is write data, command data, or address data. 8 is transferred.
  • the state machine 8 sends external address data to the column control circuit 2 and the row control circuit 3 to manage the entire ReRAM memory, receives commands from the host 9, reads, writes, erases, and data I / O management etc.
  • the host 9 can also receive status information managed by the state machine 8 and determine the operation result. Furthermore, the status information is also used for writing and erasing control.
  • peripheral circuit elements such as the column control circuit 2, the row control circuit 3, the data input / output buffer 6, the command interface 7, and the state machine 8 are directly under the memory array formed in the wiring layer. It can be formed on a Si substrate. Thus, the chip area of the nonvolatile semiconductor memory device can be made substantially equal to the area of the memory cell array.
  • the pulse generator 10 is controlled by the state machine 8. By this control, the pulse generator 10 can output a pulse having an arbitrary voltage and arbitrary timing. Here, the formed pulse can be transferred to any wiring selected by the row control circuit 3.
  • FIG. 2 is a perspective view showing the configuration of the memory cell array 1.
  • 175, 180, and 185 are word lines (WL) as a first wiring layer
  • 190 and 195 are bit lines (BL) as a second wiring layer
  • 155, 160, 165, and 170 are memory cell portions. Is shown.
  • the memory cell array 1 is a cross-point type. In this case, it is a four-layer stack memory cell array.
  • the cross-point structure refers to a structure in which a cell is sandwiched at an intersection between a first wiring arranged in parallel and a second wiring that intersects the first wiring. In this example, this structure is deposited in a plurality of layers.
  • the wiring / cell / wiring / cell / wiring is repeated, but a structure such as wiring / cell / wiring / interlayer insulating film / wiring / cell / wiring may be used.
  • the former structure has fewer layers and can provide cost advantages, but the number of cells shared by a single wiring increases, which may lead to deterioration of reliability, such as deterioration of performance and disturbance of unselected cells.
  • the latter requires more wiring layers and is costly.
  • the cells hanging on one wiring are half of the former, it is suitable for high-speed operation and is superior to the former in terms of reliability.
  • FIG. 3 shows a specific memory element structure.
  • Reference numeral 210 in the figure denotes a first wiring layer, which is preferably made of a material resistant to heat and having a low resistance, and is formed of, for example, W / WSi / NiSi / CoSi.
  • Reference numeral 225 denotes a variable resistance element whose resistance can be changed by voltage, current, heat, chemical energy, or the like, and this variable resistance element 225 stores states having different resistance values as information.
  • 220 is a lower electrode of the variable resistance element 225
  • 230 is an upper electrode of the variable resistance element 225.
  • Each of the electrodes 220 and 230 can simultaneously serve as a barrier metal or an adhesive layer.
  • 235 is a non-ohmic element, and various diodes such as a pn junction diode, a pin diode, and a Schottky diode, a MIM (Metal-Insulator-Metal) structure, a SIS structure (Silicon-Insulator-Silicon), and the like can be used.
  • FIG. 4A shows an example of the MIM structure
  • FIG. 4B shows an example of the pin structure.
  • a barrier metal layer or an adhesive layer may be inserted.
  • a diode when a diode is used, a unipolar operation can be performed due to its characteristics, and when a MIM structure or the like is used, a bipolar operation can be performed.
  • 215 is a second wiring layer that intersects the first wiring layer 210 and is formed of W / WSi / NiSi / CoSi or the like. Further, 240 becomes a barrier metal layer or an adhesive layer between the non-ohmic element 235 and the second wiring layer 215, and is formed of Ti / TiN or the like.
  • a diode is used for the non-ohmic element 215 this time and has a mirror structure with BL at the center, but the arrangement of the non-ohmic element 215 is not particularly concerned with this. In that case, it is possible to cope with this by changing the bias relationship between WL and BL. In this example, both unipolar operation and bipolar operation can be performed.
  • FIG. 5 is a cross-sectional view showing the ReRAM memory element structure.
  • a control circuit section such as a peripheral circuit is provided in an active area on the surface of the substrate.
  • a first interlayer insulating film 410 is deposited on the substrate 400, and a via 415 for making contact with a lower device is provided in the interlayer insulating film 410.
  • a first wiring layer 420 of a cross-point array is formed of W (can be applied to other low-resistance metals), and a barrier metal layer 430 is formed of Ti / TiN on the upper layer. Yes.
  • a barrier metal may also be formed below the first wiring layer 420. Further, the barrier metal layer 430 here may use both Ti and TiN, or may be either. Further, a barrier metal may be inserted into the upper layer and the subsequent layers.
  • a diode 440 serving as a non-ohmic element is formed on the barrier metal layer 430.
  • various diodes such as a pn junction diode, a pin diode, and a Schottky diode can be manufactured, and the material may be poly-Si or other materials can be applied.
  • an MIM structure, an SIS structure, or the like can be used instead of the diode 440.
  • a lower electrode 450 serving as an electrode of a variable resistance element, a variable resistance element material layer 460, and an upper electrode 470 are formed on the diode 440.
  • the electrodes 450 and 470 are, for example, TiN or TaN.
  • a barrier metal may be inserted outside the upper and lower electrodes, or a barrier metal and an adhesive layer may be inserted inside.
  • the space between the memory cells is filled with second and third interlayer insulating films 480 and 485.
  • the second interlayer insulating film 480 is not visible in this cross-sectional view.
  • a second wiring layer 490 of the cross point memory array is formed on the upper electrode 470.
  • fourth and fifth interlayer insulating films 510 and 515 are formed on the substrate formed up to the second wiring layer 490, and metal wiring layers 520 and 525 are formed on the interlayer insulating films 510 and 515.
  • FIG. 6 is a diagram showing a process flow of the ReRAM in FIG.
  • the Si substrate 400 is prepared (Step S1)
  • the FEOL process is performed on the Si substrate 400 (Step S2)
  • the first interlayer insulating film 410 is deposited thereon (Step S3).
  • the via 415 is also prepared here.
  • the first metal layer to be the first wiring layer 420 of the cross point array is deposited by W (applicable to other low-resistance metal) (step S4), and the barrier metal layer 430 is formed thereon. It forms by Ti / TiN (step S5).
  • a barrier metal layer may be formed below the metal layer that becomes the first wiring layer 420.
  • the barrier metal here may be either Ti or TiN, or may be either.
  • a layer to be a non-ohmic element 440 is deposited above the layer (step S6).
  • the non-ohmic element 440 a diode, an MIM structure, or the like is formed.
  • the material may be poly-Si, or other materials can be applied.
  • MIM (SIS) structure a metal having a high work function or poly-Si may be used.
  • the insulating film portion may be a single layer, or band engineering may be performed with two or more layers.
  • a variable resistance element layer serving as a memory element layer is deposited (step S7).
  • a lower electrode 450, a variable resistance element material layer 460, and an upper electrode 470 are formed.
  • a barrier metal layer may be inserted outside the upper and lower electrodes, or a barrier metal layer and an adhesive layer may be inserted inside thereof.
  • a layer serving as a hard mask for etching or CMP may be deposited on this upper layer.
  • FIG. 7A shows a cross-sectional view of the first deposited layer deposited from 420 to 470 with a solid film.
  • the variable resistance element material layer 460 includes a phase change material such as Ge 2 Sb 2 Te 5 and other chalcogenide materials, an Ag-rich Ag—Ge—Se chalcogenide material, an ion conductive material such as Cu 2 S, and the like.
  • Phase change material such as Ge 2 Sb 2 Te 5 and other chalcogenide materials, an Ag-rich Ag—Ge—Se chalcogenide material, an ion conductive material such as Cu 2 S, and the like.
  • Rotaxane supramolecules, other molecular materials, materials having a structure in which a metal layer is sandwiched between insulating films, and materials having a CMR (Colossal Magneto Resistive) substance such as PrCaMnO 3 can be used.
  • spin injection MTJ using electron spin Ag 2 S, ZnxCdS, Ag—Ge—Se system, PrCaMnO 3, and the like, which are known as resistance-changeable memory elements, exhibit a giant magnetoresistance effect, such as NiOx and TiOx. , HfO 2 , ZrO 2 , SrZrO 3 , SrTiO 3, etc. can also be used.
  • a first etching process is performed (step S8).
  • the first deposited layer is first processed to L / S at the minimum pitch.
  • the present embodiment is characterized in that after this processing, the side surface of the non-ohmic element layer exposed to the space portion by processing is selectively oxidized. This oxidation makes it possible to reduce the leakage current on the side of the non-ohmic device, improve read / switching characteristics, improve variation in cell resistance, etc., and reduce operating current and reduce power consumption.
  • a nonvolatile resistance change memory can be realized.
  • the second interlayer insulating film 480 is embedded (step S9), and the L / S space portion processed in S8 is embedded.
  • the material of the interlayer insulating film 480 is preferably a material having good insulating properties, low capacitance, and good embedding characteristics.
  • the second interlayer insulating film 480 is planarized (step S10), and the excess insulating film is removed by CMP and the electrode portion is exposed. A cross-sectional view at this time is shown in FIG. At this time, if a hard mask is used, etching or the like is required.
  • step S11 tungsten is laminated on the planarized portion after CMP by depositing a metal layer to be the second wiring layer 490 (step S11).
  • An image diagram at this time is shown in the perspective view of FIG.
  • step S12 the second etching process is performed on the second deposition layers from 430 to 480 with L / S in a direction intersecting with the first etching process.
  • a second wiring layer 490 composed of a plurality of wirings arranged in parallel to each other in a direction orthogonal to the first wiring layer 420 is formed.
  • This embodiment is characterized in that after this processing, the side surface of the non-ohmic element layer exposed to the space portion by processing is selectively oxidized. This oxidation makes it possible to reduce the leakage current on the side of the non-ohmic device, improve read / switching characteristics, improve variation in cell resistance, etc., and reduce operating current and reduce power consumption.
  • a nonvolatile resistance change memory can be realized.
  • step S13 the third interlayer insulating film 485 is embedded again (step S13) and the third interlayer insulating film 485 is flattened (step S14), whereby a cross-point type as shown in FIG. A memory array layer can be formed.
  • step S15 by repeating the formation of this stacked structure (step S15), it is possible to form a stacked type cross-point type memory cell array.
  • step S15 by repeating the deposition from the deposition of the barrier metal layer, a memory cell array that shares the wirings of adjacent memory cell arrays in the upper layer and the lower layer can be realized.
  • step S15 by repeating the formation of the first interlayer insulating film 410, it is possible to realize a memory cell array that does not share the wirings of adjacent memory cell arrays in the upper layer and the lower layer.
  • step S16 a metal wiring layer is formed (step S16), and the nonvolatile semiconductor memory device of this reference example is completed.
  • the selective oxidation of the side surface of the non-ohmic element layer is specifically considered.
  • metal wiring is oxidized and wiring resistance increases. Therefore, in this embodiment, selective oxidation is performed in which only the processing damage on the side surface of the non-ohmic element layer is oxidized and repaired without oxidizing the metal wiring.
  • the leakage current through the side surface can be reduced, so that stable operations such as writing, erasing operation and holding characteristics can be performed.
  • the process flow at this time is shown in FIG. The same applies to FIG. 9 up to the etching process (S8) in FIG.
  • the first selective oxidation process (S21) is performed after S8.
  • the subsequent S9 to S12 are the same as in FIG. 6, and the second selective oxidation process (S22) is performed after S12.
  • Subsequent S13 to S16 are the same as those in FIG. 6 differs from the process of FIG. 6 in that the first selective oxidation process (S21) is performed after the first etching process of S8, and further the second selective oxidation process is performed after the second etching process of S12. (S22) is performed.
  • FIG. 10A shows a cross section of the etched state of S8.
  • FIG. 10B shows a cross section of the state of selective oxidation of S21.
  • the side surfaces of the barrier metal layer 430 and the electrodes 450 and 470 are oxidized to form a sidewall oxide film 500.
  • the metal layer as the first wiring layer 420 is not oxidized.
  • the electrodes 450 and 470 are oxidized because TiN, TaN, or the like is used as the electrode material. It is also possible to use a material that is not oxidized by the selective oxidation treatment of S21 as the electrodes 450 and 470.
  • the side surface of the variable resistance element material layer 460 is not oxidized, but there is no problem if the layer 460 is oxidized.
  • FIG. 11 shows redox boundaries in W, Zr, Hf, Si and Ge, and it can be seen that the boundaries differ greatly depending on the material. Vertical arrows in the figure indicate selective oxidation regions, and there are regions where Si, Zr and Hf are oxidized but W and Ge are not oxidized in a wide temperature range. That is, under this selective oxidation condition, for example, a pn, pin diode or the like using Si is oxidized to form a side oxide film, but the W wiring is not oxidized (FIG. 10B).
  • the selective oxidation condition is 700 ° C. or lower, more preferably 500 ° C. or lower for suppressing GeO desorption.
  • the second problem is controllability of the partial pressure ratio, and it is difficult to control in-wafer plane with a partial pressure ratio exceeding 6 digits in a mass production apparatus. Accordingly, the dynamic range of P (H 2 ) / P (H 2 O) is preferably 6 digits or less.
  • Si, Zr, and Hf are ⁇ GI, W, and Ge are ⁇ GM, and water is ⁇ GH 2 O.
  • the selective oxidation condition is determined by the relationship between ⁇ GI and ⁇ GM from the equation (2), and the point is that the side surface is exposed to an atmosphere containing both hydrogen and water vapor in a temperature range where ⁇ GM has a value equal to or greater than ⁇ GI. That is, the side surface of the non-ohmic element can be oxidized without oxidizing the metal electrode if there is a combination of materials that can satisfy the condition of the formula (2) without being limited to the above materials.
  • H 2 is deuterium (D 2)
  • D 2 O deuterium
  • D 2 O is ⁇ G
  • D 2 O heavy water
  • the same selective oxidation effect can be obtained in the heat treatment in an H 2 / D 2 O, D 2 / H 2 O or D 2 / D 2 O atmosphere.
  • D atoms taken into the surrounding material are slower than the H atoms because the diffusion rate in the film is slow due to the difference in mass number unlike the H atoms.
  • Rarely form defects that is, the electrical reliability of the cell structure containing D atoms is increased.
  • the W film is mainly described as the wiring material, and Si is described as the non-ohmic element material.
  • the present invention can be applied to materials satisfying the expression (2), and particularly Si, Ti as the non-ohmic element material. , Al, La, Pr, Y, Ce, Sr, Dy, Er, Lu, or Gd. Furthermore, the effectiveness of the silicate film, aluminate film, oxynitride film, nitride film, mixed film, and various multilayer films is maintained.
  • the wiring material a material containing Ge, Ga, Au, Cu, Ta, Mo, Ir, Ru, or Ni is also applicable. In addition, the same effect can be obtained even with a film formed by sputtering, ALCVD (Atomic Layer CVD), vapor deposition, plasma CVD, or the like, regardless of the film forming method of these materials.
  • the selective oxidation process is applied to the manufacturing method of the nonvolatile semiconductor memory cell array using the variable resistance element after the wiring, the electrode, the non-ohmic element, and the variable resistance element are collectively etched. This makes it possible to reduce the leakage current on the side surface of the non-ohmic element, improve read / switching characteristics, improve variation in cell resistance change, etc., and can operate with low operating current and low power consumption. Resistance change memory can be realized.
  • the non-ohmic element is not limited to pn, pin, and Schottky diode, and the damage of the side wall portion caused during processing can be repaired by selective oxidation in a laminated insulating film or an oxide semiconductor to prevent leakage. It is effective in preventing the deterioration of the variable resistance element characteristics.
  • the selective oxidation of the side surface of the non-ohmic element is considered as in the first embodiment.
  • the cross-point memory creation process selective oxidation that oxidizes and repairs only the processing damage on the side surface of the non-ohmic element without oxidizing the metal wiring is essential. Therefore, by heating in an atmosphere in which D 2 O is discharged, the Si surface is selectively reduced without oxidizing the W surface, and the cell structure shown in FIG. 10B is completed. The discharge conditions at this time are described below.
  • the D 2 O discharge conditions are preferably a water pressure of 1 to 200 mTorr and an applied power of 10 to 500 W, and the substrate temperature is effective in the range of room temperature to 700 degrees. More preferably, the water pressure is 10 to 100 mTorr, 10 to 50 mTorr, and further 20 to 30 mTorr. In addition, a better result is obtained when the applied power is 100 W or more and the substrate temperature is in the range of room temperature to 500 degrees.
  • the radical atmosphere can obtain the same effect even when the mixed gas such as D 2 and O 2 , D 2 and D 2 O, D 2 and NO, D 2 and N 2 O is discharged or independently. be able to. Further, unlike the first embodiment, the use of radicals enables a low-temperature process, and contamination such as W and Ge can be completely ignored.
  • the selective oxidation condition by the D 2 O discharge can obtain the same effect also in the H 2 O discharge.
  • the D atom taken into the peripheral material has a low diffusion rate in the film due to the difference in mass number, so that new defects are less formed than the H atom. That is, the electrical reliability of the cell structure containing D atoms is increased.
  • the selective oxidation of the side surface of the non-ohmic element is considered as in the first embodiment.
  • selective oxidation that oxidizes and repairs only the processing damage on the side surface of the non-ohmic element is indispensable without oxidizing the metal wiring. Therefore, by heating in an atmosphere in which a mixed gas of hydrogen / oxygen is discharged, the Si layer is oxidized without oxidizing the W layer, and the cell structure shown in FIG. 10B is completed. The discharge conditions at this time are described below.
  • the H 2 / O 2 discharge conditions are preferably a H 2 / O 2 partial pressure ratio of 1 to 10000, a total pressure of 1 to 200 mTorr, and an applied power of 10 to 500 W, and the substrate temperature is effective in the range of room temperature to 700 degrees. is there. More preferably, the H 2 / O 2 partial pressure ratio is 1 to 1000, 1 to 100, the total pressure is 10 to 100 mTorr, 10 to 50 mTorr, and further 20 to 30 mTorr. In addition, a better result is obtained when the applied power is 100 W or more and the substrate temperature is in the range of room temperature to 500 degrees.
  • the microwave discharge method there are a parallel plate type using RF, a magnetron type using a magnet or an electromagnet, or a helicon wave.
  • the radical atmosphere can obtain the same effect even if discharge of a mixed gas such as H 2 O, H 2 and H 2 O, H 2 and NO, H 2 and N 2 O, or discharge each independently. it can. Further, unlike the first embodiment, the use of radicals enables a low-temperature process, and contamination such as W and Ge can be completely ignored.
  • the vacancy in the variable resistance element can be terminated with O atoms, and stable operation can be achieved.
  • there is a defect termination effect such as interface states due to H atoms, leading to high reliability of diode characteristics.
  • the oxidation-reduction effect by these radicals can improve the bulk and interface characteristics of the cell constituent material by diffusing H and O atoms into the cell from the side.
  • the cell width is 20 nm or less, the cell can be sufficiently diffused to the inside. Therefore, the presence of both H and O atoms in the cell constituent material is 1 ⁇ 10 18 cm ⁇ 3 or more. It is also possible to suppress defect generation.
  • H 2 / O 2 mixed gas discharge has been described, but the same or more effect can be obtained even if N 2 gas is added.
  • N 2 gas since excitation of N radicals is promoted by H 2 / O 2 / N 2 discharge, it is possible to form a conductive WN film without oxidizing the W wiring, and to effectively prevent the diffusion of impurities.
  • a metal nitride film electrode can be formed.
  • the selective oxidation condition by the H 2 / O 2 discharge can obtain the same effect in the D 2 / O 2 discharge. Furthermore, when D 2 is used, D atoms taken into the peripheral material have a lower diffusion rate in the film due to the difference in mass number, unlike H atoms, so that new defects are less formed than H atoms. . That is, the electrical reliability of the cell structure containing D atoms is increased.
  • this invention is not limited to each Example mentioned above.
  • the non-ohmic element and the variable resistance element are stacked in this order from the substrate side, but the stacking order may be reversed.
  • Si as a metal having an MIM structure as a non-ohmic element.
  • the side surface of the non-ohmic element layer can be selectively oxidized without oxidizing the metal layer as the wiring layer after the non-ohmic element layer is etched with a line-and-space pattern.

Abstract

In the method for fabricating a nonvolatile semiconductor memory device where a nonohmic element layer and a variable resistance element layer are formed in lamination at a cross point of a first metal layer becoming a first wiring layer and a second metal layer becoming a second wiring layer, the first metal layer, the nonohmic element layer, and the variable resistance element layer are processed into a pattern of first line and space and then the side face of the nonohmic element layer exposed to the space portion is oxidized selectively thus enhancing the switching characteristics by reducing leak current and improving variation in resistance change of cell.

Description

不揮発性半導体記憶装置の製造方法Method for manufacturing nonvolatile semiconductor memory device
　本発明は、配線層のクロスポイントに可変抵抗素子及び非オーミック素子を積層して構成される不揮発半導体記憶装置の製造方法に関する。 The present invention relates to a method for manufacturing a nonvolatile semiconductor memory device configured by laminating a variable resistance element and a non-ohmic element at a cross point of a wiring layer.
　近年、新規固体メモリとして、相変化メモリ（Phase-change Random Access Memory：ＰＣＲＡＭ）や抵抗変化メモリ（Resistive-change Random Access Memory：ＲｅＲＡＭ）と呼ばれる、記録材料の抵抗値（高抵抗と低抵抗）の変化を利用したメモリが実用化に向けて開発が進められている。これらのメモリのセルアレイは、可変抵抗素子を配線間に設置するクロスポイント構造をとることができ、更にセルアレイを積層化して３次元構造をとることが可能である。また、セルアレイ下に周辺回路を配置してチップ面積を小さくすることができるため、大容量化に適した構造となっている。 In recent years, as a new solid-state memory, the resistance value (high resistance and low resistance) of recording materials called phase change memory (Phase-change Random Access Memory: PCRAM) and resistance change memory (Resistive-change Random Access Memory: ReRAM) Development of memory using change is underway for practical application. The cell arrays of these memories can take a cross-point structure in which variable resistance elements are installed between wirings, and can further take a three-dimensional structure by stacking cell arrays. In addition, since a chip area can be reduced by arranging a peripheral circuit under the cell array, the structure is suitable for increasing the capacity.
　クロスポイント構造の特徴としては、電流を流して抵抗変化を読み取る記録方式であり、選択セル読み出し時に非選択セルを流れる迷走電流抑制のために、可変抵抗素子に非オーミック素子を直列に接続したセル構造となっている。これにより、ユニポーラ動作の場合は逆方向電流の抑制（電流の逆流防止）、バイポーラ動作の場合は低電界リーク電流の抑制（漏れ電流防止）が可能となる。 A characteristic of the cross-point structure is a recording method that reads resistance change by flowing current, and a cell in which a non-ohmic element is connected in series to a variable resistance element in order to suppress stray current flowing through the non-selected cell when reading a selected cell It has a structure. This makes it possible to suppress reverse current (prevent current backflow) in the case of unipolar operation and to suppress low electric field leakage current (prevent leakage current) in the case of bipolar operation.
　しかしながら、この種の固体メモリにあっては、次のような問題があった。即ち、セルの微細化が進むにあたり、加工時のダメージで生じる非オーミック素子の周辺リークが大きくなり、特に非オーミック素子としてダイオードを用いた場合は周辺リークが無視できないレベルとなる。このため、前記した電流抑制効果が小さくなり、読み出し特性・スイッチング特性劣化、セルの抵抗変化のばらつき、動作電流増大、消費電力増加等の問題が生じている。 However, this type of solid-state memory has the following problems. That is, as cell miniaturization proceeds, the peripheral leak of the non-ohmic element caused by damage during processing increases, and particularly when a diode is used as the non-ohmic element, the peripheral leak becomes a level that cannot be ignored. For this reason, the current suppression effect described above is reduced, and problems such as deterioration of read characteristics / switching characteristics, variation in cell resistance change, increase in operating current, and increase in power consumption occur.
　本発明は、上記実状に鑑みてなされたもので、その目的とするところは、非オーミック素子の加工時のダメージに起因するリークを抑制することができ、セルの抵抗変化のばらつきやスイッチング特性の改善に寄与し得る不揮発性半導体記憶装置の製造方法を提供することにある。 The present invention has been made in view of the above circumstances, and the object of the present invention is to suppress leakage due to damage during processing of a non-ohmic element, variation in cell resistance variation, and switching characteristics. An object of the present invention is to provide a method for manufacturing a nonvolatile semiconductor memory device that can contribute to improvement.
　本発明の一態様に係わる半導体記憶装置の製造方法は、第１の絶縁膜上に、第１の配線層となる第１のメタル層を形成する工程と、前記第１のメタル層上に、メモリセルとなる可変抵抗素子層と非オーミック素子層を積層形成する工程と、前記第１のメタル層，可変抵抗素子層，及び非オーミック素子層からなる第１の堆積層を選択的にエッチングすることにより、第１のラインアンドスペースのパターンを形成する工程と、前記第１のラインアンドスペースのパターンの形成でスペース部分に露出した前記非オーミック素子層の側面を選択的に酸化する第１の酸化工程と、前記第１の酸化工程の後に、前記第１のラインアンドスペースのパターンのスペース部分に第２の絶縁膜を埋め込み形成する工程と、前記第１の堆積層及び前記第２の絶縁膜上に、第２の配線層となる第２のメタル層を形成する工程と、前記可変抵抗素子層，非オーミック素子層，第２の絶縁膜，及び第２のメタル層からなる第２の堆積層を選択的にエッチングすることにより、前記第１のラインアンドスペースとは交差する方向の第２のラインアンドスペースのパターンを形成する工程と、前記第２のラインアンドスペースのパターンの形成でスペース部分に露出した前記非オーミック素子層の側面を選択的に酸化する第２の酸化工程と、前記第２の酸化工程の後に、前記第２のラインアンドスペースのパターンのスペース部分に第３の絶縁膜を埋め込み形成する工程と、を含むことを特徴とする。 According to one embodiment of the present invention, there is provided a method for manufacturing a semiconductor memory device, including a step of forming a first metal layer serving as a first wiring layer over a first insulating film, A step of laminating a variable resistance element layer and a non-ohmic element layer to be a memory cell, and a first deposited layer comprising the first metal layer, the variable resistance element layer, and the non-ohmic element layer are selectively etched. Thus, a first line and space pattern forming step and a first side surface of the non-ohmic element layer that is exposed in a space portion by the first line and space pattern formation are selectively oxidized. An oxidation step, a step of embedding and forming a second insulating film in a space portion of the pattern of the first line and space after the first oxidation step, the first deposited layer, and the second Forming a second metal layer serving as a second wiring layer on the insulating film; and a second layer comprising the variable resistance element layer, the non-ohmic element layer, the second insulating film, and the second metal layer. Forming a second line and space pattern in a direction intersecting with the first line and space by selectively etching the deposited layer, and forming the second line and space pattern And a second oxidation step of selectively oxidizing the side surface of the non-ohmic element layer exposed in the space portion, and a third portion in the space portion of the second line and space pattern after the second oxidation step. And a step of embedding and forming the insulating film.
図１は、ＲｅＲＡＭのメモリコア部の回路構成を示すブロック図である。FIG. 1 is a block diagram showing a circuit configuration of a memory core unit of ReRAM. 図２は、ＲｅＲＡＭのクロスポイント部の構造を示す斜視図である。FIG. 2 is a perspective view showing the structure of the cross point portion of the ReRAM. 図３は、ＲｅＲＡＭのメモリプラグ構造を模式的に示す断面図である。FIG. 3 is a sectional view schematically showing the memory plug structure of the ReRAM. 図４は、ＲｅＲＡＭに用いる非オーミック素子の構造を模式的に示す断面図である。FIG. 4 is a cross-sectional view schematically showing the structure of a non-ohmic element used in ReRAM. 図５は、ＲｅＲＡＭのメモリ素子構造を示す断面図である。FIG. 5 is a cross-sectional view showing the memory element structure of the ReRAM. 図６は、ＲｅＲＡＭのプロセスフローを示す図である。FIG. 6 is a diagram showing a process flow of ReRAM. 図７は、ＲｅＲＡＭの製造工程を示す断面図である。FIG. 7 is a cross-sectional view showing the manufacturing process of the ReRAM. 図８は、ＲｅＲＡＭの製造工程を示す斜視図である。FIG. 8 is a perspective view showing the manufacturing process of the ReRAM. 図９は、本発明の第１の実施例を説明するためのもので、選択酸化を加えたＲｅＲＡＭのプロセスフローを示す図である。FIG. 9 is a diagram for explaining the first embodiment of the present invention, and shows a process flow of ReRAM to which selective oxidation is added. 図１０は、第１の実施例における製造工程を示す断面図である。FIG. 10 is a cross-sectional view showing the manufacturing process in the first embodiment. 図１１は、水素／水蒸気を用いた選択酸化条件を説明するための特性図である。FIG. 11 is a characteristic diagram for explaining selective oxidation conditions using hydrogen / water vapor.
　以下、本発明を実施するための最良の形態について詳細に説明する。 Hereinafter, the best mode for carrying out the present invention will be described in detail.
　まず、本発明の実施形態としてＲｅＲＡＭを例にとって説明を行う。 First, an embodiment of the present invention will be described by taking ReRAM as an example.
　なお、この他の不揮発性半導体メモリ、特に抵抗変化型メモリに対しても適用可能である。また、メモリアレイの構成方法も特にここに記載したものでなくても良い。例えば、ＰＣＲＡＭメモリアレイの場合は、１Ｔ／１Ｒ型のアレイでも良いし、１Ｄ／１Ｒ型のメモリアレイでも良い。 Note that the present invention can also be applied to other nonvolatile semiconductor memories, in particular, resistance change type memories. In addition, the configuration method of the memory array may not be particularly described here. For example, in the case of a PCRAM memory array, a 1T / 1R type array or a 1D / 1R type memory array may be used.
　図１に、本発明の参考例に係わる不揮発性半導体メモリの基本構成を示す。メモリセルアレイ１は、後述する図２に示すように、ＲｅＲＡＭメモリセルを配線のクロスポイント部分に設けることにより構成されている。ここで、メモリセルが多段に積層されて複数層のメモリセルレイヤーが構成されている。また、クロスポイント型のメモリセルアレイ１は配線層に作製可能となっているが、必ずしもこの構造でなくても良い。例えば、図２のようなＷＬ，ＢＬ配線が縦のメモリセルアレイで全て連結された構造でなくても良く、１６５と１５５のメモリセルアレイが無い分離した構造にも適用可能である。さらに、下部のデバイスとのコンタクト領域にメモリセルを挿入した構造であっても良い。 FIG. 1 shows a basic configuration of a nonvolatile semiconductor memory according to a reference example of the present invention. As shown in FIG. 2 to be described later, the memory cell array 1 is configured by providing ReRAM memory cells at cross points of wiring. Here, a plurality of memory cell layers are formed by stacking memory cells in multiple stages. In addition, although the cross-point type memory cell array 1 can be formed in a wiring layer, this structure is not necessarily required. For example, the WL and BL wirings as shown in FIG. 2 need not all be connected by a vertical memory cell array, and can also be applied to a separate structure without the 165 and 155 memory cell arrays. Furthermore, a structure in which a memory cell is inserted into a contact region with a lower device may be used.
　メモリセルアレイ１のビット線ＢＬを制御し、メモリセルのデータ消去、メモリセルへのデータ書き込み、更にはメモリセルからのデータ読み出しを行うカラム制御回路２が設けられている。このカラム制御回路２は、ＭＡＴ（Memory Allocation Table）毎、セクター毎、又はメモリセルレイヤー毎に持ってもよいし、共通（共有）としても良い。さらに、面積の削減のために複数のＢＬで共通としても良い。 A column control circuit 2 is provided for controlling the bit line BL of the memory cell array 1 and erasing data in the memory cell, writing data to the memory cell, and further reading data from the memory cell. The column control circuit 2 may be provided for each MAT (Memory Allocation Table), for each sector, or for each memory cell layer, or may be shared (shared). Furthermore, a plurality of BLs may be shared in order to reduce the area.
　メモリセルアレイ１のワード線ＷＬを選択し，消去，書き込み，読み出しに必要な電圧を印加するために、ロウ制御回路３が設けられている。ロウ制御回路３は、メモリセルレイヤー毎に持ってもよいし、面積の削減のために共通としても良い。また、メモリセルアレイ１はあるメモリセル群のＭＡＴに分けられることも可能であり、その際、制御回路を個々のＭＡＴで持っても良いし、複数のＭＡＴで共有しても良い。また、メモリセルアレイ１はグローバルＢＬとグローバルＷＬを持っても良く、選択トランジスタに区切られるセクターを持っても良い。 A row control circuit 3 is provided to select a word line WL of the memory cell array 1 and apply a voltage necessary for erasing, writing, and reading. The row control circuit 3 may be provided for each memory cell layer or may be common for reducing the area. Further, the memory cell array 1 can be divided into MATs of a certain memory cell group. At this time, the control circuit may be provided by each MAT or may be shared by a plurality of MATs. Further, the memory cell array 1 may have a global BL and a global WL, or may have a sector that is partitioned by selection transistors.
　一方、外部のホスト９にＩ／Ｏ線を介して接続され、書き込みデータの受け取り、消去命令の受け取り、読み出しデータの出力、アドレスデータやコマンドデータの受け取りを行うデータ入出力バッファ６が設けられている。このバッファ６は、受け取った書き込みデータをカラム制御回路２に送り、カラム制御回路２から読み出したデータを受け取る。また、読み出したデータはカラム制御回路２にラッチし、そのデータを入出力バッファ６を通して外部にＩ／Ｏ線から出力することも可能である。 On the other hand, a data input / output buffer 6 is provided which is connected to an external host 9 via an I / O line and receives write data, receives an erase command, outputs read data, and receives address data and command data. Yes. The buffer 6 sends the received write data to the column control circuit 2 and receives data read from the column control circuit 2. It is also possible to latch the read data in the column control circuit 2 and output the data to the outside through the input / output buffer 6 from the I / O line.
　また、ホスト９からのコマンドデータを受け取るコマンド・インターフェイス７と、メモリセルの選択をするためのステートマシン８が設けられている。 Further, a command interface 7 that receives command data from the host 9 and a state machine 8 for selecting a memory cell are provided.
　コマンド・インターフェイス７は、ホスト９からの制御信号を受け、データ入出力バッファ６に入力されたデータが書き込みデータかコマンドデータかアドレスデータかを判断し、コマンドデータであれば受け取りコマンド信号としてステートマシン８に転送する。ステートマシン８は、外部からのアドレスデータをカラム制御回路２及びロウ制御回路３に送り、ＲｅＲＡＭメモリ全体の管理を行うものであり、ホスト９からのコマンドを受け、読み出し，書き込み，消去，及びデータの入出力管理等を行う。 The command interface 7 receives a control signal from the host 9 and determines whether the data input to the data input / output buffer 6 is write data, command data, or address data. 8 is transferred. The state machine 8 sends external address data to the column control circuit 2 and the row control circuit 3 to manage the entire ReRAM memory, receives commands from the host 9, reads, writes, erases, and data I / O management etc.
　また、ホスト９はステートマシン８が管理するステータス情報を受け取り、動作結果を判断することも可能である。さらに、ステータス情報は書き込み、消去の制御にも利用される。 The host 9 can also receive status information managed by the state machine 8 and determine the operation result. Furthermore, the status information is also used for writing and erasing control.
　また、カラム制御回路２，ロウ制御回路３，データ入出力バッファ６，コマンド・インターフェイス７，及びステートマシン８等の周辺回路素子（メモリセルの制御回路）は、配線層に形成されたメモリアレイ直下のＳｉ基板に形成可能である。これにより、この不揮発性半導体記憶装置のチップ面積はほぼ、メモリセルアレイの面積に等しくすることも可能である。 In addition, peripheral circuit elements (memory cell control circuits) such as the column control circuit 2, the row control circuit 3, the data input / output buffer 6, the command interface 7, and the state machine 8 are directly under the memory array formed in the wiring layer. It can be formed on a Si substrate. Thus, the chip area of the nonvolatile semiconductor memory device can be made substantially equal to the area of the memory cell array.
　また、ステートマシン８によってパルスジェネレータ１０が制御される。この制御により、パルスジェネレータ１０は任意の電圧、任意のタイミングのパルスを出力することが可能となる。ここで、形成されたパルスはロウ制御回路３で選択された任意の配線へ転送することが可能である。 Further, the pulse generator 10 is controlled by the state machine 8. By this control, the pulse generator 10 can output a pulse having an arbitrary voltage and arbitrary timing. Here, the formed pulse can be transferred to any wiring selected by the row control circuit 3.
　図２は、メモリセルアレイ１の構成を示す斜視図である。図中の１７５，１８０，１８５は第１の配線層としてのワード線（ＷＬ）、１９０，１９５は第２の配線層としてのビット線（ＢＬ）、１５５，１６０，１６５，１７０はメモリセル部を示している。 FIG. 2 is a perspective view showing the configuration of the memory cell array 1. In the figure, 175, 180, and 185 are word lines (WL) as a first wiring layer, 190 and 195 are bit lines (BL) as a second wiring layer, and 155, 160, 165, and 170 are memory cell portions. Is shown.
　メモリセルアレイ１はクロスポイント型となっており、この場合、４層スタックのメモリセルアレイとなっている。クロスポイント構造とは第１の平行に配置された配線と、それと交差する第２の配線との間の交点にセルが挟まれている構造を指す。本例では、この構造が複数層に堆積されている。ここでは、配線／セル／配線／セル／配線と繰り返されているが、配線／セル／配線／層間絶縁膜／配線／セル／配線というような構造にしても良い。 The memory cell array 1 is a cross-point type. In this case, it is a four-layer stack memory cell array. The cross-point structure refers to a structure in which a cell is sandwiched at an intersection between a first wiring arranged in parallel and a second wiring that intersects the first wiring. In this example, this structure is deposited in a plurality of layers. Here, the wiring / cell / wiring / cell / wiring is repeated, but a structure such as wiring / cell / wiring / interlayer insulating film / wiring / cell / wiring may be used.
　前者の構造はレイヤーが少なくなり、コスト的なメリットも得られるが、一つの配線が共有するセルの数が多くなり、パフォーマンスの悪化，非選択セルのディスターブ等、信頼性の悪化が考えられる。後者は配線層が多くなり、コストが高くなるが、一つの配線にぶら下がるセルが前者の半分なので、高速動作に向いており、また信頼性の面でも前者よりも優る。 The former structure has fewer layers and can provide cost advantages, but the number of cells shared by a single wiring increases, which may lead to deterioration of reliability, such as deterioration of performance and disturbance of unselected cells. The latter requires more wiring layers and is costly. However, since the cells hanging on one wiring are half of the former, it is suitable for high-speed operation and is superior to the former in terms of reliability.
　図３に、具体的なメモリ素子構造を示す。図中の２１０は第１の配線層であり、熱に強い材料、かつ抵抗の低い材料が望まれ、例えばＷ／ＷＳｉ／ＮｉＳｉ／ＣｏＳｉ等で形成される。２２５は電圧，電流、又は熱，化学エネルギー等で抵抗を変化させることができる可変抵抗素子であり、この可変抵抗素子２２５は抵抗値の異なる状態を情報として記憶するものである。２２０は可変抵抗素子２２５の下部電極、２３０は可変抵抗素子２２５の上部電極となる。各電極２２０，２３０は、バリアメタルや接着層としての役目を同時に担うことも可能で、Ｐｔ／Ａｕ／Ａｇ／ＴｉＡｌＮ／ＳｒＲｕＯ／Ｒｕ／ＲｕＮ／Ｉｒ／Ｃｏ／Ｔｉ／ＴｉＮ／ＴａＮ／ＬａＮｉＯ／Ａｌ／ＰｔＩｒＯｘ／ＰｔＲｈＯｘ／Ｒｈ／ＴａＡｌＮ等で形成される。また、配向性を一様にするようなメタル膜の挿入も可能である。さらに、別途バッファ層，バリアメタル層，接着層等を挿入することも可能である。 FIG. 3 shows a specific memory element structure. Reference numeral 210 in the figure denotes a first wiring layer, which is preferably made of a material resistant to heat and having a low resistance, and is formed of, for example, W / WSi / NiSi / CoSi. Reference numeral 225 denotes a variable resistance element whose resistance can be changed by voltage, current, heat, chemical energy, or the like, and this variable resistance element 225 stores states having different resistance values as information. 220 is a lower electrode of the variable resistance element 225, and 230 is an upper electrode of the variable resistance element 225. Each of the electrodes 220 and 230 can simultaneously serve as a barrier metal or an adhesive layer. Pt / Au / Ag / TiAlN / SrRuO / Ru / RuN / Ir / Co / Ti / TiN / TaN / LaNiO / Al / PtIrOx / PtRhOx / Rh / TaAlN or the like. It is also possible to insert a metal film that makes the orientation uniform. Further, it is possible to insert a buffer layer, a barrier metal layer, an adhesive layer and the like separately.
　２３５は非オーミック素子であり、ｐｎ接合ダイオード，ｐｉｎダイオード，ショットキーダイオード等の各種ダイオード，ＭＩＭ（Metal-Insulator-Metal）構造，ＳＩＳ構造（Silicon-Insulator-Silicon）等を用いることができる。図４（ａ）にＭＩＭ構造の例を示し、図４（ｂ）にｐｉｎ構造の例を示す。ここにも、バリアメタル層や接着層を挿入しても良い。また、ダイオードを使用する場合はその特性上、ユニポーラ動作を行うことができ、また、ＭＩＭ構造等の場合にはバイポーラ動作を行うことが可能である。 235 is a non-ohmic element, and various diodes such as a pn junction diode, a pin diode, and a Schottky diode, a MIM (Metal-Insulator-Metal) structure, a SIS structure (Silicon-Insulator-Silicon), and the like can be used. FIG. 4A shows an example of the MIM structure, and FIG. 4B shows an example of the pin structure. Also here, a barrier metal layer or an adhesive layer may be inserted. Further, when a diode is used, a unipolar operation can be performed due to its characteristics, and when a MIM structure or the like is used, a bipolar operation can be performed.
　２１５は第１の配線層２１０と交差する第２の配線層であり、Ｗ／ＷＳｉ／ＮｉＳｉ／ＣｏＳｉ等で形成される。さらに、２４０は非オーミック素子２３５と第２の配線層２１５との間のバリアメタル層又は接着層となり、Ｔｉ／ＴｉＮ等で形成される。また、今回非オーミック素子２１５にはダイオードを使用しており、ＢＬをセンターにミラー構造になっているが、非オーミック素子２１５の配置はこれにはこだわらない。その場合は、ＷＬとＢＬのバイアス関係を変化させることで、対応可能である。本例ではユニポーラ動作、バイポーラ動作どちらも実施可能である。 215 is a second wiring layer that intersects the first wiring layer 210 and is formed of W / WSi / NiSi / CoSi or the like. Further, 240 becomes a barrier metal layer or an adhesive layer between the non-ohmic element 235 and the second wiring layer 215, and is formed of Ti / TiN or the like. In addition, a diode is used for the non-ohmic element 215 this time and has a mirror structure with BL at the center, but the arrangement of the non-ohmic element 215 is not particularly concerned with this. In that case, it is possible to cope with this by changing the bias relationship between WL and BL. In this example, both unipolar operation and bipolar operation can be performed.
　図５は、ＲｅＲＡＭのメモリ素子構造を示す断面図である。 FIG. 5 is a cross-sectional view showing the ReRAM memory element structure.
　Ｓｉ基板４００上にＦＥＯＬ（Front End Of Line）プロセスを行うことにより、基板表面部のアクティブ領域に周辺回路等の制御回路部が設けられている。基板４００上に第１の層間絶縁膜４１０が堆積され、この層間絶縁膜４１０には、下部のデバイスとのコンタクトを取るためのビア４１５が設けられている。 By performing an FEOL (Front End Of Line) process on the Si substrate 400, a control circuit section such as a peripheral circuit is provided in an active area on the surface of the substrate. A first interlayer insulating film 410 is deposited on the substrate 400, and a via 415 for making contact with a lower device is provided in the interlayer insulating film 410.
　層間絶縁膜４１０上には、クロスポイントアレイの第１の配線層４２０がＷ（その他の低抵抗のメタルでも適用可能）により形成され、その上層にバリアメタル層４３０がＴｉ／ＴｉＮにより形成されている。第１の配線層４２０の下層にもバリアメタルを形成しても良い。また、ここでのバリアメタル層４３０は、Ｔｉ，ＴｉＮの両方を用いても良いし、どちらかでも良い。また、この上層以降に対してバリアメタルを挿入しても良い。 On the interlayer insulating film 410, a first wiring layer 420 of a cross-point array is formed of W (can be applied to other low-resistance metals), and a barrier metal layer 430 is formed of Ti / TiN on the upper layer. Yes. A barrier metal may also be formed below the first wiring layer 420. Further, the barrier metal layer 430 here may use both Ti and TiN, or may be either. Further, a barrier metal may be inserted into the upper layer and the subsequent layers.
　バリアメタル層４３０上には、非オーミック素子となるダイオード４４０が形成されている。ここでは、ｐｎ接合ダイオード，ｐｉｎダイオード，ショットキーダイオード等の各種ダイオードを作製可能であり、材料もポリＳｉでも良いし、その他の材料でも適用可能である。さらに、ダイオード４４０の替わりに、ＭＩＭ構造、ＳＩＳ構造等を用いることもできる。 A diode 440 serving as a non-ohmic element is formed on the barrier metal layer 430. Here, various diodes such as a pn junction diode, a pin diode, and a Schottky diode can be manufactured, and the material may be poly-Si or other materials can be applied. Further, an MIM structure, an SIS structure, or the like can be used instead of the diode 440.
　ダイオード４４０上には、可変抵抗素子の電極となる下部電極４５０、可変抵抗素子材料層４６０、上部電極４７０が形成されている。電極４５０，４７０は、例えばＴｉＮやＴａＮである。これにより、非オーミック素子と可変抵抗素子を直列接続したメモリセルが構成される。また、上部、下部電極の外側にバリアメタルを挿入しても良いし、その内側にバリアメタル、接着層を挿入しても良い。ここで、メモリセルとメモリセルの間は第２及び第３の層間絶縁膜４８０，４８５で埋められている。但し、第２の層間絶縁膜４８０はこの断面図では見えていない。さらに、上部電極４７０上には、クロスポイントメモリアレイの第２の配線層４９０が形成される。 On the diode 440, a lower electrode 450 serving as an electrode of a variable resistance element, a variable resistance element material layer 460, and an upper electrode 470 are formed. The electrodes 450 and 470 are, for example, TiN or TaN. Thereby, a memory cell in which a non-ohmic element and a variable resistance element are connected in series is configured. In addition, a barrier metal may be inserted outside the upper and lower electrodes, or a barrier metal and an adhesive layer may be inserted inside. Here, the space between the memory cells is filled with second and third interlayer insulating films 480 and 485. However, the second interlayer insulating film 480 is not visible in this cross-sectional view. Further, a second wiring layer 490 of the cross point memory array is formed on the upper electrode 470.
　また、第２の配線層４９０まで形成した基板上には第４，第５の層間絶縁膜５１０，５１５が形成され、さらに層間絶縁膜５１０，５１５上にメタル配線層５２０，５２５等が形成される。 In addition, fourth and fifth interlayer insulating films 510 and 515 are formed on the substrate formed up to the second wiring layer 490, and metal wiring layers 520 and 525 are formed on the interlayer insulating films 510 and 515. The
　図６は、図５のＲｅＲＡＭのプロセスフローを示す図である。初めにＳｉ基板４００の準備を行い（ステップＳ１）、Ｓｉ基板４００上にＦＥＯＬプロセスを行い（ステップＳ２）、その上部に第１の層間絶縁膜４１０を堆積させる（ステップＳ３）。また、ビア４１５もここで作製しておく。 FIG. 6 is a diagram showing a process flow of the ReRAM in FIG. First, the Si substrate 400 is prepared (Step S1), the FEOL process is performed on the Si substrate 400 (Step S2), and the first interlayer insulating film 410 is deposited thereon (Step S3). The via 415 is also prepared here.
　次に、クロスポイントアレイの第１の配線層４２０となる第１のメタル層の堆積をＷ（その他の低抵抗のメタルでも適用可能）により行い（ステップＳ４）、その上層にバリアメタル層４３０をＴｉ／ＴｉＮにより形成する（ステップＳ５）。また、第１の配線層４２０となるメタル層の下層にもバリアメタル層を形成しても良い。また、ここでのバリアメタルはＴｉ，ＴｉＮの両方を用いても良いし、どちらかでも良い。さらに、その上方には非オーミック素子４４０となる層の堆積を行う（ステップＳ６）。 Next, the first metal layer to be the first wiring layer 420 of the cross point array is deposited by W (applicable to other low-resistance metal) (step S4), and the barrier metal layer 430 is formed thereon. It forms by Ti / TiN (step S5). In addition, a barrier metal layer may be formed below the metal layer that becomes the first wiring layer 420. The barrier metal here may be either Ti or TiN, or may be either. Further, a layer to be a non-ohmic element 440 is deposited above the layer (step S6).
　ここで、非オーミック素子４４０としてダイオード，ＭＩＭ構造等が形成される。材料もダイオードの場合はポリＳｉでも良いし、その他の材料でも適用可能である。ＭＩＭ（ＳＩＳ）構造の場合、仕事関数が高いメタルでもポリＳｉでも良い。また、絶縁膜部も１層でも良いし、２層以上でバンドエンジニアリングしても良い。 Here, as the non-ohmic element 440, a diode, an MIM structure, or the like is formed. In the case of a diode, the material may be poly-Si, or other materials can be applied. In the case of the MIM (SIS) structure, a metal having a high work function or poly-Si may be used. Also, the insulating film portion may be a single layer, or band engineering may be performed with two or more layers.
　次に、メモリ素子層となる可変抵抗素子層の堆積を行う（ステップＳ７）。ここでは、下部電極４５０、可変抵抗素子材料層４６０、上部電極４７０が形成される。前述したように上部、下部電極の外側にバリアメタル層を挿入しても良いし、その内側にバリアメタル層、接着層を挿入しても良い。また、更にこの上層にエッチングやＣＭＰ用のハードマスクとなる層を堆積させても良い。この４２０～４７０まで、べた膜で堆積させた第１の堆積層の断面図を、図７（ａ）に示す。 Next, a variable resistance element layer serving as a memory element layer is deposited (step S7). Here, a lower electrode 450, a variable resistance element material layer 460, and an upper electrode 470 are formed. As described above, a barrier metal layer may be inserted outside the upper and lower electrodes, or a barrier metal layer and an adhesive layer may be inserted inside thereof. Further, a layer serving as a hard mask for etching or CMP may be deposited on this upper layer. FIG. 7A shows a cross-sectional view of the first deposited layer deposited from 420 to 470 with a solid film.
　なお、可変抵抗素子材料層４６０としては、Ｇｅ2 Ｓｂ2 Ｔｅ5 やその他カルコゲナイド系物質などの相変化材料や、ＡｇリッチなＡｇ－Ｇｅ－Ｓｅ系カルコゲナイド物質やＣｕ2 Ｓなどのイオン伝導材料、ロタキサン超分子やその他分子材料、絶縁膜中に金属層を挟んだ構造を持つ材料、ＰｒＣａＭｎＯ3 などのＣＭＲ（Colossal Magneto Resistive）物質を有する材料を用いることができる。また、電子のスピンを利用したスピン注入ＭＴＪや、抵抗変化性のメモリ素子として知られるＡｇ2 Ｓ，ＺｎｘＣｄＳ，Ａｇ－Ｇｅ－Ｓｅ系，ＰｒＣａＭｎＯ3 などの巨大磁気抵抗効果を示す物質、ＮｉＯｘ，ＴｉＯｘ，ＨｆＯ2，ＺｒＯ2，ＳｒＺｒＯ3、ＳｒＴｉＯ3 などを用いることも可能である。 The variable resistance element material layer 460 includes a phase change material such as Ge 2 Sb 2 Te 5 and other chalcogenide materials, an Ag-rich Ag—Ge—Se chalcogenide material, an ion conductive material such as Cu 2 S, and the like. Rotaxane supramolecules, other molecular materials, materials having a structure in which a metal layer is sandwiched between insulating films, and materials having a CMR (Colossal Magneto Resistive) substance such as PrCaMnO 3 can be used. In addition, spin injection MTJ using electron spin, Ag 2 S, ZnxCdS, Ag—Ge—Se system, PrCaMnO 3, and the like, which are known as resistance-changeable memory elements, exhibit a giant magnetoresistance effect, such as NiOx and TiOx. , HfO 2 , ZrO 2 , SrZrO 3 , SrTiO 3, etc. can also be used.
　その後、第１のエッチング加工を行う（ステップＳ８）。これにより、第１の堆積層をまず、最小ピッチでのＬ／Ｓに加工する。本実施形態では、この加工後に、加工によりスペース部分に露出した非オーミック素子層の側面を選択的に酸化することが特徴である。この酸化により、非オーミック素子側面のリーク電流の低減が可能となり、読み出し・スイッチング特性の改善、セルの抵抗変化のばらつき等の改善を行うことができ、動作電流が低く、低消費電力化が可能な不揮発性の抵抗変化メモリを実現することができる。 Thereafter, a first etching process is performed (step S8). Thereby, the first deposited layer is first processed to L / S at the minimum pitch. The present embodiment is characterized in that after this processing, the side surface of the non-ohmic element layer exposed to the space portion by processing is selectively oxidized. This oxidation makes it possible to reduce the leakage current on the side of the non-ohmic device, improve read / switching characteristics, improve variation in cell resistance, etc., and reduce operating current and reduce power consumption. A nonvolatile resistance change memory can be realized.
　次に、第２の層間絶縁膜４８０の埋め込みを行い（ステップＳ９）、Ｓ８で加工したＬ／Ｓのスペース部を埋める。この層間絶縁膜４８０の材料は絶縁性が良く、低容量で埋め込み特性が良いものが好まれる。次に、第２の層間絶縁膜４８０の平坦化を行い（ステップＳ１０）、ＣＭＰ法による余分な絶縁膜の除去と電極部の露出を行う。このときの断面図を図７（ｂ）に示す。このとき、ハードマスクを使用していた場合はそのエッチング等が必要になる。 Next, the second interlayer insulating film 480 is embedded (step S9), and the L / S space portion processed in S8 is embedded. The material of the interlayer insulating film 480 is preferably a material having good insulating properties, low capacitance, and good embedding characteristics. Next, the second interlayer insulating film 480 is planarized (step S10), and the excess insulating film is removed by CMP and the electrode portion is exposed. A cross-sectional view at this time is shown in FIG. At this time, if a hard mask is used, etching or the like is required.
　次に、第２の配線層４９０となるメタル層の堆積（ステップＳ１１）により、ＣＭＰ後の平坦化部にタングステンを積層する。このときのイメージ図を、図８（ａ）の斜視図に示す。 Next, tungsten is laminated on the planarized portion after CMP by depositing a metal layer to be the second wiring layer 490 (step S11). An image diagram at this time is shown in the perspective view of FIG.
　その後、４３０～４８０までの第２の堆積層に対し、第２のエッチング加工（ステップＳ１２）を、第１のエッチング加工と交差する方向のＬ／Ｓで行う。これにより、図８（ｂ）に示すように、第１の配線層４２０とは直交する方向に互いに平行配置された複数本の配線からなる第２の配線層４９０を形成する。 Thereafter, the second etching process (step S12) is performed on the second deposition layers from 430 to 480 with L / S in a direction intersecting with the first etching process. As a result, as shown in FIG. 8B, a second wiring layer 490 composed of a plurality of wirings arranged in parallel to each other in a direction orthogonal to the first wiring layer 420 is formed.
　本実施形態では、この加工後に、加工によりスペース部分に露出した非オーミック素子層の側面を選択的に酸化することが特徴である。この酸化により、非オーミック素子側面のリーク電流の低減が可能となり、読み出し・スイッチング特性の改善、セルの抵抗変化のばらつき等の改善を行うことができ、動作電流が低く、低消費電力化が可能な不揮発性の抵抗変化メモリを実現することができる。 This embodiment is characterized in that after this processing, the side surface of the non-ohmic element layer exposed to the space portion by processing is selectively oxidized. This oxidation makes it possible to reduce the leakage current on the side of the non-ohmic device, improve read / switching characteristics, improve variation in cell resistance, etc., and reduce operating current and reduce power consumption. A nonvolatile resistance change memory can be realized.
　次に再び、第３の層間絶縁膜４８５の埋め込み（ステップＳ１３）と、第３の層間絶縁膜４８５の平坦化（ステップＳ１４）を行うことにより、図８（ｃ）のようなクロスポイント型のメモリアレイ層が形成可能となる。 Next, the third interlayer insulating film 485 is embedded again (step S13) and the third interlayer insulating film 485 is flattened (step S14), whereby a cross-point type as shown in FIG. A memory array layer can be formed.
　このように、べた膜の積み重ねからＬ／Ｓの２回のパターニングを行うことにより、自己整合的にセル部が形成され、合わせずれをあまり気にしなくても良いプロセスを提供することができる。 Thus, by performing the L / S patterning twice from the stacking of the solid films, a cell portion is formed in a self-aligning manner, and a process that does not require much attention to misalignment can be provided.
　そして、この積層構造の形成を繰り返すことにより（ステップＳ１５）、積層タイプのクロスポイント型のメモリセルアレイの形成が可能である。このとき、バリアメタル層の堆積から繰り返すと、上層と下層で隣り合うメモリセルアレイの配線を共有化するメモリセルアレイが実現できる。また、第１の層間絶縁膜４１０の形成から繰り返すことで、上層と下層で隣り合うメモリセルアレイの配線を共有化しないメモリセルアレイを実現することができる。これらの違いによるメリット、デメリットは前述した通りである。 Then, by repeating the formation of this stacked structure (step S15), it is possible to form a stacked type cross-point type memory cell array. At this time, by repeating the deposition from the deposition of the barrier metal layer, a memory cell array that shares the wirings of adjacent memory cell arrays in the upper layer and the lower layer can be realized. Further, by repeating the formation of the first interlayer insulating film 410, it is possible to realize a memory cell array that does not share the wirings of adjacent memory cell arrays in the upper layer and the lower layer. The advantages and disadvantages of these differences are as described above.
　その後、メタル配線層の形成を行い（ステップＳ１６）、本参考例の不揮発性半導体記憶装置が完成することになる。 Thereafter, a metal wiring layer is formed (step S16), and the nonvolatile semiconductor memory device of this reference example is completed.
　（第１の実施例）
　本実施例では、非オーミック素子層の側面の選択酸化を具体的に考える。通常の酸化では、メタル配線が酸化されてしまい、配線抵抗が上昇する。そこで本実施例では、メタル配線を酸化することなく、非オーミック素子層の側面の加工ダメージのみ酸化修復する選択酸化を行う。これにより、側面を介したリーク電流が低減できるため、書込み，消去動作，保持特性等の安定動作が可能となる。この時のプロセスフローを、図９に示す。図６のエッチング加工（Ｓ８）までは図９でも同様である。 (First embodiment)
In this embodiment, the selective oxidation of the side surface of the non-ohmic element layer is specifically considered. In normal oxidation, metal wiring is oxidized and wiring resistance increases. Therefore, in this embodiment, selective oxidation is performed in which only the processing damage on the side surface of the non-ohmic element layer is oxidized and repaired without oxidizing the metal wiring. As a result, the leakage current through the side surface can be reduced, so that stable operations such as writing, erasing operation and holding characteristics can be performed. The process flow at this time is shown in FIG. The same applies to FIG. 9 up to the etching process (S8) in FIG.
　本実施例では、Ｓ８の後に第１の選択酸化処理（Ｓ２１）を行う。その後のＳ９～Ｓ１２までは図６と同様であり、Ｓ１２の後に第２の選択酸化処理（Ｓ２２）を行う。その後のＳ１３～Ｓ１６は図６と同様である。即ち、図６のプロセスと異なる点は、Ｓ８の第１のエッチング加工の後に第１の選択酸化処理（Ｓ２１）を行うこと、更にはＳ１２の第２のエッチング加工の後に第２の選択酸化処理（Ｓ２２）を行うことである。 In this embodiment, the first selective oxidation process (S21) is performed after S8. The subsequent S9 to S12 are the same as in FIG. 6, and the second selective oxidation process (S22) is performed after S12. Subsequent S13 to S16 are the same as those in FIG. 6 differs from the process of FIG. 6 in that the first selective oxidation process (S21) is performed after the first etching process of S8, and further the second selective oxidation process is performed after the second etching process of S12. (S22) is performed.
　Ｓ８のエッチングした状態の断面を図１０（ａ）に示す。また、Ｓ２１の選択酸化した状態の断面を図１０（ｂ）に示す。非オーミック素子４４０の側面と共に、バリアメタル層４３０及び電極４５０，４７０の側面が酸化され、側壁酸化膜５００が形成される。第１の配線層４２０としてのメタル層は酸化されていない。電極４５０，４７０が酸化されるのは、電極材料としてＴｉＮやＴａＮ等を用いたからであり、電極４５０，４７０としてＳ２１の選択酸化処理では酸化されない材料を用いることも可能である。また、図１０（ｂ）では、可変抵抗素子材料層４６０の側面は酸化されていないが、この層４６０が酸化されていても何ら問題はない。 FIG. 10A shows a cross section of the etched state of S8. Further, FIG. 10B shows a cross section of the state of selective oxidation of S21. Along with the side surface of the non-ohmic element 440, the side surfaces of the barrier metal layer 430 and the electrodes 450 and 470 are oxidized to form a sidewall oxide film 500. The metal layer as the first wiring layer 420 is not oxidized. The electrodes 450 and 470 are oxidized because TiN, TaN, or the like is used as the electrode material. It is also possible to use a material that is not oxidized by the selective oxidation treatment of S21 as the electrodes 450 and 470. In FIG. 10B, the side surface of the variable resistance element material layer 460 is not oxidized, but there is no problem if the layer 460 is oxidized.
　ここで、選択酸化工程の条件について図１１を用いて説明する。温度Ｔ（Ｋ）における酸化物生成の自由エネルギー（Gibbs Free Energy）をΔＧ（Ｔ）とし、材料Ｍの酸化還元反応：Ｍ＋２Ｈ2Ｏ⇔ＭＯ2 ＋２Ｈ2 が平衡状態になるための水素／水蒸気分圧比Ｐ（Ｈ2）／Ｐ（Ｈ2Ｏ）とΔＧ（Ｔ）の関係は以下のように記すことができる（A. R. Swalin：固体の熱力学）。
Figure JPOXMLDOC01-appb-M000001
 Here, the conditions of the selective oxidation step will be described with reference to FIG. The free energy of oxide formation (Gibbs Free Energy) at temperature T (K) is ΔG (T), and the redox reaction of material M: hydrogen / water vapor content for M + 2H 2 O⇔MO 2 + 2H 2 to be in an equilibrium state The relationship between the pressure ratio P (H 2 ) / P (H 2 O) and ΔG (T) can be described as follows (A. R. Swalin: solid thermodynamics).
Figure JPOXMLDOC01-appb-M000001

　ここで、Ｒは気体定数である。熱処理温度Ｔを決めれば熱力学データーベースよりΔＧ（Ｔ）が求められ、更に（１）式を用いることでＰ（Ｈ2）／Ｐ（Ｈ2Ｏ）が決定し、この比よりも小さい条件では酸化、大きい条件では還元反応が進むことになる。図１１ではＷ，Ｚｒ，Ｈｆ，Ｓｉ及びＧｅにおける酸化還元境界を示しており、材料毎に境界が大きく異なることが分かる。図中の縦の矢印は選択酸化領域を示しており、Ｓｉ，Ｚｒ及びＨｆは酸化されるがＷ及びＧｅは酸化されない領域が広い温度範囲で存在する。即ち、本選択酸化条件下において、例えばＳｉを用いたｐｎ，ｐｉｎダイオード等は酸化されて側面酸化膜を形成するものの、Ｗ配線は酸化されないことになる（図１０（ｂ））。
Here, R is a gas constant. If the heat treatment temperature T is determined, ΔG (T) is obtained from the thermodynamic database, and further, P (H 2 ) / P (H 2 O) is determined by using the equation (1). Then, oxidation and reduction reaction proceed under large conditions. FIG. 11 shows redox boundaries in W, Zr, Hf, Si and Ge, and it can be seen that the boundaries differ greatly depending on the material. Vertical arrows in the figure indicate selective oxidation regions, and there are regions where Si, Zr and Hf are oxidized but W and Ge are not oxidized in a wide temperature range. That is, under this selective oxidation condition, for example, a pn, pin diode or the like using Si is oxidized to form a side oxide film, but the W wiring is not oxidized (FIG. 10B).
　但し、この選択酸化技術を量産に適用する際、大きく二つの問題が発生している。一つはＷ，Ｇｅ等の汚染であり、これまでは高温の選択酸化と後熱処理が行われてきたが、Ｗは７００℃よりも高温でＨ2Ｏと反応して揮発することが知られており（K.Miyano et al., Adv. Met. Interconnect Syst. ULSI Appl. 677(1997).）、更にＧｅＯ2 ／Ｇｅ構造ではＴＤＳ（Thermal Desorption Spectroscopy）分析より約５００℃でＧｅＯ（質量数８８）として全て脱離してしまうことを確認している。このＧｅＯ脱離は、ＧｅにＮ等の他元素を添加することである程度抑制可能である。 However, when this selective oxidation technique is applied to mass production, two major problems occur. One is contamination of W, Ge, etc., and high-temperature selective oxidation and post-heat treatment have been performed so far, but W is known to react with H 2 O at a temperature higher than 700 ° C. and volatilize. (K.Miyano et al., Adv. Met. Interconnect Syst. ULSI Appl. 677 (1997)), and GeO 2 / Ge structure, GeO (mass number) at about 500 ° C. from TDS analysis. 88), it has been confirmed that all detachment has occurred. This GeO desorption can be suppressed to some extent by adding other elements such as N to Ge.
　これらの結果を踏まえて選択酸化条件は７００℃以下、より好ましくはＧｅＯ脱離を抑制する上でも５００℃以下が望ましい。二つ目の問題は分圧比の制御性であり、量産装置において６桁を超える分圧比のウェハ面内制御は難しい。これよりＰ（Ｈ2）／Ｐ（Ｈ2Ｏ）のダイナミックレンジは６桁以下が望ましい。 Based on these results, the selective oxidation condition is 700 ° C. or lower, more preferably 500 ° C. or lower for suppressing GeO desorption. The second problem is controllability of the partial pressure ratio, and it is difficult to control in-wafer plane with a partial pressure ratio exceeding 6 digits in a mass production apparatus. Accordingly, the dynamic range of P (H 2 ) / P (H 2 O) is preferably 6 digits or less.
　これらの議論から選択酸化の最適条件を、図１１中に斜め線で示す。より好ましい条件は更にハッチングにしている。これら最適条件を示す数式を以下に記す。
Figure JPOXMLDOC01-appb-M000002
 From these discussions, the optimum conditions for selective oxidation are indicated by diagonal lines in FIG. More preferable conditions are further hatched. Formulas indicating these optimum conditions are described below.
Figure JPOXMLDOC01-appb-M000002

　ここで、各種元素の自由エネルギーとしてＳｉ，Ｚｒ，ＨｆをΔＧＩ，Ｗ，ＧｅをΔＧＭ、更に水をΔＧＨ2Ｏとしている。（２）式より選択酸化条件はΔＧＩ，ΔＧＭの大小関係で決まり、ΔＧＭがΔＧＩ以上の値を持つ温度範囲で水素と水蒸気の両者を含む雰囲気に前記側面を曝露することがポイントである。即ち、上記材料に限らず（２）式の条件を満たすことのできる材料の組み合わせが存在すれば、金属電極を酸化することなく非オーミック素子側面を酸化することが可能である。
Here, as free energy of various elements, Si, Zr, and Hf are ΔGI, W, and Ge are ΔGM, and water is ΔGH 2 O. The selective oxidation condition is determined by the relationship between ΔGI and ΔGM from the equation (2), and the point is that the side surface is exposed to an atmosphere containing both hydrogen and water vapor in a temperature range where ΔGM has a value equal to or greater than ΔGI. That is, the side surface of the non-ohmic element can be oxidized without oxidizing the metal electrode if there is a combination of materials that can satisfy the condition of the formula (2) without being limited to the above materials.
　また、前記（２）～（４）式の最適な選択酸化条件において、Ｈ2 が重水素（Ｄ2），Ｈ2Ｏが重水（Ｄ2Ｏ）に変化してもΔＧは大きく変化しないため、その効果は維持される。即ちＨ2／Ｄ2Ｏ，Ｄ2／Ｈ2Ｏ若しくはＤ2／Ｄ2Ｏ雰囲気での熱処理において同様の選択酸化効果を得ることができる。更にＤ2 若しくはＤ2Ｏの少なくとも一方のガスを用いた場合、周辺材料に取り込まれたＤ原子はＨ原子と異なり質量数の違いから膜中の拡散速度が遅いため、Ｈ原子に比べて新たな欠陥を形成することが少ない。即ち、Ｄ原子を含むセル構造の電気的信頼性は高くなる。 Further, in the (2) to (4) of the optimum selective oxidation conditions, H 2 is deuterium (D 2), since the H 2 O is ΔG does not change significantly even if changes in heavy water (D 2 O) The effect is maintained. That is, the same selective oxidation effect can be obtained in the heat treatment in an H 2 / D 2 O, D 2 / H 2 O or D 2 / D 2 O atmosphere. Furthermore, when at least one gas of D 2 or D 2 O is used, D atoms taken into the surrounding material are slower than the H atoms because the diffusion rate in the film is slow due to the difference in mass number unlike the H atoms. Rarely form defects. That is, the electrical reliability of the cell structure containing D atoms is increased.
　本実施例では主に配線材料としてＷ膜、非オーミック素子材料としてＳｉについて述べたが、（２）式の条件を満たす材料において本発明は適用可能であり、特に非オーミック素子材料としてＳｉ，Ｔｉ，Ａｌ，Ｌａ，Ｐｒ，Ｙ，Ｃｅ，Ｓｒ，Ｄｙ，Ｅｒ，Ｌｕ若しくはＧｄを含む材料に有効である。更にそれらのシリケート膜、アルミネート膜、酸窒化膜、窒化膜、混合膜及び各種多層膜においてもその有効性が維持される。配線材料としてはＧｅ，Ｇａ，Ａｕ，Ｃｕ，Ｔａ，Ｍｏ，Ｉｒ，Ｒｕ若しくはＮｉを含む材料も適用可能である。また、これらの材料の成膜手法に依らず、スパッタ、ＡＬＣＶＤ（Atomic Layer ＣＶＤ）、蒸着及びプラズマＣＶＤ等で形成した膜であっても同様の効果を得ることができる。 In this embodiment, the W film is mainly described as the wiring material, and Si is described as the non-ohmic element material. However, the present invention can be applied to materials satisfying the expression (2), and particularly Si, Ti as the non-ohmic element material. , Al, La, Pr, Y, Ce, Sr, Dy, Er, Lu, or Gd. Furthermore, the effectiveness of the silicate film, aluminate film, oxynitride film, nitride film, mixed film, and various multilayer films is maintained. As the wiring material, a material containing Ge, Ga, Au, Cu, Ta, Mo, Ir, Ru, or Ni is also applicable. In addition, the same effect can be obtained even with a film formed by sputtering, ALCVD (Atomic Layer CVD), vapor deposition, plasma CVD, or the like, regardless of the film forming method of these materials.
　このように本実施例によれば、可変抵抗素子を用いた不揮発性半導体メモリセルアレイの製造方法に関して、配線、電極、非オーミック素子、可変抵抗素子を一括にエッチングした後、選択酸化プロセスを適用することで非オーミック素子側面のリーク電流の低減が可能となり、読み出し・スイッチング特性の改善、セルの抵抗変化のばらつき等の改善を行うことができ、動作電流が低く、低消費電力化が可能な不揮発性の抵抗変化メモリを実現することができる。 As described above, according to the present embodiment, the selective oxidation process is applied to the manufacturing method of the nonvolatile semiconductor memory cell array using the variable resistance element after the wiring, the electrode, the non-ohmic element, and the variable resistance element are collectively etched. This makes it possible to reduce the leakage current on the side surface of the non-ohmic element, improve read / switching characteristics, improve variation in cell resistance change, etc., and can operate with low operating current and low power consumption. Resistance change memory can be realized.
　ここで、非オーミック素子はｐｎ，ｐｉｎ，ショットキーダイドードに限らず積層絶縁膜若しくは酸化物半導体においても、加工時に生じた側壁部のダメージを選択酸化により修復し、リークを防止することが可能であり、可変抵抗素子特性の劣化防止に効果的である。 Here, the non-ohmic element is not limited to pn, pin, and Schottky diode, and the damage of the side wall portion caused during processing can be repaired by selective oxidation in a laminated insulating film or an oxide semiconductor to prevent leakage. It is effective in preventing the deterioration of the variable resistance element characteristics.
　（第２の実施例）
　本発明の第２の実施例について、第１の実施例と同じく非オーミック素子の側面の選択酸化を考える。前記図９の説明でも述べたようにクロスポイントメモリ作成工程では、メタル配線を酸化することなく非オーミック素子側面の加工ダメージのみ酸化修復する選択酸化が必須となる。そこで、Ｄ2Ｏを放電した雰囲気にて加熱を行うことにより、Ｗ表面を酸化することなくＳｉ表面を選択還元して、前記図１０（ｂ）に示すセル構造が完成する。このときの放電条件を以下に記す。 (Second embodiment)
For the second embodiment of the present invention, the selective oxidation of the side surface of the non-ohmic element is considered as in the first embodiment. As described in the description of FIG. 9, in the cross-point memory creation process, selective oxidation that oxidizes and repairs only the processing damage on the side surface of the non-ohmic element without oxidizing the metal wiring is essential. Therefore, by heating in an atmosphere in which D 2 O is discharged, the Si surface is selectively reduced without oxidizing the W surface, and the cell structure shown in FIG. 10B is completed. The discharge conditions at this time are described below.
　真空中昇温→Ｄ2Ｏ放電（2.45GHz，100Ｗ，20mTorr）310℃，30分→真空中降温
　本実施例で用いたＤ2Ｏ放電による選択還元は、放電により生成されたＤラジカルによる還元反応とＯＤラジカル及びＯラジカルによる酸化反応のバランスが材料によって異なる点をうまく使っている手法である。このラジカル雰囲気下での酸化還元のバランスの大小関係は、第１の実施例で述べたΔＧの大小関係と一致している。このため、同じ考え方で記述すると、ΔＧＭがΔＧＩ以上の値を持つ温度範囲でＤ原子とＯ原子の両者を含むラジカル雰囲気にセル構造を曝露することがポイントであり、上記放電条件に限ることなく適宜変化させることが可能である。 Temperature rise in vacuum → D 2 O discharge (2.45 GHz, 100 W, 20 mTorr) 310 ° C., 30 minutes → temperature drop in vacuum The selective reduction by D 2 O discharge used in this example is reduction by D radicals generated by discharge This is a technique that makes good use of the difference between the reaction and the oxidation reaction by the OD radical and O radical depending on the material. The magnitude relation of the balance of redox under the radical atmosphere is in agreement with the magnitude relation of ΔG described in the first embodiment. For this reason, if described in the same way, the point is that the cell structure is exposed to a radical atmosphere containing both D atoms and O atoms in a temperature range in which ΔGM has a value greater than or equal to ΔGI. It is possible to change appropriately.
　ここでＤ2Ｏの放電条件は、水分圧１～２００ｍＴｏｒｒ、印加電力１０～５００Ｗが好ましく、基板温度として室温から７００度の範囲において有効である。更に好ましくは、水分圧１０～１００ｍＴｏｒｒ、１０～５０ｍＴｏｒｒ、更には２０～３０ｍＴｏｒｒが良い。また、印加電力１００Ｗ以上、基板温度室温から５００度の範囲において、より良好な結果が得られる。さらにまた、放電方法はマイクロ波によるもの以外に、ＲＦを用いた並行平板型によるもの、磁石や電磁石を用いたマグネトロン型のもの、或いはヘリコン波を用いたもの等がある。 Here, the D 2 O discharge conditions are preferably a water pressure of 1 to 200 mTorr and an applied power of 10 to 500 W, and the substrate temperature is effective in the range of room temperature to 700 degrees. More preferably, the water pressure is 10 to 100 mTorr, 10 to 50 mTorr, and further 20 to 30 mTorr. In addition, a better result is obtained when the applied power is 100 W or more and the substrate temperature is in the range of room temperature to 500 degrees. In addition to the microwave discharge method, there are a parallel plate type using RF, a magnetron type using a magnet or an electromagnet, or a helicon wave.
　また、前記ラジカル雰囲気はＤ2 及びＯ2 、Ｄ2 及びＤ2Ｏ、Ｄ2 及びＮＯ、Ｄ2 及びＮ2Ｏなどの混合ガスの放電若しくはそれぞれを独立に放電しても同様の効果を得ることができる。更に第１の実施例と異なりラジカルを用いることで低温プロセスが可能となっており、Ｗ，Ｇｅ等の汚染を完全に無視することができる。 Further, the radical atmosphere can obtain the same effect even when the mixed gas such as D 2 and O 2 , D 2 and D 2 O, D 2 and NO, D 2 and N 2 O is discharged or independently. be able to. Further, unlike the first embodiment, the use of radicals enables a low-temperature process, and contamination such as W and Ge can be completely ignored.
　前記Ｄ2Ｏ放電による選択酸化条件は、Ｈ2Ｏ放電においても同様の効果を得ることができる。但し、Ｄ2Ｏ放電において、周辺材料に取り込まれたＤ原子はＨ原子と異なり質量数の違いから膜中の拡散速度が遅いため、Ｈ原子に比べて新たな欠陥を形成することが少ない。即ち、Ｄ原子を含むセル構造の電気的信頼性は高くなる。 The selective oxidation condition by the D 2 O discharge can obtain the same effect also in the H 2 O discharge. However, in the D 2 O discharge, unlike the H atom, the D atom taken into the peripheral material has a low diffusion rate in the film due to the difference in mass number, so that new defects are less formed than the H atom. That is, the electrical reliability of the cell structure containing D atoms is increased.
　本実施例では、Ｄ原子とＯ原子の両者を含むラジカル雰囲気の場合について述べたが、各種希ガス（Ｈｅ，Ｎｅ，Ａｒ，Ｋｒ，Ｘｅなど）を添加しても同様若しくはそれ以上の効果を得ることができる。例えば、Ｋｒを添加した場合は活性なＯ１Ｄラジカルの励起が促進されるために非オーミック素子側面の加工ダメージ（欠陥）を効率的に修復することができ、プロセスの目的に応じて希釈ガスを選択するのが好ましいと言える。 In the present embodiment, the case of a radical atmosphere containing both D atoms and O atoms has been described. However, even if various rare gases (He, Ne, Ar, Kr, Xe, etc.) are added, the same effect or more can be obtained. Obtainable. For example, when Kr is added, excitation of active O1D radicals is promoted, so that processing damage (defects) on the side surfaces of non-ohmic elements can be repaired efficiently, and a dilution gas can be selected according to the purpose of the process. It can be said that this is preferable.
　（第３の実施例）
　本発明の第３の実施例について、第１の実施例と同じく非オーミック素子の側面の選択酸化を考える。前記図９の説明でも述べたようにクロスポイントメモリ作成工程では、メタル配線を酸化することなく非オーミック素子側面の加工ダメージのみ酸化修復する選択酸化が必須となる。そこで、水素／酸素の混合ガスを放電した雰囲気にて加熱を行うことにより、Ｗ層を酸化することなくＳｉ層を酸化して、前記図１０（ｂ）のセル構造が完成する。この時の放電条件を以下に記す。 (Third embodiment)
As for the third embodiment of the present invention, the selective oxidation of the side surface of the non-ohmic element is considered as in the first embodiment. As described in the description of FIG. 9, in the cross-point memory creation process, selective oxidation that oxidizes and repairs only the processing damage on the side surface of the non-ohmic element is indispensable without oxidizing the metal wiring. Therefore, by heating in an atmosphere in which a mixed gas of hydrogen / oxygen is discharged, the Si layer is oxidized without oxidizing the W layer, and the cell structure shown in FIG. 10B is completed. The discharge conditions at this time are described below.
　真空中昇温→Ｈ2／Ｏ2 放電（2.45GHz，100Ｗ，Ｈ2／Ｏ2 分圧比５０、
　　　　　　　全圧２０mTorr）３１０℃，３０分→真空中降温
　本実施例で用いた水素／酸素放電による選択還元は、放電により生成されたＨラジカルによる還元反応とＯラジカル及び気相反応で形成されたＯＨラジカルによる酸化反応のバランスが材料によって異なる点をうまく使っている手法である。このラジカル雰囲気下での酸化還元のバランスの大小関係は、第２の実施例で述べたΔＧの大小関係と一致している。このため、同じ考え方で記述すると、ΔＧＭがΔＧＩ以上の値を持つ温度範囲でＨ原子とＯ原子の両者を含むラジカル雰囲気にセル構造を曝露することがポイントであり、上記放電条件に限ることなく適宜変化させることが可能である。 Temperature rise in vacuum → H 2 / O 2 discharge (2.45 GHz, 100 W, H 2 / O 2 partial pressure ratio 50,
(Total pressure 20 mTorr) 310 ° C., 30 minutes → temperature drop in vacuum The selective reduction by the hydrogen / oxygen discharge used in this example is the reduction reaction by the H radical generated by the discharge and the OH formed by the O radical and the gas phase reaction. This is a technique that makes good use of the difference in the balance of oxidation reaction by radicals depending on the material. The magnitude relation of the balance of redox under the radical atmosphere coincides with the magnitude relation of ΔG described in the second embodiment. For this reason, if it is described in the same way of thinking, the point is that the cell structure is exposed to a radical atmosphere containing both H atoms and O atoms in a temperature range in which ΔGM has a value equal to or greater than ΔGI. It is possible to change appropriately.
　ここで、Ｈ2 ／Ｏ2 の放電条件は、Ｈ2 ／Ｏ2 分圧比１～１００００、全圧１～２００ｍＴｏｒｒ、印加電力１０～５００Ｗが好ましく、基板温度として室温から７００度の範囲において有効である。更に好ましくは、Ｈ2 ／Ｏ2 分圧比１～１０００、１～１００、全圧１０～１００ｍＴｏｒｒ、１０～５０ｍＴｏｒｒ、更には２０～３０ｍＴｏｒｒが良い。また、印加電力１００Ｗ以上、基板温度室温から５００度の範囲において、より良好な結果が得られる。さらにまた、放電方法はマイクロ波によるもの以外に、ＲＦを用いた並行平板型によるもの、磁石や電磁石を用いたマグネトロン型のもの、或いはヘリコン波を用いたもの等がある。 Here, the H 2 / O 2 discharge conditions are preferably a H 2 / O 2 partial pressure ratio of 1 to 10000, a total pressure of 1 to 200 mTorr, and an applied power of 10 to 500 W, and the substrate temperature is effective in the range of room temperature to 700 degrees. is there. More preferably, the H 2 / O 2 partial pressure ratio is 1 to 1000, 1 to 100, the total pressure is 10 to 100 mTorr, 10 to 50 mTorr, and further 20 to 30 mTorr. In addition, a better result is obtained when the applied power is 100 W or more and the substrate temperature is in the range of room temperature to 500 degrees. In addition to the microwave discharge method, there are a parallel plate type using RF, a magnetron type using a magnet or an electromagnet, or a helicon wave.
　また、前記ラジカル雰囲気はＨ2Ｏ、Ｈ2 及びＨ2Ｏ、Ｈ2 及びＮＯ、Ｈ2 及びＮ2Ｏなどの混合ガスの放電若しくはそれぞれを独立に放電しても同様の効果を得ることができる。更に第１の実施例と異なりラジカルを用いることで低温プロセスが可能となっており、Ｗ，Ｇｅ等の汚染を完全に無視することができる。 In addition, the radical atmosphere can obtain the same effect even if discharge of a mixed gas such as H 2 O, H 2 and H 2 O, H 2 and NO, H 2 and N 2 O, or discharge each independently. it can. Further, unlike the first embodiment, the use of radicals enables a low-temperature process, and contamination such as W and Ge can be completely ignored.
　本実施例ではＨ原子とＯ原子の両者を含むラジカル雰囲気の場合について述べたが、各種希ガス（Ｈｅ，Ｎｅ，Ａｒ，Ｋｒ，Ｘｅなど）を添加しても同様若しくはそれ以上の効果を得ることができる。例えばＫｒを添加した場合は活性なＯ１Ｄラジカルの励起が促進されるために非オーミック素子側面の加工ダメージ（欠陥）を効率的に修復することができ、プロセスの目的に応じて希釈ガスを選択するのが好ましいと言える。 In the present embodiment, the case of a radical atmosphere containing both H atoms and O atoms has been described, but the same or more effects can be obtained even if various rare gases (He, Ne, Ar, Kr, Xe, etc.) are added. be able to. For example, when Kr is added, excitation of active O1D radicals is promoted, so that processing damage (defects) on the side surface of the non-ohmic element can be repaired efficiently, and a dilution gas is selected according to the purpose of the process. It can be said that it is preferable.
　本実施例では活性なＨラジカル、Ｏラジカル及びＯＨラジカルなどで処理することで可変抵抗素子中のＶａｃａｎｃｙをＯ原子で終端し、安定動作させることもできる。またＨ原子による界面準位等の欠陥終端効果もあり、ダイオード特性の高信頼化にもつながる。 In this embodiment, by treating with active H radical, O radical, OH radical, etc., the vacancy in the variable resistance element can be terminated with O atoms, and stable operation can be achieved. In addition, there is a defect termination effect such as interface states due to H atoms, leading to high reliability of diode characteristics.
　これらラジカルによる酸化還元効果は、側面からＨ，Ｏ原子がセル内部に拡散することでセル構成材料のバルク、界面特性を改善することも可能である。特に、セル幅が２０ｎｍ以下では十分内部まで拡散できることから、セル構成材料中のＨ，Ｏ原子の両者が１×１０18ｃｍ-3以上存在することで、各種熱工程における界面の酸化還元反応及び欠陥生成を抑制することも可能である。 The oxidation-reduction effect by these radicals can improve the bulk and interface characteristics of the cell constituent material by diffusing H and O atoms into the cell from the side. In particular, if the cell width is 20 nm or less, the cell can be sufficiently diffused to the inside. Therefore, the presence of both H and O atoms in the cell constituent material is 1 × 10 18 cm −3 or more. It is also possible to suppress defect generation.
　本実施例ではＨ2 ／Ｏ2 混合ガス放電の場合について述べたが、Ｎ2 ガスを添加しても同様若しくはそれ以上の効果を得ることができる。例えばＨ2 ／Ｏ2 ／Ｎ2 放電によりＮラジカルの励起も促進されるためにＷ配線を酸化することなく導電性ＷＮ膜を形成することも可能であり、効率的に不純物の拡散防止もできる金属窒化膜電極を形成できる。 In the present embodiment, the case of H 2 / O 2 mixed gas discharge has been described, but the same or more effect can be obtained even if N 2 gas is added. For example, since excitation of N radicals is promoted by H 2 / O 2 / N 2 discharge, it is possible to form a conductive WN film without oxidizing the W wiring, and to effectively prevent the diffusion of impurities. A metal nitride film electrode can be formed.
　前記Ｈ2 ／Ｏ2 放電による選択酸化条件は、Ｄ2 ／Ｏ2 放電においても同様の効果を得ることができる。更にＤ2 を用いた場合では、周辺材料に取り込まれたＤ原子はＨ原子と異なり質量数の違いから膜中の拡散速度が遅いため、Ｈ原子に比べて新たな欠陥を形成することが少ない。即ちＤ原子を含むセル構造の電気的信頼性は高くなる。 The selective oxidation condition by the H 2 / O 2 discharge can obtain the same effect in the D 2 / O 2 discharge. Furthermore, when D 2 is used, D atoms taken into the peripheral material have a lower diffusion rate in the film due to the difference in mass number, unlike H atoms, so that new defects are less formed than H atoms. . That is, the electrical reliability of the cell structure containing D atoms is increased.
　また、ラジカルを用いた選択酸化は面方位依存性が少ないため、セル側面の面方位はどれを用いても同様の効果を得ることができる。 In addition, since selective oxidation using radicals has little dependence on the plane orientation, the same effect can be obtained regardless of which plane orientation is used on the side surface of the cell.
　（変形例）
　なお、本発明は上述した各実施例に限定されるものではない。実施例では、基板側から順に非オーミック素子，可変抵抗素子の順に積層したが、これらの積層順序は逆にしても良い。また、非オーミック素子としてのＭＩＭ構造のメタルとしてＳｉを用いることも可能である。この場合も、非オーミック素子層をラインアンドスペースのパターンのエッチング加工した後に、配線層としてのメタル層を酸化することなしに、非オーミック素子層の側面を選択的に酸化することができる。 (Modification)
In addition, this invention is not limited to each Example mentioned above. In the embodiment, the non-ohmic element and the variable resistance element are stacked in this order from the substrate side, but the stacking order may be reversed. It is also possible to use Si as a metal having an MIM structure as a non-ohmic element. Also in this case, the side surface of the non-ohmic element layer can be selectively oxidized without oxidizing the metal layer as the wiring layer after the non-ohmic element layer is etched with a line-and-space pattern.
　その他、本発明の要旨を逸脱しない範囲で、種々変形して実施することができる。 Other various modifications can be made without departing from the scope of the present invention.
　現在のＮＡＮＤ型フラッシュメモリ記録密度の限界を大幅に超える、新規固体メモリとしての小型大容量不揮発性メモリを実現することができ、将来のユビキタス社会の実現に向けた小型携帯機器の普及に寄与する。 It is possible to realize a small-sized large-capacity nonvolatile memory as a new solid-state memory that greatly exceeds the limit of the current NAND-type flash memory recording density, and contributes to the popularization of small portable devices for the realization of a ubiquitous society in the future .

Claims (11)

  1. 　第１の絶縁膜上に、第１の配線層となる第１のメタル層を形成する工程と、
    　前記第１のメタル層上に、メモリセルとなる可変抵抗素子層と非オーミック素子層を積層形成する工程と、
    　前記第１のメタル層，可変抵抗素子層，及び非オーミック素子層からなる第１の堆積層を選択的にエッチングすることにより、第１のラインアンドスペースのパターンを形成する工程と、
    　前記第１のラインアンドスペースのパターンの形成でスペース部分に露出した前記非オーミック素子層の側面を選択的に酸化する第１の酸化工程と、
    　前記第１の酸化工程の後に、前記第１のラインアンドスペースのパターンのスペース部分に第２の絶縁膜を埋め込み形成する工程と、
    　前記第１の堆積層及び前記第２の絶縁膜上に、第２の配線層となる第２のメタル層を形成する工程と、
    　前記可変抵抗素子層，非オーミック素子層，第２の絶縁膜，及び第２のメタル層からなる第２の堆積層を選択的にエッチングすることにより、前記第１のラインアンドスペースとは交差する方向の第２のラインアンドスペースのパターンを形成する工程と、
    　前記第２のラインアンドスペースのパターンの形成でスペース部分に露出した前記非オーミック素子層の側面を選択的に酸化する第２の酸化工程と、
    　前記第２の酸化工程の後に、前記第２のラインアンドスペースのパターンのスペース部分に第３の絶縁膜を埋め込み形成する工程と、
    　を含むことを特徴とする不揮発性半導体記憶装置の製造方法。     Forming a first metal layer serving as a first wiring layer on the first insulating film;
    Forming a variable resistance element layer to be a memory cell and a non-ohmic element layer on the first metal layer;
    Forming a first line-and-space pattern by selectively etching the first deposited layer comprising the first metal layer, the variable resistance element layer, and the non-ohmic element layer;
    A first oxidation step of selectively oxidizing a side surface of the non-ohmic element layer exposed in a space portion by forming the first line and space pattern;
    A step of embedding and forming a second insulating film in a space portion of the first line-and-space pattern after the first oxidation step;
    Forming a second metal layer serving as a second wiring layer on the first deposited layer and the second insulating film;
    The first line and space intersects by selectively etching the second deposited layer comprising the variable resistance element layer, the non-ohmic element layer, the second insulating film, and the second metal layer. Forming a second line and space pattern of directions;
    A second oxidation step of selectively oxidizing a side surface of the non-ohmic element layer exposed in a space portion by forming the second line and space pattern;
    A step of embedding and forming a third insulating film in a space portion of the second line and space pattern after the second oxidation step;
    A method for manufacturing a nonvolatile semiconductor memory device, comprising:
  2. 　前記第１の絶縁膜は、表面部に前記メモリセルの制御回路が形成された半導体基板上を覆うように形成されていることを特徴とする請求項１記載の不揮発性半導体記憶装置の製造方法。 2. The method for manufacturing a nonvolatile semiconductor memory device according to claim 1, wherein the first insulating film is formed so as to cover a semiconductor substrate having a control circuit for the memory cell formed on a surface portion. .
  3. 　前記第１及び第２の酸化工程として、前記非オーミック素子層を酸化し、前記メタル層を還元する雰囲気下で熱処理することを特徴とする請求項１記載の不揮発性半導体記憶装置の製造方法。 2. The method of manufacturing a nonvolatile semiconductor memory device according to claim 1, wherein, as the first and second oxidation steps, heat treatment is performed in an atmosphere in which the non-ohmic element layer is oxidized and the metal layer is reduced.
  4. 　前記第１及び第２の酸化工程として、水素及び水蒸気、又は重水素及び重水蒸気を含む雰囲気下での熱処理を行うことを特徴とする請求項３記載の不揮発性半導体記憶装置の製造方法。 4. The method of manufacturing a nonvolatile semiconductor memory device according to claim 3, wherein, as the first and second oxidation steps, heat treatment is performed in an atmosphere containing hydrogen and water vapor, or deuterium and heavy water vapor.
  5. 　前記第１及び第２の酸化工程として、水素及び水蒸気を含む雰囲気下での熱処理を行い、該熱処理時における温度を７００℃以下、水素と水蒸気との分圧比Ｐ（Ｈ2）／Ｐ（Ｈ2Ｏ）を６桁以下に設定したことを特徴とする請求項３記載の不揮発性半導体記憶装置の製造方法。 As the first and second oxidation steps, heat treatment is performed in an atmosphere containing hydrogen and water vapor, the temperature during the heat treatment is 700 ° C. or less, and the partial pressure ratio P (H 2 ) / P (H method of manufacturing a nonvolatile semiconductor memory device according to claim 3, wherein 2 O) that was set to 6 digits.
  6. 　前記第１及び第２の酸化工程として、水素及び酸素、又は重水素及び酸素を含むガスのプラズマ若しくはラジカルによる処理を行うことを特徴とする請求項３記載の不揮発性半導体記憶装置の製造方法。 4. The method of manufacturing a nonvolatile semiconductor memory device according to claim 3, wherein as the first and second oxidation steps, treatment with plasma or radicals of gas containing hydrogen and oxygen or deuterium and oxygen is performed.
  7. 　前記プラズマ又はラジカルによる処理を、水蒸気若しくはＤ2Ｏ蒸気を含むガス雰囲気下で行うことを特徴とする請求項６記載の不揮発性半導体記憶装置の製造方法。 7. The method for manufacturing a nonvolatile semiconductor memory device according to claim 6, wherein the plasma or radical treatment is performed in a gas atmosphere containing water vapor or D 2 O vapor.
  8. 　前記非オーミック素子層として、ｐｎ接合，ｐｉｎ接合，又はショットキー接合のダイオードを用いることを特徴とする請求項１に記載の不揮発性半導体記憶装置の製造方法。 2. The method of manufacturing a nonvolatile semiconductor memory device according to claim 1, wherein a diode of a pn junction, a pin junction, or a Schottky junction is used as the non-ohmic element layer.
  9. 　前記非オーミック素子層を構成する原子の酸化物生成の自由エネルギー（Gibbs Free Energy）は、前記選択酸化時の温度範囲で前記メタル層を構成する原子の酸化物生成の自由エネルギー以下であることを特徴とする請求項１記載の不揮発性半導体記憶装置の製造方法。 The free energy (Gibbs Free Energy) for generating an oxide of atoms constituting the non-ohmic element layer is equal to or less than the free energy for forming an oxide of atoms constituting the metal layer in the temperature range during the selective oxidation. The method for manufacturing a nonvolatile semiconductor memory device according to claim 1, wherein:
  10. 　前記第２の絶縁膜を埋め込み形成する工程として、前記スペース部分を埋め込むように前記第１の堆積層上に第２の絶縁膜を形成した後に、前記第１の堆積層が露出するまで前記第２の絶縁膜をＣＭＰ法により研磨することを特徴とする請求項１記載の不揮発性半導体記憶装置の製造方法。 As the step of burying and forming the second insulating film, the second insulating film is formed on the first deposited layer so as to fill the space portion, and then the first deposited layer is exposed until the first deposited layer is exposed. 2. The method of manufacturing a nonvolatile semiconductor memory device according to claim 1, wherein the insulating film is polished by a CMP method.
  11. 　前記第３の絶縁膜を埋め込み形成する工程として、前記スペース部分を埋め込むように前記第２の堆積層上に第３の絶縁膜を形成した後に、前記第２の堆積層が露出するまで前記第３の絶縁膜をＣＭＰ法により研磨することを特徴とする請求項１記載の不揮発性半導体記憶装置の製造方法。 As the step of embedding and forming the third insulating film, the third insulating film is formed on the second deposited layer so as to embed the space portion, and then the first deposited layer is exposed until the second deposited layer is exposed. 3. The method of manufacturing a nonvolatile semiconductor memory device according to claim 1, wherein the insulating film is polished by a CMP method.
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012195530A (en) * 2011-03-18 2012-10-11 Toshiba Corp Nonvolatile semiconductor memory device and method of manufacturing nonvolatile semiconductor memory device
US8559216B2 (en) 2010-01-28 2013-10-15 Kabushiki Kaisha Toshbia Nonvolatile semiconductor memory device
US8575590B2 (en) 2008-09-02 2013-11-05 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0794716A (en) * 1993-09-22 1995-04-07 Toshiba Corp Manufacture of semiconductor device
JP2004526327A (en) * 2001-04-26 2004-08-26 インフィネオン テクノロジーズ アクチエンゲゼルシャフト Method for minimizing tungsten oxide deposition during selective sidewall oxidation of a tungsten-silicon gate
WO2005081302A1 (en) * 2004-02-19 2005-09-01 Tokyo Electron Limited Method for cleaning treatment chamber in substrate treating apparatus and method for detecting endpoint of cleaning
WO2008068992A1 (en) * 2006-12-08 2008-06-12 Sharp Kabushiki Kaisha Nonvolatile semiconductor storage device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0794716A (en) * 1993-09-22 1995-04-07 Toshiba Corp Manufacture of semiconductor device
JP2004526327A (en) * 2001-04-26 2004-08-26 インフィネオン テクノロジーズ アクチエンゲゼルシャフト Method for minimizing tungsten oxide deposition during selective sidewall oxidation of a tungsten-silicon gate
WO2005081302A1 (en) * 2004-02-19 2005-09-01 Tokyo Electron Limited Method for cleaning treatment chamber in substrate treating apparatus and method for detecting endpoint of cleaning
WO2008068992A1 (en) * 2006-12-08 2008-06-12 Sharp Kabushiki Kaisha Nonvolatile semiconductor storage device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8575590B2 (en) 2008-09-02 2013-11-05 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device
US8559216B2 (en) 2010-01-28 2013-10-15 Kabushiki Kaisha Toshbia Nonvolatile semiconductor memory device
JP2012195530A (en) * 2011-03-18 2012-10-11 Toshiba Corp Nonvolatile semiconductor memory device and method of manufacturing nonvolatile semiconductor memory device
US8766226B2 (en) 2011-03-18 2014-07-01 Kabushiki Kaisha Toshiba Non-volatile semiconductor storage device and manufacturing method of non-volatile semiconductor storage device

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