WO2010016301A1 - Phase comparator, pll circuit, and dll circuit - Google Patents
Phase comparator, pll circuit, and dll circuit Download PDFInfo
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- WO2010016301A1 WO2010016301A1 PCT/JP2009/057864 JP2009057864W WO2010016301A1 WO 2010016301 A1 WO2010016301 A1 WO 2010016301A1 JP 2009057864 W JP2009057864 W JP 2009057864W WO 2010016301 A1 WO2010016301 A1 WO 2010016301A1
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- 238000010586 diagram Methods 0.000 description 45
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- 238000006243 chemical reaction Methods 0.000 description 9
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- 238000004260 weight control Methods 0.000 description 8
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
- H03K5/26—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being duration, interval, position, frequency, or sequence
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
- H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
Definitions
- the present invention relates to a digital phase comparator, a PLL circuit, and a DLL circuit, and more particularly, to a digital type phase comparator, a PLL circuit, and a DLL circuit that determine a phase difference between two input signals.
- Clock generation circuits such as phase-locked loop circuit (Phase-Locked Loop: PLL), delay-locked loop circuit (Delay-Locked Loop: DLL), and clock data recovery circuit (Clock and Data Recovery: CDR) have a phase comparator. is doing.
- the clock signal can be synchronized with the reference signal by performing feedback control based on the signal output from the phase comparator.
- the phase comparator determines the phase relationship (phase advance or delay) of two input signals and the phase difference (phase advance or delay magnitude) between the two input signals. Note that the phase comparator, when used in the clock generation circuit, determines the phase relationship and phase difference between the clock signal generated by the clock generation circuit and the reference signal (reference clock signal or reference data signal).
- phase comparators are classified into analog type and digital type.
- the analog phase comparator is used in an analog clock generation circuit, and the digital phase comparator is used in a digital clock generation circuit.
- Analog phase comparator outputs the phase difference between two input signals as a physical quantity such as voltage, current or pulse width.
- a charge pump circuit In an analog clock generation circuit using an analog phase comparator, a charge pump circuit, a filter circuit, and an oscillator are configured by analog circuits.
- analog circuits In these analog circuits, it is difficult to design, miniaturize, and change loop parameters for feedback control. For this reason, in recent years, digital type clock generation circuits are often used, and accordingly, the demand for digital type phase comparators is also increasing.
- the digital type phase comparator has a binary type that can determine only the phase relationship between two input signals and a multi-bit type that can determine not only the phase relationship between two input signals but also the phase difference between them. .
- the binary phase comparator outputs a 2-bit digital signal indicating the phase relationship between the two signals.
- the multi-bit type phase comparator outputs a multi-bit digital signal indicating the phase difference between the two signals.
- the feedback loop gain is low, and when the phase difference is small, the feedback loop gain is high. Therefore, when the phase difference is large, the gain is low, so that the convergence of the phase difference in the feedback loop is slow, and when the phase difference is small, the gain is high and the stability of the feedback loop is not ensured. This causes problems such as jitter in the clock signal.
- N flip-flop circuits In order to discriminate the phase difference with N stages of resolution using a multi-bit type phase comparator, at least N flip-flop circuits, N delay circuits, and an N-bit thermometer code are log2N. An encoder that converts to a binary bit code is required.
- Patent Document 1 describes a timing adjuster that can suppress an increase in power consumption and circuit area of a clock generation circuit.
- This timing adjustment circuit includes a delay adjustment circuit and three latch circuits, and operates as follows.
- the delay adjustment circuit generates the first clock signal by delaying the timing signal.
- the first latch circuit latches the data signal based on the first clock signal.
- the second latch circuit latches the data signal based on the second clock signal obtained by delaying the first clock signal by the first delay time.
- the third latch circuit latches the data signal based on the third clock signal obtained by delaying the first clock signal by a second delay time longer than the first delay time.
- the timing adjustment circuit adjusts the delay time of the timing signal by the delay adjustment circuit so that the signals output from the first to third latch circuits are all equal.
- this timing adjuster is provided in front of the binary phase comparator of the clock generation circuit, the phase difference between the clock signal and the reference signal is reduced, so that the convergence of the feedback loop is delayed even with a constant feedback amount. It is possible to solve problems such as problems and the stability of the feedback loop not being ensured. In addition, since the number of circuits can be suppressed, the power consumption and circuit area of the clock generation circuit can be suppressed.
- the timing adjustment circuit described in Patent Document 1 has a problem that the phase difference cannot be determined, although the timing of two signals can be adjusted while suppressing an increase in power consumption and circuit area. For this reason, for example, in the clock generation circuit, it is necessary to use a phase comparator separately from the timing adjustment circuit. For this reason, the stability of the feedback loop may not be ensured until the apparatus configuration becomes complicated or the timing adjustment is completed.
- An object of the present invention is to provide a phase comparator, a PLL circuit, and a DLL circuit that solve the above-described problem that a phase difference cannot be determined while suppressing an increase in power consumption and circuit area. It is.
- the phase comparator includes a first input unit to which a first input signal is input, a second input unit to which a second input signal is input, and a second input signal input to the second input unit.
- An adjustment unit that adjusts the phase to generate an adjustment input signal; and a front-rear relationship between the phase of the first input signal input to the first input unit and the phase of the adjustment input signal generated by the adjustment unit And adjusting the adjustment amount of the adjusting means so that the determination means for outputting the determination result indicating the context and the context indicated by the determination result output from the determination means are changed.
- Control means for determining a weight value to be given to the discrimination result according to an adjustment amount, weighting means for giving the weight value decided by the control means to the discrimination result output from the discrimination means, and the weighting means The weight given the weight value
- An output means for outputting the result as an error signal indicating the phase relationship between the phase of the first input signal and the phase of the second input signal and the phase difference between the first input signal and the second input signal; including.
- the PLL circuit includes a filter unit that smoothes the error signal output from the phase comparator, and oscillates at a frequency corresponding to the error signal smoothed by the filter unit.
- Oscillating means for inputting the signal to the phase comparator as the first input signal or the second input signal.
- the phase comparator In the DLL circuit according to the present invention, the phase comparator, a clock input means to which a clock signal is input, a filter means for smoothing an error signal output from the phase comparator, and the filter means are smoothed.
- Control delay means for delaying the clock signal input to the clock input means in accordance with the error signal and inputting the delayed clock signal to the phase comparator as the first input signal or the second input signal. And including.
- FIG. 1 is a circuit diagram showing the configuration of the phase comparator according to the first embodiment of the present invention.
- the phase comparator includes input terminals 1 and 2, a variable delay circuit 3, a binary phase comparator 4, a weighting circuit having multipliers 5 and 6, and an output unit having output terminals 7 and 8. And a control logic circuit 9.
- the signal ⁇ 1 is input to the input terminal 1, and the input signal ⁇ 1 is output.
- a signal ⁇ 2 is input to the input terminal 2, and the input signal ⁇ 2 is output.
- Signals ⁇ 1 and ⁇ 2 are clock signals.
- the input terminal 1 is an example of a first input means, and the signal ⁇ 1 is an example of a first input signal.
- the input terminal 2 is an example of a second input means, and the signal ⁇ 2 is an example of a second input signal.
- the variable delay circuit 3 is an example of adjusting means.
- An input terminal 2 is connected to an input terminal of the variable delay circuit 3 and a signal ⁇ 2 is input.
- the delay control signal DLY is input from the control logic circuit 9 to the control terminal of the variable delay circuit 3.
- the value of the delay control signal DLY indicates the delay amount of the variable delay circuit 3.
- the delay control signal DLY is a multi-bit signal.
- the delay amount is an example of an adjustment amount.
- the delay amount may be a positive value, 0, or a negative value.
- the variable delay circuit 3 adjusts the phase of the signal ⁇ 2 by delaying the signal ⁇ 2 by the delay amount indicated by the delay control signal DLY, and generates the delay signal ⁇ 2 ′. Specifically, the variable delay circuit 3 delays the phase of the signal ⁇ 2 by the delay amount when the delay amount is positive, and advances the phase of the signal ⁇ 2 by the absolute value of the delay amount when the delay amount is negative. . Note that the delay signal ⁇ 2 'is an example of an adjustment input signal.
- variable delay circuit 3 outputs the generated delay signal ⁇ 2 'from its own output terminal.
- the binary phase comparator 4 is an example of a discrimination unit.
- the input terminal 1 is connected to the first input terminal of the binary phase comparator 4 and the signal ⁇ 1 is input. Further, the output terminal of the variable delay circuit 3 is connected to the second input terminal of the binary type phase comparator 4, and the delay signal ⁇ 2 'is input thereto.
- the binary type phase comparator 4 compares the phase of the input signal ⁇ 1 with the phase of the delay signal ⁇ 2 'to determine the front-to-back relationship between the phase of the signal ⁇ 1 and the phase of the delay signal ⁇ 2'. Specifically, the binary phase comparator 4 compares the timing relationship between the timing of the edge of the signal ⁇ 1 and the timing of the edge of the delay signal ⁇ 2 ′, and determines the timing relationship between the timing and the phase of the signal ⁇ 1. This is determined as the context of the phase of the delay signal ⁇ 2 ′.
- the binary phase comparator 4 outputs a discrimination result indicating the phase relationship of the phase as an Early signal and a Late signal. Specifically, the binary phase comparator 4 outputs an Early signal from its own first output terminal and outputs a Late signal from its own second output terminal. Each of the Early signal and the Late signal is a 1-bit binary value.
- the H level Early signal indicates that the phase of the signal ⁇ 1 is ahead of the phase of the delay signal ⁇ 2 ′
- the H level Late signal indicates that the phase of the signal ⁇ 1 is behind the phase of the delay signal ⁇ 2 ′.
- FIG. 2A is a circuit diagram showing a configuration example of the binary phase comparator 4.
- binary type phase comparator 4 includes input terminals 4a and 4b, flip-flop circuits 4c and 4d, and output terminals 4e and 4f.
- the signal ⁇ 1 is input to the input terminal 4a, and the input signal ⁇ 1 is output.
- the delay signal ⁇ 2 ' is input to the input terminal 4b, and the input delay signal ⁇ 2' is output.
- the input terminal 4a is connected to the D input terminal of the flip-flop circuit 4c, and the signal ⁇ 1 is input. Further, the input terminal 4b is connected to the CK input terminal of the flip-flop circuit 4c, and the delay signal ⁇ 2 'is input thereto.
- the flip-flop circuit 4c holds the input signal ⁇ 1 at the edge timing of the input delay signal ⁇ 2 ', and outputs the held signal ⁇ 1 as an Early signal from its own Q terminal.
- the edge may be a rising edge or a falling edge. In the following, all edges are rising edges.
- the input terminal 4b is connected to the D input terminal of the flip-flop circuit 4d, and the delay signal ⁇ 2 'is input.
- the input terminal 4a is connected to the CK input terminal of the flip-flop circuit 4d, and the signal ⁇ 1 is input.
- the flip-flop circuit 4d holds the delay signal ⁇ 2 'at the edge timing of the signal ⁇ 1, and outputs the held delay signal ⁇ 2' from its Q terminal as a Late signal.
- the Q terminal of the flip-flop circuit 4c is connected to the output terminal 4e, and the Early signal is input.
- the output terminal 4e outputs the input Early signal.
- the Q terminal of the flip-flop circuit 4d is connected to the output terminal 4f, and the Late signal is input.
- the output terminal 4f outputs the input Late signal.
- the weighting circuit having the multipliers 5 and 6 assigns a weight value to the discrimination result output from the binary phase comparator 4, and the relationship between the phase of the signal ⁇ 1 and the phase of the signal ⁇ 2, and the signals ⁇ 1 and ⁇ 2. An error signal indicating the phase difference between the two is generated.
- the first output terminal of the binary phase comparator 4 is connected to the input terminal of the multiplier 5 and the Early signal is input.
- a weighting control signal ME is input from the control logic circuit 9 to the control terminal of the multiplier 5.
- the multiplier 5 multiplies the input Early signal by the value of the input weight control signal ME as a weight value to generate an Early ′ signal.
- the multiplier 5 outputs the generated Early 'signal from its own output terminal.
- the second output terminal of the binary phase comparator 4 is connected to the input terminal of the multiplier 6 and the Late signal is input.
- a weighting control signal ML is input from the control logic circuit 9 to the control terminal of the multiplier 6.
- the multiplier 6 multiplies the input Late signal by the value of the input weighting control signal ML as a weight value to generate a Late ′ signal.
- the multiplier 5 outputs the generated Late ′ signal from its own output terminal.
- the Early 'signal and the Late' signal are error signals.
- the value of the Early ′ signal or the Late ′ signal indicates the phase difference between the signals ⁇ 1 and ⁇ 2.
- the weighting control signals ME and ML are multi-bit signals. Therefore, the error signal is also a multi-bit signal.
- the weighting circuit multiplies the Early signal and the Late signal by the weight value, but the method of assigning the weight value to the Early signal and the Late signal is not limited to multiplication and can be changed as appropriate.
- the weighting circuit is a logic circuit such as an arithmetic circuit that performs arithmetic product or arithmetic addition, a logical product (AND) circuit, a negative logical product (NAND) circuit, a logical sum (OR) circuit, or a negative logical sum (NOR) circuit.
- a weight value is given to the determination result by using at least one of the circuits and using a circuit included in the weighting circuit.
- the output unit having the output terminals 7 and 8 outputs the error signal output from the weighting circuit. Specifically, the output terminal 7 is connected to the output terminal of the multiplier 5 and receives the Early signal. The output terminal 7 outputs the input Early signal. The output terminal 8 is connected to the output terminal of the multiplier 6 and receives the Late signal. The output terminal 8 outputs the input Late signal.
- the control logic circuit 9 is an example of a control means.
- the control logic circuit 9 inputs the delay control signal DLY to the control terminal of the variable delay circuit 3. Further, the control logic circuit 9 inputs the weighting control signal ME to the control terminal of the multiplier 5 and inputs the weighting control signal ML to the control terminal of the multiplier 6.
- the Early signal and the Late signal are input to the control logic circuit 9.
- the control logic circuit 9 adjusts the delay amount indicated by the delay control signal DLY based on the Early signal and the Late signal.
- control logic circuit 9 adjusts the delay amount to a value that changes the context indicated by the Early signal and the Late signal. At this time, the phases of the signal ⁇ 1 and the delay signal ⁇ 2 'are closest to each other, and the delay amount at that time represents the phase difference between the signals ⁇ 1 and ⁇ 2.
- the control logic circuit 9 gradually decreases the delay amount until the Early signal changes to L level.
- the control logic circuit 9 gradually increases the delay amount until the Late signal changes to the L level.
- control logic circuit 9 adjusts the values of the weighting control signals ME and ML according to the delay amount indicated by the delay control signal DLY. As a result, the control logic circuit 9 adjusts the weight value provided by the weighting circuit in accordance with the delay amount indicated by the delay control signal DLY.
- the control logic circuit 9 increases the value of the weighting control signal ML as the delay amount increases. Further, the control logic circuit 9 sets the value of the weighting control signal ME to 0.
- the control logic circuit 9 When the delay amount indicated by the delay control signal DLY is negative or 0, the control logic circuit 9 increases the value of the weight control signal ME as the absolute value of the delay amount increases. Further, the control logic circuit 9 sets the value of the weighting control signal ML to 0.
- FIG. 3 is an explanatory diagram for explaining an example of the operation of the phase comparator. Note that the control logic circuit 9 sets the values of the weighting control signals ME and ML to 1 when the delay amount indicated by the delay control signal DLY is set to 0.
- the control logic circuit 9 makes the delay amount indicated by the delay control signal DLY positive and the phase of the signal ⁇ 1 is delayed from the phase of the delay signal ⁇ 2 ′, the phase of the signal ⁇ 1 is greater than the phase of the signal ⁇ 2. It will be greatly delayed. In this case, the Late signal output from the binary phase comparator 4 becomes H level.
- the control logic circuit 9 makes the value of the weight control signal ML larger than 1 and increases the value of the Late ′ signal.
- the control logic circuit 9 increases the value of the weighting control signal ML as the delay amount increases.
- the control logic circuit 9 sets the weighting control signal ME to 0.
- the control logic circuit 9 makes the delay amount indicated by the delay control signal DLY smaller than 0, if the phase of the signal ⁇ 1 is ahead of the phase of the delay signal ⁇ 2 ′, the phase of the signal ⁇ 1 is the phase of the signal ⁇ 2. It ’s a lot more advanced. In this case, the Early signal output from the binary phase comparator 4 becomes H level.
- control logic circuit 9 increases the value of the early 'signal by increasing the value of the weighting control signal ME to be greater than 1.
- control logic circuit 9 increases the value of the weighting control signal ME as the absolute value of the delay amount increases.
- the control logic circuit 9 sets the weighting control signal ML to 0.
- the control logic circuit 9 performs such control, so that the Late ′ signal and the Early ′ signal indicate not only the phase relationship between the phase of the signal ⁇ 1 and the phase of the signal ⁇ 2 but also the phase difference between the signals ⁇ 1 and ⁇ 2. Obviously, the phase comparator can output an error signal indicating the phase difference between the signals ⁇ 1 and ⁇ 2.
- FIG. 4 is an explanatory diagram for comparing the operation of the binary phase comparator 4 alone and the operation of the phase comparator shown in FIG.
- the Early signal and the Late signal become L level or H level regardless of the magnitude of the phase difference between the signals ⁇ 1 and ⁇ 2.
- the phase comparator shown in FIG. 1 As the absolute value of the delay amount of the variable delay circuit 3 increases, the weight value given to the discrimination result increases, so that the phase difference between the signals ⁇ 1 and ⁇ 2 increases. The value of the Early ′ signal or the Late ′ signal is increased. Therefore, the Early ′ signal or the value of Late ′ indicates a phase difference.
- variable delay circuit 3 adjusts the phase of the signal ⁇ 2 to generate the delay signal ⁇ 2 '.
- the binary phase comparator 4 discriminates the anteroposterior relationship between the phase of the signal ⁇ 1 and the phase of the delay signal ⁇ 2 'and outputs a discrimination result indicating the anteroposterior relationship.
- the control logic circuit 9 adjusts the delay amount of the variable delay circuit 3 so that the context indicated by the determination result changes, and according to the adjusted delay amount, assigns a weight value to the determination result. decide.
- the weighting circuit gives the determined weight value to the determination result.
- the output unit outputs the determination result obtained by assigning the weight value by the weighting circuit as an error signal indicating the front-rear relationship between the phase of the signal ⁇ 1 and the phase of the signal ⁇ 2 and the phase difference between the signals ⁇ 1 and ⁇ 2.
- the delay amount of the variable delay circuit 3 is adjusted so that the context indicated by the determination result changes. Further, a weight value corresponding to the delay amount is given to the determination result. Since this delay amount represents the phase difference between signals ⁇ 1 and ⁇ 2, the determination result multiplied by the weight value indicates the phase difference between signals ⁇ 1 and ⁇ 2.
- the delay amount has only to be adjusted to N stages, so that it is not necessary to provide N flip-flop circuits or N delay circuits. Therefore, the number of circuits can be suppressed, so that power consumption and circuit area can be suppressed. Therefore, it is possible to determine the phase difference while suppressing increases in power consumption and circuit area.
- FIG. 5A is a circuit diagram showing the configuration of the phase comparator of the present embodiment.
- the phase comparator further includes an output control unit having logic gates 10 and 11 in addition to the configuration shown in FIG.
- a common signal is used for the weighting control signals ME and ML input to the control terminals of the multipliers 5 and 6.
- this common signal is referred to as a weighting control signal M.
- the output terminal of the multiplier 5 is connected to the first input terminal of the logic gate 10, and the Early 'signal is input.
- the enable signal ENE is input from the control logic circuit 9 to the second input terminal of the logic gate 10.
- the logic gate 10 sets the value of the Early 'signal to 0 when the level of the input enable signal ENE is a predetermined level.
- the predetermined level is determined according to the type of the logic gate 10.
- the output terminal of the multiplier 6 is connected to the first input terminal of the logic gate 11 and the Late ′ signal is input.
- the enable signal ENL is input from the control logic circuit 9 to the second input terminal of the logic gate 11.
- the logic gate 11 sets the value of the Late ′ signal to 0 when the level of the input enable signal ENL is a specific level.
- the specific level is determined according to the type of the logic gate 11.
- control logic circuit 9 adjusts the value of the weighting signal M according to the absolute value of the delay amount of the variable delay circuit 3. Specifically, the control logic circuit 9 increases the value of the weighting signal M as the absolute value of the delay amount of the variable delay circuit 3 increases.
- variable delay circuit 3 delays the phase of the signal ⁇ 2, that is, when the value of the delay control signal DLY is positive, even if the Early signal becomes H level, the signal It cannot be determined that the phase of ⁇ 1 is ahead of the phase of signal ⁇ 2.
- the control logic circuit 9 controls the logic gate 10 so that the value of the Early ′ signal output from the output terminal 7 becomes zero. Specifically, if the early signal is at the H level when the delay control signal DLY is a positive value, the control logic circuit 9 inputs the enable signal ENE of a predetermined level to the logic gate 10 and the logic gate 10 Causes the value of the Early ′ signal to be zero. For example, when the logic gate 10 is an AND circuit, the control logic circuit 9 inputs an L level enable signal ENE to the logic gate 10.
- variable delay circuit 3 advances the phase of the signal ⁇ 2, that is, when the value of the delay control signal DLY is negative, the phase of the signal ⁇ 1 is the same as that of the signal ⁇ 2 even if the Late signal becomes H level. It cannot be determined that it is behind the phase.
- the control logic circuit 9 controls the logic gate 11 so that the value of the Late ′ signal output from the output terminal 8 becomes zero. Specifically, when the Late control signal DLY is a negative value and the Late signal is at the H level, the control logic circuit 9 outputs the enable signal ENE of a specific level to the logic gate 11, and the logic gate 11 Let the value of the Late 'signal be zero. For example, when the logic gate 11 is an AND circuit, the control logic circuit 9 inputs an L level enable signal ENL to the logic gate 11.
- the output control unit having logic gates 10 and 11 has an error signal indicating that the phase of signal ⁇ 1 is ahead of the phase of signal ⁇ 2 when variable delay circuit 3 delays the phase of signal ⁇ 2. Stop outputting from the output unit.
- the output control unit outputs an error signal indicating that the phase of the signal ⁇ 1 is delayed from the phase of the signal ⁇ 2 from the output unit. Will stop.
- logic gates 10 and 11 exist in the subsequent stage of the weighting circuit in FIG. 5A, they may be interposed in the binary phase comparator 4 and the weighting circuit.
- FIG. 5C is a circuit diagram showing the configuration of the phase comparator in which the logic gates 10 and 11 are interposed between the binary phase comparator 4 and the weighting circuit.
- the first output terminal of the binary phase comparator 4 is connected to the first input terminal of the logic gate 10 and the Early signal is input.
- the enable signal ENE is input from the control logic circuit 9 to the second input terminal of the logic gate 10.
- the second input terminal of the binary phase comparator 4 is connected to the first input terminal of the logic gate 11 and the Late signal is input.
- the enable signal ENL is input from the control logic circuit 9 to the second input terminal of the logic gate 11.
- the control logic circuit 9 When the delay control signal DLY is a positive value and the Early signal is at the H level, the control logic circuit 9 outputs the enable signal ENE of a predetermined level to the logic gate 10 and outputs the Early signal to the logic gate 10 as L. Let the level.
- the control logic circuit 9 when the delay control signal DLY is a negative value and the Late signal is at the L level, the control logic circuit 9 outputs an enable signal ENE of a specific level to the logic gate 11, and outputs the Late signal to the logic gate 11. To the L level.
- the output control unit when the variable delay circuit 3 delays the phase of the signal ⁇ 2, the output control unit outputs an error signal indicating that the phase of the signal ⁇ 1 is ahead of the phase of the signal ⁇ 2 from the output unit. To stop. In addition, when the variable delay circuit 3 advances the phase of the signal ⁇ 2, the output control unit outputs an error signal indicating that the phase of the signal ⁇ 1 is delayed from the phase of the signal ⁇ 2 from the output unit. Will stop.
- the output control unit when the variable delay circuit 3 delays the phase of the signal ⁇ 2, the output control unit outputs an error signal indicating that the phase of the signal ⁇ 1 is ahead of the phase of the signal ⁇ 2 from the output unit. To stop. In addition, when the variable delay circuit 3 advances the phase of the signal ⁇ 2, the output control unit outputs an error signal indicating that the phase of the signal ⁇ 1 is delayed from the phase of the signal ⁇ 2 from the output unit. To stop.
- FIG. 6 is a circuit diagram showing the configuration of the phase comparator of the present embodiment.
- the phase comparator includes a variable delay circuit 3 and a binary type phase comparator 41.
- the binary type phase comparator 4 shown in FIG. 1 outputs the Early signal and the Late signal as error signals, but the binary type phase comparator 41 shown in FIG. 6 outputs the Early / Late signal as the error signal. Is output.
- the Early / Late signal is at the H level, it indicates that the phase of the signal ⁇ 1 is ahead of the phase of the delay signal ⁇ 2 ′, and when it is at the L level, the phase of the signal ⁇ 1 is delayed from the phase of the delay signal ⁇ 2 ′. It shows that.
- the Early / Late signal is at the H level, it indicates that the phase of the signal ⁇ 1 is delayed from the phase of the delay signal ⁇ 2 ′.
- the Early / Late signal is at the L level, the phase of the signal ⁇ 1 is advanced from the phase of the delay signal ⁇ 2 ′. You may show that
- FIG. 7A is a circuit diagram showing a configuration example of the binary phase comparator 41.
- the binary phase comparator 41 includes input terminals 41a and 41b, a flip-flop circuit 41c, and an output terminal 41d.
- the signal ⁇ 1 is input to the input terminal 41a, and the input signal ⁇ 1 is output.
- the delay signal ⁇ 2 ′ is input to the input terminal 41b, and the input delay signal ⁇ 2 ′ is output.
- the input terminal 4a is connected to the D input terminal of the flip-flop circuit 41c, and the signal ⁇ 1 is input. Further, the input terminal 4b is connected to the CK input terminal of the flip-flop circuit 41c, and the delay signal ⁇ 2 'is input thereto.
- the flip-flop circuit 41c holds the input signal ⁇ 1 at the edge timing of the input delay signal ⁇ 2 ', and outputs the held signal ⁇ 1 from its Q terminal as an Early / Late signal.
- the output terminal 41d is connected to the Q terminal of the flip-flop circuit 41c and receives the Early / Late signal.
- the output terminal 41d outputs the input Early / Late signal.
- the Early / Late signal becomes L level when the phase of the signal ⁇ 1 is delayed from the phase of the delay signal ⁇ 2 ′, and the phase of the signal ⁇ 1 is the phase of the delay signal ⁇ 2 ′. When it is more advanced, it becomes H level.
- FIG. 8 is a circuit diagram showing a more detailed configuration of the phase comparator of the present embodiment.
- the phase comparator includes input terminals 1 and 2, variable delay circuit 3, multipliers 5 and 6, output terminals 7 and 8, control logic circuit 9, separator 12, and binary phase. And a comparator 41.
- the binary phase comparator 41 is an example of a discrimination unit.
- the input terminal 1 is connected to the first input terminal of the binary phase comparator 41 and the signal ⁇ 1 is input. Further, the output terminal of the variable delay circuit 3 is connected to the second input terminal of the binary phase comparator 41, and the delay signal ⁇ 2 'is input thereto.
- the binary type phase comparator 41 compares the phase of the input signal ⁇ 1 and the phase of the delay signal ⁇ 2 'to determine the front-rear relationship between the phase of the signal ⁇ 1 and the phase of the delay signal ⁇ 2'.
- the binary phase comparator 4 outputs a discrimination result indicating the context as an Early / Late signal from its own output terminal.
- the output terminal of the binary type phase comparator 41 is connected to the input terminal of the separation unit 12 and the Early / Late signal is input.
- the separation unit 12 generates an Early signal and a Late signal from the input Early / Late signal. For example, the separation unit 12 generates an Early / Late signal as an Early signal, and generates a signal obtained by inverting the level of the Early / Late signal as a Late signal.
- the separation unit 12 outputs the generated Early signal from its own first output terminal, and outputs the generated Late signal from its own second output terminal.
- the first output terminal of the separation unit 12 is connected to the input terminal of the multiplier 5 and the Early signal is input.
- the second output terminal of the separation unit 12 is connected to the input terminal of the multiplier 6 and the Late signal is input.
- the separation unit 12 simply separates the Early / Late signal into two, outputs one Early / Late signal from its own first output terminal, and outputs the other Early / Late signal to its first Early / Late signal. You may output from two output terminals. In this case, the multiplier 6 inverts the Early / Late signal input to its own input terminal to generate a Late signal.
- phase comparator described in the present embodiment may further include an output control unit having the logic gates 10 and 11 described in the second embodiment, as shown in FIG. 9A. Further, the output control unit may be interposed between the separation unit 12 and the weighting circuit as shown in FIG. 9B.
- the first input terminal of the logic gate 10 is connected to the first output terminal of the separation unit 12 and the Early signal is input.
- the second input terminal of the separation unit 12 is connected to the first input terminal of the logic gate 11 and the Late signal is input.
- FIG. 10 is a circuit diagram showing the configuration of the phase comparator of the present embodiment.
- the phase comparator includes a variable delay circuit 3 and a multi-bit type phase comparator 42.
- the multi-bit type phase comparator 42 can determine the phase difference between the signals ⁇ 1 and ⁇ 2 by itself, but in this embodiment, by introducing the variable delay circuit 3, the phase difference that can be determined is determined. And the range of the phase difference that can be discriminated can be increased.
- FIG. 11A is a circuit diagram showing a configuration example of the multi-bit type phase comparator 42.
- multibit type phase comparator 42 includes input terminals 42a and 42b, delay circuits 42c1 to 42c5, flip-flop circuits 42d1 to 42d6, encoder 42e, and output terminal 42f.
- the signal ⁇ 1 is input to the input terminal 42a, and the input signal ⁇ 1 is output.
- the delay signal ⁇ 2 ' is input to the input terminal 42b, and the input delay signal ⁇ 2' is output.
- the delay circuits 42c1 to 42c5 are connected in series with each other. Each of the delay circuits 42c1 to 42c5 delays the signal ⁇ 1 input to the input terminal 42 by a predetermined constant delay amount.
- the signal ⁇ 1 delayed in each of the delay circuits 42c1 to 42c5 is sequentially input from the signal having the smaller delay amount (delay circuit 42c1) to the signal ⁇ 1 ′, the signal ⁇ 1 ′′, the signal ⁇ 1 ′ ′′, and the signal ⁇ 1 ′ ′′.
- a signal ⁇ 1, a signal ⁇ 1 ′, a signal ⁇ 1 ′′, a signal ⁇ 1 ′ ′′, a signal ⁇ 1 ′′ ′′, and a signal ⁇ 1 ′ are sequentially input from the flip-flop circuit 42d1 to the D input terminals of the flip-flop circuits 42d1 to 42d6. Each of '' '' is entered.
- the input terminal 42b is connected to each CK input terminal of the flip-flop circuits 42d1 to 42d6, and the delay signal ⁇ 2 'is input.
- Each of the flip-flop circuits 42d1 to 42d6 holds the signal input to its own D input terminal at the timing of the edge of the delayed signal ⁇ 2 ′ input to its own CK input terminal, and holds the held signal as its own signal. Output from the Q terminal.
- each of the flip-flop circuits 42d1 to 42d6 outputs an H level signal when the phase of the input signal is ahead of the phase of the delay signal ⁇ 2 ′, and When the phase is behind the phase of the delay signal ⁇ 2 ′, an L level signal is output.
- the signal output from the flip-flop circuit 42dn is referred to as an output signal Qm.
- m is an integer from 1 to 6.
- the output signals Q1 to Q6 represent the phase difference between the signal ⁇ 1 and the delay signal ⁇ 2 'by a thermometer code.
- the thermometer code is a code that represents a value by the number of H level signals.
- the encoder 42e has at least the same number of input terminals as the number of stages of the flip-flop circuits.
- the Q terminals of the flip-flop circuits 42d1 to 42d6 are connected to the input terminals, and the output signals Q1 to Q6 are input. Is done.
- the encoder 42e converts the output signals Q1 to Q6, which are thermometer codes, into binary codes, and generates an output signal Code.
- the encoder 42e outputs the output signal Code from its own output terminal.
- the encoder 42e may not be provided.
- the output signals Q1 to Q6, which are thermometer codes, or the output signal Code is a discrimination result indicating the front-rear relationship between the phase of the signal ⁇ 1 and the phase of the signal ⁇ 2, and the phase difference between the signal ⁇ 1 and the delayed signal ⁇ 2 ′.
- FIG. 11B is an explanatory view showing an operation example of the multi-bit type phase comparator 42.
- the output signals Q1 to Q3 become H level and output Signals Q4 to Q6 are at the L level.
- the encoder 42e since the number of H levels is 3, the encoder 42e generates an output signal Code indicating 3 as a phase difference.
- the delay amount of the variable delay circuit 3 indicates the phase difference between the signal ⁇ 2 and the delay signal ⁇ 2 ′, if a weight value corresponding to the delay amount of the variable delay circuit 3 is added to the output signal Code,
- the value of the output signal Code (referred to as output signal Code ′) to which the weight value has been added indicates the phase difference between the signals ⁇ 1 and ⁇ 2.
- the resolution of the phase difference determined by the multi-bit type phase comparator 42 is determined by the delay amount (constant delay amount) per stage of the delay circuit included in the multi-bit type phase comparator 42. Therefore, if the delay amount of the variable delay circuit 3 is adjusted in units smaller than the constant delay amount, the value of the output signal Code ′ is set to a value finer than the resolution of the phase difference determined by the multi-bit type phase comparator 42. Will have. Therefore, the phase difference between signals ⁇ 1 and ⁇ 2 can be determined with higher accuracy.
- the range of the phase difference that can be detected by the multibit type phase comparator 42 is calculated by the product of the delay amount per stage of the delay circuit included in the multibit type phase comparator 42 and the number of stages of the delay circuit. Value. Hereinafter, this value is referred to as a detectable range.
- the variable delay circuit 3 delays the phase of the delay signal ⁇ 2 ′ from the phase of the signal ⁇ 1 to set any one of the output signals Q1 to Q6 of the flip-flop circuits 42d1 to 42d6 to the H level, the output The signal Code indicates the phase difference. Therefore, the phase difference between the signals ⁇ 1 and ⁇ 2 can be determined from the output signal Code ′.
- the flip-flop circuit 42d1 to Since all of the output signals Q1 to Q6 of 42d6 are at the H level, the phase difference between the signals ⁇ 1 and ⁇ 2 cannot be determined.
- variable delay circuit 3 advances the phase of the delay signal ⁇ 2 ′ from the phase of the signal ⁇ 1 ′ ′′ ′′ so that any one of the output signals Q1 to Q6 of the flip-flop circuits 42d1 to 42d6 is L
- the output signal Code indicates a phase difference. Therefore, the phase difference between the signals ⁇ 1 and ⁇ 2 can be determined from the output signal Code ′.
- FIG. 12 is a circuit diagram showing a more detailed configuration of the phase comparator of the present embodiment. 12, the phase comparator includes input terminals 1 and 2, a variable delay circuit 3, a control logic circuit 9, an adder 13, an output terminal 14, and a multi-bit type phase comparator 42.
- the delay amount of the variable delay circuit 3 can be set in units smaller than the resolution of the phase difference determined by the multi-bit type phase comparator 42.
- the multi-bit type phase comparator 42 is an example of a discrimination unit.
- the input terminal 1 is connected to the first input terminal of the multi-bit type phase comparator 42 and the signal ⁇ 1 is input. Further, the output terminal of the variable delay circuit 3 is connected to the second input terminal of the multi-bit type phase comparator 42, and the delay signal ⁇ 2 'is input thereto.
- the multi-bit type phase comparator 42 discriminates the phase difference between the input signal ⁇ 1 and the delayed signal ⁇ 2 ′ and the front-rear relationship between the phase of the signal ⁇ 1 and the phase of the delayed signal ⁇ 2 ′, and the phase difference and An output signal Code indicating the context is output from its own output terminal.
- the output signal Code is a multi-bit signal.
- the adder 13 is an example of weighting means.
- the output terminal of the multi-bit type phase comparator 42 is connected to the input terminal of the adder 13 and the output signal Code is input.
- the bias signal Bias is input from the control logic circuit 9 to the control terminal of the adder 13.
- the adder 13 gives a weight value to the output signal Code by adding the value of the input bias signal Bias signal as a weight value to the input output signal Code.
- the adder 13 outputs the output signal Code to which the weight value is given from its own output terminal as the output signal Code ′.
- the output means of the adder 13 is connected to the output terminal 14 and the output signal Code ′ is input.
- the output terminal 14 outputs the input output signal Code ′.
- the control logic circuit 9 inputs the bias signal Bias to the control terminal of the adder 13. As in the first embodiment, the control logic circuit 9 inputs the delay control signal DLY to the control terminal of the variable delay circuit 3.
- the output signal Code is input from the multi-bit type phase comparator 42 to the control logic circuit 9.
- the control logic circuit 9 adjusts the delay amount indicated by the delay control signal DLY in units smaller than the resolution of the phase difference determined by the multi-bit type phase comparator 42 according to the input output signal Code.
- the control logic circuit 9 sets the phase difference within the detectable range.
- the delay amount of the variable delay circuit 3 is adjusted so as to be included.
- the control logic circuit 9 decreases the delay amount indicated by the delay control signal DLY until the value of the output signal Code becomes smaller than the maximum value.
- the control logic circuit 9 increases the delay amount indicated by the delay control signal DLY until the value of the output signal Code becomes larger than zero.
- the multi-bit type phase comparator 42 further determines the phase difference between the signal ⁇ 1 and the delay signal ⁇ 2 ′ in addition to the phase relationship between the phase of the signal ⁇ 1 and the phase of the delay signal ⁇ 2, and the determined context And an output signal Code indicating the phase difference is output.
- the adder 13 adds a weight value to the output signal Code to generate an output signal Code ′.
- the control logic circuit 9 adjusts the delay amount of the variable delay circuit 3 by a unit smaller than the resolution of the phase difference determined by the multi-bit type phase comparator 42.
- the value of the output signal Code ′ can be made finer than the resolution of the phase difference determined by the multi-bit type phase comparator 42. Therefore, the phase difference between the signals ⁇ 1 and ⁇ 2 can be determined with a value finer than the resolution of the phase difference determined by the multi-bit type phase comparator 42.
- the control logic circuit 9 sets the phase difference within the detectable range.
- the delay amount of the variable delay circuit 3 is adjusted so as to be included.
- phase difference between the signals ⁇ 1 and ⁇ 2 can be determined in a wider range than the dynamic range of the phase difference determined by the multi-bit type phase comparator 42.
- phase comparator capable of detecting a phase difference between a data signal and a clock signal
- FIG. 13A is a circuit diagram showing the phase comparator of the present embodiment.
- the phase comparator includes a variable delay circuit 3 and a binary type phase comparator 43.
- the data signal Din and the clock signals ⁇ 1, ⁇ 2, and ⁇ 3 are input to this phase comparator.
- the phase of the clock signal ⁇ 1 is advanced from the phase of the clock signal ⁇ 2, and the phase of the clock signal ⁇ 3 is delayed from the phase of the clock signal ⁇ 2.
- the data signal Din is an example of the first signal.
- the clock signal ⁇ 1 is an example of a preceding signal
- the clock signal ⁇ 2 is an example of a second input signal
- the clock signal ⁇ 3 is an example of a subsequent signal.
- variable delay circuit 3 delays the clock signal ⁇ 2 to generate a delayed clock signal ⁇ 2 '.
- the binary phase comparator 43 uses the delayed clock signal ⁇ 2 ′, and the anteroposterior relationship between the phase of the data signal Din and the phase of the delayed clock signal ⁇ 2 ′, and the data signal Din and the delayed clock signal ⁇ 2 ′. Determine the phase difference.
- FIG. 14 is a circuit diagram showing a more detailed configuration of the phase comparator of the present embodiment.
- the phase comparator includes input terminals 1, 2 a, 2 b and 2 c, a variable delay circuit 3, multipliers 5 and 6, a control logic circuit 9, and a binary phase comparator 43.
- the data signal Din is input to the input terminal 1.
- the clock signal ⁇ 1 is input to the input terminal 2a
- the clock signal ⁇ 2 is input to the input terminal 2b
- the clock signal ⁇ 3 is input to the input terminal 2c.
- the data signal Din is a differential signal in this embodiment.
- the input terminal 2b is connected to the input terminal of the variable delay circuit 3, and the clock signal ⁇ 2 is input.
- the variable delay circuit 3 delays the clock signal ⁇ 2 by the delay amount indicated by the delay control signal DLY input to its own control terminal, thereby adjusting the phase of the clock signal ⁇ 2 and generating the delayed clock signal ⁇ 2 ′. .
- the variable delay circuit 3 outputs the generated delayed clock signal ⁇ 2 'from its output terminal.
- the binary type phase comparator 43 includes holding circuits 43a to 43c and a selection output unit having exclusive OR circuits 43d and 43e.
- Each of the holding circuits 43a to 43c is, for example, a flip-flop circuit or a sampling latch circuit.
- the input terminal 1 is connected to the first input terminal of the holding circuit 43a, and the data signal Din is input.
- the input terminal 2a is connected to the second input terminal of the holding circuit 43a, and the clock signal ⁇ 1 is input thereto.
- the holding circuit 43a holds the data signal Din at the edge timing of the clock signal ⁇ 1, and outputs the held data signal Din from its own output terminal.
- the input terminal 1 is connected to the first input terminal of the holding circuit 43b, and the data signal Din is input.
- the output terminal of the variable delay circuit 3 is connected to the second input terminal of the holding circuit 43b, and the delayed clock signal ⁇ 2 'is input thereto.
- the holding circuit 43b holds the data signal Din at the edge timing of the delayed clock signal ⁇ 2 ', and outputs the held data signal Din from its own output terminal.
- the input terminal 1 is connected to the first input terminal of the holding circuit 43c, and the data signal Din is input.
- the input terminal 2c is connected to the second input terminal of the holding circuit 43c, and the clock signal ⁇ 3 is input.
- the holding circuit 43c holds the data signal Din at the edge timing of the clock signal ⁇ 3, and outputs the held data signal Din from its own output terminal.
- the holding circuit 43a is an example of a first holding unit
- the holding circuit 43b is an example of a second holding unit
- the holding circuit 43c is an example of a third holding unit.
- the selection output unit having the exclusive OR circuits 43d and 43e has an Early signal of H level when the data signal Din output from the holding circuit 43a and the data signal Din output from the holding circuit 43b are different from each other. Is output.
- the selection output unit outputs an H-level Late signal when the data signal Din output from the holding circuit 43b and the data signal Din output from the holding circuit 43c are different from each other.
- the output terminal of the holding circuit 43a is connected to the first input terminal of the exclusive OR circuit 43d, and the data signal Din held by the clock signal ⁇ 1 is input.
- the output terminal of the holding circuit 43b is connected to the second input terminal of the exclusive OR circuit 43d, and the data signal Din held by the delayed clock signal ⁇ 2 'is input.
- the exclusive OR circuit 43d calculates the exclusive OR of the data signal Din input to its first input terminal and the data signal Din input to its second input terminal. The result is output as an Early signal from its own output terminal.
- the output terminal of the holding circuit 43b is connected to the first input terminal of the exclusive OR circuit 43e, and the data signal Din held by the delayed clock signal ⁇ 2 'is input.
- the output terminal of the holding circuit 43c is connected to the second input terminal of the exclusive OR circuit 43e, and the data signal Din held by the clock signal ⁇ 3 is input.
- the exclusive OR circuit 43e calculates an exclusive OR of the data signal Din input to its first input terminal and the data signal Din input to its second input terminal. The result is output as a Late signal from its own output terminal.
- the Late signal is assumed to be H level.
- the timing of the edge of the data signal Din is the clock signal ⁇ 1. Is between the edge timing and the edge timing of the delayed clock signal ⁇ 2 ′. Therefore, the phase of the data signal Din is ahead of the phase of the delayed clock signal ⁇ 2 '.
- the timing of the edge of the data signal Din is the timing of the delayed clock signal ⁇ 2 ′. This is between the edge timing and the edge timing of the clock signal ⁇ 3. Therefore, the phase of the data signal Din is delayed from the phase of the delayed clock signal ⁇ 2 '.
- the selection output unit outputs an Early signal of H level, and the phase of the data signal Din is delayed from the phase of the delayed clock signal ⁇ 2 ′. If so, an H-level Late signal is output.
- the control logic circuit 9 adjusts the value of the weighting control signal in accordance with the delay amount of the variable delay circuit 3, so that the phase of the data signal Din and the clock are adjusted from the weighting unit.
- the Early ′ signal and the Late ′ signal indicating the phase relationship of the signal ⁇ 2 and the phase difference between the data signal Din and the clock signal ⁇ 2 can be output.
- the holding circuit 43a holds the data signal Din at the edge timing of the clock signal ⁇ 1, and outputs the held data signal Din.
- the holding circuit 43b holds the data signal Din at the edge timing of the delayed clock signal ⁇ 2 'and outputs the held data signal Din.
- the holding circuit 43c holds the data signal Din at the edge timing of the clock signal ⁇ 3, and outputs the held data signal Din.
- the selection output unit outputs an Early signal of H level.
- the selection output unit outputs an H-level Late signal when the data signal Din output from the holding circuit 43b and the data signal Din output from the holding circuit 43c are different from each other.
- the phase difference between the data signal and the clock signal can be determined.
- FIG. 15 is a circuit diagram showing the configuration of the phase comparator of the present embodiment.
- the phase comparator includes an input terminal 15 in addition to the configuration shown in FIG. 14.
- the binary phase comparator 43 includes holding circuits 43f to 43h in addition to the configuration shown in FIG.
- the clock signal ⁇ 4 is input to the input terminal 15.
- the input terminal 15 is an example of third input means.
- the output terminal of the holding circuit 43a is connected to the first input terminal of the holding circuit 43f, and the data signal Din held by the clock signal ⁇ 1 is input.
- the input terminal 15 is connected to the second input terminal of the holding circuit 43h, and the clock signal ⁇ 4 is input thereto.
- the holding circuit 43h holds the input data signal Din at the edge timing of the clock signal ⁇ 4, and outputs the held data signal Din from its own output terminal.
- the output terminal of the holding circuit 43b is connected to the first input terminal of the holding circuit 43g, and the data signal Din held by the delayed clock signal ⁇ 2 'is input.
- the input terminal 15 is connected to the second input terminal of the holding circuit 43g, and the clock signal ⁇ 4 is input thereto.
- the holding circuit 43g holds the input data signal Din at the edge timing of the clock signal ⁇ 4, and outputs the held data signal Din from its own output terminal.
- the output terminal of the holding circuit 43c is connected to the first input terminal of the holding circuit 43h, and the data signal Din held by the clock signal ⁇ 3 is input.
- the input terminal 15 is connected to the second input terminal of the holding circuit 43h, and the clock signal ⁇ 4 is input thereto.
- the holding circuit 43h holds the input data signal Din with the clock signal ⁇ 4, and outputs the held data signal Din from its own output terminal.
- the holding circuit 43e is an example of fourth holding means
- the holding circuit 43g is an example of fifth holding means
- the holding circuit 43h is an example of sixth holding means.
- the functions of the selection output unit may be the functions described with reference to FIG. 14, in which the holding circuit 43a is read as the holding circuit 43f, the holding circuit 43b is read as the holding circuit 43g, and the holding circuit 43c is read as the holding circuit 43h.
- the timing of the data signal Din input to the exclusive OR circuits 43d and 43e is aligned. For this reason, the time range in which the output signals Early ′ and Late ′ output from the phase comparator are valid can be widened.
- the Early ′ signal and the Late ′ signal generated by the phase comparator shown in FIGS. 1, 5A, 5B, 6, 8, 9A, and 9B are shown in FIGS.
- a signal conversion circuit for converting the output signal Code ′ generated by the phase comparator will be described.
- 16A and 16B are circuit diagrams showing a configuration example of the signal conversion circuit.
- This signal conversion circuit is connected to the multipliers 5 and 6 and the output terminals 7 and 8 of the phase comparator shown in FIGS. 1, 5A, 5B, 6, 8, 8, 9A, and 9B. Can intervene.
- the phase comparator includes an output terminal 14 instead of the output terminals 7 and 8 as in the phase comparator shown in FIG.
- the signal conversion circuit includes a selector 16.
- the first input terminal of the selector 16 is connected to the output terminal of the multiplier 5 and receives the Early 'signal.
- the output terminal of the multiplier 6 is connected to the second input terminal of the selector 16 and the Late ′ signal is input.
- the selector 16 inverts the value of the input Late ′ signal.
- the selector 16 uses the Late ′ signal with the inverted value as its output signal Code ′. Output from the output terminal.
- the selector 16 when the value of the Early ′ signal is greater than 0, the selector 16 outputs the Early ′ signal from its own output terminal as the output signal Code ′.
- the signal conversion circuit includes an adder 17.
- the output terminal of the multiplier 5 is connected to the first input terminal of the adder 17 and the Early ′ signal is input.
- the output terminal of the multiplier 6 is connected to the second input terminal of the adder 17 and the Late ′ signal is input.
- the adder 17 inverts the value of the Late ′ signal.
- the adder 17 adds the Late ′ signal obtained by inverting the value and the Early ′ signal, and outputs the addition result as an output signal Code ′ from its own output terminal.
- the selector 16 and the adder 17 invert the value of the Late ′ signal, it is only necessary to invert the value of either the Early ′ signal or the Late ′ signal.
- the Early ′ signal and the Late ′ signal can be converted into one output signal Code ′ as shown in FIG.
- the horizontal axis represents the phase difference between the signals ⁇ 1 and ⁇ 2
- the vertical axis represents the value of the signal output from the phase comparator.
- variable delay circuit 3 a configuration example of the variable delay circuit 3 will be described.
- FIG. 18 is a circuit diagram showing a configuration example of the variable delay circuit 3.
- the variable delay circuit 3 includes a plurality of tri (3) state inverters 31. Each of the tri-state inverters 31 is connected in parallel with each other.
- the input terminal of the variable delay circuit 3 is connected to the input terminal of the tri-state inverter 31, and the signal ⁇ 2 (or signal ⁇ 2) is input.
- the output terminal of the variable delay circuit 3 is connected to the output terminal of the tristate inverter 31.
- the tri-state inverter 31 has two delay control terminals.
- the control logic circuit 9 is connected to each delay control terminal, and the delay control signal DLY is input. Note that the delay control terminal included in each of the tri-state inverters 31 serves as a control terminal of the variable delay circuit 3.
- Tristate inverter 31 includes pMOS transistors 32 and 33 and nMOS transistors 34 and 35.
- the source terminal is connected to the power supply, and the drain terminal is connected to the source terminal of the pMos transistor 33.
- the drain terminal is connected to the output terminal of the tri-state inverter 31 and the drain terminal of the nMos transistor 34.
- the source terminal is connected to the drain terminal of the nMos transistor 35.
- the source terminal is grounded.
- the gate terminal of the pMos transistor 33 and the gate terminal of the nMos transistor 34 are connected to the input terminal of the tri-state inverter 31.
- the gate terminal of the pMos transistor 32 is connected to one delay control terminal of the tri-state inverter 31, and the gate terminal of the nMos transistor 35 is connected to the other delay control terminal of the tri-state inverter 31.
- the gate terminal of the pMos transistor 32 and the gate terminal of the nMos transistor 35 are connected to the input terminal of the tristate inverter 31, and the gate terminal of the pMos transistor 33 is connected to one delay control terminal of the tristate inverter 31.
- the gate terminal of the nMos transistor 34 may be connected to the other delay control terminal of the tri-state inverter 31.
- the amount of delay changes according to the value of the delay control signal DLY input to each delay control terminal of the tri-state inverter 31.
- the control logic circuit 9 adjusts the delay amount of the variable delay circuit 3 by adjusting the value of the delay control signal DLY input to each delay control terminal of the tri-state inverter 31.
- FIG. 19 is a circuit diagram showing a configuration example of the control logic circuit 9.
- the control logic circuit 9 includes an n-bitUP / Down counter 91 and a determination unit having logic circuits 92 and 93.
- An n-bitUP / Down counter (hereinafter abbreviated as a counter) 91 is an example of a counting unit.
- the first output terminal of the binary phase comparator 4 is connected to the first input terminal of the counter 91, and the Early signal is input.
- the second output terminal of the binary phase comparator 4 is connected to the second input terminal of the counter 91, and the Late signal is input.
- the counter 91 holds a count value.
- the counter 91 sets the count value to 0 when the value of the delay control signal is 0.
- the count value is represented by n bits, and the negative value is represented by a complement expression.
- the counter 91 counts up or down the held count value based on the input Early signal and Late signal.
- the counter 91 counts up the count value when an H-level Late signal is input, and counts down the count value when an H-level Early signal is input.
- the counter 91 obtains the delay amount X of the variable delay circuit 3 according to the count value counted up or down. Specifically, the counter 91 obtains a larger delay amount X as the count value is larger. In the present embodiment, the count value is obtained as the delay amount X of the variable delay circuit 3.
- the method for obtaining the delay amount of the variable delay circuit 3 can be changed as appropriate. For example, the counter 91 may obtain the delay amount X of the variable delay circuit 3 by multiplying the count value by a constant.
- the counter 91 outputs a count signal n indicating the obtained delay amount X from its own output terminal.
- the output terminal of the counter 91 and the control terminal of the variable delay circuit 3 are connected, and the count signal n is used as the delay control signal DLY.
- the Late signal becomes H level.
- the count value is counted up. Therefore, the value of the delay control signal increases and the delay amount X of the variable delay circuit 3 increases. Therefore, since the phase of the delay signal ⁇ 2 ′ is delayed, the phase difference between the signal ⁇ 1 and the delay signal ⁇ 2 ′ is reduced.
- the phase of the signal ⁇ 1 is ahead of the phase of the delay signal ⁇ 2 ', the Early signal becomes H level. In this case, the count value is counted down. Therefore, the value of the delay control signal is reduced, and the delay amount X of the variable delay circuit is reduced. Therefore, since the phase of the delay signal ⁇ 2 'advances, the phase difference between the signal ⁇ 1 and the delay signal ⁇ 2' decreases.
- the output terminal of the counter 91 is connected to the input terminal of the logic circuit 92 and the count signal n is input.
- the logic circuit 92 determines the value of the weighting control signal ME according to the delay amount X indicated by the count signal n, and inputs the weighting control signal ME having the value to the control terminal of the multiplier 5.
- the logic circuit 92 increases the value of the weighting control signal ME as the absolute value of the delay amount X increases. For example, the logic circuit 92 sets the absolute value of the delay amount X to the value of the weighting control signal ME.
- the logic circuit 92 determines the value of the weighting control signal ME to be 0.
- the output terminal of the counter 91 is connected to the input terminal of the logic circuit 93, and the count signal n is input.
- the logic circuit 93 determines the value of the weighting control signal ML according to the delay amount X indicated by the count signal n, and inputs the weighting control signal ML of that value to the control terminal of the multiplier 6.
- the logic circuit 93 increases the value of the weighting control signal ML as the delay amount X increases. For example, the logic circuit 93 sets the delay amount X to the value of the weighting control signal ML.
- the logic circuit 93 determines the value of the weighting control signal ML to be 0.
- FIG. 20 is a flowchart for explaining an operation example of the control logic circuit 9.
- DLY is a count value, which is the value of the delay control signal input to the variable delay circuit 3.
- ME is a weighting value given to the Early signal
- ML is a weighting value given to the Late signal.
- step S 1 the Early signal and the Late signal are input from the binary phase comparator 4 to the counter 91 of the control logic circuit 9.
- the counter 91 determines which of the Early signal and the Late signal is at the H level.
- the counter 91 executes step S2 when the Early signal is at the H level, and the counter 91 executes step S3 when the Late signal is at the H level.
- step S2 the counter 91 counts up the held count value.
- the counter 91 obtains the counted up count value as the delay amount X.
- the counter 91 inputs the count signal n indicating the delay amount X as a delay control signal to the control terminal of the variable delay circuit 3 and inputs the count signal n to the input terminals of the logic circuits 92 and 93. Thereafter, step S4 is executed.
- step S3 the counter 91 counts down the held count value.
- the counter 91 obtains the delay amount X according to the counted down count value.
- the counter 91 inputs the count signal n indicating the delay amount X as a delay control signal to the control terminal of the variable delay circuit 3 and inputs the count signal n to the input terminals of the logic circuits 92 and 93. Thereafter, step S4 is executed.
- step 4 the logic circuit 92 determines whether or not the delay amount X indicated by the count signal n is negative.
- the logic circuit 92 When the delay amount X is negative, the logic circuit 92 generates a weighting control signal ML having the absolute value of the delay amount X as a value. On the other hand, when the value of the count signal n is 0 or positive, the logic circuit 92 generates a weighting control signal ML having 0 as a value. The logic circuit 92 inputs the generated weighting control signal to the control terminal of the multiplier 5.
- the logic circuit 93 determines whether or not the delay amount X indicated by the count signal n is positive. When the delay amount X is positive, the logic circuit 92 generates a weighting control signal ML having the delay amount as a value. When the count signal n is negative or 0, the logic circuit 92 is weighted with a value of 0. A control signal ML is generated. The logic circuit 92 inputs the generated weight control signal ML to the control terminal of the multiplier 6.
- an Early ′ signal or a Late ′ signal corresponding to the magnitude of the phase difference between the signals ⁇ 1 and ⁇ 2 can be obtained.
- the counter 91 holds a count value, and counts up or down the count value based on the Early signal and the Late signal. Further, the counter 91 adjusts the delay amount of the variable delay circuit 3 in accordance with the count value counted up or down. The determination unit determines the weight value according to the delay amount adjusted by the counter 91.
- the count value reflects the context of the phase of the signal ⁇ 1 and the phase of the delay signal ⁇ 2. Therefore, the delay amount can be easily adjusted to a value that changes the context shown by the determination result.
- FIG. 21 is an explanatory diagram showing an operation example of the phase comparator using the control logic circuit 9 shown in FIG. FIG. 21 shows a case where the phase of the signal ⁇ 1 is delayed from the phase of the signal ⁇ 2. Further, the phase difference between the signals ⁇ 1 and ⁇ 2 is gradually reduced due to a feedback loop or the like.
- the counter 91 counts up the counter value.
- the delay amount of the variable delay circuit 3 gradually increases, so that the phase of the delay signal ⁇ 2 ′ gradually delays and approaches the phase of the signal ⁇ 1.
- the Late ′ signal indicates that the phase of the signal ⁇ 1 is greatly delayed from the phase of the signal ⁇ 2.
- the phase of the delay signal ⁇ 2 ' is delayed, exceeds the phase of the signal ⁇ 1, and is delayed from the phase of the signal ⁇ 1. Then, the Early signal becomes H level and the Late signal becomes L level. At this time, the counter 91 counts down the count value. Thereby, the delay amount of the variable delay circuit 3 is reduced, the phase of the delay signal ⁇ 2 ′ is advanced from the signal ⁇ 1, the Early signal becomes L level, and the Late signal becomes H level.
- the Late ′ signal when the Late signal is at the H level indicates the phase difference between the signals ⁇ 1 and ⁇ 2.
- the Late signal is at the L level, so the value of the Late ′ signal is 0. Therefore, even when the phase of the signal ⁇ 1 is delayed from the phase of the signal ⁇ 2, the value of the Late ′ signal becomes 0, and there is a problem that the Late ′ signal does not show the phase difference between the signals ⁇ 1 and ⁇ 2.
- phase comparator capable of solving the above problem will be described as a tenth embodiment.
- FIG. 22A is a circuit diagram showing the phase comparator of the present embodiment.
- the phase comparator includes input terminals 1 and 2, variable delay circuit 3, multipliers 5a to 5c, multipliers 6a to 6c, output terminals 7 and 8, and control logic circuit 9. Includes a selection unit having units 12a to 12c, delay circuits 18 and 19, multiplexers 20 and 21, and binary phase comparators 44 to 46.
- Control logic circuit 9 includes a counter 91 and logic circuits 92 and 93.
- the multipliers 5a to 5c and the multipliers 6a to 6c constitute a weighting unit.
- the output terminals 7 and 8 and the multiplexers 20 and 21 constitute an output unit.
- the output terminal of the variable delay circuit 3 is connected to the input terminal of the delay circuit 18, and the delay signal ⁇ 2 'is input.
- the delay circuit 18 delays the delay signal ⁇ 2 ′ by a predetermined delay amount to generate a delay signal ⁇ 2 ′′.
- the delay circuit 18 outputs the generated delay signal ⁇ 2 ′′ from its output terminal.
- the output terminal of the delay circuit 18 is connected to the input terminal of the delay circuit 19, and the delay signal ⁇ 2 'is input.
- the delay circuit 19 delays the delay signal ⁇ 2 ′′ by a predetermined specific delay amount to generate a delay signal ⁇ 2 ′′ ′′.
- the delay circuit 19 outputs the generated delay signal ⁇ 2 '' 'from its own output terminal.
- the specific delay amount and the predetermined delay amount are preferably equal to each other and equal to a unit in which the delay amount of the variable delay circuit 3 can be adjusted.
- the phases of the delay signals ⁇ 2 ′, ⁇ 2 ′′, and ⁇ 2 ′′ ′′ vary according to the delay amount of the variable delay circuit 3 as shown in FIG. 22B.
- the delay circuit 18 is an example of a first delay unit
- the delay circuit 19 is an example of a second delay unit.
- the input terminal 1 is connected to the first input terminal of the binary phase comparator 44, and the signal ⁇ 1 is input.
- the output terminal of the variable delay circuit 3 is connected to the second input terminal of the binary phase comparator 44, and the delay signal ⁇ 2 'is input thereto.
- the binary phase comparator 44 discriminates the front / rear relationship between the phase of the signal ⁇ 1 and the phase of the delay signal ⁇ 2 ', and outputs an Early / Late1 signal indicating the front / rear relationship from its own output terminal.
- the Early / Late1 signal is at the H level, it indicates that the phase of the signal ⁇ 1 is ahead of the phase of the delay signal ⁇ 2 ′, and when it is at the L level, the phase of the signal ⁇ 1 is delayed from the phase of the delay signal ⁇ 2 ′.
- the input terminal 1 is connected to the first input terminal of the binary phase comparator 45, and the signal ⁇ 1 is input.
- the output terminal of the delay circuit 18 is connected to the second input terminal of the binary phase comparator 45, and the delay signal ⁇ 2 ′′ is input.
- the binary phase comparator 45 determines the front-rear relationship between the phase of the signal ⁇ 1 and the phase of the delayed signal ⁇ 2 ′′, and outputs an Early / Late2 signal indicating the front-rear relationship from its own output terminal.
- the Early / Late2 signal is at the H level, it indicates that the phase of the signal ⁇ 1 is ahead of the phase of the delay signal ⁇ 2 ′′, and when it is at the L level, the phase of the signal ⁇ 1 is the phase of the delay signal ⁇ 2 ′′. Indicates that it is later.
- the input terminal 1 is connected to the first input terminal of the binary phase comparator 46, and the signal ⁇ 1 is input.
- the output terminal of the delay circuit 19 is connected to the second input terminal of the binary phase comparator 46, and the delay signal ⁇ 2 '' 'is input.
- the binary phase comparator 46 discriminates the front / rear relationship between the phase of the signal ⁇ 1 and the phase of the delayed signal ⁇ 2 '' '', and outputs an Early / Late3 signal indicating the front / rear relationship from its own output terminal.
- the Early / Late3 signal is at the H level, it indicates that the phase of the signal ⁇ 1 is ahead of the phase of the delay signal ⁇ 2 ′ ′′, and when it is at the L level, the phase of the signal ⁇ 1 is the delay signal ⁇ 2 ′ ′′. It shows that it is behind the phase.
- the binary phase comparator 44 is an example of a first determination unit
- the binary phase comparator 45 is an example of a second determination unit
- the binary phase comparator 46 is an example of a third determination unit. It is.
- the Early / Late 1 signal is an example of a first discrimination result
- the Early / Late 2 signal is an example of a second discrimination result
- the Early / Late 3 signal is an example of a third discrimination result.
- the input terminal of the separation unit 12a is connected to the output terminal of the binary phase comparator 44, and receives the Early / Late1 signal.
- the separation unit 12a generates an Early1 signal and a Late1 signal from the input Early / Late1 signal, outputs the generated Early1 signal from its first output terminal, and generates the generated Late1 signal. Output from its second output terminal.
- the input terminal of the separation unit 12b is connected to the output terminal of the binary phase comparator 45, and the Early / Late2 signal is input.
- the separation unit 12b generates an Early2 signal and a Late2 signal from the input Early / Late2 signal, outputs the generated Early2 signal from its first output terminal, and outputs the generated Late2 signal. Output from its second output terminal.
- the input terminal of the separation unit 12c is connected to the output terminal of the binary phase comparator 46, and receives the Early / Late3 signal.
- the separation unit 12c generates an Early3 signal and a Late3 signal from the input Early / Late3 signal, outputs the generated Early3 signal from its first output terminal, and generates the generated Late3 signal as Output from its second output terminal.
- the separators 12a to 12c generate the Early1 signal and the Late1 signal, the Early2 signal and the Late2 signal, or the Early3 signal and the Late3 signal in the same manner as the method in which the separator 12 generates the Early signal and the Late signal. Can do.
- the first output terminal of the separation unit 12a is connected to the input terminal of the multiplier 5a, and the Early1 signal is input thereto.
- the weighting control signal ME1 is input from the control logic circuit 9 to the control terminal of the multiplier 5a.
- the multiplier 5a multiplies the input Early1 signal by the value of the input weighting control signal ME1 as a weight value to generate an Early1 'signal.
- the multiplier 5a outputs the generated Early1 'signal from its own output terminal.
- the first output terminal of the separation unit 12b is connected to the input terminal of the multiplier 5b, and the Early2 signal is input thereto.
- the weighting control signal ME2 is input from the control logic circuit 9 to the control terminal of the multiplier 5b.
- the multiplier 5b multiplies the input Early2 signal by the value of the input weighting control signal ME2 as a weight value to generate an Early2 'signal.
- the multiplier 5b outputs the generated Early 2 'signal from its own output terminal.
- the first output terminal of the separation unit 12c is connected to the input terminal of the multiplier 5c, and the Early3 signal is input thereto.
- the weighting control signal ME3 is input from the control logic circuit 9 to the control terminal of the multiplier 5c.
- the multiplier 5c multiplies the input Early3 signal by the value of the input weighting control signal ME3 as a weight value to generate an Early3 'signal.
- the multiplier 5c outputs the generated Early 3 'signal from its own output terminal.
- the second output terminal of the separation unit 12a is connected to the input terminal of the multiplier 6a, and the Late1 signal is input.
- the weighting control signal ML1 is input from the control logic circuit 9 to the control terminal of the multiplier 6a.
- the multiplier 6a multiplies the input Late1 signal by the value of the input weighting control signal ML1 as a weight value to generate a Late1 'signal.
- the multiplier 6a outputs the generated Late1 'signal from its own output terminal.
- the second output terminal of the separation unit 12b is connected to the input terminal of the multiplier 6b, and the Late2 signal is input.
- the weighting control signal ML2 is input from the control logic circuit 9 to the control terminal of the multiplier 6b.
- the multiplier 6b multiplies the input Late2 signal by the value of the input weighting control signal ML2 as a weight value to generate a Late2 'signal.
- the multiplier 6b outputs the generated Late2 'signal from its own output terminal.
- the second output terminal of the separation unit 12c is connected to the input terminal of the multiplier 6c, and the Late3 signal is input.
- the weighting control signal ML3 is input from the control logic circuit 9 to the control terminal of the multiplier 6c.
- the multiplier 6c multiplies the input Late3 signal by the value of the input weighting control signal ML3 as a weight value to generate a Late3 'signal.
- the multiplier 6c outputs the generated Late3 'signal from its own output terminal.
- the weighting unit gives the weight value determined by the control logic circuit to each of the first discrimination result, the second discrimination result, and the third discrimination result.
- the output terminal of the multiplier 5a is connected to the first input terminal of the multiplexer 20, and the Early1 signal is input.
- the second input terminal of the multiplexer 20 is connected to the output terminal of the multiplier 5b and receives the Early2 signal.
- the output terminal of the multiplier 5c is connected to the third input terminal of the multiplexer 20, and the Early3 signal is input.
- the multiplexer 20 outputs the signal having the largest value among the input Early1 signal or Early3 signal as an Early signal from its own output terminal.
- the output terminal of the multiplier 6a is connected to the first input terminal of the multiplexer 21, and the Late1 signal is input.
- the output terminal of the multiplier 6b is connected to the second input terminal of the multiplexer 21, and the Late2 signal is input.
- the output terminal of the multiplier 6c is connected to the third input terminal of the multiplexer 21, and the Late3 signal is input.
- the multiplexer 21 outputs the signal having the largest value among the input Late1 signal or Late3 signal from its own output terminal as the Late signal.
- the output terminal 7 is connected to the output terminal of the multiplexer 20 and receives the Early signal.
- the output terminal 8 is connected to the output terminal of the multiplexer 21 and receives the Late signal.
- the output unit having the output terminals 7 and 8 and the multiplexers 20 and 21 has the largest phase difference among the first determination result, the second determination result, and the third determination result to which the weighting unit has assigned weight values.
- the signal is output as an error signal.
- the first output terminal of the binary phase comparator 45 is connected to the first input terminal of the counter 91, and the Early / Late2 signal is input.
- the counter 91 counts up the count value when the Early / Late2 signal is at the H level, and counts down the count value when the Early / Late2 signal is at the L level.
- the logic circuit 92 determines the values of the weighting control signals ME1 to ME3 according to the delay amount X indicated by the count signal n.
- the logic circuit 92 increases the values of the weighting control signals ME1 to ME3 as the absolute value of the delay amount X increases. At this time, it is desirable to make the value of the weighting control signal ME2 larger than the value of the weighting control signal ME1, and to make the value of the weighting control signal ME3 larger than the value of the weighting control signal ME2.
- the logic circuit 92 determines the value of the weighting control signal ME1 as a value obtained by subtracting 1 from the absolute value of the delay amount X, determines the value of the weighting control signal ME2 as the absolute value of the delay amount X, and performs weighting.
- the value of the control signal ME3 is determined to be a value obtained by adding 1 to the absolute value of the delay amount X.
- the logic circuit 92 determines the respective values of the weighting control signals ME1 to ME3 as 0.
- the logic circuit 92 inputs the weighting control signal ME1 whose value is determined to the control terminal of the multiplier 5a, and inputs the weighting control signal ME2 whose value is determined to the control terminal of the multiplier 5b, thereby determining the value.
- the weighting control signal ME3 is input to the control terminal of the multiplier 5c.
- the logic circuit 93 determines the values of the weighting control signals ML1 to ML3 according to the delay amount X indicated by the count signal n.
- the logic circuit 93 increases the values of the weighting control signals ML1 to ML3 as the delay amount X increases. At this time, it is desirable to make the value of the weighting control signal ME2 larger than the value of the weighting control signal ML3 and make the value of the weighting control signal ME1 larger than the value of the weighting control signal ME2.
- the logic circuit 93 determines the value of the weighting control signal ML1 as a value obtained by adding 1 to the delay amount X, determines the value of the weighting control signal ML2 as the delay amount X, and sets the value of the weighting control signal ML3 as the value. The value is determined by subtracting 1 from the delay amount X.
- the logic circuit 92 determines the respective values of the weighting control signals ME1 to ME3 as 0.
- the logic circuit 93 inputs the weighted control signal ML1 whose value is determined to the control terminal of the multiplier 6a, and inputs the weighted control signal ML2 whose value is determined to the control terminal of the multiplier 6b, and determines the value.
- the weight control signal ML3 is input to the control terminal of the multiplier 6c.
- FIG. 23 is a flowchart for explaining the operation of the phase comparator of the present embodiment.
- step T1 the Early / Late2 signal is input from the binary phase comparator 45 to the counter 91 of the control logic circuit 9.
- the counter 91 determines whether the Early / Late2 signal is H level or L level.
- the counter 91 executes Step T2 when the Early / Late2 signal is at the H level, and the counter 91 executes Step T3 when the Early / Late2 signal is at the L level.
- step T2 the counter 91 counts up the held count value.
- the counter 91 obtains the delay amount X according to the counted up count value.
- the counter 91 inputs the count signal n indicating the delay amount X as a delay control signal DLY to the control terminal of the variable delay circuit 3 and inputs the count signal n to the input terminals of the logic circuits 92 and 93. Thereafter, Step T4 is executed.
- step T3 the counter 91 counts down the held count value.
- the counter 91 obtains the delay amount X according to the counted down count value.
- the counter 91 inputs the count signal n indicating the delay amount X as a delay control signal DLY to the control terminal of the variable delay circuit 3 and inputs the count signal n to the input terminals of the logic circuits 92 and 93. Thereafter, Step T4 is executed.
- step T4 the logic circuit 92 determines whether or not the delay amount X indicated by the count signal n is negative.
- the logic circuit 92 determines the value of the weighting control signal ME1 as a value obtained by subtracting 1 from the absolute value of the delay amount X, and sets the value of the weighting control signal ME2 as the absolute value of the delay amount X.
- the value of the weight control signal ME3 is determined to be a value obtained by adding 1 to the absolute value of the delay amount X.
- the logic circuit 92 determines the respective values of the weighting control signals ME1 to ME3 as 0.
- the logic circuit 92 generates weighting control signals ME1 to ME3 having the determined values, inputs the weighting control signal ME1 to the control terminal of the multiplier 5a, and inputs the weighting control signal ME2 to the control terminal of the multiplier 5b.
- the weight control signal ME3 is input to the control terminal of the multiplier 6c.
- the logic circuit 93 determines whether or not the delay amount X indicated by the count signal n is positive.
- the logic circuit 93 determines the value of the weighting control signal ML1 as a value obtained by subtracting 1 from the delay amount X, determines the value of the weighting control signal ML2 as the delay amount X, and performs weighting.
- the value of the control signal ML3 is determined to be a value obtained by adding 1 to the delay amount X.
- the logic circuit 93 determines each value of the weighting control signals ML1 to ML3 as 0.
- the logic circuit 93 generates weighting control signals ML1 to ML3 having the determined values, inputs the weighting control signal ML1 to the control terminal of the multiplier 6a, and inputs the weighting control signal ML2 to the control terminal of the multiplier 6b.
- the weight control signal ML3 is input to the control terminal of the multiplier 6c.
- FIG. 24 is an explanatory view showing an operation example of the present embodiment.
- FIG. 24 shows a case where the phase of the signal ⁇ 1 is delayed from the phase of the signal ⁇ 2.
- the Late1 signal becomes H level. Therefore, even if the value of the Late2 'signal becomes 0, the value of the Late1' signal becomes larger than 0. Accordingly, the Late1 'signal is output from the multiplexer 21 as the Late' signal. Therefore, the problem that the Late ′ signal does not show the phase difference between the signals ⁇ 1 and ⁇ 2 can be solved.
- the delay circuit 18 delays the delay signal ⁇ 2 ′ by a predetermined delay amount to generate the delay signal ⁇ 2 ′′.
- the delay circuit 19 delays the delay signal ⁇ 2 ′′ by a predetermined specific delay amount to generate a delay signal ⁇ 2 ′′ ′′.
- the binary phase comparator 44 discriminates the front-rear relationship between the phase of the signal ⁇ 1 and the phase of the delay signal ⁇ 2 ', and outputs an Early / Late1 signal indicating the front-rear relationship.
- the binary phase comparator 45 determines the front-rear relationship between the phase of the signal ⁇ 1 and the phase of the delayed signal ⁇ 2 ′′, and outputs an Early / Late2 signal indicating the front-rear relationship.
- the binary phase comparator 46 discriminates the front-rear relationship between the phase of the signal ⁇ 1 and the phase of the delayed signal ⁇ 2 '' ', and outputs an Early / Late3 signal indicating the front-rear relationship.
- the weighting unit assigns the weight value determined by the control logic circuit to each of the first determination result, the second determination result, and the third determination result.
- the output unit having the output terminals 7 and 8 and the multiplexers 20 and 21 indicates that the phase difference is the largest among the first discrimination result, the second discrimination result, and the third discrimination result to which the weighting unit has assigned weight values.
- the signal is output as an error signal.
- phase comparator When the phase comparator is used in a clock generation circuit such as a PLL circuit, the phases of the signals ⁇ 1 and ⁇ 2 are locked so that the phase difference between the feedback loop signals ⁇ 1 and ⁇ 2 is eliminated. In such a situation, the phase difference between the signals ⁇ 1 and ⁇ 2 can be determined more finely by intentionally changing the phase of the delay signal ⁇ 2 '.
- the counter 91 of the control logic circuit 9 varies the delay amount of the variable delay circuit 3 when a variation control signal that varies the phase of the delay signal ⁇ 2 'is input. At this time, it is desirable that the average value of the delay amount is zero.
- control logic circuit 9 randomly varies the delay amount as shown in FIG. 25A.
- control logic circuit 9 may repeat the process of gradually changing the delay amount to the first threshold value and then gradually changing the delay amount to the second threshold value.
- the control logic circuit 9 may change the delay amount in a triangular wave shape as shown in FIG. 25B, or may change the delay amount in a sine wave shape as shown in FIG. 25C.
- the phase difference between the signals ⁇ 1 and ⁇ 2 is determined from the magnitude relationship between the number of times the Early signal becomes H level and the number of times the Late signal becomes H level. It can be determined more finely. For example, if the number of times that the Late signal becomes H level is slightly larger than the number of times that the Early signal becomes H level, the signal ⁇ 1 is slightly delayed from the signal ⁇ 2. In this way, by intentionally changing the phase of the delay signal ⁇ 2, the phase difference between the signals ⁇ 1 and ⁇ 2 can be determined more finely.
- control logic circuit 9 when a variation control signal is input, the control logic circuit 9 varies the delay amount so that the average delay amount of the variable delay circuit 3 becomes zero.
- phase difference between the signals ⁇ 1 and ⁇ 2 can be determined more finely.
- FIG. 26 is a block diagram showing the PLL circuit of the present embodiment.
- the PLL circuit includes a phase comparator 101, a digital filter 102, a DCO (Digital Controlled Oscillator) 103, and a frequency divider 104.
- the phase comparator 101 has one of the configurations of the phase comparators described in the first to eleventh embodiments.
- the reference signal is input to the phase comparator 101 as the signal ⁇ 1 (or data signal Din).
- the digital filter 102 smoothes the error signal output from the phase comparator 101 and inputs the smoothed error signal to the DCO 103.
- the DCO 103 oscillates at a frequency corresponding to the input error signal, outputs a signal of the oscillated frequency as a control clock signal, and inputs the control clock signal to the frequency divider 104.
- the frequency divider 104 divides the input control clock signal by N and inputs the N-divided control clock signal to the phase comparator 101 as a signal ⁇ 2 (or clock signal ⁇ 2).
- CDR circuit can also be realized with the same configuration as the PLL circuit shown in FIG.
- the gain of the feedback loop that converges the phase difference between the two input signals to 0 can be made constant while suppressing increases in power consumption and circuit area.
- FIG. 27 is a block diagram showing the DLL circuit of this embodiment.
- the DLL circuit includes a phase comparator 101, a digital filter 102, a frequency divider 104, an input terminal 201, and a DCDL (Digital Voltage Controlled Delay Line: digital control delay line) 202.
- a phase comparator 101 a digital filter 102
- a frequency divider 104 an input terminal 201
- a DCDL Digital Voltage Controlled Delay Line: digital control delay line
- Digital filter 102 smoothes the error signal output from phase comparator 101, and inputs the smoothed error signal to DCDL 202.
- a reference clock signal is input to the input terminal 201, and the reference clock signal is input to the DCDL 202.
- the input terminal 201 is an example of a clock input unit.
- the DCDL 202 delays the input reference clock signal in accordance with the input error signal, outputs the delayed reference clock signal as a control clock signal, and inputs the control clock signal to the frequency divider 104. To do.
- the CDR circuit can also be realized with the same configuration as the DLL circuit shown in FIG.
- the gain of the feedback loop that converges the phase difference between the two input signals to 0 can be made constant while suppressing increases in power consumption and circuit area.
- variable delay circuit 3 delays the signal ⁇ 2, but it is only necessary to delay one of the signals ⁇ 1 and ⁇ 2.
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Abstract
A phase comparator which allows solution of the problem that a phase difference cannot be discriminated, while suppressing increase in power consumption and a circuit area. A variable delay circuit (3) adjusts the phase of a signal (φ2) to generate a delay signal (φ2'). A binary phase comparator (4) discriminates the front/rear relation between the phase of a signal (φ1) and that of the delay signal (φ2'), and outputs the discrimination result showing the front/rear relation. A control logic circuit (9) adjusts the delay amount of the variable delay circuit (3) on the basis of the discrimination result, and determines a weight value to be imparted to the discrimination result according to the adjusted delay amount. A weighting circuit imparts the determined weight value to the discrimination result. An output part outputs the discrimination result to which the weighting circuit imparts the weight value, as error signals showing the front/rear relation between the phase of the signal (φ1) and that of the signal (φ2) and the phase difference between the signals (φ1 and φ2).
Description
本発明は、デジタル型の位相比較器、PLL回路およびDLL回路に関し、特には、二つの入力信号の位相差を判別するデジタル型の位相比較器、PLL回路およびDLL回路に関する。
The present invention relates to a digital phase comparator, a PLL circuit, and a DLL circuit, and more particularly, to a digital type phase comparator, a PLL circuit, and a DLL circuit that determine a phase difference between two input signals.
位相固定ループ回路(Phase-Locked Loop:PLL)、遅延固定ループ回路(Delay-Locked Loop:DLL)およびクロックデータ再生回路(Clock and Data Recovery:CDR)などのクロック生成回路は、位相比較器を有している。このようなクロック生成回路では、この位相比較器から出力された信号に基づいて、フィードバック制御を行うことで、クロック信号を参照信号に同期させることができる。
Clock generation circuits such as phase-locked loop circuit (Phase-Locked Loop: PLL), delay-locked loop circuit (Delay-Locked Loop: DLL), and clock data recovery circuit (Clock and Data Recovery: CDR) have a phase comparator. is doing. In such a clock generation circuit, the clock signal can be synchronized with the reference signal by performing feedback control based on the signal output from the phase comparator.
位相比較器は、2つの入力信号の位相の前後関係(位相の進みまたは遅れ)や、その2つの入力信号の位相差(位相の進みまたは遅れの大きさ)を判別する。なお、位相比較器は、クロック生成回路に用いられる場合、クロック生成回路が生成したクロック信号と、参照信号(参照クロック信号または参照データ信号)の位相の前後関係や位相差を判別する。
The phase comparator determines the phase relationship (phase advance or delay) of two input signals and the phase difference (phase advance or delay magnitude) between the two input signals. Note that the phase comparator, when used in the clock generation circuit, determines the phase relationship and phase difference between the clock signal generated by the clock generation circuit and the reference signal (reference clock signal or reference data signal).
このような位相比較器には、アナログ型とデジタル型がある。なお、アナログ型位相比較器は、アナログ型クロック生成回路で用いられ、デジタル型位相比較器は、デジタル型クロック生成回路で用いられる。
Such phase comparators are classified into analog type and digital type. The analog phase comparator is used in an analog clock generation circuit, and the digital phase comparator is used in a digital clock generation circuit.
アナログ型位相比較器は、2つの入力信号の位相差を、電圧、電流またはパルス幅などの物理量で出力する。また、アナログ型位相比較器を用いるアナログ型のクロック生成回路では、チャージポンプ回路、フィルタ回路および発振器がアナログ回路で構成される。これらのアナログ回路では、設計、微細化、および、フィードバック制御のためのループパラメータの変更などが困難である。このため、近年では、デジタル型クロック生成回路が多く用いられており、これに伴い、デジタル型位相比較器の需要も多くなっている。
Analog phase comparator outputs the phase difference between two input signals as a physical quantity such as voltage, current or pulse width. In an analog clock generation circuit using an analog phase comparator, a charge pump circuit, a filter circuit, and an oscillator are configured by analog circuits. In these analog circuits, it is difficult to design, miniaturize, and change loop parameters for feedback control. For this reason, in recent years, digital type clock generation circuits are often used, and accordingly, the demand for digital type phase comparators is also increasing.
以下では、デジタル型位相比較器について説明する。
In the following, a digital phase comparator will be described.
デジタル型位相比較器は、2つの入力信号の位相の前後関係だけを判別可能なバイナリ型と、2つの入力信号の位相の前後関係だけでなく、その位相差を判別可能な多ビット型がある。なお、バイナリ型位相比較器は、2つの信号の位相の前後関係を示す2ビットのデジタル信号を出力する。また、多ビット型位相比較器は、2つの信号の位相差を示す複数ビットのデジタル信号を出力する。
The digital type phase comparator has a binary type that can determine only the phase relationship between two input signals and a multi-bit type that can determine not only the phase relationship between two input signals but also the phase difference between them. . The binary phase comparator outputs a 2-bit digital signal indicating the phase relationship between the two signals. The multi-bit type phase comparator outputs a multi-bit digital signal indicating the phase difference between the two signals.
バイナリ型位相比較器がPLL回路などに用いられると、クロック信号と参照信号との位相差が検出できないため、クロック生成回路における、2つの入力信号の位相差を0に収束させるフィードバックループの利得が一定にならないという問題があった。つまり、フィードバックループでは、位相差の大きさに応じてフィードバック量を変えることができないため、位相差が大きくても小さくても、フィードバック量が一定になるという問題があった。
When a binary phase comparator is used in a PLL circuit or the like, the phase difference between the clock signal and the reference signal cannot be detected. Therefore, the gain of the feedback loop that converges the phase difference between the two input signals to 0 in the clock generation circuit is There was a problem that it was not constant. That is, in the feedback loop, the feedback amount cannot be changed according to the magnitude of the phase difference, and there is a problem that the feedback amount becomes constant regardless of whether the phase difference is large or small.
より具体的には、位相差が大きい場合には、フィードバックループの利得が低くなり、位相差が小さい場合には、フィードバックループの利得が高くなる。したがって、位相差が大きい場合には、利得が低いために、フィードバックループにおける位相差の収束が遅くなり、位相差が小さい場合には、利得が高いために、フィードバックループの安定性が確保されず、クロック信号にジッタが発生するなどの問題が生じる。
More specifically, when the phase difference is large, the feedback loop gain is low, and when the phase difference is small, the feedback loop gain is high. Therefore, when the phase difference is large, the gain is low, so that the convergence of the phase difference in the feedback loop is slow, and when the phase difference is small, the gain is high and the stability of the feedback loop is not ensured. This causes problems such as jitter in the clock signal.
したがって、クロック生成回路には、多ビット型位相比較器が用いられることが望ましい。
Therefore, it is desirable to use a multi-bit type phase comparator for the clock generation circuit.
しかしながら、多ビット型位相比較器を用いて、位相差をN段階の分解能で判別するためには、少なくともN個のフリップフロップ回路と、N個の遅延回路と、Nビットのサーモメータコードをlog2Nビットのバイナリコードに変換するエンコーダとが必要となる。
However, in order to discriminate the phase difference with N stages of resolution using a multi-bit type phase comparator, at least N flip-flop circuits, N delay circuits, and an N-bit thermometer code are log2N. An encoder that converts to a binary bit code is required.
このため、位相比較器内の回路数が増加するので、位相比較器の消費電力および回路面積が増加する。したがって、クロック生成回路の消費電力および回路面積も増加するという問題があった。特に、位相差のダイナミックレンジを広く確保することと、位相差の分解能を細かくすることの両方を行う場合、Nが非常に大きくなるので、クロック生成回路の消費電力および回路面積が非常に大きくなる。
For this reason, since the number of circuits in the phase comparator increases, the power consumption and circuit area of the phase comparator increase. Therefore, there is a problem that the power consumption and circuit area of the clock generation circuit also increase. In particular, when both securing a wide dynamic range of the phase difference and making the resolution of the phase difference fine, N becomes very large, so that the power consumption and circuit area of the clock generation circuit become very large. .
特許文献1には、クロック生成回路の消費電力および回路面積の増加を抑制することが可能なタイミング調整器が記載されている。このタイミング調整回路は、遅延調整回路と、3個のラッチ回路を含み、以下のように動作する。
Patent Document 1 describes a timing adjuster that can suppress an increase in power consumption and circuit area of a clock generation circuit. This timing adjustment circuit includes a delay adjustment circuit and three latch circuits, and operates as follows.
遅延調整回路は、タイミング信号を遅延して第一のクロック信号を生成する。
The delay adjustment circuit generates the first clock signal by delaying the timing signal.
また、第一のラッチ回路は、第一クロック信号に基づいてデータ信号をラッチする。第二のラッチ回路は、第一のクロック信号が第一の遅延時間だけ遅延された第二のクロック信号に基づいて、データ信号をラッチする。第三のラッチ回路は、第一のクロック信号が第一の遅延時間より長い第二の遅延時間だけ遅延された第三のクロック信号に基づいて、データ信号をラッチする。
The first latch circuit latches the data signal based on the first clock signal. The second latch circuit latches the data signal based on the second clock signal obtained by delaying the first clock signal by the first delay time. The third latch circuit latches the data signal based on the third clock signal obtained by delaying the first clock signal by a second delay time longer than the first delay time.
また、タイミング調整回路は、第一ないし第三のラッチ回路から出力される信号が全て等しくなるように、遅延調整回路によるタイミング信号の遅延時間を調整する。
The timing adjustment circuit adjusts the delay time of the timing signal by the delay adjustment circuit so that the signals output from the first to third latch circuits are all equal.
これにより、タイミング信号とデータ信号の位相差が小さくなる。
This reduces the phase difference between the timing signal and the data signal.
このタイミング調整器を、クロック生成回路のバイナリ型位相比較器の前段に設ければ、クロック信号と参照信号との位相差が小さくなるので、一定のフィードバック量でも、フィードバックループの収束が遅くなるという問題や、フィードバックループの安定性が確保されないなどの問題を解決することができる。また、回路数も抑制できるので、クロック生成回路の消費電力および回路面積を抑制することが可能になる。
If this timing adjuster is provided in front of the binary phase comparator of the clock generation circuit, the phase difference between the clock signal and the reference signal is reduced, so that the convergence of the feedback loop is delayed even with a constant feedback amount. It is possible to solve problems such as problems and the stability of the feedback loop not being ensured. In addition, since the number of circuits can be suppressed, the power consumption and circuit area of the clock generation circuit can be suppressed.
特許文献1に記載のタイミング調整回路は、消費電力および回路面積の増加を抑制しながら、二つの信号のタイミングを調整することはできるが、位相差を判別することができないという問題があった。このため、例えば、クロック生成回路では、このタイミング調整回路とは別に、位相比較器を用いる必要があった。このため、装置構成が複雑になったり、タイミングの調整が終了するまで、フィードバックループの安定性が確保されなかったりする。
The timing adjustment circuit described in Patent Document 1 has a problem that the phase difference cannot be determined, although the timing of two signals can be adjusted while suppressing an increase in power consumption and circuit area. For this reason, for example, in the clock generation circuit, it is necessary to use a phase comparator separately from the timing adjustment circuit. For this reason, the stability of the feedback loop may not be ensured until the apparatus configuration becomes complicated or the timing adjustment is completed.
本発明の目的は、上記の課題である、消費電力および回路面積の増加を抑制しながら、位相差を判別することができないという問題を解決する位相比較器、PLL回路およびDLL回路を提供することである。
An object of the present invention is to provide a phase comparator, a PLL circuit, and a DLL circuit that solve the above-described problem that a phase difference cannot be determined while suppressing an increase in power consumption and circuit area. It is.
本発明による位相比較器は、第一入力信号が入力される第一入力手段と、第二入力信号が入力される第二入力手段と、前記第二入力手段に入力された第二入力信号の位相を調整して、調整入力信号を生成する調整手段と、前記第一入力手段に入力された第一入力信号の位相と、前記調整手段が生成した調整入力信号の位相との前後関係を判別し、該前後関係を示す判別結果を出力する判別手段と、前記判別手段から出力された判別結果が示す前後関係が変化するように、前記調整手段の調整量を調節していき、該調節した調整量に応じて、前記判別結果に付与する重み値を決定する制御手段と、前記判別手段から出力された判別結果に前記制御手段が決定した重み値を付与する重み付け手段と、前記重み付け手段が前記重み値を付与した判別結果を、前記第一入力信号の位相と前記第二入力信号の位相との前後関係と、前記第一入力信号および前記第二入力信号の位相差とを示す誤差信号として出力する出力手段と、を含む。
The phase comparator according to the present invention includes a first input unit to which a first input signal is input, a second input unit to which a second input signal is input, and a second input signal input to the second input unit. An adjustment unit that adjusts the phase to generate an adjustment input signal; and a front-rear relationship between the phase of the first input signal input to the first input unit and the phase of the adjustment input signal generated by the adjustment unit And adjusting the adjustment amount of the adjusting means so that the determination means for outputting the determination result indicating the context and the context indicated by the determination result output from the determination means are changed. Control means for determining a weight value to be given to the discrimination result according to an adjustment amount, weighting means for giving the weight value decided by the control means to the discrimination result output from the discrimination means, and the weighting means The weight given the weight value An output means for outputting the result as an error signal indicating the phase relationship between the phase of the first input signal and the phase of the second input signal and the phase difference between the first input signal and the second input signal; including.
また、本発明によるPLL回路は、前記位相比較器から出力された誤差信号を平滑化するフィルタ手段と、前記フィルタ手段が平滑化した誤差信号に応じた周波数で発振し、該発振した周波数の信号を前記第一入力信号または前記第二入力信号として前記位相比較器に入力する発振手段と、を含む。
Further, the PLL circuit according to the present invention includes a filter unit that smoothes the error signal output from the phase comparator, and oscillates at a frequency corresponding to the error signal smoothed by the filter unit. Oscillating means for inputting the signal to the phase comparator as the first input signal or the second input signal.
また、本発明によるDLL回路は、前記位相比較器と、クロック信号が入力されるクロック入力手段と、前記位相比較器から出力された誤差信号を平滑化するフィルタ手段と、前記フィルタ手段が平滑化した誤差信号に応じて、前記クロック入力手段に入力されたクロック信号を遅延し、該遅延したクロック信号を前記第一の入力信号または前記第二入力信号として前記位相比較器に入力する制御遅延手段と、を含む。
In the DLL circuit according to the present invention, the phase comparator, a clock input means to which a clock signal is input, a filter means for smoothing an error signal output from the phase comparator, and the filter means are smoothed. Control delay means for delaying the clock signal input to the clock input means in accordance with the error signal and inputting the delayed clock signal to the phase comparator as the first input signal or the second input signal. And including.
本発明によれば、消費電力および回路面積の増加を抑制しながら、位相差を判別することが可能になる。
According to the present invention, it is possible to determine a phase difference while suppressing an increase in power consumption and circuit area.
以下、本発明の実施形態について図面を参照して説明する。なお、以下の説明では、同じ機能を有する構成には同じ符号を付け、その説明を省略する場合がある。
Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, components having the same function may be denoted by the same reference numerals and description thereof may be omitted.
図1は、本発明の第一の実施形態の位相比較器の構成を示した回路図である。図1において、位相比較器は、入力端子1および2と、可変遅延回路3と、バイナリ型位相比較器4と、乗算器5および6を有する重み付け回路と、出力端子7および8を有する出力部と、制御ロジック回路9とを含む。
FIG. 1 is a circuit diagram showing the configuration of the phase comparator according to the first embodiment of the present invention. 1, the phase comparator includes input terminals 1 and 2, a variable delay circuit 3, a binary phase comparator 4, a weighting circuit having multipliers 5 and 6, and an output unit having output terminals 7 and 8. And a control logic circuit 9.
入力端子1には、信号φ1が入力され、その入力された信号φ1が出力される。入力端子2には、信号φ2が入力され、その入力された信号φ2が出力される。信号φ1およびφ2は、クロック信号である。
The signal φ1 is input to the input terminal 1, and the input signal φ1 is output. A signal φ2 is input to the input terminal 2, and the input signal φ2 is output. Signals φ1 and φ2 are clock signals.
なお、入力端子1は、第一入力手段の一例であり、信号φ1は、第一入力信号の一例である。また、入力端子2は、第二入力手段の一例であり、信号φ2は、第二入力信号の一例である。
The input terminal 1 is an example of a first input means, and the signal φ1 is an example of a first input signal. The input terminal 2 is an example of a second input means, and the signal φ2 is an example of a second input signal.
可変遅延回路3は、調整手段の一例である。可変遅延回路3の入力端子には、入力端子2が接続され、信号φ2が入力される。また、可変遅延回路3の制御端子には、制御ロジック回路9から、遅延制御信号DLYが入力される。遅延制御信号DLYの値は、可変遅延回路3の遅延量を示す。なお、遅延制御信号DLYは、複数ビットの信号である。また、遅延量は、調整量の一例である。遅延量は、正の値でもよいし、0でもよいし、負の値でもよい。
The variable delay circuit 3 is an example of adjusting means. An input terminal 2 is connected to an input terminal of the variable delay circuit 3 and a signal φ2 is input. The delay control signal DLY is input from the control logic circuit 9 to the control terminal of the variable delay circuit 3. The value of the delay control signal DLY indicates the delay amount of the variable delay circuit 3. The delay control signal DLY is a multi-bit signal. The delay amount is an example of an adjustment amount. The delay amount may be a positive value, 0, or a negative value.
可変遅延回路3は、信号φ2を遅延制御信号DLYが示す遅延量だけ遅延させることで、信号φ2の位相を調整して、遅延信号φ2’を生成する。具体的には、可変遅延回路3は、遅延量が正の場合、信号φ2の位相をその遅延量だけ遅らせ、遅延量が負の場合、信号φ2の位相をその遅延量の絶対値だけ進ませる。なお、遅延信号φ2’は、調整入力信号の一例である。
The variable delay circuit 3 adjusts the phase of the signal φ2 by delaying the signal φ2 by the delay amount indicated by the delay control signal DLY, and generates the delay signal φ2 ′. Specifically, the variable delay circuit 3 delays the phase of the signal φ2 by the delay amount when the delay amount is positive, and advances the phase of the signal φ2 by the absolute value of the delay amount when the delay amount is negative. . Note that the delay signal φ2 'is an example of an adjustment input signal.
可変遅延回路3は、その生成した遅延信号φ2’を自己の出力端子から出力する。
The variable delay circuit 3 outputs the generated delay signal φ2 'from its own output terminal.
バイナリ型位相比較器4は、判別手段の一例である。バイナリ型位相比較器4の第一の入力端子には、入力端子1が接続され、信号φ1が入力される。また、バイナリ型位相比較器4の第二の入力端子には、可変遅延回路3の出力端子が接続され、遅延信号φ2’が入力される。
The binary phase comparator 4 is an example of a discrimination unit. The input terminal 1 is connected to the first input terminal of the binary phase comparator 4 and the signal φ1 is input. Further, the output terminal of the variable delay circuit 3 is connected to the second input terminal of the binary type phase comparator 4, and the delay signal φ2 'is input thereto.
バイナリ型位相比較器4は、その入力された信号φ1の位相と遅延信号φ2’の位相とを比較して、信号φ1の位相と遅延信号φ2’の位相との前後関係を判別する。具体的には、バイナリ型位相比較器4は、信号φ1のエッジのタイミングと、遅延信号φ2’のエッジのタイミングとの前後関係を比較し、それらのタイミングの前後関係を、信号φ1の位相と遅延信号φ2’の位相との前後関係として判別する。
The binary type phase comparator 4 compares the phase of the input signal φ1 with the phase of the delay signal φ2 'to determine the front-to-back relationship between the phase of the signal φ1 and the phase of the delay signal φ2'. Specifically, the binary phase comparator 4 compares the timing relationship between the timing of the edge of the signal φ1 and the timing of the edge of the delay signal φ2 ′, and determines the timing relationship between the timing and the phase of the signal φ1. This is determined as the context of the phase of the delay signal φ2 ′.
バイナリ型位相比較器4は、その位相の前後関係を示す判別結果をEarly信号およびLate信号として出力する。具体的には、バイナリ型位相比較器4は、Early信号を自己の第一の出力端子から出力し、Late信号を自己の第二の出力端子から出力する。なお、Early信号およびLate信号のそれぞれは、1ビットのバイナリ値である。
The binary phase comparator 4 outputs a discrimination result indicating the phase relationship of the phase as an Early signal and a Late signal. Specifically, the binary phase comparator 4 outputs an Early signal from its own first output terminal and outputs a Late signal from its own second output terminal. Each of the Early signal and the Late signal is a 1-bit binary value.
ここで、HレベルのEarly信号が、信号φ1の位相が遅延信号φ2’の位相より進んでいることを示し、HレベルのLate信号が、信号φ1の位相が遅延信号φ2’の位相より遅れていることを示す。
Here, the H level Early signal indicates that the phase of the signal φ1 is ahead of the phase of the delay signal φ2 ′, and the H level Late signal indicates that the phase of the signal φ1 is behind the phase of the delay signal φ2 ′. Indicates that
図2Aは、バイナリ型位相比較器4の構成例を示した回路図である。図2Aにおいて、バイナリ型位相比較器4は、入力端子4aおよび4bと、フリップフロップ回路4cおよび4dと、出力端子4eおよび4fとを含む。
FIG. 2A is a circuit diagram showing a configuration example of the binary phase comparator 4. In FIG. 2A, binary type phase comparator 4 includes input terminals 4a and 4b, flip- flop circuits 4c and 4d, and output terminals 4e and 4f.
入力端子4aには、信号φ1が入力され、その入力された信号φ1が出力される。入力端子4bには、遅延信号φ2’が入力され、その入力された遅延信号φ2’が出力される。
The signal φ1 is input to the input terminal 4a, and the input signal φ1 is output. The delay signal φ2 'is input to the input terminal 4b, and the input delay signal φ2' is output.
フリップフロップ回路4cのD入力端子には、入力端子4aが接続され、信号φ1が入力される。また、フリップフロップ回路4cのCK入力端子には、入力端子4bが接続され、遅延信号φ2’が入力される。フリップフロップ回路4cは、その入力された信号φ1を、その入力された遅延信号φ2’のエッジのタイミングで保持し、その保持した信号φ1をEarly信号として自己のQ端子から出力する。なお、エッジは、立ち上がりエッジでもよいし、立ち下がりエッジでもよい。以下では、エッジは、全て立ち上がりエッジとする。
The input terminal 4a is connected to the D input terminal of the flip-flop circuit 4c, and the signal φ1 is input. Further, the input terminal 4b is connected to the CK input terminal of the flip-flop circuit 4c, and the delay signal φ2 'is input thereto. The flip-flop circuit 4c holds the input signal φ1 at the edge timing of the input delay signal φ2 ', and outputs the held signal φ1 as an Early signal from its own Q terminal. The edge may be a rising edge or a falling edge. In the following, all edges are rising edges.
また、フリップフロップ回路4dのD入力端子には、入力端子4bが接続され、遅延信号φ2’が入力される。また、フリップフロップ回路4dのCK入力端子には、入力端子4aが接続され、信号φ1が入力される。フリップフロップ回路4dは、遅延信号φ2’を信号φ1のエッジのタイミングで保持し、その保持した遅延信号φ2’をLate信号として自己のQ端子から出力する。
Also, the input terminal 4b is connected to the D input terminal of the flip-flop circuit 4d, and the delay signal φ2 'is input. The input terminal 4a is connected to the CK input terminal of the flip-flop circuit 4d, and the signal φ1 is input. The flip-flop circuit 4d holds the delay signal φ2 'at the edge timing of the signal φ1, and outputs the held delay signal φ2' from its Q terminal as a Late signal.
出力端子4eには、フリップフロップ回路4cのQ端子が接続され、Early信号が入力される。出力端子4eは、その入力されたEarly信号を出力する。
The Q terminal of the flip-flop circuit 4c is connected to the output terminal 4e, and the Early signal is input. The output terminal 4e outputs the input Early signal.
出力端子4fには、フリップフロップ回路4dのQ端子が接続され、Late信号が入力される。出力端子4fは、その入力されたLate信号を出力する。
The Q terminal of the flip-flop circuit 4d is connected to the output terminal 4f, and the Late signal is input. The output terminal 4f outputs the input Late signal.
これにより、図2Bで示すように、信号φ1の位相が遅延信号φ2’の位相より遅れている場合、Late信号がHレベルになり、Early信号がLレベルになる。また、信号φ1の位相が遅延信号φ2’の位相より進んでいる場合、Late信号がLレベルになり、Early信号がHレベルになる。
Thereby, as shown in FIG. 2B, when the phase of the signal φ1 is delayed from the phase of the delay signal φ2 ', the Late signal becomes H level and the Early signal becomes L level. When the phase of the signal φ1 is ahead of the phase of the delay signal φ2 ', the Late signal becomes L level and the Early signal becomes H level.
図1に戻る。乗算器5および6を有する重み付け回路は、バイナリ型位相比較器4から出力された判別結果に重み値を付与して、信号φ1の位相と信号φ2の位相との前後関係と、信号φ1およびφ2の位相差とを示す誤差信号を生成する。
Return to Figure 1. The weighting circuit having the multipliers 5 and 6 assigns a weight value to the discrimination result output from the binary phase comparator 4, and the relationship between the phase of the signal φ 1 and the phase of the signal φ 2, and the signals φ 1 and φ 2. An error signal indicating the phase difference between the two is generated.
乗算器5の入力端子には、バイナリ型位相比較器4の第一の出力端子が接続され、Early信号が入力される。また、乗算器5の制御端子には、制御ロジック回路9から重み付け制御信号MEが入力される。
The first output terminal of the binary phase comparator 4 is connected to the input terminal of the multiplier 5 and the Early signal is input. A weighting control signal ME is input from the control logic circuit 9 to the control terminal of the multiplier 5.
乗算器5は、その入力されたEarly信号に、その入力された重み付け制御信号MEの値を重み値として乗算して、Early’信号を生成する。乗算器5は、その生成したEarly’信号を自己の出力端子から出力する。
The multiplier 5 multiplies the input Early signal by the value of the input weight control signal ME as a weight value to generate an Early ′ signal. The multiplier 5 outputs the generated Early 'signal from its own output terminal.
乗算器6の入力端子には、バイナリ型位相比較器4の第二の出力端子が接続され、Late信号が入力される。また、乗算器6の制御端子には、制御ロジック回路9から重み付け制御信号MLが入力される。
The second output terminal of the binary phase comparator 4 is connected to the input terminal of the multiplier 6 and the Late signal is input. A weighting control signal ML is input from the control logic circuit 9 to the control terminal of the multiplier 6.
乗算器6は、その入力されたLate信号に、その入力された重み付け制御信号MLの値を重み値として乗算して、Late’信号を生成する。乗算器5は、その生成したLate’信号を自己の出力端子から出力する。
The multiplier 6 multiplies the input Late signal by the value of the input weighting control signal ML as a weight value to generate a Late ′ signal. The multiplier 5 outputs the generated Late ′ signal from its own output terminal.
Early’信号およびLate’信号が誤差信号となる。また、Early’信号またはLate’信号の値が、信号φ1およびφ2の位相差を示す。重み付け制御信号MEおよびMLは、複数ビットの信号である。したがって、誤差信号も複数ビットの信号である。
The Early 'signal and the Late' signal are error signals. The value of the Early ′ signal or the Late ′ signal indicates the phase difference between the signals φ1 and φ2. The weighting control signals ME and ML are multi-bit signals. Therefore, the error signal is also a multi-bit signal.
なお、重み付け回路は、Early信号およびLate信号に重み値を乗算していたが、Early信号およびLate信号に重み値を付与する方法は、乗算に限らず適宜変更可能である。例えば、重み付け回路は、算術積や算術加算などを行う算術回路や、論理積(AND)回路、否定論理積(NAND)回路、論理和(OR)回路および否定論理和(NOR)回路などの論理回路のうち少なくともいずれか一つを含み、その重み付け回路に含まれる回路を使用して、判別結果に重み値を付与する。
The weighting circuit multiplies the Early signal and the Late signal by the weight value, but the method of assigning the weight value to the Early signal and the Late signal is not limited to multiplication and can be changed as appropriate. For example, the weighting circuit is a logic circuit such as an arithmetic circuit that performs arithmetic product or arithmetic addition, a logical product (AND) circuit, a negative logical product (NAND) circuit, a logical sum (OR) circuit, or a negative logical sum (NOR) circuit. A weight value is given to the determination result by using at least one of the circuits and using a circuit included in the weighting circuit.
出力端子7および8を有する出力部は、重み付け回路から出力された誤差信号を出力する。具体的には、出力端子7には、乗算器5の出力端子が接続され、Early信号が入力される。出力端子7は、その入力されたEarly信号を出力する。また、出力端子8には、乗算器6の出力端子が接続され、Late信号が入力される。出力端子8は、その入力されたLate信号を出力する。
The output unit having the output terminals 7 and 8 outputs the error signal output from the weighting circuit. Specifically, the output terminal 7 is connected to the output terminal of the multiplier 5 and receives the Early signal. The output terminal 7 outputs the input Early signal. The output terminal 8 is connected to the output terminal of the multiplier 6 and receives the Late signal. The output terminal 8 outputs the input Late signal.
制御ロジック回路9は、制御手段の一例である。制御ロジック回路9は、遅延制御信号DLYを可変遅延回路3の制御端子に入力する。また、制御ロジック回路9は、重み付け制御信号MEを乗算器5の制御端子に入力し、重み付け制御信号MLを乗算器6の制御端子に入力する。
The control logic circuit 9 is an example of a control means. The control logic circuit 9 inputs the delay control signal DLY to the control terminal of the variable delay circuit 3. Further, the control logic circuit 9 inputs the weighting control signal ME to the control terminal of the multiplier 5 and inputs the weighting control signal ML to the control terminal of the multiplier 6.
また、制御ロジック回路9には、Early信号およびLate信号が入力される。制御ロジック回路9は、そのEarly信号およびLate信号に基づいて、遅延制御信号DLYが示す遅延量を調節する。
The Early signal and the Late signal are input to the control logic circuit 9. The control logic circuit 9 adjusts the delay amount indicated by the delay control signal DLY based on the Early signal and the Late signal.
具体的には、制御ロジック回路9は、遅延量を、Early信号およびLate信号が示す前後関係が変化するような値に調節する。このとき、信号φ1と遅延信号φ2’の位相が最も近づくので、そのときの遅延量が、信号φ1およびφ2の位相差を表わすためである。
Specifically, the control logic circuit 9 adjusts the delay amount to a value that changes the context indicated by the Early signal and the Late signal. At this time, the phases of the signal φ1 and the delay signal φ2 'are closest to each other, and the delay amount at that time represents the phase difference between the signals φ1 and φ2.
例えば、Early信号がHレベルの場合、制御ロジック回路9は、遅延量を、Early信号がLレベルに変化するまで徐々に小さくしていく。また、Late信号がHレベルの場合、制御ロジック回路9は、遅延量を、Late信号がLレベルに変化するまで、徐々に大きくしていく。
For example, when the Early signal is at H level, the control logic circuit 9 gradually decreases the delay amount until the Early signal changes to L level. When the Late signal is at the H level, the control logic circuit 9 gradually increases the delay amount until the Late signal changes to the L level.
また、制御ロジック回路9は、遅延制御信号DLYが示す遅延量に応じて、重み付け制御信号MEおよびMLの値を調節する。これにより、制御ロジック回路9は、遅延制御信号DLYが示す遅延量に応じて、重み付け回路が付与する重み値を調節することになる。
Further, the control logic circuit 9 adjusts the values of the weighting control signals ME and ML according to the delay amount indicated by the delay control signal DLY. As a result, the control logic circuit 9 adjusts the weight value provided by the weighting circuit in accordance with the delay amount indicated by the delay control signal DLY.
具体的には、遅延制御信号DLYが示す遅延量が正の場合、制御ロジック回路9は、その遅延量が大きいほど、重み付け制御信号MLの値を大きくしていく。また、制御ロジック回路9は、重み付け制御信号MEの値を0にする。
Specifically, when the delay amount indicated by the delay control signal DLY is positive, the control logic circuit 9 increases the value of the weighting control signal ML as the delay amount increases. Further, the control logic circuit 9 sets the value of the weighting control signal ME to 0.
また、遅延制御信号DLYが示す遅延量が負または0の場合、制御ロジック回路9は、その遅延量の絶対値が大きいほど、重み付け制御信号MEの値を大きくしていく。また、制御ロジック回路9は、重み付け制御信号MLの値を0にする。
When the delay amount indicated by the delay control signal DLY is negative or 0, the control logic circuit 9 increases the value of the weight control signal ME as the absolute value of the delay amount increases. Further, the control logic circuit 9 sets the value of the weighting control signal ML to 0.
次に動作を説明する。
Next, the operation will be described.
図3は、位相比較器の動作の一例を説明するための説明図である。なお、制御ロジック回路9は、遅延制御信号DLYが示す遅延量を0にした場合、重み付け制御信号MEおよびMLの値を1にするものとする。
FIG. 3 is an explanatory diagram for explaining an example of the operation of the phase comparator. Note that the control logic circuit 9 sets the values of the weighting control signals ME and ML to 1 when the delay amount indicated by the delay control signal DLY is set to 0.
また、制御ロジック回路9が遅延制御信号DLYの示す遅延量を正にした場合に、信号φ1の位相が遅延信号φ2’の位相より遅れていると、信号φ1の位相は、信号φ2の位相より大きく遅れていることになる。この場合、バイナリ型位相比較器4から出力されるLate信号がHレベルになる。
When the control logic circuit 9 makes the delay amount indicated by the delay control signal DLY positive and the phase of the signal φ1 is delayed from the phase of the delay signal φ2 ′, the phase of the signal φ1 is greater than the phase of the signal φ2. It will be greatly delayed. In this case, the Late signal output from the binary phase comparator 4 becomes H level.
このとき、制御ロジック回路9は、重み付け制御信号MLの値を1より大きくして、Late’信号の値を大きくする。ここで、制御ロジック回路9は、遅延量が大きいほど、重み付け制御信号MLの値を大きくする。なお、制御ロジック回路9は、重み付け制御信号MEを0にする。
At this time, the control logic circuit 9 makes the value of the weight control signal ML larger than 1 and increases the value of the Late ′ signal. Here, the control logic circuit 9 increases the value of the weighting control signal ML as the delay amount increases. The control logic circuit 9 sets the weighting control signal ME to 0.
また、制御ロジック回路9が遅延制御信号DLYの示す遅延量を0より小さくした場合に、信号φ1の位相が遅延信号φ2’の位相より進んでいると、信号φ1の位相は、信号φ2の位相より大きく進んでいることになる。この場合、バイナリ型位相比較器4から出力されるEarly信号がHレベルになる。
Further, when the control logic circuit 9 makes the delay amount indicated by the delay control signal DLY smaller than 0, if the phase of the signal φ1 is ahead of the phase of the delay signal φ2 ′, the phase of the signal φ1 is the phase of the signal φ2. It ’s a lot more advanced. In this case, the Early signal output from the binary phase comparator 4 becomes H level.
このとき、制御ロジック回路9は、重み付け制御信号MEの値を1より大きくして、Early’信号の値を大きくする。ここで、制御ロジック回路9は、遅延量の絶対値が大きいほど、重み付け制御信号MEの値を大きくする。なお、制御ロジック回路9は、重み付け制御信号MLを0にする。
At this time, the control logic circuit 9 increases the value of the early 'signal by increasing the value of the weighting control signal ME to be greater than 1. Here, the control logic circuit 9 increases the value of the weighting control signal ME as the absolute value of the delay amount increases. The control logic circuit 9 sets the weighting control signal ML to 0.
制御ロジック回路9がこのような制御を行うことで、Late’信号およびEarly’信号が、信号φ1の位相と信号φ2の位相と前後関係だけでなく、信号φ1およびφ2の位相差を示す多ビット信号になる。このため、位相比較器は、信号φ1とφ2の位相差を示す誤差信号を出力することが可能になる。
The control logic circuit 9 performs such control, so that the Late ′ signal and the Early ′ signal indicate not only the phase relationship between the phase of the signal φ1 and the phase of the signal φ2 but also the phase difference between the signals φ1 and φ2. Become a signal. For this reason, the phase comparator can output an error signal indicating the phase difference between the signals φ1 and φ2.
図4は、バイナリ型位相比較器4単体の動作と、図1で示した位相比較器との動作を比較するための説明図である。
FIG. 4 is an explanatory diagram for comparing the operation of the binary phase comparator 4 alone and the operation of the phase comparator shown in FIG.
バイナリ型位相比較器4単体では、信号φ1およびφ2の位相差の大きさに関わらず、Early信号およびLate信号は、LレベルまたはHレベルになる。
In the binary type phase comparator 4 alone, the Early signal and the Late signal become L level or H level regardless of the magnitude of the phase difference between the signals φ1 and φ2.
一方、図1で示した位相比較器では、可変遅延回路3の遅延量の絶対値が大きくなるほど、判別結果に付与される重み値が大きくなるので、信号φ1およびφ2の位相差が大きくなるほど、Early’信号またはLate’信号の値が大きくなる。したがって、Early’信号またはLate’の値が位相差を示すことになる。
On the other hand, in the phase comparator shown in FIG. 1, as the absolute value of the delay amount of the variable delay circuit 3 increases, the weight value given to the discrimination result increases, so that the phase difference between the signals φ1 and φ2 increases. The value of the Early ′ signal or the Late ′ signal is increased. Therefore, the Early ′ signal or the value of Late ′ indicates a phase difference.
次に効果を説明する。
Next, the effect will be explained.
本実施形態では、可変遅延回路3は、信号φ2の位相を調整して、遅延信号φ2’を生成する。バイナリ型位相比較器4は、信号φ1の位相と遅延信号φ2’の位相との前後関係を判別し、その前後関係を示す判別結果を出力する。制御ロジック回路9は、その判別結果が示す前後関係が変化するように、可変遅延回路3の遅延量を調節していき、その調節した遅延量に応じて、その判別結果に付与する重み値を決定する。重み付け回路は、その判別結果にその決定された重み値を付与する。出力部は、重み付け回路が重み値を付与した判別結果を、信号φ1の位相と信号φ2の位相との前後関係と、信号φ1およびφ2の位相差とを示す誤差信号として出力する。
In this embodiment, the variable delay circuit 3 adjusts the phase of the signal φ2 to generate the delay signal φ2 '. The binary phase comparator 4 discriminates the anteroposterior relationship between the phase of the signal φ1 and the phase of the delay signal φ2 'and outputs a discrimination result indicating the anteroposterior relationship. The control logic circuit 9 adjusts the delay amount of the variable delay circuit 3 so that the context indicated by the determination result changes, and according to the adjusted delay amount, assigns a weight value to the determination result. decide. The weighting circuit gives the determined weight value to the determination result. The output unit outputs the determination result obtained by assigning the weight value by the weighting circuit as an error signal indicating the front-rear relationship between the phase of the signal φ1 and the phase of the signal φ2 and the phase difference between the signals φ1 and φ2.
この場合、可変遅延回路3の遅延量が、判別結果が示す前後関係が変化するように調節される。また、その遅延量に応じた重み値がその判別結果に付与される。この遅延量は、信号φ1およびφ2の位相差を表わすため、重み値が乗算された判別結果は、信号φ1およびφ2の位相差を示す。位相差をN段階の分解能で判別するためには、遅延量をN段階に調節すればよいので、N個のフリップフロップ回路やN個の遅延回路を設けなくてもよくなる。よって、回路数を抑制することが可能になるので、消費電力および回路面積を抑制することが可能になる。したがって、消費電力および回路面積の増加を抑制しながら、位相差を判別することが可能になる。
In this case, the delay amount of the variable delay circuit 3 is adjusted so that the context indicated by the determination result changes. Further, a weight value corresponding to the delay amount is given to the determination result. Since this delay amount represents the phase difference between signals φ1 and φ2, the determination result multiplied by the weight value indicates the phase difference between signals φ1 and φ2. In order to discriminate the phase difference with N stages of resolution, the delay amount has only to be adjusted to N stages, so that it is not necessary to provide N flip-flop circuits or N delay circuits. Therefore, the number of circuits can be suppressed, so that power consumption and circuit area can be suppressed. Therefore, it is possible to determine the phase difference while suppressing increases in power consumption and circuit area.
次に第二の実施形態について説明する。
Next, a second embodiment will be described.
図5Aは、本実施形態の位相比較器の構成を示した回路図である。図5Aにおいて、位相比較器は、図1で示した構成に加え、論理ゲート10および11を有する出力制御部をさらに含む。また、乗算器5および6の制御端子に入力される重み付け制御信号MEおよびMLには、共通の信号が用いられる。以下、この共通の信号を、重み付け制御信号Mと称する。
FIG. 5A is a circuit diagram showing the configuration of the phase comparator of the present embodiment. 5A, the phase comparator further includes an output control unit having logic gates 10 and 11 in addition to the configuration shown in FIG. A common signal is used for the weighting control signals ME and ML input to the control terminals of the multipliers 5 and 6. Hereinafter, this common signal is referred to as a weighting control signal M.
論理ゲート10の第一の入力端子には、乗算器5の出力端子が接続され、Early’信号が入力される。また、論理ゲート10の第二の入力端子には、制御ロジック回路9からイネーブル信号ENEが入力される。
The output terminal of the multiplier 5 is connected to the first input terminal of the logic gate 10, and the Early 'signal is input. The enable signal ENE is input from the control logic circuit 9 to the second input terminal of the logic gate 10.
論理ゲート10は、その入力されたイネーブル信号ENEのレベルが所定のレベルであると、Early’信号の値を0にする。なお、所定のレベルは、論理ゲート10の種類に応じて定められる。
The logic gate 10 sets the value of the Early 'signal to 0 when the level of the input enable signal ENE is a predetermined level. The predetermined level is determined according to the type of the logic gate 10.
論理ゲート11の第一の入力端子には、乗算器6の出力端子が接続され、Late’信号が入力される。また、論理ゲート11の第二の入力端子には、制御ロジック回路9からイネーブル信号ENLが入力される。
The output terminal of the multiplier 6 is connected to the first input terminal of the logic gate 11 and the Late ′ signal is input. The enable signal ENL is input from the control logic circuit 9 to the second input terminal of the logic gate 11.
論理ゲート11は、その入力されたイネーブル信号ENLのレベルが特定のレベルであると、Late’信号の値を0にする。なお、特定のレベルは、論理ゲート11の種類に応じて定められる。
The logic gate 11 sets the value of the Late ′ signal to 0 when the level of the input enable signal ENL is a specific level. The specific level is determined according to the type of the logic gate 11.
制御ロジック回路9は、本実施形態では、可変遅延回路3の遅延量の絶対値に応じて、重み付け信号Mの値を調整する。具体的には、制御ロジック回路9は、可変遅延回路3の遅延量の絶対値が大きいほど、重み付け信号Mの値を大きくする。
In the present embodiment, the control logic circuit 9 adjusts the value of the weighting signal M according to the absolute value of the delay amount of the variable delay circuit 3. Specifically, the control logic circuit 9 increases the value of the weighting signal M as the absolute value of the delay amount of the variable delay circuit 3 increases.
ここで、図5Bで示すように、可変遅延回路3が信号φ2の位相を遅らせている場合、つまり、遅延制御信号DLYの値が正の場合に、Early信号がHレベルになっても、信号φ1の位相が信号φ2の位相より進んでいるとは判別できない。
Here, as shown in FIG. 5B, when the variable delay circuit 3 delays the phase of the signal φ2, that is, when the value of the delay control signal DLY is positive, even if the Early signal becomes H level, the signal It cannot be determined that the phase of φ1 is ahead of the phase of signal φ2.
このとき、制御ロジック回路9は、出力端子7から出力されるEarly’信号の値が0になるように、論理ゲート10を制御する。具体的には、遅延制御信号DLYが正の値の場合にEarly信号がHレベルであると、制御ロジック回路9は、所定のレベルのイネーブル信号ENEを論理ゲート10に入力して、論理ゲート10にEarly’信号の値を0にさせる。例えば、論理ゲート10が論理積回路の場合、制御ロジック回路9は、Lレベルのイネーブル信号ENEを論理ゲート10に入力する。
At this time, the control logic circuit 9 controls the logic gate 10 so that the value of the Early ′ signal output from the output terminal 7 becomes zero. Specifically, if the early signal is at the H level when the delay control signal DLY is a positive value, the control logic circuit 9 inputs the enable signal ENE of a predetermined level to the logic gate 10 and the logic gate 10 Causes the value of the Early ′ signal to be zero. For example, when the logic gate 10 is an AND circuit, the control logic circuit 9 inputs an L level enable signal ENE to the logic gate 10.
また、可変遅延回路3が信号φ2の位相を進ませている場合、つまり、遅延制御信号DLYの値が負の場合に、Late信号がHレベルになっても、信号φ1の位相が信号φ2の位相より遅れているとは判別できない。
Further, when the variable delay circuit 3 advances the phase of the signal φ2, that is, when the value of the delay control signal DLY is negative, the phase of the signal φ1 is the same as that of the signal φ2 even if the Late signal becomes H level. It cannot be determined that it is behind the phase.
このとき、制御ロジック回路9は、出力端子8から出力されるLate’信号の値が0になるように、論理ゲート11を制御する。具体的には、遅延制御信号DLYが負の値の場合にLate信号がHレベルであると、制御ロジック回路9は、特定のレベルのイネーブル信号ENEを論理ゲート11に出力して、論理ゲート11にLate’信号の値を0にさせる。例えば、論理ゲート11が論理積回路の場合、制御ロジック回路9は、Lレベルのイネーブル信号ENLを論理ゲート11に入力する。
At this time, the control logic circuit 9 controls the logic gate 11 so that the value of the Late ′ signal output from the output terminal 8 becomes zero. Specifically, when the Late control signal DLY is a negative value and the Late signal is at the H level, the control logic circuit 9 outputs the enable signal ENE of a specific level to the logic gate 11, and the logic gate 11 Let the value of the Late 'signal be zero. For example, when the logic gate 11 is an AND circuit, the control logic circuit 9 inputs an L level enable signal ENL to the logic gate 11.
これにより、論理ゲート10および11を有する出力制御部は、可変遅延回路3が信号φ2の位相を遅らせている場合に、信号φ1の位相が信号φ2の位相より進んでいることを示す誤差信号が出力部から出力されるのを停止する。また、出力制御部は、可変遅延回路3が信号φ2の位相を進ませている場合に、信号φ1の位相が信号φ2の位相より遅れていることを示す誤差信号が出力部から出力されるのを停止することになる。
As a result, the output control unit having logic gates 10 and 11 has an error signal indicating that the phase of signal φ1 is ahead of the phase of signal φ2 when variable delay circuit 3 delays the phase of signal φ2. Stop outputting from the output unit. In addition, when the variable delay circuit 3 advances the phase of the signal φ2, the output control unit outputs an error signal indicating that the phase of the signal φ1 is delayed from the phase of the signal φ2 from the output unit. Will stop.
なお、論理ゲート10および11は、図5Aでは、重み付け回路の後段に存在していたが、バイナリ型位相比較器4と重み付け回路とに介在してもよい。
Although the logic gates 10 and 11 exist in the subsequent stage of the weighting circuit in FIG. 5A, they may be interposed in the binary phase comparator 4 and the weighting circuit.
図5Cは、論理ゲート10および11がバイナリ型位相比較器4と重み付け回路とに介在する位相比較器の構成を示した回路図である。
FIG. 5C is a circuit diagram showing the configuration of the phase comparator in which the logic gates 10 and 11 are interposed between the binary phase comparator 4 and the weighting circuit.
この場合、論理ゲート10の第一の入力端子には、バイナリ型位相比較器4の第一の出力端子が接続され、Early信号が入力される。論理ゲート10の第二の入力端子には、制御ロジック回路9からイネーブル信号ENEが入力される。
In this case, the first output terminal of the binary phase comparator 4 is connected to the first input terminal of the logic gate 10 and the Early signal is input. The enable signal ENE is input from the control logic circuit 9 to the second input terminal of the logic gate 10.
また、論理ゲート11の第一の入力端子には、バイナリ型位相比較器4の第二の出力端子が接続され、Late信号が入力される。論理ゲート11の第二の入力端子には、制御ロジック回路9からイネーブル信号ENLが入力される。
Further, the second input terminal of the binary phase comparator 4 is connected to the first input terminal of the logic gate 11 and the Late signal is input. The enable signal ENL is input from the control logic circuit 9 to the second input terminal of the logic gate 11.
遅延制御信号DLYが正の値の場合にEarly信号がHレベルであると、制御ロジック回路9は、所定のレベルのイネーブル信号ENEを論理ゲート10に出力して、論理ゲート10にEarly信号をLレベルにさせる。
When the delay control signal DLY is a positive value and the Early signal is at the H level, the control logic circuit 9 outputs the enable signal ENE of a predetermined level to the logic gate 10 and outputs the Early signal to the logic gate 10 as L. Let the level.
また、遅延制御信号DLYが負の値の場合にLate信号がLレベルであると、制御ロジック回路9は、特定のレベルのイネーブル信号ENEを論理ゲート11に出力して、論理ゲート11にLate信号をLレベルにさせる。
Further, when the delay control signal DLY is a negative value and the Late signal is at the L level, the control logic circuit 9 outputs an enable signal ENE of a specific level to the logic gate 11, and outputs the Late signal to the logic gate 11. To the L level.
この場合でも、出力制御部は、可変遅延回路3が信号φ2の位相を遅らせている場合に、信号φ1の位相が信号φ2の位相より進んでいることを示す誤差信号が出力部から出力されるのを停止する。また、出力制御部は、可変遅延回路3が信号φ2の位相を進ませている場合に、信号φ1の位相が信号φ2の位相より遅れていることを示す誤差信号が出力部から出力されるのを停止することになる。
Even in this case, when the variable delay circuit 3 delays the phase of the signal φ2, the output control unit outputs an error signal indicating that the phase of the signal φ1 is ahead of the phase of the signal φ2 from the output unit. To stop. In addition, when the variable delay circuit 3 advances the phase of the signal φ2, the output control unit outputs an error signal indicating that the phase of the signal φ1 is delayed from the phase of the signal φ2 from the output unit. Will stop.
次に効果を説明する。
Next, the effect will be explained.
本実施形態では、出力制御部は、可変遅延回路3が信号φ2の位相を遅らせている場合に、信号φ1の位相が信号φ2の位相より進んでいることを示す誤差信号が出力部から出力されるのを停止する。また、出力制御部は、可変遅延回路3が信号φ2の位相を進ませている場合に、信号φ1の位相が信号φ2の位相より遅れていることを示す誤差信号が出力部から出力されるのを停止する。
In this embodiment, when the variable delay circuit 3 delays the phase of the signal φ2, the output control unit outputs an error signal indicating that the phase of the signal φ1 is ahead of the phase of the signal φ2 from the output unit. To stop. In addition, when the variable delay circuit 3 advances the phase of the signal φ2, the output control unit outputs an error signal indicating that the phase of the signal φ1 is delayed from the phase of the signal φ2 from the output unit. To stop.
この場合、信号φ1およびφ2の前後関係の判別が不確かなときに、その前後関係を示す判別結果が出力されることを抑制することが可能になる。
In this case, when it is uncertain whether the signals φ1 and φ2 are in the context, it is possible to suppress the output of the determination result indicating the context.
次に第三の実施形態について説明する。
Next, a third embodiment will be described.
図6は、本実施形態の位相比較器の構成を示した回路図である。図6において、位相比較器は、可変遅延回路3と、バイナリ型位相比較器41とを含む。
FIG. 6 is a circuit diagram showing the configuration of the phase comparator of the present embodiment. In FIG. 6, the phase comparator includes a variable delay circuit 3 and a binary type phase comparator 41.
図1で示したバイナリ型位相比較器4は、誤差信号として、Early信号およびLate信号を出力していたが、図6で示したバイナリ型位相比較器41は、誤差信号として、Early/Late信号を出力する。Early/Late信号は、Hレベルの場合、信号φ1の位相が遅延信号φ2’の位相より進んでいることを示し、Lレベルの場合、信号φ1の位相が遅延信号φ2’の位相より遅れいていることを示す。なお、Early/Late信号は、Hレベルの場合、信号φ1の位相が遅延信号φ2’の位相より遅れていることを示し、Lレベルの場合、信号φ1の位相が遅延信号φ2’の位相より進んでいることを示してもよい。
The binary type phase comparator 4 shown in FIG. 1 outputs the Early signal and the Late signal as error signals, but the binary type phase comparator 41 shown in FIG. 6 outputs the Early / Late signal as the error signal. Is output. When the Early / Late signal is at the H level, it indicates that the phase of the signal φ1 is ahead of the phase of the delay signal φ2 ′, and when it is at the L level, the phase of the signal φ1 is delayed from the phase of the delay signal φ2 ′. It shows that. When the Early / Late signal is at the H level, it indicates that the phase of the signal φ1 is delayed from the phase of the delay signal φ2 ′. When the Early / Late signal is at the L level, the phase of the signal φ1 is advanced from the phase of the delay signal φ2 ′. You may show that
図7Aは、バイナリ型位相比較器41の構成例を示した回路図である。図7Aにおいて、バイナリ型位相比較器41は、入力端子41aおよび41bと、フリップフロップ回路41cと、出力端子41dとを含む。
FIG. 7A is a circuit diagram showing a configuration example of the binary phase comparator 41. In FIG. 7A, the binary phase comparator 41 includes input terminals 41a and 41b, a flip-flop circuit 41c, and an output terminal 41d.
入力端子41aには、信号φ1が入力され、その入力された信号φ1を出力する。入力端子41bには、遅延信号φ2’が入力され、その入力された遅延信号φ2’を出力する。
The signal φ1 is input to the input terminal 41a, and the input signal φ1 is output. The delay signal φ2 ′ is input to the input terminal 41b, and the input delay signal φ2 ′ is output.
フリップフロップ回路41cのD入力端子には、入力端子4aが接続され、信号φ1が入力される。また、フリップフロップ回路41cのCK入力端子には、入力端子4bが接続され、遅延信号φ2’が入力される。フリップフロップ回路41cは、その入力された信号φ1を、その入力された遅延信号φ2’のエッジのタイミングで保持し、その保持した信号φ1を、Early/Late信号として自己のQ端子から出力する。
The input terminal 4a is connected to the D input terminal of the flip-flop circuit 41c, and the signal φ1 is input. Further, the input terminal 4b is connected to the CK input terminal of the flip-flop circuit 41c, and the delay signal φ2 'is input thereto. The flip-flop circuit 41c holds the input signal φ1 at the edge timing of the input delay signal φ2 ', and outputs the held signal φ1 from its Q terminal as an Early / Late signal.
出力端子41dは、フリップフロップ回路41cのQ端子が接続され、Early/Late信号が入力される。出力端子41dは、その入力されたEarly/Late信号を出力する。
The output terminal 41d is connected to the Q terminal of the flip-flop circuit 41c and receives the Early / Late signal. The output terminal 41d outputs the input Early / Late signal.
これにより、図7Bで示すように、Early/Late信号は、信号φ1の位相が遅延信号φ2’の位相より遅れている場合に、Lレベルになり、信号φ1の位相が遅延信号φ2’の位相より進んでいる場合に、Hレベルになる。
Thus, as shown in FIG. 7B, the Early / Late signal becomes L level when the phase of the signal φ1 is delayed from the phase of the delay signal φ2 ′, and the phase of the signal φ1 is the phase of the delay signal φ2 ′. When it is more advanced, it becomes H level.
図8は、本実施形態の位相比較器のより詳細な構成を示した回路図である。図8において、位相比較器は、入力端子1および2と、可変遅延回路3と、乗算器5および6と、出力端子7および8と、制御ロジック回路9と、分離部12と、バイナリ型位相比較器41とを含む。
FIG. 8 is a circuit diagram showing a more detailed configuration of the phase comparator of the present embodiment. In FIG. 8, the phase comparator includes input terminals 1 and 2, variable delay circuit 3, multipliers 5 and 6, output terminals 7 and 8, control logic circuit 9, separator 12, and binary phase. And a comparator 41.
バイナリ型位相比較器41は、判別手段の一例である。バイナリ型位相比較器41の第一の入力端子には、入力端子1が接続され、信号φ1が入力される。また、バイナリ型位相比較器41の第二の入力端子には、可変遅延回路3の出力端子が接続され、遅延信号φ2’が入力される。
The binary phase comparator 41 is an example of a discrimination unit. The input terminal 1 is connected to the first input terminal of the binary phase comparator 41 and the signal φ1 is input. Further, the output terminal of the variable delay circuit 3 is connected to the second input terminal of the binary phase comparator 41, and the delay signal φ2 'is input thereto.
バイナリ型位相比較器41は、その入力された信号φ1の位相と遅延信号φ2’の位相とを比較して、信号φ1の位相と遅延信号φ2’の位相の前後関係を判別する。バイナリ型位相比較器4は、その前後関係を示す判別結果を、Early/Late信号として自己の出力端子から出力する。
The binary type phase comparator 41 compares the phase of the input signal φ1 and the phase of the delay signal φ2 'to determine the front-rear relationship between the phase of the signal φ1 and the phase of the delay signal φ2'. The binary phase comparator 4 outputs a discrimination result indicating the context as an Early / Late signal from its own output terminal.
分離部12の入力端子には、バイナリ型位相比較器41の出力端子が接続され、Early/Late信号が入力される。
The output terminal of the binary type phase comparator 41 is connected to the input terminal of the separation unit 12 and the Early / Late signal is input.
分離部12は、その入力されたEarly/Late信号から、Early信号とLate信号とを生成する。例えば、分離部12は、Early/Late信号をEarly信号として生成し、Early/Late信号のレベルを反転させた信号をLate信号として生成する。
The separation unit 12 generates an Early signal and a Late signal from the input Early / Late signal. For example, the separation unit 12 generates an Early / Late signal as an Early signal, and generates a signal obtained by inverting the level of the Early / Late signal as a Late signal.
分離部12は、その生成したEarly信号を、自己の第一の出力端子から出力し、その生成したLate信号を、自己の第二の出力端子から出力する。
The separation unit 12 outputs the generated Early signal from its own first output terminal, and outputs the generated Late signal from its own second output terminal.
乗算器5の入力端子には、分離部12の第一の出力端子が接続され、Early信号が入力される。また、乗算器6の入力端子には、分離部12の第二の出力端子が接続され、Late信号が入力される。
The first output terminal of the separation unit 12 is connected to the input terminal of the multiplier 5 and the Early signal is input. The second output terminal of the separation unit 12 is connected to the input terminal of the multiplier 6 and the Late signal is input.
なお、分離部12は、Early/Late信号は、単純に二つに分離し、その一方のEarly/Late信号を自己の第一の出力端子から出力し、他方のEarly/Late信号を自己の第二の出力端子から出力してもよい。この場合、乗算器6は、自己の入力端子に入力されたEarly/Late信号を反転させて、Late信号を生成する。
The separation unit 12 simply separates the Early / Late signal into two, outputs one Early / Late signal from its own first output terminal, and outputs the other Early / Late signal to its first Early / Late signal. You may output from two output terminals. In this case, the multiplier 6 inverts the Early / Late signal input to its own input terminal to generate a Late signal.
また、本実施形態で説明した位相比較器は、図9Aで示すように、第二の実施形態で説明した、論理ゲート10および11を有する出力制御部をさらに含んでいてもよい。さらに、出力制御部は、図9Bで示すように、分離部12と重み付け回路とに介在してもよい。この場合、論理ゲート10の第一の入力端子には、分離部12の第一の出力端子が接続され、Early信号が入力される。また、論理ゲート11の第一の入力端子には、分離部12の第二の出力端子が接続され、Late信号が入力される。
Further, the phase comparator described in the present embodiment may further include an output control unit having the logic gates 10 and 11 described in the second embodiment, as shown in FIG. 9A. Further, the output control unit may be interposed between the separation unit 12 and the weighting circuit as shown in FIG. 9B. In this case, the first input terminal of the logic gate 10 is connected to the first output terminal of the separation unit 12 and the Early signal is input. The second input terminal of the separation unit 12 is connected to the first input terminal of the logic gate 11 and the Late signal is input.
次に効果を説明する。
Next, the effect will be explained.
本実施形態でも、第一の実施形態と同様に、消費電力および回路面積を抑制しながら、位相差を判別することが可能になる。また、バイナリ型位相比較器41内のフリップフロップ回路の数が、図1で示したバイナリ型位相比較器4内のフリップフロップ回路の数より少ないので、消費電力および回路面積の増加をさらに抑制することが可能になる。
In this embodiment as well, as in the first embodiment, it is possible to determine the phase difference while suppressing power consumption and circuit area. Further, since the number of flip-flop circuits in the binary phase comparator 41 is smaller than the number of flip-flop circuits in the binary phase comparator 4 shown in FIG. 1, the increase in power consumption and circuit area is further suppressed. It becomes possible.
次に第四の実施形態について説明する。
Next, a fourth embodiment will be described.
図10は、本実施形態の位相比較器の構成を示した回路図である。図10において、位相比較器は、可変遅延回路3と、多ビット型位相比較器42とを含む。
FIG. 10 is a circuit diagram showing the configuration of the phase comparator of the present embodiment. In FIG. 10, the phase comparator includes a variable delay circuit 3 and a multi-bit type phase comparator 42.
多ビット型位相比較器42は、単体でも、信号φ1およびφ2の位相差を判別することが可能であるが、本実施形態では、可変遅延回路3を導入することで、その判別可能な位相差の分解能を向上させることと、その判別可能な位相差の範囲を大きくすることが可能になる。
The multi-bit type phase comparator 42 can determine the phase difference between the signals φ1 and φ2 by itself, but in this embodiment, by introducing the variable delay circuit 3, the phase difference that can be determined is determined. And the range of the phase difference that can be discriminated can be increased.
図11Aは、多ビット型位相比較器42の構成例を示した回路図である。図11Aにおいて、多ビット型位相比較器42は、入力端子42aおよび42bと、遅延回路42c1ないし42c5と、フリップフロップ回路42d1ないし42d6と、エンコーダ42eと、出力端子42fとを含む。
FIG. 11A is a circuit diagram showing a configuration example of the multi-bit type phase comparator 42. In FIG. 11A, multibit type phase comparator 42 includes input terminals 42a and 42b, delay circuits 42c1 to 42c5, flip-flop circuits 42d1 to 42d6, encoder 42e, and output terminal 42f.
入力端子42aには、信号φ1が入力され、その入力された信号φ1が出力される。入力端子42bには、遅延信号φ2’が入力され、その入力された遅延信号φ2’が出力される。
The signal φ1 is input to the input terminal 42a, and the input signal φ1 is output. The delay signal φ2 'is input to the input terminal 42b, and the input delay signal φ2' is output.
遅延回路42c1ないし42c5のそれぞれは、互いに直列に接続される。遅延回路42c1ないし42c5のそれぞれは、入力端子42に入力された信号φ1を、予め定められた定遅延量だけ遅延する。以下、遅延回路42c1ないし42c5のそれぞれで遅延された信号φ1を、遅延量の少ない方(遅延回路42c1)から順に、信号φ1’、信号φ1’’、信号φ1’’’、信号φ1’’’’および信号φ1’’’’’と称する。
The delay circuits 42c1 to 42c5 are connected in series with each other. Each of the delay circuits 42c1 to 42c5 delays the signal φ1 input to the input terminal 42 by a predetermined constant delay amount. Hereinafter, the signal φ1 delayed in each of the delay circuits 42c1 to 42c5 is sequentially input from the signal having the smaller delay amount (delay circuit 42c1) to the signal φ1 ′, the signal φ1 ″, the signal φ1 ′ ″, and the signal φ1 ′ ″. 'And signal φ1' '' ''.
フリップフロップ回路42d1ないし42d6のそれぞれのD入力端子には、フリップフロップ回路42d1から順に、信号φ1、信号φ1’、信号φ1’’、信号φ1’’’、信号φ1’’’’および信号φ1’’’’’のそれぞれが入力される。
A signal φ1, a signal φ1 ′, a signal φ1 ″, a signal φ1 ′ ″, a signal φ1 ″ ″, and a signal φ1 ′ are sequentially input from the flip-flop circuit 42d1 to the D input terminals of the flip-flop circuits 42d1 to 42d6. Each of '' '' is entered.
また、フリップフロップ回路42d1ないし42d6のそれぞれのCK入力端子には、入力端子42bが接続され、遅延信号φ2’が入力される。
Also, the input terminal 42b is connected to each CK input terminal of the flip-flop circuits 42d1 to 42d6, and the delay signal φ2 'is input.
フリップフロップ回路42d1ないし42d6のそれぞれは、自己のD入力端子に入力された信号を、自己のCK入力端子に入力された遅延信号φ2’のエッジのタイミングで保持し、その保持した信号を、自己のQ端子から出力する。
Each of the flip-flop circuits 42d1 to 42d6 holds the signal input to its own D input terminal at the timing of the edge of the delayed signal φ2 ′ input to its own CK input terminal, and holds the held signal as its own signal. Output from the Q terminal.
これにより、フリップフロップ回路42d1ないし42d6のそれぞれは、その入力された信号の位相が遅延信号φ2’の位相よりも進んでいる場合には、Hレベルの信号を出力し、その入力された信号の位相が遅延信号φ2’の位相よりも遅れている場合には、Lレベルの信号を出力する。
Thus, each of the flip-flop circuits 42d1 to 42d6 outputs an H level signal when the phase of the input signal is ahead of the phase of the delay signal φ2 ′, and When the phase is behind the phase of the delay signal φ2 ′, an L level signal is output.
以下、フリップフロップ回路42dnから出力された信号を出力信号Qmと称する。mは、1から6までの整数である。
Hereinafter, the signal output from the flip-flop circuit 42dn is referred to as an output signal Qm. m is an integer from 1 to 6.
この出力信号Q1ないしQ6は、信号φ1および遅延信号φ2’の位相差を、サーモメータコードで表したものになる。なお、サーモメータコードとは、Hレベルの信号の数で値を表したコードである。
The output signals Q1 to Q6 represent the phase difference between the signal φ1 and the delay signal φ2 'by a thermometer code. The thermometer code is a code that represents a value by the number of H level signals.
エンコーダ42eは、少なくともフリップフロップ回路の段数と同じ数の入力端子を有し、各入力端子には、フリップフロップ回路42d1ないし42d6のそれぞれのQ端子が接続され、出力信号Q1ないしQ6のそれぞれが入力される。
The encoder 42e has at least the same number of input terminals as the number of stages of the flip-flop circuits. The Q terminals of the flip-flop circuits 42d1 to 42d6 are connected to the input terminals, and the output signals Q1 to Q6 are input. Is done.
エンコーダ42eは、そのサーモメータコードである出力信号Q1ないしQ6をバイナリコードに変換して、出力信号Code生成する。エンコーダ42eは、出力信号Codeを自己の出力端子から出力する。
The encoder 42e converts the output signals Q1 to Q6, which are thermometer codes, into binary codes, and generates an output signal Code. The encoder 42e outputs the output signal Code from its own output terminal.
なお、位相比較器が位相差を示す信号をサーモメータコードで出力する場合には、エンコーダ42eはなくてもよい。また、サーモメータコードである出力信号Q1ないしQ6、または、出力信号Codeが、信号φ1の位相と信号φ2の位相との前後関係と、信号φ1および遅延信号φ2’の位相差を示す判別結果となる。
When the phase comparator outputs a signal indicating a phase difference with a thermometer code, the encoder 42e may not be provided. The output signals Q1 to Q6, which are thermometer codes, or the output signal Code is a discrimination result indicating the front-rear relationship between the phase of the signal φ1 and the phase of the signal φ2, and the phase difference between the signal φ1 and the delayed signal φ2 ′. Become.
図11Bは、多ビット型位相比較器42の動作例を示した説明図である。図11Bで示したように、遅延信号φ2’のエッジが、信号φ1’’のエッジと信号φ1’’’のエッジとの間にある場合、出力信号Q1ないしQ3は、Hレベルになり、出力信号Q4ないしQ6は、Lレベルになる。この場合、Hレベルの数が3なので、エンコーダ42eは、3を位相差として示す出力信号Codeを生成する。
FIG. 11B is an explanatory view showing an operation example of the multi-bit type phase comparator 42. As shown in FIG. 11B, when the edge of the delay signal φ2 ′ is between the edge of the signal φ1 ″ and the edge of the signal φ1 ′ ″, the output signals Q1 to Q3 become H level and output Signals Q4 to Q6 are at the L level. In this case, since the number of H levels is 3, the encoder 42e generates an output signal Code indicating 3 as a phase difference.
また、可変遅延回路3の遅延量は、信号φ2と遅延信号φ2’の位相差を示すので、この出力信号Codeに、可変遅延回路3の遅延量に応じた重み値が加算されれば、その重み値が加算された出力信号Code(出力信号Code’と称する)の値が、信号φ1およびφ2の位相差を示すことになる。
Since the delay amount of the variable delay circuit 3 indicates the phase difference between the signal φ2 and the delay signal φ2 ′, if a weight value corresponding to the delay amount of the variable delay circuit 3 is added to the output signal Code, The value of the output signal Code (referred to as output signal Code ′) to which the weight value has been added indicates the phase difference between the signals φ1 and φ2.
多ビット型位相比較器42が判別する位相差の分解能は、多ビット型位相比較器42に含まれる遅延回路の1段あたりの遅延量(定遅延量)で決定される。このため、可変遅延回路3の遅延量が定遅延量よりも小さい単位で調整されれば、出力信号Code’の値は、多ビット型位相比較器42が判別する位相差の分解能より細かい値を有することになる。したがって、信号φ1およびφ2の位相差をより精度よく判別することが可能になる。
The resolution of the phase difference determined by the multi-bit type phase comparator 42 is determined by the delay amount (constant delay amount) per stage of the delay circuit included in the multi-bit type phase comparator 42. Therefore, if the delay amount of the variable delay circuit 3 is adjusted in units smaller than the constant delay amount, the value of the output signal Code ′ is set to a value finer than the resolution of the phase difference determined by the multi-bit type phase comparator 42. Will have. Therefore, the phase difference between signals φ1 and φ2 can be determined with higher accuracy.
また、多ビット型位相比較器42が検出可能な位相差の範囲は、多ビット型位相比較器42に含まれる遅延回路の1段あたりの遅延量と遅延回路の段数との積で算出される値となる。以下、この値を検出可能範囲と称する。
The range of the phase difference that can be detected by the multibit type phase comparator 42 is calculated by the product of the delay amount per stage of the delay circuit included in the multibit type phase comparator 42 and the number of stages of the delay circuit. Value. Hereinafter, this value is referred to as a detectable range.
例えば、信号φ1の位相が遅延信号φ2の位相より遅れていると、出力信号Q1ないしQ6の全てがLレベルになるので、信号φ1およびφ2の位相差を判別することができない。
For example, if the phase of the signal φ1 is delayed from the phase of the delay signal φ2, all the output signals Q1 to Q6 are at the L level, so that the phase difference between the signals φ1 and φ2 cannot be determined.
このような場合、可変遅延回路3が、遅延信号φ2’の位相を信号φ1の位相より遅らせることで、フリップフロップ回路42d1ないし42d6の出力信号Q1ないしQ6のいずれかをHレベルにすれば、出力信号Codeが位相差を示すことになる。したがって、出力信号Code’にて信号φ1およびφ2の位相差を判別することが可能になる。
In such a case, if the variable delay circuit 3 delays the phase of the delay signal φ2 ′ from the phase of the signal φ1 to set any one of the output signals Q1 to Q6 of the flip-flop circuits 42d1 to 42d6 to the H level, the output The signal Code indicates the phase difference. Therefore, the phase difference between the signals φ1 and φ2 can be determined from the output signal Code ′.
また、信号φ1の位相が遅延信号φ2’の位相より検出可能範囲以上に進んでいると、つまり、信号φ1’’’’’が遅延信号φ2’より進んでいると、そのフリップフロップ回路42d1ないし42d6の出力信号Q1ないしQ6の全てがHレベルになるので、信号φ1およびφ2の位相差を判別することができない。
Further, if the phase of the signal φ1 has advanced beyond the detectable range from the phase of the delay signal φ2 ′, that is, if the signal φ1 ″ ″ ′ has advanced from the delay signal φ2 ′, the flip-flop circuit 42d1 to Since all of the output signals Q1 to Q6 of 42d6 are at the H level, the phase difference between the signals φ1 and φ2 cannot be determined.
このような場合、可変遅延回路3が、遅延信号φ2’の位相を信号φ1’’’’’の位相より進ませることで、フリップフロップ回路42d1ないし42d6の出力信号Q1ないしQ6のいずれかをLレベルにすれば、出力信号Codeが位相差を示すことになる。したがって、出力信号Code’にて、信号φ1およびφ2の位相差を判別することが可能になる。
In such a case, the variable delay circuit 3 advances the phase of the delay signal φ2 ′ from the phase of the signal φ1 ′ ″ ″ so that any one of the output signals Q1 to Q6 of the flip-flop circuits 42d1 to 42d6 is L When the level is set, the output signal Code indicates a phase difference. Therefore, the phase difference between the signals φ1 and φ2 can be determined from the output signal Code ′.
図12は、本実施形態の位相比較器のより詳細な構成を示した回路図である。図12において、位相比較器は、入力端子1および2と、可変遅延回路3と、制御ロジック回路9と、加算器13と、出力端子14と、多ビット型位相比較器42とを含む。
FIG. 12 is a circuit diagram showing a more detailed configuration of the phase comparator of the present embodiment. 12, the phase comparator includes input terminals 1 and 2, a variable delay circuit 3, a control logic circuit 9, an adder 13, an output terminal 14, and a multi-bit type phase comparator 42.
可変遅延回路3の遅延量は、多ビット型位相比較器42が判別する位相差の分解能より小さい単位で設定可能である。
The delay amount of the variable delay circuit 3 can be set in units smaller than the resolution of the phase difference determined by the multi-bit type phase comparator 42.
多ビット型位相比較器42は、判別手段の一例である。多ビット型位相比較器42の第一の入力端子には、入力端子1が接続され、信号φ1が入力される。また、多ビット型位相比較器42の第二の入力端子には、可変遅延回路3の出力端子が接続され、遅延信号φ2’が入力される。
The multi-bit type phase comparator 42 is an example of a discrimination unit. The input terminal 1 is connected to the first input terminal of the multi-bit type phase comparator 42 and the signal φ1 is input. Further, the output terminal of the variable delay circuit 3 is connected to the second input terminal of the multi-bit type phase comparator 42, and the delay signal φ2 'is input thereto.
多ビット型位相比較器42は、その入力された信号φ1および遅延信号φ2’の位相差と、信号φ1の位相と遅延信号φ2’の位相の前後関係とを判別し、その判別した位相差および前後関係を示す出力信号Codeを自己の出力端子から出力する。なお、出力信号Codeは、複数ビットの信号である。
The multi-bit type phase comparator 42 discriminates the phase difference between the input signal φ1 and the delayed signal φ2 ′ and the front-rear relationship between the phase of the signal φ1 and the phase of the delayed signal φ2 ′, and the phase difference and An output signal Code indicating the context is output from its own output terminal. The output signal Code is a multi-bit signal.
加算器13は、重み付け手段の一例である。加算器13の入力端子には、多ビット型位相比較器42の出力端子が接続され、出力信号Codeが入力される。また、加算器13の制御端子には、制御ロジック回路9からバイアス信号Biasが入力される。
The adder 13 is an example of weighting means. The output terminal of the multi-bit type phase comparator 42 is connected to the input terminal of the adder 13 and the output signal Code is input. The bias signal Bias is input from the control logic circuit 9 to the control terminal of the adder 13.
加算器13は、その入力された出力信号Codeに、その入力されたバイアス信号Bias信号の値を重み値として加算することで、出力信号Codeに重み値を付与する。加算器13は、その重み値を付与した出力信号Codeを、出力信号Code’として自己の出力端子から出力する。
The adder 13 gives a weight value to the output signal Code by adding the value of the input bias signal Bias signal as a weight value to the input output signal Code. The adder 13 outputs the output signal Code to which the weight value is given from its own output terminal as the output signal Code ′.
出力端子14には、加算器13の出力手段が接続され、出力信号Code’が入力される。出力端子14は、その入力された出力信号Code’を出力する。
The output means of the adder 13 is connected to the output terminal 14 and the output signal Code ′ is input. The output terminal 14 outputs the input output signal Code ′.
制御ロジック回路9は、バイアス信号Biasを加算器13の制御端子に入力する。また、第一の実施形態と同様に、制御ロジック回路9は、遅延制御信号DLYを可変遅延回路3の制御端子に入力する。
The control logic circuit 9 inputs the bias signal Bias to the control terminal of the adder 13. As in the first embodiment, the control logic circuit 9 inputs the delay control signal DLY to the control terminal of the variable delay circuit 3.
また、制御ロジック回路9には、多ビット型位相比較器42から出力信号Codeが入力される。制御ロジック回路9は、その入力された出力信号Codeに応じて、遅延制御信号DLYが示す遅延量を、多ビット型位相比較器42が判別する位相差の分解能より小さい単位で調整する。
Also, the output signal Code is input from the multi-bit type phase comparator 42 to the control logic circuit 9. The control logic circuit 9 adjusts the delay amount indicated by the delay control signal DLY in units smaller than the resolution of the phase difference determined by the multi-bit type phase comparator 42 according to the input output signal Code.
さらに、制御ロジック回路9は、信号φ1および遅延信号φ2’の位相差が、多ビット型位相比較器42にて判別可能な検出可能範囲を超えている場合、その位相差がその検出可能範囲に含まれるように、可変遅延回路3の遅延量を調節する。
Furthermore, when the phase difference between the signal φ1 and the delay signal φ2 ′ exceeds the detectable range that can be discriminated by the multi-bit type phase comparator 42, the control logic circuit 9 sets the phase difference within the detectable range. The delay amount of the variable delay circuit 3 is adjusted so as to be included.
例えば、信号φ1の位相が遅延信号φ2’の位相より検出可能範囲以上に進んでいる場合、出力信号Codeの値が最大値(図11Aで示した例では、6)になり、出力信号Codeが、その位相差が検出可能範囲を超えていることを示すことになる。この場合、制御ロジック回路9は、出力信号Codeの値が最大値より小さくなるまで、遅延制御信号DLYが示す遅延量を小さくしていく。
For example, when the phase of the signal φ1 has advanced beyond the detectable range from the phase of the delay signal φ2 ′, the value of the output signal Code becomes the maximum value (6 in the example shown in FIG. 11A), and the output signal Code is This indicates that the phase difference exceeds the detectable range. In this case, the control logic circuit 9 decreases the delay amount indicated by the delay control signal DLY until the value of the output signal Code becomes smaller than the maximum value.
また、信号φ1の位相が遅延信号φ2’の位相より遅れていている場合、出力信号Codeの値が0になり、出力信号が、その位相差が検出可能範囲を超えていることを示すことになる。この場合、制御ロジック回路9は、出力信号Codeの値が0より大きくなるまで、遅延制御信号DLYが示す遅延量を大きくしていく。
Further, when the phase of the signal φ1 is delayed from the phase of the delay signal φ2 ′, the value of the output signal Code becomes 0, and the output signal indicates that the phase difference exceeds the detectable range. Become. In this case, the control logic circuit 9 increases the delay amount indicated by the delay control signal DLY until the value of the output signal Code becomes larger than zero.
次に効果を説明する。
Next, the effect will be explained.
本実施形態では、多ビット型位相比較器42は、信号φ1の位相と遅延信号φ2の位相の前後関係に加え、信号φ1および遅延信号φ2’の位相差をさらに判別し、その判別した前後関係および位相差を示す出力信号Codeを出力する。加算器13は、その出力信号Codeに重み値を加算して、出力信号Code’を生成する。制御ロジック回路9は、出力信号Codeに基づいて、可変遅延回路3の遅延量を、多ビット型位相比較器42が判別する位相差の分解能より小さい単位で調節する。
In the present embodiment, the multi-bit type phase comparator 42 further determines the phase difference between the signal φ1 and the delay signal φ2 ′ in addition to the phase relationship between the phase of the signal φ1 and the phase of the delay signal φ2, and the determined context And an output signal Code indicating the phase difference is output. The adder 13 adds a weight value to the output signal Code to generate an output signal Code ′. Based on the output signal Code, the control logic circuit 9 adjusts the delay amount of the variable delay circuit 3 by a unit smaller than the resolution of the phase difference determined by the multi-bit type phase comparator 42.
この場合、出力信号Code’の値を、多ビット型位相比較器42が判別する位相差の分解能より細かい値にすることが可能になる。したがって、信号φ1およびφ2の位相差を、多ビット型位相比較器42が判別する位相差の分解能より細かい値で判別することが可能になる。
In this case, the value of the output signal Code ′ can be made finer than the resolution of the phase difference determined by the multi-bit type phase comparator 42. Therefore, the phase difference between the signals φ1 and φ2 can be determined with a value finer than the resolution of the phase difference determined by the multi-bit type phase comparator 42.
また、制御ロジック回路9は、信号φ1および遅延信号φ2’の位相差が、多ビット型位相比較器42にて判別可能な検出可能範囲を超えている場合、その位相差がその検出可能範囲に含まれるように、可変遅延回路3の遅延量を調節する。
Further, when the phase difference between the signal φ1 and the delay signal φ2 ′ exceeds the detectable range that can be discriminated by the multi-bit type phase comparator 42, the control logic circuit 9 sets the phase difference within the detectable range. The delay amount of the variable delay circuit 3 is adjusted so as to be included.
この場合、多ビット型位相比較器42が判別する位相差のダイナミックレンジより広い範囲で、信号φ1およびφ2の位相差を判別することができる。
In this case, the phase difference between the signals φ1 and φ2 can be determined in a wider range than the dynamic range of the phase difference determined by the multi-bit type phase comparator 42.
また、本実施形態では、位相差のダイナミックレンジを広く確保することと、位相差の分解能を細かくすることの両方を行う場合でも、多ビット型位相比較器42内のフリップフロップ回路の増加を抑制することができる。よって、消費電力および回路面積の増加を抑制することができる。
Further, in the present embodiment, even when both a wide dynamic range of the phase difference is ensured and the resolution of the phase difference is made fine, an increase in the number of flip-flop circuits in the multi-bit type phase comparator 42 is suppressed. can do. Therefore, increase in power consumption and circuit area can be suppressed.
次に第五の実施形態について説明する。本実施形態では、データ信号と、クロック信号の位相差を検出することが可能な位相比較器について説明する。
Next, a fifth embodiment will be described. In this embodiment, a phase comparator capable of detecting a phase difference between a data signal and a clock signal will be described.
図13Aは、本実施形態の位相比較器を示した回路図である。図13Aにおいて、位相比較器は、可変遅延回路3と、バイナリ型位相比較器43とを含む。また、この位相比較器には、データ信号Dinと、クロック信号ψ1、ψ2およびψ3とが入力される。クロック信号ψ1の位相は、クロック信号ψ2の位相より進んでおり、クロック信号ψ3の位相は、クロック信号ψ2の位相より遅れている。なお、データ信号Dinは、第一信号の一例である。また、クロック信号ψ1は、先行信号の一例であり、クロック信号ψ2は、第二入力信号の一例であり、クロック信号ψ3は、後行信号の一例である。
FIG. 13A is a circuit diagram showing the phase comparator of the present embodiment. In FIG. 13A, the phase comparator includes a variable delay circuit 3 and a binary type phase comparator 43. Further, the data signal Din and the clock signals ψ1, ψ2, and ψ3 are input to this phase comparator. The phase of the clock signal ψ1 is advanced from the phase of the clock signal ψ2, and the phase of the clock signal ψ3 is delayed from the phase of the clock signal ψ2. The data signal Din is an example of the first signal. The clock signal ψ1 is an example of a preceding signal, the clock signal ψ2 is an example of a second input signal, and the clock signal ψ3 is an example of a subsequent signal.
可変遅延回路3は、クロック信号ψ2を遅延して、遅延クロック信号ψ2’を生成する。
The variable delay circuit 3 delays the clock signal ψ2 to generate a delayed clock signal ψ2 '.
バイナリ型位相比較器43は、図13Bのように遅延クロック信号ψ2’を用いて、データ信号Dinの位相と遅延クロック信号ψ2’の位相の前後関係と、データ信号Dinおよび遅延クロック信号ψ2’の位相差を判別する。
As shown in FIG. 13B, the binary phase comparator 43 uses the delayed clock signal ψ2 ′, and the anteroposterior relationship between the phase of the data signal Din and the phase of the delayed clock signal ψ2 ′, and the data signal Din and the delayed clock signal ψ2 ′. Determine the phase difference.
図14は、本実施形態の位相比較器のより詳細な構成を示した回路図である。図14において、位相比較器は、入力端子1、2a、2bおよび2cと、可変遅延回路3と、乗算器5および6と、制御ロジック回路9と、バイナリ型位相比較器43とを含む。
FIG. 14 is a circuit diagram showing a more detailed configuration of the phase comparator of the present embodiment. 14, the phase comparator includes input terminals 1, 2 a, 2 b and 2 c, a variable delay circuit 3, multipliers 5 and 6, a control logic circuit 9, and a binary phase comparator 43.
入力端子1には、データ信号Dinが入力される。入力端子2aには、クロック信号ψ1が入力され、入力端子2bには、クロック信号ψ2が入力され、入力端子2cには、クロック信号ψ3が入力される。なお、データ信号Dinは、本実施形態では、差動信号であるとしている。
The data signal Din is input to the input terminal 1. The clock signal ψ1 is input to the input terminal 2a, the clock signal ψ2 is input to the input terminal 2b, and the clock signal ψ3 is input to the input terminal 2c. Note that the data signal Din is a differential signal in this embodiment.
可変遅延回路3の入力端子には、入力端子2bが接続され、クロック信号ψ2が入力される。可変遅延回路3は、クロック信号ψ2を自己の制御端子に入力された遅延制御信号DLYが示す遅延量だけ遅延させることで、クロック信号φ2の位相を調整して、遅延クロック信号ψ2’を生成する。可変遅延回路3は、その生成した遅延クロック信号ψ2’を自己の出力端子から出力する。
The input terminal 2b is connected to the input terminal of the variable delay circuit 3, and the clock signal ψ2 is input. The variable delay circuit 3 delays the clock signal ψ2 by the delay amount indicated by the delay control signal DLY input to its own control terminal, thereby adjusting the phase of the clock signal φ2 and generating the delayed clock signal ψ2 ′. . The variable delay circuit 3 outputs the generated delayed clock signal ψ2 'from its output terminal.
バイナリ型位相比較器43は、保持回路43aないし43cと、排他的論理和回路43dおよび43eを有する選択出力部とを含む。
The binary type phase comparator 43 includes holding circuits 43a to 43c and a selection output unit having exclusive OR circuits 43d and 43e.
保持回路43aないし43cのそれぞれは、例えば、フリップフロップ回路やサンプリングラッチ回路などである。
Each of the holding circuits 43a to 43c is, for example, a flip-flop circuit or a sampling latch circuit.
保持回路43aの第一の入力端子には、入力端子1が接続され、データ信号Dinが入力される。保持回路43aの第二の入力端子には、入力端子2aが接続され、クロック信号ψ1が入力される。保持回路43aは、データ信号Dinをクロック信号ψ1のエッジのタイミングで保持し、その保持したデータ信号Dinを自己の出力端子から出力する。
The input terminal 1 is connected to the first input terminal of the holding circuit 43a, and the data signal Din is input. The input terminal 2a is connected to the second input terminal of the holding circuit 43a, and the clock signal ψ1 is input thereto. The holding circuit 43a holds the data signal Din at the edge timing of the clock signal ψ1, and outputs the held data signal Din from its own output terminal.
保持回路43bの第一の入力端子には、入力端子1が接続され、データ信号Dinが入力される。保持回路43bの第二の入力端子には、可変遅延回路3の出力端子が接続され、遅延クロック信号ψ2’が入力される。保持回路43bは、データ信号Dinを遅延クロック信号ψ2’のエッジのタイミングで保持し、その保持したデータ信号Dinを自己の出力端子から出力する。
The input terminal 1 is connected to the first input terminal of the holding circuit 43b, and the data signal Din is input. The output terminal of the variable delay circuit 3 is connected to the second input terminal of the holding circuit 43b, and the delayed clock signal ψ2 'is input thereto. The holding circuit 43b holds the data signal Din at the edge timing of the delayed clock signal ψ2 ', and outputs the held data signal Din from its own output terminal.
保持回路43cの第一の入力端子には、入力端子1が接続され、データ信号Dinが入力される。保持回路43cの第二の入力端子には、入力端子2cが接続され、クロック信号ψ3が入力される。保持回路43cは、データ信号Dinをクロック信号ψ3のエッジのタイミングで保持し、その保持したデータ信号Dinを自己の出力端子から出力する。
The input terminal 1 is connected to the first input terminal of the holding circuit 43c, and the data signal Din is input. The input terminal 2c is connected to the second input terminal of the holding circuit 43c, and the clock signal ψ3 is input. The holding circuit 43c holds the data signal Din at the edge timing of the clock signal ψ3, and outputs the held data signal Din from its own output terminal.
なお、保持回路43aは、第一保持手段の一例であり、保持回路43bは、第二保持手段の一例であり、保持回路43cは、第三保持手段の一例である。
The holding circuit 43a is an example of a first holding unit, the holding circuit 43b is an example of a second holding unit, and the holding circuit 43c is an example of a third holding unit.
排他的論理和回路43dおよび43eを有する選択出力部は、保持回路43aから出力されたデータ信号Dinと、保持回路43bから出力されたデータ信号Dinとが互いに異なっていると、HレベルのEarly信号を出力する。また、選択出力部は、保持回路43bから出力されたデータ信号Dinと、保持回路43cから出力されたデータ信号Dinと、が互いに異なっていると、HレベルのLate信号を出力する。
The selection output unit having the exclusive OR circuits 43d and 43e has an Early signal of H level when the data signal Din output from the holding circuit 43a and the data signal Din output from the holding circuit 43b are different from each other. Is output. The selection output unit outputs an H-level Late signal when the data signal Din output from the holding circuit 43b and the data signal Din output from the holding circuit 43c are different from each other.
排他的論理和回路43dの第一の入力端子には、保持回路43aの出力端子が接続され、クロック信号ψ1で保持されたデータ信号Dinが入力される。排他的論理和回路43dの第二の入力端子には、保持回路43bの出力端子が接続され、遅延クロック信号ψ2’で保持されたデータ信号Dinが入力される。
The output terminal of the holding circuit 43a is connected to the first input terminal of the exclusive OR circuit 43d, and the data signal Din held by the clock signal ψ1 is input. The output terminal of the holding circuit 43b is connected to the second input terminal of the exclusive OR circuit 43d, and the data signal Din held by the delayed clock signal ψ2 'is input.
排他的論理和回路43dは、自己の第一の入力端子に入力されたデータ信号Dinと、自己の第二の入力端子に入力されたデータ信号Dinとの排他的論理和を算出し、その算出結果を自己の出力端子からEarly信号として出力する。
The exclusive OR circuit 43d calculates the exclusive OR of the data signal Din input to its first input terminal and the data signal Din input to its second input terminal. The result is output as an Early signal from its own output terminal.
排他的論理和回路43eの第一の入力端子には、保持回路43bの出力端子が接続され、遅延クロック信号ψ2’で保持されたデータ信号Dinが入力される。排他的論理和回路43eの第二の入力端子には、保持回路43cの出力端子が接続され、クロック信号ψ3で保持されたデータ信号Dinが入力される。
The output terminal of the holding circuit 43b is connected to the first input terminal of the exclusive OR circuit 43e, and the data signal Din held by the delayed clock signal ψ2 'is input. The output terminal of the holding circuit 43c is connected to the second input terminal of the exclusive OR circuit 43e, and the data signal Din held by the clock signal ψ3 is input.
排他的論理和回路43eは、自己の第一の入力端子に入力されたデータ信号Dinと、自己の第二の入力端子に入力されたデータ信号Dinとの排他的論理和を算出し、その算出結果を自己の出力端子からLate信号として出力する。
The exclusive OR circuit 43e calculates an exclusive OR of the data signal Din input to its first input terminal and the data signal Din input to its second input terminal. The result is output as a Late signal from its own output terminal.
ここで、遅延クロック信号ψ2’で保持されたデータ信号の値と、クロック信号ψ3で保持されたデータ信号の値とが異なっている場合、Late信号がHレベルになるとする。
Here, if the value of the data signal held by the delayed clock signal ψ2 'is different from the value of the data signal held by the clock signal ψ3, the Late signal is assumed to be H level.
ここで、クロック信号ψ1で保持されたデータ信号Dinの値と、遅延クロック信号ψ2’で保持されたデータ信号の値Dinとが異なっている場合、データ信号Dinのエッジのタイミングは、クロック信号ψ1のエッジのタイミングと、遅延クロック信号ψ2’のエッジのタイミングと間にあることになる。したがって、データ信号Dinの位相が遅延クロック信号ψ2’の位相より進んでいることになる。
Here, when the value of the data signal Din held by the clock signal ψ1 is different from the value Din of the data signal held by the delayed clock signal ψ2 ′, the timing of the edge of the data signal Din is the clock signal ψ1. Is between the edge timing and the edge timing of the delayed clock signal ψ2 ′. Therefore, the phase of the data signal Din is ahead of the phase of the delayed clock signal ψ2 '.
また、遅延クロック信号ψ2’で保持されたデータ信号の値と、クロック信号ψ3で保持されたデータ信号の値とが異なっている場合、データ信号Dinのエッジのタイミングは、遅延クロック信号ψ2’のエッジのタイミングと、クロック信号ψ3のエッジのタイミングと間にあることになる。したがって、データ信号Dinの位相が遅延クロック信号ψ2’の位相より遅れていることになる。
In addition, when the value of the data signal held by the delayed clock signal ψ2 ′ is different from the value of the data signal held by the clock signal ψ3, the timing of the edge of the data signal Din is the timing of the delayed clock signal ψ2 ′. This is between the edge timing and the edge timing of the clock signal ψ3. Therefore, the phase of the data signal Din is delayed from the phase of the delayed clock signal ψ2 '.
したがって、選択出力部は、データ信号Dinの位相が遅延クロック信号ψ2’の位相より進んでいると、HレベルのEarly信号を出力し、データ信号Dinの位相が遅延クロック信号ψ2’の位相より遅れていると、HレベルのLate信号を出力することになる。
Therefore, when the phase of the data signal Din is advanced from the phase of the delayed clock signal ψ2 ′, the selection output unit outputs an Early signal of H level, and the phase of the data signal Din is delayed from the phase of the delayed clock signal ψ2 ′. If so, an H-level Late signal is output.
このため、第一の実施形態と同様に、制御ロジック回路9が可変遅延回路3の遅延量に応じて、重み付け制御信号の値を調整することで、重み付け部から、データ信号Dinの位相とクロック信号ψ2の位相の前後関係と、データ信号Dinおよびクロック信号ψ2の位相差とを示すEarly’信号およびLate’信号を出力することができる。
Therefore, as in the first embodiment, the control logic circuit 9 adjusts the value of the weighting control signal in accordance with the delay amount of the variable delay circuit 3, so that the phase of the data signal Din and the clock are adjusted from the weighting unit. The Early ′ signal and the Late ′ signal indicating the phase relationship of the signal ψ2 and the phase difference between the data signal Din and the clock signal ψ2 can be output.
次に効果について説明する。
Next, the effect will be described.
本実施形態では、保持回路43aは、データ信号Dinをクロック信号ψ1のエッジのタイミングで保持し、その保持したデータ信号Dinを出力する。保持回路43bは、データ信号Dinを遅延クロック信号ψ2’のエッジのタイミングで保持し、その保持したデータ信号Dinを出力する。保持回路43cは、データ信号Dinをクロック信号ψ3のエッジのタイミングで保持し、その保持したデータ信号Dinを出力する。選択出力部は、保持回路43aから出力されたデータ信号Dinと、保持回路43bから出力されたデータ信号Dinとが互いに異なっていると、HレベルのEarly信号を出力する。また、選択出力部は、保持回路43bから出力されたデータ信号Dinと、保持回路43cから出力されたデータ信号Dinと、が互いに異なっていると、HレベルのLate信号を出力する。
In the present embodiment, the holding circuit 43a holds the data signal Din at the edge timing of the clock signal ψ1, and outputs the held data signal Din. The holding circuit 43b holds the data signal Din at the edge timing of the delayed clock signal ψ2 'and outputs the held data signal Din. The holding circuit 43c holds the data signal Din at the edge timing of the clock signal ψ3, and outputs the held data signal Din. When the data signal Din output from the holding circuit 43a and the data signal Din output from the holding circuit 43b are different from each other, the selection output unit outputs an Early signal of H level. The selection output unit outputs an H-level Late signal when the data signal Din output from the holding circuit 43b and the data signal Din output from the holding circuit 43c are different from each other.
この場合、データ信号およびクロック信号の位相差を判別することができる。
In this case, the phase difference between the data signal and the clock signal can be determined.
次に第六の実施形態について説明する。
Next, a sixth embodiment will be described.
図15は、本実施形態の位相比較器の構成を示した回路図である。図15において、位相比較器は、図14で示した構成に加えて、入力端子15を含む。また、バイナリ型位相比較器43は、図14で示した構成に加えて、保持回路43fないし43hを含む。
FIG. 15 is a circuit diagram showing the configuration of the phase comparator of the present embodiment. 15, the phase comparator includes an input terminal 15 in addition to the configuration shown in FIG. 14. Further, the binary phase comparator 43 includes holding circuits 43f to 43h in addition to the configuration shown in FIG.
入力端子15には、クロック信号ψ4が入力される。なお、入力端子15は、第三入力手段の一例である。
The clock signal ψ 4 is input to the input terminal 15. The input terminal 15 is an example of third input means.
保持回路43fの第一の入力端子には、保持回路43aの出力端子が接続され、クロック信号ψ1で保持されたデータ信号Dinが入力される。保持回路43hの第二の入力端子には、入力端子15が接続され、クロック信号ψ4が入力される。保持回路43hは、その入力されたデータ信号Dinをクロック信号ψ4のエッジのタイミングで保持し、その保持したデータ信号Dinを自己の出力端子から出力する。
The output terminal of the holding circuit 43a is connected to the first input terminal of the holding circuit 43f, and the data signal Din held by the clock signal ψ1 is input. The input terminal 15 is connected to the second input terminal of the holding circuit 43h, and the clock signal ψ4 is input thereto. The holding circuit 43h holds the input data signal Din at the edge timing of the clock signal ψ4, and outputs the held data signal Din from its own output terminal.
保持回路43gの第一の入力端子には、保持回路43bの出力端子が接続され、遅延クロック信号ψ2’で保持されたデータ信号Dinが入力される。保持回路43gの第二の入力端子には、入力端子15が接続され、クロック信号ψ4が入力される。保持回路43gは、その入力されたデータ信号Dinをクロック信号ψ4のエッジのタイミングで保持し、その保持したデータ信号Dinを自己の出力端子から出力する。
The output terminal of the holding circuit 43b is connected to the first input terminal of the holding circuit 43g, and the data signal Din held by the delayed clock signal ψ2 'is input. The input terminal 15 is connected to the second input terminal of the holding circuit 43g, and the clock signal ψ4 is input thereto. The holding circuit 43g holds the input data signal Din at the edge timing of the clock signal ψ4, and outputs the held data signal Din from its own output terminal.
保持回路43hの第一の入力端子には、保持回路43cの出力端子が接続され、クロック信号ψ3で保持されたデータ信号Dinが入力される。保持回路43hの第二の入力端子には、入力端子15が接続され、クロック信号ψ4が入力される。保持回路43hは、その入力されたデータ信号Dinをクロック信号ψ4で保持し、その保持したデータ信号Dinを自己の出力端子から出力する。
The output terminal of the holding circuit 43c is connected to the first input terminal of the holding circuit 43h, and the data signal Din held by the clock signal ψ3 is input. The input terminal 15 is connected to the second input terminal of the holding circuit 43h, and the clock signal ψ4 is input thereto. The holding circuit 43h holds the input data signal Din with the clock signal ψ4, and outputs the held data signal Din from its own output terminal.
なお、保持回路43eは、第四保持手段の一例であり、保持回路43gは、第五保持手段の一例であり、保持回路43hは、第六保持手段の一例である。
The holding circuit 43e is an example of fourth holding means, the holding circuit 43g is an example of fifth holding means, and the holding circuit 43h is an example of sixth holding means.
選択出力部の機能は、図14で説明した機能において、保持回路43aを保持回路43fに読み替え、保持回路43bを保持回路43gに読み替え、保持回路43cを保持回路43hに読み替えればよい。
The functions of the selection output unit may be the functions described with reference to FIG. 14, in which the holding circuit 43a is read as the holding circuit 43f, the holding circuit 43b is read as the holding circuit 43g, and the holding circuit 43c is read as the holding circuit 43h.
次に効果を説明する。
Next, the effect will be explained.
本実施形態では、排他的論理和回路43dおよび43eに入力されるデータ信号Dinのタイミングが揃う。このため、位相比較器から出力される出力信号Early’とLate’が有効となる時間範囲を広くすることが可能になる。
In the present embodiment, the timing of the data signal Din input to the exclusive OR circuits 43d and 43e is aligned. For this reason, the time range in which the output signals Early ′ and Late ′ output from the phase comparator are valid can be widened.
次に、第七の実施形態について説明する。
Next, a seventh embodiment will be described.
本実施形態では、図1、図5A、図5B、図6、図8、図9Aおよび図9Bで示した位相比較器が生成したEarly’信号およびLate’信号を、図10および図12で示した位相比較器が生成した出力信号Code’に変換するための信号変換回路を説明する。
In this embodiment, the Early ′ signal and the Late ′ signal generated by the phase comparator shown in FIGS. 1, 5A, 5B, 6, 8, 9A, and 9B are shown in FIGS. A signal conversion circuit for converting the output signal Code ′ generated by the phase comparator will be described.
図16Aおよび図16Bは、信号変換回路の構成例を示した回路図である。なお、この信号変換回路は、図1、図5A、図5B、図6、図8、図9Aおよび図9Bで示した位相比較器の、乗算器5および6と、出力端子7および8とに介在させることができる。この場合、この位相比較器は、出力端子7および8の代わりに、図12で示した位相比較器のように、出力端子14を含む。
16A and 16B are circuit diagrams showing a configuration example of the signal conversion circuit. This signal conversion circuit is connected to the multipliers 5 and 6 and the output terminals 7 and 8 of the phase comparator shown in FIGS. 1, 5A, 5B, 6, 8, 8, 9A, and 9B. Can intervene. In this case, the phase comparator includes an output terminal 14 instead of the output terminals 7 and 8 as in the phase comparator shown in FIG.
図16Aでは、信号変換回路は、セレクタ16で構成される。
In FIG. 16A, the signal conversion circuit includes a selector 16.
セレクタ16の第一の入力端子には、乗算器5の出力端子が接続され、Early’信号が入力される。セレクタ16の第二の入力端子には、乗算器6の出力端子が接続され、Late’信号が入力される。セレクタ16は、その入力されたLate’信号の値を反転させる。
The first input terminal of the selector 16 is connected to the output terminal of the multiplier 5 and receives the Early 'signal. The output terminal of the multiplier 6 is connected to the second input terminal of the selector 16 and the Late ′ signal is input. The selector 16 inverts the value of the input Late ′ signal.
値が反転されたLate’信号の値が0より小さい場合、つまり、Late’信号の値が0より大きい場合、セレクタ16は、値が反転されたLate’信号を、出力信号Code’として自己の出力端子から出力する。
When the value of the Late ′ signal with the inverted value is smaller than 0, that is, when the value of the Late ′ signal is larger than 0, the selector 16 uses the Late ′ signal with the inverted value as its output signal Code ′. Output from the output terminal.
一方、Early’信号の値が0より大きい場合、セレクタ16は、そのEarly’信号を、出力信号Code’として自己の出力端子から出力する。
On the other hand, when the value of the Early ′ signal is greater than 0, the selector 16 outputs the Early ′ signal from its own output terminal as the output signal Code ′.
図16Bでは、信号変換回路は、加算器17で構成される。
In FIG. 16B, the signal conversion circuit includes an adder 17.
加算器17の第一の入力端子には、乗算器5の出力端子が接続され、Early’信号が入力される。加算器17の第二の入力端子には、乗算器6の出力端子が接続され、Late’信号が入力される。
The output terminal of the multiplier 5 is connected to the first input terminal of the adder 17 and the Early ′ signal is input. The output terminal of the multiplier 6 is connected to the second input terminal of the adder 17 and the Late ′ signal is input.
加算器17は、Late’信号の値を反転する。加算器17は、その値を反転したLate’信号と、Early’信号とを加算し、その加算結果を、出力信号Code’として自己の出力端子から出力する。
The adder 17 inverts the value of the Late ′ signal. The adder 17 adds the Late ′ signal obtained by inverting the value and the Early ′ signal, and outputs the addition result as an output signal Code ′ from its own output terminal.
なお、セレクタ16および加算器17は、Late’信号の値を反転させていたが、Early’信号とLate’信号のどちらか一方の値を反転させればよい。
Although the selector 16 and the adder 17 invert the value of the Late ′ signal, it is only necessary to invert the value of either the Early ′ signal or the Late ′ signal.
図16Aおよび図16Bで示した信号変換回路を用いることで、図17で示すように、Early’信号およびLate’信号を、一つの出力信号Code’に変換することができる。なお、図17では、横軸は、信号φ1およびφ2の位相差を示し、縦軸は、位相比較器から出力される信号の値を示す。
By using the signal conversion circuit shown in FIG. 16A and FIG. 16B, the Early ′ signal and the Late ′ signal can be converted into one output signal Code ′ as shown in FIG. In FIG. 17, the horizontal axis represents the phase difference between the signals φ1 and φ2, and the vertical axis represents the value of the signal output from the phase comparator.
次に、第八の実施形態について説明する。本実施形態では、可変遅延回路3の構成例を説明する。
Next, an eighth embodiment will be described. In the present embodiment, a configuration example of the variable delay circuit 3 will be described.
図18は、可変遅延回路3の構成例を示した回路図である。図18において、可変遅延回路3では、複数のトライ(3)ステートインバータ31を含む。トライステートインバータ31のそれぞれは、互いに並列に接続されている。
FIG. 18 is a circuit diagram showing a configuration example of the variable delay circuit 3. In FIG. 18, the variable delay circuit 3 includes a plurality of tri (3) state inverters 31. Each of the tri-state inverters 31 is connected in parallel with each other.
トライステートインバータ31の入力端子には、可変遅延回路3の入力端子が接続され、信号φ2(または信号ψ2)が入力される。また、トライステートインバータ31の出力端子には、可変遅延回路3の出力端子が接続される。さらに、トライステートインバータ31は、二つの遅延制御端子を有し、各遅延制御端子には、制御ロジック回路9が接続され、遅延制御信号DLYが入力される。なお、トライステートインバータ31のそれぞれが有する遅延制御端子が、可変遅延回路3の制御端子となる。
The input terminal of the variable delay circuit 3 is connected to the input terminal of the tri-state inverter 31, and the signal φ2 (or signal φ2) is input. The output terminal of the variable delay circuit 3 is connected to the output terminal of the tristate inverter 31. Further, the tri-state inverter 31 has two delay control terminals. The control logic circuit 9 is connected to each delay control terminal, and the delay control signal DLY is input. Note that the delay control terminal included in each of the tri-state inverters 31 serves as a control terminal of the variable delay circuit 3.
トライステートインバータ31は、pMOSトランジスタ32および33と、nMOSトランジスタ34および35とを含む。
Tristate inverter 31 includes pMOS transistors 32 and 33 and nMOS transistors 34 and 35.
pMosトランジスタ32では、ソース端子が電源と接続され、ドレイン端子がpMosトランジスタ33のソース端子に接続される。pMosトランジスタ33では、ドレイン端子が、トライステートインバータ31の出力端子とnMosトランジスタ34のドレイン端子とに接続される。nMosトランジスタ34では、ソース端子が、nMosトランジスタ35のドレイン端子に接続される。nMosトランジスタ35では、ソース端子が接地される。
In the pMos transistor 32, the source terminal is connected to the power supply, and the drain terminal is connected to the source terminal of the pMos transistor 33. In the pMos transistor 33, the drain terminal is connected to the output terminal of the tri-state inverter 31 and the drain terminal of the nMos transistor 34. In the nMos transistor 34, the source terminal is connected to the drain terminal of the nMos transistor 35. In the nMos transistor 35, the source terminal is grounded.
また、pMosトランジスタ33のゲート端子と、nMosトランジスタ34のゲート端子とが、トライステートインバータ31の入力端子と接続される。pMosトランジスタ32のゲート端子が、トライステートインバータ31の一方の遅延制御端子と接続され、nMosトランジスタ35のゲート端子が、トライステートインバータ31の他方の遅延制御端子と接続される。
Further, the gate terminal of the pMos transistor 33 and the gate terminal of the nMos transistor 34 are connected to the input terminal of the tri-state inverter 31. The gate terminal of the pMos transistor 32 is connected to one delay control terminal of the tri-state inverter 31, and the gate terminal of the nMos transistor 35 is connected to the other delay control terminal of the tri-state inverter 31.
なお、pMosトランジスタ32のゲート端子と、nMosトランジスタ35のゲート端子とが、トライステートインバータ31の入力端子と接続され、pMosトランジスタ33のゲート端子が、トライステートインバータ31の一方の遅延制御端子と接続され、nMosトランジスタ34のゲート端子が、トライステートインバータ31の他方の遅延制御端子と接続されてもよい。
The gate terminal of the pMos transistor 32 and the gate terminal of the nMos transistor 35 are connected to the input terminal of the tristate inverter 31, and the gate terminal of the pMos transistor 33 is connected to one delay control terminal of the tristate inverter 31. The gate terminal of the nMos transistor 34 may be connected to the other delay control terminal of the tri-state inverter 31.
これにより、トライステートインバータ31のそれぞれの遅延制御端子に入力される遅延制御信号DLYの値に応じて、遅延量が変化する。制御ロジック回路9は、トライステートインバータ31のそれぞれの遅延制御端子に入力する遅延制御信号DLYの値を調節して、可変遅延回路3の遅延量を調節する。
Thus, the amount of delay changes according to the value of the delay control signal DLY input to each delay control terminal of the tri-state inverter 31. The control logic circuit 9 adjusts the delay amount of the variable delay circuit 3 by adjusting the value of the delay control signal DLY input to each delay control terminal of the tri-state inverter 31.
次に、第九の実施形態について説明する。本実施形態では、制御ロジック回路9の構成例を説明する。
Next, a ninth embodiment will be described. In the present embodiment, a configuration example of the control logic circuit 9 will be described.
図19は、制御ロジック回路9の構成例を示した回路図である。図19において、制御ロジック回路9は、n-bitUP/Downカウンタ91と、論理回路92および93とを有する決定部とを含む。
FIG. 19 is a circuit diagram showing a configuration example of the control logic circuit 9. In FIG. 19, the control logic circuit 9 includes an n-bitUP / Down counter 91 and a determination unit having logic circuits 92 and 93.
n-bitUP/Downカウンタ(以下、カウンタと略す)91は、カウント部の一例である。カウンタ91の第一の入力端子には、バイナリ型位相比較器4の第一の出力端子が接続され、Early信号が入力される。カウンタ91の第二の入力端子には、バイナリ型位相比較器4の第二の出力端子が接続され、Late信号が入力される。
An n-bitUP / Down counter (hereinafter abbreviated as a counter) 91 is an example of a counting unit. The first output terminal of the binary phase comparator 4 is connected to the first input terminal of the counter 91, and the Early signal is input. The second output terminal of the binary phase comparator 4 is connected to the second input terminal of the counter 91, and the Late signal is input.
カウンタ91は、カウント値を保持する。なお、カウンタ91は、遅延制御信号の値が0の場合に、カウント値を0に設定する。また、カウント値は、nビットで表され、負の値は、補数表現で表される。
The counter 91 holds a count value. The counter 91 sets the count value to 0 when the value of the delay control signal is 0. The count value is represented by n bits, and the negative value is represented by a complement expression.
カウンタ91は、入力されたEarly信号およびLate信号に基づいて、保持しているカウント値をカウントアップまたはカウントダウンさせる。
The counter 91 counts up or down the held count value based on the input Early signal and Late signal.
具体的には、カウンタ91は、HレベルのLate信号が入力された場合には、カウント値をカウントアップし、HレベルのEarly信号が入力された場合には、カウント値をカウントダウンする。
Specifically, the counter 91 counts up the count value when an H-level Late signal is input, and counts down the count value when an H-level Early signal is input.
カウンタ91は、そのカウントアップまたはカウントダウンしたカウント値に応じて、可変遅延回路3の遅延量Xを求める。具体的には、カウンタ91は、そのカウント値が大きいほど、遅延量Xを大きく求める。本実施形態では、カウント値を可変遅延回路3の遅延量Xとして求める。なお、可変遅延回路3の遅延量を求める方法は、適宜変更可能である。例えば、カウンタ91は、そのカウント値を定数倍した値を可変遅延回路3の遅延量Xを求めてもよい。
The counter 91 obtains the delay amount X of the variable delay circuit 3 according to the count value counted up or down. Specifically, the counter 91 obtains a larger delay amount X as the count value is larger. In the present embodiment, the count value is obtained as the delay amount X of the variable delay circuit 3. The method for obtaining the delay amount of the variable delay circuit 3 can be changed as appropriate. For example, the counter 91 may obtain the delay amount X of the variable delay circuit 3 by multiplying the count value by a constant.
カウンタ91は、その求めた遅延量Xを示すカウント信号nを自己の出力端子から出力する。なお、本実施形態では、カウンタ91の出力端子と、可変遅延回路3の制御端子とが接続され、カウント信号nが、遅延制御信号DLYとして用いられる。
The counter 91 outputs a count signal n indicating the obtained delay amount X from its own output terminal. In the present embodiment, the output terminal of the counter 91 and the control terminal of the variable delay circuit 3 are connected, and the count signal n is used as the delay control signal DLY.
ここで、信号φ1の位相が遅延信号φ2’の位相より遅れている場合、Late信号がHレベルになる。この場合、カウント値がカウントアップされる。したがって、遅延制御信号の値が大きくなり、可変遅延回路3の遅延量Xが大きくなる。よって、遅延信号φ2’の位相が遅れるので、信号φ1および遅延信号φ2’の位相差が小さくなる。
Here, when the phase of the signal φ1 is delayed from the phase of the delay signal φ2 ', the Late signal becomes H level. In this case, the count value is counted up. Therefore, the value of the delay control signal increases and the delay amount X of the variable delay circuit 3 increases. Therefore, since the phase of the delay signal φ2 ′ is delayed, the phase difference between the signal φ1 and the delay signal φ2 ′ is reduced.
また、信号φ1の位相が遅延信号φ2’の位相より進んでいる場合、Early信号がHレベルになる。この場合、カウント値がカウントダウンされる。したがって、遅延制御信号の値が小さくなり、可変遅延回路の遅延量Xが小さくなる。よって、遅延信号φ2’の位相が進むので、信号φ1および遅延信号φ2’の位相差が小さくなる。
Also, when the phase of the signal φ1 is ahead of the phase of the delay signal φ2 ', the Early signal becomes H level. In this case, the count value is counted down. Therefore, the value of the delay control signal is reduced, and the delay amount X of the variable delay circuit is reduced. Therefore, since the phase of the delay signal φ2 'advances, the phase difference between the signal φ1 and the delay signal φ2' decreases.
論理回路92の入力端子には、カウンタ91の出力端子が接続され、カウント信号nが入力される。論理回路92は、そのカウント信号nが示す遅延量Xに応じて重み付け制御信号MEの値を決定し、その値を有する重み付け制御信号MEを乗算器5の制御端子に入力する。
The output terminal of the counter 91 is connected to the input terminal of the logic circuit 92 and the count signal n is input. The logic circuit 92 determines the value of the weighting control signal ME according to the delay amount X indicated by the count signal n, and inputs the weighting control signal ME having the value to the control terminal of the multiplier 5.
具体的には、遅延量Xが負の場合、論理回路92は、遅延量Xの絶対値が大きくなるほど、重み付け制御信号MEの値を大きくする。例えば、論理回路92は、遅延量Xの絶対値を、重み付け制御信号MEの値にする。
Specifically, when the delay amount X is negative, the logic circuit 92 increases the value of the weighting control signal ME as the absolute value of the delay amount X increases. For example, the logic circuit 92 sets the absolute value of the delay amount X to the value of the weighting control signal ME.
また、遅延量Xが0または正の場合、論理回路92は、重み付け制御信号MEの値を0に決定する。
In addition, when the delay amount X is 0 or positive, the logic circuit 92 determines the value of the weighting control signal ME to be 0.
論理回路93の入力端子には、カウンタ91の出力端子が接続され、カウント信号nが入力される。論理回路93は、そのカウント信号nが示す遅延量Xに応じて重み付け制御信号MLの値を決定し、その値の重み付け制御信号MLを乗算器6の制御端子に入力する。
The output terminal of the counter 91 is connected to the input terminal of the logic circuit 93, and the count signal n is input. The logic circuit 93 determines the value of the weighting control signal ML according to the delay amount X indicated by the count signal n, and inputs the weighting control signal ML of that value to the control terminal of the multiplier 6.
具体的には、遅延量Xが正の場合、論理回路93は、遅延量Xが大きくなるほど、重み付け制御信号MLの値を大きくする。例えば、論理回路93は、遅延量Xを、重み付け制御信号MLの値にする。
Specifically, when the delay amount X is positive, the logic circuit 93 increases the value of the weighting control signal ML as the delay amount X increases. For example, the logic circuit 93 sets the delay amount X to the value of the weighting control signal ML.
また、遅延量Xが負または0の場合、論理回路93は、重み付け制御信号MLの値を0に決定する。
Further, when the delay amount X is negative or 0, the logic circuit 93 determines the value of the weighting control signal ML to be 0.
次に制御ロジック回路9の動作を説明する。
Next, the operation of the control logic circuit 9 will be described.
図20は、制御ロジック回路9の動作例を説明するためのフローチャートである。なお、図20において、DLYは、カウント値であり、可変遅延回路3に入力される遅延制御信号の値である。また、MEは、Early信号に付与される重み付け値であり、MLはLate信号に付与する重み付け値である。
FIG. 20 is a flowchart for explaining an operation example of the control logic circuit 9. In FIG. 20, DLY is a count value, which is the value of the delay control signal input to the variable delay circuit 3. Further, ME is a weighting value given to the Early signal, and ML is a weighting value given to the Late signal.
ステップS1では、制御ロジック回路9のカウンタ91に、バイナリ型位相比較器4からEarly信号およびLate信号が入力される。カウンタ91は、そのEarly信号およびLate信号のどちらがHレベルかを判断する。カウンタ91は、Early信号がHレベルであると、ステップS2を実行し、カウンタ91は、Late信号がHレベルであると、ステップS3を実行する。
In step S 1, the Early signal and the Late signal are input from the binary phase comparator 4 to the counter 91 of the control logic circuit 9. The counter 91 determines which of the Early signal and the Late signal is at the H level. The counter 91 executes step S2 when the Early signal is at the H level, and the counter 91 executes step S3 when the Late signal is at the H level.
ステップS2では、カウンタ91は、保持しているカウント値をカウントアップする。カウンタ91は、そのカウントアップしたカウント値を遅延量Xとして求める。カウンタ91は、遅延量Xを示すカウント信号nを遅延制御信号として可変遅延回路3の制御端子に入力すると共に、そのカウント信号nを論理回路92および93のそれぞれの入力端子に入力する。その後、ステップS4が実行される。
In step S2, the counter 91 counts up the held count value. The counter 91 obtains the counted up count value as the delay amount X. The counter 91 inputs the count signal n indicating the delay amount X as a delay control signal to the control terminal of the variable delay circuit 3 and inputs the count signal n to the input terminals of the logic circuits 92 and 93. Thereafter, step S4 is executed.
ステップS3では、カウンタ91は、保持しているカウント値をカウントダウンする。カウンタ91は、そのカウントダウンしたカウント値に応じて遅延量Xを求める。カウンタ91は、遅延量Xを示すカウント信号nを遅延制御信号として可変遅延回路3の制御端子に入力すると共に、そのカウント信号nを論理回路92および93のそれぞれの入力端子に入力する。その後、ステップS4が実行される。
In step S3, the counter 91 counts down the held count value. The counter 91 obtains the delay amount X according to the counted down count value. The counter 91 inputs the count signal n indicating the delay amount X as a delay control signal to the control terminal of the variable delay circuit 3 and inputs the count signal n to the input terminals of the logic circuits 92 and 93. Thereafter, step S4 is executed.
ステップ4では、論理回路92は、そのカウント信号nが示す遅延量Xが負か否かを判断する。
In step 4, the logic circuit 92 determines whether or not the delay amount X indicated by the count signal n is negative.
遅延量Xが負の場合、論理回路92は、遅延量Xの絶対値を値として有する重み付け制御信号MLを生成する。一方、論理回路92は、そのカウント信号nの値が0または正であると、値として0を有する重みづけ制御信号MLを生成する。論理回路92は、その生成した重みづけ制御信号を乗算器5の制御端子に入力する。
When the delay amount X is negative, the logic circuit 92 generates a weighting control signal ML having the absolute value of the delay amount X as a value. On the other hand, when the value of the count signal n is 0 or positive, the logic circuit 92 generates a weighting control signal ML having 0 as a value. The logic circuit 92 inputs the generated weighting control signal to the control terminal of the multiplier 5.
また、論理回路93は、そのカウント信号nが示す遅延量Xが正か否かを判断する。論理回路92は、遅延量Xが正であると、その遅延量を値として有する重み付け制御信号MLを生成し、そのカウント信号nの値が負または0であると、値として0を有する重みづけ制御信号MLを生成する。論理回路92は、その生成した重みづけ制御信号MLを乗算器6の制御端子に入力する。
Also, the logic circuit 93 determines whether or not the delay amount X indicated by the count signal n is positive. When the delay amount X is positive, the logic circuit 92 generates a weighting control signal ML having the delay amount as a value. When the count signal n is negative or 0, the logic circuit 92 is weighted with a value of 0. A control signal ML is generated. The logic circuit 92 inputs the generated weight control signal ML to the control terminal of the multiplier 6.
以上の処理を、制御ロジック回路9がLate信号およびEarly信号のレベルが変わるまで繰り返すことで、信号φ1と信号φ2の位相差の大きさに応じたEarly’信号またはLate’信号を得ることができる。
By repeating the above processing until the control logic circuit 9 changes the level of the Late signal and the Early signal, an Early ′ signal or a Late ′ signal corresponding to the magnitude of the phase difference between the signals φ1 and φ2 can be obtained. .
次に効果を説明する。
Next, the effect will be explained.
本実施形態では、カウンタ91は、カウント値を保持し、Early信号およびLate信号に基づいて、そのカウント値をカウントアップまたはカウントダウンする。また、カウンタ91は、そのカウントアップまたはカウントダウンしたカウント値に応じて、可変遅延回路3の遅延量を調節する。決定部は、カウンタ91が調節した遅延量に応じて重み値を決定する。
In the present embodiment, the counter 91 holds a count value, and counts up or down the count value based on the Early signal and the Late signal. Further, the counter 91 adjusts the delay amount of the variable delay circuit 3 in accordance with the count value counted up or down. The determination unit determines the weight value according to the delay amount adjusted by the counter 91.
この場合、カウント値が、信号φ1の位相と遅延信号φ2の位相との前後関係を反映する。したがって、容易に、遅延量を、判別結果が示す前後関係が変化するような値に調節することができる。
In this case, the count value reflects the context of the phase of the signal φ1 and the phase of the delay signal φ2. Therefore, the delay amount can be easily adjusted to a value that changes the context shown by the determination result.
図21は、図20で示した制御ロジック回路9が用いられた位相比較器の動作例を示した説明図である。図21は、信号φ1の位相が信号φ2の位相より遅れている場合を示している。さらに、信号φ1およびφ2の位相差は、フィードバックループなどにより、徐々に小さくなっている。
FIG. 21 is an explanatory diagram showing an operation example of the phase comparator using the control logic circuit 9 shown in FIG. FIG. 21 shows a case where the phase of the signal φ1 is delayed from the phase of the signal φ2. Further, the phase difference between the signals φ1 and φ2 is gradually reduced due to a feedback loop or the like.
先ず、信号φ1が信号φ2より遅れているので、Late信号がHレベルになる。したがって、カウンタ91は、カウンタ値をカウントアップしていく。これにより、可変遅延回路3の遅延量が徐々に大きくなっていくので、遅延信号φ2’の位相は、徐々に遅れていき信号φ1の位相に近づいていく。
First, since the signal φ1 is delayed from the signal φ2, the Late signal becomes H level. Therefore, the counter 91 counts up the counter value. As a result, the delay amount of the variable delay circuit 3 gradually increases, so that the phase of the delay signal φ2 ′ gradually delays and approaches the phase of the signal φ1.
これと同時に、Late信号に付与される重み値が増加していくので、Late’信号の値が大きくなっていく。これにより、Late’信号は、信号φ1の位相が信号φ2の位相より大きく遅れていることを示すことになる。
At the same time, since the weight value given to the Late signal increases, the value of the Late ′ signal increases. Thus, the Late ′ signal indicates that the phase of the signal φ1 is greatly delayed from the phase of the signal φ2.
その後、遅延信号φ2’の位相は、遅れていき、信号φ1の位相を超えて、信号φ1の位相より遅れる。すると、Early信号がHレベルとなり、Late信号がLレベルとなる。このとき、カウンタ91は、カウント値をカウントダウンする。これにより、可変遅延回路3の遅延量が小さくなり、遅延信号φ2’の位相が信号φ1より進み、Early信号がLレベルとなり、Late信号がHレベルとなる。
Thereafter, the phase of the delay signal φ2 'is delayed, exceeds the phase of the signal φ1, and is delayed from the phase of the signal φ1. Then, the Early signal becomes H level and the Late signal becomes L level. At this time, the counter 91 counts down the count value. Thereby, the delay amount of the variable delay circuit 3 is reduced, the phase of the delay signal φ2 ′ is advanced from the signal φ1, the Early signal becomes L level, and the Late signal becomes H level.
以降、Early信号とLate信号が交互にHレベルになる。
Thereafter, the Early signal and the Late signal alternately become H level.
このような状況では、Late信号がHレベルのときのLate’信号が信号φ1およびφ2の位相差を示す。しかしながら、Early信号がHレベルになっているときには、Late信号がLレベルになるので、Late’信号の値が0になる。したがって、信号φ1の位相が信号φ2の位相より遅れている場合でも、Late’信号の値が0となり、Late’信号が、信号φ1およびφ2の位相差を示さなくなるという問題が生じる。
In such a situation, the Late ′ signal when the Late signal is at the H level indicates the phase difference between the signals φ1 and φ2. However, when the Early signal is at the H level, the Late signal is at the L level, so the value of the Late ′ signal is 0. Therefore, even when the phase of the signal φ1 is delayed from the phase of the signal φ2, the value of the Late ′ signal becomes 0, and there is a problem that the Late ′ signal does not show the phase difference between the signals φ1 and φ2.
次に、第十の実施形態として、上記の問題を解決することが可能な位相比較器について説明する。
Next, a phase comparator capable of solving the above problem will be described as a tenth embodiment.
図22Aは、本実施形態の位相比較器を示した回路図である。図22Aにおいて、位相比較器は、入力端子1および2と、可変遅延回路3と、乗算器5aないし5cと、乗算器6aないし6cと、出力端子7および8と、制御ロジック回路9と、分離部12aないし12cと、遅延回路18および19と、マルチプレクサ20および21とを有する選択部と、バイナリ型位相比較器44ないし46とを含む。また、制御ロジック回路9は、カウンタ91と、論理回路92および93とを含む。なお、乗算器5aないし5cと、乗算器6aないし6cとが重み付け部を構成する。出力端子7および8と、マルチプレクサ20および21とが出力部を構成する。
FIG. 22A is a circuit diagram showing the phase comparator of the present embodiment. 22A, the phase comparator includes input terminals 1 and 2, variable delay circuit 3, multipliers 5a to 5c, multipliers 6a to 6c, output terminals 7 and 8, and control logic circuit 9. Includes a selection unit having units 12a to 12c, delay circuits 18 and 19, multiplexers 20 and 21, and binary phase comparators 44 to 46. Control logic circuit 9 includes a counter 91 and logic circuits 92 and 93. The multipliers 5a to 5c and the multipliers 6a to 6c constitute a weighting unit. The output terminals 7 and 8 and the multiplexers 20 and 21 constitute an output unit.
遅延回路18の入力端子には、可変遅延回路3の出力端子が接続され、遅延信号φ2’が入力される。遅延回路18は、その遅延信号φ2’を予め定められた所定遅延量だけ遅延して、遅延信号φ2’’を生成する。遅延回路18は、その生成した遅延信号φ2’’を自己の出力端子から出力する。
The output terminal of the variable delay circuit 3 is connected to the input terminal of the delay circuit 18, and the delay signal φ2 'is input. The delay circuit 18 delays the delay signal φ2 ′ by a predetermined delay amount to generate a delay signal φ2 ″. The delay circuit 18 outputs the generated delay signal φ2 ″ from its output terminal.
遅延回路19の入力端子には、遅延回路18の出力端子が接続され、遅延信号φ2’が入力される。遅延回路19は、その遅延信号φ2’’を予め定められた特定遅延量だけ遅延して、遅延信号φ2’’’を生成する。遅延回路19は、その生成した遅延信号φ2’’’を自己の出力端子から出力する。なお、特定遅延量および所定遅延量は、互いに等しく、かつ、可変遅延回路3の遅延量の調節可能な単位と等しいことが望ましい。
The output terminal of the delay circuit 18 is connected to the input terminal of the delay circuit 19, and the delay signal φ2 'is input. The delay circuit 19 delays the delay signal φ2 ″ by a predetermined specific delay amount to generate a delay signal φ2 ″ ″. The delay circuit 19 outputs the generated delay signal φ2 '' 'from its own output terminal. The specific delay amount and the predetermined delay amount are preferably equal to each other and equal to a unit in which the delay amount of the variable delay circuit 3 can be adjusted.
遅延信号φ2’、φ2’’およびφ2’’’の位相は、図22Bで示すように、可変遅延回路3の遅延量に応じて変動する。なお、遅延回路18は、第一遅延手段の一例であり、遅延回路19は、第二遅延手段の一例である。
The phases of the delay signals φ2 ′, φ2 ″, and φ2 ″ ″ vary according to the delay amount of the variable delay circuit 3 as shown in FIG. 22B. The delay circuit 18 is an example of a first delay unit, and the delay circuit 19 is an example of a second delay unit.
バイナリ型位相比較器44の第一の入力端子には、入力端子1が接続され、信号φ1が入力される。バイナリ型位相比較器44の第二の入力端子には、可変遅延回路3の出力端子が接続され、遅延信号φ2’が入力される。
The input terminal 1 is connected to the first input terminal of the binary phase comparator 44, and the signal φ1 is input. The output terminal of the variable delay circuit 3 is connected to the second input terminal of the binary phase comparator 44, and the delay signal φ2 'is input thereto.
バイナリ型位相比較器44は、その信号φ1の位相と、遅延信号φ2’の位相との前後関係を判別し、その前後関係を示すEarly/Late1信号を自己の出力端子から出力する。なお、Early/Late1信号は、Hレベルの場合、信号φ1の位相が遅延信号φ2’の位相より進んでいることを示し、Lレベルの場合、信号φ1の位相が遅延信号φ2’の位相より遅れいていることを示す。
The binary phase comparator 44 discriminates the front / rear relationship between the phase of the signal φ1 and the phase of the delay signal φ2 ', and outputs an Early / Late1 signal indicating the front / rear relationship from its own output terminal. When the Early / Late1 signal is at the H level, it indicates that the phase of the signal φ1 is ahead of the phase of the delay signal φ2 ′, and when it is at the L level, the phase of the signal φ1 is delayed from the phase of the delay signal φ2 ′. Indicates that
バイナリ型位相比較器45の第一の入力端子には、入力端子1が接続され、信号φ1が入力される。バイナリ型位相比較器45の第二の入力端子には、遅延回路18の出力端子が接続され、遅延信号φ2’’が入力される。
The input terminal 1 is connected to the first input terminal of the binary phase comparator 45, and the signal φ1 is input. The output terminal of the delay circuit 18 is connected to the second input terminal of the binary phase comparator 45, and the delay signal φ2 ″ is input.
バイナリ型位相比較器45は、その信号φ1の位相と、遅延信号φ2’’の位相との前後関係を判別し、その前後関係を示すEarly/Late2信号を自己の出力端子から出力する。なお、Early/Late2信号は、Hレベルの場合、信号φ1の位相が遅延信号φ2’’の位相より進んでいることを示し、Lレベルの場合、信号φ1の位相が遅延信号φ2’’の位相より遅れいていることを示す。
The binary phase comparator 45 determines the front-rear relationship between the phase of the signal φ1 and the phase of the delayed signal φ2 ″, and outputs an Early / Late2 signal indicating the front-rear relationship from its own output terminal. When the Early / Late2 signal is at the H level, it indicates that the phase of the signal φ1 is ahead of the phase of the delay signal φ2 ″, and when it is at the L level, the phase of the signal φ1 is the phase of the delay signal φ2 ″. Indicates that it is later.
バイナリ型位相比較器46の第一の入力端子には、入力端子1が接続され、信号φ1が入力される。バイナリ型位相比較器46の第二の入力端子には、遅延回路19の出力端子が接続され、遅延信号φ2’’’が入力される。
The input terminal 1 is connected to the first input terminal of the binary phase comparator 46, and the signal φ1 is input. The output terminal of the delay circuit 19 is connected to the second input terminal of the binary phase comparator 46, and the delay signal φ2 '' 'is input.
バイナリ型位相比較器46は、その信号φ1の位相と、遅延信号φ2’’’の位相との前後関係を判別し、その前後関係を示すEarly/Late3信号を自己の出力端子から出力する。なお、Early/Late3信号は、Hレベルの場合、信号φ1の位相が遅延信号φ2’’’の位相より進んでいることを示し、Lレベルの場合、信号φ1の位相が遅延信号φ2’’’の位相より遅れいていることを示す。
The binary phase comparator 46 discriminates the front / rear relationship between the phase of the signal φ1 and the phase of the delayed signal φ2 '' '', and outputs an Early / Late3 signal indicating the front / rear relationship from its own output terminal. When the Early / Late3 signal is at the H level, it indicates that the phase of the signal φ1 is ahead of the phase of the delay signal φ2 ′ ″, and when it is at the L level, the phase of the signal φ1 is the delay signal φ2 ′ ″. It shows that it is behind the phase.
なお、バイナリ型位相比較器44は、第一判定手段の一例であり、バイナリ型位相比較器45は、第二判定手段の一例であり、バイナリ型位相比較器46は、第三判定手段の一例である。また、Early/Late1信号は、第一判別結果の一例であり、Early/Late2信号は、第二判別結果の一例であり、Early/Late3信号は、第三判別結果の一例である。
The binary phase comparator 44 is an example of a first determination unit, the binary phase comparator 45 is an example of a second determination unit, and the binary phase comparator 46 is an example of a third determination unit. It is. The Early / Late 1 signal is an example of a first discrimination result, the Early / Late 2 signal is an example of a second discrimination result, and the Early / Late 3 signal is an example of a third discrimination result.
分離部12aの入力端子は、バイナリ型位相比較器44の出力端子が接続され、Early/Late1信号が入力される。分離部12aは、その入力されたEarly/Late1信号から、Early1信号とLate1信号とを生成し、その生成したEarly1信号を、自己の第一の出力端子から出力し、その生成したLate1信号を、自己の第二の出力端子から出力する。
The input terminal of the separation unit 12a is connected to the output terminal of the binary phase comparator 44, and receives the Early / Late1 signal. The separation unit 12a generates an Early1 signal and a Late1 signal from the input Early / Late1 signal, outputs the generated Early1 signal from its first output terminal, and generates the generated Late1 signal. Output from its second output terminal.
分離部12bの入力端子は、バイナリ型位相比較器45の出力端子が接続され、Early/Late2信号が入力される。分離部12bは、その入力されたEarly/Late2信号から、Early2信号とLate2信号とを生成し、その生成したEarly2信号を、自己の第一の出力端子から出力し、その生成したLate2信号を、自己の第二の出力端子から出力する。
The input terminal of the separation unit 12b is connected to the output terminal of the binary phase comparator 45, and the Early / Late2 signal is input. The separation unit 12b generates an Early2 signal and a Late2 signal from the input Early / Late2 signal, outputs the generated Early2 signal from its first output terminal, and outputs the generated Late2 signal. Output from its second output terminal.
分離部12cの入力端子は、バイナリ型位相比較器46の出力端子が接続され、Early/Late3信号が入力される。分離部12cは、その入力されたEarly/Late3信号から、Early3信号とLate3信号とを生成し、その生成したEarly3信号を、自己の第一の出力端子から出力し、その生成したLate3信号を、自己の第二の出力端子から出力する。
The input terminal of the separation unit 12c is connected to the output terminal of the binary phase comparator 46, and receives the Early / Late3 signal. The separation unit 12c generates an Early3 signal and a Late3 signal from the input Early / Late3 signal, outputs the generated Early3 signal from its first output terminal, and generates the generated Late3 signal as Output from its second output terminal.
なお、分離部12aないし12cは、Early1信号およびLate1信号、Early2信号およびLate2信号、または、Early3信号およびLate3信号を、分離部12がEarly信号およびLate信号を生成する方法と同じ方法で生成することができる。
The separators 12a to 12c generate the Early1 signal and the Late1 signal, the Early2 signal and the Late2 signal, or the Early3 signal and the Late3 signal in the same manner as the method in which the separator 12 generates the Early signal and the Late signal. Can do.
乗算器5aの入力端子には、分離部12aの第一の出力端子が接続され、Early1信号が入力される。乗算器5aの制御端子には、制御ロジック回路9から重み付け制御信号ME1が入力される。乗算器5aは、その入力されたEarly1信号に、その入力された重み付け制御信号ME1の値を重み値として乗算して、Early1’信号を生成する。乗算器5aは、その生成したEarly1’信号を自己の出力端子から出力する。
The first output terminal of the separation unit 12a is connected to the input terminal of the multiplier 5a, and the Early1 signal is input thereto. The weighting control signal ME1 is input from the control logic circuit 9 to the control terminal of the multiplier 5a. The multiplier 5a multiplies the input Early1 signal by the value of the input weighting control signal ME1 as a weight value to generate an Early1 'signal. The multiplier 5a outputs the generated Early1 'signal from its own output terminal.
乗算器5bの入力端子には、分離部12bの第一の出力端子が接続され、Early2信号が入力される。乗算器5bの制御端子には、制御ロジック回路9から重み付け制御信号ME2が入力される。乗算器5bは、その入力されたEarly2信号に、その入力された重み付け制御信号ME2の値を重み値として乗算して、Early2’信号を生成する。乗算器5bは、その生成したEarly2’信号を自己の出力端子から出力する。
The first output terminal of the separation unit 12b is connected to the input terminal of the multiplier 5b, and the Early2 signal is input thereto. The weighting control signal ME2 is input from the control logic circuit 9 to the control terminal of the multiplier 5b. The multiplier 5b multiplies the input Early2 signal by the value of the input weighting control signal ME2 as a weight value to generate an Early2 'signal. The multiplier 5b outputs the generated Early 2 'signal from its own output terminal.
乗算器5cの入力端子には、分離部12cの第一の出力端子が接続され、Early3信号が入力される。乗算器5cの制御端子には、制御ロジック回路9から重み付け制御信号ME3が入力される。乗算器5cは、その入力されたEarly3信号に、その入力された重み付け制御信号ME3の値を重み値として乗算して、Early3’信号を生成する。乗算器5cは、その生成したEarly3’信号を自己の出力端子から出力する。
The first output terminal of the separation unit 12c is connected to the input terminal of the multiplier 5c, and the Early3 signal is input thereto. The weighting control signal ME3 is input from the control logic circuit 9 to the control terminal of the multiplier 5c. The multiplier 5c multiplies the input Early3 signal by the value of the input weighting control signal ME3 as a weight value to generate an Early3 'signal. The multiplier 5c outputs the generated Early 3 'signal from its own output terminal.
乗算器6aの入力端子には、分離部12aの第二の出力端子が接続され、Late1信号が入力される。乗算器6aの制御端子には、制御ロジック回路9から重み付け制御信号ML1が入力される。乗算器6aは、その入力されたLate1信号に、その入力された重み付け制御信号ML1の値を重み値として乗算して、Late1’信号を生成する。乗算器6aは、その生成したLate1’信号を自己の出力端子から出力する。
The second output terminal of the separation unit 12a is connected to the input terminal of the multiplier 6a, and the Late1 signal is input. The weighting control signal ML1 is input from the control logic circuit 9 to the control terminal of the multiplier 6a. The multiplier 6a multiplies the input Late1 signal by the value of the input weighting control signal ML1 as a weight value to generate a Late1 'signal. The multiplier 6a outputs the generated Late1 'signal from its own output terminal.
乗算器6bの入力端子には、分離部12bの第二の出力端子が接続され、Late2信号が入力される。乗算器6bの制御端子には、制御ロジック回路9から重み付け制御信号ML2が入力される。乗算器6bは、その入力されたLate2信号に、その入力された重み付け制御信号ML2の値を重み値として乗算して、Late2’信号を生成する。乗算器6bは、その生成したLate2’信号を自己の出力端子から出力する。
The second output terminal of the separation unit 12b is connected to the input terminal of the multiplier 6b, and the Late2 signal is input. The weighting control signal ML2 is input from the control logic circuit 9 to the control terminal of the multiplier 6b. The multiplier 6b multiplies the input Late2 signal by the value of the input weighting control signal ML2 as a weight value to generate a Late2 'signal. The multiplier 6b outputs the generated Late2 'signal from its own output terminal.
乗算器6cの入力端子には、分離部12cの第二の出力端子が接続され、Late3信号が入力される。乗算器6cの制御端子には、制御ロジック回路9から重み付け制御信号ML3が入力される。乗算器6cは、その入力されたLate3信号に、その入力された重み付け制御信号ML3の値を重み値として乗算して、Late3’信号を生成する。乗算器6cは、その生成したLate3’信号を自己の出力端子から出力する。
The second output terminal of the separation unit 12c is connected to the input terminal of the multiplier 6c, and the Late3 signal is input. The weighting control signal ML3 is input from the control logic circuit 9 to the control terminal of the multiplier 6c. The multiplier 6c multiplies the input Late3 signal by the value of the input weighting control signal ML3 as a weight value to generate a Late3 'signal. The multiplier 6c outputs the generated Late3 'signal from its own output terminal.
これにより、重み付け部は、第一判別結果、第二判別結果および第三判別結果のそれぞれに制御ロジック回路が決定した重み値を付与することになる。
Thereby, the weighting unit gives the weight value determined by the control logic circuit to each of the first discrimination result, the second discrimination result, and the third discrimination result.
マルチプレクサ20の第一の入力端子には、乗算器5aの出力端子が接続され、Early1信号が入力される。マルチプレクサ20の第二の入力端子には、乗算器5bの出力端子が接続され、Early2信号が入力される。マルチプレクサ20の第三の入力端子には、乗算器5cの出力端子が接続され、Early3信号が入力される。
The output terminal of the multiplier 5a is connected to the first input terminal of the multiplexer 20, and the Early1 signal is input. The second input terminal of the multiplexer 20 is connected to the output terminal of the multiplier 5b and receives the Early2 signal. The output terminal of the multiplier 5c is connected to the third input terminal of the multiplexer 20, and the Early3 signal is input.
マルチプレクサ20は、その入力されたEarly1信号ないしEarly3信号のうち、最も値の大きい信号を、Early信号として自己の出力端子から出力する。
The multiplexer 20 outputs the signal having the largest value among the input Early1 signal or Early3 signal as an Early signal from its own output terminal.
マルチプレクサ21の第一の入力端子には、乗算器6aの出力端子が接続され、Late1信号が入力される。マルチプレクサ21の第二の入力端子には、乗算器6bの出力端子が接続され、Late2信号が入力される。マルチプレクサ21の第三の入力端子には、乗算器6cの出力端子が接続され、Late3信号が入力される。
The output terminal of the multiplier 6a is connected to the first input terminal of the multiplexer 21, and the Late1 signal is input. The output terminal of the multiplier 6b is connected to the second input terminal of the multiplexer 21, and the Late2 signal is input. The output terminal of the multiplier 6c is connected to the third input terminal of the multiplexer 21, and the Late3 signal is input.
マルチプレクサ21は、その入力されたLate1信号ないしLate3信号のうち、最も値の大きい信号を、Late信号として自己の出力端子から出力する。
The multiplexer 21 outputs the signal having the largest value among the input Late1 signal or Late3 signal from its own output terminal as the Late signal.
出力端子7は、マルチプレクサ20の出力端子が接続され、Early信号が入力される。また、出力端子8は、マルチプレクサ21の出力端子が接続され、Late信号が入力される。
The output terminal 7 is connected to the output terminal of the multiplexer 20 and receives the Early signal. The output terminal 8 is connected to the output terminal of the multiplexer 21 and receives the Late signal.
これにより、出力端子7および8と、マルチプレクサ20および21を有する出力部は、重み付け部が重み値を付与した第一判別結果、第二判別結果および第三判別結果のうち、最も位相差が大きいことを示し信号を誤差信号として出力することになる。
As a result, the output unit having the output terminals 7 and 8 and the multiplexers 20 and 21 has the largest phase difference among the first determination result, the second determination result, and the third determination result to which the weighting unit has assigned weight values. The signal is output as an error signal.
カウンタ91の第一の入力端子には、バイナリ型位相比較器45の第一の出力端子が接続され、Early/Late2信号が入力される。
The first output terminal of the binary phase comparator 45 is connected to the first input terminal of the counter 91, and the Early / Late2 signal is input.
カウンタ91は、Early/Late2信号がHレベルの場合には、カウント値をカウントアップし、Early/Late2信号がLレベルの場合には、カウント値をカウントダウンする。
The counter 91 counts up the count value when the Early / Late2 signal is at the H level, and counts down the count value when the Early / Late2 signal is at the L level.
論理回路92は、カウント信号nが示す遅延量Xに応じて重み付け制御信号ME1ないしME3の値を決定する。
The logic circuit 92 determines the values of the weighting control signals ME1 to ME3 according to the delay amount X indicated by the count signal n.
具体的には、遅延量Xが負の場合、論理回路92は、遅延量Xの絶対値が大きくなるほど、重み付け制御信号ME1ないしME3の値を大きくする。このとき、重み付け制御信号ME1の値より重み付け制御信号ME2の値を大きくし、重み付け制御信号ME2の値より重み付け制御信号ME3の値を大きくすることが望ましい。
Specifically, when the delay amount X is negative, the logic circuit 92 increases the values of the weighting control signals ME1 to ME3 as the absolute value of the delay amount X increases. At this time, it is desirable to make the value of the weighting control signal ME2 larger than the value of the weighting control signal ME1, and to make the value of the weighting control signal ME3 larger than the value of the weighting control signal ME2.
例えば、論理回路92は、重み付け制御信号ME1の値を、遅延量Xの絶対値から1を引いた値に決定し、重み付け制御信号ME2の値を、遅延量Xの絶対値に決定し、重み付け制御信号ME3の値を、遅延量Xの絶対値に1を加えた値に決定する。
For example, the logic circuit 92 determines the value of the weighting control signal ME1 as a value obtained by subtracting 1 from the absolute value of the delay amount X, determines the value of the weighting control signal ME2 as the absolute value of the delay amount X, and performs weighting. The value of the control signal ME3 is determined to be a value obtained by adding 1 to the absolute value of the delay amount X.
また、遅延量Xが0または正の場合、論理回路92は、重み付け制御信号ME1ないしME3のそれぞれの値を0に決定する。
Further, when the delay amount X is 0 or positive, the logic circuit 92 determines the respective values of the weighting control signals ME1 to ME3 as 0.
論理回路92は、その値を決定した重み付け制御信号ME1を乗算器5aの制御端子に入力し、その値を決定した重み付け制御信号ME2を乗算器5bの制御端子に入力し、その値を決定した重み付け制御信号ME3を乗算器5cの制御端子に入力する。
The logic circuit 92 inputs the weighting control signal ME1 whose value is determined to the control terminal of the multiplier 5a, and inputs the weighting control signal ME2 whose value is determined to the control terminal of the multiplier 5b, thereby determining the value. The weighting control signal ME3 is input to the control terminal of the multiplier 5c.
論理回路93は、カウント信号nが示す遅延量Xに応じて重み付け制御信号ML1ないしML3の値を決定する。
The logic circuit 93 determines the values of the weighting control signals ML1 to ML3 according to the delay amount X indicated by the count signal n.
具体的には、遅延量Xが正の場合、論理回路93は、遅延量Xが大きくなるほど、重み付け制御信号ML1ないしML3の値を大きくする。このとき、重み付け制御信号ML3の値より重み付け制御信号ME2の値を大きくし、重み付け制御信号ME2の値より重み付け制御信号ME1の値を大きくすることが望ましい。
Specifically, when the delay amount X is positive, the logic circuit 93 increases the values of the weighting control signals ML1 to ML3 as the delay amount X increases. At this time, it is desirable to make the value of the weighting control signal ME2 larger than the value of the weighting control signal ML3 and make the value of the weighting control signal ME1 larger than the value of the weighting control signal ME2.
例えば、論理回路93は、重み付け制御信号ML1の値を、遅延量Xに1を加えた値に決定し、重み付け制御信号ML2の値を、遅延量Xに決定し、重み付け制御信号ML3の値を、遅延量Xから1を引いた値に決定する。
For example, the logic circuit 93 determines the value of the weighting control signal ML1 as a value obtained by adding 1 to the delay amount X, determines the value of the weighting control signal ML2 as the delay amount X, and sets the value of the weighting control signal ML3 as the value. The value is determined by subtracting 1 from the delay amount X.
また、遅延量Xが負または0の場合、論理回路92は、重み付け制御信号ME1ないしME3のそれぞれの値を0に決定する。
Further, when the delay amount X is negative or 0, the logic circuit 92 determines the respective values of the weighting control signals ME1 to ME3 as 0.
論理回路93は、その値を決定した重み付け制御信号ML1を乗算器6aの制御端子に入力し、その値を決定した重み付け制御信号ML2を乗算器6bの制御端子に入力し、その値を決定した重み付け制御信号ML3を乗算器6cの制御端子に入力する。
The logic circuit 93 inputs the weighted control signal ML1 whose value is determined to the control terminal of the multiplier 6a, and inputs the weighted control signal ML2 whose value is determined to the control terminal of the multiplier 6b, and determines the value. The weight control signal ML3 is input to the control terminal of the multiplier 6c.
次に動作を説明する。図23は、本実施形態の位相比較器の動作を説明するためのフローチャートである。
Next, the operation will be described. FIG. 23 is a flowchart for explaining the operation of the phase comparator of the present embodiment.
ステップT1では、制御ロジック回路9のカウンタ91に、バイナリ型位相比較器45からEarly/Late2信号が入力される。カウンタ91は、そのEarly/Late2信号がHレベルかLレベルかを判断する。カウンタ91は、Early/Late2信号がHレベルであると、ステップT2を実行し、カウンタ91は、Early/Late2信号がLレベルであると、ステップT3を実行する。
In step T1, the Early / Late2 signal is input from the binary phase comparator 45 to the counter 91 of the control logic circuit 9. The counter 91 determines whether the Early / Late2 signal is H level or L level. The counter 91 executes Step T2 when the Early / Late2 signal is at the H level, and the counter 91 executes Step T3 when the Early / Late2 signal is at the L level.
ステップT2では、カウンタ91は、保持しているカウント値をカウントアップする。カウンタ91は、そのカウントアップしたカウント値に応じて遅延量Xを求める。カウンタ91は、遅延量Xを示すカウント信号nを遅延制御信号DLYとして可変遅延回路3の制御端子に入力すると共に、そのカウント信号nを論理回路92および93のそれぞれの入力端子に入力する。その後、ステップT4が実行される。
In step T2, the counter 91 counts up the held count value. The counter 91 obtains the delay amount X according to the counted up count value. The counter 91 inputs the count signal n indicating the delay amount X as a delay control signal DLY to the control terminal of the variable delay circuit 3 and inputs the count signal n to the input terminals of the logic circuits 92 and 93. Thereafter, Step T4 is executed.
ステップT3では、カウンタ91は、保持しているカウント値をカウントダウンする。カウンタ91は、そのカウントダウンしたカウント値に応じて遅延量Xを求める。カウンタ91は、遅延量Xを示すカウント信号nを遅延制御信号DLYとして可変遅延回路3の制御端子に入力すると共に、そのカウント信号nを論理回路92および93のそれぞれの入力端子に入力する。その後、ステップT4が実行される。
In step T3, the counter 91 counts down the held count value. The counter 91 obtains the delay amount X according to the counted down count value. The counter 91 inputs the count signal n indicating the delay amount X as a delay control signal DLY to the control terminal of the variable delay circuit 3 and inputs the count signal n to the input terminals of the logic circuits 92 and 93. Thereafter, Step T4 is executed.
ステップT4では、論理回路92は、そのカウント信号nが示す遅延量Xが負か否かを判断する。
In step T4, the logic circuit 92 determines whether or not the delay amount X indicated by the count signal n is negative.
遅延量Xが負の場合、論理回路92は、重み付け制御信号ME1の値を、遅延量Xの絶対値から1を引いた値に決定し、重み付け制御信号ME2の値を、遅延量Xの絶対値に決定し、重み付け制御信号ME3の値を、遅延量Xの絶対値に1を加えた値に決定する。一方、遅延量Xが0または正の場合、論理回路92は、重み付け制御信号ME1ないしME3のそれぞれの値を0に決定する。
When the delay amount X is negative, the logic circuit 92 determines the value of the weighting control signal ME1 as a value obtained by subtracting 1 from the absolute value of the delay amount X, and sets the value of the weighting control signal ME2 as the absolute value of the delay amount X. The value of the weight control signal ME3 is determined to be a value obtained by adding 1 to the absolute value of the delay amount X. On the other hand, when the delay amount X is 0 or positive, the logic circuit 92 determines the respective values of the weighting control signals ME1 to ME3 as 0.
論理回路92は、その決定した値を有する重み付け制御信号ME1ないしME3を生成し、重み付け制御信号ME1を乗算器5aの制御端子に入力し、重み付け制御信号ME2を乗算器5bの制御端子に入力し、重み付け制御信号ME3を乗算器6cの制御端子に入力する。
The logic circuit 92 generates weighting control signals ME1 to ME3 having the determined values, inputs the weighting control signal ME1 to the control terminal of the multiplier 5a, and inputs the weighting control signal ME2 to the control terminal of the multiplier 5b. The weight control signal ME3 is input to the control terminal of the multiplier 6c.
また、論理回路93は、そのカウント信号nが示す遅延量Xが正か否かを判断する。
Also, the logic circuit 93 determines whether or not the delay amount X indicated by the count signal n is positive.
遅延量Xが正の場合、論理回路93は、重み付け制御信号ML1の値を、遅延量Xから1を引いた値に決定し、重み付け制御信号ML2の値を、遅延量Xに決定し、重み付け制御信号ML3の値を、遅延量Xに1を加えた値に決定する。一方、遅延量Xが負または0の場合、論理回路93は、重み付け制御信号ML1ないしML3のそれぞれの値を0に決定する。
When the delay amount X is positive, the logic circuit 93 determines the value of the weighting control signal ML1 as a value obtained by subtracting 1 from the delay amount X, determines the value of the weighting control signal ML2 as the delay amount X, and performs weighting. The value of the control signal ML3 is determined to be a value obtained by adding 1 to the delay amount X. On the other hand, when the delay amount X is negative or 0, the logic circuit 93 determines each value of the weighting control signals ML1 to ML3 as 0.
論理回路93は、その決定した値を有する重み付け制御信号ML1ないしML3を生成し、重み付け制御信号ML1を乗算器6aの制御端子に入力し、重み付け制御信号ML2を乗算器6bの制御端子に入力し、重み付け制御信号ML3を乗算器6cの制御端子に入力する。
The logic circuit 93 generates weighting control signals ML1 to ML3 having the determined values, inputs the weighting control signal ML1 to the control terminal of the multiplier 6a, and inputs the weighting control signal ML2 to the control terminal of the multiplier 6b. The weight control signal ML3 is input to the control terminal of the multiplier 6c.
図24は、本実施形態の動作例を示した説明図である。図24は、信号φ1の位相が信号φ2の位相より遅れている場合を示している。
FIG. 24 is an explanatory view showing an operation example of the present embodiment. FIG. 24 shows a case where the phase of the signal φ1 is delayed from the phase of the signal φ2.
遅延信号φ2’、φ2’’およびφ2’’’の位相が遅れていき、信号φ2’’の位相が信号φ1の位相より遅れると、その後、Early2信号とLate2信号が交互にHレベルになる。
When the phases of the delay signals φ2 ′, φ2 ″, and φ2 ″ ″ are delayed and the phase of the signal φ2 ″ is delayed from the phase of the signal φ1, the Early2 signal and the Late2 signal alternately become H level.
このとき、Late2信号がLレベルになっても、Late1信号がHレベルになるので、Late2’信号の値が0になっても、Late1’信号の値が0より大きくなる。したがって、マルチプレクサ21からそのLate1’信号がLate’信号として出力される。よって、Late’信号が、信号φ1およびφ2の位相差を示さなくなるという問題を解決することができる。
At this time, even if the Late2 signal becomes L level, the Late1 signal becomes H level. Therefore, even if the value of the Late2 'signal becomes 0, the value of the Late1' signal becomes larger than 0. Accordingly, the Late1 'signal is output from the multiplexer 21 as the Late' signal. Therefore, the problem that the Late ′ signal does not show the phase difference between the signals φ1 and φ2 can be solved.
次に効果を説明する。
Next, the effect will be explained.
本実施形態では、遅延回路18は、遅延信号φ2’を所定遅延量だけ遅延して、遅延信号φ2’’を生成する。遅延回路19は、その遅延信号φ2’’を予め定められた特定遅延量だけ遅延して、遅延信号φ2’’’を生成する。バイナリ型位相比較器44は、信号φ1の位相と、遅延信号φ2’の位相との前後関係を判別し、その前後関係を示すEarly/Late1信号を出力する。バイナリ型位相比較器45は、信号φ1の位相と、遅延信号φ2’’の位相との前後関係を判別し、その前後関係を示すEarly/Late2信号を出力する。バイナリ型位相比較器46は、その信号φ1の位相と、遅延信号φ2’’’の位相との前後関係を判別し、その前後関係を示すEarly/Late3信号を出力する。重み付け部は、第一判別結果、第二判別結果および第三判別結果のそれぞれに制御ロジック回路が決定した重み値を付与する。出力端子7および8と、マルチプレクサ20および21を有する出力部は、重み付け部が重み値を付与した第一判別結果、第二判別結果および第三判別結果のうち、最も位相差が大きいことを示し信号を誤差信号として出力することになる。
In this embodiment, the delay circuit 18 delays the delay signal φ2 ′ by a predetermined delay amount to generate the delay signal φ2 ″. The delay circuit 19 delays the delay signal φ2 ″ by a predetermined specific delay amount to generate a delay signal φ2 ″ ″. The binary phase comparator 44 discriminates the front-rear relationship between the phase of the signal φ1 and the phase of the delay signal φ2 ', and outputs an Early / Late1 signal indicating the front-rear relationship. The binary phase comparator 45 determines the front-rear relationship between the phase of the signal φ1 and the phase of the delayed signal φ2 ″, and outputs an Early / Late2 signal indicating the front-rear relationship. The binary phase comparator 46 discriminates the front-rear relationship between the phase of the signal φ1 and the phase of the delayed signal φ2 '' ', and outputs an Early / Late3 signal indicating the front-rear relationship. The weighting unit assigns the weight value determined by the control logic circuit to each of the first determination result, the second determination result, and the third determination result. The output unit having the output terminals 7 and 8 and the multiplexers 20 and 21 indicates that the phase difference is the largest among the first discrimination result, the second discrimination result, and the third discrimination result to which the weighting unit has assigned weight values. The signal is output as an error signal.
この場合、重み値を付与された第二判別結果が信号φ1およびφ2の位相差を示さなくなる場合でも、信号φ1およびφ2の位相差を示すような誤差信号を出力することができる。
In this case, even when the second determination result given the weight value does not indicate the phase difference between the signals φ1 and φ2, an error signal indicating the phase difference between the signals φ1 and φ2 can be output.
次に第十一の実施形態について説明する。
Next, an eleventh embodiment will be described.
位相比較器がPLL回路などクロック生成回路で用いられると、フィードバックループ信号φ1およびφ2の位相差がなくなるように、信号φ1およびφ2の位相がロックされる。このような状況では、遅延信号φ2’の位相を故意に変動させることで、信号φ1およびφ2の位相差をより細かく判別することができる。
When the phase comparator is used in a clock generation circuit such as a PLL circuit, the phases of the signals φ1 and φ2 are locked so that the phase difference between the feedback loop signals φ1 and φ2 is eliminated. In such a situation, the phase difference between the signals φ1 and φ2 can be determined more finely by intentionally changing the phase of the delay signal φ2 '.
これを実現するために、制御ロジック回路9のカウンタ91は、遅延信号φ2’の位相を変動する変動制御信号が入力されると、可変遅延回路3の遅延量を変動させる。このとき、その遅延量の平均値は0であることが望ましい。
To realize this, the counter 91 of the control logic circuit 9 varies the delay amount of the variable delay circuit 3 when a variation control signal that varies the phase of the delay signal φ2 'is input. At this time, it is desirable that the average value of the delay amount is zero.
例えば、制御ロジック回路9は、図25Aに示すように、その遅延量をランダムに変動させる。
For example, the control logic circuit 9 randomly varies the delay amount as shown in FIG. 25A.
また、制御ロジック回路9は、その遅延量を、第一の閾値まで徐々に変動させ、その後、第二の閾値まで徐々に変動させる処理を繰り返してもよい。例えば、制御ロジック回路9は、図25Bに示すように、その遅延量を三角波状に変動させてもよいし、図25Cに示すように、その遅延量を正弦波状に変動させてもよい。
Further, the control logic circuit 9 may repeat the process of gradually changing the delay amount to the first threshold value and then gradually changing the delay amount to the second threshold value. For example, the control logic circuit 9 may change the delay amount in a triangular wave shape as shown in FIG. 25B, or may change the delay amount in a sine wave shape as shown in FIG. 25C.
この場合、遅延制御信号DLYが示す遅延量を変動させた場合に、Early信号がHレベルとなる回数と、Late信号がHレベルとなる回数との大小関係から、信号φ1およびφ2の位相差をより細かく判別することができる。例えば、Late信号がHレベルとなる回数が、Early信号がHレベルとなる回数より少しだけ多いと、信号φ1は、信号φ2より少しだけ遅れていることになる。このように故意に遅延信号φ2の位相を変動させることで、信号φ1とφ2の位相差をより細かく判別することができる。
In this case, when the delay amount indicated by the delay control signal DLY is changed, the phase difference between the signals φ1 and φ2 is determined from the magnitude relationship between the number of times the Early signal becomes H level and the number of times the Late signal becomes H level. It can be determined more finely. For example, if the number of times that the Late signal becomes H level is slightly larger than the number of times that the Early signal becomes H level, the signal φ1 is slightly delayed from the signal φ2. In this way, by intentionally changing the phase of the delay signal φ2, the phase difference between the signals φ1 and φ2 can be determined more finely.
次に効果を説明する。
Next, the effect will be explained.
本実施形態では、制御ロジック回路9は、変動制御信号が入力された場合、可変遅延回路3の遅延量の平均値が0になるように、その遅延量を変動させる。
In this embodiment, when a variation control signal is input, the control logic circuit 9 varies the delay amount so that the average delay amount of the variable delay circuit 3 becomes zero.
この場合、信号φ1およびφ2の位相差をより細かく判別することができる。
In this case, the phase difference between the signals φ1 and φ2 can be determined more finely.
次に第十二の実施形態を説明する。本実施形態では、上述の各実施形態で説明した位相比較器を用いたPLL回路を説明する。
Next, a twelfth embodiment will be described. In this embodiment, a PLL circuit using the phase comparator described in each of the above embodiments will be described.
図26は、本実施形態のPLL回路を示したブロック図である。図26において、PLL回路は、位相比較器101と、デジタルフィルタ102と、DCO(Digital Controlled Oscillator:デジタル制御発振器)103と、分周器104とを含む。
FIG. 26 is a block diagram showing the PLL circuit of the present embodiment. In FIG. 26, the PLL circuit includes a phase comparator 101, a digital filter 102, a DCO (Digital Controlled Oscillator) 103, and a frequency divider 104.
位相比較器101は、第一の実施形態から第十一の実施形態で説明した位相比較器のいずれかの構成を有する。
The phase comparator 101 has one of the configurations of the phase comparators described in the first to eleventh embodiments.
位相比較器101には、信号φ1(またはデータ信号Din)として参照信号が入力される。デジタルフィルタ102は、位相比較器101から出力された誤差信号を平滑化し、その平滑化した誤差信号をDCO103に入力する。
The reference signal is input to the phase comparator 101 as the signal φ1 (or data signal Din). The digital filter 102 smoothes the error signal output from the phase comparator 101 and inputs the smoothed error signal to the DCO 103.
DCO103は、その入力された誤差信号に応じた周波数で発振し、その発振した周波数の信号を制御クロック信号として出力するとともに、その制御クロック信号を分周器104に入力する。分周器104は、その入力された制御クロック信号をN分周し、そのN分周した制御クロック信号を信号φ2(またはクロック信号ψ2)として位相比較器101に入力する。
The DCO 103 oscillates at a frequency corresponding to the input error signal, outputs a signal of the oscillated frequency as a control clock signal, and inputs the control clock signal to the frequency divider 104. The frequency divider 104 divides the input control clock signal by N and inputs the N-divided control clock signal to the phase comparator 101 as a signal φ2 (or clock signal ψ2).
なお、CDR回路も図26で示したPLL回路と同様な構成で実現することができる。
Note that the CDR circuit can also be realized with the same configuration as the PLL circuit shown in FIG.
本実施形態によれば、消費電力および回路面積の増加を抑制しながら、位相差を判別することが可能になる。したがって、消費電力および回路面積の増加を抑制しながら、2つの入力信号の位相差を0に収束させるフィードバックループの利得を一定にすることが可能になる。
According to the present embodiment, it is possible to determine the phase difference while suppressing increase in power consumption and circuit area. Therefore, the gain of the feedback loop that converges the phase difference between the two input signals to 0 can be made constant while suppressing increases in power consumption and circuit area.
次に第十三の実施形態を説明する。本実施形態では、上述の各実施形態で説明した位相比較器を用いたDLL回路を説明する。
Next, a thirteenth embodiment will be described. In this embodiment, a DLL circuit using the phase comparator described in each of the above embodiments will be described.
図27は、本実施形態のDLL回路を示したブロック図である。図27において、DLL回路は、位相比較器101と、デジタルフィルタ102と、分周器104と、入力端子201と、DCDL(Digital Voltage Controlled Delay Line:デジタル制御遅延ライン)202とを含む。
FIG. 27 is a block diagram showing the DLL circuit of this embodiment. In FIG. 27, the DLL circuit includes a phase comparator 101, a digital filter 102, a frequency divider 104, an input terminal 201, and a DCDL (Digital Voltage Controlled Delay Line: digital control delay line) 202.
デジタルフィルタ102は、位相比較器101から出力された誤差信号を平滑化し、その平滑化した誤差信号をDCDL202に入力する。
Digital filter 102 smoothes the error signal output from phase comparator 101, and inputs the smoothed error signal to DCDL 202.
入力端子201には、基準クロック信号が入力され、その基準クロック信号をDCDL202に入力する。なお、入力端子201は、クロック入力手段の一例である。
A reference clock signal is input to the input terminal 201, and the reference clock signal is input to the DCDL 202. The input terminal 201 is an example of a clock input unit.
DCDL202は、その入力された誤差信号に応じて、その入力された基準クロック信号を遅延し、その遅延した基準クロック信号を制御クロック信号として出力するとともに、その制御クロック信号を分周器104に入力する。
The DCDL 202 delays the input reference clock signal in accordance with the input error signal, outputs the delayed reference clock signal as a control clock signal, and inputs the control clock signal to the frequency divider 104. To do.
なお、CDR回路も図27で示したDLL回路と同様な構成で実現することができる。
The CDR circuit can also be realized with the same configuration as the DLL circuit shown in FIG.
本実施形態によれば、消費電力および回路面積の増加を抑制しながら、位相差を判別することが可能になる。したがって、消費電力および回路面積の増加を抑制しながら、2つの入力信号の位相差を0に収束させるフィードバックループの利得を一定にすることが可能になる。
According to the present embodiment, it is possible to determine the phase difference while suppressing increase in power consumption and circuit area. Therefore, the gain of the feedback loop that converges the phase difference between the two input signals to 0 can be made constant while suppressing increases in power consumption and circuit area.
以上、実施形態を参照して本願発明を説明したが、本願発明は、上記実施形態に限定されたものではない。本願発明の構成や詳細には、本願発明のスコープ内で当業者が理解し得る様々な変更を行うことができる。
As mentioned above, although this invention was demonstrated with reference to embodiment, this invention is not limited to the said embodiment. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention.
例えば、可変遅延回路3は、信号φ2を遅延させていたが、信号φ1およびφ2のどちらか一方を遅延させればよい。
For example, the variable delay circuit 3 delays the signal φ2, but it is only necessary to delay one of the signals φ1 and φ2.
この出願は、2008年8月7日に出願された日本出願特願2008-204494号公報を基礎とする優先権を主張し、その開示の全てをここに取り込む。
This application claims priority based on Japanese Patent Application No. 2008-204494 filed on Aug. 7, 2008, the entire disclosure of which is incorporated herein.
Claims (11)
- 第一入力信号が入力される第一入力手段と、
第二入力信号が入力される第二入力手段と、
前記第二入力手段に入力された第二入力信号の位相を調整して、調整入力信号を生成する調整手段と、
前記第一入力手段に入力された第一入力信号の位相と、前記調整手段が生成した調整入力信号の位相との前後関係を判別し、該前後関係を示す判別結果を出力する判別手段と、
前記判別手段から出力された判別結果が示す前後関係が変化するように、前記調整手段の調整量を調節していき、該調節した調整量に応じて、前記判別結果に付与する重み値を決定する制御手段と、
前記判別手段から出力された判別結果に前記制御手段が決定した重み値を付与する重み付け手段と、
前記重み付け手段が前記重み値を付与した判別結果を、前記第一入力信号の位相と前記第二入力信号の位相との前後関係と、前記第一入力信号および前記第二入力信号の位相差とを示す誤差信号として出力する出力手段と、を含む位相比較器。 A first input means for receiving a first input signal;
A second input means for receiving a second input signal;
Adjusting means for adjusting the phase of the second input signal input to the second input means to generate an adjusted input signal;
Discriminating means for discriminating the front-rear relationship between the phase of the first input signal input to the first input unit and the phase of the adjustment input signal generated by the adjusting unit, and outputting a determination result indicating the front-rear relationship;
The adjustment amount of the adjustment unit is adjusted so that the context indicated by the determination result output from the determination unit changes, and a weight value to be given to the determination result is determined according to the adjusted adjustment amount. Control means for
Weighting means for giving a weight value determined by the control means to the discrimination result output from the discrimination means;
The determination result that the weighting unit assigns the weight value includes the anteroposterior relationship between the phase of the first input signal and the phase of the second input signal, and the phase difference between the first input signal and the second input signal. Output means for outputting as an error signal indicating a phase comparator. - 請求の範囲第1項に記載の位相比較器において、
前記調整手段が前記第二入力信号の位相を遅らせている場合に、前記第一入力信号の位相が前記第二入力信号の位相より進んでいることを示す誤差信号が前記出力手段から出力されるのを停止し、前記調整手段が前記第二入力信号の位相を進ませている場合に、前記第一入力信号の位相が前記第二入力信号の位相より遅れていることを示す誤差信号が前記出力手段から出力されるのを停止する出力制御手段と、を含む位相比較器。 In the phase comparator according to claim 1,
When the adjusting unit delays the phase of the second input signal, an error signal indicating that the phase of the first input signal is ahead of the phase of the second input signal is output from the output unit. When the adjustment means advances the phase of the second input signal, an error signal indicating that the phase of the first input signal is delayed from the phase of the second input signal is Output control means for stopping output from the output means, and a phase comparator. - 請求の範囲第1項または第2項に記載の位相比較器において、
前記第二入力手段には、前記第二入力信号より位相が進んだ先行信号と、前記第二入力信号より位相が遅れた後行信号とがさらに入力され、
前記判別手段は、
前記第一入力手段に入力された第一入力信号を、前記第二入力手段に入力された先行信号のエッジのタイミングで保持し、該保持した第一入力信号を出力する第一保持手段と、
前記第一入力手段に入力された第一入力信号を、前記調整手段が生成した調整入力信号のエッジのタイミングで保持し、該保持した第一入力信号を出力する第二保持手段と、
前記第一入力手段に入力された第一入力信号を、前記第二入力手段に入力された後行信号のエッジのタイミングで保持し、該保持した第一入力信号を出力する第三保持手段と、
前記第一保持手段から出力された第一入力信号と、前記第二保持手段から出力された第一入力信号と、が互いに異なっていると、前記第一入力信号の位相が前記調整入力信号の位相より進んでいることを示す判別結果を出力し、前記第二保持手段から出力された第一入力信号と、前記第三保持手段から出力された第一入力信号と、が互いに異なっていると、前記第一入力信号の位相が前記調整入力信号の位相より遅れていることを示す判別結果を出力する選択出力手段と、を含む、位相比較器。 In the phase comparator according to claim 1 or 2,
The second input means further receives a preceding signal whose phase is advanced from the second input signal and a succeeding signal whose phase is delayed from the second input signal.
The discrimination means includes
First holding means for holding the first input signal input to the first input means at the timing of the edge of the preceding signal input to the second input means, and outputting the held first input signal;
A second holding means for holding the first input signal input to the first input means at the edge timing of the adjustment input signal generated by the adjustment means, and outputting the held first input signal;
Third holding means for holding the first input signal input to the first input means at the edge timing of the subsequent signal input to the second input means and outputting the held first input signal; ,
When the first input signal output from the first holding unit and the first input signal output from the second holding unit are different from each other, the phase of the first input signal is the phase of the adjustment input signal. A determination result indicating that the phase is advanced is output, and the first input signal output from the second holding unit and the first input signal output from the third holding unit are different from each other. And a selection output means for outputting a discrimination result indicating that the phase of the first input signal is delayed from the phase of the adjustment input signal. - 請求の範囲第3項に記載の位相比較器において、
クロック信号が入力される第三入力手段を含み、
前記判別手段は、
前記第一保持手段から出力された第一入力信号を、前記第三入力手段に入力されたクロック信号のエッジのタイミングで保持し、該保持した第一入力信号を出力する第四保持手段と、
前記第二保持手段から出力された第一入力信号を、前記第三入力手段に入力されたクロック信号のエッジのタイミングで保持し、該保持した第一入力信号を出力する第五保持手段と、
前記第三保持手段から出力された第一入力信号を、前記第三入力手段に入力されたクロック信号のエッジのタイミングで保持し、該保持した第一入力信号を出力する第六保持手段と、を含み、
前記選択出力手段は、前記第四保持手段から出力された第一入力信号と、前記第五保持手段から出力された第一入力信号と、が互いに異なっていると、前記第一入力信号の位相が前記調整入力信号の位相より進んでいることを示す判別結果を出力し、前記第五保持手段から出力された第一入力信号と、前記第六保持手段から出力された第一入力信号と、が互いに異なっていると、前記第一入力信号の位相が前記調整入力信号の位相より遅れていることを示す判別結果を出力する、位相比較器。 In the phase comparator according to claim 3,
Including a third input means for inputting a clock signal;
The discrimination means includes
Fourth holding means for holding the first input signal output from the first holding means at the edge timing of the clock signal input to the third input means, and outputting the held first input signal;
A fifth holding means for holding the first input signal output from the second holding means at the timing of the edge of the clock signal input to the third input means, and outputting the held first input signal;
Sixth holding means for holding the first input signal output from the third holding means at the timing of the edge of the clock signal input to the third input means, and outputting the held first input signal; Including
The selection output means, when the first input signal output from the fourth holding means and the first input signal output from the fifth holding means are different from each other, the phase of the first input signal Output a determination result indicating that the phase is advanced from the phase of the adjustment input signal, the first input signal output from the fifth holding means, the first input signal output from the sixth holding means, And a phase comparator that outputs a discrimination result indicating that the phase of the first input signal is delayed from the phase of the adjustment input signal. - 請求の範囲第1項ないし第4項のいずれか1項に記載の位相比較器において、
前記制御手段は、
カウント値を保持し、前記判別結果に基づいて、前記カウント値をカウントアップまたはカウントダウンし、該カウントアップまたはカウントダウンしたカウント値に応じて、前記調整量を調節するカウント手段と、
前記カウント手段が調節した調整量に応じて前記重み値を決定する決定手段と、を含む、位相比較器。 In the phase comparator according to any one of claims 1 to 4,
The control means includes
Counting means for holding a count value, counting up or counting down the count value based on the determination result, and adjusting the adjustment amount according to the count up or down count value;
Determining means for determining the weight value according to the adjustment amount adjusted by the counting means. - 請求の範囲第5項に記載の位相比較器において、
前記調整手段が生成した調整入力信号を所定遅延量だけ遅延する第一遅延手段と、
前記第一遅延手段が遅延した調整入力信号を特定遅延量だけ遅延する第二遅延手段と、を含み、
前記判別手段は、
前記第一入力手段に入力された第一入力信号の位相と、前記調整手段が生成した調整入力信号の位相との前後関係を判別し、該前後関係を示す第一判別結果を前記判別結果として出力する第一判定手段と、
前記第一入力手段に入力された第一入力信号の位相と、前記第一遅延手段が遅延した調整入力信号の位相との前後関係を判別し、該前後関係を示す第二判別結果を前記判別結果として出力する第二判定手段と、
前記第一入力手段に入力された第一入力信号の位相と、前記第一遅延手段が遅延した調整入力信号の位相との前後関係を判別し、該前後関係を示す第三判別結果を前記判別結果として出力する第三判定手段と、を含み、
前記重み付け手段は、前記第一判別結果、前記第二判別結果および前記第三判別結果のそれぞれに前記制御手段が決定した重み値を付与し、
前記出力手段は、前記重み付け手段が前記重み値を付与した第一判別結果、第二判別結果および第三判別結果のうち、最も位相差が大きいことを示す信号を前記誤差信号として出力する、位相比較器。 In the phase comparator according to claim 5,
First delay means for delaying the adjustment input signal generated by the adjustment means by a predetermined delay amount;
Second delay means for delaying the adjusted input signal delayed by the first delay means by a specific delay amount,
The discrimination means includes
The front-rear relationship between the phase of the first input signal input to the first input unit and the phase of the adjustment input signal generated by the adjustment unit is determined, and a first determination result indicating the front-rear relationship is used as the determination result. First determination means for outputting;
Determining the front-rear relationship between the phase of the first input signal input to the first input unit and the phase of the adjustment input signal delayed by the first delay unit, and determining a second determination result indicating the front-rear relationship; Second determination means for outputting as a result;
Determining the front-rear relationship between the phase of the first input signal input to the first input unit and the phase of the adjustment input signal delayed by the first delay unit, and determining the third determination result indicating the front-rear relationship; Third determination means for outputting as a result,
The weighting unit gives the weight value determined by the control unit to each of the first determination result, the second determination result, and the third determination result,
The output means outputs, as the error signal, a signal indicating that the phase difference is the largest among the first discrimination result, the second discrimination result, and the third discrimination result to which the weighting unit has assigned the weight value. Comparator. - 請求の範囲第1項ないし第6項のいずれか1項に記載の位相比較器において、
前記制御手段は、前記調整入力信号の位相を変動する変動制御信号が入力された場合、前記調整量の平均値が0になるように、前記調整量を変動させる、位相比較器。 The phase comparator according to any one of claims 1 to 6, wherein
The control means is a phase comparator that varies the adjustment amount so that an average value of the adjustment amounts becomes zero when a variation control signal that varies the phase of the adjustment input signal is input. - 請求の範囲第1項または第2項に記載の位相比較器において、
前記判別手段は、前記第一入力信号および前記調整入力信号の位相差をさらに判別し、該位相差をさらに示す判別結果を出力し、
前記重み付け手段は、前記判別手段が出力した判別結果に前記重み値を加算し、
前記制御手段は、前記判別結果に基づいて、前記調整量を、前記判別手段が判別する位相差の分解能より小さい単位で調節する、位相比較器。 In the phase comparator according to claim 1 or 2,
The determination means further determines a phase difference between the first input signal and the adjustment input signal, and outputs a determination result further indicating the phase difference,
The weighting means adds the weight value to the discrimination result output by the discrimination means,
The control means adjusts the adjustment amount in units smaller than the resolution of the phase difference determined by the determination means based on the determination result. - 請求の範囲第8項に記載の位相比較器において、
前記制御手段は、前記第一入力信号および前記調整入力信号の位相差が、前記判別手段にて判別可能な範囲を超えている場合、該位相差が前記範囲に含まれるように、前記調整量を調節する、位相比較器。 In the phase comparator according to claim 8,
When the phase difference between the first input signal and the adjustment input signal exceeds a range discriminable by the discriminating unit, the control unit adjusts the adjustment amount so that the phase difference is included in the range. Adjust the phase comparator. - 請求の範囲第1項ないし第9項のいずれか1項に記載の位相比較器と、
前記位相比較器から出力された誤差信号を平滑化するフィルタ手段と、
前記フィルタ手段が平滑化した誤差信号に応じた周波数で発振し、該発振した周波数の信号を前記第一入力信号または前記第二入力信号として前記位相比較器に入力する発振手段と、を含むPLL回路。 A phase comparator according to any one of claims 1 to 9,
Filter means for smoothing the error signal output from the phase comparator;
An oscillation means for oscillating at a frequency corresponding to the error signal smoothed by the filter means and inputting the signal of the oscillated frequency to the phase comparator as the first input signal or the second input signal. circuit. - 請求の範囲第1項ないし第9項のいずれか1項に記載の位相比較器と、
クロック信号が入力されるクロック入力手段と、
前記位相比較器から出力された誤差信号を平滑化するフィルタ手段と、
前記フィルタ手段が平滑化した誤差信号に応じて、前記クロック入力手段に入力されたクロック信号を遅延し、該遅延したクロック信号を前記第一の入力信号または前記第二入力信号として前記位相比較器に入力する制御遅延手段と、を含むDLL回路。 A phase comparator according to any one of claims 1 to 9,
A clock input means for inputting a clock signal;
Filter means for smoothing the error signal output from the phase comparator;
In response to the error signal smoothed by the filter means, the clock signal input to the clock input means is delayed, and the delayed clock signal is used as the first input signal or the second input signal as the phase comparator. And a control delay means for inputting to the DLL circuit.
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Cited By (3)
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JP2015033123A (en) * | 2013-08-07 | 2015-02-16 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
WO2017119183A1 (en) * | 2016-01-08 | 2017-07-13 | ソニー株式会社 | Synchronization circuit and control method for synchronization circuit |
US10291214B2 (en) | 2017-03-01 | 2019-05-14 | Analog Devices Global Unlimited Company | Feedforward phase noise compensation |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61227422A (en) * | 1985-03-30 | 1986-10-09 | Toshiba Corp | Phase comparator circuit |
JPS61232716A (en) * | 1985-04-08 | 1986-10-17 | Sumitomo Electric Ind Ltd | Phase comparator |
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JPS61227422A (en) * | 1985-03-30 | 1986-10-09 | Toshiba Corp | Phase comparator circuit |
JPS61232716A (en) * | 1985-04-08 | 1986-10-17 | Sumitomo Electric Ind Ltd | Phase comparator |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2015033123A (en) * | 2013-08-07 | 2015-02-16 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
WO2017119183A1 (en) * | 2016-01-08 | 2017-07-13 | ソニー株式会社 | Synchronization circuit and control method for synchronization circuit |
JPWO2017119183A1 (en) * | 2016-01-08 | 2018-10-25 | ソニー株式会社 | Synchronous circuit and method for controlling synchronous circuit |
US10291214B2 (en) | 2017-03-01 | 2019-05-14 | Analog Devices Global Unlimited Company | Feedforward phase noise compensation |
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