WO2010016171A1 - Manufacturing method of dielectric thin-film capacitor and dielectric thin-film capacitor - Google Patents
Manufacturing method of dielectric thin-film capacitor and dielectric thin-film capacitor Download PDFInfo
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- WO2010016171A1 WO2010016171A1 PCT/JP2009/002090 JP2009002090W WO2010016171A1 WO 2010016171 A1 WO2010016171 A1 WO 2010016171A1 JP 2009002090 W JP2009002090 W JP 2009002090W WO 2010016171 A1 WO2010016171 A1 WO 2010016171A1
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- electrode
- thin film
- layer
- capacitor
- dielectric
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- 239000003990 capacitor Substances 0.000 title claims abstract description 142
- 239000010409 thin film Substances 0.000 title claims abstract description 107
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 103
- 238000010438 heat treatment Methods 0.000 claims abstract description 24
- 230000015572 biosynthetic process Effects 0.000 claims description 12
- 238000000034 method Methods 0.000 abstract description 27
- 239000010408 film Substances 0.000 description 19
- 238000009792 diffusion process Methods 0.000 description 18
- 230000002265 prevention Effects 0.000 description 15
- 229920002120 photoresistant polymer Polymers 0.000 description 13
- 229910052751 metal Inorganic materials 0.000 description 11
- 239000002184 metal Substances 0.000 description 11
- 229910052710 silicon Inorganic materials 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 7
- 239000011347 resin Substances 0.000 description 7
- 229920005989 resin Polymers 0.000 description 7
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 6
- 230000001681 protective effect Effects 0.000 description 6
- 230000005496 eutectics Effects 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 238000004544 sputter deposition Methods 0.000 description 5
- 229910004298 SiO 2 Inorganic materials 0.000 description 4
- 229910052786 argon Inorganic materials 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 4
- 150000001875 compounds Chemical class 0.000 description 4
- 230000006866 deterioration Effects 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 239000000203 mixture Substances 0.000 description 4
- 239000001301 oxygen Substances 0.000 description 4
- 229910052760 oxygen Inorganic materials 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- -1 Pb (Zr Chemical class 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 238000000992 sputter etching Methods 0.000 description 3
- 238000001771 vacuum deposition Methods 0.000 description 3
- 229910002367 SrTiO Inorganic materials 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 229910052788 barium Inorganic materials 0.000 description 2
- 229910052797 bismuth Inorganic materials 0.000 description 2
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 238000001755 magnetron sputter deposition Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 239000002994 raw material Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 229910052726 zirconium Inorganic materials 0.000 description 2
- 229910018487 Ni—Cr Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- JRPBQTZRNDNNOP-UHFFFAOYSA-N barium titanate Chemical compound [Ba+2].[Ba+2].[O-][Ti]([O-])([O-])[O-] JRPBQTZRNDNNOP-UHFFFAOYSA-N 0.000 description 1
- 229910002113 barium titanate Inorganic materials 0.000 description 1
- 238000000224 chemical solution deposition Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/01—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate comprising only passive thin-film or thick-film elements formed on a common insulating substrate
- H01L27/016—Thin-film circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/002—Details
- H01G4/224—Housing; Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/002—Details
- H01G4/228—Terminals
- H01G4/236—Terminals leading through the housing, i.e. lead-through
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/33—Thin- or thick-film capacitors
Definitions
- the present invention relates to a dielectric thin film capacitor manufacturing method and a dielectric thin film capacitor. More specifically, the present invention relates to a dielectric thin film capacitor manufacturing method in which external electrodes are formed on both sides of a main surface of a conductive substrate, and the manufacturing method. The present invention relates to a dielectric thin film capacitor manufactured using the same.
- an oxide having a perovskite structure such as barium titanate is often used in the dielectric portion of the capacitor.
- a conductive film 102 is in ohmic contact with one surface of a low-resistance silicon substrate 101, and the other surface is almost equal to a titanate-based insulator.
- the first metal electrode 103 having a lattice constant is interposed through a eutectic prevention film 104 having a predetermined pattern for preventing the first metal electrode 103 and the silicon substrate 101 from being eutectic.
- 103 is deposited so as to be connected to the silicon substrate 101, a titanate-based insulating film 105 is deposited on the first metal electrode 103, and a second layer is formed on the insulating film 105.
- a thin film capacitor (dielectric thin film capacitor) having a metal electrode 106 deposited thereon has been proposed.
- Each of the first metal electrode 103 and the second metal electrode 106 has a three-layer structure of Cr layers 103a and 106a, Pt layers 103b and 106b, and Au layers 103c and 106c, and the insulating film 105 is a dielectric portion of the capacitor. It corresponds to.
- the first metal electrode 103 has a structure in which the pattern is formed larger than the eutectic prevention film 104 and is in contact with the silicon substrate 101, and the insulating layer 105 is sputtered at 500 to 600 ° C.
- the first metal electrode 103 and the silicon substrate 101 are eutectic and are in ohmic contact.
- the crystallinity of the dielectric thin film is improved by heat treatment, thereby improving the dielectric characteristics.
- Electrodes are formed on both sides of the silicon substrate 101, such as a thin film capacitor in which a conductive film 102 is formed on the lower surface of the silicon substrate 101 as shown in Patent Document 1, the eutectic portion and silicon are formed when heat treatment is performed. Because of the oxidation, the contact resistance between the first metal electrode 103 and the silicon substrate 101 increases, and the equivalent series resistance (hereinafter referred to as “ESR”) of the capacitor may increase.
- ESR equivalent series resistance
- the present invention has been made in view of such circumstances, and provides a dielectric thin film capacitor manufacturing method and a dielectric thin film capacitor capable of suppressing an increase in ESR without impairing reliability even when heat treatment is performed. For the purpose.
- a method of manufacturing a dielectric thin film capacitor according to the present invention includes forming at least one first external electrode on one main surface side of a conductive substrate, and forming the other main electrode of the conductive substrate.
- a capacitor portion forming step formed on the one main surface of the conductive substrate, and an electrode layer to be one of the electrode layers and the conductive substrate are electrically connected to form a substrate wiring A wiring formation step, and a heat treatment step of heat treating the capacitor portion between the capacitor formation step and the wiring formation step.
- the dielectric thin film capacitor manufacturing method of the present invention further includes an insulating layer forming step of covering the capacitor portion with an insulating layer between the heat treatment step and the wiring forming step, and at least a part of the substrate wiring. Is formed on the insulating layer.
- the dielectric thin film capacitor manufacturing method of the present invention includes a thin film resistance forming step for forming a thin film resistor electrically connected to the capacitor portion between the heat treatment step and the wiring forming step. It is characterized by that.
- the dielectric thin film capacitor manufacturing method of the present invention is characterized in that the thin film resistor forming step forms the thin film resistor in a flat shape.
- At least one first external electrode is formed on one main surface side of the conductive substrate, and the second main surface side of the conductive substrate is a second one.
- a dielectric thin film capacitor in which an external electrode is formed, wherein the capacitor portion including at least one capacitance generating portion having electrode layers on both upper and lower surfaces of the dielectric layer is the one main surface of the conductive substrate.
- An electrode layer that is formed on the electrode layer and is to be one of the electrode layers is electrically connected to the second external electrode via a substrate wiring and the conductive substrate, and the other electrode layer
- An electrode layer to be a pole is electrically connected to the first external electrode, the capacitor portion is heat-treated, and at least the substrate wiring is formed after the heat treatment.
- the dielectric thin film capacitor of the present invention is characterized in that the capacitor portion is covered with an insulating layer, and at least a part of the substrate wiring is formed on the insulating layer.
- the dielectric thin film capacitor of the present invention is characterized in that the thin film resistor is formed so as to be electrically connected to the electrode layer to be the other electrode.
- the dielectric thin film capacitor of the present invention is characterized in that the thin film resistor is formed on a capacitor portion.
- the dielectric thin film capacitor of the present invention is characterized in that the thin film resistor is formed in a flat shape.
- the substrate wiring is formed after the capacitor portion is heat-treated, the substrate wiring is not exposed to the heat treatment atmosphere and oxidized. Accordingly, even if heat treatment is performed, the reliability of the capacitor portion is not impaired, and an increase in ESR can be suppressed.
- the substrate wiring can be made sufficiently thick.
- a low resistance conductive material such as Au or Cu, and it is possible to sufficiently reduce the resistance between the electrode layer to be the one electrode and the second external electrode. is there. That is, it is possible to obtain a high-capacity, high-reliability, low-ESR dielectric thin film capacitor with a high degree of freedom in selecting the material and shape of the wiring and adjusting the length.
- the capacitor portion is covered with an insulating layer before the substrate wiring is formed, it is possible to prevent deterioration of the capacitor characteristics due to etching during wiring formation.
- the thin film resistor is formed on the capacitor portion, it is possible to avoid the increase in size of the element as much as possible even when the thin film resistor is provided.
- the thin film resistor is formed in a flat shape, it is possible to suppress variation in the resistance value of the thin film resistor.
- FIG. 1 is a sectional view showing an embodiment (first embodiment) of a dielectric thin film capacitor manufactured by the manufacturing method of the present invention.
- a diffusion prevention layer 2 made of SiO 2 or the like is formed on one main surface of a conductive substrate 1 made of a semiconductor such as Si, and on the surface of the diffusion prevention layer 2.
- An adhesion layer 3 is formed, and a capacitor portion 4 is formed on the surface of the adhesion layer 3.
- the diffusion prevention layer 2 has a function of preventing elements contained in the conductive substrate 1 from diffusing into the capacitor portion 4.
- the capacitor unit 4 includes a first electrode layer 5 formed on the adhesion layer 3, a dielectric layer 6 formed on the first electrode layer 5, and a first electrode formed on the dielectric layer 6. 2 electrode layers 7.
- the dielectric layer 6 includes, for example, (Ba, Sr) TiO 3 (hereinafter referred to as “BST”), BaTiO 3 , SrTiO 3, etc., Pb (Zr, Ti) O 3 , SrBi 4 Ti 4 O 15, etc.
- BST Ba, Sr TiO 3
- BaTiO 3 BaTiO 3
- SrTiO 3 etc.
- SrBi 4 Ti 4 O 15 etc.
- the bismuth layered compound can be used.
- the capacitor part 4 is preferably heat-treated in an oxygen-containing atmosphere
- the first and second electrode layers 5 and 7 are resistant to heat treatment such as Pt, Au, and Ru.
- a material having properties is preferably used.
- the adhesion layer 3 a material having the same composition as that of the dielectric layer 6 or a material having the same composition can be used.
- the capacitor unit 4 is entirely covered with an insulating layer 8.
- the insulating layer 8 includes an inorganic insulating layer 9 and an organic insulating layer 10.
- the inorganic insulating layer 9 has a function of preventing moisture from the outside from entering the capacitor unit 4 and is made of, for example, SiN x or SiO 2 .
- SiN x as the inorganic insulating layer 9, the molar ratio of Si and N 3: Other 4 stoichiometry having a composition Si 3 N 4, and deviates from the stoichiometric composition as required Compounds can be used.
- the organic insulating layer 10 is formed of a polyimide resin or an epoxy resin, and absorbs mechanical stress from electrode wiring and substrate wiring described later.
- the first electrode layer 5 is connected to the substrate wiring 11, and the second electrode layer 7 is connected to the electrode wiring 12.
- the substrate wiring 11 penetrates the insulating layer 8 (the inorganic insulating layer 9 and the organic insulating layer 1) from the upper surface of the first electrode layer 5, and extends from the organic insulating layer 10 to the side surface of the insulating layer 8. And electrically connected to the first connection electrode 14 that is in ohmic contact with the conductive substrate 1.
- the electrode wiring 12 is formed so as to penetrate the insulating layer 8 (inorganic insulating layer 9 and organic insulating layer 1) from the upper surface of the second electrode layer 7 and to be disposed on the organic insulating layer 10. .
- An upper external electrode (first external electrode) 15 is formed on the upper surface of the electrode wiring 12, and the second electrode layer 7 is electrically connected to the upper external electrode 15 through the electrode wiring 12. .
- the upper surface side of the conductive substrate 1 is covered with a protective resin 18 except for the upper external electrode 15.
- a second connection electrode 16 is formed on the other main surface of the conductive substrate 1, and a lower external electrode (second external electrode) 17 is formed on the second connection electrode 16. .
- first and second connection electrodes 14 and 16 are preferably formed of Au because it is necessary to lower the ESR by making ohmic contact with the conductive substrate 1.
- the upper external electrode 15 and the lower external electrode 17 preferably have a multilayer structure, and for example, Au / Cu, Au / Ni, Sn / Cu can be used.
- the lower external electrode 17 is electrically connected to the first electrode layer 5 via the second connection electrode 16, the conductive substrate 1, the first connection electrode 14, and the substrate wiring 11.
- the upper external electrode 15 is electrically connected to the second electrode layer 7 through the electrode wiring 12.
- a conductive substrate 1 made of, for example, a p-type conductive Si substrate having a thickness of 525 ⁇ m is prepared.
- the diffusion prevention layer 2 and the adhesion layer 3 are sequentially formed.
- the diffusion prevention layer 2 made of SiO 2 or the like having a thickness of 700 nm is formed by a thermal oxidation method.
- an adhesion layer 3 of, eg, a 100 nm-thickness is formed on the diffusion prevention layer 2 by a chemical solution deposition (hereinafter referred to as “CSD”) method or the like.
- CSD chemical solution deposition
- BST SrTiO 3 , BaTiO 3 , perovskite compounds such as Pb (Zr, Ti) O 3 , bismuth layered compounds such as SrBi 4 Ti 4 O 15, etc.
- BST chemical solution deposition
- this film forming raw material solution is applied onto the diffusion preventing layer 2, dried on a hot plate at 300 to 400 ° C., and subjected to crystallization at high temperature heating treatment at a temperature of 650 ° C. for 30 minutes.
- the adhesion layer 3 is formed.
- a first electrode layer 5, a dielectric layer 6, and a second electrode layer 7 are sequentially formed.
- the first electrode layer 5 made of Pt having a film thickness of 200 nm is formed by RF magnetron sputtering or the like, and then the dielectric layer having a film thickness of 100 nm made of BST or the like by the CSD method or the like, similar to the adhesion layer 3. 6 is formed, and then, similarly to the first electrode layer 5, a second electrode layer 6 made of Pt having a thickness of 200 nm is formed by an RF magnetron sputtering method or the like.
- the adhesion layer 3, the first electrode layer 5, the dielectric layer 6, and the second electrode layer 7 are formed by using a well-known photolithography technique, an argon ion milling method, or the like. Is etched into a predetermined pattern to form the capacitor portion 4. That is, after a photoresist is applied and prebaked, the photoresist is irradiated with ultraviolet light through a photomask, and exposure, development, and postbaking are performed to transfer the photomask pattern to the resist pattern.
- argon ions are collided with the etching surface by an argon ion milling method to etch predetermined regions of the second electrode layer 7, the dielectric layer 6, the first electrode layer 5, and the adhesion layer 3, and thereby the capacitor portion 4 is produced.
- the capacitor portion 4 is heat-treated to improve the dielectric characteristics of the dielectric layer 6.
- This heat treatment is performed to improve the crystallinity of the dielectric layer 6, and is performed at a temperature of, for example, 850 ° C. for 30 minutes.
- the heat treatment is preferably performed in an oxygen-containing atmosphere.
- an insulating layer 8 including an inorganic insulating layer 9 and an organic insulating layer 10 is formed so as to cover the entire capacitor unit 4. That is, for example, the inorganic insulating layer 9 made of SiN x or the like having a thickness of 500 nm is formed by sputtering. Next, a photosensitive polyimide is applied so as to cover the upper surface of the inorganic insulating layer 9, and then heated at a temperature of 125 ° C. for 5 minutes, exposed and developed, and then heated at 350 ° C. for about 1 hour. For example, the organic insulating layer 10 having a predetermined pattern with a film thickness of 5000 nm is formed.
- the organic insulating layer 10 made of photosensitive polyimide is used as a mask, the inorganic insulating layer 9 is processed by reactive ion etching to form holes 19 and 20, and the first Then, a part of the second electrode layers 5 and 7 is exposed on the surface.
- a part of the diffusion preventing layer 2 is dissolved and removed with buffered hydrofluoric acid to expose a part of the conductive substrate 1 on the surface.
- Au having a film thickness of, for example, 300 nm is deposited on the surface exposed portion of the conductive substrate 1 by a vacuum deposition method, and the photoresist is removed by a lift-off method, and as shown in FIG. Form.
- the substrate wiring 11 is formed from the inner surface of the hole 20 to the upper surface and side surfaces of the organic insulating layer 10 and further to the first connection electrode 14, and from the inner surface of the hole 19.
- An electrode wiring 12 is formed over the upper surface of the organic insulating layer 10. Thereafter, an upper external electrode 15 is formed on the electrode wiring 12.
- the substrate wiring 11, the electrode wiring 12, and the upper external electrode 15 are specifically produced as follows.
- a Ti layer having a thickness of 100 nm is formed on the surface by sputtering, and a Cu layer having a thickness of 500 nm is formed on the Ti layer.
- a photoresist is applied on the Cu layer so as to have an opening on the Cu layer to form a predetermined resist pattern, and then electrolytic plating is performed to form a Ni layer having a thickness of 2000 nm in the opening.
- an Au layer having a thickness of 1000 nm is sequentially formed.
- the photoresist is removed to form an upper external electrode 15 having a two-layer structure composed of an Au layer and a Ni layer.
- a predetermined resist pattern is formed by applying a photoresist on the Cu layer so that the portion to be the electrode wiring 12 and the portion to be the substrate wiring 11 are separated from each other, and then wet etching is performed. Etch Cu layer and Ti layer. Thereafter, the photoresist is removed, and an electrode wiring 12 and a substrate wiring 11 having a two-layer structure composed of a Cu layer and a Ti layer are formed.
- the portion excluding the upper external electrode 15 on the conductive substrate 1 is covered with a protective resin layer 18.
- a photosensitive resin such as photosensitive polyimide is applied to the upper surface, and then heated at 125 ° C. for 5 minutes, exposed and developed, and then heated at 350 ° C. for about 1 hour.
- a protective resin layer 18 having a predetermined pattern of 5000 nm is formed.
- the second connection electrode 16 is formed on the other main surface of the conductive substrate 1, and the lower external electrode 17 is formed on the second connection electrode 16.
- the back surface of the conductive substrate 1 is ground to a predetermined thickness, treated with buffered hydrofluoric acid, and a second connection electrode 16 made of Au having a thickness of 300 nm is formed by vacuum deposition.
- electrolytic plating is performed to sequentially form a 2000 nm thick Ni layer and a 1000 nm thick Au layer, thereby forming a lower external electrode 17 having a two-layer structure.
- heat treatment is performed at a temperature of 350 ° C. to stabilize the interface between the lower external electrode 17 and the conductive substrate 1, thereby obtaining a dielectric thin film capacitor.
- the substrate wiring 11 is formed after the capacitor portion 4 is heat-treated, the substrate wiring 11 is not exposed to the heat treatment atmosphere and oxidized. Therefore, even if heat treatment is performed, the increase in ESR can be suppressed without impairing the reliability of the capacitor unit 4.
- the substrate wiring 11 can be made sufficiently thick, A low resistance conductive material such as Au or Cu can be used for the wiring 11, and the resistance between the second electrode layer 7 and the second external electrode 17 can be sufficiently reduced. It is. That is, it is possible to obtain a high-capacity, high-reliability, low-ESR dielectric thin film capacitor with a high degree of freedom in selecting the material and shape of the wiring and adjusting the length.
- the capacitor portion 4 is covered with the insulating layer 8 before the substrate wiring 11 is formed, deterioration of the capacitor characteristics due to etching during wiring formation can be prevented.
- FIG. 5 is a cross-sectional view of a dielectric thin film capacitor showing a second embodiment of the present invention.
- the second embodiment has two capacitors on one main surface side of the conductive substrate 1.
- the portions 21a and 21b are formed, and the capacitor portions 21a and 21b are alternately laminated with electrode layers and dielectric layers, and have a plurality of capacitance generating portions.
- two adhesion layers 23 a and 23 b are formed on the diffusion prevention layer 2 formed on the conductive substrate 1 with the inorganic insulating layer 22 interposed therebetween.
- the first electrode layers 24a, 24b, the first dielectric layers 25a, 25b, the second electrode layers 26a, 26b, the second dielectric layers 27a, 27b, Third electrode layers 28a and 28b, third dielectric layers 29a and 29b, and fourth electrode layers 30a and 30b are sequentially stacked to form capacitor portions 21a and 21b.
- the fourth dielectric layers 31a and 31b are formed on the surfaces of the uppermost fourth electrode layers 30a and 30b of the capacitor portions 21a and 21b.
- the inorganic insulating layer 22 is covered with an organic insulating layer 32.
- the substrate wirings 33a and 33b and the electrode wirings 35a and 35b are formed so as to have substantially the same shape as in the first embodiment, and the substrate wirings 33a and 33b are in ohmic contact with the conductive substrate 1.
- One connection electrode 34a, 34b is electrically connected.
- the first electrode layers 24 a and 24 b are electrically connected to the lower external electrode 17 through the substrate wirings 33 a and 33 b, the first connection electrodes 34 a and 34 b, the conductive substrate 1, and the second connection electrode 16.
- the fourth electrode layers 30a and 30b are electrically connected to the upper external electrodes 36a and 36b via the electrode wirings 35a and 35b.
- the entire capacitor substrate 21a, 21b side of the conductive substrate 1 is covered with a protective resin layer 37 except for the upper external electrodes 36a, 36b.
- the heat treatment of the capacitor portions 21a and 21b is performed before the substrate wirings 33a and 33b are formed, thereby increasing the ESR without impairing the reliability of the capacitor portions. Suppressed.
- the capacitor portions 21a and 21b have a plurality of capacitance generating portions, a thin film capacitor with improved withstand voltage can be obtained. Further, since the fourth dielectric layers 31a and 31b are formed on the capacitor portions 21a and 21b, it is possible to prevent deterioration of the capacitor during the formation of the inorganic insulating layer 22, and to suppress the leakage current. It becomes possible.
- FIG. 6 is a cross-sectional view of a dielectric thin film capacitor showing a third embodiment of the present invention.
- the dielectric thin film capacitor is formed on the diffusion prevention layer 2 formed on the conductive substrate 1.
- An adhesion layer 23, a first electrode layer 24, and a first dielectric layer 25 are sequentially formed, and electrode layers and dielectric layers are alternately stacked on the first dielectric layer 25 to form a capacitor portion. Forming.
- the second electrode layers 26a and 26b, the second dielectric layers 27a and 27b, the third electrode layers 28a and 28b, and the third electrode layer are interposed via the inorganic insulating layer 22.
- the dielectric layers 29a, 29b and the fourth electrode layers 30a, 30b are sequentially stacked.
- the first to fourth dielectric layers 25, 27a, 27b, 29a, 29b and the first electrode layers 24, 26a, 26b, 28a, 28b, 30a, 30b form a capacitor portion.
- heat treatment of the capacitor portion is performed before the formation of the substrate wirings 33a and 33b, thereby suppressing an increase in ESR without impairing the reliability of the capacitor portion. Yes.
- the third embodiment also includes a capacitor section having a plurality of capacitance generating sections, as in the second embodiment, a thin film capacitor with improved withstand voltage can be formed.
- the fourth dielectric layers 31a and 31b are formed on the capacitor portion, it is possible to prevent the capacitor from being deteriorated when the inorganic insulating layer 22 is formed, and to suppress the leakage current.
- the first and second embodiments except that the number of laminated dielectric layers and electrode layers and the formation pattern of the dielectric layers, electrode layers, electrode wirings, and substrate wirings are adjusted as appropriate. It can be manufactured in the same manner as in the embodiment.
- FIG. 7 is a cross-sectional view of a dielectric thin film capacitor showing a fourth embodiment of the present invention.
- a thin film resistor 42 is formed flat on the organic insulating layer 10.
- the second electrode layer 7 is electrically connected to the thin film resistor 42 via the electrode wiring 12.
- the electrode wiring 12 also serves as an upper external electrode, and the thin film resistor 42 is electrically connected to another upper external electrode 41.
- a diffusion prevention layer 2 made of SiO 2 or the like is formed on one main surface of the conductive substrate 1, and the diffusion prevention layer is formed.
- An adhesion layer 3 is formed on the surface 2, and a capacitor portion 4 including a first electrode layer 5, a dielectric layer 6, and a second electrode layer 7 is formed on the surface of the adhesion layer 3. .
- the capacitor portion 4 is covered with an insulating layer 8 composed of an inorganic insulating layer 9 and an organic insulating layer 10 as in the first embodiment.
- the substrate wiring 11 and the electrode wiring 12 are also formed in substantially the same shape as in the first embodiment, and the first electrode layer 5 is connected to the substrate wiring 11 and the second electrode layer 7 is an electrode. It is connected to the wiring 12.
- the electrode wiring 12 also serves as the upper external electrode as described above.
- an upper external electrode 41 is formed on the surface of the organic insulating layer 10, and the upper external electrode 41 and the electrode wiring 12 are electrically connected via a thin film resistor 42.
- the conductive substrate 1 is entirely covered with a protective resin layer 43 except for the electrode wiring 12 and the upper external electrode 41.
- the diffusion prevention layer 2, the adhesion layer 3, the first electrode layer 5, the dielectric layer 6, and the second electrode layer 6 are sequentially formed on the conductive substrate 1,
- the capacitor portion 4 is formed by etching into a predetermined pattern using a known photolithography technique and an argon ion milling method. And in order to improve the dielectric characteristic of the dielectric material layer 6, the capacitor
- an insulating layer 8 composed of an inorganic insulating layer 9 and an organic insulating layer 10 is formed so as to cover the capacitor portion 4, and the inorganic insulating layer 9 is processed by a reactive ion etching method.
- the holes 19 and 20 are formed and a part of 1st and 2nd electrode layers 5 and 7 are surface-exposed.
- a thin film layer made of TaN or Ni—Cr alloy having a film thickness of 40 to 60 nm is formed by sputtering.
- a predetermined region is etched away by reactive ion etching to form a thin film resistor 42, and then the photoresist is dissolved and removed.
- a part of the diffusion preventing layer 2 is dissolved and removed with buffered hydrofluoric acid, and a part of the conductive substrate 1 is exposed on the surface.
- a 100 nm thick Ti layer and a 500 nm thick Au layer are formed by sputtering, then a photoresist is applied to form a resist pattern, and the Au layer and Ti layer are processed by wet etching. The photoresist is removed, thereby forming the substrate wiring 11, the electrode wiring 12, and the upper external electrode 41 as shown in FIG. 9D. Thereafter, heat treatment is performed in air at 370 ° C. for 30 minutes to oxidize the thin film resistor 42 and perform stabilization treatment.
- the protective resin layer 43 is covered so as to cover the whole except for the upper external electrode 41 and the electrode wiring 12 by the same method and procedure as in the first embodiment.
- the second connection electrode 16 is formed on the other main surface of the conductive substrate 1 by the same method and procedure as in the first embodiment, and the second A lower external electrode 17 is formed on the connection electrode 16.
- a thin film resistor 42 is added, so that a thin film having a high capacity, high reliability, and low ESR combined with a resistance function.
- a capacitor can be realized.
- the thin film resistor is formed on the capacitor portion 4, it is possible to avoid the increase in the size of the element as much as possible.
- the thin film resistor 42 is formed in a flat shape, it is possible to suppress variation in the resistance value.
- FIG. 10 is a cross-sectional view of a dielectric thin film capacitor showing a fifth embodiment.
- the thin film resistor 46 is formed on the diffusion preventing layer 2, and the electrode wiring 47 and the upper external electrode 45 are electrically connected to the thin film resistor 46 on the surface of the diffusion preventing layer 2. It is connected.
- the thin film resistor 46 is formed on the diffusion prevention layer 2 as in the fifth embodiment, the thin film resistor 46 is added in addition to the function and effect of the first embodiment. It is possible to realize a high-capacity, high-reliability, low-ESR thin-film capacitor that combines functions.
- the thin film resistor 46 is formed in a flat shape, it is possible to suppress variation in resistance value.
- FIG. 11 is a cross-sectional view of a dielectric thin film capacitor showing a sixth embodiment.
- the capacitor section has a structure substantially similar to that of the third embodiment.
- the adhesion layer 48, the first electrode layer 49, and the first dielectric layer 50 are sequentially formed on the diffusion prevention layer 2 formed on the conductive substrate 1, and the first dielectric layer 50 is formed on the first dielectric layer 50. Electrode layers and dielectric layers are alternately stacked to form a capacitor portion.
- the dielectric layers 55a and 55b, the fourth electrode layers 56a and 56b, the fourth dielectric layers 57a and 57b, and the fifth electrode layers 58a and 58b are sequentially stacked, and the first to fourth dielectric layers are sequentially stacked.
- the body layers 50, 53a, 53b, 55a, 55b, 57a, 57b and the first to fifth electrode layers 49, 52a, 52b, 54a, 54b, 56a, 56b, 58a, 58b form a capacitor portion.
- fifth dielectric layers 59 a and 59 b are formed on the fifth electrode layers 58 a and 58 b, and the upper surface of the inorganic insulating layer 51 is covered with the organic insulating layer 60.
- the substrate wiring 61 and the electrode wirings 62 and 63 have substantially the same shape as that of the fourth embodiment, and the first electrode layer 49 is connected to the first connection electrode 14 via the substrate wiring 11.
- the fifth electrode layers 58a and 58b are electrically connected to electrode wirings 63 and 62 that also serve as upper external electrodes, respectively.
- a thin film resistor 64 is formed on the organic insulating layer 60, and the electrode wiring 63 and the upper external electrode 65 are electrically connected to the thin film resistance 64, whereby the fifth electrode layer 58 is connected to the electrode wiring 63 and the thin film.
- the upper external electrode 65 is electrically connected through the resistor 64.
- the thin film resistor 64 in addition to the function and effect of the first embodiment, by adding the thin film resistor 64, the high-capacity, high reliability, and low ESR combined with the resistance function are achieved.
- a thin film capacitor can be realized.
- the thin film resistor 64 is formed on the capacitor portion, it is possible to avoid the increase in size of the element as much as possible.
- the thin film resistor 64 is formed in a flat shape, it is possible to suppress the variation in the resistance value.
- the present invention is not limited to the above embodiment. Although the present invention can be modified in various ways as described above, the film formation method, film formation conditions, film thickness, etc. described in the above embodiments are exemplifications. It is not limited. Needless to say, when a plurality of parts are manufactured together, they may be divided individually by dicing or the like.
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Abstract
Description
4、21a、21b キャパシタ部
5、7 電極層
6 誘電体層
8 絶縁層
11、33、61 基板配線
12、47、62、63 電極配線、
15、41、45 上部外部電極(第1の外部電極)
17 下部外部電極(第2の外部電極)
24、26、28、30 電極層
25、27、29 誘電体層
42、46、64 薄膜抵抗
49、52、54、56、58 電極層
50、53、55、57、59 誘電体層 DESCRIPTION OF
15, 41, 45 Upper external electrode (first external electrode)
17 Lower external electrode (second external electrode)
24, 26, 28, 30
Claims (9)
- 導電性基板の一方の主面側に少なくとも一つの第1の外部電極を形成し、前記導電性基板の他方の主面側に第2の外部電極を形成した誘電体薄膜キャパシタの製造方法であって、
誘電体層の上下両面に電極層が形成された少なくとも一つ以上の容量発生部を有するキャパシタ部を前記導電性基板の前記一方の主面上に形成するキャパシタ部形成工程と、
前記電極層のうちの一方の極となるべき電極層と前記導電性基板とを電気的に接続する基板配線を形成する配線形成工程とを有し、
前記キャパシタ形成工程と前記配線形成工程との間に前記キャパシタ部を熱処理する熱処理工程を含んでいることを特徴とする誘電体薄膜キャパシタの製造方法。 A method of manufacturing a dielectric thin film capacitor in which at least one first external electrode is formed on one main surface side of a conductive substrate and a second external electrode is formed on the other main surface side of the conductive substrate. And
Forming a capacitor portion having at least one capacitance generating portion having electrode layers formed on both upper and lower surfaces of the dielectric layer on the one main surface of the conductive substrate; and
A wiring forming step of forming a substrate wiring that electrically connects the electrode layer to be one of the electrode layers and the conductive substrate;
A method of manufacturing a dielectric thin film capacitor, comprising a heat treatment step of heat treating the capacitor portion between the capacitor formation step and the wiring formation step. - 前記熱処理工程と前記配線形成工程との間に前記キャパシタ部を絶縁層で被覆する絶縁層形成工程を有し、前記基板配線の少なくとも一部を前記絶縁層上に形成することを特徴とする請求項1記載の誘電体薄膜キャパシタの製造方法。 An insulating layer forming step of covering the capacitor portion with an insulating layer between the heat treatment step and the wiring forming step, wherein at least a part of the substrate wiring is formed on the insulating layer. Item 2. A method for producing a dielectric thin film capacitor according to Item 1.
- 前記キャパシタ部と電気的に接続された薄膜抵抗を形成する薄膜抵抗形成工程を前記熱処理工程と前記配線形成工程との間に有していることを特徴とする請求項1記載又は請求項2記載の誘電体薄膜キャパシタの製造方法。 The thin film resistor forming step for forming a thin film resistor electrically connected to the capacitor portion is provided between the heat treatment step and the wiring forming step. Of manufacturing a dielectric thin film capacitor.
- 前記薄膜抵抗形成工程は、前記薄膜抵抗を平坦状に形成することを特徴とする請求項3記載の誘電体薄膜キャパシタの製造方法。 4. The method of manufacturing a dielectric thin film capacitor according to claim 3, wherein the thin film resistor forming step forms the thin film resistor in a flat shape.
- 導電性基板の一方の主面側に少なくとも一つの第1の外部電極が形成されると共に、前記導電性基板の他方の主面側に第2の外部電極が形成された誘電体薄膜キャパシタであって、
誘電体層の上下両面に電極層を有する少なくとも一つ以上の容量発生部を備えたキャパシタ部が、前記導電性基板の前記一方の主面上に形成されると共に、
前記電極層のうちの一方の極となるべき電極層が、基板配線及び前記導電性基板を介して前記第2の外部電極と電気的に接続され、かつ、他方の極となるべき電極層が、前記第1の外部電極と電気的に接続され、
前記キャパシタ部が熱処理されてなると共に、少なくとも前記基板配線は、前記熱処理後に形成されることを特徴とする誘電体薄膜キャパシタ。 A dielectric thin film capacitor in which at least one first external electrode is formed on one main surface side of a conductive substrate and a second external electrode is formed on the other main surface side of the conductive substrate. And
A capacitor unit including at least one capacitance generating unit having electrode layers on both upper and lower surfaces of the dielectric layer is formed on the one main surface of the conductive substrate;
An electrode layer to be one of the electrode layers is electrically connected to the second external electrode through a substrate wiring and the conductive substrate, and an electrode layer to be the other electrode , Electrically connected to the first external electrode,
The dielectric thin film capacitor, wherein the capacitor portion is heat-treated, and at least the substrate wiring is formed after the heat treatment. - 前記キャパシタ部が絶縁層で被覆されると共に、前記基板配線の少なくも一部が前記絶縁層上に形成されていることを特徴とする請求項5記載の誘電体薄膜キャパシタ。 6. The dielectric thin film capacitor according to claim 5, wherein the capacitor portion is covered with an insulating layer, and at least a part of the substrate wiring is formed on the insulating layer.
- 薄膜抵抗が、前記他方の極となるべき電極層と電気的に接続されるように形成されていることを特徴とする請求項5又は請求項6記載の誘電体薄膜キャパシタ。 7. The dielectric thin film capacitor according to claim 5, wherein a thin film resistor is formed so as to be electrically connected to the electrode layer to be the other electrode.
- 前記薄膜抵抗は、キャパシタ部上に形成されていることを特徴とする請求項7記載の誘電体薄膜キャパシタ。 8. The dielectric thin film capacitor according to claim 7, wherein the thin film resistor is formed on a capacitor portion.
- 前記薄膜抵抗は、平坦状に形成されていることを特徴とする請求項7又は請求項8記載の誘電体薄膜キャパシタ。 9. The dielectric thin film capacitor according to claim 7, wherein the thin film resistor is formed in a flat shape.
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2016021529A1 (en) * | 2014-08-06 | 2016-02-11 | 株式会社村田製作所 | Composite electronic component |
WO2017057422A1 (en) * | 2015-10-02 | 2017-04-06 | 株式会社村田製作所 | Thin film lc component and mounting structure of same |
KR20180016228A (en) * | 2016-08-05 | 2018-02-14 | 삼성전기주식회사 | Thin-film ceramic capacitor |
JP2019106485A (en) * | 2017-12-13 | 2019-06-27 | 富士電機株式会社 | Resistive element and method for manufacturing the same |
US10468187B2 (en) | 2016-08-05 | 2019-11-05 | Samsung Electro-Mechanics Co., Ltd. | Thin-film ceramic capacitor having capacitance forming portions separated by separation slit |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
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CN103219318B (en) * | 2013-04-12 | 2015-07-08 | 中国电子科技集团公司第十三研究所 | High-temperature-resistant MIM capacitor for microwave internal matching transistor and manufacturing method thereof |
CN109923630B (en) * | 2016-11-02 | 2023-04-28 | 株式会社村田制作所 | Capacitor with a capacitor body |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH1022464A (en) * | 1996-07-03 | 1998-01-23 | Matsushita Electron Corp | Semiconductor device and manufacture thereof |
JPH1041485A (en) * | 1996-07-26 | 1998-02-13 | Hitachi Ltd | Semiconductor device and production of the same |
JPH10321803A (en) * | 1997-05-23 | 1998-12-04 | Mitsubishi Materials Corp | Thin film capacitor |
-
2009
- 2009-05-13 WO PCT/JP2009/002090 patent/WO2010016171A1/en active Application Filing
- 2009-05-13 JP JP2010523721A patent/JP5348565B2/en not_active Expired - Fee Related
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Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH1022464A (en) * | 1996-07-03 | 1998-01-23 | Matsushita Electron Corp | Semiconductor device and manufacture thereof |
JPH1041485A (en) * | 1996-07-26 | 1998-02-13 | Hitachi Ltd | Semiconductor device and production of the same |
JPH10321803A (en) * | 1997-05-23 | 1998-12-04 | Mitsubishi Materials Corp | Thin film capacitor |
Cited By (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5924461B1 (en) * | 2014-08-06 | 2016-05-25 | 株式会社村田製作所 | Composite electronic components |
WO2016021529A1 (en) * | 2014-08-06 | 2016-02-11 | 株式会社村田製作所 | Composite electronic component |
US10290425B2 (en) | 2014-08-06 | 2019-05-14 | Murata Manufacturing Co., Ltd. | Composite electronic component |
JP2020145475A (en) * | 2015-10-02 | 2020-09-10 | 株式会社村田製作所 | Thin film lc component and mounting structure of the same |
WO2017057422A1 (en) * | 2015-10-02 | 2017-04-06 | 株式会社村田製作所 | Thin film lc component and mounting structure of same |
JPWO2017057422A1 (en) * | 2015-10-02 | 2018-04-19 | 株式会社村田製作所 | Thin film type LC component and its mounting structure |
JP7052824B2 (en) | 2015-10-02 | 2022-04-12 | 株式会社村田製作所 | Thin-film LC component and its mounting structure |
KR20180016228A (en) * | 2016-08-05 | 2018-02-14 | 삼성전기주식회사 | Thin-film ceramic capacitor |
US10468187B2 (en) | 2016-08-05 | 2019-11-05 | Samsung Electro-Mechanics Co., Ltd. | Thin-film ceramic capacitor having capacitance forming portions separated by separation slit |
US10720280B2 (en) | 2016-08-05 | 2020-07-21 | Samsung Electro-Mechanics Co., Ltd. | Thin-film ceramic capacitor having capacitance forming portions separated by separation slit |
KR101912282B1 (en) * | 2016-08-05 | 2018-10-29 | 삼성전기 주식회사 | Thin-film ceramic capacitor |
JP2019106485A (en) * | 2017-12-13 | 2019-06-27 | 富士電機株式会社 | Resistive element and method for manufacturing the same |
JP7039982B2 (en) | 2017-12-13 | 2022-03-23 | 富士電機株式会社 | Resistor element and its manufacturing method |
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