WO2010005470A2

WO2010005470A2 - Bit interleaved ldpc coded modulation and physical layer signaling

Info

Publication number: WO2010005470A2
Application number: PCT/US2009/003578
Authority: WO
Inventors: Jing LEI; Wen Gao; Paul Gothard Knutson; Hou-Shin Chen
Original assignee: Thomson Licensing
Priority date: 2008-06-16
Filing date: 2009-06-16
Publication date: 2010-01-14
Also published as: WO2010005470A3

Abstract

A proposal for a DVB-C2 baseline system, mainly focused on the channel coding and bit interleaving modules for spectrally efficient modulation is described. Due to the implementation simplicity of the low density parity check (LDPC) codes standardized in the DVB-S2 specification, it is proposed to extend their application to cable channels and choose the subset with long block length ( L = 64800 ) and medium to high rates ( 2/5 ≤ R ≤ 9/10 ) as the forward error correction (FEC) codes of DVB-C2 systems. Due to the non-uniform bitwise error protection inherent to high-order modulations (e.g. 256-QAM, 1024-QAM) and irregular LDPC codes (e.g. DVB-S2 codes), there exists a mismatch between the modulation and the channel coding in general if the two modules are developed independently but concatenated directly. To match the error resilience of a finite-length channel code and a given constellation, the principles described herein design a bit interleaver and insert it between the channel encoder and the modulator. As a result, a better tradeoff between bandwidth-efficiency and power-efficiency can be achieved with a minor increase of hardware complexity.

Description

BIT INTERLEAVED LDPC CODED MODULATION AND PHYSICAL

LAYER SIGNALING

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of U.S. Provisional Application Serial No. 61/132,176, filed June 16, 2008 and U.S. Provisional Application Serial No. 61/077895, filed July 3, 2008, which is incorporated by reference herein in its entirety.

TECHNICAL FIELD

The present principles relate generally to cable modulation and, more particularly, to a method and apparatus for channel coding and bit interleaving modules for spectrally efficient modulation.

BACKGROUND

Unlike satellite and terrestrial transmissions, cable channels do not exhibit significant time and frequency selectivity. Consequently, spectrally-efficient modulations, such as 256-QAM and 1024-QAM, have been adopted or are to be deployed in cable networks to meet the ever-increasing capacity demand of bandwidth-consuming services such as HDTV and VoD, and to boost the penetration of digital video broadcasting services. Recently, LDPC codes have been introduced in DVB-S2 and DVB-T2 standards because of their design flexibility, decoding simplicity and the universally excellent error correction performance over various channel types.

Out of the considerations for implementation simplicity and component interoperability, it is proposed to extend the application of LDPC codes standardized in the DVB-S2 specification to cable channels. In particular, it has been observed through simulations that among the DVB-S2 codes family, the subset with long block length 64800 and rates higher than 1/3 exhibit good tradeoff between power and spectral efficiency. Therefore, this description describes this subset as the forward error correction (FEC) codes for the DVB-C2 system. SUMMARY

This specification describes a proposal for a DVB-C2 baseline system, mainly focused on the channel coding and bit interleaving modules for spectrally efficient modulation. Due to the outstanding implementation simplicity of the low density parity check (LDPC) codes standardized in the DVB-S2 specification, it is proposed to extend their application to cable channels and choose the subset with long block length (L = 64800 ) and medium to high rates (2/5 ≤ R ≤ 9/10) as the forward error correction (FEC) codes of DVB-C2 systems.

Nevertheless, due to the non-uniform bitwise error protection inherent to high-order modulations (e.g. 256-QAM, 1024-QAM) and irregular LDPC codes (e.g. DVB-S2 codes), there exists a mismatch between the modulation and the channel coding in general if the two modules are developed independently but concatenated directly. To match the error resilience of a finite-length channel code and a given constellation, the principles described herein design a bit interleaver and plug it between the channel encoder and the modulator. As a result, a better tradeoff between bandwidth-efficiency and power-efficiency can be achieved with a minor increase of hardware complexity.

The main advantages of this proposal include the following:

1. Preserves the linear encoding and decoding complexities of DVB-S2 LDPC codes;

2. Simplifies the realization of bit interleaving by taking advantage of the structural regularity of DVB-S2 LDPC codes

3. Improves the system performance significantly by employing the proposed bit interleavers.

Using the consecutive bits group mapping (in natural order of coded bits without interleaving) as the benchmark, results have found that the proposed bit interleaver can significantly reduce (from 20% to 46%) the gap to the capacity of bit-interleaved coded modulation (BICM).

This specification will describe the interleavers in details with only a brief description of the design methodology. It is worth noting that the methodology of interleaver design is generic and can be extended from single-carrier modulation to multicarrier transmission (e.g. OFDM) and from uniform constellation to non-uniform constellation (geometrical shaping or probabilistic shaping). In addition, the principles described herein will propose a frame structure that carries physical layer signaling.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 is a generic block diagram of the proposed DVB-C2 transmitter.

Figure 2 is a generic block diagram of the proposed DVB-C2 receiver.

Figure 3 is bit level capacity for uniform spaced square 1024-QAM.

Figure 4 is an illustration of the mapping rule for the proposed BICM scheme.

Figure 5a is the physical layer frame. Figure 5b is a QPSK constellation. Figure 5 shows error performance for 1024-QAM coded by rate 1/2 LDPC code.

Figure 6 is error performance for 1024-QAM coded by rate 3/5 LDPC code.

Figure 7 is error performance for 1024-QAM coded by rate 2/3 LDPC code.

Figure 8 is error performance for 1024-QAM coded by rate 3/4 LDPC code.

Figure 9 is error performance for 1024_:QAM coded by.rate 4/5 LDPC code.

Figure 10 is error performance for 1024-QAM coded by rate 5/6 LDPC code.

Figure 11 is error performance for 1024-QAM coded by rate 8/9 LDPC code.

Figure 12 is error performance for 1024-QAM coded by rate 9/10 LDPC code.

Figure 13 is error performance for 256-QAM coded by rate 2/5 LDPC code.

Figure 14 is error performance for 256-QAM coded by rate 1/2 LDPC code.

Figure 15 is error performance for 256-QAM coded by rate 3/5 LDPC code.

Figure 16 is error performance for 256-QAM coded by rate 2/3 LDPC code.

Figure 17 is error performance for 256-QAM coded by rate 3/4 LDPC code.

Figure 18 is error performance for 256-QAM coded by rate 4/5 LDPC code.

Figure 19 is error performance for 256-QAM coded by rate 5/6 LDPC code.

Figure 20 is error performance for 256-QAM coded by rate 8/9 LDPC code.

Figure 21 is error performance for 256-QAM coded by rate 9/10 LDPC code.

Table 0 is Labeling for 1024-QAM

Table 1 is Variable Node and Check node Degree Distribution of LDPC Codes Proposed for

FEC Module of DVB-C2

Tables 2 through 19 are Configurations of the Bit Interleaver for various LDPC Code Rates DETAILED DESCRIPTION

Out of the considerations for implementation simplicity and component interoperability, it is proposed to extend the application of LDPC codes standardized in the DVB-S2 specification to cable channels. In particular, it has been observed through simulations that among the DVB-S2 codes family, the subset with long block length 64800 and rates higher than 1/3 exhibit good tradeoff between power and spectral efficiency. Therefore, this proposal will choose this subset as the forward error correction (FEC) codes for the DVB-C2 system.

Nevertheless, it is well known that a powerful binary LDPC code designed for BPSK will not necessarily work well when concatenated directly with higher order modulations, which is due to the non-uniform bitwise error resilience inherent to high order modulation. To make up for this mismatch, a bit interleaver is inserted between the channel encoder and the modulator. Note that the experiments with random interleaver and a simple block interleaver demonstrate that they can not effectively improve the performance of bit- interleaved LDPC -coded modulation over AWGN channel. Employing density evolution as a tool, the present principles have been used to design a set of interleavers to optimize the decoding threshold.

In the interleavers, LDPC coded bits are allocated selectively to different bit levels. Specifically, for QAM modulation of order 2^2Q , we group the length-Z, LDPC code into Q mutually-exclusive subsets. We call each subset a "sub-code" of length LIQ. At the transmitter side, the proposed interleaver is inserted between the channel encoder and the modulator to make sure that different subsets of coded bits are transferred to the appropriate bit levels of the constellation. Scope of Proposed System

Fig. 1 and Fig. 2 illustrate the generic block diagrams of proposed DVB-C2 transmitter and the corresponding receiver, respectively. The major contribution is outlined by the highlighted blocks in the transmitter, which comprise the advanced bit-interleaved LDPC- coded QAM-modulation and physical layer signaling, summarized as the following:

• LDPC Channel Encoder o subset of DVB-S2 codes family o code rate R is chosen from the set {2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9, 9/10} o long block length L=64800

• Bit Interleaver o tailored for a given constellation and a given code o block-wise processing with unit block size of 360

• QAM Modulator o uniformly spaced square-QAM with order 2^2ρ , ( Q ≥ 4) o binary reflected gray code labeling

• Physical Layer signaling o Signal the LDPC code rate and the order of the modulation

These functions will be described in detail in the following sections.

1. Bit Interleaved LDPC Coded Modulation for DVB-C2

1.1 Channel Coding

The LDPC encoding process is described in Section 5.3.2-5.3.2.1 of the DVB-S2 document - ETSI EN 302307 (Vl.1.1, June 2004) (Digital Video Broadcasting (DVB): Second Generation framing structure, channel coding and modulation systems for Broadcasting, Interactive Services, News Gathering and other broadband satellite applications).

Table 1 shows the variable node (VND) and check node (CND) degree distribution of the DVB-S2 LDPC codes subset proposed for FEC of DVB-C2. Each VND corresponds to one bit in the coded sequence of length 64800. Each CND is associated with one distinct parity check constraint specified by a row of the parity check matrix. The degree of a node is defined as the number of edges which are adjacent to it. Take the rate 2/5 code for example (the second row of Table 1). Its VNDs can be classified into fthe categories according to its degree, namely: 12, 3, 2 and 1; and the number of VNDs belonging to each category is given by 8640, 17280, 38879 and 1, respectively. Its CND degree has two types, namely: 5 and 6. It is interesting to note that due to the quasi-cyclic structure of the parity check matrix, the CND degree distribution is almost regular except for the last node. In other words, the last CND differs from the others by having one less degree and that exception happens only once among the 38880 CNDs. The codes of other rates exhibit the same regularities with respect to VND and CND degree distribution.

1.2 QAM Modulation

High order QAM modulations, i.e., 256-QAM, 1024-QAM and 4096-QAM, are proposed in the system to take advantage of the good channel conditions in cable systems. In this proposal, we consider uniform square QAM constellation with binary reflected Gray code (BRGC) labeling since the BRGC has been proved to yield the lowest possible average BER. To illustrate, we will depict the BRGC labeling up to order 1024-QAM constellation.

For 1024-QAM constellation, its binary labeling can be separated into two independent groups: the in-phase set (horizontal) and the quadrature set (vertical). Moreover, each direction can be viewed as a uniformly spaced 32-ASK. Without loss of generality, we consider the labeling in the vertical direction only, and the labeling for the other direction can be ordered in the same way. Assuming the vertical coordinates of the 32-ASK sub- constellation is arranged in descending order as: A_x > A₂ > ••• > A₂₂. Actually, the BRGC labeling for ASK of order 2^Q can be obtained recursively. To illustrate, the following graph shows the recursive construction of BRGC for 32-ASK, starting from the BRGC for 4-ASK. Finally, the labeling for 1024-QAM is given by the cross product of two 32-ASK BRGC labeling.

Using gray labeled 1024-QAM as the prototype, there are five distinctive bit levels that are characterized by different capacities. The most significant bit (MSB) has the highest capacity, whereas the least significant bit (LSB) has the lowest capacity. Fig. 3 shows the bit level capacity as a function of SNR. The significant difference in the bit level capacities implies the non-uniform error resilience for the corresponding 1024-QAM constellation, which motivates us to match the degree irregularity of LDPC codes to the bit level capacity difference tactfully such that the decoding threshold SNR of this coded modulation system can be minimized. 1.3 Bit Interleaving

Tables 2-10 show the configurations of the bit interleavers for LDPC-coded 1024-QAM. By selectively mapping VNDs of various categories to different bit levels, the optimization of the interleavers has taken into account the minimization of the decoding threshold SNR as well as the reduction of the error floor (incurred by suboptimal iterative decoding). The coded bits are classified according to the number of degrees. Since the VND category of degree- 1 includes one coded bit only, we simply combine it with the VND category with degree-2 for the simplicity of subsequent processing. From the tanner graph of the proposed LDPC codes, it can be seen that the distribution of the VND degrees exhibits strong regularity.

Similarly, Tables 11-19 give the configurations of the bit interleavers for 256-QAM (Note: the bit interleavers for 4096-QAM will be provided soon).

To be more specific, let us still look at the rate 2/5 code. For the simplicity of statement, we arrange the coded bits of length 64800 in their natural order and denote them by sequence (C₁ ,C₂ ••• C₈₆₄₀ , C₈₆₄₁ -- C₂₅₉₂₀ , C₂₅₉₂₁ ••• C₆₄₈₀₀J, where the subscript i of bit C₁ represents the order of its occurrence in the sequence. Based on the optimization results of bit interleaving, the first 5040 bits of degree-12, i.e. {C, }*"° , are assigned to the MSB of the in- phase and quadrature branches of 1024-QAM modulator. Of the remaining 3600 bits of degree-12, 1440 of them, which are indexed by (C₁ )^j₄₁ , go to the bit level whose capacity is second to the MSB, and the other 2160 bits are assigned to the LSB level whose capacity is the lowest. Similarly, for the degree-3 VNDs indexed by {C, J^₁ , the first 6480 of them, i.e. (C, C are allocated to bit level IV, and the rest of them, i.e. (C, }"™ , , all go to LSB. The allocation of degree-2 VNDs follows the same rule as above.

A graphical description of the bits allocation up to the 1024-QAM constellation is given by Fig. 4. We can view the 5 distinct bit levels as 5 parallel bit pipes, numbered from 1 to 5, in the descending order of bit level capacities. Each pipe has two output branches. Without loss of generality, we name the upper branch as / (in-phase) and the lower branch as Q (quadrature). For the example above, (C₂, }²"⁰ and (C₂,_, }",²⁰ are sequentially assigned to the / and Q branches of pipe # 1 , respectively. For the queued bits {&,' , } and {b_t' _Q } in the two branches, the superscript / denotes the symbol index they are mapped to, while the first subscript denotes the index of the pipe they are in. Then, the subsets {b' , },*,, and {b,¹ _ϋ}*₌, are used to choose the in-phase and quadrature components of 1024-QAM symbol S¹.

2. Physical Layer Signaling

The proposal supports multiple system parameters, i.e., different QAM modulations and different LDPC code rate. In addition, LDPC codes are transmitted in blocks. To allow the receiver to identify the system parameters and the start of the LDPC code block, certain physical layer signaling is required.

We propose to carry an LDPC code block in a physical layer frame (named

(named PLPAYLOAD, shown as following:

PLPAYLOAD contains N symbols that carries an LDPC code block (64800 bits), where N = 64800/(2Q) for Q=4,5,6. PLHEADER contains 40 bits that are defined as following:

1. The first 8 bits are (y_o,yi,...,y₇) = (01 00 01 1 1) (0x47).

2. The next 32 bits is a codeword encoded from 6 bits that convey the system parameters. Here we denote the 6 bits as S=[S5, S4,.., SO] and name it as the system parameter. The encoding process is shown as

3. Form 20 bit pairs (y_2l ,y_2l+i ) and carry them using QPSK modulation with the following constellation:

The 6 bits S is coded as in the following table (Table 20). The first row of the table indicates the LDPC code rate and the first column indicates the modulation type. The entry (i j) is the system parameter value for the modulation type of row i and the code rate of column j. For example, the system parameter S=O indicates that the modulation is 256 QAM and LDPC code rate is 2/5. The system parameter values 27-63 are reserved for future use.

The setup of the computer simulation can be summarized by the following block diagram. The choice of the interleaver depends on the code rate as well as the order of QAM modulation.

Performance

Compared to block interleaving and consecutive group-mapping (no interleaving), the proposed bit interleaving scheme can reduce the decoding thresholds significantly. Figures 5-12 present the power gain of proposed bit interleavers for 1024-QAM modulation, and the interleavers' configurations are given by Tables 3-10. As a benchmark, the Shannon limit of BICM is also shown. It can be observed from these figures that the ad hoc "block interleaving" approach, which was proposed for DVB-T2 to combat the impairments of fading channels, is not an appropriate choice for high order modulation transmitted over cable channels, since its performance is even worse than the case that no interleaving is employed. Compared to the case of no interleaving, the proposed bit interleaver can significantly reduce the gap to the capacity limit of BICM, with the scales of reduction ranging from 20 to 46 in percentage.

For 256-QAM modulation, its error performance under the proposed bit interleaving and FEC schemes is shown in Figures 13-21. The configurations of the corresponding bit interleavers can be found in Tables 11-19.

To quantify the power efficiency gained by the proposed bit interleavers, we define the decoding threshold γ as the minimum Es/N0 that makes the BER of information bit lower than lO^"7 . Table 21 and Table 22 present the decoding thresholds for three different bit interleaving strategies for 1024- and 256-QAM, respectively, where "NO INT" corresponds to the case of consecutive bits group mapping, "Block" denotes the bit interleaver used in DVB-T2, where the coded bits are write column-wisely and read out row-wisely, and "BICM" represents the proposed bit interleaver. It can be observed from these tables that using the decoding threshold of "NO INT' as the benchmark, the proposed bit interleaver can significantly reduce the capacity gap to the ultimate Shannon bound of BICM, and the scale of reduction ranges from 20 to 46 in percentage.

Claims

1. A forward error correction apparatus using a bit interleaver between a channel encoder and a modulator.

2. The apparatus of Claim 1, using low density parity check codes with block lengths of 64800.

3. The apparatus of Claim 2, using code rates of 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9, or 9/10.

4. The apparatus of Claim 2, using modulations of either 256-QAM or 1024-QAM.

5. A method of forward error correction comprising: channel encoding of a digital bitstream, interleaving the bits of the encoded digital bitstream, modulating the bit interleaved encoded digital bitstream.

6. The method of Claim 5, wherein the channel encoder has long block length of 64800.

7. The method of Claim 6, wherein the channel encoder code rate is 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9, or 9/10.

8. The method of Claim 5, wherein bit interleaving step uses block size of 360.

9. The method of Claim 5, wherein the modulation is 256-QAM or 1024-QAM.

10. A method of constructing a frame comprising: creating a payload header that conveys system parameters, and forming bit pairs which are carried by QPSK modulation.

1 1. The method of Claim 10 wherein the system parameters comprise modulation type.

12. The method of Claim 10 wherein the system parameters comprise code rate.

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