WO2009157299A1 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- WO2009157299A1 WO2009157299A1 PCT/JP2009/060459 JP2009060459W WO2009157299A1 WO 2009157299 A1 WO2009157299 A1 WO 2009157299A1 JP 2009060459 W JP2009060459 W JP 2009060459W WO 2009157299 A1 WO2009157299 A1 WO 2009157299A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 219
- 238000000034 method Methods 0.000 title claims abstract description 26
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 24
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41741—Source or drain electrodes for field effect devices for vertical or pseudo-vertical devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
- H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
Definitions
- the present invention relates to a semiconductor device which is an insulated gate semiconductor element and a method for manufacturing the same.
- the insulated gate bipolar transistor is called IGBT (Insulated Gate Bipolar Transistor) and is known as a power semiconductor element that simultaneously realizes high-speed operation of MOSFET (Metal Oxide Semiconductor Semiconductor Field Effect Transistor) and low on-voltage of the bipolar transistor.
- IGBT Insulated Gate Bipolar Transistor
- MOSFET Metal Oxide Semiconductor Semiconductor Field Effect Transistor
- FIG. 6 is a side sectional view of a punch-through IGBT having a conventional trench structure.
- This IGBT includes a semiconductor layer 10 composed of a p + type collector layer 1, an n + type buffer layer 2, an n ⁇ type drift layer 3, a p type base layer 4, and an n + type emitter layer 5.
- a trench 6 formed so as to reach from the main surface 11 of the semiconductor layer 10 to the inside of the drift layer 3, a gate insulating film 7 and a gate electrode 21 formed in the trench 6, an emitter layer 5 and a gate electrode Interlayer insulating film 8 formed on 21, emitter electrode 22 formed on base layer 4, emitter layer 5 and interlayer insulating film 8, and Ti (titanium) formed on main surface 12 of collector layer 1.
- a collector electrode 23a is a collector electrode 23a.
- IGBTs are classified into punch-through types and non-punch-through types depending on their structure. Particularly in the punch-through type, since the buffer layer 2 forcibly suppresses the spread of the depletion layer from the drift layer 3 to the collector layer 1 when a reverse voltage is applied between the emitter and the collector, the resistance is relatively high. A certain drift layer 3 can be formed thin. As a result, the punch-through IGBT has a feature that the on-voltage is low.
- the IGBT has a specific failure mode called a latch-up phenomenon. This is due to the structure of the operation of the parasitic thyristor built in the IGBT, and the hole current flows through the gate of the parasitic thyristor by the holes injected from the collector layer 1 during the normal operation, thereby operating the parasitic thyristor. This is a phenomenon that occurs.
- a method of using the collector layer 1 having a low impurity concentration is known in order to suppress the amount of injected holes. According to this method, it is possible to prevent the latch-up phenomenon by reducing the hole current, but a good contact, that is, an ohmic junction is obtained between the collector layer 1 having a low impurity concentration and the collector electrode 23a. It is difficult to form a Schottky junction. As a result, as shown in FIG. 7, the ON voltage becomes high, and an unstable operation in which the output voltage V CE and the output current I C are not proportional at the time of rising occurs.
- the IGBT is described in, for example, Patent Document 1 below.
- Such a phenomenon depends on the relationship between the electron affinity ⁇ s of the collector layer 1 and the work function ⁇ m of the collector electrode 23a.
- the collector layer 1 is p-type, the lower the impurity concentration of the surface layer, the larger ⁇ s becomes, and the difference ( ⁇ s ⁇ m ) between the electron affinity of the collector layer 1 and the work function of the collector electrode 23a becomes larger.
- a Schottky junction is easily formed between the collector layer 1 and the collector electrode 23a.
- a method is known in which after the collector layer 1 is thinned, a p-type impurity is introduced only into the main surface 12 side of the collector layer 1 to form a local high concentration region. According to this method, since the electron affinity ⁇ s of the collector layer 1 becomes small and ⁇ s ⁇ m becomes small or becomes negative, an ohmic junction is formed, and a low on-voltage can be obtained.
- a step of implanting p-type ions into the main surface 12 side of the collector layer 1 and an annealing step of activating the p-type ions are required.
- Production costs increase with the increase.
- the collector layer 1 is thinned from the main surface 12 side by a polishing process, and an ion implantation process and an annealing process are performed. In the process after stratification, the IGBT is easily damaged, and the manufacturing yield is lowered.
- the present invention has been made to solve the above-described problems, and provides a semiconductor device capable of preventing a latch-up phenomenon and achieving a low on-voltage. Moreover, this invention is providing the manufacturing method which can improve the manufacture yield of such a semiconductor device.
- a semiconductor device includes a first semiconductor layer of a first conductivity type or a second conductivity type opposite to the first conductivity type, and a first semiconductor layer formed on the first semiconductor layer.
- the method of manufacturing a semiconductor device includes a step of forming a first semiconductor layer of a first conductivity type or a second conductivity type opposite to the first conductivity type, and a first conductivity type on the first semiconductor layer.
- Forming a second semiconductor layer, forming a second conductive type third semiconductor layer in an island shape on the second semiconductor layer, and forming an insulating film on the second semiconductor layer and the third semiconductor layer A step of forming a control electrode on the insulating film, a step of forming a first main electrode on the second semiconductor layer and the third semiconductor layer, and a second main electrode having Pd on the first semiconductor layer And a step of forming the structure.
- the present invention it is possible to provide a semiconductor device capable of preventing a latch-up phenomenon and achieving a low on-voltage. Moreover, according to the present invention, it is possible to provide a manufacturing method capable of improving the manufacturing yield of such a semiconductor device.
- FIG. 6 is a first process cross-sectional view illustrating the method of manufacturing the semiconductor device according to Example 1.
- FIG. It is 2nd process sectional drawing. It is 3rd process sectional drawing. It is side surface sectional drawing which shows the semiconductor device which concerns on Example 2 of this invention. It is side surface sectional drawing which shows the structure of IGBT which concerns on a prior art. It is a scatter diagram showing the characteristic of the output voltage V CE and the output current I C of the IGBT according to the prior art.
- Example 1 of the present invention describes an example in which the present invention is applied to a semiconductor device having a punch-through IGBT having a trench structure.
- the IGBT according to Example 1 includes a first conductivity type first semiconductor layer 1 and a second conductivity type second semiconductor layer formed on the first semiconductor layer 1 and opposite to the first conductivity type.
- a second conductive type third semiconductor layer 5 formed in an island shape on the second semiconductor layer 4; an insulating film 7 formed on the second semiconductor layer 4 and the third semiconductor layer 5;
- the first main electrode 22 electrically connected to the second semiconductor layer 4 and the third semiconductor layer 5, and the first semiconductor layer 1, and Pd (palladium).
- the 2nd main electrode 23 which has.
- the first conductivity type is p-type
- the second conductivity type is n-type. That is, the first conductivity type first semiconductor layer 1 is a p + type collector layer, the second conductivity type fourth semiconductor layer 2 is an n + type buffer layer, and the second conductivity type fifth semiconductor layer 3 is an n ⁇ type drift layer.
- the first conductivity type second semiconductor layer 4 is a p-type base layer, and the second conductivity type third semiconductor layer 5 is an n + -type emitter layer.
- the control electrode 21 functions as a gate electrode.
- the first semiconductor layer 1, the fourth semiconductor layer 2, the fifth semiconductor layer 3, the second semiconductor layer 4, the third semiconductor layer 5, the insulating film 7, and the control electrode 21 constitute a punch-through IGBT.
- the first semiconductor layer 1 to the third semiconductor layer 5 are used as a wafer during the manufacturing process, and the semiconductor layer 10 used as a subdivided chip after the dicing step of the manufacturing process is constructed.
- the IGBT employs a trench structure
- the main surface 11 of the semiconductor layer 10 (upper surface in FIG. 1 and the surface of the third semiconductor layer 5) is opposed to the main surface 11.
- a trench 6 formed to face the other main surface (the lower back surface in FIG. 1 and the surface of the first semiconductor layer) 12 and reach the inside of the fifth semiconductor layer 3 is provided.
- the insulating film 7 is formed along the side surface and the bottom surface in the trench 6.
- the control electrode 21 is formed in the trench 6 via the insulating film 7 and is embedded in the trench 6.
- the first main electrode 22 is formed on the second semiconductor layer 4, the third semiconductor layer 5, and the interlayer insulating film 8 formed on the control electrode 21, and is formed on the second semiconductor layer 4 and the third semiconductor layer 5. Electrically connected. That is, the first main electrode 22 is formed on the main surface 11 side of the semiconductor layer 10.
- an Al (aluminum) layer, an Al alloy layer, or the like is used for the first main electrode 22.
- the second main electrode 23 is formed on the entire surface of the first semiconductor layer 1, that is, on the main surface 12 of the semiconductor layer 10.
- the second main electrode 23 is formed by sequentially laminating a Pd layer 231, a Ti (titanium) layer 232, a Ni (nickel) layer 233, and an Au (gold) layer 234 sequentially from the surface of the first semiconductor layer 1. It is comprised by the structure.
- the Pd layer 231 reduces or negatively adjusts the difference ( ⁇ s ⁇ m ) between the electron affinity of the first semiconductor layer 1 and the work function of the second main electrode 23, so that the first semiconductor layer 1 and the second main electrode 1 It has a function of obtaining an ohmic junction with the electrode 23.
- the Pd layer 231 may be pure Pd, but may be Pd silicide for the purpose of obtaining an ohmic junction.
- Pd silicide itself may be formed, but Pd is formed and combined with silicon of the first semiconductor layer 1 by heat treatment at that time or subsequent heat treatment, and all film thicknesses on which Pd is formed are formed. Alternatively, a part of the film thickness may be formed by silicidation.
- the Ti layer 232 has a function as a barrier metal layer, suppresses mixing of oxygen at the interface between the first semiconductor layer 1 and the Pd layer 231, and prevents peeling at the interface.
- the Ni layer 233 has a function as an adhesive layer (alloying reaction layer) when the semiconductor device is mounted by soldering or the like in the assembly process.
- the Au layer 234 has a function of preventing oxidation of the Ni layer 233.
- the Ni layer 233 may be formed on the user side after the semiconductor device is completed, or may not use solder. Therefore, the Ni layer 233 may not be particularly provided in the first embodiment. Similarly, the Au layer 234 may not be provided.
- the second main electrode 23 includes a Pd layer, a Ti layer, a Ni layer, and a Pd layer instead of the stacked structure of the Pd layer 231, the Ti layer 232, the Ni layer 233, and the Au layer 234 described above.
- a laminated structure of Ag layers, or a laminated structure of Pd layers, Ti layers, Ni layers, V (vanadium) layers, and Ag layers can be used.
- an example of a method for manufacturing a semiconductor device according to the first embodiment of the present invention is as follows.
- the semiconductor layer 10 is formed.
- the semiconductor layer 10 first, phosphorus (P) as an n-type impurity is diffused into the first semiconductor layer 1 which is a p + type collector layer to form a fourth semiconductor layer 2 which is an n + type buffer layer.
- a fifth semiconductor layer 3 which is an n ⁇ type drift layer is formed on the fourth semiconductor layer 2 by epitaxial growth, and boron (B) as a p-type impurity is diffused into the fifth semiconductor layer 3 to form a p-type base.
- a second semiconductor layer 4 which is a layer is formed.
- the semiconductor layer 10 of the semiconductor device according to the first embodiment includes the fourth semiconductor layer 2 and the fifth semiconductor layer 3, the present invention does not form the fourth semiconductor layer 2 and the fifth semiconductor. Only layer 3 may be formed.
- a trench 6 is formed on the main surface 11 side of the semiconductor layer 10 (see FIG. 3).
- the trench 6 is formed by dry etching such as reactive ion etching (RIE) using a mask formed by a photolithography technique. It is formed by performing patterning so as to penetrate the second semiconductor layer 4 and the third semiconductor layer 5 and reach the fifth semiconductor layer 3.
- RIE reactive ion etching
- an insulating film 7 made of a silicon oxide film (SiO 2 ) is formed in the trench 6 by using, for example, a thermal oxidation method. As shown in FIG.
- polycrystal silicon is formed on the entire main surface 11 of the semiconductor layer 10 and on the insulating film 7 in the trench 6, and the main surface 11 of the semiconductor layer 10 is subjected to chemical mechanical polishing (CMP).
- CMP chemical mechanical polishing
- the control electrode 21 embedded in the trench 6 is formed by planarization using a polishing method such as).
- the planar shape of the trench 6 and the control electrode 21 is formed in a stripe shape, a lattice shape, or a dot shape.
- an interlayer insulating film 8 is formed on the third semiconductor layer 5, the insulating film 7, and the control electrode 21 (see FIG. 4).
- a silicon oxide film formed by using, for example, a CVD method is used for the interlayer insulating film 8.
- An opening (contact opening) that reaches the second semiconductor layer 4 is formed in the third semiconductor layer 5, the insulating film 7, and the interlayer insulating film 8 using a technique similar to the technique for forming the trench 6.
- a first main electrode 22 made of, for example, Al is formed using a sputtering method.
- the front surface (back surface) of the first semiconductor layer 1 is thinned by using a polishing (back grinding process) (see FIG. 1).
- a Pd layer 231, a Ti layer 232, a Ni layer 233, and an Au layer 234 are sequentially formed on the surface of the first semiconductor layer 1 by sputtering, and the second main layer is formed.
- Electrode 23 is formed.
- the Pd layer 231 of the second main electrode 23 is combined with Si of the first semiconductor layer 1 by heat treatment accompanying the formation of the second main electrode 231 or subsequent heat treatment, for example, heat treatment at about 100 ° C. to 150 ° C.
- the Pd silicide is easily generated at least at the interface between the Pd layer 231 and the first semiconductor layer 1.
- the semiconductor device manufacturing method according to the first embodiment is different from the conventional IGBT manufacturing method in that it includes a step of forming a second main electrode 23 having at least a Pd layer 231, and this second main electrode.
- the steps other than the step of forming the step 23 are formed using the same steps as those of the conventional IGBT manufacturing method.
- the thickness of the first semiconductor layer 1 is, for example, 50 ⁇ m to 300 ⁇ m
- the thickness of the fourth semiconductor layer 2 is, for example, 5 ⁇ m to 20 ⁇ m
- the thickness of the fifth semiconductor layer 3 For example, the thickness is set to 20 ⁇ m to 70 ⁇ m.
- the impurity concentration of the first semiconductor layer 1 is, for example, 1 ⁇ 10 16 cm ⁇ 3 to 1 ⁇ 10 19 cm ⁇ 3 , preferably 5 ⁇ 10 17 cm ⁇ 3 to 8 ⁇ 10 18 cm ⁇ 3 .
- the impurity concentration of the fifth semiconductor layer 3 is set to, for example, 5 ⁇ 10 13 cm ⁇ 3 to 5 ⁇ 10 15 cm ⁇ 3. ing.
- the electron affinity of the first semiconductor layer 1 and the work function of the second main electrode 23 are Difference ( ⁇ s ⁇ m ) can be reduced or set negative, and an ohmic junction is obtained for both connections, so that the on-voltage is low and stable operation is possible. Furthermore, since the impurity concentration of the first semiconductor layer 1 is 5 ⁇ 10 17 cm ⁇ 3 to 8 ⁇ 10 18 cm ⁇ 3, which is lower by one digit or more than the conventional one, the injection amount of holes during the operation of the IGBT is suppressed. And latch-up phenomenon can be prevented.
- the second main electrode 23 has a laminated structure, it can be formed by continuous processing in the same sputtering apparatus. Therefore, there is no increase in the number of steps, and there is no need for special post-processing, so that a semiconductor device can be manufactured at a low cost and with a high yield.
- the semiconductor device and the manufacturing method thereof according to the first embodiment are not limited to the above-described example.
- the present invention is most effective when used in a punch-through IGBT, but may be applied to a non-punch-through IGBT or a planar IGBT having no trench structure. If the present invention is applied to the semiconductor device provided with these IGBTs, the same effect as that obtained by the semiconductor device according to the first embodiment can be obtained.
- the structure of the second main electrode 23 may be a laminated structure including other electrode materials as long as Pd is formed closest to the main surface 12.
- Example 2 of the present invention describes an example in which the present invention is applied to a semiconductor device including a vertical power MOSFET having a trench structure.
- the vertical power MOSFET according to the second embodiment includes a second conductivity type first semiconductor layer 1 and a second conductivity type fifth semiconductor layer 3 formed on the first semiconductor layer 1.
- the insulating film 7 formed on the second semiconductor layer 4 and the third semiconductor layer 5, the control electrode 21 formed on the insulating film 7, and the second semiconductor layer 4 and the third semiconductor layer 5 are electrically connected.
- the first main electrode 22 and the second main electrode 23 electrically connected to the first semiconductor layer 1 and having Pd are provided.
- Example 2 as in Example 1 described above, the first conductivity type is p-type, and the second conductivity type is n-type. That is, the second conductivity type first semiconductor layer 1 is an n + type substrate (drain layer), the second conductivity type fifth semiconductor layer 3 is an n type drain layer, and the first conductivity type second semiconductor layer 4 is a p type.
- the body layer and the third semiconductor layer 5 of the second conductivity type are n + type source layers.
- the control electrode 21 functions as a gate electrode.
- the first semiconductor layer 1, the fifth semiconductor layer 3, the second semiconductor layer 4, the third semiconductor layer 5, the insulating film 7 and the control electrode 21 constitute an n-channel conductivity type vertical power MOSFET.
- the second main electrode 23 has a structure in which, for example, a Pd layer 231, a Ti layer 232, a Ni layer 233, and an Au layer 234 are stacked, similarly to the second main electrode 23 of the semiconductor device according to the first embodiment described above.
- a Schottky junction is formed when a metal such as Ti is brought into direct contact with the first semiconductor layer 1.
- the Pd layer 231 or its silicide layer is in direct contact with the main surface 12 of the first semiconductor layer 1, so that the ohmic junction is the same as in the semiconductor device according to the first embodiment. Can be obtained, and the same effect can be obtained.
- the present invention is not limited to the n-channel conductivity type vertical power MOSFET, but can be applied to a p-channel conductivity type vertical power MOSFET.
- the present invention is not limited to a MOSFET using an oxide film as the insulating film 7, but is applied to a MISFET (MetalMetaInsulator Semiconductor Field Effect Transistor) using a nitride film or an oxynitride film as the insulating film 7. be able to.
- the present invention is not limited to a vertical power MOSFET having a trench structure, but can be applied to a vertical power MOSFET having a planar structure.
- the present invention can be widely applied to a semiconductor device that can prevent a latch-up phenomenon and achieve a low on-voltage and a manufacturing method that can improve the manufacturing yield of such a semiconductor device.
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- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
本発明の実施例1は、トレンチ構造を有するパンチスルー型IGBTを備えた半導体装置に本発明を適用した例を説明するものである。
本発明の実施例2は、トレンチ構造を有する縦型パワーMOSFETを備えた半導体装置に本発明を適用した例を説明するものである。
2 第4半導体層
3 第5半導体層
4 第2の半導体層
5 第3半導体層
6 トレンチ
7 絶縁膜
8 層間絶縁膜
10 半導体層
21 制御電極
22 第1主電極
23 第2主電極
231 Pd層
232 Ti層
233 Ni層
234 Au層
Claims (9)
- 第1導電型又はそれとは反対の第2の導電型の第1半導体層と、
前記第1半導体層上に形成された前記第1導電型の第2半導体層と、
前記第2半導体層上に島状に形成された前記第2導電型の第3半導体層と、
前記第2半導体層及び前記第3半導体層上に形成された絶縁膜と、
前記絶縁膜上に形成された制御電極と、
前記第2半導体層及び前記第3半導体層に電気的に接続された第1主電極と、
前記第1半導体層に電気的に接続され、Pdを有する第2主電極と、
を備えることを特徴とする半導体装置。 - 前記第2の主電極は前記第1半導体層の前記第2半導体層が形成された表面に対向する裏面の全域に形成されていることを特徴とする請求項1に記載の半導体装置。
- 前記第2主電極はPdシリサイド層を有することを特徴とする請求項1又は請求項2に記載の半導体装置。
- 前記第2主電極は、前記第1半導体層上に形成されたPd層若しくはPdシリサイド層と、このPd層若しくはPdシリサイド層上に形成されたTi層と、このTi層上に形成されたNi層とを有することを特徴とする請求項1乃至請求項3のいずれかに記載の半導体装置。
- 前記第2主電極の前記Ni層上には更にAu層を備えたことを特徴とする請求項4に記載の半導体装置。
- 前記第1半導体層により形成されるコレクタ層と、前記第2半導体層により形成されるベース層と、前記第3半導体層により形成されるエミッタ層とを有するIGBTを備えたことを特徴とする請求項1乃至請求項5のいずれかに記載の半導体装置。
- 前記第1半導体装置により形成されるドレイン層と、前記第2半導体層により形成されるボディ層と、前記第3半導体層により形成されるソース層とを有するMOSFETを備えたことを特徴とする請求項1乃至請求項5のいずれかに記載の半導体装置。
- 第1導電型又はそれとは反対の第2導電型の第1半導体層を形成する工程と、
前記第1半導体層上に前記第1導電型の第2半導体層を形成する工程と、
前記第2半導体層上に島状に前記第2導電型の第3半導体層を形成する工程と、
前記第2半導体層及び前記第3半導体層上に絶縁膜を形成する工程と、
前記絶縁膜上に制御電極を形成する工程と、
前記第2半導体層及び前記第3半導体層上に第1主電極を形成する工程と、
前記第1半導体層上にPdを有する第2主電極を形成する工程と、
を備えることを特徴とする半導体装置の製造方法。 - 前記第2主電極を形成する工程は、前記第1半導体層上にPd層若しくはPdシリサイド層、Ti層、Ni層のそれぞれを順次積層する工程であることを特徴とする請求項8に記載の半導体装置の製造方法。
Priority Applications (5)
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JP2010517851A JPWO2009157299A1 (ja) | 2008-06-26 | 2009-06-08 | 半導体装置及びその製造方法 |
KR1020107009506A KR101128286B1 (ko) | 2008-06-26 | 2009-06-08 | 반도체 장치 및 그 제조 방법 |
US12/740,310 US20100237385A1 (en) | 2008-06-26 | 2009-06-08 | Semiconductor device and method of fabricating the same |
CN200980100856A CN101842903A (zh) | 2008-06-26 | 2009-06-08 | 半导体装置及其制造方法 |
EP09770009A EP2293337A4 (en) | 2008-06-26 | 2009-06-08 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR |
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US (1) | US20100237385A1 (ja) |
EP (1) | EP2293337A4 (ja) |
JP (1) | JPWO2009157299A1 (ja) |
KR (1) | KR101128286B1 (ja) |
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WO (1) | WO2009157299A1 (ja) |
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JP2021506111A (ja) * | 2017-12-05 | 2021-02-18 | 無錫華潤上華科技有限公司Csmc Technologies Fab2 Co., Ltd. | 絶縁ゲートバイポーラトランジスタおよびその製造方法 |
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KR20120127055A (ko) * | 2011-05-13 | 2012-11-21 | 삼성전자주식회사 | 절연 게이트 바이폴라 트랜지스터의 제조 방법 |
US9431484B2 (en) * | 2011-07-29 | 2016-08-30 | Infineon Technologies Austria Ag | Vertical transistor with improved robustness |
JP2014187190A (ja) * | 2013-03-22 | 2014-10-02 | Toshiba Corp | 半導体装置の製造方法 |
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- 2009-06-08 US US12/740,310 patent/US20100237385A1/en not_active Abandoned
- 2009-06-08 CN CN200980100856A patent/CN101842903A/zh active Pending
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JP2002525849A (ja) * | 1998-09-16 | 2002-08-13 | クリー インコーポレイテッド | 縦型デバイスのための裏面オーミックコンタクトの低温形成 |
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EP2293337A4 (en) | 2011-12-28 |
KR20100072325A (ko) | 2010-06-30 |
US20100237385A1 (en) | 2010-09-23 |
JPWO2009157299A1 (ja) | 2011-12-08 |
KR101128286B1 (ko) | 2012-03-23 |
EP2293337A1 (en) | 2011-03-09 |
CN101842903A (zh) | 2010-09-22 |
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