WO2009133510A1

WO2009133510A1 - Method of manufacturing a capacitor on a nanowire and integrated circuit having such a capacitor

Info

Publication number: WO2009133510A1
Application number: PCT/IB2009/051694
Authority: WO
Inventors: Jozef T M. Van Beek; Erik P. A. M. Bakkers; Freddy Roozeboom
Original assignee: Nxp B.V.
Priority date: 2008-04-29
Filing date: 2009-04-24
Publication date: 2009-11-05

Abstract

A method of manufacturing a capacitor on a wafer, and an IC comprising such a capacitor is disclosed. The method comprises forming a plurality of vertical structures (140) each having a sub-micron thickness on the wafer; and growing a metal-insulator-metal (MIM) stack (150) over the plurality of vertical structures (140). In a preferred embodiment, the method further comprises depositing a catalyst layer (130) over the wafer; and patterning the catalyst layer, and wherein the step of forming the plurality of vertical structures (140) comprises growing a plurality of nanowires on the patterned catalyst layer. Consequently, a capacitor formed by the MIM stack (150) is obtained that has a very high capacitance density and that can be formed on top of an IC in the back- end process of an IC manufacturing process.

Description

DESCRIPTION

METHOD OF MANUFACTURING A CAPACITOR ON A NANOWIRE AND INTEGRATED CIRCUIT HAVING SUCH A CAPACITOR

The present invention relates to a method of manufacturing a capacitor on a wafer, the method comprising forming a plurality of vertical structures each having a sub-micron thickness on the wafer.

The present invention further relates to an integrated circuit (IC) comprising a capacitor.

The ongoing downscaling of semiconductor device feature sizes poses a continuous design challenge. For instance, the decrease in footprint of a semiconductor device makes it more difficult to include capacitors have a substantial capacitance in such a device, since the capacitance scales linearly with the electrode plate area of the capacitor. Nevertheless, semiconductor devices are becoming more complex, which usually means that the device requires the inclusion of a higher density of capacitors having a certain capacitance, thus further complicating the design process. Furthermore, higher capacitance densities usually lead to a reduction of cost, since less chip area is required in order to realize a certain capacitance value.

In order to increase the capacitance of the capacitive element of a semiconductor device, nanostructures have been used to form capacitive elements that are grown vertically on a horizontal substrate, i.e. perpendicularly to the substrate surface to increase the surface area of the electrode plates.

For instance, US2007/0082495 A1 discloses a method of forming a capacitor having vertical pillars of a conductive material by depositing nanocrystals over the conductive material and using the nanocrystals as a hard mask to form the pillars. The pillars are subsequently covered by a dielectric layer and a further conductive layer to form the capacitor. A drawback of this method is its complexity, which significantly increases the manufacturing cost of such a device.

US2006/0279905 A1 discloses a method of forming a capacitor wherein a first electrode is formed by vertically growing a plurality of nanofibers on a substrate, subsequently coating the nanofibers with a dielectric layer and subsequently coating the dielectric layer with a conductive material to form the opposite electrode of the capacitor.

US2006/0186451 A1 discloses a method of fabricating a memory element comprising a capacitor in which a first electrode of the capacitor is formed by growing a plurality of multi-walled carbon nanotubes in a vertical direction on a catalyst layer deposited over a silicon (Si) substrate. The nanotubes are covered by a dielectric layer deposited by means of chemical vapor deposition (CVD) or atomic layer deposition (ALD) to form thin dielectric layers, thereby increasing the capacitance of the capacitor. The dielectric layer is subsequently covered by a second electrode layer to complete the capacitor.

However, the use of nanofibers or multi-walled nanocrystals as a capacitor electrode can have a detrimental effect on the conductive properties of such an electrode. For instance, the semiconductor properties of such nanostructures can lead to a substantial series resistance across the capacitor plates. Moreover, when such nanostructures are used as electrodes, the nanostructures must be formed on a conductive layer that is externally contactable in order to make the nanostructure electrode externally accessible. This limits the applicability of such capacitors.

Hence, the present invention seeks to provide an improved method of forming a capacitor on a wafer.

The present invention further seeks to provide an integrated circuit having at least one of such a capacitor on its substrate.

According to a first aspect of the present invention, there is provided a method of manufacturing a capacitor on a wafer, the method comprising forming a plurality of vertical structures each having a sub-micron thickness on the wafer; and growing a metal-insulator-metal stack over the plurality of vertical structures.

Such a method provides a capacitor with a much higher capacitance than a planar, e.g. horizontal capacitor, due to the increased surface area provided by the vertical structures of a sub-micron thickness, i.e. vertical nanostructures, in which the electrodes are formed on the vertical nanostructures without requiring the nanostructures to act as the bottom electrode. In addition, the inner metal layer of the MIM stack, i.e. the metal layer covering the nanostructures lowers the series resistance of the capacitor plates compared to a capacitor plate formed by the nanostructure itself. This is particularly valid when the nanostructure dimension, e.g. the diameter of a nanowire, is of the same magnitude as the thickness of the first metal layer in order to get a high packing density of the wires and hence a high capacitance density. In that case, the series resistance of a semi-conductor nanostructure will be much higher than the metal layer of the present invention.

The nanostructures may be formed by patterning a deposited layer such as a dielectric layer, for instance as disclosed in US2007/0082495 A1. Preferably, the vertical nanostructures are formed by depositing a catalyst layer over the wafer, patterning the catalyst layer, and growing a plurality of nanowires on the patterned catalyst layer. This is a more cost-effective way of forming such a capacitor.

A further advantage of using nanowires in the method of the present invention is that the steps are suitable for integration in a back-end integrated circuit (IC) manufacturing process, where temperatures in excess of 500 C are typically undesirable because such high temperatures can deteriorate deposited materials and dopant regions. The nanowires, such as GaP, InAs, InP, GaAs, Si, or Ge nanowires can be grown at temperatures well below 500 C, in contrast to the deposition of nanotubes, which deposition step typically has to be performed at temperatures in excess of 500 C. In an embodiment, the step of growing the plurality of nanowires is executed at a temperature in a temperature range of 300-500 C. - A -

In another embodiment, the step of growing the metal-insulator-metal stack is executed at a temperature not exceeding 400 C.

Advantageously, the various layers of the metal-insulator-metal stack are grown by means of ALD. ALD has the advantage that very thin layers with very high step coverage can be deposited over non-planar surfaces, which makes this technique suitable for depositing the various layers over nanostructures such as nanowires.

The method of the present invention typically forms part of an IC manufacturing process. The manufacturing of such an IC may be completed using any suitable process. In an embodiment, the method further comprises patterning the metal-insulator-metal stack, covering the patterned metal-insulator- metal stack covered vertical structures with an insulating layer; patterning the insulating layer to expose the respective metal layers of the metal-insulator-metal stack; depositing a conductive material over the patterned insulating layer; and patterning the conductive material to form individual connections with the respective metal layers of the patterned metal-insulator-metal stack to make the capacitor electrodes accessible.

The conductive material may be any suitable conductive metal. In an embodiment, the conductive material is a metal chosen from the group consisting of copper and aluminum because these metals are particularly suitable for integration in a CMOS process.

In an embodiment, the wafer comprises a passivation layer covering a buried interconnect layer, and wherein the step of patterning the insulating layer further comprises patterning the insulating layer and the substrate to expose the buried layer, and wherein the step of patterning the conductive material to form individual connections comprises patterning the conductive material to form individual connections between the respective metal layers of the metal-insulator- metal stacks and the buried interconnect layer. The buried interconnect layer may form a part of an IC formed in the wafer. In this case, the capacitor is formed on top of the IC, which means that the whole area of the IC, excluding the area needed for the IC interconnects such as bond pads, can be utilized for the formation of one or more capacitors. By connecting the capacitor to the buried interconnect layer, the capacitor may for instance be used in an electrostatic discharge protection circuit of the IC, for instance by connecting it to a diode structure in the IC in the wafer. According to a further aspect of the present invention, there is provided an

IC comprising at least one capacitor formed on a layer of the IC, wherein the at least one capacitor comprises a stack of a first metal, an insulator and a second metal, said stack covering a plurality of vertical structures each having a sub- micron thickness. Such an IC benefits from providing a high-capacitance capacitor at relatively low cost because the capacitor can be manufactured using existing manufacturing technologies such as CMOS.

In an embodiment, the integrated circuit comprises a plurality of capacitors, each capacitor being arranged to act as a memory element. This provides a memory device having memory elements that can retain large amounts of charge, thus improving the charge retention time of the elements.

Preferably, the IC layer carries at least one catalyst layer portion, and wherein each vertical structure comprises a nanowire formed on a respective catalyst layer portion, because such an IC can be manufactured relatively cheaply since the nanostructures do not have to be formed by patterning. The IC of the present invention may be integrated in any suitable electronic device.

Embodiments of the invention are described in more detail and by way of non-limiting examples with reference to the accompanying drawings, wherein:

FIGs.1a-i schematically depict the steps of an embodiment of the method of the present invention;

FIG. 2 shows a scanning electron microscope (SEM) image of nanowires grown on a SiO₂ layer; FIG. 3 shows another scanning electron microscope (SEM) image of nanowires grown on a SiO₂ layer; FIG. 4 shows a scanning electron microscope (SEM) image of nanowires grown on a patterned catalyst layer; and

FIG. 5 depicts the impact of the length of the nanowire on the capacitance of the formed capacitor.

It should be understood that the Figures are merely schematic and are not drawn to scale. It should also be understood that the same reference numerals are used throughout the Figures to indicate the same or similar parts.

In FIG. 1a, a wafer comprising a device layer 100, an interconnect layer 110 and a passivation layer 120 is provided. The device layer 100 may include a plurality of transistors formed on the wafer substrate and the interconnect layer

110 may comprise one or more metal layers for interconnecting the devices in the device layer 110. In other words, the layers 100 and 110 may comprise an integrated circuit formed in the wafer. The wafer may be a silicon wafer or another suitable material for forming an IC. The passivation layer 120 typically comprises a dielectric material such as SO₂ or Si₃N₄, or any other suitable dielectric material such as a high-k dielectric. The passivation layer 120 has the function of electrically insulating the interconnect layer 110.

In FIG. 1 b, a catalyst layer 130 is deposited over the passivation layer. This catalyst layer 130 is intended to facilitate the growth of a nanostructure such as a nanowire or a nanotube thereon. Any suitable catalyst material may be used for the catalyst layer 130. In an embodiment, the catalyst material is chosen from the group of noble metals, because such metals have excellent catalytic properties, and in particular gold (Au). The catalyst layer 130 may be grown using any suitable deposition, e.g. by evaporation or sputtering, and can be kept relatively thin, e.g. less than 10 nm.

In Fig. 1c, the catalyst layer 130 is patterned into catalyst regions 135. The patterning may be done using any suitable patterning techniques including wet etching and dry etching. The catalyst regions 135 may have any suitable shape, e.g. circular shapes, square shapes, rectangular shapes and so on. The spacing between the catalyst regions is chosen such that the nanostructures grown thereon are sufficiently far apart to allow the nanostructures to be covered by a metal-insulator-metal stack. In an embodiment, the distance between the catalyst regions 135 is chosen from a range of 50-500 nm.

In FIG. 1 d, nanostructures 140, e.g. nanowires or nanotubes, are grown on the catalyst regions 135. This increases the effective surface area of the passivation layer 120. FIG. 2-4 demonstrate that such nanostructures 140 can be effectively grown on such a passivation layer 120. The SEM image of FIG. 2 shows nanowires 220 that are directly grown on a Siθ2 layer with a random orientation and position. FIG. 3 shows a SEM image of nanowires 320 that are epitaxially grown on a SiO₂ layer, thus giving a defined orientation but a random position. The nanowires 320 have an increasing thickness going from panel (a) to panel (c). The scale bars in FIG. 3 define 1 micron. FIG. 4 shows a SEM image of nanowires 140 epitaxially grown on patterned catalyst regions 135. It can be seen that a well-controlled distribution and orientation of nanowires 140 is obtained.

Now, returning to FIG. 1d, the nanostructures 140 may be grown at temperatures that are compatible with the back-end processes for forming a CMOS IC in the wafer, thereby avoiding damage to the IC during the growth of the nanostructures 140. In embodiment, the nanostructures 140 are grown at a temperature from the range of 300-500 C. Since the technique of growing such nanowires is well-known to the skilled person, this will not be explained in detail for reasons of brevity only. The nanostructures 140 may be grown from any suitable material. In an embodiment, the nanostructures 140 are nanowires grown from a material selected from the group consisting of GaP, InAs, InP, GaAs, Si, Ge, because these materials allow formation of the nanowires at temperatures below 500 C, e.g. 420 C.

The nanostructures 140 typically have a sub-micron thickness in the nanometer domain, e.g. 10-50 nm. In the context of the present invention, the phrase 'thickness' is intended to describe the horizontal dimension of the nanostructures 140 such as the diameter of nanotubes or nanowires. The nanostructures may be grown to any suitable height. In an embodiment, the nanostructures 140 are grown to a height in the range of 1 -10 micron.

In FIG. 1 e, a metal-insulator-metal (MIM) stack 150 is grown over the passivated layer 120, thereby covering the nanostructures 140. In a preferred embodiment, the layers of the MIM stack 150 are grown by means of sequential ALD steps, because ALD grown layers have good uniformity in their thickness. For example, the first metal layer 152 may be a TiN layer grown to a thickness of 20 nm, after which the insulator layer 154, e.g. an AI₂O₃ layer, is grown to a thickness of 10 nm. The MIM stack 150 is completed by subsequently growing the second metal layer 156, which may be a TiN layer, to a thickness of 20 nm.

This yields a capacitor having an overall thickness of 50 nm, with the first metal layer 152 being the first plate of the capacitor and the second metal layer 156 being the second plate of the capacitor. The capacitor is wrapped around the nanostructures 140 rather than the nanostructures 140 forming a part of one of the capacitor plates. As is well known in the art, the insulator layer 154, which acts as the dielectric layer between the plates of the capacitor, may be kept as thin as possible to maximize the capacitance of the capacitor. It should be appreciated that the above thicknesses of the respective layers of the MIM stack 150 are given by way of non-limiting example only and that other thicknesses are equally feasible.

In an embodiment, The ALD process steps are performed at temperatures not exceeding 400 C. This also makes the ALD process steps compatible with the back-end process of the manufacturing of a CMOS IC. It will be appreciated that the MIM stack 150 may be grown using any suitable layer deposition technique such as chemical vapor deposition (CVD), plasma-enhanced CVD or physical vapor, or sputter, deposition (PVD).

At this point, it is emphasized that the nanostructures 140 do not have to be grown in the aforementioned manner. For instance, the approach described in US2007/0082495 A1 may also be used to form nanostructures 140 in the form of nanopillars by means of patterning, after which the MIM stack 150 may be deposited over such nanostructures. The manufacturing process of an IC carrying the MIM capacitor 150 may be completed in any suitable manner. For instance, as shown in FIG. 1f, the MIM stack 150 may be patterned such that the first metal layer 152 and the second metal layer 156 may be individually connected, as shown in regions 158. The patterning of the MIM stack 150 may be performed using any suitable patterning process such as a wet etch or a dry etch.

In a next step shown in FIG. 1g, a dielectric layer 160 is deposited over the patterned MIM stack 150. This layer may be formed of any suitable dielectric material. In an embodiment, the dielectric material is polyimide. The deposition may be achieved using any suitable technique. In case of dielectric material being polyimide, the polyimide layer may be spin-coated over the patterned MIM stack 150. The dielectric layer 160 is used to protect the MIM stack 150 from further processing, as well as to improve the structural integrity of the stack.

The dielectric layer 160 is subsequently patterned as shown in FIG. 1 h. A trench 162 is formed to provide access to the first metal layer 152, and a trench 164 is formed to provide access to the second metal layer 156. In case the MIM capacitor 150 is to be connected to the buried interconnect layer 110, further trenches 166 and 168 may be formed to provide access to the appropriate sections of the buried interconnect layer 110. It should be appreciated that although the interconnect layer 110 is depicted as a continuous layer, the interconnect layer 110 typically comprises a plurality of patterned conductive structures, with the trenches 166 and 168 providing access to respective conductive structures in the buried interconnect layer 120.

As shown in FIG. 1 i, a conductive material is subsequently deposited over the patterned dielectric layer 160 and subsequently patterned into conductive structures 170 such that the respective electrodes of the MIM capacitor 150 can be controlled through the conductive structures 170. In an embodiment, the material used for forming the conductive structures is Cu or Al, because these metals are compatible with a conventional CMOS process. Consequently, a MIM capacitor 150 is obtained that is formed on top of an

IC. As shown in FIG. 5, left panel, which depicts the surface area of such a capacitor compared to a planar capacitor covering the same area of the passivation layer 120 as a function of wire diameter (shown in units of 10 nm) and length (three wire lengths of 1 micron, 5 micron and 9 micron respectively are shown), an increase in effective surface area in excess of a factor 50 can be achieved. The predicted capacitance density per square millimeter of these MIM capacitors 150 is depicted in the right panel of FIG. 5. It can be seen that densities in well in excess of 0.5^*10^"6 Farad/mm² can be achieved by the MIM capacitor 150.

When utilizing the top surface of an IC for the manufacturing of such MIM capacitors 150, an aggregate capacitance in the microfarad range can be obtained. This for instance allows for the integration of on-chip high-value capacitors that can be used as decoupling capacitors, or that can be used in power management applications such as DC-DC conversion stages when combined with e.g. planar inductors and field-effect-transistor based switches. In general, the ability to utilize substantially the whole top surface area of the IC, except area regions required for forming interconnects such as bond pads, makes it possible to integrate capacitors that previously had to be provided off- chip.

By integrating such an IC in an electronic device, this means that an electronic device is obtained that requires less discrete components, thereby reducing the risk of failure of the electronic device caused by of a faulty discrete component.

It is emphasized that the present invention is not limited to growing a MIM capacitor 150 on top of an IC. The MIM capacitor 150 may for instance also be formed in the transistor layer 100 without departing from the teachings of the present invention.

It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps other than those listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Claims

1. A method of manufacturing a capacitor on a wafer, the method comprising: forming a plurality of vertical structures (140) each having a sub-micron thickness on the wafer; and growing a metal-insulator-metal stack (150) over the plurality of vertical structures (140).

2. A method according to claim 1 , further comprising: depositing a catalyst layer (130) over the wafer; and patterning the catalyst layer, and wherein the step of forming the plurality of vertical structures (140) comprises growing a plurality of nanowires on the patterned catalyst layer.

3. A method according to claim 2, wherein the step of growing the plurality of nanowires is executed at a temperature range of 300-500 C.

4. A method according to any of claims 1-3, wherein the various layers of the metal-insulator-metal stack (150) are grown by means of atomic layer deposition.

5. A method according to any of claims 1-4, wherein the step of growing the metal-insulator-metal stack (150) is executed at a temperature not exceeding 400^°C.

6. A method according to any of claims 1-5, further comprising: patterning the metal-insulator-metal stack (150); covering the metal-insulator-metal stack covered vertical structures (140) with an insulating layer (160); patterning the insulating layer to expose the respective metal layers (152,

156) of the patterned metal-insulator-metal stack (150); depositing a conductive material over the patterned insulating layer (160); and patterning the conductive material to form individual connections (170) with the respective metal layers (152, 156) of the patterned metal-insulator-metal stack (150).

7. A method according to claim 6, wherein the conductive material is a metal chosen from the group consisting of copper and aluminum.

8. A method according to claim 6 or 7, wherein the wafer comprises a passivated layer (120) covering a buried interconnect layer (110), and wherein the step of patterning the insulating layer (160) further comprises pattering the insulating layer (160) and the passivated layer (120) to expose the buried interconnect layer (110), and wherein the step of patterning the conductive material to form individual connections (170) comprises patterning the conductive material to form individual connections (170) between the respective metal layers (152, 156) of the metal-insulator-metal stack and the buried interconnect layer (110).

9. A method as claimed in claim 8, wherein the buried interconnect layer (110) forms a part of an integrated circuit in the wafer.

10. An integrated circuit comprising at least one capacitor formed on a layer (120) of the integrated circuit, wherein the at least one capacitor comprises a stack (150) of a first metal (152), an insulator (154) and a second metal, said stack (150) covering a plurality of vertical structures (140) each having a sub- micron thickness.

11. An integrated circuit according to claim 10, wherein the layer (120) is a passivation layer.

12. An integrated circuit according to claim 11 , wherein the passivation layer (120) covers an interconnect layer (110), and wherein the first metal (152) and the second metal (156) are individually connected to the interconnect layer (110).

13. An integrated circuit according to any of claims 10-12, wherein the integrated circuit comprises a plurality of capacitors, each capacitor being arranged to act as a memory element.

14. An integrated circuit according to any of claims 10-13, wherein the layer carries at least one catalyst layer portion (135), and wherein each vertical structure (140) comprises a nanowire formed on a respective catalyst layer portion (135).

15. An electronic device comprising an integrated circuit according to any of claims 10-14.