WO2009123335A1 - Mos型半導体メモリ装置の製造方法およびプラズマcvd装置 - Google Patents
Mos型半導体メモリ装置の製造方法およびプラズマcvd装置 Download PDFInfo
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- WO2009123335A1 WO2009123335A1 PCT/JP2009/057019 JP2009057019W WO2009123335A1 WO 2009123335 A1 WO2009123335 A1 WO 2009123335A1 JP 2009057019 W JP2009057019 W JP 2009057019W WO 2009123335 A1 WO2009123335 A1 WO 2009123335A1
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- Prior art keywords
- insulating film
- forming
- band gap
- semiconductor memory
- memory device
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 126
- 238000000034 method Methods 0.000 title claims abstract description 59
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 53
- 238000005268 plasma chemical vapour deposition Methods 0.000 claims abstract description 26
- 239000007789 gas Substances 0.000 claims description 171
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 61
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 61
- 230000008569 process Effects 0.000 claims description 25
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 21
- 230000007246 mechanism Effects 0.000 claims description 15
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 14
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 6
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 5
- 239000002994 raw material Substances 0.000 claims description 4
- 239000002210 silicon-based material Substances 0.000 claims description 4
- 230000007423 decrease Effects 0.000 claims description 3
- 229910001873 dinitrogen Inorganic materials 0.000 claims description 3
- 239000010408 film Substances 0.000 description 505
- 229910052710 silicon Inorganic materials 0.000 description 45
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 44
- 239000010703 silicon Substances 0.000 description 44
- 239000000758 substrate Substances 0.000 description 33
- 239000010410 layer Substances 0.000 description 23
- 238000010586 diagram Methods 0.000 description 18
- 230000014759 maintenance of location Effects 0.000 description 18
- 238000003860 storage Methods 0.000 description 18
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 14
- 125000006850 spacer group Chemical group 0.000 description 13
- 230000004888 barrier function Effects 0.000 description 12
- 230000005855 radiation Effects 0.000 description 12
- 230000015572 biosynthetic process Effects 0.000 description 11
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 6
- 230000008859 change Effects 0.000 description 6
- 239000011261 inert gas Substances 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 229910000077 silane Inorganic materials 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 230000005540 biological transmission Effects 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- 208000025174 PANDAS Diseases 0.000 description 3
- 208000021155 Paediatric autoimmune neuropsychiatric disorders associated with streptococcal infection Diseases 0.000 description 3
- 240000004718 Panda Species 0.000 description 3
- 235000016496 Panda oleosa Nutrition 0.000 description 3
- 238000009825 accumulation Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 238000010030 laminating Methods 0.000 description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 3
- 150000004706 metal oxides Chemical class 0.000 description 3
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Substances [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- VOSJXMPCFODQAR-UHFFFAOYSA-N ac1l3fa4 Chemical compound [SiH3]N([SiH3])[SiH3] VOSJXMPCFODQAR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910021529 ammonia Inorganic materials 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000005284 excitation Effects 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 229910052451 lead zirconate titanate Inorganic materials 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- HDZGCSFEDULWCS-UHFFFAOYSA-N monomethylhydrazine Chemical compound CNN HDZGCSFEDULWCS-UHFFFAOYSA-N 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 102000007696 Proto-Oncogene Proteins c-yes Human genes 0.000 description 1
- 108010021833 Proto-Oncogene Proteins c-yes Proteins 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- JRPBQTZRNDNNOP-UHFFFAOYSA-N barium titanate Chemical compound [Ba+2].[Ba+2].[O-][Ti]([O-])([O-])[O-] JRPBQTZRNDNNOP-UHFFFAOYSA-N 0.000 description 1
- 229910002113 barium titanate Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000010494 dissociation reaction Methods 0.000 description 1
- 230000005593 dissociations Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000005672 electromagnetic field Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000002784 hot electron Substances 0.000 description 1
- 150000002429 hydrazines Chemical class 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- HFGPZNIAWCZYJU-UHFFFAOYSA-N lead zirconate titanate Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ti+4].[Zr+4].[Pb+2] HFGPZNIAWCZYJU-UHFFFAOYSA-N 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- UVGLBOPDEUYYCS-UHFFFAOYSA-N silicon zirconium Chemical compound [Si].[Zr] UVGLBOPDEUYYCS-UHFFFAOYSA-N 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 229910002076 stabilized zirconia Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
- C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
- C23C16/34—Nitrides
- C23C16/345—Silicon nitride
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
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- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
- C23C16/50—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges
- C23C16/511—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges using microwave discharges
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/318—Inorganic layers composed of nitrides
- H01L21/3185—Inorganic layers composed of nitrides of siliconnitrides
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
- H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
- H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
- H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
Definitions
- the present invention relates to a method for manufacturing an MO S (Me te a l -O x i d e -S i 1 i kon) type semiconductor memory device, and a plasma C V D device used therefor.
- MO S Metal te a l -O x i d e -S i 1 i kon
- E E P ROM E l c t r i c a l l y-E r a s a b 1 e-a n d-P r a g r amm a b 1 e-R OM
- E E P ROM E l c t r i c a l l y-E r a s a b 1 e-a n d-P r a g r amm a b 1 e-R OM
- EEPROM a voltage is applied between the semiconductor substrate and the control gate electrode, and the insulating film (insulating film laminate) of the above laminated structure is mainly in the silicon nitride film or the silicon nitride film and the silicon oxide films above and below it.
- the insulating film laminate of the above laminated structure is mainly in the silicon nitride film or the silicon nitride film and the silicon oxide films above and below it.
- the prior art will be described by taking as an example the case of injecting electrons into an insulating film stack as a charge storage region.
- 0 V is applied to the semiconductor substrate, and, for example, 10 V is applied to the control gate electrode.
- semiconductor A strong electric field is applied to the insulating film stack between the body substrate and the control gate electrode, and electrons are injected from the semiconductor substrate into the silicon nitride film through the lower silicon oxide film by a tunnel phenomenon.
- the injected electrons are trapped mainly in the silicon nitride film or near the interface between the silicon nitride film and the lower silicon oxide film or the upper silicon oxide film, and are accumulated as data.
- an important performance required for a nonvolatile semiconductor memory device such as E EP PROM is data retention characteristics.
- a MOS semiconductor memory device of the prior art electrons trapped in a silicon nitride film or near the interface between a silicon nitride film and a lower silicon oxide film or an upper silicon oxide film are stably stabilized for a long time.
- the thickness of the upper and lower silicon oxide films is increased, there is a problem that the data writing speed becomes slow because the electric field applied to the insulating film stack becomes weak when writing data.
- Patent Document 1 Japanese Laid-Open Patent Publication No. 2 0 0 2 — 2 0 3 9 1 7 Disclosure of Invention
- the inventors of the present invention have improved data retention characteristics and high-speed data by controlling the bandgap structure of the insulating film that constitutes the insulating film stack functioning as the charge storage region in the MOS semiconductor memory device. We obtained knowledge that evening rewriting performance, operation performance with low power consumption, and high reliability could be realized at the same time.
- the present invention has been made in view of the above circumstances, and a MOS semiconductor memory device that can easily manufacture a MOS semiconductor memory device having insulating film stacks having different band gaps between adjacent insulating films.
- An object is to provide a method for manufacturing a device. Means for solving the problem
- the manufacturing method of the MOS type semiconductor memory device of the present invention includes a MOS type semiconductor comprising an insulating film laminate formed by laminating a plurality of insulating films as a region for accumulating charges between a semiconductor layer and a gate electrode.
- a method for manufacturing a memory device which uses a plasma processing apparatus that introduces microwaves into a processing chamber using a planar antenna having a plurality of holes, and at least supplies a source gas.
- plasma CVD under a pressure condition different from the pressure condition for forming the adjacent insulating film, the band gap size of the adjacent insulating films constituting the insulating film stack is sequentially changed. An insulating film is formed, and the insulating film stack is formed.
- the step of forming the insulating film stacked body uses ammonia gas and silicon-containing compound gas as the source gas, and a processing pressure is 1 Pa or more 1 3 3 Plasma C VD is performed at a first pressure within a range of 3 Pa or less to form a silicon nitride film having a first band gap, and a processing pressure is 1 Pa or more 1 3 3 3 Pa or less
- the step of forming the insulating film laminate uses a nitrogen gas and a silicon-containing compound gas as the source gas, and a processing pressure is 1 Pa or more 1 3 3 Plasma C VD is performed at a first pressure within a range of 3 Pa or less to form a silicon nitride film having a first pand gap, and the processing pressure is 1 Pa or more 1 3 3 3 Pa
- the step of forming the insulating film stack is provided at a position closest to the semiconductor layer.
- a step of forming a third insulating film having: a step of forming a fourth recording film having a band gap smaller than that of the third insulating film; and a position closest to the gate electrode, And a step of forming a fifth insulating film having a larger band gap than the fourth insulating film.
- the step of forming the insulating film stack includes the step of forming a first insulating film provided at a position closest to the semiconductor layer, Forming a second insulating film having a smaller band gap than the first insulating film; forming a third insulating film having a smaller band gap than the second insulating film; and Forming a fourth insulating film having a larger band gap than the third insulating film, and a fifth insulating film provided at a position closest to the gate electrode and having a larger gap than the fourth insulating film. It is preferable that the method includes a step of forming a film.
- the second insulating film in the thickness direction of the film from the semiconductor layer side to the gate electrode side, the second insulating film is formed. It is preferable that the bandgap has an energy band structure that gradually increases or decreases from the vicinity of the interface with the insulating film toward the vicinity of the interface with the fourth insulating film.
- the second insulating film, the third insulating film, and the fourth insulating film are interposed between the first insulating film and the fifth insulating film. It is preferable to repeatedly form an intermediate laminate including an insulating film.
- a silicon oxide film is formed as the first insulating film and the fifth insulating film, the second insulating film, the third insulating film, and A silicon nitride film is preferably formed as the fourth insulating film.
- the computer-readable storage medium of the present invention is a computer-readable storage medium in which a control program that operates on a computer is stored, and the control program is executed between the semiconductor layer and the gate electrode when executed.
- a control program that operates on a computer is stored, and the control program is executed between the semiconductor layer and the gate electrode when executed.
- an insulating film at least adjacent to the source gas is formed in the processing chamber. Insulating films are sequentially formed by changing the band gap size of adjacent insulating films constituting the insulating film stack by plasmaizing and performing plasma CVD under pressure conditions different from the pressure conditions used in the process. Then, the plasma CVD apparatus is controlled in a combined manner so that the step of forming the insulating film laminate is performed.
- the plasma C VD apparatus is a plasma C VD apparatus for forming an insulating film on a target object by a plasma C VD method, the processing chamber for mounting the target object on a mounting table, A dielectric member that closes the opening of the processing chamber; an antenna that is provided outside the dielectric member and that introduces microwaves into the processing chamber; A gas supply mechanism for supplying gas, an exhaust mechanism for evacuating the processing chamber, and an insulating film laminate in which a plurality of insulating films are stacked as a region for accumulating charges between the semiconductor layer and the gate electrode
- the source gas is converted into plasma by the microwave under a pressure condition different from the pressure condition for forming the adjacent insulating film in the processing chamber.
- the insulating film stack is sequentially formed by changing the bandgap size of adjacent insulating films to form the insulating film stack. And a control unit.
- plasma CVD is performed under a pressure condition different from the pressure condition in forming an adjacent insulating film, so that the adjacent insulating film stack is formed.
- Insulating films can be alternately deposited by changing the band gap of the insulating film.
- the bandgap size can be easily controlled only by the processing pressure, it becomes possible to continuously form films when forming an insulating film stack having different bandgap with high accuracy, thereby improving process efficiency. This is extremely advantageous.
- the band gap of the silicon nitride film can be adjusted accurately and easily only by adjusting the processing pressure, it is possible to easily manufacture insulating film laminates having various band gap structures. Therefore, it is optimal as a process for manufacturing a MOS semiconductor memory device that combines excellent data retention characteristics, high-speed data rewriting performance, low power consumption operation performance, and high reliability.
- FIG. 1 is a schematic cross-sectional view showing an example of a plasma processing apparatus suitable for forming an insulating film.
- Figure 2 shows the structure of a planar antenna.
- FIG. 3 is an explanatory diagram showing the configuration of the control unit.
- FIG. 4 is a graph showing the relationship between the processing pressure and the band gap in plasma C VD using ammonia as the source gas.
- FIG. 5 is a graph showing the relationship between the processing pressure and the band gap in plasma C V D using nitrogen as the source gas.
- FIG. 6 is an explanatory diagram showing a schematic configuration of a MOS type semiconductor memory device to which the manufacturing method according to the first embodiment of the present invention is applicable.
- FIG. 7 is an energy band diagram of the MOS type semiconductor memory device shown in FIG.
- 8A to 8C are diagrams showing energy diagrams in the prior art.
- 8D to 8F are diagrams showing energy diagrams in the present invention.
- FIG. 9 is an explanatory diagram showing a schematic configuration of a MOS type semiconductor memory device to which the manufacturing method according to the second embodiment of the present invention can be applied.
- FIG. 10 is an energy band diagram of the MOS type semiconductor memory device shown in FIG.
- FIG. 11 is an explanatory diagram showing a schematic configuration of a MOS type semiconductor memory device to which the manufacturing method according to the third embodiment of the present invention can be applied.
- FIG. 12 is an example of an energy band diagram of the MOS type semiconductor memory device shown in FIG.
- Fig. 13 shows the energy of the MOS type semiconductor memory device shown in Fig. 11. —Another example of a Pand diagram.
- FIG. 14 is an energy band diagram showing a modified example of the MOS semiconductor memory device shown in FIG. BEST MODE FOR CARRYING OUT THE INVENTION
- FIG. 1 is a cross-sectional view schematically showing a schematic configuration of a plasma processing apparatus 100 that can be used as a plasma C VD apparatus in the manufacturing method of the MOS type semiconductor memory device of the present invention.
- the plasma processing apparatus 100 introduces microwaves into the processing chamber using a planar antenna with multiple slot-shaped holes, especially RLSA (Radial—Line—Slot—Antenna).
- RLSA Rotary—Line—Slot—Antenna
- the plasma processing apparatus 100 it is possible to process with plasma having a plasma density of 1 X 1 0 1 0 ⁇ ⁇ ⁇ ⁇ 1 2 / cm 3 and a low electron temperature of 0.7-2 eV It is. Therefore, the plasma processing apparatus 100 can be suitably used for the purpose of forming a silicon nitride film by the plasma CVD method in the manufacturing process of various semiconductor devices.
- the plasma processing apparatus 100 includes, as main components, an airtight chamber (processing chamber) 1, a gas supply mechanism 18 for supplying gas into the chamber 1, and a pressure reduction in the chamber 1. Exhaust mechanism for exhausting As an exhaust device 24, a microphone mouth wave introduction mechanism 2 7 that is provided in the upper part of the chamber 1 and introduces microwaves into the chamber 1, and controls each component of the plasma processing apparatus 100 And a control unit 5 0.
- the chamber 11 is formed of a substantially cylindrical container that is grounded.
- the chamber 1 may be formed of a rectangular tube-shaped container.
- the chamber 1 has a bottom wall 1a and a side wall 1b made of a material such as aluminum.
- a mounting table 2 for horizontally supporting a silicon wafer (hereinafter simply referred to as “wafer”) W as an object to be processed.
- the mounting table 2 is made of a ceramic material such as A 1 N having a high thermal conductivity.
- the mounting table 2 is supported by a cylindrical support member 3 that extends upward from the center of the bottom of the exhaust chamber 11.
- the support member 3 is made of ceramics such as A 1 N, for example.
- the mounting table 2 is provided with a covering ring 4 for covering the outer edge portion thereof and guiding the wafer W.
- the cover ring 4 is an annular member made of a material such as quartz, A 1 N, A 1 2 0 3 , Si N or the like.
- a resistance heating type heater 5 as a temperature adjusting mechanism is embedded in the mounting table 2.
- the mounting table 2 is heated by being supplied with power from the heater power source 5 a, and the wafer W as the substrate to be processed is uniformly heated by the heat. (0 0 2 9)
- the mounting table 2 is provided with a thermocouple (TC) 6.
- TC thermocouple
- the heating temperature of the wafer W can be controlled in the range from room temperature to 90, for example.
- the mounting table 2 has wafer support pins (not shown) for supporting the wafer W and moving it up and down.
- Each wafer support pin is provided so as to protrude and retract with respect to the surface of the mounting table 2.
- a circular opening 10 is formed in a substantially central portion of the bottom wall 1 a of the chamber 11.
- the bottom wall l a is provided with an exhaust chamber 11 that communicates with the opening 10 and protrudes downward.
- An exhaust pipe 1 2 is connected to the exhaust chamber 11, and is connected to the exhaust device 2 4 via the exhaust pipe 12.
- An annular gas inlet 14 is provided at the upper end of the side wall 1 b forming the chamber 1. Further, an annular gas introduction part 15 is provided on the side wall 1 b of the chamber 11. In other words, the gas introduction parts 14 and 15 are provided in two upper and lower stages. Each gas introduction part 14 and 15 is connected to a gas supply mechanism 18 that supplies a raw material gas for film formation and a gas for plasma excitation. The gas introduction parts 14 and 15 may be provided in a nozzle shape or a shower shape.
- a loading / unloading port 16 for loading / unloading the wafer “W” between the plasma processing apparatus 100 and a transfer chamber (not shown) adjacent thereto is provided on the side wall 1 b of the chamber 11.
- a gate valve 17 that opens and closes the loading / unloading port 16. (0 0 3 4)
- the gas supply mechanism 1 8 is connected to the gas inlet by providing a pipe, for example, a nitrogen-containing gas (N-containing gas) supply source 1 9 a, a silicon-containing gas (S i-containing gas) supply source 1 9 b, It has an active gas supply source 19c.
- the nitrogen-containing gas supply source 19 a is connected to the upper gas introduction section 14.
- the silicon-containing gas supply source 19 b and the inert gas supply source 19 c are connected to the lower gas introduction unit 15.
- the gas supply mechanism 18 may have, for example, a cleaning gas supply source used for cleaning the inside of the chamber 11 as a gas supply source (not shown) other than the above.
- the nitrogen-containing gas that is a raw material gas for example, a gas such as nitrogen gas (N 2 ), ammonia (NH 3), hydrazine derivatives such as MH (monomethyl hydrazine) can be used.
- a gas such as silane (S i H 4 ), disilane (S i 2 H 6 ), lysylsilane (S i 3 H 8 ), TSA (trisilylamine) Can be used. Of these, disilane (Si 2 H 6 ) is particularly preferable.
- the inert gas for example, N 2 gas or rare gas can be used as the inert gas.
- the rare gas is a plasma excitation gas for stably generating plasma.
- Ar gas, Kr gas, Xe gas, He gas, and the like can be used.
- the nitrogen-containing gas is introduced from the nitrogen-containing gas supply source 19 a of the gas supply mechanism 18 into the chamber 11 through the gas line 20 through the gas line 20.
- silicon-containing gas and inert gas are supplied from silicon-containing gas supply source 19 b and inert gas supply source 19
- the gas is introduced into the chamber 1 from the gas introduction part 15 through the gas line 20.
- the gas line 20 is provided with a mass port controller 21 and an opening / closing valve 22 before and behind it, so that the gas to be supplied can be switched and the flow rate can be controlled.
- the gas in the chamber 11 is exhausted to the outside through the exhaust pipe 12 by operating the exhaust device 24.
- the inside of the chamber 11 can be depressurized at a high speed to a predetermined degree of vacuum, for example, 0.13 3 Pa.
- the chamber 1 is provided with a pressure gauge (not shown) so that the pressure in the chamber 1 can be measured.
- the microwave introduction mechanism 27 has the following main components: a transmission plate 28, a planar antenna 31, a slow wave material 33, a cover 34, a waveguide 37, and matching A circuit 3 8 and a microwave generator 3 9 are provided.
- the planar antenna 31 is made of, for example, a copper plate or an aluminum plate whose surface is plated with gold or silver.
- the planar antenna 3 1 has a number of slot-like microphone mouth wave radiation holes 3 2 that radiate microwaves.
- the microphone mouth wave radiation hole 3 2 is formed to penetrate the planar antenna 3 1 in a predetermined pattern.
- Each microwave radiation hole 32 has an elongated rectangular shape (slot shape) as shown in FIG. 2, for example.
- adjacent microphone mouth wave radiation holes 32 are arranged in a “T” shape.
- it is arranged in combination with a predetermined shape (for example, a letter shape).
- the microphone mouth wave radiation holes 32 are further arranged concentrically as a whole.
- the length and arrangement interval of the microwave radiation holes 32 are determined according to the wavelength ( ⁇ g) of the microwave.
- the distance between the microwave radiation holes 3 2 is set to be from A g Z 4.
- the interval between adjacent microphone mouth wave radiation holes 3 2 formed concentrically is indicated by ⁇ r.
- the shape of the microwave radiation hole 32 may be other shapes such as a circular shape and an arc shape.
- the arrangement form of the microwave radiation holes 32 is not particularly limited, and the microwave radiation holes 32 can be arranged concentrically, for example, spirally, radially, or the like.
- the control unit 50 includes a computer.
- the process controller 5 1 having a CPU and a user controller connected to the process controller 51 It has an in-night face 5 2 and a storage unit 5 3.
- the process controller 51 is a component related to process conditions such as temperature, pressure, gas flow rate, and microwave output (for example, the heater power supply 5a, the gas supply mechanism 18 and the like). It is a control means that controls the exhaust system 24, the microwave generator 39, etc.).
- the user interface 5 2 is a keyboard that allows process managers to input commands to manage the plasma processing device 100, a display that visualizes and displays the operating status of the plasma processing device 100, etc. have.
- the storage unit 53 has a plasma processing device. Control program (software) and processing condition data to realize various processes executed by the device 100 under the control of the process controller 51
- an arbitrary recipe is called from the storage unit 53 by an instruction from the user interface 52, etc., and is executed by the process controller 51, so that the plasma processing is performed under the control of the process controller 51. Desired processing is performed in the chamber 1 of the apparatus 100.
- recipes such as the control program and processing condition data are stored in a computer-readable storage medium such as a CD-ROM, hard disk, flexible disk, flash memory, DVD, or Blu-ray disc. It can also be transmitted from other devices, for example via a dedicated line, and used online.
- the gate valve 17 is opened and the wafer W is loaded into the chamber 11 from the loading / unloading port 16 and mounted on the mounting table 2.
- the gas supply mechanism 18 uses the nitrogen-containing gas supply source 19a, the silicon-containing gas supply source 19b, and the inert gas supply source 19c for film formation.
- nitrogen-containing gas, silicon-containing gas and, if necessary, inert gas are introduced into the chamber 11 at a predetermined flow rate through the gas introduction portions 14 and 15 respectively. In this way, the inside of the chamber 1 is adjusted to a predetermined pressure. Note that it is preferable to introduce a rare gas in order to stably generate plasma in the chamber 11 and perform uniform film formation. (0 0 4 6)
- a microwave having a predetermined frequency for example, 2.45 GHz generated by the microwave generator 39, is transmitted from the slot-like microwave radiation hole 3 2 formed through the planar antenna 31 to the transmission plate 2. 8 is emitted to the upper space of the wafer W in the chamber 1 through 8.
- Microphone port wave output at this time for example, be a 5 0 0 ⁇ 3 0 0 0 W ( transparent plate 2 8 area 1 cm 2 per 0. 2 5 ⁇ 1. 5 4WZ cm 2) of degree
- An electromagnetic field is formed in the chamber 1 by the microwave radiated from the planar antenna 31 to the chamber 1 through the transmission plate 28, and a source gas such as a nitrogen-containing gas and a silicon-containing gas and a rare gas are plasma. Turn into Then, the dissociation of the source gas proceeds in the plasma, and S i p H q , ⁇ ? ⁇ ! ⁇ ⁇ where ⁇ means any number. The same applies hereinafter.
- a thin film of silicon nitride Si N is deposited by the reaction of active species such as
- the band gap of the silicon nitride film to be formed is set to a desired value by selecting the plasma CVD processing conditions, particularly the pressure conditions, when forming the silicon nitride film.
- the size can be controlled. This will be explained based on experimental data.
- 4 and 5 show the relationship between the band gap of the silicon nitride film and the processing pressure when the plasma C VD is performed by the plasma processing apparatus 100 and a single silicon nitride film is formed. 4, NH 3 gas as the nitrogen-containing gas, the result when using the S i 2 H 6 gas as the silicon-containing gas, Fig. 5, S i 2 as a nitrogen-containing gas N 2 gas, as the silicon-containing gas Using H ⁇ gas It is a result in the case of.
- the plasma C VD conditions are as follows. (0 0 4 9)
- Processing temperature (mounting table): 4 0 0 t:
- Microwave power 2 kW (Power density 1.0 2 WZ cm 2 ; per area of transmission plate)
- N H 3 gas flow rate 20 0 m L / m in (s c c m)
- Processing pressure 2. 7 Pa (20 mTorr) to 66.7 Pa (50000 mTorr)
- the band gap of the silicon nitride film was measured using a thin film characteristic measuring apparatus n & k -A n aly z er (trade name; manufactured by n & k Technology Co., Ltd.).
- the processing pressure is 13.3 Pa ⁇ 1 33.3
- the band gap of the silicon nitride film to be formed changes within the range of about 5. leV to 5.8 eV. That is, a silicon nitride film having a desired band gap can be easily formed by changing only the processing pressure while keeping the Si 2 H 6 flow rate constant.
- the processing pressure can be mainly controlled, and the Si 2 H 6 flow rate can be controlled as necessary.
- Si 2 H 6 flow rate is 3 mLZm in (sccm) or more 40 mL "min
- the following range is preferable, and the range of 3 mLZm in (sccm) to SO mLZm in (sccm) is more preferable.
- the NH 3 flow rate is preferably in the range of 50 mL / min (sccm) or more and lOO mL Zm in (sccm) or less, 50 mL Zm in
- a range of (sccm) to 50 O mL / min (sccm) is more preferable.
- the flow rate ratio of S i 2 H 6 gas to NH 3 gas is preferably in the range of 0.0 1 5 to 0.2, A range of 5 or more and 0.1 or less is more preferable.
- the processing pressure is within the range of 2.7 Pa to 6 6.7 Pa.
- the band gap of the silicon nitride film formed changed within the range of about 4.9 eV to 5.8 eV.
- the size of the band gap could also be changed by changing the flow rate of Si 2 H 6 gas. .
- the flow ratio (S i 2 H 6 / N 2 ) between the Si 2 H 6 gas and the N 2 gas is preferably in the range of 0.0 1 or more and 0.2 or less, and 0.0 1 or more and 0 Within the range of 1 or less is more preferable.
- a silicon nitride film having a band gap of 4.9 eV or more can be formed.
- a silicon nitride film was formed by LPC VD with the processing pressure varied in the same way, but the band gap varied between 4.9 eV and 5 eV, and 0.leV. However, it was difficult to control the band gap with LPC VD.
- the main factor that determines the size of the band gap to be formed is the processing pressure. Therefore, by using the plasma processing apparatus 100, other conditions are kept constant, and only the processing pressure is changed, whereby a silicon nitride film having a relatively large band gap and a small silicon nitride film can be easily formed. Was confirmed.
- the pressure When using a silane-based gas such as NH 3 gas as the nitrogen-containing gas and Si 2 H 6 gas as the silicon-containing gas, it is preferable to set the pressure within the range of 1 to 1 3 3 3 Pa, More preferably, it is within the range of 1 to 1 3 3 Pa.
- the flow rate ratio of NH 3 gas to the total gas flow rate is in the range of 10 to 99.99%, preferably in the range of 90 to 99.99%.
- the flow rate ratio of i 2 H 6 gas is in the range of 0.0 1 to 90%, preferably 0, 1 to 1 Within 0% range.
- the flow ratio of Si 2 H 6 gas to NH 3 gas increases the charge trap amount of the silicon nitride film, and increases the write speed and erase speed. From the viewpoint of increasing the speed and increasing the charge retention performance, it is preferably within the range of 0.015 to 0.2.
- the flow rate of rare gas is within the range of 20 to 2 00 m L / min (sccm), preferably within the range of 20 to: LOOO m L / min (sccm), and the flow rate of NH 3 gas is 2 0 to 30 OO mL / min (sccm), preferably 20 to: L 0 0 O mLZm in (sccm), Si 2 H 6 gas flow rate is 0.1 l SO mLZm in ( The flow rate ratio can be set within the range of sccm), preferably from 0.5 to: LO mLZm in (sccm).
- the treatment pressure when using a silane-based gas such as N 2 gas as the nitrogen-containing gas and Si 2 H 6 gas as the silicon-containing gas, it is preferable to set the treatment pressure within the range of 1 to 1 3 3 3 Pa. 1 to 1 3 3 Pa is more preferable.
- the flow rate ratio of N 2 gas to the total gas flow rate is within the range of 10 to 99.99%, preferably within the range of 90 to 99.99%.
- the flow rate ratio of the Si 2 H 6 gas relative to is in the range of 0.01 to 90%, preferably in the range of 0.0 :! to 10%.
- the flow ratio of Si 2 H 6 gas to N 2 gas increases the charge trap amount of the silicon nitride film, and the write speed and erase speed From the standpoint of speeding up the process and increasing the charge retention performance, it is preferably within the range of 0.01 to 0.2.
- the processing pressure When using a silane-based gas such as NH 3 gas as the nitrogen-containing gas and Si 2 H 6 gas as the silicon-containing gas, it is preferable to set the processing pressure within the range of 1 to 1 3 3 3 Pa. More preferably, it is within the range of ⁇ 1 3 3 Pa.
- the flow rate ratio of NH 3 gas to the total gas flow rate is in the range of 10 to 99.99%, preferably in the range of 90 to 99.99%.
- the flow rate ratio of i 2 H 6 gas is in the range of 0.0 0 1 to 10%, preferably in the range of 0.0 1 to 10%.
- the flow rate ratio between Si 2 H 6 gas and NH 3 gas increases the charge trap amount of the silicon nitride film, and the write speed and erase speed. From the standpoint of speeding up the process and increasing the charge retention performance, it is preferably within the range of 0.015 to 0.2.
- the range of the flow rate of rare gas is 2 0 ⁇ 2 0 0 0 m L / in (sccm), preferably from the flow rate of NH 3 gas 2 0 0 ⁇ 1 0 OO mLZm in (sccm) 2 S i 2 H 6 gas flow in the range of 0 to 1 00 0 mLZm in (sccm), preferably in the range of 2 00 to 80 0 mLZm in (sccm)
- the amount can be set within the range of 0.5 to 50 mL Zm in (sccm), preferably within the range of 0.5 to: LO mLZm in (sccm) so that the flow rate ratio is as described above. .
- the treatment pressure when using a silane-based gas such as N 2 gas as the nitrogen-containing gas and Sia H 6 gas as the silicon-containing gas, it is preferable to set the treatment pressure within the range of 1 to 1 3 3 3 Pa. 1 to 1 3 3 Pa is more preferable.
- the flow rate ratio of N 2 gas to the total gas flow rate is within the range of 10 to 99.99%, preferably within the range of 90 to 99.99%, with respect to the total gas flow rate.
- the flow rate ratio of S 2 to 6 gas is in the range of 0.1 to 90%, preferably in the range of 0.1 to 10%.
- the flow rate ratio between Si 2 H 6 gas and N 2 gas increases the charge trap amount of the silicon nitride film, writing speed and erase From the viewpoint of increasing the speed and increasing the charge retention performance, it is preferable to be within the range of 0.01 to 0.2.
- the range of the flow rate of rare gas is 2 0 ⁇ 3 0 0 0 mL / ln (sccm), preferably in the range of 2 0 0 ⁇ 1 0 0 0 mL Zm in (sccm), the N 2 gas flow rate Within the range of 2 0 to 3 0 0 0 mL / min (sccm), preferably within the range of 2 0 0 to 2 0 0 0 mL / in (sccm), the flow rate of Si 2 H 6 gas is 0.5
- the flow rate ratio can be set within the range of ⁇ 50 mL / min (sccm), preferably within the range of 0.5 to l O mL / min (sccm).
- the plasma C VD treatment temperature is preferably set to a temperature of 300 ° C. or higher, preferably from 400 to 600 ° C. (0 0 6 5)
- silicon nitride films having different band gaps can be deposited alternately.
- the band gap can be easily and accurately controlled only by the processing pressure, continuous film formation becomes possible when forming a silicon nitride film stack having different band gaps. It is extremely advantageous to improve the ratio.
- the band gap of the silicon nitride film can be adjusted accurately and easily only by adjusting the processing pressure, it is possible to easily manufacture insulating film laminates having various band gap structures. Therefore, it can be preferably applied to a process for manufacturing a MOS type semiconductor memory device that combines excellent data retention characteristics, high-speed data rewriting performance, low power consumption operation performance, and high reliability at the same time. It is.
- FIG. 6 is a cross-sectional view showing a schematic configuration of a MOS semiconductor memory device 61 to which the manufacturing method of the MOS semiconductor memory device according to the first embodiment of the present invention can be applied.
- FIG. 7 is an example of an energy panda diagram of the MOS semiconductor memory device 6 0 1 in FIG.
- the MOS type semiconductor memory device 60 1 includes a p-type silicon substrate 10 0 1 as a semiconductor layer and a band gap formed on the p-type silicon substrate 10 1.
- Insulating film laminate 10 0 a composed of a plurality of insulating films of different sizes, and this insulating film laminate 10 2 a having a gate electrode 10 3 formed on 2 a.
- the first insulating film 1 1 1, the second insulating film 1 1 2, the third insulating film 1 1 3, and the fourth insulating film Insulating film 1 1 4 and insulating film laminate 1 0 2 a having fifth insulating film 1 1 5 are provided.
- the silicon substrate 10 0 1 includes a first source / drain 10 4 and a second source / drain that are n-type diffusion layers at a predetermined depth from the surface so as to be located on both sides of the gate electrode 10 3.
- a drain 1 0 5 is formed, and a channel forming region 1 0 6 is formed between the two.
- the MOS type semiconductor memory device 61 may be formed on a P-well or P-type silicon layer formed in the semiconductor substrate. Although this embodiment will be described by taking an n-channel MOS device as an example, it may be implemented using a P-channel MOS device. Therefore, the contents of the present embodiment described below can be applied to all n-channel MOS devices and P-channel MOS devices. Further, although not shown, the source / drain 10 4 and 10 5 are provided with a source Z drain electrode as is well known, and the electric potential of these regions can be controlled from the outside.
- the first insulating film 11 1 1 is, for example, a silicon dioxide film (Si 0 2 film) formed by oxidizing the surface of the silicon substrate 110 1 by a thermal oxidation method.
- the first insulating film 1 1 1 has the largest energy band gap in the range of 8 to 10 eV, for example.
- the film thickness of the first insulating film 1 1 1 is, for example, 0.5 ⁇ !
- the range of ⁇ 20 nm is preferred, I nm ⁇ : the range of LO nm is more preferred, and the range of lnm-3 nm is desirable.
- the second insulating film 1 1 2 is formed on the surface of the first insulating film 1 1 1 Silicon nitride film (SiN film; where the composition ratio of Si and N is not necessarily determined stoichiometrically, but takes different values depending on the deposition conditions. The same applies hereinafter) .
- the second insulating film 112 has an energy panda gap within a range of 5 to 7 eV, for example.
- the film thickness of the second insulating film 1 1 2 is preferably in the range of 2 nm to 20 nm, for example.
- ⁇ More preferably in the range of 2 nm to 1 nm, and more preferably in the range of 3 nm to 5 nm.
- the third insulating film 1 13 is a silicon nitride film formed on the second insulating film 1 12.
- This third insulating film 11 13 has an energy band gap in the range of 2.5 to 4 eV, for example.
- the film thickness of the third insulating film 1 1 3 is, for example, preferably in the range of 2 nm to 30 nm, more preferably in the range of 2 nm to 15 nm, and in the range of 4 nm to 10 nm. Is desirable.
- the fourth insulating film 1 14 is a silicon nitride film (SiN film) formed on the third insulating film 1 13. This fourth insulating film 1 14 has the same energy gap and film thickness as the second insulating film 1 1 2.
- the fifth insulating film 1 1 5 is a silicon dioxide film (S) deposited on the fourth insulating film 1 1 4 by, for example, the C VD (Chemica 1 -V apor-Deposition) method. io 2 membrane).
- the fifth insulating film 1 15 functions as a block layer (a rear layer) between the electrode 10 3 and the fourth insulating film 1 14.
- the fifth insulating film 1 15 has an energy band gap in the range of 8 to 10 eV, for example.
- the thickness of the fifth insulating film 1 1 5 is 2 nm, for example. It is preferably in the range of ⁇ 30 nm, more preferably in the range of 2 nm to l 5 nm, and preferably in the range of 5 nm to 8 nm.
- the gate electrode 103 is made of, for example, a polycrystalline silicon film formed by the CVD method, and functions as a control gate (CG) electrode.
- the gate electrode 103 may be a film containing a metal such as W, Ti, Ta, Cu, A1, Au, Pt.
- the gate electrode 10 3 is not limited to a single layer, but for the purpose of reducing the specific resistance of the gate electrode 10 3 and increasing the speed, for example, tungsten, molybdenum, tantalum, titanium, platinum, their silicides, nitrides, alloys It is also possible to make a laminated structure including the like.
- the gate electrode 103 is connected to a wiring layer (not shown).
- the first insulating film 1 1 1 and the fifth insulating film 1 1 5 are made of a silicon nitride oxide film (S i ON film) or silicon dioxide. Rukoto using membrane (S i 0 2 film) is preferable.
- the material of the second insulating film 1 1 2, the third insulating film 1 1 3, and the fourth insulating film 1 1 4 is silicon nitride.
- the MOS type semiconductor memory device 60 1 includes a first gap between the first insulating film 1 1 1 and a fifth insulating film 1 1 5, 1 1 1 a and 1 1 5 a.
- Gap 1 1 2 A second insulating film 1 1 2 having a and 1 1 4 a and a fourth insulating film 1 1 4 are interposed.
- reference numeral 10 1 a is a band gap of the silicon substrate 10 1
- reference numeral 1 0 3 a is a band gap of the gate electrode 1 0 3 a.
- the MOS type semiconductor memory device 61 having the above structure will be described.
- the first source Z drain 10 4 and the second source Z drain 1 0 5 are held at 0 V with reference to the potential of the silicon substrate 10 1, and the gate electrode 3 has a predetermined value. Apply a positive voltage.
- electrons are accumulated in the channel formation region 106 to form an inversion layer, and a part of the charge in the inversion layer is caused to pass through the first insulating film 1 1 1 due to the tunnel phenomenon.
- 1 0 2 Move to a. Electrons that have moved to the insulating film stack 1 0 2 a Data is stored by being captured by the formed charge trapping centers.
- a voltage of 0 V is applied to either the first source / drain 10 04 or the second source Z drain 1 0 5 with the potential of the silicon substrate 10 1 as a reference, and the other is predetermined. Apply a voltage of. Further, a predetermined voltage is also applied to the gate electrode 103. By applying the voltage in this way, the channel current amount and the drain voltage change depending on the presence or absence of the charge accumulated in the insulating film laminate 10 2 a and the amount of the accumulated charge. Therefore, the data can be read out by detecting the change in the channel current or the drain voltage.
- a voltage of 0 V is applied to both the first source / drain 10 4 and the second source / drain 1 0 5 with reference to the potential of the silicon substrate 10 1, and the gate electrode 1 0 Apply a negative voltage to 3 in the specified magnitude.
- the electric charge held in the insulating film laminated body 10 2 a is extracted to the channel formation region 10 6 of the silicon substrate 1 0 1 through the first insulating film 1 1 1. .
- the MOS semiconductor memory device 60 1 returns to the erased state in which the amount of accumulated electrons in the insulating film stack 10 02 a is low.
- the method of writing, reading, and erasing information in the MOS semiconductor memory device 61 is not limited, and writing, reading, and erasing may be performed by a method different from the above.
- information can be written, read and erased using physical phenomena such as FN tunneling, hot-electron injection, hot-hole injection, and photoelectric effects.
- the first source / drain 1 0 4 and the second source drain 1 0 5 are not fixed, but can function alternately as a source or drain so that one memory cell can write and read information of 2 bits or more. Also good.
- the MOS type semiconductor memory device 6 0 1 has improved retention characteristics, increased write operation speed, reduced power consumption and reliability compared to the conventional M0S type semiconductor memory device. This is an excellent MOS semiconductor memory device that has been improved at the same time.
- FIGS. 8A to 8C schematically show energy diagrams in writing, erasing, and data holding states of a conventional MOS semiconductor memory device.
- 8D to 8F schematically show energy diagrams in writing, erasing, and data holding states of the MOS type semiconductor memory device of the present invention.
- the MOS type semiconductor memory device 60 charges are held in a certain distribution between the first insulating film and the fifth insulating film, but mainly in the third insulating film or the third insulating film. Since the region centered around the interface is the portion that plays the role of charge accumulation, this portion is expressed as the “charge accumulation region” in FIGS. 8A to 8F for convenience of explanation.
- the probability that electrons move between the silicon substrate and the charge storage region is inversely proportional to the size of the energy barrier EB (that is, the height H and width T of the energy barrier EB).
- the band gap of the first insulating film increases, so that the movement of electrons between the silicon substrate side and the charge storage layer side is limited.
- the thickness of the insulating film 1 is increased, the width T is increased, so that the energy barrier EB is also increased.
- increasing the film thickness of the first insulating film is effective in preventing electrons held on the charge storage region side from leaking out to the silicon substrate side through the first insulating film. It is a simple method. Therefore, in order to improve the charge retention capability in the MOS type semiconductor memory device, the band gap of the first insulating film is increased and the film thickness is increased, as shown in FIG. Energy barrier by insulating film EB height H and width T should be increased.
- the thickness of the first insulating film is increased, for example, electrons are less likely to be injected from the silicon substrate into the charge storage region due to the tunnel effect during writing, as shown in FIG. 8A.
- a large write voltage must be applied during writing.
- a large erasing voltage is required during erasing.
- the band gap of the first insulating film should be reduced and the film thickness should be reduced. However, this reduces the energy barrier EB, which reduces the data retention characteristics. Resulting in.
- the first insulating film and the fifth insulating film having a large band gap are adjacent to each other and the band gap is smaller than these.
- Second and fourth insulating films having the followings were provided.
- the energy barrier when electrons pass from the charge storage region side to the silicon substrate side ⁇ ⁇ width can be 1, and the movement of electrons is smooth even with a low erasing voltage. Is done.
- FIG. 8F not only the first insulating film (fifth insulating film) but also the second insulating film (fourth insulating film) in the state where electrons are held in the charge storage region.
- the energy barrier (including the film) becomes ⁇ ⁇ , the width ⁇ increases, and even if the thickness of the first insulating film (fifth insulating film) is not increased, charge can escape from the charge storage region. Therefore, excellent charge retention characteristics can be obtained.
- the device isolation film (not shown) is formed by techniques such as the LOCOS (Local — O xidation— of — S i 1 icon) method and the STI (S ha 1 low— Trenench— I so 1 ation) method.
- LOCOS Local — O xidation— of — S i 1 icon
- STI shallow-trenench— I so 1 ation
- the second insulating film 1 1 2, the third insulating film 1 1 3, and the fourth insulating film are formed on the first insulating film 1 1 1 by a plasma C VD method using a plasma processing apparatus 1 100. Insulating films 1 1 4 are formed sequentially.
- plasma C VD is performed under the condition that the band gap is smaller than that of the first insulating film 1 1 1.
- 3rd recording film 1 1 3 When forming, plasma CVD is performed under the condition that the band gap is smaller than that of the second insulating film 1 1 2.
- the fourth insulating film 1 14 the plasma C VD is performed under the condition that the band gap is larger than that of the third insulating film 1 1 3.
- the insulating film is formed under the same plasma C VD conditions so that the second insulating film 1 1 2 and the fourth insulating film 1 1 4 have the same span gap.
- the band gaps 1 1 2 a and 1 14 a of the second insulating film 1 1 2 and the fourth insulating film 1 1 4 may be the same or different.
- the size of the band gap of each film can be controlled by changing only the pressure condition of the plasma CVD treatment.
- a fifth insulating film 1 15 is formed on the fourth insulating film 1 1 4 so that the band gap is larger than that of the fourth insulating film 1 1 4.
- the fifth insulating film 115 can be formed by, for example, the CVD method. Further, a polysilicon film, a metal layer, a metal silicide layer, or the like is formed on the fifth insulating film 115 by, for example, the C V D method to form a metal film that becomes the gate electrode 103.
- FIG. 10 is an energy band diagram of the MOS semiconductor memory device 60 2 in FIG.
- the MOS type semiconductor memory device 60 2 is formed by stacking on a p-type silicon substrate 10 1 as a semiconductor layer and this p-type silicon substrate 10 1.
- An insulating film laminate 10 0 2 b composed of a plurality of insulating films having different bandgap sizes, and a gate electrode 1 0 3 formed on the insulating film laminate 1 0 2 b .
- the first insulating film 1 2 1, the second insulating film 1 2 2, the third insulating film 1 2 3, and the fourth insulating film Insulating film 1 2 4 and fifth insulating film 1 2 5 are provided.
- the silicon substrate 10 1 includes a first source / drain 10 4 and a second source / drain made of an n-type diffusion layer at a predetermined depth from the surface so as to be located on both sides of the gate electrode 10 3. 1 0 5 is formed, and a channel forming region 1 0 6 is formed between the two.
- the MO S type semiconductor memory device 60 2 may be formed in a p-type silicon layer formed in a semiconductor substrate. Although this embodiment will be described by taking an n-channel MOS device as an example, it may be implemented with a P-channel MOS device. Therefore, the contents of this embodiment described below are all n-channel MOS devices. It can be applied to p-channel mos devices. (0 0 9 3)
- the first insulating film 1 2 1, the fifth insulating film 1 2 5 and the gate electrode 1 0 3 are the MOS type semiconductor shown in FIG. Since the first insulating film 1 11, the fifth insulating film 1 15, and the gate electrode 10 3 of the memory device 60 1 have the same configuration, the description thereof is omitted.
- the second insulating film 1 2 2 is a silicon nitride film (SiN film) formed on the first insulating film 1 2 1.
- the second insulating film 1 2 2 has an energy band gap in the range of 2.54 eV, for example.
- the film thickness of the second insulating film 1 2 2 is preferably, for example, in the range of 2 nm 20 nm, more preferably in the range of 2 nm 10 nm, and preferably in the range of 3 nm 5 nm.
- the third insulating film 1 23 is a silicon nitride film (SiN film) formed on the second insulating film 1 2 2.
- the third insulating film 1 2 3 has an energy-band gap in a range of 5 7 eV, for example.
- the thickness of the third insulating film 1 23 is preferably in the range of 2 nm 30 ⁇ m, more preferably in the range of 2 nm 15 nm, and preferably in the range of 4 nm to 10 nm.
- the fourth insulating film 1 24 is a silicon nitride film (SiN film) formed on the third insulating film 1 23.
- the fourth insulating film 1 24 has the same energy band gap and film thickness as the second insulating film 1 2 2.
- the MOS type semiconductor memory device 60 2 includes the first and second insulating films 1 2 1 and 1 2 5, and 1 2 1 a and 1 2 5 a force. Band gaps of the second insulating film 1 2 2, the third insulating film 1 2 3, and the fourth insulating film 1 2 4 that are intermediate laminates interposed between the two 1 2 2 a, 1 2 3 a, and 1 Compared to 2 4 a, it has a larger energy band structure. Further, adjacent to the first insulating film 1 2 1 and the fifth insulating film 1 2 5, the second insulating film 1 2 2 and the second insulating film having the smallest band gaps 1 2 2 a and 1 2 4 a are provided.
- insulating films 1 2 are arranged. Between the second insulating film 1 2 2 and the fourth insulating film 1 2 4, the band gaps 1 2 1 a and 1 2 5 a are smaller than the band gaps 1 2 2 a, 1 2 4 a A third insulating film 1 2 3 having a larger intermediate band gap 1 2 3 a is provided. In other words, the first insulating film 1 2 1 and the fifth insulating film 1 2 5 having the largest band gap 1 2 la and 1 2 5 a and the first insulating film having the middle band gap 1 2 3 a Between the third insulating film 1 2 3, a second insulating film 1 2 2 and a fourth insulating film 1 2 4 having the smallest band gap are interposed.
- the charge is mainly near the interface between the third insulating film 1 2 3 and the second insulating film 1 2 2 and the fourth insulating film 1 2 4 having a small band gap. Is easy to accumulate.
- the second insulating film 1 2 2 and The presence of the fourth insulating film 1 24 increases the energy barrier and prevents the electric charge from being extracted through the first insulating film 1 2 1 or the fifth insulating film 1 2 5. Therefore, it is possible to stably hold charges in the insulating film stack 10 2 b without increasing the thickness of the first insulating film 1 21 and the fifth insulating film 1 2. Yes, excellent data retention characteristics can be obtained.
- the MOS type semiconductor memory device 60 2 has improved data retention characteristics, higher write operation speed, lower power consumption, and higher reliability than the conventional MOS type semiconductor memory device. It is an excellent MOS type semiconductor memory device realized at the same time.
- the writing, reading and erasing operations of the MOS type semiconductor memory device 62 according to the present embodiment can be performed in the same manner as in the first embodiment.
- the MOS type semiconductor memory device 60 2 can be manufactured in the same manner as in the first embodiment, except that the formation of the insulating film stacked body 10 2 b is performed according to the following procedure.
- the second insulating film 1 2 2, the third insulating film 1 2 3, and the fourth insulating film 1 2 4 that mainly play a central role as a charge storage region are connected to the plasma processing apparatus.
- Film formation is performed using plasma CVD method using 100. That is, a plasma processing apparatus 100 is used on the first insulating film 1 2 1, and the second insulating film 1 2 2, the third insulating film 1 2 3, and the first 4 insulating films 1 2 4 are formed sequentially.
- the second insulating film 1 2 When forming the second insulating film 1 2 2, plasma CVD is performed under the condition that the bandgap is smaller than that of the first insulating film.
- the third insulating film 1 2 3 Plasma C VD is performed under conditions where the bandgap is larger than 2 and the bandgap is smaller than that of the first insulating film 1 2 1.
- plasma CVD is performed under the condition that the band gap is smaller than that of the third insulating film 1 2 3.
- the insulating film is formed under the same plasma CVD conditions so that the second insulating film 1 2 2 and the fourth insulating film 1 2 4 have the same band gap size. .
- the band gaps 1 2 2 a and 1 2 4 a of the second insulating film 1 2 2 and the fourth insulating film 1 2 4 may be the same or different.
- the size of the band gap can be controlled by changing only the pressure condition of the plasma C VD treatment.
- FIG. 12 shows an example of an energy band diagram of the MOS type semiconductor memory device 60 3 of FIG. 11.
- FIG. 13 shows another example.
- the MOS type semiconductor memory device 60 3 is formed by stacking a p-type silicon substrate 10 0 1 as a semiconductor layer and the p-type silicon substrate 1 0 1.
- An insulating film stack 10 0 2 c composed of a plurality of insulating films having different bandgap sizes, and a gate electrode 1 0 3 formed on the insulating film stack 1 0 2 c Yes.
- an insulating film stacked body 10 2 c is provided, and this insulating film stacked body 1 0 2 c is a first insulating layer.
- the three-layered laminate of the second insulating film 1 3 2, the third insulating film 1 3 3 and the fourth insulating film 1 3 4 is a unit. Three units are laminated repeatedly through one insulating film 1 3 6.
- the silicon substrate 1001 includes a first source drain 104 and a second drain made of an n-type diffusion layer at a predetermined depth from the surface so as to be located on both sides of the gate electrode 103.
- Source / drain 10 5 is formed, and a channel forming region 10 6 is formed between the two.
- this embodiment will be described by taking an n-channel MSS device as an example, it may be implemented with a ⁇ channel] iOS device. Therefore, the contents of the present embodiment described below can be applied to all n-channel MOS devices and P-channel MOS devices.
- the first insulating film 1 31, the fifth insulating film 1 3 5, and the gate electrode 10 3 have the MOS type shown in FIG. Since the configuration is the same as that of the first insulating film 111, the fifth insulating film 115, and the gate electrode 103 of the semiconductor memory device 61, description thereof is omitted.
- the second insulating film 1 3 2 is a silicon nitride film (SiN film) formed on the first insulating film 1 3 1.
- the second insulating film 1 3 2 has an energy band gap in the range of 2.5 to 4 eV, for example.
- the film thickness of the second recording film 1 3 2 is preferably in the range of 2 nm to 20 nm, for example, and more preferably in the range of 3 nm to 5 nm. (0 1 0 7)
- the third insulating film 1 3 3 is a silicon nitride film (SiN film) formed on the second insulating film 1 3 2.
- This third insulating film 1 3 3 has an energy band gap in the range of 5 to 7 eV, for example.
- the film thickness of the third insulating film 1 33 is preferably in the range of 2 nm to 3 O nm, for example, and more preferably in the range of 4 nm to L O nm.
- the fourth insulating film 1 3 4 is a silicon nitride film (SiN film) formed on the third insulating film 1 3 3.
- the fourth insulating film 13 4 has the same energy band gap and film thickness as the second insulating film 13 2.
- Spacer insulating film 1 3 6 is a silicon nitride film (SiN film) formed on fourth insulating film 1 3 4.
- SiN film silicon nitride film
- the spacer one insulating film 1 3 6 a film similar to the third insulating film 1 3 3 can be used. That is, the spacer-insulating film 1 3 6 has an energy band gap in the range of 5 to 7 eV, for example.
- the thickness of the spacer insulating film 6 is preferably in the range of 2 nm to 30 nm, for example, and more preferably in the range of 4 nm ′ to 1 Onm.
- the MOS type semiconductor memory device 6 0 3 includes the band gaps 1 3 1 a and 1 3 5 of the first insulating film 1 3 1 and the fifth insulating film 1 3 5.
- Third insulation film 1 3 3 and spacer 1 insulation film 1 3 6 The band gaps 1 3 3 a and 1 3 6 a of the first insulating film 1 3 1 and the fifth insulating film 1 3 5 are smaller than the pand gaps 1 3 1 a and 1 3 5 a, and the second The first and second insulating films 1 3 2 and 1 3 4 have a larger gap than 1 3 2 a and 1 3 4 a.
- the second insulating film 1 3 2 and the fourth insulating film 1 3 4 having the smallest band gap are interposed at the positions in contact with the first insulating film 1 3 1 and the fifth insulating film 1 3 5. I am letting.
- the insulating film stack 10 0 2 c mainly near the interface between the third insulating film 1 3 3 and the second insulating film 1 3 2 and the fourth insulating film 1 3 4 having a small band gap. Charges are likely to accumulate. In addition, once the charge is held in the region centered around the interface of the third insulating film 1 3 3, the energy of the second insulating film 1 3 2 and the fourth insulating film 1 3 4 The barrier is increased, and it is possible to prevent electric charges from being released through the first insulating film 1 3 1 or the fifth insulating film 1 3 5. Therefore, it is possible to stably hold charges in the insulating film stack 10 2 c without increasing the thickness of the first insulating film 1 31 and the fifth insulating film 1 3 5. Excellent data retention characteristics can be obtained.
- the MOS type semiconductor memory device has a higher data retention characteristic, higher write operation speed, lower power consumption, and higher reliability than the conventional MOS type semiconductor memory device. These are excellent semiconductor memory devices realized at the same time. (0 1 1 3)
- the MOS type semiconductor memory device 60 3 can be manufactured in the same manner as in the first embodiment, except that the formation of the insulating film stacked body 102 c is performed according to the following procedure.
- the second insulating film 1 3 2, the third insulating film 1 3 3, the fourth insulating film 1 3 4, and the spacer insulating film that mainly play a central role as the charge storage region 1 3 6 is formed using a plasma C VD method using a plasma processing apparatus 100.
- the second insulating film 1 3 2, the third insulating film 1 3 3, and the first insulating film 1 3 1 are formed by a plasma C VD method using a plasma processing apparatus 100.
- 4 insulating films 1 3 4 are formed sequentially.
- plasma CVD is performed under the condition that the band gap is smaller than that of the first insulating film 1 3 1.
- plasma is used under the condition that the bandgap is smaller than that of the first insulating film 1 3 1 and that the bandgap is larger than that of the second insulating film 1 3 2.
- C Perform VD.
- plasma C VD is performed under the condition that the band gap is smaller than that of the third insulating film 1 3 3.
- the plasma is obtained under the condition that the band gap is smaller than that of the first insulating film 1 3 1 and the band gap is larger than that of the fourth insulating film 1 3 4.
- C Perform VD. Note that in this embodiment, the band gap between the second insulating film 1 3 2 and the fourth insulating film 1 3 4 and the third insulating film 1 3 3 and the spacer insulating film 1 3 6 is large.
- the insulating film is formed under the same plasma CVD conditions so that the lengths are the same. However, the sizes of the band gaps 1 3 2 a and 1 3 4 a, or the band gaps 1 3 3 a and the band gaps 1 3 6 a may be the same or different.
- the size of the band gap can be changed by changing only the pressure condition of the plasma C VD process. Can be controlled.
- the second insulating film 1 3 2, the third insulating film 1 3 3 and the fourth insulating film 1 3 4 formed in this way are regarded as one unit, and the spacer insulating film 1 3 is interposed therebetween. By repeatedly laminating with 6 interposed therebetween, the insulating film laminated body 10 2 c can be formed.
- a stacked body of the second insulating film 1 3 2, the third insulating film 1 3 3 and the fourth insulating film 1 3 4 is 1 Although 3 units were repeatedly laminated as a unit, the number of repetitions may be 2 units or 4 units or more.
- the stacked body of the second insulating film 1 3 2, the third insulating film 1 3 3 and the fourth insulating film 1 3 4 is interposed via the spacer insulating film 1 3 6.
- the spacer insulating film 1 3 6 need not be provided.
- the second insulating film 1 3 2, the third insulating film 1 3 3, the fourth insulating film 1 3 4, and the spacer insulating film The magnitude of the band gap may be reversed by reversing the pressure at the time of forming the film 1 3 6.
- An example of the energy-band structure in that case is shown in Fig. 13.
- the write, read and erase operations of the MOS type semiconductor memory device 63 according to the present embodiment can be performed in the same manner as in the first embodiment.
- the silicon nitride film formed at each processing pressure stage or each gas flow stage has the same thickness.
- FIG. 14 shows an example in which the processing pressure is changed so that the bandgap 1 1 3 a gradually increases in the process of forming the third insulating film 1 1 3. Contrary to FIG. 14, in the process of forming the third insulating film 1 1 3, the band gap 1 1 3 a can be gradually reduced.
- an n-channel type MOS type semiconductor memory device is taken as an example.
- the impurity conductivity type may be reversed. . (0 1 1 9)
- the band gap of the silicon nitride film is changed by changing the processing pressure of the plasma CVD process.
- the method of the present invention is an MO having a laminated body of silicon nitride films as an insulating film. Not only when manufacturing S-type semiconductor memory devices, but also when manufacturing MO S-type semiconductor memory devices having insulating film stacks such as metal oxide films, especially high-k metal oxide films, etc. Is possible.
- a high dielectric constant metal oxide for example, H f 0 2
Abstract
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CN2009801111719A CN101981690A (zh) | 2008-03-31 | 2009-03-30 | Mos型半导体存储装置的制造方法和等离子体cvd装置 |
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US9064694B2 (en) * | 2012-07-12 | 2015-06-23 | Tokyo Electron Limited | Nitridation of atomic layer deposited high-k dielectrics using trisilylamine |
JP6875188B2 (ja) * | 2017-04-25 | 2021-05-19 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
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- 2009-03-30 CN CN2009801111719A patent/CN101981690A/zh active Pending
- 2009-03-31 TW TW098110761A patent/TWI524478B/zh active
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TWI745890B (zh) * | 2020-01-21 | 2021-11-11 | 大陸商長江存儲科技有限責任公司 | 三維記憶體元件的互連結構 |
US11342355B2 (en) | 2020-01-21 | 2022-05-24 | Yangtze Memory Technologies Co., Ltd. | Interconnect structures of three-dimensional memory devices |
US11574925B2 (en) | 2020-01-21 | 2023-02-07 | Yangtze Memory Technologies Co., Ltd. | Interconnect structures of three-dimensional memory devices |
US11903204B2 (en) | 2020-01-21 | 2024-02-13 | Yangtze Memory Technologies Co., Ltd. | Interconnect structures of three-dimensional memory devices |
Also Published As
Publication number | Publication date |
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CN101981690A (zh) | 2011-02-23 |
KR101153310B1 (ko) | 2012-06-08 |
US20110086485A1 (en) | 2011-04-14 |
US8124484B2 (en) | 2012-02-28 |
TWI524478B (zh) | 2016-03-01 |
JP2009246211A (ja) | 2009-10-22 |
TW201003855A (en) | 2010-01-16 |
KR20100123889A (ko) | 2010-11-25 |
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